├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── config ├── Makefrag └── PrivateConfigs.scala ├── software ├── README.md ├── build.sh ├── jtr │ ├── .gitignore │ ├── bench.sh │ ├── buildroot-config │ ├── buildroot-external │ │ ├── Config.in │ │ ├── external.desc │ │ ├── external.mk │ │ └── package │ │ │ └── john │ │ │ ├── Config.in │ │ │ └── john.mk │ ├── crack.sh │ └── overlay │ │ ├── etc │ │ └── init.d │ │ │ └── S50apache │ │ └── root │ │ └── sha3 │ │ ├── long.txt │ │ └── short.txt ├── marshal-configs │ ├── sha3-bare-rocc.yaml │ ├── sha3-bare-sw.yaml │ ├── sha3-linux-jtr-crack.yaml │ ├── sha3-linux-jtr-test.yaml │ ├── sha3-linux-jtr.yaml │ ├── sha3-linux-test.yaml │ └── sha3-linux.yaml ├── test-reference │ ├── bare-rocc │ │ └── sha3-bare-rocc │ │ │ └── uartlog │ ├── bare-sw │ │ └── sha3-bare-sw │ │ │ └── uartlog │ ├── linux-jtr │ │ └── sha3-linux-jtr-test │ │ │ └── uartlog │ └── linux │ │ └── sha3-linux-test │ │ └── uartlog ├── test_local.sh └── tests │ ├── .gitignore │ ├── bare │ ├── Makefile │ ├── crt.S │ ├── link.ld │ ├── mmio.h │ ├── syscalls.c │ └── util.h │ ├── common.mk │ ├── linux │ └── Makefile │ └── src │ ├── compiler.h │ ├── encoding.h │ ├── rocc.h │ ├── sha3-rocc.c │ ├── sha3-sw.c │ └── sha3.h └── src └── main ├── resources └── vsrc │ └── Sha3BlackBox.v └── scala ├── chi.scala ├── common.scala ├── constants.scala ├── ctrl.scala ├── dmem.scala ├── dpath.scala ├── iota.scala ├── rhopi.scala ├── sha3.scala └── theta.scala /.gitignore: -------------------------------------------------------------------------------- 1 | .*.swp 2 | target/ 3 | *.doit* 4 | *.rv 5 | *.riscv 6 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "isa-sim/riscv-isa-sim"] 2 | path = isa-sim/riscv-isa-sim 3 | url = https://github.com/riscv/riscv-isa-sim.git 4 | [submodule "software/linux"] 5 | path = software/linux 6 | url = https://github.com/firesim/linux.git 7 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012-2014, The Regents of the University of California 2 | (Regents). All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SHA3 RoCC Accelerator 2 | 3 | This is an accelerator that implements the Secure Hash Algorithm 3. 4 | It is mainly meant to be used in the 5 | [Chipyard development environment](https://github.com/ucb-bar/chipyard) 6 | but can be ported to other environments (i.e. plain 7 | [Rocket Chip](https://github.com/chipsalliance/rocket-chip)). 8 | For more information on how the accelerator works, please refer to the 9 | [SHA3 documentation in Chipyard](https://chipyard.readthedocs.io/en/latest/Generators/SHA3.html). 10 | 11 | # Software Workloads 12 | 13 | See [software/README.md](software/README.md) for more information on building software tests for this 14 | accelerator. 15 | 16 | # References 17 | 18 | https://people.eecs.berkeley.edu/~kubitron/courses/cs262a-F13/projects/reports/project11_report.pdf 19 | -------------------------------------------------------------------------------- /config/Makefrag: -------------------------------------------------------------------------------- 1 | # check RISCV environment variable 2 | ifndef RISCV 3 | $(error Please set environment variable RISCV. Please take a look at README) 4 | endif 5 | 6 | MODEL ?= Top 7 | PROJECT := rocketchip 8 | 9 | #this defines a list of addons to build and is set as an env var 10 | export ROCKETCHIP_ADDONS ?= sha3 11 | 12 | CXX ?= g++ 13 | CXXFLAGS := -O1 14 | 15 | SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar 16 | SHELL := /bin/bash 17 | 18 | CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) 19 | 20 | src_path = src/main/scala 21 | default_submodules = . junctions uncore hardfloat rocket zscale groundtest context-dependent-environments 22 | chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules) $(ROCKETCHIP_ADDONS))) 23 | 24 | disasm := 2> 25 | which_disasm := $(shell which spike-dasm 2> /dev/null) 26 | ifneq ($(which_disasm),) 27 | disasm := 3>&1 1>&2 2>&3 | $(which_disasm) $(DISASM_EXTENSION) > 28 | endif 29 | 30 | timeout_cycles = 100000000 31 | 32 | #-------------------------------------------------------------------- 33 | # DRAMSim2 34 | #-------------------------------------------------------------------- 35 | 36 | DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard $(base_dir)/dramsim2/*.cpp)) 37 | $(DRAMSIM_OBJS): %.o: %.cpp 38 | $(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $< 39 | $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS) 40 | ar rcs $@ $^ 41 | 42 | #-------------------------------------------------------------------- 43 | # Build Tests 44 | #-------------------------------------------------------------------- 45 | 46 | %.hex: 47 | $(MAKE) -C $(dir $@) $(notdir $@) 48 | 49 | %.riscv.hex: %.riscv 50 | $(MAKE) -C $(dir $@) $(notdir $@) 51 | 52 | #--------------------------------------------------------------------- 53 | # Constants Header Files 54 | #--------------------------------------------------------------------- 55 | 56 | params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm 57 | consts_header = $(generated_dir)/consts.$(CONFIG).h 58 | scr_header = $(generated_dir)/$(MODEL).$(CONFIG).scr_map.h 59 | $(consts_header): $(params_file) 60 | echo "#ifndef __CONST_H__" > $@ 61 | echo "#define __CONST_H__" >> $@ 62 | sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@ 63 | echo "#define TBFRAG \"$(MODEL).$(CONFIG).tb.cpp\"" >> $@ 64 | echo "#endif // __CONST_H__" >> $@ 65 | 66 | params_file_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).prm 67 | consts_header_debug = $(generated_dir_debug)/consts.$(CONFIG).h 68 | $(consts_header_debug): $(params_file_debug) 69 | echo "#ifndef __CONST_H__" > $@ 70 | echo "#define __CONST_H__" >> $@ 71 | sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@ 72 | echo "#define TBFRAG \"$(MODEL).$(CONFIG).tb.cpp\"" >> $@ 73 | echo "#endif // __CONST_H__" >> $@ 74 | scr_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).scr_map.h 75 | -------------------------------------------------------------------------------- /config/PrivateConfigs.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | package rocketchip 3 | 4 | import Chisel._ 5 | import uncore._ 6 | import rocket._ 7 | //import cde._ 8 | import cde.{Parameters, Field, Config, Knob, Dump, World, Ex, ViewSym} 9 | import cde.Implicits._ 10 | import sha3._ 11 | 12 | //case object Width extends Field[Int] 13 | //case object Stages extends Field[Int] 14 | //case object FastMem extends Field[Boolean] 15 | //case object BufferSram extends Field[Boolean] 16 | 17 | class Sha3Config extends Config { 18 | override val topDefinitions:World.TopDefs = { 19 | (pname,site,here) => pname match { 20 | case WidthP => 64 21 | case Stages => Knob("stages") 22 | case FastMem => Knob("fast_mem") 23 | case BufferSram => Dump(Knob("buffer_sram")) 24 | case RoccMaxTaggedMemXacts => 32 25 | case BuildRoCC => Seq( 26 | RoccParameters( 27 | opcodes = OpcodeSet.custom0, 28 | generator = (p: Parameters) => (Module(new Sha3Accel()(p.alterPartial({ case CoreName => "Rocket" })))) )) 29 | } 30 | } 31 | 32 | override val topConstraints:List[ViewSym=>Ex[Boolean]] = List( 33 | ex => ex(WidthP) === 64, 34 | ex => ex(Stages) >= 1 && ex(Stages) <= 4 && (ex(Stages)%2 === 0 || ex(Stages) === 1), 35 | ex => ex(FastMem) === ex(FastMem), 36 | ex => ex(BufferSram) === ex(BufferSram) 37 | //ex => ex[Boolean]("multi_vt") === ex[Boolean]("multi_vt") 38 | ) 39 | override val knobValues:Any=>Any = { 40 | case "stages" => 1 41 | case "fast_mem" => true 42 | case "buffer_sram" => false 43 | case "multi_vt" => true 44 | } 45 | } 46 | 47 | class Sha3VLSIConfig extends Config(new Sha3Config ++ new DefaultVLSIConfig) 48 | class Sha3FPGAConfig extends Config(new Sha3Config ++ new DefaultFPGAConfig) 49 | class Sha3CPPConfig extends Config(new Sha3Config ++ new DefaultCPPConfig) 50 | -------------------------------------------------------------------------------- /software/README.md: -------------------------------------------------------------------------------- 1 | # SHA3 Software Workloads 2 | 3 | This is an example set of workloads that uses the SHA3 rocc accelerator. 4 | 5 | # Getting Started 6 | 7 | Running these workloads require a modified Spike simulator that supports the SHA3 8 | custom extension, which can be found [here](https://github.com/ucb-bar/esp-isa-sim). If 9 | you are using Chipyard, you should install the esp-tools toolchain which comes 10 | with the appropriate version of Spike. 11 | 12 | To run linux-based workloads, you'll also need to update the linux submodule: 13 | 14 | cd sha3 15 | git submodule update --init software/linux 16 | 17 | These workloads all use FireMarshal to build and test. All the examples in this 18 | README assume that marshal is on your PATH (the default if you've set up 19 | chipyard). 20 | 21 | The first time you build a workload using FireMarshal, the `build.sh` script 22 | will be run automatically. This script compiles all of our dependencies (e.g. 23 | Linux and Buildroot). The first time building will take a long time since some 24 | of these dependencies take a long time to build (especially Buildroot). 25 | Subsequent builds will go faster since FireMarshal caches dependencies. 26 | 27 | # Workloads 28 | 29 | All workload configuration files are in `marshal-configs`. 30 | 31 | ## Bare-Metal 32 | 33 | There are two different bare-metal workloads that are packaged in this 34 | repository. `sha3-bare-rocc` uses the SHA3 accelerator to run a SHA3 35 | computation. The `sha3-bare-sw` instead computes the 36 | SHA3 hash using software only. 37 | 38 | sha3-bare-rocc.yaml 39 | sha3-bare-sw.yaml 40 | 41 | To build either binary run: 42 | 43 | marshal build marshal-configs/sha3-bare-rocc.yaml 44 | marshal build marshal-configs/sha3-bare-sw.yaml 45 | 46 | To run the test interactively run: 47 | 48 | marshal launch --spike marshal-configs/sha3-bare-rocc.yaml 49 | marshal launch --spike marshal-configs/sha3-bare-sw.yaml 50 | 51 | To run the unit test run: 52 | 53 | marshal test --spike marshal-configs/sha3-bare-rocc.yaml 54 | marshal test --spike marshal-configs/sha3-bare-sw.yaml 55 | 56 | ## Linux 57 | 58 | ***sha3-linux*.yaml*** 59 | 60 | The linux-based workloads can boot in qemu so long as you don't actually access 61 | the rocc accelerator. To use the custom hardware, you must boot in spike: 62 | 63 | marshal --no-disk build marshal-configs/sha3-linux.yaml 64 | marshal --no-disk launch --spike marshal-configs/sha3-linux.yaml 65 | 66 | The `--no-disk` option tells marshal to build the root filesystem into the 67 | binary as an initial ram filesystem (this is needed because spike does not 68 | include a disk model). The `--spike` option tells FireMarshal to boot the image 69 | in spike so we can use the sha3 functional model (FireMarshal uses QEMU by 70 | default). 71 | 72 | ### Interactive Linux 73 | 74 | ***sha3-linux.yaml*** 75 | 76 | This workload boots buildroot and uses the SHA3 accelerator as a user-space 77 | program. The basic workload boots into an interactive session. You can look at 78 | `/root` in the target for binaries to execute. `sha3-sw` acts as a baseline and 79 | computes the hash in software only. `sha3-rocc` uses the rocc accelerator to 80 | compute the hash. 81 | 82 | ### Automated Linux Test 83 | 84 | ***sha3-linux-test.yaml*** 85 | 86 | This workload inherits from sha3-linux.yaml and adds a 'command' field that 87 | tells FireMarshal to run a command automatically when the workload runs. It also 88 | adds a 'testing' field that provides a reference output for FireMarshal to compare 89 | against when running `marshal test marshal-configs/sha3-linux-test.yaml`. Note that 90 | in FireMarshal, the reference output needs to match some subset of the actual 91 | output (notice that `test-reference/linux/sha3-linux-test/uartlog` only has the 92 | test output, while the actual program output is much longer. 93 | 94 | To use this workload, try running: 95 | 96 | marshal --no-disk test --spike marshal-configs/sha3-linux-test.yaml 97 | 98 | # Key Components of this Workload 99 | 100 | ## linux 101 | 102 | A fork of Linux with some minor changes to support the sha3 accelerator. 103 | 104 | ## marshal-configs 105 | 106 | This directory contains our FireMarshal configurations for each workload. 107 | 108 | ## test-reference 109 | 110 | This directory contains reference outputs for each of our automated test 111 | workloads. 112 | 113 | ## tests 114 | 115 | Contains simple unit tests for the accelerator. These will be incorproated into 116 | various test workloads. They are cross-compiled by `build.sh` (called 117 | automatically by FireMarshal when building workloads). 118 | 119 | ## jtr 120 | 121 | Contains a fork of John the Ripper that targets the SHA3 accelerator. This 122 | serves as our main end-to-end benchmark. 123 | -------------------------------------------------------------------------------- /software/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | 4 | # Build bare-metal tests 5 | echo "Building bare-metal tests" 6 | make -C tests/bare 7 | 8 | echo "Building linux tests" 9 | make -C tests/linux 10 | 11 | if [ ! -f linux/README ]; then 12 | echo "" 13 | echo "WARNING: Linux submodule not initialized, linux-based workloads will not work." >&2 14 | fi 15 | -------------------------------------------------------------------------------- /software/jtr/.gitignore: -------------------------------------------------------------------------------- 1 | overlay/usr/bin/john 2 | overlay/usr/share/john/ 3 | -------------------------------------------------------------------------------- /software/jtr/bench.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | set -e 3 | 4 | export HOME=/root 5 | cd /root/sha3 6 | 7 | echo 8 | echo 'John the Ripper: self-test/benchmark [baseline]' 9 | john --test=1 --format=Raw-SHA3-256 10 | echo 'John the Ripper: self-test/benchmark [RoCC]' 11 | john --test=1 --format=Raw-SHA3-256-rocc 12 | 13 | echo 'John the Ripper: wordlist crack mode [RoCC]' 14 | rm -f short.pot 15 | time john --wordlist --format=Raw-SHA3-256-rocc --pot='short.pot' short.txt 16 | echo 17 | 18 | poweroff 19 | -------------------------------------------------------------------------------- /software/jtr/buildroot-config: -------------------------------------------------------------------------------- 1 | BR2_PACKAGE_JOHN=y 2 | -------------------------------------------------------------------------------- /software/jtr/buildroot-external/Config.in: -------------------------------------------------------------------------------- 1 | source "$BR2_EXTERNAL_RISCV_SHA3_PATH/package/john/Config.in" 2 | -------------------------------------------------------------------------------- /software/jtr/buildroot-external/external.desc: -------------------------------------------------------------------------------- 1 | name: RISCV_SHA3 2 | -------------------------------------------------------------------------------- /software/jtr/buildroot-external/external.mk: -------------------------------------------------------------------------------- 1 | include $(sort $(wildcard $(BR2_EXTERNAL_RISCV_SHA3_PATH)/package/*/*.mk)) 2 | -------------------------------------------------------------------------------- /software/jtr/buildroot-external/package/john/Config.in: -------------------------------------------------------------------------------- 1 | config BR2_PACKAGE_JOHN 2 | bool "john" 3 | depends on BR2_USE_MMU # fork() 4 | select BR2_PACKAGE_OPENSSL 5 | help 6 | John the Ripper is a fast password cracker. 7 | 8 | https://www.openwall.com/john/ 9 | -------------------------------------------------------------------------------- /software/jtr/buildroot-external/package/john/john.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # John the Ripper 4 | # 5 | ################################################################################ 6 | 7 | JOHN_VERSION = riscv 8 | JOHN_SITE = https://github.com/ucb-bar/JohnTheRipper.git 9 | JOHN_SITE_METHOD = git 10 | #JOHN_VERSION = 1.9.0-jumbo-1 11 | #JOHN_SOURCE = john-$(JOHN_VERSION).tar.xz 12 | #JOHN_SITE = https://www.openwall.com/john/k 13 | JOHN_LICENSE = GPL-2.0 14 | JOHN_LICENSE_FILES = doc/LICENSE doc/COPYING 15 | JOHN_DEPENDENCIES = host-pkgconf openssl 16 | JOHN_SUBDIR = src 17 | 18 | # The build expects to run these with same options as gcc 19 | JOHN_CONF_ENV = CPP="$(TARGET_CC) -E" LD="$(TARGET_CC)" AS="$(TARGET_CC)" 20 | JOHN_CONF_OPTS = \ 21 | --enable-pkg-config \ 22 | --disable-native-tests \ 23 | $(if $(BR2_TOOLCHAIN_HAS_OPENMP),--enable,--disable)-openmp \ 24 | --with-systemwide 25 | 26 | # 0001-configure-use-pkg-config-openssl.patch 27 | # 0002-configure-fix-unsafe-library-paths.patch 28 | JOHN_AUTORECONF = YES 29 | 30 | define JOHN_INSTALL_TARGET_CMDS 31 | $(INSTALL) -m 0755 -D $(@D)/run/john $(TARGET_DIR)/usr/bin 32 | $(foreach f,unshadow unafs undrop zip2john gpg2john rar2john base64conv unique, 33 | ln -sf john $(TARGET_DIR)/usr/bin/$(f)) 34 | mkdir -p $(TARGET_DIR)/usr/share/john/rules 35 | $(INSTALL) -D -m 0644 -t $(TARGET_DIR)/usr/share/john $(@D)/run/*.chr $(@D)/run/*.conf $(@D)/run/*.lst 36 | $(INSTALL) -D -m 0644 -t $(TARGET_DIR)/usr/share/john/rules $(@D)/run/rules/* 37 | endef 38 | 39 | $(eval $(autotools-package)) 40 | -------------------------------------------------------------------------------- /software/jtr/crack.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | set -e 3 | 4 | export HOME=/root 5 | cd /root/sha3 6 | 7 | echo 8 | echo 'John the Ripper: incremental crack mode [RoCC]' 9 | rm -f long.pot 10 | time /usr/bin/john --format=Raw-SHA3-256-rocc --pot='long.pot' --incremental --verbosity=4 long.txt 11 | 12 | poweroff 13 | -------------------------------------------------------------------------------- /software/jtr/overlay/etc/init.d/S50apache: -------------------------------------------------------------------------------- 1 | #!/bin/true 2 | # Disable httpd service 3 | -------------------------------------------------------------------------------- /software/jtr/overlay/root/sha3/long.txt: -------------------------------------------------------------------------------- 1 | hash_4:8ea37d801ab88c0dbad5d7b8217ef9baafe0424c40aa6c027e04d442e94a83f0 2 | -------------------------------------------------------------------------------- /software/jtr/overlay/root/sha3/short.txt: -------------------------------------------------------------------------------- 1 | hash_0:be87f99a67e48ec4ec9f05b565f6ca531e24b9c71a62cfd3a58f54ebc60115ea 2 | hash_1:f706280cdf972ed4af636d540e7d2ea2ff3e9f91e63bc389b2aa0fa288c486a9 3 | hash_2:2cd81e6887b1618af765e2bc127f68b563e6a1b4abd397331b759f878eb8515e 4 | hash_3:9cdc6b9ff3d0d0a90cb8670fb972debc08947697c6b63903458abbaaa0fe93c9 5 | -------------------------------------------------------------------------------- /software/marshal-configs/sha3-bare-rocc.yaml: -------------------------------------------------------------------------------- 1 | { 2 | "name" : "sha3-bare-rocc", 3 | "workdir" : "..", 4 | "base" : "bare-base.json", 5 | "host-init" : "build.sh", 6 | "bin" : "tests/bare/sha3-rocc.riscv", 7 | "spike-args" : "--extension=sha3", 8 | "testing" : { 9 | "refDir" : "test-reference/bare-rocc" 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /software/marshal-configs/sha3-bare-sw.yaml: -------------------------------------------------------------------------------- 1 | { 2 | "name" : "sha3-bare-sw", 3 | "workdir" : "..", 4 | "base" : "bare-base.json", 5 | "host-init" : "build.sh", 6 | "bin" : "tests/bare/sha3-sw.riscv", 7 | "testing" : { 8 | "refDir" : "test-reference/bare-sw" 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /software/marshal-configs/sha3-linux-jtr-crack.yaml: -------------------------------------------------------------------------------- 1 | { 2 | "name" : "sha3-linux-jtr-crack", 3 | "base" : "sha3-linux-jtr.yaml", 4 | "workdir" : "..", 5 | "run" : "jtr/crack.sh" 6 | } 7 | -------------------------------------------------------------------------------- /software/marshal-configs/sha3-linux-jtr-test.yaml: -------------------------------------------------------------------------------- 1 | { 2 | "name" : "sha3-linux-jtr-test", 3 | "base" : "sha3-linux-jtr.yaml", 4 | "workdir" : "..", 5 | "run" : "jtr/bench.sh", 6 | "testing" : { 7 | "refDir" : "test-reference/linux-jtr" 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /software/marshal-configs/sha3-linux-jtr.yaml: -------------------------------------------------------------------------------- 1 | { 2 | "name" : "sha3-linux-jtr", 3 | "base" : "sha3-linux.yaml", 4 | "workdir" : "..", 5 | "distro" : { 6 | "name": "br", 7 | "opts": { 8 | "configs" : [ "jtr/buildroot-config" ], 9 | "environment" : { 10 | "BR2_EXTERNAL": "${SHA3_LINUX_JTR_PATH}/jtr/buildroot-external" 11 | } 12 | } 13 | }, 14 | "overlay" : "jtr/overlay" 15 | } 16 | -------------------------------------------------------------------------------- /software/marshal-configs/sha3-linux-test.yaml: -------------------------------------------------------------------------------- 1 | { 2 | "name" : "sha3-linux-test", 3 | "base" : "sha3-linux.yaml", 4 | "workdir" : "..", 5 | "command" : "/root/sha3-rocc", 6 | "testing" : { 7 | "refDir" : "test-reference/linux" 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /software/marshal-configs/sha3-linux.yaml: -------------------------------------------------------------------------------- 1 | { 2 | "name" : "sha3-linux", 3 | "base" : "br-base.json", 4 | "workdir" : "..", 5 | "host-init" : "build.sh", 6 | "files" : [ 7 | ["tests/linux/sha3-sw.riscv", "/root/sha3-sw"], 8 | ["tests/linux/sha3-rocc.riscv", "/root/sha3-rocc"] 9 | ], 10 | "linux-src" : "linux", 11 | "spike-args" : "--extension=sha3" 12 | } 13 | -------------------------------------------------------------------------------- /software/test-reference/bare-rocc/sha3-bare-rocc/uartlog: -------------------------------------------------------------------------------- 1 | Start basic test 1. 2 | output[0]:203 ==? results[0]:203 3 | output[1]:52 ==? results[1]:52 4 | output[2]:27 ==? results[2]:27 5 | output[3]:85 ==? results[3]:85 6 | output[4]:46 ==? results[4]:46 7 | output[5]:79 ==? results[5]:79 8 | output[6]:152 ==? results[6]:152 9 | output[7]:228 ==? results[7]:228 10 | output[8]:86 ==? results[8]:86 11 | output[9]:138 ==? results[9]:138 12 | output[10]:201 ==? results[10]:201 13 | output[11]:206 ==? results[11]:206 14 | output[12]:253 ==? results[12]:253 15 | output[13]:168 ==? results[13]:168 16 | output[14]:255 ==? results[14]:255 17 | output[15]:107 ==? results[15]:107 18 | output[16]:122 ==? results[16]:122 19 | output[17]:177 ==? results[17]:177 20 | output[18]:65 ==? results[18]:65 21 | output[19]:68 ==? results[19]:68 22 | output[20]:231 ==? results[20]:231 23 | output[21]:19 ==? results[21]:19 24 | output[22]:70 ==? results[22]:70 25 | output[23]:198 ==? results[23]:198 26 | output[24]:64 ==? results[24]:64 27 | output[25]:90 ==? results[25]:90 28 | output[26]:192 ==? results[26]:192 29 | output[27]:80 ==? results[27]:80 30 | output[28]:206 ==? results[28]:206 31 | output[29]:234 ==? results[29]:234 32 | output[30]:168 ==? results[30]:168 33 | output[31]:159 ==? results[31]:159 34 | Success! 35 | -------------------------------------------------------------------------------- /software/test-reference/bare-sw/sha3-bare-sw/uartlog: -------------------------------------------------------------------------------- 1 | Start basic test 1. 2 | output[0]:203 ==? results[0]:203 3 | output[1]:52 ==? results[1]:52 4 | output[2]:27 ==? results[2]:27 5 | output[3]:85 ==? results[3]:85 6 | output[4]:46 ==? results[4]:46 7 | output[5]:79 ==? results[5]:79 8 | output[6]:152 ==? results[6]:152 9 | output[7]:228 ==? results[7]:228 10 | output[8]:86 ==? results[8]:86 11 | output[9]:138 ==? results[9]:138 12 | output[10]:201 ==? results[10]:201 13 | output[11]:206 ==? results[11]:206 14 | output[12]:253 ==? results[12]:253 15 | output[13]:168 ==? results[13]:168 16 | output[14]:255 ==? results[14]:255 17 | output[15]:107 ==? results[15]:107 18 | output[16]:122 ==? results[16]:122 19 | output[17]:177 ==? results[17]:177 20 | output[18]:65 ==? results[18]:65 21 | output[19]:68 ==? results[19]:68 22 | output[20]:231 ==? results[20]:231 23 | output[21]:19 ==? results[21]:19 24 | output[22]:70 ==? results[22]:70 25 | output[23]:198 ==? results[23]:198 26 | output[24]:64 ==? results[24]:64 27 | output[25]:90 ==? results[25]:90 28 | output[26]:192 ==? results[26]:192 29 | output[27]:80 ==? results[27]:80 30 | output[28]:206 ==? results[28]:206 31 | output[29]:234 ==? results[29]:234 32 | output[30]:168 ==? results[30]:168 33 | output[31]:159 ==? results[31]:159 34 | Success! 35 | -------------------------------------------------------------------------------- /software/test-reference/linux-jtr/sha3-linux-jtr-test/uartlog: -------------------------------------------------------------------------------- 1 | bears (hash_3) 2 | california (hash_2) 3 | passw0rd (hash_0) 4 | micro (hash_1) 5 | -------------------------------------------------------------------------------- /software/test-reference/linux/sha3-linux-test/uartlog: -------------------------------------------------------------------------------- 1 | Start basic test 1. 2 | output[0]:203 ==? results[0]:203 3 | output[1]:52 ==? results[1]:52 4 | output[2]:27 ==? results[2]:27 5 | output[3]:85 ==? results[3]:85 6 | output[4]:46 ==? results[4]:46 7 | output[5]:79 ==? results[5]:79 8 | output[6]:152 ==? results[6]:152 9 | output[7]:228 ==? results[7]:228 10 | output[8]:86 ==? results[8]:86 11 | output[9]:138 ==? results[9]:138 12 | output[10]:201 ==? results[10]:201 13 | output[11]:206 ==? results[11]:206 14 | output[12]:253 ==? results[12]:253 15 | output[13]:168 ==? results[13]:168 16 | output[14]:255 ==? results[14]:255 17 | output[15]:107 ==? results[15]:107 18 | output[16]:122 ==? results[16]:122 19 | output[17]:177 ==? results[17]:177 20 | output[18]:65 ==? results[18]:65 21 | output[19]:68 ==? results[19]:68 22 | output[20]:231 ==? results[20]:231 23 | output[21]:19 ==? results[21]:19 24 | output[22]:70 ==? results[22]:70 25 | output[23]:198 ==? results[23]:198 26 | output[24]:64 ==? results[24]:64 27 | output[25]:90 ==? results[25]:90 28 | output[26]:192 ==? results[26]:192 29 | output[27]:80 ==? results[27]:80 30 | output[28]:206 ==? results[28]:206 31 | output[29]:234 ==? results[29]:234 32 | output[30]:168 ==? results[30]:168 33 | output[31]:159 ==? results[31]:159 34 | Success! 35 | -------------------------------------------------------------------------------- /software/test_local.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | 4 | ../../../software/firemarshal/marshal test -s marshal-configs/sha3-bare-rocc.json 5 | if [ $? != 0 ]; then 6 | echo "Bare-metal test failed" 7 | fi 8 | 9 | ../../../software/firemarshal/marshal -d test -s marshal-configs/sha3-linux-test.json 10 | if [ $? != 0 ]; then 11 | echo "Linux unit test failed" 12 | fi 13 | 14 | ../../../software/firemarshal/marshal -d test -s marshal-configs/sha3-linux-jtr-test.json 15 | if [ $? != 0 ]; then 16 | echo "Linux John the Ripper test failed" 17 | fi 18 | -------------------------------------------------------------------------------- /software/tests/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.dump 3 | *.riscv 4 | *.rv 5 | -------------------------------------------------------------------------------- /software/tests/bare/Makefile: -------------------------------------------------------------------------------- 1 | bmarkdir := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) 2 | 3 | TARGET := riscv64-unknown-elf 4 | CFLAGS := -mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -fno-tree-loop-distribute-patterns 5 | LDFLAGS := -static -nostdlib -nostartfiles -lgcc 6 | 7 | PROGRAMS := sha3-rocc sha3-sw 8 | 9 | objs := crt.o syscalls.o 10 | ldscript := link.ld 11 | 12 | include $(bmarkdir)/../common.mk 13 | -------------------------------------------------------------------------------- /software/tests/bare/crt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "encoding.h" 4 | 5 | #if __riscv_xlen == 64 6 | # define LREG ld 7 | # define SREG sd 8 | # define REGBYTES 8 9 | #else 10 | # define LREG lw 11 | # define SREG sw 12 | # define REGBYTES 4 13 | #endif 14 | 15 | .section ".text.init" 16 | .globl _start 17 | _start: 18 | li x1, 0 19 | li x2, 0 20 | li x3, 0 21 | li x4, 0 22 | li x5, 0 23 | li x6, 0 24 | li x7, 0 25 | li x8, 0 26 | li x9, 0 27 | li x10,0 28 | li x11,0 29 | li x12,0 30 | li x13,0 31 | li x14,0 32 | li x15,0 33 | li x16,0 34 | li x17,0 35 | li x18,0 36 | li x19,0 37 | li x20,0 38 | li x21,0 39 | li x22,0 40 | li x23,0 41 | li x24,0 42 | li x25,0 43 | li x26,0 44 | li x27,0 45 | li x28,0 46 | li x29,0 47 | li x30,0 48 | li x31,0 49 | 50 | # enable FPU and accelerator if present 51 | li t0, MSTATUS_FS | MSTATUS_XS 52 | csrs mstatus, t0 53 | 54 | # make sure XLEN agrees with compilation choice 55 | li t0, 1 56 | slli t0, t0, 31 57 | #if __riscv_xlen == 64 58 | bgez t0, 1f 59 | #else 60 | bltz t0, 1f 61 | #endif 62 | 2: 63 | li a0, 1 64 | sw a0, tohost, t0 65 | j 2b 66 | 1: 67 | 68 | #ifdef __riscv_flen 69 | # initialize FPU if we have one 70 | la t0, 1f 71 | csrw mtvec, t0 72 | 73 | fssr x0 74 | fmv.s.x f0, x0 75 | fmv.s.x f1, x0 76 | fmv.s.x f2, x0 77 | fmv.s.x f3, x0 78 | fmv.s.x f4, x0 79 | fmv.s.x f5, x0 80 | fmv.s.x f6, x0 81 | fmv.s.x f7, x0 82 | fmv.s.x f8, x0 83 | fmv.s.x f9, x0 84 | fmv.s.x f10,x0 85 | fmv.s.x f11,x0 86 | fmv.s.x f12,x0 87 | fmv.s.x f13,x0 88 | fmv.s.x f14,x0 89 | fmv.s.x f15,x0 90 | fmv.s.x f16,x0 91 | fmv.s.x f17,x0 92 | fmv.s.x f18,x0 93 | fmv.s.x f19,x0 94 | fmv.s.x f20,x0 95 | fmv.s.x f21,x0 96 | fmv.s.x f22,x0 97 | fmv.s.x f23,x0 98 | fmv.s.x f24,x0 99 | fmv.s.x f25,x0 100 | fmv.s.x f26,x0 101 | fmv.s.x f27,x0 102 | fmv.s.x f28,x0 103 | fmv.s.x f29,x0 104 | fmv.s.x f30,x0 105 | fmv.s.x f31,x0 106 | 1: 107 | #endif 108 | 109 | # initialize trap vector 110 | la t0, trap_entry 111 | csrw mtvec, t0 112 | 113 | # initialize global pointer 114 | .option push 115 | .option norelax 116 | la gp, __global_pointer$ 117 | .option pop 118 | 119 | la tp, _end + 63 120 | and tp, tp, -64 121 | 122 | # get core id 123 | csrr a0, mhartid 124 | # for now, assume only 1 core 125 | li a1, 1 126 | 1:bgeu a0, a1, 1b 127 | 128 | # give each core 128KB of stack + TLS 129 | #define STKSHIFT 17 130 | sll a2, a0, STKSHIFT 131 | add tp, tp, a2 132 | add sp, a0, 1 133 | sll sp, sp, STKSHIFT 134 | add sp, sp, tp 135 | 136 | j _init 137 | 138 | .align 2 139 | trap_entry: 140 | addi sp, sp, -272 141 | 142 | SREG x1, 1*REGBYTES(sp) 143 | SREG x2, 2*REGBYTES(sp) 144 | SREG x3, 3*REGBYTES(sp) 145 | SREG x4, 4*REGBYTES(sp) 146 | SREG x5, 5*REGBYTES(sp) 147 | SREG x6, 6*REGBYTES(sp) 148 | SREG x7, 7*REGBYTES(sp) 149 | SREG x8, 8*REGBYTES(sp) 150 | SREG x9, 9*REGBYTES(sp) 151 | SREG x10, 10*REGBYTES(sp) 152 | SREG x11, 11*REGBYTES(sp) 153 | SREG x12, 12*REGBYTES(sp) 154 | SREG x13, 13*REGBYTES(sp) 155 | SREG x14, 14*REGBYTES(sp) 156 | SREG x15, 15*REGBYTES(sp) 157 | SREG x16, 16*REGBYTES(sp) 158 | SREG x17, 17*REGBYTES(sp) 159 | SREG x18, 18*REGBYTES(sp) 160 | SREG x19, 19*REGBYTES(sp) 161 | SREG x20, 20*REGBYTES(sp) 162 | SREG x21, 21*REGBYTES(sp) 163 | SREG x22, 22*REGBYTES(sp) 164 | SREG x23, 23*REGBYTES(sp) 165 | SREG x24, 24*REGBYTES(sp) 166 | SREG x25, 25*REGBYTES(sp) 167 | SREG x26, 26*REGBYTES(sp) 168 | SREG x27, 27*REGBYTES(sp) 169 | SREG x28, 28*REGBYTES(sp) 170 | SREG x29, 29*REGBYTES(sp) 171 | SREG x30, 30*REGBYTES(sp) 172 | SREG x31, 31*REGBYTES(sp) 173 | 174 | csrr a0, mcause 175 | csrr a1, mepc 176 | mv a2, sp 177 | jal handle_trap 178 | csrw mepc, a0 179 | 180 | # Remain in M-mode after eret 181 | li t0, MSTATUS_MPP 182 | csrs mstatus, t0 183 | 184 | LREG x1, 1*REGBYTES(sp) 185 | LREG x2, 2*REGBYTES(sp) 186 | LREG x3, 3*REGBYTES(sp) 187 | LREG x4, 4*REGBYTES(sp) 188 | LREG x5, 5*REGBYTES(sp) 189 | LREG x6, 6*REGBYTES(sp) 190 | LREG x7, 7*REGBYTES(sp) 191 | LREG x8, 8*REGBYTES(sp) 192 | LREG x9, 9*REGBYTES(sp) 193 | LREG x10, 10*REGBYTES(sp) 194 | LREG x11, 11*REGBYTES(sp) 195 | LREG x12, 12*REGBYTES(sp) 196 | LREG x13, 13*REGBYTES(sp) 197 | LREG x14, 14*REGBYTES(sp) 198 | LREG x15, 15*REGBYTES(sp) 199 | LREG x16, 16*REGBYTES(sp) 200 | LREG x17, 17*REGBYTES(sp) 201 | LREG x18, 18*REGBYTES(sp) 202 | LREG x19, 19*REGBYTES(sp) 203 | LREG x20, 20*REGBYTES(sp) 204 | LREG x21, 21*REGBYTES(sp) 205 | LREG x22, 22*REGBYTES(sp) 206 | LREG x23, 23*REGBYTES(sp) 207 | LREG x24, 24*REGBYTES(sp) 208 | LREG x25, 25*REGBYTES(sp) 209 | LREG x26, 26*REGBYTES(sp) 210 | LREG x27, 27*REGBYTES(sp) 211 | LREG x28, 28*REGBYTES(sp) 212 | LREG x29, 29*REGBYTES(sp) 213 | LREG x30, 30*REGBYTES(sp) 214 | LREG x31, 31*REGBYTES(sp) 215 | 216 | addi sp, sp, 272 217 | mret 218 | 219 | .section ".tdata.begin" 220 | .globl _tdata_begin 221 | _tdata_begin: 222 | 223 | .section ".tdata.end" 224 | .globl _tdata_end 225 | _tdata_end: 226 | 227 | .section ".tbss.end" 228 | .globl _tbss_end 229 | _tbss_end: 230 | 231 | .section ".tohost","aw",@progbits 232 | .align 6 233 | .globl tohost 234 | tohost: .dword 0 235 | .align 6 236 | .globl fromhost 237 | fromhost: .dword 0 238 | -------------------------------------------------------------------------------- /software/tests/bare/link.ld: -------------------------------------------------------------------------------- 1 | /*======================================================================*/ 2 | /* Proxy kernel linker script */ 3 | /*======================================================================*/ 4 | /* This is the linker script used when building the proxy kernel. */ 5 | 6 | /*----------------------------------------------------------------------*/ 7 | /* Setup */ 8 | /*----------------------------------------------------------------------*/ 9 | 10 | /* The OUTPUT_ARCH command specifies the machine architecture where the 11 | argument is one of the names used in the BFD library. More 12 | specifically one of the entires in bfd/cpu-mips.c */ 13 | 14 | OUTPUT_ARCH( "riscv" ) 15 | ENTRY(_start) 16 | 17 | /*----------------------------------------------------------------------*/ 18 | /* Sections */ 19 | /*----------------------------------------------------------------------*/ 20 | 21 | SECTIONS 22 | { 23 | 24 | /* text: test code section */ 25 | . = 0x80000000; 26 | .text.init : { *(.text.init) } 27 | 28 | .tohost ALIGN(0x1000) : { *(.tohost) } 29 | 30 | .text : { *(.text) } 31 | 32 | . = 0x80004000; 33 | .rodata : { *(.rodata) } 34 | 35 | /* data segment */ 36 | .data ALIGN(0x40) : { *(.data) } 37 | 38 | .sdata : { 39 | __global_pointer$ = . + 0x800; 40 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) 41 | *(.sdata .sdata.* .gnu.linkonce.s.*) 42 | } 43 | 44 | /* bss segment */ 45 | .sbss : { 46 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 47 | *(.scommon) 48 | } 49 | .bss ALIGN(0x40) : { *(.bss) } 50 | 51 | /* thread-local data segment */ 52 | .tdata : 53 | { 54 | _tls_data = .; 55 | *(.tdata.begin) 56 | *(.tdata) 57 | *(.tdata.end) 58 | } 59 | .tbss : 60 | { 61 | *(.tbss) 62 | *(.tbss.end) 63 | } 64 | 65 | 66 | /* End of uninitalized data segement */ 67 | _end = .; 68 | } 69 | 70 | -------------------------------------------------------------------------------- /software/tests/bare/mmio.h: -------------------------------------------------------------------------------- 1 | #ifndef __MMIO_H__ 2 | #define __MMIO_H__ 3 | 4 | #include 5 | 6 | static inline void reg_write8(uintptr_t addr, uint8_t data) 7 | { 8 | volatile uint8_t *ptr = (volatile uint8_t *) addr; 9 | *ptr = data; 10 | } 11 | 12 | static inline uint8_t reg_read8(uintptr_t addr) 13 | { 14 | volatile uint8_t *ptr = (volatile uint8_t *) addr; 15 | return *ptr; 16 | } 17 | 18 | static inline void reg_write16(uintptr_t addr, uint16_t data) 19 | { 20 | volatile uint16_t *ptr = (volatile uint16_t *) addr; 21 | *ptr = data; 22 | } 23 | 24 | static inline uint16_t reg_read16(uintptr_t addr) 25 | { 26 | volatile uint16_t *ptr = (volatile uint16_t *) addr; 27 | return *ptr; 28 | } 29 | 30 | static inline void reg_write32(uintptr_t addr, uint32_t data) 31 | { 32 | volatile uint32_t *ptr = (volatile uint32_t *) addr; 33 | *ptr = data; 34 | } 35 | 36 | static inline uint32_t reg_read32(uintptr_t addr) 37 | { 38 | volatile uint32_t *ptr = (volatile uint32_t *) addr; 39 | return *ptr; 40 | } 41 | 42 | static inline void reg_write64(unsigned long addr, uint64_t data) 43 | { 44 | volatile uint64_t *ptr = (volatile uint64_t *) addr; 45 | *ptr = data; 46 | } 47 | 48 | static inline uint64_t reg_read64(unsigned long addr) 49 | { 50 | volatile uint64_t *ptr = (volatile uint64_t *) addr; 51 | return *ptr; 52 | } 53 | 54 | #endif 55 | -------------------------------------------------------------------------------- /software/tests/bare/syscalls.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include "util.h" 11 | 12 | #define SYS_write 64 13 | 14 | #undef strcmp 15 | 16 | extern volatile uint64_t tohost; 17 | extern volatile uint64_t fromhost; 18 | 19 | static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2) 20 | { 21 | volatile uint64_t magic_mem[8] __attribute__((aligned(64))); 22 | magic_mem[0] = which; 23 | magic_mem[1] = arg0; 24 | magic_mem[2] = arg1; 25 | magic_mem[3] = arg2; 26 | __sync_synchronize(); 27 | 28 | tohost = (uintptr_t)magic_mem; 29 | while (fromhost == 0) 30 | ; 31 | fromhost = 0; 32 | 33 | __sync_synchronize(); 34 | return magic_mem[0]; 35 | } 36 | 37 | #define NUM_COUNTERS 2 38 | static uintptr_t counters[NUM_COUNTERS]; 39 | static char* counter_names[NUM_COUNTERS]; 40 | 41 | void setStats(int enable) 42 | { 43 | int i = 0; 44 | #define READ_CTR(name) do { \ 45 | while (i >= NUM_COUNTERS) ; \ 46 | uintptr_t csr = read_csr(name); \ 47 | if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ 48 | counters[i++] = csr; \ 49 | } while (0) 50 | 51 | READ_CTR(mcycle); 52 | READ_CTR(minstret); 53 | 54 | #undef READ_CTR 55 | } 56 | 57 | void __attribute__((noreturn)) tohost_exit(uintptr_t code) 58 | { 59 | tohost = (code << 1) | 1; 60 | while (1); 61 | } 62 | 63 | uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) 64 | { 65 | tohost_exit(1337); 66 | } 67 | 68 | void exit(int code) 69 | { 70 | tohost_exit(code); 71 | } 72 | 73 | void abort() 74 | { 75 | exit(128 + SIGABRT); 76 | } 77 | 78 | void printstr(const char* s) 79 | { 80 | syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); 81 | } 82 | 83 | void __attribute__((weak)) thread_entry(int cid, int nc) 84 | { 85 | // multi-threaded programs override this function. 86 | // for the case of single-threaded programs, only let core 0 proceed. 87 | while (cid != 0); 88 | } 89 | 90 | int __attribute__((weak)) main(int argc, char** argv) 91 | { 92 | // single-threaded programs override this function. 93 | printstr("Implement main(), foo!\n"); 94 | return -1; 95 | } 96 | 97 | static void init_tls() 98 | { 99 | register void* thread_pointer asm("tp"); 100 | extern char _tls_data; 101 | extern __thread char _tdata_begin, _tdata_end, _tbss_end; 102 | size_t tdata_size = &_tdata_end - &_tdata_begin; 103 | memcpy(thread_pointer, &_tls_data, tdata_size); 104 | size_t tbss_size = &_tbss_end - &_tdata_end; 105 | memset(thread_pointer + tdata_size, 0, tbss_size); 106 | } 107 | 108 | void _init(int cid, int nc) 109 | { 110 | init_tls(); 111 | thread_entry(cid, nc); 112 | 113 | // only single-threaded programs should ever get here. 114 | int ret = main(0, 0); 115 | 116 | char buf[NUM_COUNTERS * 32] __attribute__((aligned(64))); 117 | char* pbuf = buf; 118 | for (int i = 0; i < NUM_COUNTERS; i++) 119 | if (counters[i]) 120 | pbuf += sprintf(pbuf, "%s = %" PRIuPTR "\n", counter_names[i], counters[i]); 121 | if (pbuf != buf) 122 | printstr(buf); 123 | 124 | exit(ret); 125 | } 126 | 127 | #undef putchar 128 | int putchar(int ch) 129 | { 130 | static __thread char buf[64] __attribute__((aligned(64))); 131 | static __thread int buflen = 0; 132 | 133 | buf[buflen++] = ch; 134 | 135 | if (ch == '\n' || buflen == sizeof(buf)) 136 | { 137 | syscall(SYS_write, 1, (uintptr_t)buf, buflen); 138 | buflen = 0; 139 | } 140 | 141 | return 0; 142 | } 143 | 144 | void printhex(uint64_t x) 145 | { 146 | char str[17]; 147 | int i; 148 | for (i = 0; i < 16; i++) 149 | { 150 | str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); 151 | x >>= 4; 152 | } 153 | str[16] = 0; 154 | 155 | printstr(str); 156 | } 157 | 158 | static inline void printnum(void (*putch)(int, void**), void **putdat, 159 | unsigned long long num, unsigned base, int width, int padc) 160 | { 161 | unsigned digs[sizeof(num)*CHAR_BIT]; 162 | int pos = 0; 163 | 164 | while (1) 165 | { 166 | digs[pos++] = num % base; 167 | if (num < base) 168 | break; 169 | num /= base; 170 | } 171 | 172 | while (width-- > pos) 173 | putch(padc, putdat); 174 | 175 | while (pos-- > 0) 176 | putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); 177 | } 178 | 179 | static unsigned long long getuint(va_list *ap, int lflag) 180 | { 181 | if (lflag >= 2) 182 | return va_arg(*ap, unsigned long long); 183 | else if (lflag) 184 | return va_arg(*ap, unsigned long); 185 | else 186 | return va_arg(*ap, unsigned int); 187 | } 188 | 189 | static long long getint(va_list *ap, int lflag) 190 | { 191 | if (lflag >= 2) 192 | return va_arg(*ap, long long); 193 | else if (lflag) 194 | return va_arg(*ap, long); 195 | else 196 | return va_arg(*ap, int); 197 | } 198 | 199 | static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) 200 | { 201 | register const char* p; 202 | const char* last_fmt; 203 | register int ch, err; 204 | unsigned long long num; 205 | int base, lflag, width, precision, altflag; 206 | char padc; 207 | 208 | while (1) { 209 | while ((ch = *(unsigned char *) fmt) != '%') { 210 | if (ch == '\0') 211 | return; 212 | fmt++; 213 | putch(ch, putdat); 214 | } 215 | fmt++; 216 | 217 | // Process a %-escape sequence 218 | last_fmt = fmt; 219 | padc = ' '; 220 | width = -1; 221 | precision = -1; 222 | lflag = 0; 223 | altflag = 0; 224 | reswitch: 225 | switch (ch = *(unsigned char *) fmt++) { 226 | 227 | // flag to pad on the right 228 | case '-': 229 | padc = '-'; 230 | goto reswitch; 231 | 232 | // flag to pad with 0's instead of spaces 233 | case '0': 234 | padc = '0'; 235 | goto reswitch; 236 | 237 | // width field 238 | case '1': 239 | case '2': 240 | case '3': 241 | case '4': 242 | case '5': 243 | case '6': 244 | case '7': 245 | case '8': 246 | case '9': 247 | for (precision = 0; ; ++fmt) { 248 | precision = precision * 10 + ch - '0'; 249 | ch = *fmt; 250 | if (ch < '0' || ch > '9') 251 | break; 252 | } 253 | goto process_precision; 254 | 255 | case '*': 256 | precision = va_arg(ap, int); 257 | goto process_precision; 258 | 259 | case '.': 260 | if (width < 0) 261 | width = 0; 262 | goto reswitch; 263 | 264 | case '#': 265 | altflag = 1; 266 | goto reswitch; 267 | 268 | process_precision: 269 | if (width < 0) 270 | width = precision, precision = -1; 271 | goto reswitch; 272 | 273 | // long flag (doubled for long long) 274 | case 'l': 275 | lflag++; 276 | goto reswitch; 277 | 278 | // character 279 | case 'c': 280 | putch(va_arg(ap, int), putdat); 281 | break; 282 | 283 | // string 284 | case 's': 285 | if ((p = va_arg(ap, char *)) == NULL) 286 | p = "(null)"; 287 | if (width > 0 && padc != '-') 288 | for (width -= strnlen(p, precision); width > 0; width--) 289 | putch(padc, putdat); 290 | for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { 291 | putch(ch, putdat); 292 | p++; 293 | } 294 | for (; width > 0; width--) 295 | putch(' ', putdat); 296 | break; 297 | 298 | // (signed) decimal 299 | case 'd': 300 | num = getint(&ap, lflag); 301 | if ((long long) num < 0) { 302 | putch('-', putdat); 303 | num = -(long long) num; 304 | } 305 | base = 10; 306 | goto signed_number; 307 | 308 | // unsigned decimal 309 | case 'u': 310 | base = 10; 311 | goto unsigned_number; 312 | 313 | // (unsigned) octal 314 | case 'o': 315 | // should do something with padding so it's always 3 octits 316 | base = 8; 317 | goto unsigned_number; 318 | 319 | // pointer 320 | case 'p': 321 | static_assert(sizeof(long) == sizeof(void*)); 322 | lflag = 1; 323 | putch('0', putdat); 324 | putch('x', putdat); 325 | /* fall through to 'x' */ 326 | 327 | // (unsigned) hexadecimal 328 | case 'x': 329 | base = 16; 330 | unsigned_number: 331 | num = getuint(&ap, lflag); 332 | signed_number: 333 | printnum(putch, putdat, num, base, width, padc); 334 | break; 335 | 336 | // escaped '%' character 337 | case '%': 338 | putch(ch, putdat); 339 | break; 340 | 341 | // unrecognized escape sequence - just print it literally 342 | default: 343 | putch('%', putdat); 344 | fmt = last_fmt; 345 | break; 346 | } 347 | } 348 | } 349 | 350 | int printf(const char* fmt, ...) 351 | { 352 | va_list ap; 353 | va_start(ap, fmt); 354 | 355 | vprintfmt((void*)putchar, 0, fmt, ap); 356 | 357 | va_end(ap); 358 | return 0; // incorrect return value, but who cares, anyway? 359 | } 360 | 361 | int sprintf(char* str, const char* fmt, ...) 362 | { 363 | va_list ap; 364 | char* str0 = str; 365 | va_start(ap, fmt); 366 | 367 | void sprintf_putch(int ch, void** data) 368 | { 369 | char** pstr = (char**)data; 370 | **pstr = ch; 371 | (*pstr)++; 372 | } 373 | 374 | vprintfmt(sprintf_putch, (void**)&str, fmt, ap); 375 | *str = 0; 376 | 377 | va_end(ap); 378 | return str - str0; 379 | } 380 | 381 | void* memcpy(void* dest, const void* src, size_t len) 382 | { 383 | if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { 384 | const uintptr_t* s = src; 385 | uintptr_t *d = dest; 386 | while (d < (uintptr_t*)(dest + len)) 387 | *d++ = *s++; 388 | } else { 389 | const char* s = src; 390 | char *d = dest; 391 | while (d < (char*)(dest + len)) 392 | *d++ = *s++; 393 | } 394 | return dest; 395 | } 396 | 397 | void* memset(void* dest, int byte, size_t len) 398 | { 399 | if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { 400 | uintptr_t word = byte & 0xFF; 401 | word |= word << 8; 402 | word |= word << 16; 403 | word |= word << 16 << 16; 404 | 405 | uintptr_t *d = dest; 406 | while (d < (uintptr_t*)(dest + len)) 407 | *d++ = word; 408 | } else { 409 | char *d = dest; 410 | while (d < (char*)(dest + len)) 411 | *d++ = byte; 412 | } 413 | return dest; 414 | } 415 | 416 | size_t strlen(const char *s) 417 | { 418 | const char *p = s; 419 | while (*p) 420 | p++; 421 | return p - s; 422 | } 423 | 424 | size_t strnlen(const char *s, size_t n) 425 | { 426 | const char *p = s; 427 | while (n-- && *p) 428 | p++; 429 | return p - s; 430 | } 431 | 432 | int strcmp(const char* s1, const char* s2) 433 | { 434 | unsigned char c1, c2; 435 | 436 | do { 437 | c1 = *s1++; 438 | c2 = *s2++; 439 | } while (c1 != 0 && c1 == c2); 440 | 441 | return c1 - c2; 442 | } 443 | 444 | char* strcpy(char* dest, const char* src) 445 | { 446 | char* d = dest; 447 | while ((*d++ = *src++)) 448 | ; 449 | return dest; 450 | } 451 | 452 | long atol(const char* str) 453 | { 454 | long res = 0; 455 | int sign = 0; 456 | 457 | while (*str == ' ') 458 | str++; 459 | 460 | if (*str == '-' || *str == '+') { 461 | sign = *str == '-'; 462 | str++; 463 | } 464 | 465 | while (*str) { 466 | res *= 10; 467 | res += *str++ - '0'; 468 | } 469 | 470 | return sign ? -res : res; 471 | } 472 | -------------------------------------------------------------------------------- /software/tests/bare/util.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef __UTIL_H 4 | #define __UTIL_H 5 | 6 | //-------------------------------------------------------------------------- 7 | // Macros 8 | 9 | // Set HOST_DEBUG to 1 if you are going to compile this for a host 10 | // machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG 11 | // to 0 if you are compiling with the smips-gcc toolchain. 12 | 13 | #ifndef HOST_DEBUG 14 | #define HOST_DEBUG 0 15 | #endif 16 | 17 | // Set PREALLOCATE to 1 if you want to preallocate the benchmark 18 | // function before starting stats. If you have instruction/data 19 | // caches and you don't want to count the overhead of misses, then 20 | // you will need to use preallocation. 21 | 22 | #ifndef PREALLOCATE 23 | #define PREALLOCATE 0 24 | #endif 25 | 26 | // Set SET_STATS to 1 if you want to carve out the piece that actually 27 | // does the computation. 28 | 29 | #if HOST_DEBUG 30 | #include 31 | static void setStats(int enable) {} 32 | #else 33 | extern void setStats(int enable); 34 | #endif 35 | 36 | #include 37 | 38 | #define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } 39 | 40 | static void printArray(const char name[], int n, const int arr[]) 41 | { 42 | #if HOST_DEBUG 43 | int i; 44 | printf( " %10s :", name ); 45 | for ( i = 0; i < n; i++ ) 46 | printf( " %3d ", arr[i] ); 47 | printf( "\n" ); 48 | #endif 49 | } 50 | 51 | static void printDoubleArray(const char name[], int n, const double arr[]) 52 | { 53 | #if HOST_DEBUG 54 | int i; 55 | printf( " %10s :", name ); 56 | for ( i = 0; i < n; i++ ) 57 | printf( " %g ", arr[i] ); 58 | printf( "\n" ); 59 | #endif 60 | } 61 | 62 | static int verify(int n, const volatile int* test, const int* verify) 63 | { 64 | int i; 65 | // Unrolled for faster verification 66 | for (i = 0; i < n/2*2; i+=2) 67 | { 68 | int t0 = test[i], t1 = test[i+1]; 69 | int v0 = verify[i], v1 = verify[i+1]; 70 | if (t0 != v0) return i+1; 71 | if (t1 != v1) return i+2; 72 | } 73 | if (n % 2 != 0 && test[n-1] != verify[n-1]) 74 | return n; 75 | return 0; 76 | } 77 | 78 | static int verifyDouble(int n, const volatile double* test, const double* verify) 79 | { 80 | int i; 81 | // Unrolled for faster verification 82 | for (i = 0; i < n/2*2; i+=2) 83 | { 84 | double t0 = test[i], t1 = test[i+1]; 85 | double v0 = verify[i], v1 = verify[i+1]; 86 | int eq1 = t0 == v0, eq2 = t1 == v1; 87 | if (!(eq1 & eq2)) return i+1+eq1; 88 | } 89 | if (n % 2 != 0 && test[n-1] != verify[n-1]) 90 | return n; 91 | return 0; 92 | } 93 | 94 | static void __attribute__((noinline)) barrier(int ncores) 95 | { 96 | static volatile int sense; 97 | static volatile int count; 98 | static __thread int threadsense; 99 | 100 | __sync_synchronize(); 101 | 102 | threadsense = !threadsense; 103 | if (__sync_fetch_and_add(&count, 1) == ncores-1) 104 | { 105 | count = 0; 106 | sense = threadsense; 107 | } 108 | else while(sense != threadsense) 109 | ; 110 | 111 | __sync_synchronize(); 112 | } 113 | 114 | static uint64_t lfsr(uint64_t x) 115 | { 116 | uint64_t bit = (x ^ (x >> 1)) & 1; 117 | return (x >> 1) | (bit << 62); 118 | } 119 | 120 | #ifdef __riscv 121 | #include "encoding.h" 122 | #endif 123 | 124 | #define stringify_1(s) #s 125 | #define stringify(s) stringify_1(s) 126 | #define stats(code, iter) do { \ 127 | unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ 128 | code; \ 129 | _c += read_csr(mcycle), _i += read_csr(minstret); \ 130 | if (cid == 0) \ 131 | printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ 132 | stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ 133 | } while(0) 134 | 135 | #endif //__UTIL_H 136 | -------------------------------------------------------------------------------- /software/tests/common.mk: -------------------------------------------------------------------------------- 1 | basedir := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) 2 | srcdir := $(basedir)/src 3 | 4 | PROGRAMS ?= sha3-sw sha3-rocc 5 | 6 | CC := $(TARGET)-gcc 7 | OBJDUMP := $(TARGET)-objdump 8 | 9 | CFLAGS += -I $(srcdir) 10 | 11 | hdrs := $(wildcard *.h) $(wildcard $(srcdir)/*.h) 12 | objs ?= 13 | ldscript ?= 14 | 15 | %.o: $(srcdir)/%.c $(hdrs) 16 | $(CC) $(CFLAGS) -o $@ -c $< 17 | %.o: %.c $(hdrs) 18 | $(CC) $(CFLAGS) -o $@ -c $< 19 | %.o: %.S $(hdrs) 20 | $(CC) $(CFLAGS) -D__ASSEMBLY__=1 -o $@ -c $< 21 | 22 | %.riscv: %.o $(objs) $(ldscript) 23 | $(CC) $(LDFLAGS) $(if $(ldscript),-T $(ldscript)) -o $@ $< $(objs) 24 | 25 | %.dump: %.riscv 26 | $(OBJDUMP) -d $< > $@ 27 | 28 | .DEFAULT: elf 29 | 30 | .PHONY: elf dumps 31 | elf: $(addsuffix .riscv,$(PROGRAMS)) 32 | dumps: $(addsuffix .dump,$(PROGRAMS)) 33 | 34 | .PHONY: clean 35 | clean: 36 | rm -f -- *.riscv *.o *.dump 37 | 38 | .SUFFIXES: 39 | .SUFFIXES: .o .c .S 40 | -------------------------------------------------------------------------------- /software/tests/linux/Makefile: -------------------------------------------------------------------------------- 1 | bmarkdir := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) 2 | 3 | TARGET := riscv64-unknown-linux-gnu 4 | CFLAGS := -std=gnu99 -O2 -Wall 5 | LDFLAGS := 6 | 7 | include $(bmarkdir)/../common.mk 8 | -------------------------------------------------------------------------------- /software/tests/src/compiler.h: -------------------------------------------------------------------------------- 1 | #ifndef __COMPILER_H 2 | #define __COMPILER_H 3 | 4 | #ifdef __GNUC__ 5 | 6 | #ifndef __aligned 7 | #define __aligned(x) __attribute__ ((aligned (x))) 8 | #endif 9 | 10 | #else /* !__GNU_C__ */ 11 | #warning "Unknown compiler" 12 | 13 | #ifndef 14 | #define __aligned(x) 15 | #endif 16 | #endif 17 | 18 | #endif /* __COMPILER_H */ 19 | -------------------------------------------------------------------------------- /software/tests/src/encoding.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef RISCV_CSR_ENCODING_H 4 | #define RISCV_CSR_ENCODING_H 5 | 6 | #define MSTATUS_UIE 0x00000001 7 | #define MSTATUS_SIE 0x00000002 8 | #define MSTATUS_HIE 0x00000004 9 | #define MSTATUS_MIE 0x00000008 10 | #define MSTATUS_UPIE 0x00000010 11 | #define MSTATUS_SPIE 0x00000020 12 | #define MSTATUS_HPIE 0x00000040 13 | #define MSTATUS_MPIE 0x00000080 14 | #define MSTATUS_SPP 0x00000100 15 | #define MSTATUS_HPP 0x00000600 16 | #define MSTATUS_MPP 0x00001800 17 | #define MSTATUS_FS 0x00006000 18 | #define MSTATUS_XS 0x00018000 19 | #define MSTATUS_MPRV 0x00020000 20 | #define MSTATUS_PUM 0x00040000 21 | #define MSTATUS_MXR 0x00080000 22 | #define MSTATUS_VM 0x1F000000 23 | #define MSTATUS32_SD 0x80000000 24 | #define MSTATUS64_SD 0x8000000000000000 25 | 26 | #define SSTATUS_UIE 0x00000001 27 | #define SSTATUS_SIE 0x00000002 28 | #define SSTATUS_UPIE 0x00000010 29 | #define SSTATUS_SPIE 0x00000020 30 | #define SSTATUS_SPP 0x00000100 31 | #define SSTATUS_FS 0x00006000 32 | #define SSTATUS_XS 0x00018000 33 | #define SSTATUS_PUM 0x00040000 34 | #define SSTATUS32_SD 0x80000000 35 | #define SSTATUS64_SD 0x8000000000000000 36 | 37 | #define DCSR_XDEBUGVER (3U<<30) 38 | #define DCSR_NDRESET (1<<29) 39 | #define DCSR_FULLRESET (1<<28) 40 | #define DCSR_EBREAKM (1<<15) 41 | #define DCSR_EBREAKH (1<<14) 42 | #define DCSR_EBREAKS (1<<13) 43 | #define DCSR_EBREAKU (1<<12) 44 | #define DCSR_STOPCYCLE (1<<10) 45 | #define DCSR_STOPTIME (1<<9) 46 | #define DCSR_CAUSE (7<<6) 47 | #define DCSR_DEBUGINT (1<<5) 48 | #define DCSR_HALT (1<<3) 49 | #define DCSR_STEP (1<<2) 50 | #define DCSR_PRV (3<<0) 51 | 52 | #define DCSR_CAUSE_NONE 0 53 | #define DCSR_CAUSE_SWBP 1 54 | #define DCSR_CAUSE_HWBP 2 55 | #define DCSR_CAUSE_DEBUGINT 3 56 | #define DCSR_CAUSE_STEP 4 57 | #define DCSR_CAUSE_HALT 5 58 | 59 | #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 60 | #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 61 | #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 62 | 63 | #define MCONTROL_SELECT (1<<19) 64 | #define MCONTROL_TIMING (1<<18) 65 | #define MCONTROL_ACTION (0x3f<<12) 66 | #define MCONTROL_CHAIN (1<<11) 67 | #define MCONTROL_MATCH (0xf<<7) 68 | #define MCONTROL_M (1<<6) 69 | #define MCONTROL_H (1<<5) 70 | #define MCONTROL_S (1<<4) 71 | #define MCONTROL_U (1<<3) 72 | #define MCONTROL_EXECUTE (1<<2) 73 | #define MCONTROL_STORE (1<<1) 74 | #define MCONTROL_LOAD (1<<0) 75 | 76 | #define MCONTROL_TYPE_NONE 0 77 | #define MCONTROL_TYPE_MATCH 2 78 | 79 | #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 80 | #define MCONTROL_ACTION_DEBUG_MODE 1 81 | #define MCONTROL_ACTION_TRACE_START 2 82 | #define MCONTROL_ACTION_TRACE_STOP 3 83 | #define MCONTROL_ACTION_TRACE_EMIT 4 84 | 85 | #define MCONTROL_MATCH_EQUAL 0 86 | #define MCONTROL_MATCH_NAPOT 1 87 | #define MCONTROL_MATCH_GE 2 88 | #define MCONTROL_MATCH_LT 3 89 | #define MCONTROL_MATCH_MASK_LOW 4 90 | #define MCONTROL_MATCH_MASK_HIGH 5 91 | 92 | #define MIP_SSIP (1 << IRQ_S_SOFT) 93 | #define MIP_HSIP (1 << IRQ_H_SOFT) 94 | #define MIP_MSIP (1 << IRQ_M_SOFT) 95 | #define MIP_STIP (1 << IRQ_S_TIMER) 96 | #define MIP_HTIP (1 << IRQ_H_TIMER) 97 | #define MIP_MTIP (1 << IRQ_M_TIMER) 98 | #define MIP_SEIP (1 << IRQ_S_EXT) 99 | #define MIP_HEIP (1 << IRQ_H_EXT) 100 | #define MIP_MEIP (1 << IRQ_M_EXT) 101 | 102 | #define SIP_SSIP MIP_SSIP 103 | #define SIP_STIP MIP_STIP 104 | 105 | #define PRV_U 0 106 | #define PRV_S 1 107 | #define PRV_H 2 108 | #define PRV_M 3 109 | 110 | #define VM_MBARE 0 111 | #define VM_MBB 1 112 | #define VM_MBBID 2 113 | #define VM_SV32 8 114 | #define VM_SV39 9 115 | #define VM_SV48 10 116 | 117 | #define IRQ_S_SOFT 1 118 | #define IRQ_H_SOFT 2 119 | #define IRQ_M_SOFT 3 120 | #define IRQ_S_TIMER 5 121 | #define IRQ_H_TIMER 6 122 | #define IRQ_M_TIMER 7 123 | #define IRQ_S_EXT 9 124 | #define IRQ_H_EXT 10 125 | #define IRQ_M_EXT 11 126 | #define IRQ_COP 12 127 | #define IRQ_HOST 13 128 | 129 | #define DEFAULT_RSTVEC 0x00001000 130 | #define DEFAULT_NMIVEC 0x00001004 131 | #define DEFAULT_MTVEC 0x00001010 132 | #define CONFIG_STRING_ADDR 0x0000100C 133 | #define EXT_IO_BASE 0x40000000 134 | #define DRAM_BASE 0x80000000 135 | 136 | // page table entry (PTE) fields 137 | #define PTE_V 0x001 // Valid 138 | #define PTE_R 0x002 // Read 139 | #define PTE_W 0x004 // Write 140 | #define PTE_X 0x008 // Execute 141 | #define PTE_U 0x010 // User 142 | #define PTE_G 0x020 // Global 143 | #define PTE_A 0x040 // Accessed 144 | #define PTE_D 0x080 // Dirty 145 | #define PTE_SOFT 0x300 // Reserved for Software 146 | 147 | #define PTE_PPN_SHIFT 10 148 | 149 | #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 150 | 151 | #ifdef __riscv 152 | 153 | #ifdef __riscv64 154 | # define MSTATUS_SD MSTATUS64_SD 155 | # define SSTATUS_SD SSTATUS64_SD 156 | # define RISCV_PGLEVEL_BITS 9 157 | #else 158 | # define MSTATUS_SD MSTATUS32_SD 159 | # define SSTATUS_SD SSTATUS32_SD 160 | # define RISCV_PGLEVEL_BITS 10 161 | #endif 162 | #define RISCV_PGSHIFT 12 163 | #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 164 | 165 | #ifndef __ASSEMBLER__ 166 | 167 | #ifdef __GNUC__ 168 | 169 | #define read_csr(reg) ({ unsigned long __tmp; \ 170 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 171 | __tmp; }) 172 | 173 | #define write_csr(reg, val) ({ \ 174 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 175 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 176 | else \ 177 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 178 | 179 | #define swap_csr(reg, val) ({ unsigned long __tmp; \ 180 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 181 | asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ 182 | else \ 183 | asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ 184 | __tmp; }) 185 | 186 | #define set_csr(reg, bit) ({ unsigned long __tmp; \ 187 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 188 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 189 | else \ 190 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 191 | __tmp; }) 192 | 193 | #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 194 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 195 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 196 | else \ 197 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 198 | __tmp; }) 199 | 200 | #define rdtime() read_csr(time) 201 | #define rdcycle() read_csr(cycle) 202 | #define rdinstret() read_csr(instret) 203 | 204 | #endif 205 | 206 | #endif 207 | 208 | #endif 209 | 210 | #endif 211 | /* Automatically generated by parse-opcodes */ 212 | #ifndef RISCV_ENCODING_H 213 | #define RISCV_ENCODING_H 214 | #define MATCH_BEQ 0x63 215 | #define MASK_BEQ 0x707f 216 | #define MATCH_BNE 0x1063 217 | #define MASK_BNE 0x707f 218 | #define MATCH_BLT 0x4063 219 | #define MASK_BLT 0x707f 220 | #define MATCH_BGE 0x5063 221 | #define MASK_BGE 0x707f 222 | #define MATCH_BLTU 0x6063 223 | #define MASK_BLTU 0x707f 224 | #define MATCH_BGEU 0x7063 225 | #define MASK_BGEU 0x707f 226 | #define MATCH_JALR 0x67 227 | #define MASK_JALR 0x707f 228 | #define MATCH_JAL 0x6f 229 | #define MASK_JAL 0x7f 230 | #define MATCH_LUI 0x37 231 | #define MASK_LUI 0x7f 232 | #define MATCH_AUIPC 0x17 233 | #define MASK_AUIPC 0x7f 234 | #define MATCH_ADDI 0x13 235 | #define MASK_ADDI 0x707f 236 | #define MATCH_SLLI 0x1013 237 | #define MASK_SLLI 0xfc00707f 238 | #define MATCH_SLTI 0x2013 239 | #define MASK_SLTI 0x707f 240 | #define MATCH_SLTIU 0x3013 241 | #define MASK_SLTIU 0x707f 242 | #define MATCH_XORI 0x4013 243 | #define MASK_XORI 0x707f 244 | #define MATCH_SRLI 0x5013 245 | #define MASK_SRLI 0xfc00707f 246 | #define MATCH_SRAI 0x40005013 247 | #define MASK_SRAI 0xfc00707f 248 | #define MATCH_ORI 0x6013 249 | #define MASK_ORI 0x707f 250 | #define MATCH_ANDI 0x7013 251 | #define MASK_ANDI 0x707f 252 | #define MATCH_ADD 0x33 253 | #define MASK_ADD 0xfe00707f 254 | #define MATCH_SUB 0x40000033 255 | #define MASK_SUB 0xfe00707f 256 | #define MATCH_SLL 0x1033 257 | #define MASK_SLL 0xfe00707f 258 | #define MATCH_SLT 0x2033 259 | #define MASK_SLT 0xfe00707f 260 | #define MATCH_SLTU 0x3033 261 | #define MASK_SLTU 0xfe00707f 262 | #define MATCH_XOR 0x4033 263 | #define MASK_XOR 0xfe00707f 264 | #define MATCH_SRL 0x5033 265 | #define MASK_SRL 0xfe00707f 266 | #define MATCH_SRA 0x40005033 267 | #define MASK_SRA 0xfe00707f 268 | #define MATCH_OR 0x6033 269 | #define MASK_OR 0xfe00707f 270 | #define MATCH_AND 0x7033 271 | #define MASK_AND 0xfe00707f 272 | #define MATCH_ADDIW 0x1b 273 | #define MASK_ADDIW 0x707f 274 | #define MATCH_SLLIW 0x101b 275 | #define MASK_SLLIW 0xfe00707f 276 | #define MATCH_SRLIW 0x501b 277 | #define MASK_SRLIW 0xfe00707f 278 | #define MATCH_SRAIW 0x4000501b 279 | #define MASK_SRAIW 0xfe00707f 280 | #define MATCH_ADDW 0x3b 281 | #define MASK_ADDW 0xfe00707f 282 | #define MATCH_SUBW 0x4000003b 283 | #define MASK_SUBW 0xfe00707f 284 | #define MATCH_SLLW 0x103b 285 | #define MASK_SLLW 0xfe00707f 286 | #define MATCH_SRLW 0x503b 287 | #define MASK_SRLW 0xfe00707f 288 | #define MATCH_SRAW 0x4000503b 289 | #define MASK_SRAW 0xfe00707f 290 | #define MATCH_LB 0x3 291 | #define MASK_LB 0x707f 292 | #define MATCH_LH 0x1003 293 | #define MASK_LH 0x707f 294 | #define MATCH_LW 0x2003 295 | #define MASK_LW 0x707f 296 | #define MATCH_LD 0x3003 297 | #define MASK_LD 0x707f 298 | #define MATCH_LBU 0x4003 299 | #define MASK_LBU 0x707f 300 | #define MATCH_LHU 0x5003 301 | #define MASK_LHU 0x707f 302 | #define MATCH_LWU 0x6003 303 | #define MASK_LWU 0x707f 304 | #define MATCH_SB 0x23 305 | #define MASK_SB 0x707f 306 | #define MATCH_SH 0x1023 307 | #define MASK_SH 0x707f 308 | #define MATCH_SW 0x2023 309 | #define MASK_SW 0x707f 310 | #define MATCH_SD 0x3023 311 | #define MASK_SD 0x707f 312 | #define MATCH_FENCE 0xf 313 | #define MASK_FENCE 0x707f 314 | #define MATCH_FENCE_I 0x100f 315 | #define MASK_FENCE_I 0x707f 316 | #define MATCH_MUL 0x2000033 317 | #define MASK_MUL 0xfe00707f 318 | #define MATCH_MULH 0x2001033 319 | #define MASK_MULH 0xfe00707f 320 | #define MATCH_MULHSU 0x2002033 321 | #define MASK_MULHSU 0xfe00707f 322 | #define MATCH_MULHU 0x2003033 323 | #define MASK_MULHU 0xfe00707f 324 | #define MATCH_DIV 0x2004033 325 | #define MASK_DIV 0xfe00707f 326 | #define MATCH_DIVU 0x2005033 327 | #define MASK_DIVU 0xfe00707f 328 | #define MATCH_REM 0x2006033 329 | #define MASK_REM 0xfe00707f 330 | #define MATCH_REMU 0x2007033 331 | #define MASK_REMU 0xfe00707f 332 | #define MATCH_MULW 0x200003b 333 | #define MASK_MULW 0xfe00707f 334 | #define MATCH_DIVW 0x200403b 335 | #define MASK_DIVW 0xfe00707f 336 | #define MATCH_DIVUW 0x200503b 337 | #define MASK_DIVUW 0xfe00707f 338 | #define MATCH_REMW 0x200603b 339 | #define MASK_REMW 0xfe00707f 340 | #define MATCH_REMUW 0x200703b 341 | #define MASK_REMUW 0xfe00707f 342 | #define MATCH_AMOADD_W 0x202f 343 | #define MASK_AMOADD_W 0xf800707f 344 | #define MATCH_AMOXOR_W 0x2000202f 345 | #define MASK_AMOXOR_W 0xf800707f 346 | #define MATCH_AMOOR_W 0x4000202f 347 | #define MASK_AMOOR_W 0xf800707f 348 | #define MATCH_AMOAND_W 0x6000202f 349 | #define MASK_AMOAND_W 0xf800707f 350 | #define MATCH_AMOMIN_W 0x8000202f 351 | #define MASK_AMOMIN_W 0xf800707f 352 | #define MATCH_AMOMAX_W 0xa000202f 353 | #define MASK_AMOMAX_W 0xf800707f 354 | #define MATCH_AMOMINU_W 0xc000202f 355 | #define MASK_AMOMINU_W 0xf800707f 356 | #define MATCH_AMOMAXU_W 0xe000202f 357 | #define MASK_AMOMAXU_W 0xf800707f 358 | #define MATCH_AMOSWAP_W 0x800202f 359 | #define MASK_AMOSWAP_W 0xf800707f 360 | #define MATCH_LR_W 0x1000202f 361 | #define MASK_LR_W 0xf9f0707f 362 | #define MATCH_SC_W 0x1800202f 363 | #define MASK_SC_W 0xf800707f 364 | #define MATCH_AMOADD_D 0x302f 365 | #define MASK_AMOADD_D 0xf800707f 366 | #define MATCH_AMOXOR_D 0x2000302f 367 | #define MASK_AMOXOR_D 0xf800707f 368 | #define MATCH_AMOOR_D 0x4000302f 369 | #define MASK_AMOOR_D 0xf800707f 370 | #define MATCH_AMOAND_D 0x6000302f 371 | #define MASK_AMOAND_D 0xf800707f 372 | #define MATCH_AMOMIN_D 0x8000302f 373 | #define MASK_AMOMIN_D 0xf800707f 374 | #define MATCH_AMOMAX_D 0xa000302f 375 | #define MASK_AMOMAX_D 0xf800707f 376 | #define MATCH_AMOMINU_D 0xc000302f 377 | #define MASK_AMOMINU_D 0xf800707f 378 | #define MATCH_AMOMAXU_D 0xe000302f 379 | #define MASK_AMOMAXU_D 0xf800707f 380 | #define MATCH_AMOSWAP_D 0x800302f 381 | #define MASK_AMOSWAP_D 0xf800707f 382 | #define MATCH_LR_D 0x1000302f 383 | #define MASK_LR_D 0xf9f0707f 384 | #define MATCH_SC_D 0x1800302f 385 | #define MASK_SC_D 0xf800707f 386 | #define MATCH_ECALL 0x73 387 | #define MASK_ECALL 0xffffffff 388 | #define MATCH_EBREAK 0x100073 389 | #define MASK_EBREAK 0xffffffff 390 | #define MATCH_URET 0x200073 391 | #define MASK_URET 0xffffffff 392 | #define MATCH_SRET 0x10200073 393 | #define MASK_SRET 0xffffffff 394 | #define MATCH_HRET 0x20200073 395 | #define MASK_HRET 0xffffffff 396 | #define MATCH_MRET 0x30200073 397 | #define MASK_MRET 0xffffffff 398 | #define MATCH_DRET 0x7b200073 399 | #define MASK_DRET 0xffffffff 400 | #define MATCH_SFENCE_VM 0x10400073 401 | #define MASK_SFENCE_VM 0xfff07fff 402 | #define MATCH_WFI 0x10500073 403 | #define MASK_WFI 0xffffffff 404 | #define MATCH_CSRRW 0x1073 405 | #define MASK_CSRRW 0x707f 406 | #define MATCH_CSRRS 0x2073 407 | #define MASK_CSRRS 0x707f 408 | #define MATCH_CSRRC 0x3073 409 | #define MASK_CSRRC 0x707f 410 | #define MATCH_CSRRWI 0x5073 411 | #define MASK_CSRRWI 0x707f 412 | #define MATCH_CSRRSI 0x6073 413 | #define MASK_CSRRSI 0x707f 414 | #define MATCH_CSRRCI 0x7073 415 | #define MASK_CSRRCI 0x707f 416 | #define MATCH_FADD_S 0x53 417 | #define MASK_FADD_S 0xfe00007f 418 | #define MATCH_FSUB_S 0x8000053 419 | #define MASK_FSUB_S 0xfe00007f 420 | #define MATCH_FMUL_S 0x10000053 421 | #define MASK_FMUL_S 0xfe00007f 422 | #define MATCH_FDIV_S 0x18000053 423 | #define MASK_FDIV_S 0xfe00007f 424 | #define MATCH_FSGNJ_S 0x20000053 425 | #define MASK_FSGNJ_S 0xfe00707f 426 | #define MATCH_FSGNJN_S 0x20001053 427 | #define MASK_FSGNJN_S 0xfe00707f 428 | #define MATCH_FSGNJX_S 0x20002053 429 | #define MASK_FSGNJX_S 0xfe00707f 430 | #define MATCH_FMIN_S 0x28000053 431 | #define MASK_FMIN_S 0xfe00707f 432 | #define MATCH_FMAX_S 0x28001053 433 | #define MASK_FMAX_S 0xfe00707f 434 | #define MATCH_FSQRT_S 0x58000053 435 | #define MASK_FSQRT_S 0xfff0007f 436 | #define MATCH_FADD_D 0x2000053 437 | #define MASK_FADD_D 0xfe00007f 438 | #define MATCH_FSUB_D 0xa000053 439 | #define MASK_FSUB_D 0xfe00007f 440 | #define MATCH_FMUL_D 0x12000053 441 | #define MASK_FMUL_D 0xfe00007f 442 | #define MATCH_FDIV_D 0x1a000053 443 | #define MASK_FDIV_D 0xfe00007f 444 | #define MATCH_FSGNJ_D 0x22000053 445 | #define MASK_FSGNJ_D 0xfe00707f 446 | #define MATCH_FSGNJN_D 0x22001053 447 | #define MASK_FSGNJN_D 0xfe00707f 448 | #define MATCH_FSGNJX_D 0x22002053 449 | #define MASK_FSGNJX_D 0xfe00707f 450 | #define MATCH_FMIN_D 0x2a000053 451 | #define MASK_FMIN_D 0xfe00707f 452 | #define MATCH_FMAX_D 0x2a001053 453 | #define MASK_FMAX_D 0xfe00707f 454 | #define MATCH_FCVT_S_D 0x40100053 455 | #define MASK_FCVT_S_D 0xfff0007f 456 | #define MATCH_FCVT_D_S 0x42000053 457 | #define MASK_FCVT_D_S 0xfff0007f 458 | #define MATCH_FSQRT_D 0x5a000053 459 | #define MASK_FSQRT_D 0xfff0007f 460 | #define MATCH_FLE_S 0xa0000053 461 | #define MASK_FLE_S 0xfe00707f 462 | #define MATCH_FLT_S 0xa0001053 463 | #define MASK_FLT_S 0xfe00707f 464 | #define MATCH_FEQ_S 0xa0002053 465 | #define MASK_FEQ_S 0xfe00707f 466 | #define MATCH_FLE_D 0xa2000053 467 | #define MASK_FLE_D 0xfe00707f 468 | #define MATCH_FLT_D 0xa2001053 469 | #define MASK_FLT_D 0xfe00707f 470 | #define MATCH_FEQ_D 0xa2002053 471 | #define MASK_FEQ_D 0xfe00707f 472 | #define MATCH_FCVT_W_S 0xc0000053 473 | #define MASK_FCVT_W_S 0xfff0007f 474 | #define MATCH_FCVT_WU_S 0xc0100053 475 | #define MASK_FCVT_WU_S 0xfff0007f 476 | #define MATCH_FCVT_L_S 0xc0200053 477 | #define MASK_FCVT_L_S 0xfff0007f 478 | #define MATCH_FCVT_LU_S 0xc0300053 479 | #define MASK_FCVT_LU_S 0xfff0007f 480 | #define MATCH_FMV_X_S 0xe0000053 481 | #define MASK_FMV_X_S 0xfff0707f 482 | #define MATCH_FCLASS_S 0xe0001053 483 | #define MASK_FCLASS_S 0xfff0707f 484 | #define MATCH_FCVT_W_D 0xc2000053 485 | #define MASK_FCVT_W_D 0xfff0007f 486 | #define MATCH_FCVT_WU_D 0xc2100053 487 | #define MASK_FCVT_WU_D 0xfff0007f 488 | #define MATCH_FCVT_L_D 0xc2200053 489 | #define MASK_FCVT_L_D 0xfff0007f 490 | #define MATCH_FCVT_LU_D 0xc2300053 491 | #define MASK_FCVT_LU_D 0xfff0007f 492 | #define MATCH_FMV_X_D 0xe2000053 493 | #define MASK_FMV_X_D 0xfff0707f 494 | #define MATCH_FCLASS_D 0xe2001053 495 | #define MASK_FCLASS_D 0xfff0707f 496 | #define MATCH_FCVT_S_W 0xd0000053 497 | #define MASK_FCVT_S_W 0xfff0007f 498 | #define MATCH_FCVT_S_WU 0xd0100053 499 | #define MASK_FCVT_S_WU 0xfff0007f 500 | #define MATCH_FCVT_S_L 0xd0200053 501 | #define MASK_FCVT_S_L 0xfff0007f 502 | #define MATCH_FCVT_S_LU 0xd0300053 503 | #define MASK_FCVT_S_LU 0xfff0007f 504 | #define MATCH_FMV_S_X 0xf0000053 505 | #define MASK_FMV_S_X 0xfff0707f 506 | #define MATCH_FCVT_D_W 0xd2000053 507 | #define MASK_FCVT_D_W 0xfff0007f 508 | #define MATCH_FCVT_D_WU 0xd2100053 509 | #define MASK_FCVT_D_WU 0xfff0007f 510 | #define MATCH_FCVT_D_L 0xd2200053 511 | #define MASK_FCVT_D_L 0xfff0007f 512 | #define MATCH_FCVT_D_LU 0xd2300053 513 | #define MASK_FCVT_D_LU 0xfff0007f 514 | #define MATCH_FMV_D_X 0xf2000053 515 | #define MASK_FMV_D_X 0xfff0707f 516 | #define MATCH_FLW 0x2007 517 | #define MASK_FLW 0x707f 518 | #define MATCH_FLD 0x3007 519 | #define MASK_FLD 0x707f 520 | #define MATCH_FSW 0x2027 521 | #define MASK_FSW 0x707f 522 | #define MATCH_FSD 0x3027 523 | #define MASK_FSD 0x707f 524 | #define MATCH_FMADD_S 0x43 525 | #define MASK_FMADD_S 0x600007f 526 | #define MATCH_FMSUB_S 0x47 527 | #define MASK_FMSUB_S 0x600007f 528 | #define MATCH_FNMSUB_S 0x4b 529 | #define MASK_FNMSUB_S 0x600007f 530 | #define MATCH_FNMADD_S 0x4f 531 | #define MASK_FNMADD_S 0x600007f 532 | #define MATCH_FMADD_D 0x2000043 533 | #define MASK_FMADD_D 0x600007f 534 | #define MATCH_FMSUB_D 0x2000047 535 | #define MASK_FMSUB_D 0x600007f 536 | #define MATCH_FNMSUB_D 0x200004b 537 | #define MASK_FNMSUB_D 0x600007f 538 | #define MATCH_FNMADD_D 0x200004f 539 | #define MASK_FNMADD_D 0x600007f 540 | #define MATCH_C_NOP 0x1 541 | #define MASK_C_NOP 0xffff 542 | #define MATCH_C_ADDI16SP 0x6101 543 | #define MASK_C_ADDI16SP 0xef83 544 | #define MATCH_C_JR 0x8002 545 | #define MASK_C_JR 0xf07f 546 | #define MATCH_C_JALR 0x9002 547 | #define MASK_C_JALR 0xf07f 548 | #define MATCH_C_EBREAK 0x9002 549 | #define MASK_C_EBREAK 0xffff 550 | #define MATCH_C_LD 0x6000 551 | #define MASK_C_LD 0xe003 552 | #define MATCH_C_SD 0xe000 553 | #define MASK_C_SD 0xe003 554 | #define MATCH_C_ADDIW 0x2001 555 | #define MASK_C_ADDIW 0xe003 556 | #define MATCH_C_LDSP 0x6002 557 | #define MASK_C_LDSP 0xe003 558 | #define MATCH_C_SDSP 0xe002 559 | #define MASK_C_SDSP 0xe003 560 | #define MATCH_C_ADDI4SPN 0x0 561 | #define MASK_C_ADDI4SPN 0xe003 562 | #define MATCH_C_FLD 0x2000 563 | #define MASK_C_FLD 0xe003 564 | #define MATCH_C_LW 0x4000 565 | #define MASK_C_LW 0xe003 566 | #define MATCH_C_FLW 0x6000 567 | #define MASK_C_FLW 0xe003 568 | #define MATCH_C_FSD 0xa000 569 | #define MASK_C_FSD 0xe003 570 | #define MATCH_C_SW 0xc000 571 | #define MASK_C_SW 0xe003 572 | #define MATCH_C_FSW 0xe000 573 | #define MASK_C_FSW 0xe003 574 | #define MATCH_C_ADDI 0x1 575 | #define MASK_C_ADDI 0xe003 576 | #define MATCH_C_JAL 0x2001 577 | #define MASK_C_JAL 0xe003 578 | #define MATCH_C_LI 0x4001 579 | #define MASK_C_LI 0xe003 580 | #define MATCH_C_LUI 0x6001 581 | #define MASK_C_LUI 0xe003 582 | #define MATCH_C_SRLI 0x8001 583 | #define MASK_C_SRLI 0xec03 584 | #define MATCH_C_SRAI 0x8401 585 | #define MASK_C_SRAI 0xec03 586 | #define MATCH_C_ANDI 0x8801 587 | #define MASK_C_ANDI 0xec03 588 | #define MATCH_C_SUB 0x8c01 589 | #define MASK_C_SUB 0xfc63 590 | #define MATCH_C_XOR 0x8c21 591 | #define MASK_C_XOR 0xfc63 592 | #define MATCH_C_OR 0x8c41 593 | #define MASK_C_OR 0xfc63 594 | #define MATCH_C_AND 0x8c61 595 | #define MASK_C_AND 0xfc63 596 | #define MATCH_C_SUBW 0x9c01 597 | #define MASK_C_SUBW 0xfc63 598 | #define MATCH_C_ADDW 0x9c21 599 | #define MASK_C_ADDW 0xfc63 600 | #define MATCH_C_J 0xa001 601 | #define MASK_C_J 0xe003 602 | #define MATCH_C_BEQZ 0xc001 603 | #define MASK_C_BEQZ 0xe003 604 | #define MATCH_C_BNEZ 0xe001 605 | #define MASK_C_BNEZ 0xe003 606 | #define MATCH_C_SLLI 0x2 607 | #define MASK_C_SLLI 0xe003 608 | #define MATCH_C_FLDSP 0x2002 609 | #define MASK_C_FLDSP 0xe003 610 | #define MATCH_C_LWSP 0x4002 611 | #define MASK_C_LWSP 0xe003 612 | #define MATCH_C_FLWSP 0x6002 613 | #define MASK_C_FLWSP 0xe003 614 | #define MATCH_C_MV 0x8002 615 | #define MASK_C_MV 0xf003 616 | #define MATCH_C_ADD 0x9002 617 | #define MASK_C_ADD 0xf003 618 | #define MATCH_C_FSDSP 0xa002 619 | #define MASK_C_FSDSP 0xe003 620 | #define MATCH_C_SWSP 0xc002 621 | #define MASK_C_SWSP 0xe003 622 | #define MATCH_C_FSWSP 0xe002 623 | #define MASK_C_FSWSP 0xe003 624 | #define MATCH_CUSTOM0 0xb 625 | #define MASK_CUSTOM0 0x707f 626 | #define MATCH_CUSTOM0_RS1 0x200b 627 | #define MASK_CUSTOM0_RS1 0x707f 628 | #define MATCH_CUSTOM0_RS1_RS2 0x300b 629 | #define MASK_CUSTOM0_RS1_RS2 0x707f 630 | #define MATCH_CUSTOM0_RD 0x400b 631 | #define MASK_CUSTOM0_RD 0x707f 632 | #define MATCH_CUSTOM0_RD_RS1 0x600b 633 | #define MASK_CUSTOM0_RD_RS1 0x707f 634 | #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 635 | #define MASK_CUSTOM0_RD_RS1_RS2 0x707f 636 | #define MATCH_CUSTOM1 0x2b 637 | #define MASK_CUSTOM1 0x707f 638 | #define MATCH_CUSTOM1_RS1 0x202b 639 | #define MASK_CUSTOM1_RS1 0x707f 640 | #define MATCH_CUSTOM1_RS1_RS2 0x302b 641 | #define MASK_CUSTOM1_RS1_RS2 0x707f 642 | #define MATCH_CUSTOM1_RD 0x402b 643 | #define MASK_CUSTOM1_RD 0x707f 644 | #define MATCH_CUSTOM1_RD_RS1 0x602b 645 | #define MASK_CUSTOM1_RD_RS1 0x707f 646 | #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 647 | #define MASK_CUSTOM1_RD_RS1_RS2 0x707f 648 | #define MATCH_CUSTOM2 0x5b 649 | #define MASK_CUSTOM2 0x707f 650 | #define MATCH_CUSTOM2_RS1 0x205b 651 | #define MASK_CUSTOM2_RS1 0x707f 652 | #define MATCH_CUSTOM2_RS1_RS2 0x305b 653 | #define MASK_CUSTOM2_RS1_RS2 0x707f 654 | #define MATCH_CUSTOM2_RD 0x405b 655 | #define MASK_CUSTOM2_RD 0x707f 656 | #define MATCH_CUSTOM2_RD_RS1 0x605b 657 | #define MASK_CUSTOM2_RD_RS1 0x707f 658 | #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 659 | #define MASK_CUSTOM2_RD_RS1_RS2 0x707f 660 | #define MATCH_CUSTOM3 0x7b 661 | #define MASK_CUSTOM3 0x707f 662 | #define MATCH_CUSTOM3_RS1 0x207b 663 | #define MASK_CUSTOM3_RS1 0x707f 664 | #define MATCH_CUSTOM3_RS1_RS2 0x307b 665 | #define MASK_CUSTOM3_RS1_RS2 0x707f 666 | #define MATCH_CUSTOM3_RD 0x407b 667 | #define MASK_CUSTOM3_RD 0x707f 668 | #define MATCH_CUSTOM3_RD_RS1 0x607b 669 | #define MASK_CUSTOM3_RD_RS1 0x707f 670 | #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 671 | #define MASK_CUSTOM3_RD_RS1_RS2 0x707f 672 | #define CSR_FFLAGS 0x1 673 | #define CSR_FRM 0x2 674 | #define CSR_FCSR 0x3 675 | #define CSR_CYCLE 0xc00 676 | #define CSR_TIME 0xc01 677 | #define CSR_INSTRET 0xc02 678 | #define CSR_HPMCOUNTER3 0xc03 679 | #define CSR_HPMCOUNTER4 0xc04 680 | #define CSR_HPMCOUNTER5 0xc05 681 | #define CSR_HPMCOUNTER6 0xc06 682 | #define CSR_HPMCOUNTER7 0xc07 683 | #define CSR_HPMCOUNTER8 0xc08 684 | #define CSR_HPMCOUNTER9 0xc09 685 | #define CSR_HPMCOUNTER10 0xc0a 686 | #define CSR_HPMCOUNTER11 0xc0b 687 | #define CSR_HPMCOUNTER12 0xc0c 688 | #define CSR_HPMCOUNTER13 0xc0d 689 | #define CSR_HPMCOUNTER14 0xc0e 690 | #define CSR_HPMCOUNTER15 0xc0f 691 | #define CSR_HPMCOUNTER16 0xc10 692 | #define CSR_HPMCOUNTER17 0xc11 693 | #define CSR_HPMCOUNTER18 0xc12 694 | #define CSR_HPMCOUNTER19 0xc13 695 | #define CSR_HPMCOUNTER20 0xc14 696 | #define CSR_HPMCOUNTER21 0xc15 697 | #define CSR_HPMCOUNTER22 0xc16 698 | #define CSR_HPMCOUNTER23 0xc17 699 | #define CSR_HPMCOUNTER24 0xc18 700 | #define CSR_HPMCOUNTER25 0xc19 701 | #define CSR_HPMCOUNTER26 0xc1a 702 | #define CSR_HPMCOUNTER27 0xc1b 703 | #define CSR_HPMCOUNTER28 0xc1c 704 | #define CSR_HPMCOUNTER29 0xc1d 705 | #define CSR_HPMCOUNTER30 0xc1e 706 | #define CSR_HPMCOUNTER31 0xc1f 707 | #define CSR_SSTATUS 0x100 708 | #define CSR_SIE 0x104 709 | #define CSR_STVEC 0x105 710 | #define CSR_SSCRATCH 0x140 711 | #define CSR_SEPC 0x141 712 | #define CSR_SCAUSE 0x142 713 | #define CSR_SBADADDR 0x143 714 | #define CSR_SIP 0x144 715 | #define CSR_SPTBR 0x180 716 | #define CSR_MSTATUS 0x300 717 | #define CSR_MISA 0x301 718 | #define CSR_MEDELEG 0x302 719 | #define CSR_MIDELEG 0x303 720 | #define CSR_MIE 0x304 721 | #define CSR_MTVEC 0x305 722 | #define CSR_MSCRATCH 0x340 723 | #define CSR_MEPC 0x341 724 | #define CSR_MCAUSE 0x342 725 | #define CSR_MBADADDR 0x343 726 | #define CSR_MIP 0x344 727 | #define CSR_TSELECT 0x7a0 728 | #define CSR_TDATA1 0x7a1 729 | #define CSR_TDATA2 0x7a2 730 | #define CSR_TDATA3 0x7a3 731 | #define CSR_DCSR 0x7b0 732 | #define CSR_DPC 0x7b1 733 | #define CSR_DSCRATCH 0x7b2 734 | #define CSR_MCYCLE 0xb00 735 | #define CSR_MINSTRET 0xb02 736 | #define CSR_MHPMCOUNTER3 0xb03 737 | #define CSR_MHPMCOUNTER4 0xb04 738 | #define CSR_MHPMCOUNTER5 0xb05 739 | #define CSR_MHPMCOUNTER6 0xb06 740 | #define CSR_MHPMCOUNTER7 0xb07 741 | #define CSR_MHPMCOUNTER8 0xb08 742 | #define CSR_MHPMCOUNTER9 0xb09 743 | #define CSR_MHPMCOUNTER10 0xb0a 744 | #define CSR_MHPMCOUNTER11 0xb0b 745 | #define CSR_MHPMCOUNTER12 0xb0c 746 | #define CSR_MHPMCOUNTER13 0xb0d 747 | #define CSR_MHPMCOUNTER14 0xb0e 748 | #define CSR_MHPMCOUNTER15 0xb0f 749 | #define CSR_MHPMCOUNTER16 0xb10 750 | #define CSR_MHPMCOUNTER17 0xb11 751 | #define CSR_MHPMCOUNTER18 0xb12 752 | #define CSR_MHPMCOUNTER19 0xb13 753 | #define CSR_MHPMCOUNTER20 0xb14 754 | #define CSR_MHPMCOUNTER21 0xb15 755 | #define CSR_MHPMCOUNTER22 0xb16 756 | #define CSR_MHPMCOUNTER23 0xb17 757 | #define CSR_MHPMCOUNTER24 0xb18 758 | #define CSR_MHPMCOUNTER25 0xb19 759 | #define CSR_MHPMCOUNTER26 0xb1a 760 | #define CSR_MHPMCOUNTER27 0xb1b 761 | #define CSR_MHPMCOUNTER28 0xb1c 762 | #define CSR_MHPMCOUNTER29 0xb1d 763 | #define CSR_MHPMCOUNTER30 0xb1e 764 | #define CSR_MHPMCOUNTER31 0xb1f 765 | #define CSR_MUCOUNTEREN 0x320 766 | #define CSR_MSCOUNTEREN 0x321 767 | #define CSR_MHPMEVENT3 0x323 768 | #define CSR_MHPMEVENT4 0x324 769 | #define CSR_MHPMEVENT5 0x325 770 | #define CSR_MHPMEVENT6 0x326 771 | #define CSR_MHPMEVENT7 0x327 772 | #define CSR_MHPMEVENT8 0x328 773 | #define CSR_MHPMEVENT9 0x329 774 | #define CSR_MHPMEVENT10 0x32a 775 | #define CSR_MHPMEVENT11 0x32b 776 | #define CSR_MHPMEVENT12 0x32c 777 | #define CSR_MHPMEVENT13 0x32d 778 | #define CSR_MHPMEVENT14 0x32e 779 | #define CSR_MHPMEVENT15 0x32f 780 | #define CSR_MHPMEVENT16 0x330 781 | #define CSR_MHPMEVENT17 0x331 782 | #define CSR_MHPMEVENT18 0x332 783 | #define CSR_MHPMEVENT19 0x333 784 | #define CSR_MHPMEVENT20 0x334 785 | #define CSR_MHPMEVENT21 0x335 786 | #define CSR_MHPMEVENT22 0x336 787 | #define CSR_MHPMEVENT23 0x337 788 | #define CSR_MHPMEVENT24 0x338 789 | #define CSR_MHPMEVENT25 0x339 790 | #define CSR_MHPMEVENT26 0x33a 791 | #define CSR_MHPMEVENT27 0x33b 792 | #define CSR_MHPMEVENT28 0x33c 793 | #define CSR_MHPMEVENT29 0x33d 794 | #define CSR_MHPMEVENT30 0x33e 795 | #define CSR_MHPMEVENT31 0x33f 796 | #define CSR_MVENDORID 0xf11 797 | #define CSR_MARCHID 0xf12 798 | #define CSR_MIMPID 0xf13 799 | #define CSR_MHARTID 0xf14 800 | #define CSR_CYCLEH 0xc80 801 | #define CSR_TIMEH 0xc81 802 | #define CSR_INSTRETH 0xc82 803 | #define CSR_HPMCOUNTER3H 0xc83 804 | #define CSR_HPMCOUNTER4H 0xc84 805 | #define CSR_HPMCOUNTER5H 0xc85 806 | #define CSR_HPMCOUNTER6H 0xc86 807 | #define CSR_HPMCOUNTER7H 0xc87 808 | #define CSR_HPMCOUNTER8H 0xc88 809 | #define CSR_HPMCOUNTER9H 0xc89 810 | #define CSR_HPMCOUNTER10H 0xc8a 811 | #define CSR_HPMCOUNTER11H 0xc8b 812 | #define CSR_HPMCOUNTER12H 0xc8c 813 | #define CSR_HPMCOUNTER13H 0xc8d 814 | #define CSR_HPMCOUNTER14H 0xc8e 815 | #define CSR_HPMCOUNTER15H 0xc8f 816 | #define CSR_HPMCOUNTER16H 0xc90 817 | #define CSR_HPMCOUNTER17H 0xc91 818 | #define CSR_HPMCOUNTER18H 0xc92 819 | #define CSR_HPMCOUNTER19H 0xc93 820 | #define CSR_HPMCOUNTER20H 0xc94 821 | #define CSR_HPMCOUNTER21H 0xc95 822 | #define CSR_HPMCOUNTER22H 0xc96 823 | #define CSR_HPMCOUNTER23H 0xc97 824 | #define CSR_HPMCOUNTER24H 0xc98 825 | #define CSR_HPMCOUNTER25H 0xc99 826 | #define CSR_HPMCOUNTER26H 0xc9a 827 | #define CSR_HPMCOUNTER27H 0xc9b 828 | #define CSR_HPMCOUNTER28H 0xc9c 829 | #define CSR_HPMCOUNTER29H 0xc9d 830 | #define CSR_HPMCOUNTER30H 0xc9e 831 | #define CSR_HPMCOUNTER31H 0xc9f 832 | #define CSR_MCYCLEH 0xb80 833 | #define CSR_MINSTRETH 0xb82 834 | #define CSR_MHPMCOUNTER3H 0xb83 835 | #define CSR_MHPMCOUNTER4H 0xb84 836 | #define CSR_MHPMCOUNTER5H 0xb85 837 | #define CSR_MHPMCOUNTER6H 0xb86 838 | #define CSR_MHPMCOUNTER7H 0xb87 839 | #define CSR_MHPMCOUNTER8H 0xb88 840 | #define CSR_MHPMCOUNTER9H 0xb89 841 | #define CSR_MHPMCOUNTER10H 0xb8a 842 | #define CSR_MHPMCOUNTER11H 0xb8b 843 | #define CSR_MHPMCOUNTER12H 0xb8c 844 | #define CSR_MHPMCOUNTER13H 0xb8d 845 | #define CSR_MHPMCOUNTER14H 0xb8e 846 | #define CSR_MHPMCOUNTER15H 0xb8f 847 | #define CSR_MHPMCOUNTER16H 0xb90 848 | #define CSR_MHPMCOUNTER17H 0xb91 849 | #define CSR_MHPMCOUNTER18H 0xb92 850 | #define CSR_MHPMCOUNTER19H 0xb93 851 | #define CSR_MHPMCOUNTER20H 0xb94 852 | #define CSR_MHPMCOUNTER21H 0xb95 853 | #define CSR_MHPMCOUNTER22H 0xb96 854 | #define CSR_MHPMCOUNTER23H 0xb97 855 | #define CSR_MHPMCOUNTER24H 0xb98 856 | #define CSR_MHPMCOUNTER25H 0xb99 857 | #define CSR_MHPMCOUNTER26H 0xb9a 858 | #define CSR_MHPMCOUNTER27H 0xb9b 859 | #define CSR_MHPMCOUNTER28H 0xb9c 860 | #define CSR_MHPMCOUNTER29H 0xb9d 861 | #define CSR_MHPMCOUNTER30H 0xb9e 862 | #define CSR_MHPMCOUNTER31H 0xb9f 863 | #define CAUSE_MISALIGNED_FETCH 0x0 864 | #define CAUSE_FAULT_FETCH 0x1 865 | #define CAUSE_ILLEGAL_INSTRUCTION 0x2 866 | #define CAUSE_BREAKPOINT 0x3 867 | #define CAUSE_MISALIGNED_LOAD 0x4 868 | #define CAUSE_FAULT_LOAD 0x5 869 | #define CAUSE_MISALIGNED_STORE 0x6 870 | #define CAUSE_FAULT_STORE 0x7 871 | #define CAUSE_USER_ECALL 0x8 872 | #define CAUSE_SUPERVISOR_ECALL 0x9 873 | #define CAUSE_HYPERVISOR_ECALL 0xa 874 | #define CAUSE_MACHINE_ECALL 0xb 875 | #endif 876 | #ifdef DECLARE_INSN 877 | DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 878 | DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 879 | DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 880 | DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 881 | DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 882 | DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 883 | DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 884 | DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 885 | DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 886 | DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 887 | DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 888 | DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 889 | DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 890 | DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 891 | DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 892 | DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 893 | DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 894 | DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 895 | DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 896 | DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 897 | DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 898 | DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 899 | DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 900 | DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 901 | DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 902 | DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 903 | DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 904 | DECLARE_INSN(or, MATCH_OR, MASK_OR) 905 | DECLARE_INSN(and, MATCH_AND, MASK_AND) 906 | DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 907 | DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 908 | DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 909 | DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 910 | DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 911 | DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 912 | DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 913 | DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 914 | DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 915 | DECLARE_INSN(lb, MATCH_LB, MASK_LB) 916 | DECLARE_INSN(lh, MATCH_LH, MASK_LH) 917 | DECLARE_INSN(lw, MATCH_LW, MASK_LW) 918 | DECLARE_INSN(ld, MATCH_LD, MASK_LD) 919 | DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 920 | DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 921 | DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 922 | DECLARE_INSN(sb, MATCH_SB, MASK_SB) 923 | DECLARE_INSN(sh, MATCH_SH, MASK_SH) 924 | DECLARE_INSN(sw, MATCH_SW, MASK_SW) 925 | DECLARE_INSN(sd, MATCH_SD, MASK_SD) 926 | DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 927 | DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 928 | DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 929 | DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 930 | DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 931 | DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 932 | DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 933 | DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 934 | DECLARE_INSN(rem, MATCH_REM, MASK_REM) 935 | DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 936 | DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 937 | DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 938 | DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 939 | DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 940 | DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 941 | DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 942 | DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 943 | DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 944 | DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 945 | DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 946 | DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 947 | DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 948 | DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 949 | DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 950 | DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 951 | DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 952 | DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 953 | DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 954 | DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 955 | DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 956 | DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 957 | DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 958 | DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 959 | DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 960 | DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 961 | DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 962 | DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 963 | DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 964 | DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 965 | DECLARE_INSN(uret, MATCH_URET, MASK_URET) 966 | DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 967 | DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) 968 | DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 969 | DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 970 | DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) 971 | DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 972 | DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 973 | DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 974 | DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 975 | DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 976 | DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 977 | DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 978 | DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 979 | DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 980 | DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 981 | DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 982 | DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 983 | DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 984 | DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 985 | DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 986 | DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 987 | DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 988 | DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 989 | DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 990 | DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 991 | DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 992 | DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 993 | DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 994 | DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 995 | DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 996 | DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 997 | DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 998 | DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 999 | DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 1000 | DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 1001 | DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 1002 | DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 1003 | DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 1004 | DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 1005 | DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 1006 | DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 1007 | DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 1008 | DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 1009 | DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 1010 | DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) 1011 | DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 1012 | DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 1013 | DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 1014 | DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 1015 | DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 1016 | DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 1017 | DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 1018 | DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 1019 | DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 1020 | DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 1021 | DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 1022 | DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) 1023 | DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 1024 | DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 1025 | DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 1026 | DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 1027 | DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 1028 | DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 1029 | DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 1030 | DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 1031 | DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 1032 | DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 1033 | DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 1034 | DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 1035 | DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 1036 | DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 1037 | DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 1038 | DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 1039 | DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 1040 | DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 1041 | DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 1042 | DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 1043 | DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 1044 | DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 1045 | DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 1046 | DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 1047 | DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 1048 | DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 1049 | DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 1050 | DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 1051 | DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 1052 | DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 1053 | DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 1054 | DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 1055 | DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 1056 | DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 1057 | DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 1058 | DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 1059 | DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 1060 | DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 1061 | DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 1062 | DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 1063 | DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 1064 | DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 1065 | DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 1066 | DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 1067 | DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 1068 | DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 1069 | DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 1070 | DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 1071 | DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 1072 | DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 1073 | DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 1074 | DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 1075 | DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 1076 | DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 1077 | DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 1078 | DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 1079 | DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 1080 | DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 1081 | DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 1082 | DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 1083 | DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 1084 | DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 1085 | DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 1086 | DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 1087 | DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) 1088 | DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 1089 | DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 1090 | DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 1091 | DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 1092 | DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 1093 | DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) 1094 | DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 1095 | DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 1096 | DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 1097 | DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 1098 | DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 1099 | DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) 1100 | DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 1101 | DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 1102 | DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 1103 | DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 1104 | DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 1105 | DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) 1106 | #endif 1107 | #ifdef DECLARE_CSR 1108 | DECLARE_CSR(fflags, CSR_FFLAGS) 1109 | DECLARE_CSR(frm, CSR_FRM) 1110 | DECLARE_CSR(fcsr, CSR_FCSR) 1111 | DECLARE_CSR(cycle, CSR_CYCLE) 1112 | DECLARE_CSR(time, CSR_TIME) 1113 | DECLARE_CSR(instret, CSR_INSTRET) 1114 | DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) 1115 | DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) 1116 | DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) 1117 | DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) 1118 | DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) 1119 | DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) 1120 | DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) 1121 | DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) 1122 | DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) 1123 | DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) 1124 | DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) 1125 | DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) 1126 | DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) 1127 | DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) 1128 | DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) 1129 | DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) 1130 | DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) 1131 | DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) 1132 | DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) 1133 | DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) 1134 | DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) 1135 | DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) 1136 | DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) 1137 | DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) 1138 | DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) 1139 | DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) 1140 | DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) 1141 | DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) 1142 | DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) 1143 | DECLARE_CSR(sstatus, CSR_SSTATUS) 1144 | DECLARE_CSR(sie, CSR_SIE) 1145 | DECLARE_CSR(stvec, CSR_STVEC) 1146 | DECLARE_CSR(sscratch, CSR_SSCRATCH) 1147 | DECLARE_CSR(sepc, CSR_SEPC) 1148 | DECLARE_CSR(scause, CSR_SCAUSE) 1149 | DECLARE_CSR(sbadaddr, CSR_SBADADDR) 1150 | DECLARE_CSR(sip, CSR_SIP) 1151 | DECLARE_CSR(sptbr, CSR_SPTBR) 1152 | DECLARE_CSR(mstatus, CSR_MSTATUS) 1153 | DECLARE_CSR(misa, CSR_MISA) 1154 | DECLARE_CSR(medeleg, CSR_MEDELEG) 1155 | DECLARE_CSR(mideleg, CSR_MIDELEG) 1156 | DECLARE_CSR(mie, CSR_MIE) 1157 | DECLARE_CSR(mtvec, CSR_MTVEC) 1158 | DECLARE_CSR(mscratch, CSR_MSCRATCH) 1159 | DECLARE_CSR(mepc, CSR_MEPC) 1160 | DECLARE_CSR(mcause, CSR_MCAUSE) 1161 | DECLARE_CSR(mbadaddr, CSR_MBADADDR) 1162 | DECLARE_CSR(mip, CSR_MIP) 1163 | DECLARE_CSR(tselect, CSR_TSELECT) 1164 | DECLARE_CSR(tdata1, CSR_TDATA1) 1165 | DECLARE_CSR(tdata2, CSR_TDATA2) 1166 | DECLARE_CSR(tdata3, CSR_TDATA3) 1167 | DECLARE_CSR(dcsr, CSR_DCSR) 1168 | DECLARE_CSR(dpc, CSR_DPC) 1169 | DECLARE_CSR(dscratch, CSR_DSCRATCH) 1170 | DECLARE_CSR(mcycle, CSR_MCYCLE) 1171 | DECLARE_CSR(minstret, CSR_MINSTRET) 1172 | DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) 1173 | DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) 1174 | DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) 1175 | DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) 1176 | DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) 1177 | DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) 1178 | DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) 1179 | DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) 1180 | DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) 1181 | DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) 1182 | DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) 1183 | DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) 1184 | DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) 1185 | DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) 1186 | DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) 1187 | DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) 1188 | DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) 1189 | DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) 1190 | DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) 1191 | DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) 1192 | DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) 1193 | DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) 1194 | DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) 1195 | DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) 1196 | DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) 1197 | DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) 1198 | DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) 1199 | DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) 1200 | DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) 1201 | DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) 1202 | DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) 1203 | DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) 1204 | DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) 1205 | DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) 1206 | DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) 1207 | DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) 1208 | DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) 1209 | DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) 1210 | DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) 1211 | DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) 1212 | DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) 1213 | DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) 1214 | DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) 1215 | DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) 1216 | DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) 1217 | DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) 1218 | DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) 1219 | DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) 1220 | DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) 1221 | DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) 1222 | DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) 1223 | DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) 1224 | DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) 1225 | DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) 1226 | DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) 1227 | DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) 1228 | DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) 1229 | DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) 1230 | DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) 1231 | DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) 1232 | DECLARE_CSR(mvendorid, CSR_MVENDORID) 1233 | DECLARE_CSR(marchid, CSR_MARCHID) 1234 | DECLARE_CSR(mimpid, CSR_MIMPID) 1235 | DECLARE_CSR(mhartid, CSR_MHARTID) 1236 | DECLARE_CSR(cycleh, CSR_CYCLEH) 1237 | DECLARE_CSR(timeh, CSR_TIMEH) 1238 | DECLARE_CSR(instreth, CSR_INSTRETH) 1239 | DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) 1240 | DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) 1241 | DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) 1242 | DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) 1243 | DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) 1244 | DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) 1245 | DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) 1246 | DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) 1247 | DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) 1248 | DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) 1249 | DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) 1250 | DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) 1251 | DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) 1252 | DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) 1253 | DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) 1254 | DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) 1255 | DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) 1256 | DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) 1257 | DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) 1258 | DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) 1259 | DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) 1260 | DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) 1261 | DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) 1262 | DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) 1263 | DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) 1264 | DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) 1265 | DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) 1266 | DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) 1267 | DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) 1268 | DECLARE_CSR(mcycleh, CSR_MCYCLEH) 1269 | DECLARE_CSR(minstreth, CSR_MINSTRETH) 1270 | DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) 1271 | DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) 1272 | DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) 1273 | DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) 1274 | DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) 1275 | DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) 1276 | DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) 1277 | DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) 1278 | DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) 1279 | DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) 1280 | DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) 1281 | DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) 1282 | DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) 1283 | DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) 1284 | DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) 1285 | DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) 1286 | DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) 1287 | DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) 1288 | DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) 1289 | DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) 1290 | DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) 1291 | DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) 1292 | DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) 1293 | DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) 1294 | DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) 1295 | DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) 1296 | DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) 1297 | DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) 1298 | DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) 1299 | #endif 1300 | #ifdef DECLARE_CAUSE 1301 | DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) 1302 | DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) 1303 | DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) 1304 | DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) 1305 | DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) 1306 | DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) 1307 | DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) 1308 | DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) 1309 | DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) 1310 | DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) 1311 | DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) 1312 | DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) 1313 | #endif 1314 | -------------------------------------------------------------------------------- /software/tests/src/rocc.h: -------------------------------------------------------------------------------- 1 | // Based on code by Schuyler Eldridge. Copyright (c) Boston University 2 | // https://github.com/seldridge/rocket-rocc-examples/blob/master/src/main/c/rocc.h 3 | 4 | #ifndef SRC_MAIN_C_ROCC_H 5 | #define SRC_MAIN_C_ROCC_H 6 | 7 | // Standard macro that passes rd, rs1, and rs2 via registers 8 | #define ROCC_INSTRUCTION_DSS(X, rd, rs1, rs2, funct) \ 9 | ROCC_INSTRUCTION_R_R_R(X, rd, rs1, rs2, funct) 10 | 11 | #define ROCC_INSTRUCTION_DS(X, rd, rs1, funct) \ 12 | ROCC_INSTRUCTION_R_R_I(X, rd, rs1, 0, funct) 13 | 14 | #define ROCC_INSTRUCTION_D(X, rd, funct) \ 15 | ROCC_INSTRUCTION_R_I_I(X, rd, 0, 0, funct) 16 | 17 | #define ROCC_INSTRUCTION_SS(X, rs1, rs2, funct) \ 18 | ROCC_INSTRUCTION_I_R_R(X, 0, rs1, rs2, funct) 19 | 20 | #define ROCC_INSTRUCTION_S(X, rs1, funct) \ 21 | ROCC_INSTRUCTION_I_R_I(X, 0, rs1, 0, funct) 22 | 23 | #define ROCC_INSTRUCTION(X, funct) \ 24 | ROCC_INSTRUCTION_I_I_I(X, 0, 0, 0, funct) 25 | 26 | // funct3 flags 27 | #define ROCC_XD 0x4 28 | #define ROCC_XS1 0x2 29 | #define ROCC_XS2 0x1 30 | 31 | // rd must be an lvalue if used as a register. 32 | // These macros do not insert a compiler memory barrier. 33 | 34 | #define ROCC_INSTRUCTION_R_R_R(X, rd, rs1, rs2, funct) \ 35 | do { \ 36 | __asm__ __volatile__ ( \ 37 | ".insn r CUSTOM_" #X ", %3, %4, %0, %1, %2\n\t" \ 38 | : "=r" (rd) \ 39 | : "r" (rs1), "r" (rs2), \ 40 | "i" (ROCC_XD | ROCC_XS1 | ROCC_XS2), "i" (funct)); \ 41 | } while (0) 42 | 43 | #define ROCC_INSTRUCTION_R_R_I(X, rd, rs1, rs2, funct) \ 44 | do { \ 45 | __asm__ __volatile__ ( \ 46 | ".insn r CUSTOM_" #X ", %3, %4, %0, %1, x%2\n\t" \ 47 | : "=r" (rd) \ 48 | : "r" (rs1), "K" (rs2), \ 49 | "i" (ROCC_XD | ROCC_XS1), "i" (funct)); \ 50 | } while (0) 51 | 52 | #define ROCC_INSTRUCTION_R_I_I(X, rd, rs1, rs2, funct) \ 53 | do { \ 54 | __asm__ __volatile__ ( \ 55 | ".insn r CUSTOM_" #X ", %3, %4, %0, x%1, x%2\n\t" \ 56 | : "=r" (rd) \ 57 | : "K" (rs1), "K" (rs2), \ 58 | "i" (ROCC_XD), "i" (funct)); \ 59 | } while (0) 60 | 61 | #define ROCC_INSTRUCTION_I_R_R(X, rd, rs1, rs2, funct) \ 62 | do { \ 63 | __asm__ __volatile__ ( \ 64 | ".insn r CUSTOM_" #X ", %3, %4, x%0, %1, %2\n\t" \ 65 | : \ 66 | : "K" (rd), "r" (rs1), "r" (rs2), \ 67 | "i" (ROCC_XS1 | ROCC_XS2), "i" (funct)); \ 68 | } while (0) 69 | 70 | #define ROCC_INSTRUCTION_I_R_I(X, rd, rs1, rs2, funct) \ 71 | do { \ 72 | __asm__ __volatile__ ( \ 73 | ".insn r CUSTOM_" #X ", %3, %4, x%0, %1, x%2\n\t" \ 74 | : \ 75 | : "K" (rd), "r" (rs1), "K" (rs2), \ 76 | "i" (ROCC_XS1), "i" (funct)); \ 77 | } while (0) 78 | 79 | #define ROCC_INSTRUCTION_I_I_I(X, rd, rs1, rs2, funct) \ 80 | do { \ 81 | __asm__ __volatile__ ( \ 82 | ".insn r CUSTOM_" #X ", %3, %4, x%0, x%1, x%2\n\t" \ 83 | : \ 84 | : "K" (rd), "K" (rs1), "K" (rs2), \ 85 | "i" (0), "i" (funct)); \ 86 | } while (0) 87 | 88 | #endif // SRC_MAIN_C_ROCC_H 89 | -------------------------------------------------------------------------------- /software/tests/src/sha3-rocc.c: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | // The following is a RISC-V program to test the functionality of the 3 | // sha3 RoCC accelerator. 4 | // Compile with riscv-gcc sha3-rocc.c 5 | // Run with spike --extension=sha3 pk a.out 6 | 7 | #include 8 | #include 9 | #include "rocc.h" 10 | #include "sha3.h" 11 | #include "encoding.h" 12 | #include "compiler.h" 13 | 14 | #ifdef __linux 15 | #include 16 | #endif 17 | 18 | int main() { 19 | 20 | unsigned long start, end; 21 | 22 | #ifdef __linux 23 | // Ensure all pages are resident to avoid accelerator page faults 24 | if (mlockall(MCL_CURRENT | MCL_FUTURE)) { 25 | perror("mlockall"); 26 | return 1; 27 | } 28 | #endif 29 | 30 | do { 31 | printf("Start basic test 1.\n"); 32 | // BASIC TEST 1 - 150 zero bytes 33 | 34 | // Setup some test data 35 | static unsigned char input[150] __aligned(8) = { '\0' }; 36 | unsigned char output[SHA3_256_DIGEST_SIZE] __aligned(8); 37 | 38 | start = rdcycle(); 39 | 40 | // Compute hash with accelerator 41 | asm volatile ("fence"); 42 | // Invoke the acclerator and check responses 43 | 44 | // setup accelerator with addresses of input and output 45 | // opcode rd rs1 rs2 funct 46 | /* asm volatile ("custom2 x0, %[msg_addr], %[hash_addr], 0" : : [msg_addr]"r"(&input), [hash_addr]"r"(&output)); */ 47 | ROCC_INSTRUCTION_SS(2, &input, &output, 0); 48 | 49 | // Set length and compute hash 50 | // opcode rd rs1 rs2 funct 51 | /* asm volatile ("custom2 x0, %[length], x0, 1" : : [length]"r"(ilen)); */ 52 | ROCC_INSTRUCTION_S(2, sizeof(input), 1); 53 | asm volatile ("fence" ::: "memory"); 54 | 55 | end = rdcycle(); 56 | 57 | // Check result 58 | int i; 59 | static const unsigned char result[SHA3_256_DIGEST_SIZE] = 60 | #ifdef KECCAK 61 | {221,204,157,217,67,211,86,31,54,168,44,245,97,194,193,26,234,42,135,166,66,134,39,174,184,61,3,149,137,42,57,238}; 62 | #else /* FIPS 202 */ 63 | {203,52,27,85,46,79,152,228,86,138,201,206,253,168,255,107,122,177,65,68,231,19,70,198,64,90,192,80,206,234,168,159}; 64 | #endif 65 | //sha3ONE(input, sizeof(input), result); 66 | for(i = 0; i < SHA3_256_DIGEST_SIZE; i++){ 67 | printf("output[%d]:%d ==? results[%d]:%d \n",i,output[i],i,result[i]); 68 | if(output[i] != result[i]) { 69 | printf("Failed: Outputs don't match!\n"); 70 | printf("SHA execution took %lu cycles\n", end - start); 71 | return 1; 72 | } 73 | } 74 | } while(0); 75 | 76 | printf("Success!\n"); 77 | 78 | printf("SHA execution took %lu cycles\n", end - start); 79 | 80 | return 0; 81 | } 82 | -------------------------------------------------------------------------------- /software/tests/src/sha3-sw.c: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | // The following is a RISC-V program to test the functionality of the 3 | // sha3 RoCC accelerator. 4 | // Compile with riscv-gcc sha3-rocc.c 5 | // Run with spike --extension=sha3 pk a.out 6 | 7 | #include 8 | #include 9 | #include "sha3.h" 10 | #include "encoding.h" 11 | #include "compiler.h" 12 | 13 | int main() { 14 | 15 | unsigned long start, end; 16 | 17 | do { 18 | printf("Start basic test 1.\n"); 19 | // BASIC TEST 1 - 150 zero bytes 20 | 21 | // Setup some test data 22 | static unsigned char input[150] __aligned(8) = { '\0' }; 23 | unsigned char output[SHA3_256_DIGEST_SIZE] __aligned(8); 24 | 25 | start = rdcycle(); 26 | 27 | // Compute hash in SW 28 | sha3ONE(input, sizeof(input), output); 29 | 30 | end = rdcycle(); 31 | 32 | // Check result 33 | int i; 34 | static const unsigned char result[SHA3_256_DIGEST_SIZE] = 35 | #ifdef KECCAK 36 | {221,204,157,217,67,211,86,31,54,168,44,245,97,194,193,26,234,42,135,166,66,134,39,174,184,61,3,149,137,42,57,238}; 37 | #else /* FIPS 202 */ 38 | {203,52,27,85,46,79,152,228,86,138,201,206,253,168,255,107,122,177,65,68,231,19,70,198,64,90,192,80,206,234,168,159}; 39 | #endif 40 | //sha3ONE(input, sizeof(input), result); 41 | for(i = 0; i < SHA3_256_DIGEST_SIZE; i++){ 42 | printf("output[%d]:%d ==? results[%d]:%d \n",i,output[i],i,result[i]); 43 | if(output[i] != result[i]) { 44 | printf("Failed: Outputs don't match!\n"); 45 | printf("SHA execution took %lu cycles\n", end - start); 46 | return 1; 47 | } 48 | } 49 | 50 | } while(0); 51 | 52 | printf("Success!\n"); 53 | 54 | printf("SHA execution took %lu cycles\n", end - start); 55 | 56 | return 0; 57 | } 58 | -------------------------------------------------------------------------------- /software/tests/src/sha3.h: -------------------------------------------------------------------------------- 1 | // Define reference (software) sha3 2 | 3 | #ifndef __SHA3_H 4 | #define __SHA3_H 5 | 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | #define SHA3_224_DIGEST_SIZE (224 / 8) 12 | #define SHA3_224_BLOCK_SIZE (200 - 2 * SHA3_224_DIGEST_SIZE) 13 | 14 | #define SHA3_256_DIGEST_SIZE (256 / 8) 15 | #define SHA3_256_BLOCK_SIZE (200 - 2 * SHA3_256_DIGEST_SIZE) 16 | 17 | #define SHA3_384_DIGEST_SIZE (384 / 8) 18 | #define SHA3_384_BLOCK_SIZE (200 - 2 * SHA3_384_DIGEST_SIZE) 19 | 20 | #define SHA3_512_DIGEST_SIZE (512 / 8) 21 | #define SHA3_512_BLOCK_SIZE (200 - 2 * SHA3_512_DIGEST_SIZE) 22 | 23 | #define SHA3_DEFAULT_BLOCK_SIZE SHA3_256_BLOCK_SIZE 24 | #define SHA3_DEFAULT_DIGEST_SIZE SHA3_256_DIGEST_SIZE 25 | 26 | int sha3ONE(unsigned char *, unsigned int, unsigned char *); 27 | 28 | typedef struct { 29 | uint64_t st[25]; 30 | unsigned int md_len; 31 | unsigned int rsiz; 32 | unsigned int rsizw; 33 | 34 | unsigned int partial; 35 | uint8_t buf[SHA3_DEFAULT_BLOCK_SIZE]; 36 | } sha3_state; 37 | 38 | void sha3_init(sha3_state *sctx); 39 | void sha3_update(sha3_state *sctx, const uint8_t *data, unsigned int len); 40 | void sha3_final(sha3_state *sctx, uint8_t *out); 41 | 42 | void hash_init_sha3(void * ctx); 43 | void hash_update_sha3(void * ctx, const uint8_t * input, size_t length); 44 | void hash_final_sha3(void * ctx, unsigned char * digest); 45 | 46 | #define KECCAK_ROUNDS 24 47 | 48 | #define ROTL64(x, y) (((x) << (y)) | ((x) >> (64 - (y)))) 49 | 50 | static const uint64_t keccakf_rndc[24] = 51 | { 52 | 0x0000000000000001, 0x0000000000008082, 0x800000000000808a, 53 | 0x8000000080008000, 0x000000000000808b, 0x0000000080000001, 54 | 0x8000000080008081, 0x8000000000008009, 0x000000000000008a, 55 | 0x0000000000000088, 0x0000000080008009, 0x000000008000000a, 56 | 0x000000008000808b, 0x800000000000008b, 0x8000000000008089, 57 | 0x8000000000008003, 0x8000000000008002, 0x8000000000000080, 58 | 0x000000000000800a, 0x800000008000000a, 0x8000000080008081, 59 | 0x8000000000008080, 0x0000000080000001, 0x8000000080008008 60 | }; 61 | 62 | static const int keccakf_rotc[24] = 63 | { 64 | 1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14, 65 | 27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44 66 | }; 67 | 68 | static const int keccakf_piln[24] = 69 | { 70 | 10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4, 71 | 15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1 72 | }; 73 | 74 | void hash_init_sha3(void * ctx) 75 | { 76 | sha3_init((sha3_state *)ctx); 77 | } 78 | 79 | void hash_update_sha3(void * ctx, const uint8_t * input, size_t length) 80 | { 81 | sha3_update((sha3_state *)ctx, input, length); 82 | } 83 | 84 | void hash_final_sha3(void * ctx, unsigned char * digest) 85 | { 86 | sha3_final((sha3_state *)ctx, digest); 87 | } 88 | 89 | void printState(uint64_t st[25]) 90 | { 91 | int i,j; 92 | for(i = 0; i<5; i++){ 93 | for(j = 0; j<5; j++){ 94 | printf("%016" PRIx64, st[i+j*5]); 95 | } 96 | printf("\n"); 97 | } 98 | printf("\n"); 99 | } 100 | 101 | // update the state with given number of rounds 102 | static void keccakf(uint64_t st[25], int rounds) 103 | { 104 | int i, j, round_num; 105 | uint64_t t, bc[5]; 106 | 107 | //printf("Starting\n"); 108 | //printState(st); 109 | for (round_num = 0; round_num < rounds; round_num++) 110 | { 111 | // Theta 112 | for (i = 0; i < 5; i++) 113 | bc[i] = st[i] ^ st[i + 5] ^ st[i + 10] ^ st[i + 15] ^ st[i + 20]; 114 | 115 | for (i = 0; i < 5; i++) 116 | { 117 | t = bc[(i + 4) % 5] ^ ROTL64(bc[(i + 1) % 5], 1); 118 | for (j = 0; j < 25; j += 5) 119 | st[j + i] ^= t; 120 | } 121 | 122 | //printf("After Theta:\n"); 123 | //printState(st); 124 | // Rho Pi 125 | t = st[1]; 126 | for (i = 0; i < 24; i++) 127 | { 128 | j = keccakf_piln[i]; 129 | bc[0] = st[j]; 130 | st[j] = ROTL64(t, keccakf_rotc[i]); 131 | t = bc[0]; 132 | } 133 | //printf("After RhoPi:\n"); 134 | //printState(st); 135 | 136 | // Chi 137 | for (j = 0; j < 25; j += 5) 138 | { 139 | for (i = 0; i < 5; i++) 140 | bc[i] = st[j + i]; 141 | for (i = 0; i < 5; i++) 142 | st[j + i] ^= (~bc[(i + 1) % 5]) & bc[(i + 2) % 5]; 143 | } 144 | 145 | //printf("After Chi:\n"); 146 | //printState(st); 147 | // Iota 148 | st[0] ^= keccakf_rndc[round_num]; 149 | //printf("After Round %d:\n",round_num); 150 | //printState(st); 151 | } 152 | } 153 | 154 | void sha3_init(sha3_state *sctx) 155 | { 156 | memset(sctx, 0, sizeof(*sctx)); 157 | sctx->md_len = SHA3_DEFAULT_DIGEST_SIZE; 158 | sctx->rsiz = 200 - 2 * SHA3_DEFAULT_DIGEST_SIZE; 159 | sctx->rsizw = sctx->rsiz / 8; 160 | } 161 | 162 | int sha3ONE(unsigned char *message, unsigned int len, unsigned char *digest) 163 | { 164 | sha3_state sctx; 165 | sha3_init(&sctx); 166 | sha3_update(&sctx, message, len); 167 | sha3_final(&sctx, digest); 168 | return 0; 169 | } 170 | 171 | void sha3_update(sha3_state *sctx, const uint8_t *data, unsigned int len) 172 | { 173 | unsigned int done; 174 | const uint8_t *src; 175 | 176 | done = 0; 177 | src = data; 178 | 179 | if ((sctx->partial + len) > (sctx->rsiz - 1)) 180 | { 181 | if (sctx->partial) 182 | { 183 | done = -sctx->partial; 184 | memcpy(sctx->buf + sctx->partial, data, 185 | done + sctx->rsiz); 186 | src = sctx->buf; 187 | } 188 | 189 | do { 190 | unsigned int i; 191 | 192 | for (i = 0; i < sctx->rsizw; i++) 193 | sctx->st[i] ^= ((uint64_t *) src)[i]; 194 | keccakf(sctx->st, KECCAK_ROUNDS); 195 | 196 | done += sctx->rsiz; 197 | src = data + done; 198 | } while (done + (sctx->rsiz - 1) < len); 199 | 200 | sctx->partial = 0; 201 | } 202 | memcpy(sctx->buf + sctx->partial, src, len - done); 203 | sctx->partial += (len - done); 204 | } 205 | 206 | 207 | void sha3_final(sha3_state *sctx, uint8_t *out) 208 | { 209 | unsigned int i, inlen = sctx->partial; 210 | 211 | #ifdef KECCAK 212 | #define PAD 0x1 213 | #else /* FIPS 202 */ 214 | #define PAD 0x6 215 | #endif 216 | 217 | sctx->buf[inlen++] = PAD; 218 | memset(sctx->buf + inlen, 0, sctx->rsiz - inlen); 219 | sctx->buf[sctx->rsiz - 1] |= 0x80; 220 | 221 | for (i = 0; i < sctx->rsizw; i++) 222 | sctx->st[i] ^= ((uint64_t *) sctx->buf)[i]; 223 | 224 | keccakf(sctx->st, KECCAK_ROUNDS); 225 | 226 | // RBF - On big endian systems, we may need to reverse the bit order here 227 | // RBF - CONVERT FROM CPU TO LE64 228 | /* 229 | for (i = 0; i < sctx->rsizw; i++) 230 | sctx->st[i] = cpu_to_le64(sctx->st[i]); 231 | */ 232 | memcpy(out, sctx->st, sctx->md_len); 233 | 234 | memset(sctx, 0, sizeof(*sctx)); 235 | } 236 | #endif 237 | -------------------------------------------------------------------------------- /src/main/scala/chi.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | //import chiseltest.iotesters.PeekPokeTester 7 | import scala.collection.mutable.HashMap 8 | import scala.collection.mutable.ArrayBuffer 9 | import scala.util.Random 10 | 11 | class ChiModule(val W: Int = 64) extends Module { 12 | //val W = 64 13 | val io = new Bundle { 14 | val state_i = Vec(5*5, Bits(INPUT,W)) 15 | val state_o = Vec(5*5, Bits(OUTPUT,W)) 16 | } 17 | 18 | //TODO: c code uses falttened rep for this 19 | for(i <- 0 until 5) { 20 | for(j <- 0 until 5) { 21 | io.state_o(i*5+j) := io.state_i(i*5+j) ^ 22 | ( (~io.state_i(((i+1)%5)*5+((j)%5))) & io.state_i(((i+2)%5)*5+((j)%5))) 23 | } 24 | } 25 | } 26 | 27 | // class ChiModuleTests(c: ChiModule) extends PeekPokeTester(c) { 28 | // var allGood = true 29 | // val rand = new Random(1) 30 | // val W = 4 31 | // val maxInt = 1 << (5*5*W) 32 | // for (i <- 0 until 1) { 33 | // val state = Array.fill(5*5){BigInt(rand.nextInt(1 < Module(new ChiModule())){c => new ChiModuleTests(c) 52 | } 53 | } 54 | } 55 | */ 56 | -------------------------------------------------------------------------------- /src/main/scala/common.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | import scala.util.Random 7 | 8 | class SHA3_State extends Bundle { 9 | val words = Vec.fill(5){ Vec.fill(5) { Bits(width = 64) }} 10 | } 11 | 12 | object common { 13 | val rand = new Random(2013) 14 | //def generate_random_bigint() = BigInt(rand.nextLong()) + (BigInt(1) << 63) 15 | def generate_random_bigint(size: Int) : BigInt = BigInt(rand.nextLong()) + (BigInt(1) << (size-1)) 16 | def generate_random_int(size: Int) = math.abs(rand.nextInt()) % (1 << size) //128 17 | def generate_test_matrix(size: Int) = Array.fill(5*5)(generate_random_int(size)) 18 | def print_matrix(testmatrix: Array[Int]) = { 19 | (0 until 5).foreach(row => println((0 until 5).toArray.map(col => "%016x".format(testmatrix(row*5+col))).reduce(_+" "+_))) 20 | } 21 | def print_bigmatrix(testmatrix: Array[BigInt]) = { 22 | (0 until 5).foreach(row => println((0 until 5).toArray.map(col => "%d".format(testmatrix(row*5+col))).reduce(_+" "+_))) 23 | } 24 | def ROTL(x: UInt, y: UInt, W: UInt) = (((x) << (y)) | ((x) >> (W - (y)))) 25 | //def ROTLscala(x: UInt, y: Int, W: Int) = (((x) << (y)) | ((x) >> (W - (y)))) 26 | } 27 | //use with 28 | //val state = new SHA3_State() 29 | //state.words(i)(j)(k) ? not sure if this line works 30 | -------------------------------------------------------------------------------- /src/main/scala/constants.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | 7 | object RHOPI { 8 | 9 | val piln = Array( 10 | 0, 18, 21, 19, 14, 11 | 10, 3, 24, 13, 22, 12 | 7, 5, 4, 12, 9, 13 | 11, 16, 15, 2, 6, 14 | 17, 8, 23, 20, 1 15 | ) 16 | 17 | val tri = Array( 18 | 0, 36, 3, 41, 18, 19 | 1, 44, 10, 45, 2, 20 | 62, 6, 43, 15, 61, 21 | 28, 55, 25, 21, 56, 22 | 27, 20, 39, 8, 14 23 | ) 24 | } 25 | object IOTA { 26 | def round_const = Vec( 27 | Bits("h0000000000000001",64), 28 | Bits("h0000000000008082",64), 29 | Bits("h800000000000808a",64), 30 | Bits("h8000000080008000",64), 31 | Bits("h000000000000808b",64), 32 | Bits("h0000000080000001",64), 33 | Bits("h8000000080008081",64), 34 | Bits("h8000000000008009",64), 35 | Bits("h000000000000008a",64), 36 | Bits("h0000000000000088",64), 37 | Bits("h0000000080008009",64), 38 | Bits("h000000008000000a",64), 39 | Bits("h000000008000808b",64), 40 | Bits("h800000000000008b",64), 41 | Bits("h8000000000008089",64), 42 | Bits("h8000000000008003",64), 43 | Bits("h8000000000008002",64), 44 | Bits("h8000000000000080",64), 45 | Bits("h000000000000800a",64), 46 | Bits("h800000008000000a",64), 47 | Bits("h8000000080008081",64), 48 | Bits("h8000000000008080",64), 49 | Bits("h0000000080000001",64), 50 | Bits("h8000000080008008",64), 51 | Bits("h0000000000000000",64) ) 52 | } 53 | -------------------------------------------------------------------------------- /src/main/scala/ctrl.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | import scala.collection.mutable.HashMap 7 | import scala.collection.mutable.ArrayBuffer 8 | import scala.util.Random 9 | import Chisel.ImplicitConversions._ 10 | import scala.collection.mutable.HashMap 11 | import freechips.rocketchip.tile.HasCoreParameters 12 | import freechips.rocketchip.rocket.constants.MemoryOpConstants 13 | import org.chipsalliance.cde.config._ 14 | 15 | class CtrlModule(val W: Int, val S: Int)(implicit val p: Parameters) extends Module 16 | with HasCoreParameters 17 | with MemoryOpConstants { 18 | val r = 2*256 19 | val c = 25*W - r 20 | val round_size_words = c/W 21 | val rounds = 24 //12 + 2l 22 | val hash_size_words = 256/W 23 | val bytes_per_word = W/8 24 | 25 | val io = new Bundle { 26 | val rocc_req_val = Bool(INPUT) 27 | val rocc_req_rdy = Bool(OUTPUT) 28 | val rocc_funct = Bits(INPUT, 2) 29 | val rocc_rs1 = Bits(INPUT, 64) 30 | val rocc_rs2 = Bits(INPUT, 64) 31 | val rocc_rd = Bits(INPUT, 5) 32 | 33 | val busy = Bool(OUTPUT) 34 | 35 | val dmem_req_val = Bool(OUTPUT) 36 | val dmem_req_rdy = Bool(INPUT) 37 | val dmem_req_tag = Bits(OUTPUT, coreParams.dcacheReqTagBits) 38 | val dmem_req_addr = Bits(OUTPUT, coreMaxAddrBits) 39 | val dmem_req_cmd = Bits(OUTPUT, M_SZ) 40 | val dmem_req_size = Bits(OUTPUT, log2Ceil(coreDataBytes + 1)) 41 | 42 | val dmem_resp_val = Bool(INPUT) 43 | val dmem_resp_tag = Bits(INPUT, 7) 44 | val dmem_resp_data = Bits(INPUT, W) 45 | 46 | val sfence = Bool(OUTPUT) 47 | 48 | //Sha3 Specific signals 49 | val round = UInt(OUTPUT,width=5) 50 | val stage = UInt(OUTPUT,width=log2Up(S)) 51 | val absorb = Bool(OUTPUT) 52 | val aindex = UInt(OUTPUT,width=log2Up(round_size_words)) 53 | val init = Bool(OUTPUT) 54 | val write = Bool(OUTPUT) 55 | val windex = UInt(OUTPUT,width=log2Up(hash_size_words+1)) 56 | 57 | val buffer_out = Bits(OUTPUT,width=W) 58 | } 59 | 60 | //RoCC HANDLER 61 | //rocc pipe state 62 | val r_idle :: r_eat_addr :: r_eat_len :: Nil = Enum(UInt(), 3) 63 | 64 | val msg_addr = Reg(init = UInt(0,64)) 65 | val hash_addr= Reg(init = UInt(0,64)) 66 | val msg_len = Reg(init = UInt(0,64)) 67 | 68 | val busy = Reg(init=Bool(false)) 69 | 70 | val rocc_s = Reg(init=r_idle) 71 | //register inputs 72 | val rocc_req_val_reg = Reg(next=io.rocc_req_val) 73 | val rocc_funct_reg = Reg(init = Bits(0,2)) 74 | rocc_funct_reg := io.rocc_funct 75 | val rocc_rs1_reg = Reg(next=io.rocc_rs1) 76 | val rocc_rs2_reg = Reg(next=io.rocc_rs2) 77 | val rocc_rd_reg = Reg(next=io.rocc_rd) 78 | 79 | val dmem_resp_val_reg = Reg(next=io.dmem_resp_val) 80 | val dmem_resp_tag_reg = Reg(next=io.dmem_resp_tag) 81 | //memory pipe state 82 | val fast_mem = p(Sha3FastMem) 83 | val m_idle :: m_read :: m_wait :: m_pad :: m_absorb :: Nil = Enum(UInt(), 5) 84 | val mem_s = Reg(init=m_idle) 85 | 86 | val buffer_sram = p(Sha3BufferSram) 87 | //SRAM Buffer 88 | val buffer_mem = Mem(round_size_words, UInt(width = W)) 89 | //Flip-Flop buffer 90 | val buffer = Reg(init=Vec.fill(round_size_words) { 0.U(W.W) }) 91 | 92 | val buffer_raddr = Reg(UInt(width = log2Up(round_size_words))) 93 | val buffer_wen = Wire(Bool()); 94 | buffer_wen := Bool(false) //Defaut value 95 | val buffer_waddr = Wire(UInt(width = W)); buffer_waddr := UInt(0) 96 | val buffer_wdata = Wire(UInt(width = W)); buffer_wdata := UInt(0) 97 | val buffer_rdata = Bits(width = W); 98 | if(buffer_sram){ 99 | when(buffer_wen) { buffer_mem.write(buffer_waddr, buffer_wdata) } 100 | buffer_rdata := buffer_mem(buffer_raddr) 101 | } 102 | 103 | //This is used to prevent the pad index from advancing if waiting for the sram to read 104 | //SRAM reads take 1 cycle 105 | val wait_for_sram = Reg(init = Bool(true)) 106 | 107 | val buffer_valid = Reg(init = Bool(false)) 108 | val buffer_count = Reg(init = UInt(0,5)) 109 | val read = Reg(init = UInt(0,32)) 110 | val hashed = Reg(init = UInt(0,32)) 111 | val areg = Reg(init = Bool(false)) 112 | val mindex = Reg(init = UInt(0,5)) 113 | val windex = Reg(init = UInt(0,log2Up(hash_size_words+1))) 114 | val aindex = Reg(init = UInt(0,log2Up(round_size_words))) 115 | val pindex = Reg(init = UInt(0,log2Up(round_size_words))) 116 | val writes_done = Reg( init=Vec.fill(hash_size_words) { Bool(false) }) 117 | val next_buff_val = Reg(init = Bool(false)) 118 | if(fast_mem){ 119 | next_buff_val := (buffer_count >= mindex) && 120 | (pindex >= UInt(round_size_words - 1)) 121 | }else{ 122 | next_buff_val := ((mindex >= UInt(round_size_words)) || 123 | (read >= msg_len)) && 124 | (pindex >= UInt(round_size_words - 1)) 125 | } 126 | 127 | //Note that the output of io.aindex is delayed by 1 cycle 128 | io.aindex := Reg(next = aindex) 129 | io.absorb := areg 130 | areg := Bool(false) 131 | if(buffer_sram){ 132 | //when(areg) { 133 | //Note that the aindex used here is one cycle behind that is passed to the datapath (out of phase) 134 | buffer_raddr := aindex 135 | //}.elsewhen(mem_s === m_pad){ 136 | when(mem_s === m_pad) { 137 | buffer_raddr := pindex 138 | } 139 | io.buffer_out := buffer_rdata 140 | }else{ 141 | //Note that this uses the index that is passed to the datapath (in phase) 142 | io.buffer_out := buffer(io.aindex) 143 | } 144 | io.windex := windex 145 | 146 | //misc padding signals 147 | val first_pad = Bits(if (p(Sha3Keccak)) "b0000_0001" else "b0000_0110") 148 | val last_pad = Bits("b1000_0000") 149 | val both_pad = first_pad | last_pad 150 | //last word with message in it 151 | val words_filled =// if(fast_mem){ 152 | Mux(mindex > UInt(0), mindex - UInt(1), mindex) 153 | //}else{ 154 | //mindex 155 | //} 156 | 157 | //last byte with message in it 158 | val byte_offset = (msg_len)%UInt(bytes_per_word) 159 | 160 | //hasher state 161 | val s_idle :: s_absorb :: s_finish_abs :: s_hash :: s_write :: Nil = Enum(UInt(), 5) 162 | 163 | val state = Reg(init=s_idle) 164 | 165 | 166 | val rindex = Reg(init = UInt(rounds+1,5)) 167 | val sindex = Reg(init = UInt(0,log2Up(S))) 168 | 169 | //default 170 | io.rocc_req_rdy := Bool(false) 171 | io.init := Bool(false) 172 | io.busy := busy 173 | io.round := rindex 174 | io.stage := sindex 175 | io.write := Bool(true) 176 | io.dmem_req_val:= Bool(false) 177 | io.dmem_req_tag:= rindex 178 | io.dmem_req_addr:= Bits(0, 32) 179 | io.dmem_req_cmd:= M_XRD 180 | io.dmem_req_size:= log2Ceil(8).U 181 | io.sfence := Bool(false) 182 | 183 | val rindex_reg = Reg(next=rindex) 184 | 185 | 186 | switch(rocc_s) { 187 | is(r_idle) { 188 | io.rocc_req_rdy := !busy 189 | when(io.rocc_req_val && !busy){ 190 | when(io.rocc_funct === UInt(0)){ 191 | io.rocc_req_rdy := Bool(true) 192 | msg_addr := io.rocc_rs1 193 | hash_addr := io.rocc_rs2 194 | println("Msg Addr: "+msg_addr+", Hash Addr: "+hash_addr) 195 | io.busy := Bool(true) 196 | }.elsewhen(io.rocc_funct === UInt(1)) { 197 | busy := Bool(true) 198 | io.rocc_req_rdy := Bool(true) 199 | io.busy := Bool(true) 200 | msg_len := io.rocc_rs1 201 | } 202 | if (p(Sha3TLB).isDefined) { 203 | when (io.rocc_funct === UInt(2)) { 204 | io.rocc_req_rdy := Bool(true) 205 | io.sfence := Bool(true) 206 | } 207 | } 208 | } 209 | } 210 | } 211 | 212 | //END RoCC HANDLER 213 | //START MEM HANDLER 214 | 215 | 216 | switch(mem_s){ 217 | is(m_idle){ 218 | //we can start filling the buffer if we aren't writing and if we got a new message 219 | //or the hashing started 220 | //and there is more to read 221 | //and the buffer has been absorbed 222 | val canRead = busy && ( (read < msg_len || (read === msg_len && msg_len === UInt(0)) ) && 223 | (!buffer_valid && buffer_count === UInt(0))) 224 | when(canRead){ 225 | //buffer := Vec.fill(round_size_words){Bits(0,W)} 226 | buffer_count := UInt(0) 227 | mindex := UInt(0) 228 | mem_s := m_read 229 | }.otherwise{ 230 | mem_s := m_idle 231 | } 232 | } 233 | is(m_read) { 234 | //dmem signals 235 | //only read if we aren't writing 236 | when(state =/= s_write){ 237 | io.dmem_req_val := read < msg_len && mindex < UInt(round_size_words) 238 | io.dmem_req_addr := msg_addr 239 | io.dmem_req_tag := mindex 240 | io.dmem_req_cmd := M_XRD 241 | io.dmem_req_size := log2Ceil(8).U 242 | 243 | when(io.dmem_req_rdy && io.dmem_req_val){ 244 | mindex := mindex + UInt(1) 245 | msg_addr := msg_addr + UInt(8) 246 | read := read + UInt(8)//read 8 bytes 247 | if(!fast_mem){ 248 | mem_s := m_wait 249 | } 250 | }.otherwise{ 251 | if(!fast_mem){ 252 | mem_s := m_read 253 | } 254 | } 255 | //TODO: don't like special casing this 256 | when(msg_len === UInt(0)){ 257 | read := UInt(1) 258 | if(!fast_mem){ 259 | mem_s := m_pad 260 | pindex := words_filled 261 | } 262 | } 263 | } 264 | if(fast_mem){ 265 | //next state 266 | when(mindex < UInt(round_size_words - 1)){ 267 | //TODO: in pad check buffer_count ( or move on to next thread?) 268 | when(msg_len > read){ 269 | //not sure if this case will be used but this means we haven't 270 | //sent all the requests yet (maybe back pressure causes this) 271 | when((msg_len+UInt(8)) < read){ 272 | buffer_valid := Bool(false) 273 | mem_s := m_pad 274 | pindex := words_filled 275 | } 276 | mem_s := m_read 277 | }.otherwise{ 278 | //its ok we didn't send them all because the message wasn't big enough 279 | buffer_valid := Bool(false) 280 | mem_s := m_pad 281 | pindex := words_filled 282 | } 283 | }.otherwise{ 284 | when(mindex < UInt(round_size_words) && 285 | !(io.dmem_req_rdy && io.dmem_req_val)){ 286 | //we are still waiting to send the last request 287 | mem_s := m_read 288 | }.otherwise{ 289 | //we have reached the end of this chunk 290 | mindex := mindex + UInt(1) 291 | msg_addr := msg_addr + UInt(8) 292 | read := read + UInt(8)//read 8 bytes 293 | //we sent all the requests 294 | when((msg_len < (read+UInt(8) ))){ 295 | //but the buffer still isn't full 296 | buffer_valid := Bool(false) 297 | mem_s := m_pad 298 | pindex := words_filled 299 | }.otherwise{ 300 | //we have more to read eventually 301 | mem_s := m_idle 302 | } 303 | } 304 | } 305 | } 306 | } 307 | is(m_wait){ 308 | //the code to process read responses 309 | when(io.dmem_resp_val) { 310 | //This is read response 311 | if(buffer_sram){ 312 | buffer_wen := Bool(true) 313 | buffer_waddr := mindex - UInt(1) 314 | buffer_wdata := io.dmem_resp_data 315 | }else{ 316 | buffer(mindex-UInt(1)) := io.dmem_resp_data 317 | } 318 | buffer_count := buffer_count + UInt(1) 319 | 320 | //next state 321 | when(mindex < UInt(round_size_words- 1)){ 322 | //TODO: in pad check buffer_count ( or move on to next thread?) 323 | when(msg_len > read){ 324 | //not sure if this case will be used but this means we haven't 325 | //sent all the requests yet (maybe back pressure causes this) 326 | when((msg_len+UInt(8)) < read){ 327 | buffer_valid := Bool(false) 328 | mem_s := m_pad 329 | pindex := words_filled 330 | } 331 | mem_s := m_read 332 | }.otherwise{ 333 | //its ok we didn't send them all because the message wasn't big enough 334 | buffer_valid := Bool(false) 335 | mem_s := m_pad 336 | pindex := words_filled 337 | } 338 | }.otherwise{ 339 | when(mindex < UInt(round_size_words) && 340 | !(io.dmem_req_rdy && io.dmem_req_val)){ 341 | //we are still waiting to send the last request 342 | mem_s := m_read 343 | }.otherwise{ 344 | //we have reached the end of this chunk 345 | //mindex := mindex + UInt(1) 346 | //read := read + UInt(8)//read 8 bytes 347 | //we sent all the requests 348 | msg_addr := msg_addr + UInt(round_size_words << 3) 349 | when((msg_len < (read+UInt(8) ))){ 350 | //but the buffer still isn't full 351 | buffer_valid := Bool(false) 352 | mem_s := m_pad 353 | pindex := words_filled 354 | }.otherwise{ 355 | //we have more to read eventually 356 | buffer_valid := Bool(true) 357 | mem_s := m_idle 358 | } 359 | } 360 | } 361 | } 362 | } 363 | is(m_pad) { 364 | //local signals 365 | //make sure we have received all the responses for this message 366 | //TODO: update next_buff_val to use pindex 367 | buffer_valid := next_buff_val 368 | 369 | //only update the buffer if we have already written the mem resp to the word 370 | when(! (buffer_count < mindex && (pindex >= buffer_count)) ){ 371 | //set everything to 0000_000 after end of message first 372 | when(pindex > words_filled && pindex < UInt(round_size_words-1)){ 373 | //there is a special case where we need to pad on a word boundary 374 | //when we have to put in first_pad here rather than just all zeros 375 | when(byte_offset === UInt(0) && (pindex === words_filled+UInt(1)) 376 | && mindex =/= UInt(0)){ 377 | if(buffer_sram){ 378 | buffer_wen := Bool(true) 379 | buffer_waddr := pindex 380 | buffer_wdata := Cat(Bits(0,W-8),first_pad) 381 | }else{ 382 | buffer(pindex) := Cat(Bits(0,W-8),first_pad) 383 | } 384 | }.otherwise{ 385 | if(buffer_sram){ 386 | buffer_wen := Bool(true) 387 | buffer_waddr := pindex 388 | buffer_wdata := Bits(0,W) 389 | }else{ 390 | buffer(pindex) := Bits(0,W) 391 | } 392 | } 393 | }.elsewhen(pindex === UInt(round_size_words -1)){ 394 | //this is normally when we write the last_pad but we might end up writing both_pad 395 | //we write both pad if we filled all of the words 396 | //and all but one of the bytes 397 | when(words_filled === UInt(round_size_words - 1)){ 398 | when(byte_offset === UInt(bytes_per_word -1)){ 399 | //together with the first pad 400 | if(buffer_sram){ 401 | when(wait_for_sram === Bool(false)){ 402 | buffer_wen := Bool(true) 403 | buffer_waddr := pindex 404 | buffer_wdata := Cat(both_pad, buffer_rdata(55,0)) 405 | } 406 | }else{ 407 | buffer(pindex) := Cat(both_pad, buffer(pindex)(55,0)) 408 | } 409 | }.elsewhen(byte_offset === UInt(0)){ 410 | //do nothing since we hit the exact size of the word 411 | } 412 | }.otherwise{ 413 | //at the end of the last word 414 | //we clear the word if we didn't fill it 415 | when(words_filled < UInt(round_size_words - 1)){ 416 | if(buffer_sram){ 417 | buffer_wen := Bool(true) 418 | buffer_waddr := pindex 419 | buffer_wdata := Cat(last_pad, Bits(0,(bytes_per_word-1)*8)) 420 | }else{ 421 | buffer(pindex) := Cat(last_pad, Bits(0,(bytes_per_word-1)*8)) 422 | } 423 | }.otherwise{ 424 | if(buffer_sram){ 425 | when(wait_for_sram === Bool(false)){ 426 | buffer_wen := Bool(true) 427 | buffer_waddr := pindex 428 | buffer_wdata := Cat(last_pad, buffer_rdata((bytes_per_word-1)*8-1,0)) 429 | } 430 | }else{ 431 | buffer(pindex) := Cat(last_pad, buffer(pindex)((bytes_per_word-1)*8-1,0)) 432 | } 433 | } 434 | } 435 | }.elsewhen(pindex === words_filled){ 436 | //normally this is when we need to write the first_pad 437 | when(byte_offset =/= UInt(0)) { 438 | //not last byte so we put first pad here 439 | when(byte_offset === UInt(1)){ 440 | if(buffer_sram){ 441 | when(wait_for_sram === Bool(false)){ 442 | //SRAM was allowed 1 cycle to read 443 | buffer_wen := Bool(true) 444 | buffer_waddr := pindex 445 | buffer_wdata := Cat(first_pad,buffer_rdata(7,0)) 446 | //the pindex is still the same as last cycle and buffer_rdata contains buffer(pindex) 447 | } 448 | }else{ 449 | buffer(pindex) := Cat(first_pad,buffer(pindex)(7,0)) 450 | } 451 | }.elsewhen(byte_offset === UInt(2)){ 452 | if(buffer_sram){ 453 | when(wait_for_sram === Bool(false)){ 454 | buffer_wen := Bool(true) 455 | buffer_waddr := pindex 456 | buffer_wdata := Cat(first_pad,buffer_rdata(15,0)) 457 | } 458 | }else{ 459 | buffer(pindex) := Cat(first_pad,buffer(pindex)(15,0)) 460 | } 461 | }.elsewhen(byte_offset === UInt(3)){ 462 | if(buffer_sram){ 463 | when(wait_for_sram === Bool(false)){ 464 | buffer_wen := Bool(true) 465 | buffer_waddr := pindex 466 | buffer_wdata := Cat(first_pad,buffer_rdata(23,0)) 467 | } 468 | }else{ 469 | buffer(pindex) := Cat(first_pad,buffer(pindex)(23,0)) 470 | } 471 | }.elsewhen(byte_offset === UInt(4)){ 472 | if(buffer_sram){ 473 | when(wait_for_sram === Bool(false)){ 474 | buffer_wen := Bool(true) 475 | buffer_waddr := pindex 476 | buffer_wdata := Cat(first_pad,buffer_rdata(31,0)) 477 | } 478 | }else{ 479 | buffer(pindex) := Cat(first_pad,buffer(pindex)(31,0)) 480 | } 481 | }.elsewhen(byte_offset === UInt(5)){ 482 | if(buffer_sram){ 483 | when(wait_for_sram === Bool(false)){ 484 | buffer_wen := Bool(true) 485 | buffer_waddr := pindex 486 | buffer_wdata := Cat(first_pad,buffer_rdata(39,0)) 487 | } 488 | }else{ 489 | buffer(pindex) := Cat(first_pad,buffer(pindex)(39,0)) 490 | } 491 | }.elsewhen(byte_offset === UInt(6)){ 492 | if(buffer_sram){ 493 | when(wait_for_sram === Bool(false)){ 494 | buffer_wen := Bool(true) 495 | buffer_waddr := pindex 496 | buffer_wdata := Cat(first_pad,buffer_rdata(47,0)) 497 | } 498 | }else{ 499 | buffer(pindex) := Cat(first_pad,buffer(pindex)(47,0)) 500 | } 501 | }.elsewhen(byte_offset === UInt(7)){ 502 | if(buffer_sram){ 503 | when(wait_for_sram === Bool(false)){ 504 | buffer_wen := Bool(true) 505 | buffer_waddr := pindex 506 | buffer_wdata := Cat(first_pad,buffer_rdata(55,0)) 507 | } 508 | }else{ 509 | buffer(pindex) := Cat(first_pad,buffer(pindex)(55,0)) 510 | } 511 | } 512 | }.otherwise{ 513 | //this is only valid if we didn't fill any words 514 | when(mindex === UInt(0) && byte_offset === UInt(0)){ 515 | if(buffer_sram){ 516 | buffer_wen := Bool(true) 517 | buffer_waddr := pindex 518 | buffer_wdata := Cat(Bits(0,W-8),first_pad) 519 | }else{ 520 | buffer(pindex) := Cat(Bits(0,W-8),first_pad) 521 | } 522 | } 523 | } 524 | } 525 | } 526 | 527 | //next state 528 | when(next_buff_val){ 529 | //we have received all responses so the buffer is as full as it will get 530 | mindex := UInt(0)//reset this for absorb 531 | when(areg){ 532 | //we already started absorbing so skip to idle and go to next thread 533 | buffer_count := UInt(0) 534 | mindex := UInt(0)//reset this for absorb 535 | mem_s := m_idle 536 | pindex := UInt(0) 537 | wait_for_sram := Bool(true) 538 | }.otherwise{ 539 | mem_s := m_absorb 540 | pindex := UInt(0) 541 | wait_for_sram := Bool(true) 542 | } 543 | }.otherwise{ 544 | //don't move pindex if we haven't received a response for this index 545 | when(buffer_count < mindex && (pindex >= buffer_count) ){ 546 | mem_s := m_pad 547 | }.otherwise{ 548 | if(buffer_sram){ 549 | //With SRAM, we need to increment pindex every other cycle 550 | when(wait_for_sram === Bool(false)){ 551 | pindex := pindex + UInt(1) 552 | wait_for_sram := Bool(true) 553 | }.otherwise{ 554 | wait_for_sram := Bool(false) 555 | } 556 | } 557 | else{ 558 | //Register buffer does not need to wait a cycle 559 | pindex := pindex + UInt(1) 560 | } 561 | mem_s := m_pad 562 | } 563 | } 564 | } 565 | is(m_absorb){ 566 | buffer_valid := Bool(true) 567 | //move to idle when we know this thread was absorbed 568 | when(aindex >= UInt(round_size_words-1)){ 569 | mem_s := m_idle 570 | } 571 | } 572 | } 573 | //the code to process read responses 574 | if(fast_mem){ 575 | when(io.dmem_resp_val) { 576 | when(io.dmem_resp_tag(4,0) < UInt(round_size_words)){ 577 | //This is read response 578 | if(buffer_sram){ 579 | buffer_wen := Bool(true) 580 | buffer_waddr := io.dmem_resp_tag(4,0) 581 | buffer_wdata := io.dmem_resp_data 582 | }else{ 583 | buffer(io.dmem_resp_tag(4,0)) := io.dmem_resp_data 584 | } 585 | buffer_count := buffer_count + UInt(1) 586 | } 587 | } 588 | when(buffer_count >= (mindex) && 589 | (mindex >= UInt(round_size_words))){// || 590 | //read(i) > msg_len(i))){ 591 | when(read > msg_len){ 592 | //padding needed 593 | }.otherwise{ 594 | //next cycle the buffer will be valid 595 | buffer_valid := Bool(true) 596 | } 597 | } 598 | } 599 | //END MEM HANDLER 600 | 601 | 602 | switch(state) { 603 | is(s_idle) { 604 | val canAbsorb = busy && (rindex_reg >= UInt(rounds) && buffer_valid && hashed <= msg_len) 605 | when(canAbsorb){ 606 | busy := Bool(true) 607 | state := s_absorb 608 | }.otherwise{ 609 | state := s_idle 610 | } 611 | } 612 | is(s_absorb){ 613 | io.write := !areg //Bool(false) 614 | areg := Bool(true) 615 | aindex := aindex + UInt(1) 616 | when(io.aindex >= UInt(round_size_words-1)){ 617 | rindex := UInt(0) 618 | sindex := UInt(0) 619 | aindex := UInt(0) 620 | //Delayed 1 cycle for sram 621 | //areg := Bool(false) 622 | buffer_valid := Bool(false) 623 | buffer_count := UInt(0) 624 | hashed := hashed + UInt(8*round_size_words) 625 | state := s_finish_abs 626 | }.otherwise{ 627 | state := s_absorb 628 | } 629 | } 630 | is(s_finish_abs){ 631 | //There is a 1 cycle delay for absorb to finish (since the SRAM read is delayed by 1 cycle) 632 | areg := Bool(false) 633 | state := s_hash 634 | } 635 | is(s_hash){ 636 | when(rindex < UInt(rounds)){ 637 | when(sindex < UInt(S-1)){ 638 | sindex := sindex + UInt(1) 639 | io.round := rindex 640 | io.stage := sindex 641 | io.write := Bool(false) 642 | state := s_hash 643 | }.otherwise{ 644 | sindex := UInt(0) 645 | rindex := rindex + UInt(1) 646 | io.round := rindex 647 | io.write := Bool(false) 648 | state := s_hash 649 | } 650 | }.otherwise{ 651 | io.write := Bool(true) 652 | when(hashed > msg_len || (hashed === msg_len && rindex === UInt(rounds))){ 653 | windex := UInt(0) 654 | state := s_write 655 | }.otherwise{ 656 | state := s_idle 657 | } 658 | } 659 | } 660 | is(s_write){ 661 | //we are writing 662 | //request 663 | io.dmem_req_val := windex < UInt(hash_size_words) 664 | io.dmem_req_addr := hash_addr 665 | io.dmem_req_tag := UInt(round_size_words) + windex 666 | io.dmem_req_cmd := M_XWR 667 | 668 | when(io.dmem_req_rdy){ 669 | windex := windex + UInt(1) 670 | hash_addr := hash_addr + UInt(8) 671 | } 672 | 673 | //response 674 | when(dmem_resp_val_reg){ 675 | //there is a response from memory 676 | when(dmem_resp_tag_reg(4,0) >= UInt(round_size_words)) { 677 | //this is a response to a write 678 | writes_done(dmem_resp_tag_reg(4,0)-UInt(round_size_words)) := Bool(true) 679 | } 680 | } 681 | when(writes_done.reduce(_&&_)){ 682 | //all the writes have been responded to 683 | //this is essentially reset time 684 | busy := Bool(false) 685 | 686 | writes_done := Vec.fill(hash_size_words){Bool(false)} 687 | windex := UInt(hash_size_words) 688 | rindex := UInt(rounds+1) 689 | buffer_count := UInt(0) 690 | msg_addr := UInt(0) 691 | hash_addr := UInt(0) 692 | msg_len := UInt(0) 693 | hashed := UInt(0) 694 | read := UInt(0) 695 | buffer_valid := Bool(false) 696 | io.init := Bool(true) 697 | state := s_idle 698 | }.otherwise{ 699 | state := s_write 700 | } 701 | } 702 | } 703 | } 704 | -------------------------------------------------------------------------------- /src/main/scala/dmem.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Albert Ou 3 | package sha3 4 | 5 | import Chisel._ 6 | import org.chipsalliance.cde.config.{Field, Parameters} 7 | import freechips.rocketchip.tile.HasCoreParameters 8 | import freechips.rocketchip.rocket.{HellaCacheReq, TLB, TLBPTWIO, TLBConfig, MStatus, PRV} 9 | import freechips.rocketchip.diplomacy._ 10 | import freechips.rocketchip.tilelink._ 11 | 12 | case object Sha3TLB extends Field[Option[TLBConfig]](None) 13 | 14 | class DmemModule(implicit p: Parameters) extends LazyModule { 15 | lazy val module = new DmemModuleImp(this) 16 | // FIXME: Unused Diplomacy node needed for conveying the physical address map to the TLB 17 | val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("SHA3"))))) 18 | } 19 | 20 | class DmemModuleImp(outer: DmemModule)(implicit p: Parameters) extends LazyModuleImp(outer) 21 | with HasCoreParameters { 22 | 23 | val io = IO(new Bundle { 24 | val req = Decoupled(new HellaCacheReq).flip 25 | val mem = Decoupled(new HellaCacheReq) 26 | val ptw = new TLBPTWIO 27 | val status = new MStatus().asInput 28 | val sfence = Bool(INPUT) 29 | }) 30 | 31 | val (tl, edge) = outer.node.out.head 32 | // Tie off unused channels 33 | tl.a.valid := Bool(false) 34 | tl.b.ready := Bool(true) 35 | tl.c.valid := Bool(false) 36 | tl.d.ready := Bool(true) 37 | tl.e.valid := Bool(false) 38 | 39 | val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), p(Sha3TLB).get)(edge, p)) 40 | tlb.io.req.valid := io.req.valid 41 | tlb.io.req.bits.vaddr := io.req.bits.addr 42 | tlb.io.req.bits.size := io.req.bits.size 43 | tlb.io.req.bits.cmd := io.req.bits.cmd 44 | tlb.io.req.bits.prv := io.req.bits.dprv 45 | tlb.io.req.bits.v := io.req.bits.dv 46 | tlb.io.req.bits.passthrough := Bool(false) 47 | val tlb_ready = tlb.io.req.ready && !tlb.io.resp.miss 48 | 49 | io.ptw <> tlb.io.ptw 50 | tlb.io.ptw.status := io.status 51 | tlb.io.sfence.valid := io.sfence 52 | tlb.io.sfence.bits.rs1 := Bool(false) 53 | tlb.io.sfence.bits.rs2 := Bool(false) 54 | tlb.io.sfence.bits.addr := UInt(0) 55 | tlb.io.sfence.bits.asid := UInt(0) 56 | tlb.io.kill := Bool(false) 57 | 58 | io.req.ready := io.mem.ready && tlb_ready 59 | 60 | io.mem.valid := io.req.valid && tlb_ready 61 | io.mem.bits := io.req.bits 62 | io.mem.bits.addr := tlb.io.resp.paddr 63 | /* 64 | * FIXME: Asserting phys sets io.req.bits.passthrough to true in the 65 | * DCache TLB, which causes it to assume that the request originates 66 | * from the PTW and treat it as a supervisor access. This may lead to 67 | * spurious PMP exceptions (io.resp.ae.ld) even when the actual 68 | * privilege level is M-mode. 69 | */ 70 | io.mem.bits.phys := (io.req.bits.dprv =/= UInt(PRV.M)) 71 | 72 | // FIXME: Check TLB exceptions 73 | } 74 | -------------------------------------------------------------------------------- /src/main/scala/dpath.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | import scala.collection.mutable.HashMap 7 | import scala.collection.mutable.ArrayBuffer 8 | import scala.util.Random 9 | import org.chipsalliance.cde.config.Parameters 10 | 11 | class DpathModule(val W: Int, val S: Int)(implicit p: Parameters) extends Module { 12 | //constants 13 | val r = 2*256 14 | val c = 25*W - r 15 | val round_size_words = c/W 16 | val rounds = 24 //12 + 2l 17 | val hash_size_words = 256/W 18 | val bytes_per_word = W/8 19 | 20 | val io = new Bundle { 21 | val absorb = Bool(INPUT) 22 | val init = Bool(INPUT) 23 | val write = Bool(INPUT) 24 | val round = UInt(INPUT,width=5) 25 | val stage = UInt(INPUT,width=log2Up(S)) 26 | val aindex = UInt(INPUT,width=log2Up(round_size_words)) 27 | val message_in = Bits(INPUT, width = W) 28 | val hash_out = Vec(hash_size_words, Bits(OUTPUT, width = W)) 29 | } 30 | 31 | val state = Reg(init=Vec.fill(5*5){ Bits(0, width = W)}) 32 | 33 | //submodules 34 | val theta = Module(new ThetaModule(W)).io 35 | val rhopi = Module(new RhoPiModule(W)).io 36 | val chi = Module(new ChiModule(W)).io 37 | val iota = Module(new IotaModule(W)) 38 | 39 | //default 40 | theta.state_i := Vec.fill(25){Bits(0,W)} 41 | iota.io.round := UInt(0) 42 | 43 | //connect submodules to each other 44 | if(S == 1){ 45 | theta.state_i := state 46 | rhopi.state_i <> theta.state_o 47 | chi.state_i <> rhopi.state_o 48 | iota.io.state_i <> chi.state_o 49 | state := iota.io.state_o 50 | } 51 | if(S == 2){ 52 | //stage 1 53 | theta.state_i := state 54 | rhopi.state_i <> theta.state_o 55 | 56 | //stage 2 57 | chi.state_i := state 58 | iota.io.state_i <> chi.state_o 59 | } 60 | if(S == 4){ 61 | //stage 1 62 | theta.state_i := state 63 | //stage 2 64 | rhopi.state_i := state 65 | //stage 3 66 | chi.state_i := state 67 | //stage 3 68 | iota.io.state_i := state 69 | } 70 | 71 | iota.io.round := io.round 72 | 73 | //try moving mux out 74 | switch(io.stage){ 75 | is(UInt(0)){ 76 | if(S == 1){ 77 | state := iota.io.state_o 78 | }else if(S == 2){ 79 | state := rhopi.state_o 80 | }else if(S == 4){ 81 | state := theta.state_o 82 | } 83 | } 84 | is(UInt(1)){ 85 | if(S == 2){ 86 | state := iota.io.state_o 87 | }else if(S == 4){ 88 | state := rhopi.state_o 89 | } 90 | } 91 | is(UInt(2)){ 92 | if(S == 4){ 93 | state := chi.state_o 94 | } 95 | } 96 | is(UInt(3)){ 97 | if(S == 4){ 98 | state := iota.io.state_o 99 | } 100 | } 101 | } 102 | 103 | when(io.absorb){ 104 | state := state 105 | if(p(Sha3PrintfEnable)){ 106 | printf(midas.targetutils.SynthesizePrintf("SHA3 finished an iteration with index %d and message %x\n", io.aindex, io.message_in)) 107 | } 108 | when(io.aindex < UInt(round_size_words)){ 109 | state((io.aindex%UInt(5))*UInt(5)+(io.aindex/UInt(5))) := 110 | state((io.aindex%UInt(5))*UInt(5)+(io.aindex/UInt(5))) ^ io.message_in 111 | } 112 | } 113 | 114 | val hash_res = Wire(Vec(hash_size_words, Bits(width = W))) 115 | for( i <- 0 until hash_size_words){ 116 | io.hash_out(i) := state(i*5) 117 | } 118 | 119 | //keep state from changing while we write 120 | when(io.write){ 121 | state := state 122 | } 123 | 124 | //initialize state to 0 for new hashes or at reset 125 | when(io.init){ 126 | state := Vec.fill(5*5){Bits(0, width = W)} 127 | } 128 | 129 | when(reset){ 130 | state := Vec.fill(5*5){Bits(0, width = W)} 131 | } 132 | } 133 | -------------------------------------------------------------------------------- /src/main/scala/iota.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | import scala.collection.mutable.HashMap 7 | import scala.collection.mutable.ArrayBuffer 8 | import scala.util.Random 9 | //import chiseltest.iotesters.PeekPokeTester 10 | 11 | class IotaModule(val W: Int = 64) extends Module { 12 | val io = new Bundle { 13 | val state_i = Vec(5*5, Bits(INPUT,W)) 14 | val state_o = Vec(5*5, Bits(OUTPUT,W)) 15 | val round = UInt(INPUT, 5) 16 | } 17 | 18 | //TODO: c code uses look up table for this 19 | for(i <- 0 until 5) { 20 | for(j <- 0 until 5) { 21 | if(i !=0 || j!=0) 22 | io.state_o(i*5+j) := io.state_i(i*5+j) 23 | } 24 | } 25 | //val const = ROUND_CONST.value(io.round) 26 | val const = IOTA.round_const(io.round) 27 | io.state_o(0) := io.state_i(0) ^ const 28 | /* 29 | io.state_o(0) := Cat(io.state_i(0)(63) ^ const(6), 30 | io.state_i(0)(62,32), 31 | io.state_i(0)(31) ^ const(5), 32 | io.state_i(0)(30,16), 33 | io.state_i(0)(15) ^ const(4), 34 | io.state_i(0)(14,8), 35 | io.state_i(0)( 7) ^ const(3), 36 | io.state_i(0)(6,4), 37 | io.state_i(0)( 3) ^ const(2), 38 | io.state_i(0)( 2), 39 | io.state_i(0)( 1) ^ const(1), 40 | io.state_i(0)( 0) ^ const(0)) 41 | */ 42 | } 43 | 44 | // class IotaModuleTests(c: IotaModule) extends PeekPokeTester(c) { 45 | // val W = 64 46 | // val maxInt = 1 << (5*5*W) 47 | // //val state_i = rnd.nextInt(maxInt) 48 | // val round = 0 49 | // val state = Array.fill(5*5){BigInt(3)} 50 | // val out_state = Array.fill(5*5){BigInt(3)} 51 | // out_state(0) = state(0) ^ BigInt(1) 52 | // poke(c.io.state_i, state) 53 | // poke(c.io.round, round) 54 | // step(1) 55 | // expect(c.io.state_o, out_state) 56 | // } 57 | /* 58 | object iotaMain { 59 | def main(args: Array[String]): Unit = { 60 | //chiselMainTest(Array[String]("--backend", "c", "--genHarness", "--compile", "--test"), 61 | chiselMainTest(args, 62 | () => Module(new IotaModule())){c => new IotaModuleTests(c) 63 | } 64 | } 65 | } 66 | */ 67 | -------------------------------------------------------------------------------- /src/main/scala/rhopi.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | //import chiseltest.iotesters.PeekPokeTester 7 | import scala.collection.mutable.HashMap 8 | import scala.collection.mutable.ArrayBuffer 9 | import scala.util.Random 10 | 11 | class RhoPiModule(val W : Int = 64) extends Module { 12 | //val W = 64 13 | val io = new Bundle { 14 | val state_i = Vec(25, Bits(INPUT, W)) 15 | val state_o = Vec(25, Bits(OUTPUT,W)) 16 | } 17 | 18 | //TODO: c code uses falttened rep for this 19 | /* 20 | val piln = Array( 21 | 0, 18, 21, 19, 14, 22 | 10, 3, 24, 13, 22, 23 | 7, 5, 4, 12, 9, 24 | 11, 16, 15, 2, 6, 25 | 17, 8, 23, 20, 1 26 | ) 27 | 28 | val tri = Array( 29 | 0, 36, 3, 41, 18, 30 | 1, 44, 10, 45, 2, 31 | 62, 6, 43, 15, 61, 32 | 28, 55, 25, 21, 56, 33 | 27, 20, 39, 8, 14 34 | ) 35 | */ 36 | 37 | for(i <- 0 until 5) { 38 | for(j <- 0 until 5) { 39 | val temp = Wire(Bits()) 40 | if((RHOPI.tri(i*5+j)%W) == 0){ 41 | temp := io.state_i(i*5+j) 42 | }else{ 43 | temp := Cat(io.state_i(i*5+j)((W-1) - (RHOPI.tri(i*5+j)-1)%W,0),io.state_i(i*5+j)(W-1,W-1 - ((RHOPI.tri(i*5+j)-1)%W))) 44 | } 45 | io.state_o(j*5+((2*i+3*j)%5)) := temp 46 | } 47 | } 48 | } 49 | -------------------------------------------------------------------------------- /src/main/scala/sha3.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | import freechips.rocketchip.tile._ 8 | import org.chipsalliance.cde.config._ 9 | import freechips.rocketchip.diplomacy._ 10 | import freechips.rocketchip.rocket.{TLBConfig, HellaCacheReq} 11 | 12 | 13 | case object Sha3WidthP extends Field[Int] 14 | case object Sha3Stages extends Field[Int] 15 | case object Sha3FastMem extends Field[Boolean] 16 | case object Sha3BufferSram extends Field[Boolean] 17 | /* 18 | * Implement original Keccak candidate instead of the finalized FIPS 202 19 | * specification, which differs in the padding behavior 20 | */ 21 | case object Sha3Keccak extends Field[Boolean] 22 | /* 23 | * Enable specific printf's. This is used to demonstrate MIDAS 24 | * printf's during the MICRO2019 tutorial. 25 | */ 26 | case object Sha3PrintfEnable extends Field[Boolean](false) 27 | 28 | /* 29 | * Use a Blackbox verilog version of the inner SHA3 accelerator 30 | */ 31 | case object Sha3BlackBox extends Field[Boolean](false) 32 | 33 | /* 34 | abstract class SimpleRoCC()(implicit p: Parameters) extends RoCC()(p) 35 | { 36 | io.interrupt := Bool(false) 37 | // Set this true to trigger an interrupt on the processor (please refer to supervisor documentation) 38 | 39 | //a simple accelerator doesn't use imem or page tables 40 | 41 | //Old Format 42 | //io.imem.acquire.valid := Bool(false) 43 | //io.imem.grant.ready := Bool(false) 44 | //io.imem.finish.valid := Bool(false) 45 | //io.iptw.req.valid := Bool(false) 46 | //io.dptw.req.valid := Bool(false) 47 | //io.pptw.req.valid := Bool(false) 48 | 49 | //New Format 50 | io.autl.acquire.valid := Bool(false) 51 | io.autl.grant.ready := Bool(false) 52 | for(i <- 0 until p(RoccNPTWPorts)) io.ptw(i).req.valid := Bool(false) 53 | } 54 | */ 55 | 56 | class WrapBundle(nPTWPorts: Int)(implicit p: Parameters) extends Bundle { 57 | val io = new RoCCIO(nPTWPorts, 0) 58 | val clock = Input(Clock()) 59 | val reset = Input(UInt(1.W)) 60 | } 61 | 62 | class Sha3BlackBox(implicit p: Parameters) extends BlackBox with HasBlackBoxResource { 63 | val io = IO(new WrapBundle(0)) 64 | 65 | addResource("/vsrc/Sha3BlackBox.v") 66 | } 67 | 68 | class Sha3Accel(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC( 69 | opcodes = opcodes, nPTWPorts = if (p(Sha3TLB).isDefined) 1 else 0) { 70 | override lazy val module = new Sha3AccelImp(this) 71 | val dmemOpt = p(Sha3TLB).map { _ => 72 | val dmem = LazyModule(new DmemModule) 73 | tlNode := dmem.node 74 | dmem 75 | } 76 | } 77 | 78 | class Sha3AccelImp(outer: Sha3Accel)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) { 79 | // Suppress DCE to ensure that the module ports are kept consistent 80 | // between the regular generated Verilog and Sha3BlackBox version 81 | //chisel3.dontTouch(io) 82 | 83 | //parameters 84 | val W = p(Sha3WidthP) 85 | val S = p(Sha3Stages) 86 | //constants 87 | val r = 2*256 88 | val c = 25*W - r 89 | val round_size_words = c/W 90 | val rounds = 24 //12 + 2l 91 | val hash_size_words = 256/W 92 | val bytes_per_word = W/8 93 | 94 | //RoCC Interface defined in testMems.scala 95 | //cmd 96 | //resp 97 | io.resp.valid := false.B //Sha3 never returns values with the resp 98 | //mem 99 | //busy 100 | if (p(Sha3BlackBox)) { 101 | require(!p(Sha3TLB).isDefined, "Blackbox SHA3 does not support Dmemmodule") 102 | 103 | val sha3bb = Module(new Sha3BlackBox) 104 | io <> sha3bb.io.io 105 | sha3bb.io.clock := clock 106 | sha3bb.io.reset := reset.asBool 107 | } else { 108 | 109 | val ctrl = Module(new CtrlModule(W,S)(p)) 110 | 111 | ctrl.io.rocc_req_val <> io.cmd.valid 112 | io.cmd.ready := ctrl.io.rocc_req_rdy 113 | ctrl.io.rocc_funct <> io.cmd.bits.inst.funct 114 | ctrl.io.rocc_rs1 <> io.cmd.bits.rs1 115 | ctrl.io.rocc_rs2 <> io.cmd.bits.rs2 116 | ctrl.io.rocc_rd <> io.cmd.bits.inst.rd 117 | io.busy := ctrl.io.busy 118 | 119 | val status = RegEnable(io.cmd.bits.status, io.cmd.fire()) 120 | val dmem_data = Wire(Bits()) 121 | def dmem_ctrl(req: DecoupledIO[HellaCacheReq]) { 122 | req.valid := ctrl.io.dmem_req_val 123 | ctrl.io.dmem_req_rdy := req.ready 124 | req.bits.tag := ctrl.io.dmem_req_tag 125 | req.bits.addr := ctrl.io.dmem_req_addr 126 | req.bits.cmd := ctrl.io.dmem_req_cmd 127 | req.bits.size := ctrl.io.dmem_req_size 128 | req.bits.data := dmem_data 129 | req.bits.signed := false.B 130 | req.bits.dprv := status.dprv 131 | req.bits.dv := status.dv 132 | req.bits.phys := false.B 133 | } 134 | 135 | outer.dmemOpt match { 136 | case Some(m) => { 137 | val dmem = m.module 138 | dmem.io := DontCare 139 | dmem_ctrl(dmem.io.req) 140 | io.mem.req <> dmem.io.mem 141 | io.ptw.head <> dmem.io.ptw 142 | 143 | dmem.io.status := status 144 | dmem.io.sfence := ctrl.io.sfence 145 | } 146 | case None => dmem_ctrl(io.mem.req) 147 | } 148 | 149 | ctrl.io.dmem_resp_val <> io.mem.resp.valid 150 | ctrl.io.dmem_resp_tag <> io.mem.resp.bits.tag 151 | ctrl.io.dmem_resp_data := io.mem.resp.bits.data 152 | 153 | val dpath = Module(new DpathModule(W,S)(p)) 154 | 155 | dpath.io.message_in <> ctrl.io.buffer_out 156 | dmem_data := dpath.io.hash_out(ctrl.io.windex) 157 | 158 | //ctrl.io <> dpath.io 159 | dpath.io.absorb := ctrl.io.absorb 160 | dpath.io.init := ctrl.io.init 161 | dpath.io.write := ctrl.io.write 162 | dpath.io.round := ctrl.io.round 163 | dpath.io.stage := ctrl.io.stage 164 | dpath.io.aindex := ctrl.io.aindex 165 | } 166 | } 167 | 168 | class WithSha3BlackBox extends Config((site, here, up) => { 169 | case Sha3BlackBox => true 170 | case Sha3TLB => None // Do not use the more correct DmemModule when blackboxing 171 | }) 172 | 173 | class WithSha3Accel(fastMem: Boolean = true) extends Config ((site, here, up) => { 174 | case Sha3WidthP => 64 175 | case Sha3Stages => 1 176 | case Sha3FastMem => fastMem 177 | case Sha3BufferSram => false 178 | case Sha3Keccak => false 179 | case Sha3BlackBox => false 180 | case Sha3TLB => Some(TLBConfig(nSets = 1, nWays = 4, nSectors = 1, nSuperpageEntries = 1)) 181 | case BuildRoCC => up(BuildRoCC) ++ Seq( 182 | (p: Parameters) => { 183 | val sha3 = LazyModule.apply(new Sha3Accel(OpcodeSet.custom2)(p)) 184 | sha3 185 | } 186 | ) 187 | }) 188 | 189 | class WithSha3Printf extends Config((site, here, up) => { 190 | case Sha3PrintfEnable => true 191 | }) 192 | -------------------------------------------------------------------------------- /src/main/scala/theta.scala: -------------------------------------------------------------------------------- 1 | //see LICENSE for license 2 | //authors: Colin Schmidt, Adam Izraelevitz 3 | package sha3 4 | 5 | import Chisel._ 6 | //import chiseltest.iotesters.PeekPokeTester 7 | import scala.collection.mutable.HashMap 8 | import scala.collection.mutable.ArrayBuffer 9 | 10 | 11 | class ThetaModule(val W: Int = 64) extends Module { 12 | //val W = 64 13 | //val W = RangeParam(64, 8, 64, 8).register(this, "W") 14 | val io = new Bundle { 15 | val state_i = Vec(5*5, Bits(INPUT, width = W)) 16 | val state_o = Vec(5*5, Bits(OUTPUT,width = W)) 17 | } 18 | 19 | val bc = Vec.fill(5){Wire(Bits(width = W))} 20 | for(i <- 0 until 5) { 21 | bc(i) := io.state_i(i*5+0) ^ io.state_i(i*5+1) ^ io.state_i(i*5+2) ^ io.state_i(i*5+3) ^ io.state_i(i*5+4) 22 | } 23 | 24 | for(i <- 0 until 5) { 25 | val t = Wire(Bits(width = W)) 26 | t := bc((i+4)%5) ^ common.ROTL(bc((i+1)%5), UInt(1), UInt(W)) 27 | for(j <- 0 until 5) { 28 | io.state_o(i*5+j) := io.state_i(i*5+j) ^ t 29 | } 30 | } 31 | } 32 | 33 | class Parity extends Module { 34 | val io = new Bundle { 35 | val in = Vec.fill(5){Bool(INPUT)} 36 | val res = Bool(OUTPUT) 37 | } 38 | io.res := io.in(0) ^ io.in(1) ^ io.in(2) ^ io.in(3) ^ io.in(4) 39 | } 40 | /* 41 | class ThetaModuleTests(c: ThetaModule) extends Tester(c, Array(c.io)) { 42 | defTests { 43 | var allGood = true 44 | val vars = new HashMap[Node, Node]() 45 | val W = 4 46 | for (i <- 0 until 1) { 47 | val state = Vec.fill(5*5){Bits(width = W)} 48 | val out_state = Vec.fill(5*5){Bits(width = W)} 49 | val matrix = common.generate_test_matrix(W) 50 | var out_matrix = ArrayBuffer.empty[BigInt] 51 | 52 | for (i <- 0 until 5) { 53 | for (j <- 0 until 5) { 54 | val word = matrix(i*5+j) 55 | state(i*5+j) = Bits(word,width=W) 56 | vars(c.io.state_i(i*5+j)) = state(i*5+j) 57 | } 58 | } 59 | 60 | val bc = Vec.fill(5){Bits(width = W)} 61 | for(i <- 0 until 5) { 62 | bc(i) := state(0*5+i) ^ state(1*5+i) ^ state(2*5+i) ^ state(3*5+i) ^ state(4*5+i) 63 | } 64 | 65 | for(i <- 0 until 5) { 66 | val t = Bits(width = W) 67 | t := bc((i+4)%5) ^ common.ROTL(bc((i+1)%5), UInt(1), UInt(W)) 68 | for(j <- 0 until 5) { 69 | out_state(i*5+j) := state(i*5+j) ^ t 70 | vars(c.io.state_o(i*5+j)) = out_state(i*5+j) 71 | } 72 | } 73 | allGood = step(vars) && allGood 74 | common.print_matrix(matrix) 75 | //common.print_bigmatrix(out_matrix.toArray) 76 | } 77 | printf("Test passed: " + allGood + "\n") 78 | allGood 79 | } 80 | } 81 | */ 82 | /* 83 | object thetaMain { 84 | def main(args: Array[String]): Unit = { 85 | val res = 86 | args(0) match { 87 | // Generate default design and dump parameter space 88 | case "THETA_dump" => { 89 | chiselMain(args.slice(2,args.length), () => Module(new ThetaModule())) 90 | Params.dump(args(1)) 91 | } 92 | // Generate design based on design point input 93 | case "THETA" => { 94 | Params.load(args(1)) 95 | chiselMain(args.slice(2,args.length), () => Module(new ThetaModule())) 96 | } 97 | case "THETA_test" => { 98 | Params.load(args(1)) 99 | chiselMainTest(args.slice(1,args.length), () => Module(new ThetaModule())) {c => new ThetaModuleTests(c) } 100 | } 101 | case "THETA_NP_test" => { 102 | chiselMainTest(args.slice(1,args.length), () => Module(new ThetaModule())) {c => new ThetaModuleTests(c) } 103 | } 104 | case _ => { 105 | printf("Bad arg(0)\n") 106 | } 107 | } 108 | } 109 | } 110 | 111 | */ 112 | --------------------------------------------------------------------------------