├── .gitignore ├── LICENSE ├── Makefrag ├── README.md ├── bootrom ├── csrc ├── project └── build.properties ├── src └── main │ ├── resources │ ├── dramsim2_ini │ │ ├── DDR3_micron_64M_8B_x4_sg15.ini │ │ └── system.ini │ └── testchipip │ │ ├── bootrom │ │ ├── Makefile │ │ ├── bootrom.S │ │ ├── bootrom.radiance.S │ │ ├── bootrom.radiance.rv32.dump │ │ ├── bootrom.radiance.rv32.img │ │ ├── bootrom.rv32.dump │ │ ├── bootrom.rv32.img │ │ ├── bootrom.rv64.dump │ │ ├── bootrom.rv64.img │ │ └── linker.ld │ │ ├── csrc │ │ ├── SimBlockDevice.cc │ │ ├── SimDRAM.cc │ │ ├── SimDromajoCosim.cc │ │ ├── SimTSI.cc │ │ ├── SimUART.cc │ │ ├── TestchipSimDTM.cc │ │ ├── blkdev.cc │ │ ├── blkdev.h │ │ ├── cospike.cc │ │ ├── cospike_dtm.h │ │ ├── cospike_impl.cc │ │ ├── cospike_impl.h │ │ ├── dromajo_wrapper.cc │ │ ├── dromajo_wrapper.h │ │ ├── mm.cc │ │ ├── mm.h │ │ ├── mm_dramsim2.cc │ │ ├── mm_dramsim2.h │ │ ├── plusarg_file_mem.cc │ │ ├── plusarg_file_mem.h │ │ ├── testchip_dtm.cc │ │ ├── testchip_dtm.h │ │ ├── testchip_htif.cc │ │ ├── testchip_htif.h │ │ ├── testchip_tsi.cc │ │ ├── testchip_tsi.h │ │ ├── uart.cc │ │ └── uart.h │ │ ├── tlrom │ │ ├── Makefile │ │ ├── linker.ld │ │ └── rom.S │ │ └── vsrc │ │ ├── ClockUtil.v │ │ ├── SPIFlashMemCtrl.sv │ │ ├── SimBlockDevice.v │ │ ├── SimDRAM.v │ │ ├── SimDromajoCosimBlackBox.v │ │ ├── SimSPIFlashModel.sv │ │ ├── SimTSI.v │ │ ├── SimUART.v │ │ ├── TestchipSimDTM.v │ │ ├── cospike.v │ │ └── plusarg_file_mem.sv │ └── scala │ ├── boot │ ├── BootAddrReg.scala │ ├── Configs.scala │ ├── CustomBootPin.scala │ └── TileResetCtrl.scala │ ├── clocking │ ├── ClockUtil.scala │ └── ResetUtil.scala │ ├── cosim │ ├── Cospike.scala │ ├── Dromajo.scala │ └── TraceIO.scala │ ├── ctc │ ├── CTC.scala │ ├── CTCToTileLink.scala │ └── TileLinkToCTC.scala │ ├── dram │ ├── SimDRAM.scala │ └── SimTLMem.scala │ ├── iceblk │ ├── BlockDevice.scala │ └── Configs.scala │ ├── serdes │ ├── Adapter.scala │ ├── Bundles.scala │ ├── Configs.scala │ ├── Parameters.scala │ ├── PeripheryTLSerial.scala │ ├── ProbeBlocker.scala │ ├── Serdes.scala │ ├── SerialPhy.scala │ ├── SourceAdjuster.scala │ ├── SourceCombiner.scala │ ├── Stream.scala │ ├── TLChannelCompactor.scala │ ├── TLSerdes.scala │ └── old │ │ ├── Configs.scala │ │ ├── PeripheryTLSerial.scala │ │ ├── Serdes.scala │ │ └── TLSerdes.scala │ ├── soc │ ├── ChipIdPin.scala │ ├── Configs.scala │ ├── Network.scala │ ├── NoDebug.scala │ ├── OffchipBus.scala │ ├── Ring.scala │ ├── Scratchpad.scala │ ├── SimDTM.scala │ └── SubsystemInjector.scala │ ├── spi │ └── SimSPIFlash.scala │ ├── test │ ├── ClockUtilTests.scala │ ├── Configs.scala │ └── Unittests.scala │ ├── tsi │ ├── Configs.scala │ ├── PeripheryUARTTSI.scala │ ├── SimTSI.scala │ ├── TSIHarness.scala │ └── TSIToTileLink.scala │ ├── uart │ ├── SimUART.scala │ └── UARTToSerial.scala │ └── util │ ├── HeaderEnum.scala │ ├── Switcher.scala │ └── Util.scala ├── uart_tsi ├── .gitignore ├── Makefile ├── testchip_uart_tsi.cc └── testchip_uart_tsi.h └── vsrc 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