├── LICENSE ├── README.md ├── examples ├── Fomu │ ├── OSS_CAD_Suite │ │ ├── Makefile │ │ ├── input │ │ │ ├── demo │ │ │ │ ├── gtkwave │ │ │ │ │ ├── app.cmd.map │ │ │ │ │ ├── app.state.map │ │ │ │ │ └── procs.tcl │ │ │ │ ├── hdl_files.mk │ │ │ │ └── pre-pack.py │ │ │ ├── loopback │ │ │ │ ├── hdl_files.mk │ │ │ │ └── pre-pack.py │ │ │ └── soc │ │ │ │ ├── hdl_files.mk │ │ │ │ └── pre-pack.py │ │ ├── output │ │ │ ├── demo │ │ │ │ ├── demo.bin │ │ │ │ ├── demo.rpt │ │ │ │ ├── log_nextpnr_demo.txt │ │ │ │ └── log_yosys_demo.txt │ │ │ ├── loopback │ │ │ │ ├── log_nextpnr_loopback.txt │ │ │ │ ├── log_yosys_loopback.txt │ │ │ │ ├── loopback.bin │ │ │ │ └── loopback.rpt │ │ │ └── soc │ │ │ │ ├── log_nextpnr_soc.txt │ │ │ │ ├── log_yosys_soc.txt │ │ │ │ ├── soc.bin │ │ │ │ └── soc.rpt │ │ └── pcf │ │ │ ├── fomu-evt2.pcf │ │ │ ├── fomu-evt3.pcf │ │ │ ├── fomu-hacker.pcf │ │ │ └── fomu-pvt.pcf │ ├── hdl │ │ ├── demo │ │ │ ├── app.v │ │ │ ├── demo.v │ │ │ ├── demo_fpga.vhd │ │ │ ├── demo_tasks.v │ │ │ └── tb_demo.v │ │ ├── loopback │ │ │ ├── loopback.v │ │ │ └── tb_loopback.v │ │ └── soc │ │ │ ├── app.v │ │ │ ├── soc.v │ │ │ └── tb_soc.v │ ├── iCEcube2 │ │ ├── demo │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── demo_bitmap.bin │ │ │ │ │ ├── demo_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── demo_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ ├── demo_allverilog │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── demo_bitmap.bin │ │ │ │ │ ├── demo_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── demo_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ ├── loopback │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── loopback_bitmap.bin │ │ │ │ │ ├── loopback_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── loopback_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ └── soc │ │ │ ├── constraints │ │ │ ├── clk.sdc │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ └── sbt │ │ │ │ └── outputs │ │ │ │ ├── bitmap │ │ │ │ └── soc_bitmap.bin │ │ │ │ ├── soc_sbt.rpt │ │ │ │ └── timer │ │ │ │ └── soc_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ └── python │ │ ├── demo │ │ ├── dump.py │ │ ├── fomu.py │ │ └── run.py │ │ └── loopback │ │ ├── fomu.py │ │ └── run.py ├── README.md ├── TinyFPGA-BX │ ├── OSS_CAD_Suite │ │ ├── Makefile │ │ ├── input │ │ │ ├── bootloader │ │ │ │ ├── gtkwave │ │ │ │ │ ├── app.state.map │ │ │ │ │ └── procs.tcl │ │ │ │ ├── hdl_files.mk │ │ │ │ ├── pins.pcf │ │ │ │ └── pre-pack.py │ │ │ ├── demo │ │ │ │ ├── gtkwave │ │ │ │ │ ├── app.cmd.map │ │ │ │ │ ├── app.state.map │ │ │ │ │ └── procs.tcl │ │ │ │ ├── hdl_files.mk │ │ │ │ ├── pins.pcf │ │ │ │ └── pre-pack.py │ │ │ ├── loopback │ │ │ │ ├── gtkwave │ │ │ │ │ └── procs.tcl │ │ │ │ ├── hdl_files.mk │ │ │ │ ├── pins.pcf │ │ │ │ └── pre-pack.py │ │ │ ├── loopback_2ch │ │ │ │ ├── gtkwave │ │ │ │ │ └── procs.tcl │ │ │ │ ├── hdl_files.mk │ │ │ │ ├── pins.pcf │ │ │ │ └── pre-pack.py │ │ │ ├── loopback_7ch │ │ │ │ ├── gtkwave │ │ │ │ │ └── procs.tcl │ │ │ │ ├── hdl_files.mk │ │ │ │ ├── pins.pcf │ │ │ │ └── pre-pack.py │ │ │ └── soc │ │ │ │ ├── hdl_files.mk │ │ │ │ ├── pins.pcf │ │ │ │ └── pre-pack.py │ │ └── output │ │ │ ├── bootloader │ │ │ ├── bootloader.bin │ │ │ ├── bootloader.rpt │ │ │ ├── fw_bootloader.bin │ │ │ ├── log_nextpnr_bootloader.txt │ │ │ └── log_yosys_bootloader.txt │ │ │ ├── demo │ │ │ ├── demo.bin │ │ │ ├── demo.rpt │ │ │ ├── log_nextpnr_demo.txt │ │ │ └── log_yosys_demo.txt │ │ │ ├── loopback │ │ │ ├── log_nextpnr_loopback.txt │ │ │ ├── log_yosys_loopback.txt │ │ │ ├── loopback.bin │ │ │ └── loopback.rpt │ │ │ ├── loopback_2ch │ │ │ ├── log_nextpnr_loopback_2ch.txt │ │ │ ├── log_yosys_loopback_2ch.txt │ │ │ ├── loopback_2ch.bin │ │ │ └── loopback_2ch.rpt │ │ │ ├── loopback_7ch │ │ │ ├── log_nextpnr_loopback_7ch.txt │ │ │ ├── log_yosys_loopback_7ch.txt │ │ │ ├── loopback_7ch.bin │ │ │ └── loopback_7ch.rpt │ │ │ └── soc │ │ │ ├── log_nextpnr_soc.txt │ │ │ ├── log_yosys_soc.txt │ │ │ ├── soc.bin │ │ │ └── soc.rpt │ ├── hdl │ │ ├── bootloader │ │ │ ├── app.v │ │ │ ├── bootloader.v │ │ │ ├── bootloader_tasks.v │ │ │ └── tb_bootloader.v │ │ ├── demo │ │ │ ├── app.v │ │ │ ├── demo.v │ │ │ ├── demo_fpga.vhd │ │ │ ├── demo_tasks.v │ │ │ └── tb_demo.v │ │ ├── loopback │ │ │ ├── loopback.v │ │ │ └── tb_loopback.v │ │ ├── loopback_2ch │ │ │ ├── loopback_2ch.v │ │ │ └── tb_loopback_2ch.v │ │ ├── loopback_7ch │ │ │ ├── loopback_7ch.v │ │ │ └── tb_loopback_7ch.v │ │ └── soc │ │ │ ├── app.v │ │ │ ├── soc.v │ │ │ └── tb_soc.v │ ├── iCEcube2 │ │ ├── bootloader │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── bootloader_bitmap.bin │ │ │ │ │ ├── bootloader_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── bootloader_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ ├── demo │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── demo_bitmap.bin │ │ │ │ │ ├── demo_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── demo_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ ├── demo_allverilog │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── demo_bitmap.bin │ │ │ │ │ ├── demo_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── demo_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ ├── loopback │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── loopback_bitmap.bin │ │ │ │ │ ├── loopback_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── loopback_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ ├── loopback_2ch │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── loopback_2ch_bitmap.bin │ │ │ │ │ ├── loopback_2ch_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── loopback_2ch_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ ├── loopback_7ch │ │ │ ├── constraints │ │ │ │ ├── clk.sdc │ │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── loopback_7ch_bitmap.bin │ │ │ │ │ ├── loopback_7ch_sbt.rpt │ │ │ │ │ └── timer │ │ │ │ │ └── loopback_7ch_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ │ └── soc │ │ │ ├── constraints │ │ │ ├── clk.sdc │ │ │ └── pins.pcf │ │ │ ├── usb_cdc_Implmnt │ │ │ └── sbt │ │ │ │ └── outputs │ │ │ │ ├── bitmap │ │ │ │ └── soc_bitmap.bin │ │ │ │ ├── soc_sbt.rpt │ │ │ │ └── timer │ │ │ │ └── soc_timing.rpt │ │ │ ├── usb_cdc_sbt.project │ │ │ └── usb_cdc_syn.prj │ └── python │ │ ├── bootloader │ │ ├── bootloader-1.0.1.bin │ │ ├── dump.py │ │ ├── run.py │ │ └── tinyfpga.py │ │ ├── demo │ │ ├── dump.py │ │ ├── run.py │ │ └── tinyfpga.py │ │ ├── loopback │ │ ├── run.py │ │ └── tinyfpga.py │ │ └── loopback_nch │ │ ├── list.py │ │ ├── pyusb.py │ │ ├── run.py │ │ └── tinyfpga.py └── common │ ├── gtkwave │ ├── ctrl_endp.dev_state.map │ ├── ctrl_endp.req.map │ ├── ctrl_endp.state.map │ ├── out_fifo.out_state.map │ ├── phy_rx.nrzi.map │ ├── phy_rx.rx_state.map │ ├── phy_rx.state.map │ ├── phy_tx.tx_state.map │ ├── procs.tcl │ ├── sie.phy_state.map │ └── sie.pid.map │ ├── hdl │ ├── fifo_if.v │ ├── flash │ │ ├── AT25SF081.v │ │ ├── flash_spi.v │ │ ├── init_cell_data.hex │ │ ├── init_cell_data_sec.hex │ │ └── spi.v │ ├── ice40 │ │ ├── SB_PLL40_CORE.v │ │ ├── SB_RAM256x16.v │ │ ├── cells_sim.v.patch │ │ ├── ram.v │ │ └── rom.v │ ├── prescaler.v │ ├── prescaler_rtl.vhd │ ├── sim_tasks.v │ ├── sync.v │ ├── usb_monitor.v │ ├── usb_rx_tasks.v │ ├── usb_tasks.v │ ├── usb_test_1ch.v │ ├── usb_test_2ch.v │ └── usb_test_7ch.v │ └── synplifypro │ └── usb_cdc.sdc ├── readme_files ├── bit_samples.png ├── fifo_protocol.png ├── fifo_timings.png ├── sync.png ├── usb_cdc.png └── usb_cdc.vsdx └── usb_cdc ├── README.md ├── bulk_endp.v ├── ctrl_endp.v ├── in_fifo.v ├── out_fifo.v ├── phy_rx.v ├── phy_tx.v ├── sie.v └── usb_cdc.v /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/README.md 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