├── readme_files ├── sync.png ├── usb_cdc.png ├── usb_cdc.vsdx ├── bit_samples.png ├── fifo_timings.png └── fifo_protocol.png ├── examples ├── TinyFPGA-BX │ ├── OSS_CAD_Suite │ │ ├── input │ │ │ ├── bootloader │ │ │ │ ├── pre-pack.py │ │ │ │ ├── gtkwave │ │ │ │ │ ├── app.state.map │ │ │ │ │ └── procs.tcl │ │ │ │ ├── pins.pcf │ │ │ │ └── hdl_files.mk │ │ │ ├── loopback │ │ │ │ ├── pre-pack.py │ │ │ │ ├── pins.pcf │ │ │ │ ├── hdl_files.mk │ │ │ │ └── gtkwave │ │ │ │ │ └── procs.tcl │ │ │ ├── demo │ │ │ │ ├── pre-pack.py │ │ │ │ ├── pins.pcf │ │ │ │ ├── gtkwave │ │ │ │ │ ├── app.cmd.map │ │ │ │ │ ├── app.state.map │ │ │ │ │ └── procs.tcl │ │ │ │ └── hdl_files.mk │ │ │ ├── loopback_7ch │ │ │ │ ├── pre-pack.py │ │ │ │ ├── pins.pcf │ │ │ │ ├── hdl_files.mk │ │ │ │ └── gtkwave │ │ │ │ │ └── procs.tcl │ │ │ ├── loopback_2ch │ │ │ │ ├── pre-pack.py │ │ │ │ ├── pins.pcf │ │ │ │ ├── hdl_files.mk │ │ │ │ └── gtkwave │ │ │ │ │ └── procs.tcl │ │ │ └── soc │ │ │ │ ├── pre-pack.py │ │ │ │ ├── pins.pcf │ │ │ │ └── hdl_files.mk │ │ ├── output │ │ │ ├── soc │ │ │ │ ├── soc.bin │ │ │ │ └── soc.rpt │ │ │ ├── demo │ │ │ │ ├── demo.bin │ │ │ │ └── demo.rpt │ │ │ ├── loopback │ │ │ │ └── loopback.bin │ │ │ ├── bootloader │ │ │ │ ├── bootloader.bin │ │ │ │ └── fw_bootloader.bin │ │ │ ├── loopback_2ch │ │ │ │ └── loopback_2ch.bin │ │ │ └── loopback_7ch │ │ │ │ └── loopback_7ch.bin │ │ └── Makefile │ ├── python │ │ ├── bootloader │ │ │ ├── bootloader-1.0.1.bin │ │ │ ├── dump.py │ │ │ └── run.py │ │ ├── loopback_nch │ │ │ ├── list.py │ │ │ ├── tinyfpga.py │ │ │ ├── pyusb.py │ │ │ └── run.py │ │ ├── demo │ │ │ ├── dump.py │ │ │ └── run.py │ │ └── loopback │ │ │ ├── run.py │ │ │ └── tinyfpga.py │ ├── iCEcube2 │ │ ├── soc │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── soc_bitmap.bin │ │ │ │ │ └── soc_sbt.rpt │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ ├── demo │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ └── bitmap │ │ │ │ │ └── demo_bitmap.bin │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ ├── loopback │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── loopback_bitmap.bin │ │ │ │ │ └── loopback_sbt.rpt │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ ├── demo_allverilog │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ └── bitmap │ │ │ │ │ └── demo_bitmap.bin │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ ├── bootloader │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ └── bitmap │ │ │ │ │ └── bootloader_bitmap.bin │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ ├── loopback_2ch │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ ├── bitmap │ │ │ │ │ └── loopback_2ch_bitmap.bin │ │ │ │ │ └── loopback_2ch_sbt.rpt │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ └── loopback_7ch │ │ │ ├── usb_cdc_Implmnt │ │ │ └── sbt │ │ │ │ └── outputs │ │ │ │ ├── bitmap │ │ │ │ └── loopback_7ch_bitmap.bin │ │ │ │ └── loopback_7ch_sbt.rpt │ │ │ ├── constraints │ │ │ ├── pins.pcf │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ └── hdl │ │ ├── bootloader │ │ ├── bootloader_tasks.v │ │ └── bootloader.v │ │ └── soc │ │ └── tb_soc.v ├── Fomu │ ├── OSS_CAD_Suite │ │ ├── output │ │ │ ├── soc │ │ │ │ ├── soc.bin │ │ │ │ └── soc.rpt │ │ │ ├── demo │ │ │ │ ├── demo.bin │ │ │ │ └── demo.rpt │ │ │ └── loopback │ │ │ │ ├── loopback.bin │ │ │ │ └── loopback.rpt │ │ ├── input │ │ │ ├── demo │ │ │ │ ├── pre-pack.py │ │ │ │ ├── gtkwave │ │ │ │ │ ├── app.cmd.map │ │ │ │ │ ├── app.state.map │ │ │ │ │ └── procs.tcl │ │ │ │ └── hdl_files.mk │ │ │ ├── soc │ │ │ │ ├── pre-pack.py │ │ │ │ └── hdl_files.mk │ │ │ └── loopback │ │ │ │ ├── pre-pack.py │ │ │ │ └── hdl_files.mk │ │ ├── pcf │ │ │ ├── fomu-pvt.pcf │ │ │ ├── fomu-hacker.pcf │ │ │ ├── fomu-evt2.pcf │ │ │ └── fomu-evt3.pcf │ │ └── Makefile │ ├── iCEcube2 │ │ ├── soc │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ └── bitmap │ │ │ │ │ └── soc_bitmap.bin │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ ├── demo │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ └── bitmap │ │ │ │ │ └── demo_bitmap.bin │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ ├── loopback │ │ │ ├── usb_cdc_Implmnt │ │ │ │ └── sbt │ │ │ │ │ └── outputs │ │ │ │ │ └── bitmap │ │ │ │ │ └── loopback_bitmap.bin │ │ │ ├── constraints │ │ │ │ ├── pins.pcf │ │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ │ └── demo_allverilog │ │ │ ├── usb_cdc_Implmnt │ │ │ └── sbt │ │ │ │ └── outputs │ │ │ │ └── bitmap │ │ │ │ └── demo_bitmap.bin │ │ │ ├── constraints │ │ │ ├── pins.pcf │ │ │ └── clk.sdc │ │ │ ├── usb_cdc_syn.prj │ │ │ └── usb_cdc_sbt.project │ ├── python │ │ ├── demo │ │ │ ├── dump.py │ │ │ └── run.py │ │ └── loopback │ │ │ ├── run.py │ │ │ └── fomu.py │ └── hdl │ │ └── loopback │ │ └── loopback.v ├── common │ ├── gtkwave │ │ ├── phy_rx.nrzi.map │ │ ├── out_fifo.out_state.map │ │ ├── ctrl_endp.dev_state.map │ │ ├── phy_tx.tx_state.map │ │ ├── phy_rx.rx_state.map │ │ ├── phy_rx.state.map │ │ ├── ctrl_endp.state.map │ │ ├── sie.pid.map │ │ ├── sie.phy_state.map │ │ └── ctrl_endp.req.map │ └── hdl │ │ ├── prescaler.v │ │ ├── prescaler_rtl.vhd │ │ ├── ice40 │ │ ├── cells_sim.v.patch │ │ ├── SB_RAM256x16.v │ │ └── SB_PLL40_CORE.v │ │ ├── usb_monitor.v │ │ ├── sync.v │ │ ├── sim_tasks.v │ │ └── fifo_if.v └── README.md └── LICENSE /readme_files/sync.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/readme_files/sync.png -------------------------------------------------------------------------------- /readme_files/usb_cdc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/readme_files/usb_cdc.png -------------------------------------------------------------------------------- /readme_files/usb_cdc.vsdx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/readme_files/usb_cdc.vsdx -------------------------------------------------------------------------------- /readme_files/bit_samples.png: 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ctx.addClock("clk_pll", 48) 3 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/pre-pack.py: -------------------------------------------------------------------------------- 1 | ctx.addClock("clk", 16) 2 | ctx.addClock("clk_pll", 48) 3 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/output/soc/soc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/examples/Fomu/OSS_CAD_Suite/output/soc/soc.bin -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/output/demo/demo.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/examples/Fomu/OSS_CAD_Suite/output/demo/demo.bin -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/pre-pack.py: -------------------------------------------------------------------------------- 1 | ctx.addClock("clk", 16) 2 | ctx.addClock("clk_pll", 48) 3 | ctx.addClock("clk_div8", 2) 4 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback_7ch/pre-pack.py: -------------------------------------------------------------------------------- 1 | ctx.addClock("clk", 16) 2 | ctx.addClock("clk_pll", 48) 3 | ctx.addClock("clk_div4", 12) 4 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/output/soc/soc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/examples/TinyFPGA-BX/OSS_CAD_Suite/output/soc/soc.bin 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ctx.addClock("clk_12mhz", 12) 5 | -------------------------------------------------------------------------------- /examples/common/gtkwave/phy_rx.nrzi.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## phy_rx\.nrzi 3 | ## color ## Blue 4 | ## data ## Decimal 5 | 6 | 0 SE0 7 | 1 DJ 8 | 2 DK 9 | 3 SE1 10 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/input/loopback/pre-pack.py: -------------------------------------------------------------------------------- 1 | ctx.addClock("clki", 48) 2 | ctx.addClock("clk", 48) 3 | ctx.addClock("clk_3mhz", 3) 4 | ctx.addClock("clk_12mhz", 12) 5 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/output/loopback/loopback.bin: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /examples/common/gtkwave/out_fifo.out_state.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## out_fifo\.out_state 3 | ## color ## Blue 4 | ## data ## Decimal 5 | 6 | 0 ST_OUT_IDLE 7 | 1 ST_OUT_DATA 8 | 2 ST_OUT_NAK 9 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/bitmap/soc_bitmap.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/examples/Fomu/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/bitmap/soc_bitmap.bin -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo/usb_cdc_Implmnt/sbt/outputs/bitmap/demo_bitmap.bin: -------------------------------------------------------------------------------- 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name ## phy_rx\.rx_state_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 ST_IDLE 8 | 1 ST_SYNC 9 | 2 ST_DATA 10 | 3 ST_EOP 11 | 4 ST_ERR 12 | -------------------------------------------------------------------------------- /examples/common/gtkwave/phy_rx.state.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## phy_rx\.state_q 3 | ## name ## phy_rx\.state_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 ST_RESET 8 | 1 ST_DETACHED 9 | 2 ST_ATTACHED 10 | 3 ST_ENABLED 11 | 4 ST_DETACH -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_2ch/usb_cdc_Implmnt/sbt/outputs/bitmap/loopback_2ch_bitmap.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ulixxe/usb_cdc/HEAD/examples/TinyFPGA-BX/iCEcube2/loopback_2ch/usb_cdc_Implmnt/sbt/outputs/bitmap/loopback_2ch_bitmap.bin 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-------------------------------------------------------------------------------- 1 | # 2 | ## name ## \.pid 3 | ## color ## Blue 4 | ## data ## Binary 5 | 6 | 0000 PID_RESERVED 7 | 0001 PID_OUT 8 | 1001 PID_IN 9 | 0101 PID_SOF 10 | 1101 PID_SETUP 11 | 0011 PID_DATA0 12 | 1011 PID_DATA1 13 | 0010 PID_ACK 14 | 1010 PID_NAK 15 | 1110 PID_STALL 16 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/input/demo/gtkwave/app.cmd.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## app\.cmd_q 3 | ## name ## app\.cmd_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 NO_CMD 8 | 1 IN_CMD 9 | 2 OUT_CMD 10 | 3 WAIT_CMD 11 | 4 LFSR_WRITE_CMD 12 | 5 LFSR_READ_CMD 13 | 6 ROM_READ_CMD 14 | 7 RAM_READ_CMD 15 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/soc/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/gtkwave/app.state.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## app\.state_q 3 | ## name ## app\.state_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 ST_IDLE 8 | 1 ST_WR_LO_LENGTH 9 | 2 ST_WR_HI_LENGTH 10 | 3 ST_RD_LO_LENGTH 11 | 4 ST_RD_HI_LENGTH 12 | 5 ST_WR_DATA 13 | 6 ST_RD_DATA 14 | 7 ST_BOOT 15 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/soc/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback_2ch/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback_7ch/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_2ch/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_7ch/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # Fomu 3 | # ############################################################################## 4 | 5 | set_io rgb0 A5 6 | set_io rgb1 B5 7 | set_io rgb2 C5 8 | set_io clki F4 9 | set_io usb_dn A2 10 | set_io usb_dp A1 11 | set_io usb_dp_pu A4 12 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/soc/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # Fomu 3 | # ############################################################################## 4 | 5 | set_io rgb0 A5 6 | set_io rgb1 B5 7 | set_io rgb2 C5 8 | set_io clki F4 9 | set_io usb_dn A2 10 | set_io usb_dp A1 11 | set_io usb_dp_pu A4 12 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/loopback/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # Fomu 3 | # ############################################################################## 4 | 5 | set_io rgb0 A5 6 | set_io rgb1 B5 7 | set_io rgb2 C5 8 | set_io clki F4 9 | set_io usb_dn A2 10 | set_io usb_dp A1 11 | set_io usb_dp_pu A4 12 | 13 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo_allverilog/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # Fomu 3 | # ############################################################################## 4 | 5 | set_io rgb0 A5 6 | set_io rgb1 B5 7 | set_io rgb2 C5 8 | set_io clki F4 9 | set_io usb_dn A2 10 | set_io usb_dp A1 11 | set_io usb_dp_pu A4 12 | -------------------------------------------------------------------------------- /examples/common/gtkwave/sie.phy_state.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## sie\.phy_state_q 3 | ## name ## sie\.phy_state_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 PHY_IDLE 8 | 1 PHY_RX_PID 9 | 2 PHY_RX_ADDR 10 | 3 PHY_RX_ENDP 11 | 4 PHY_RX_DATA0 12 | 5 PHY_RX_DATA 13 | 6 PHY_RX_WAIT_EOP 14 | 7 PHY_TX_HANDSHAKE_PID 15 | 8 PHY_TX_DATA_PID 16 | 9 PHY_TX_DATA 17 | 10 PHY_TX_CRC16_0 18 | 11 PHY_TX_CRC16_1 -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | set_io sck G7 11 | set_io ss F7 12 | set_io sdo G6 13 | set_io sdi H7 14 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | set_io sck G7 11 | set_io ss F7 12 | set_io sdo G6 13 | set_io sdi H7 14 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | set_io sck G7 11 | set_io ss F7 12 | set_io sdo G6 13 | set_io sdi H7 14 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/bootloader/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | set_io sck G7 11 | set_io ss F7 12 | set_io sdo G6 13 | set_io sdi H7 14 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/input/demo/gtkwave/app.state.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## app\.state_q 3 | ## name ## app\.state_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 RESET_STATE 8 | 1 LOOPBACK_STATE 9 | 2 CMD0_STATE 10 | 3 CMD1_STATE 11 | 4 CMD2_STATE 12 | 5 CMD3_STATE 13 | 6 IN_STATE 14 | 7 OUT_STATE 15 | 8 READ0_STATE 16 | 9 READ1_STATE 17 | 10 READ2_STATE 18 | 11 READ3_STATE 19 | 12 READ_ROM_STATE 20 | 13 READ_RAM_STATE -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo_allverilog/constraints/pins.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | # TinyFPGA BX 3 | # ############################################################################## 4 | 5 | set_io usb_pu A3 6 | set_io usb_n A4 7 | set_io usb_p B4 8 | set_io led B3 9 | set_io clk B2 10 | set_io sck G7 11 | set_io ss F7 12 | set_io sdo G6 13 | set_io sdi H7 14 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/gtkwave/app.cmd.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## app\.cmd_q 3 | ## name ## app\.cmd_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 NO_CMD 8 | 1 IN_CMD 9 | 2 OUT_CMD 10 | 3 ADDR_CMD 11 | 4 WAIT_CMD 12 | 5 LFSR_WRITE_CMD 13 | 6 LFSR_READ_CMD 14 | 7 ROM_READ_CMD 15 | 8 RAM_READ_CMD 16 | 9 FLASH_READ_CMD 17 | 10 FLASH_WRITE_CMD 18 | 11 FLASH_READ_STATUS_CMD 19 | 12 FLASH_CLEAR_STATUS_CMD 20 | -------------------------------------------------------------------------------- /examples/common/gtkwave/ctrl_endp.req.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## ctrl_endp\.req_ 3 | ## color ## Blue 4 | ## data ## Decimal 5 | 6 | 0 REQ_NONE 7 | 1 REQ_CLEAR_FEATURE 8 | 2 REQ_GET_CONFIGURATION 9 | 3 REQ_GET_DESCRIPTOR 10 | 4 REQ_GET_DESCRIPTOR_DEVICE 11 | 5 REQ_GET_DESCRIPTOR_CONFIGURATION 12 | 6 REQ_GET_DESCRIPTOR_STRING 13 | 7 REQ_GET_INTERFACE 14 | 8 REQ_GET_STATUS 15 | 9 REQ_SET_ADDRESS 16 | 10 REQ_SET_CONFIGURATION 17 | 11 REQ_DUMMY 18 | 12 REQ_UNSUPPORTED 19 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/gtkwave/app.state.map: -------------------------------------------------------------------------------- 1 | # 2 | ## name ## app\.state_q 3 | ## name ## app\.state_d 4 | ## color ## Blue 5 | ## data ## Decimal 6 | 7 | 0 RESET_STATE 8 | 1 LOOPBACK_STATE 9 | 2 CMD0_STATE 10 | 3 CMD1_STATE 11 | 4 CMD2_STATE 12 | 5 CMD3_STATE 13 | 6 IN_STATE 14 | 7 OUT_STATE 15 | 8 READ0_STATE 16 | 9 READ1_STATE 17 | 10 READ2_STATE 18 | 11 READ3_STATE 19 | 12 READ_ROM_STATE 20 | 13 READ_RAM_STATE 21 | 14 READ_FLASH_STATE 22 | 15 WRITE_FLASH_STATE -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/input/loopback/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | loopback.v \ 13 | 14 | # Testbench HDL files 15 | TB_HDL_FILES = \ 16 | tb_loopback.v \ 17 | 18 | # list of HDL files directories separated by ":" 19 | VPATH = ../../../usb_cdc: \ 20 | ../hdl/loopback: \ 21 | ../../common/hdl: \ 22 | ../../common/hdl/ice40: \ 23 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/input/soc/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | fifo_if.v \ 13 | app.v \ 14 | soc.v \ 15 | 16 | # Testbench HDL files 17 | TB_HDL_FILES = \ 18 | tb_soc.v \ 19 | 20 | # list of HDL files directories separated by ":" 21 | VPATH = ../../../usb_cdc: \ 22 | ../hdl/soc: \ 23 | ../../common/hdl: \ 24 | ../../common/hdl/ice40: \ 25 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/soc/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | fifo_if.v \ 13 | app.v \ 14 | soc.v \ 15 | 16 | # Testbench HDL files 17 | TB_HDL_FILES = \ 18 | SB_PLL40_CORE.v \ 19 | tb_soc.v \ 20 | 21 | # list of HDL files directories separated by ":" 22 | VPATH = ../../../usb_cdc: \ 23 | ../hdl/soc: \ 24 | ../../common/hdl: \ 25 | ../../common/hdl/ice40: \ 26 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/input/demo/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | SB_RAM256x16.v \ 13 | rom.v \ 14 | ram.v \ 15 | app.v \ 16 | demo.v \ 17 | 18 | # Testbench HDL files 19 | TB_HDL_FILES = \ 20 | tb_demo.v \ 21 | 22 | # list of HDL files directories separated by ":" 23 | VPATH = ../../../usb_cdc: \ 24 | ../hdl/demo: \ 25 | ../../common/hdl: \ 26 | ../../common/hdl/ice40: \ 27 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | loopback.v \ 13 | 14 | # Testbench HDL files 15 | TB_HDL_FILES = \ 16 | SB_PLL40_CORE.v \ 17 | usb_monitor.v \ 18 | tb_loopback.v \ 19 | 20 | # list of HDL files directories separated by ":" 21 | VPATH = ../../../usb_cdc: \ 22 | ../hdl/loopback: \ 23 | ../../common/hdl: \ 24 | ../../common/hdl/ice40: \ 25 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback_2ch/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | loopback_2ch.v \ 13 | 14 | # Testbench HDL files 15 | TB_HDL_FILES = \ 16 | SB_PLL40_CORE.v \ 17 | usb_monitor.v \ 18 | tb_loopback_2ch.v \ 19 | 20 | # list of HDL files directories separated by ":" 21 | VPATH = ../../../usb_cdc: \ 22 | ../hdl/loopback_2ch: \ 23 | ../../common/hdl: \ 24 | ../../common/hdl/ice40: \ 25 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback_7ch/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | loopback_7ch.v \ 13 | 14 | # Testbench HDL files 15 | TB_HDL_FILES = \ 16 | SB_PLL40_CORE.v \ 17 | usb_monitor.v \ 18 | tb_loopback_7ch.v \ 19 | 20 | # list of HDL files directories separated by ":" 21 | VPATH = ../../../usb_cdc: \ 22 | ../hdl/loopback_7ch: \ 23 | ../../common/hdl: \ 24 | ../../common/hdl/ice40: \ 25 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | spi.v \ 12 | app.v \ 13 | bootloader.v \ 14 | 15 | # Testbench HDL files 16 | TB_HDL_FILES = \ 17 | SB_PLL40_CORE.v \ 18 | AT25SF081.v \ 19 | usb_monitor.v \ 20 | tb_bootloader.v \ 21 | 22 | # list of HDL files directories separated by ":" 23 | VPATH = ../../../usb_cdc: \ 24 | ../hdl/bootloader: \ 25 | ../../common/hdl: \ 26 | ../../common/hdl/ice40: \ 27 | ../../common/hdl/flash: \ 28 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/pcf/fomu-pvt.pcf: -------------------------------------------------------------------------------- 1 | set_io rgb0 A5 2 | set_io rgb1 B5 3 | set_io rgb2 C5 4 | set_io pmod_1 E4 5 | set_io pmod_2 D5 6 | set_io pmod_3 E5 7 | set_io pmod_4 F5 8 | set_io pmoda_1 E4 9 | set_io pmoda_2 D5 10 | set_io pmoda_3 E5 11 | set_io pmoda_4 F5 12 | set_io clki F4 13 | set_io user_1 E4 14 | set_io user_2 D5 15 | set_io user_3 E5 16 | set_io user_4 F5 17 | set_io touch_1 E4 18 | set_io touch_2 D5 19 | set_io touch_3 E5 20 | set_io touch_4 F5 21 | set_io spi_mosi F1 22 | set_io spi_miso E1 23 | set_io spi_clk D1 24 | set_io spi_io2 F2 25 | set_io spi_io3 B1 26 | set_io spi_cs C1 27 | set_io usb_dn A2 28 | set_io usb_dp A1 29 | set_io usb_dp_pu A4 30 | -------------------------------------------------------------------------------- /examples/common/hdl/prescaler.v: -------------------------------------------------------------------------------- 1 | 2 | module prescaler 3 | ( 4 | input clk_i, 5 | input rstn_i, 6 | output clk_div16_o, 7 | output clk_div8_o, 8 | output clk_div4_o, 9 | output clk_div2_o 10 | ); 11 | 12 | reg [3:0] prescaler_cnt; 13 | 14 | always @(posedge clk_i or negedge rstn_i) begin 15 | if (~rstn_i) begin 16 | prescaler_cnt <= 'd0; 17 | end else begin 18 | prescaler_cnt <= prescaler_cnt + 1; 19 | end 20 | end 21 | 22 | assign clk_div16_o = prescaler_cnt[3]; 23 | assign clk_div8_o = prescaler_cnt[2]; 24 | assign clk_div4_o = prescaler_cnt[1]; 25 | assign clk_div2_o = prescaler_cnt[0]; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/hdl_files.mk: -------------------------------------------------------------------------------- 1 | # HDL files 2 | HDL_FILES = \ 3 | phy_tx.v \ 4 | phy_rx.v \ 5 | sie.v \ 6 | ctrl_endp.v \ 7 | in_fifo.v \ 8 | out_fifo.v \ 9 | bulk_endp.v \ 10 | usb_cdc.v \ 11 | prescaler.v \ 12 | SB_RAM256x16.v \ 13 | rom.v \ 14 | ram.v \ 15 | spi.v \ 16 | flash_spi.v \ 17 | app.v \ 18 | demo.v \ 19 | 20 | # Testbench HDL files 21 | TB_HDL_FILES = \ 22 | SB_PLL40_CORE.v \ 23 | AT25SF081.v \ 24 | usb_monitor.v \ 25 | tb_demo.v \ 26 | 27 | # list of HDL files directories separated by ":" 28 | VPATH = ../../../usb_cdc: \ 29 | ../hdl/demo: \ 30 | ../../common/hdl: \ 31 | ../../common/hdl/ice40: \ 32 | ../../common/hdl/flash: \ 33 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/bootloader/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clk} -period [expr 1000 / 16.0] [get_ports {clk}] 8 | create_clock -name {clk_usb} -period $CLK_PERIOD [get_nets {clk_pll}] 9 | 10 | set_clock_groups -asynchronous -group {clk} -group {clk_usb} 11 | 12 | set_false_path -to [get_ports {led usb_pu}] 13 | 14 | set root_path "u_usb_cdc" 15 | source ../../../../common/synplifypro/usb_cdc.sdc 16 | 17 | set fid [open all_registers.txt w] 18 | file_puts $fid "all_registers:" [all_registers] 19 | close $fid 20 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/pcf/fomu-hacker.pcf: -------------------------------------------------------------------------------- 1 | # Configuration for the Fomu hacker board. 2 | set_io rgb0 A5 # Blue LED 3 | set_io rgb1 B5 # Green LED 4 | set_io rgb2 C5 # Red LED 5 | set_io clki F5 # Clock input from 48MHz Oscillator 6 | set_io spi_mosi F1 # SPI Master Out, Slave In Pin 7 | set_io spi_miso E1 # SPI Master In, Slave Out Pin 8 | set_io spi_clk D1 # SPI Master Clock Output Pin 9 | set_io spi_cs C1 # SPI Chip Select 10 | set_io user_1 F4 # User touch pad 1 11 | set_io user_2 E5 # User touch pad 2 12 | set_io user_3 E4 # User touch pad 3 13 | set_io user_4 F2 # User touch pad 4 14 | set_io usb_dn A2 # USB D- pad 15 | set_io usb_dp A4 # USB D+ pad 16 | set_io usb_dp_pu D5 # USB D+ pull up (indicates device connected) 17 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/loopback_nch/list.py: -------------------------------------------------------------------------------- 1 | import serial.tools.list_ports 2 | 3 | VID = 0x1D50 4 | PID = 0x6130 5 | device_list = [p for p in serial.tools.list_ports.comports() if p.vid == VID and p.pid == PID] 6 | for device in device_list: 7 | print (f"Device: {device.device}") 8 | print (f"name: {device.name}") 9 | print (f"description: {device.description}") 10 | print (f"hwid: {device.hwid}") 11 | print (f"vid: {device.vid}") 12 | print (f"pid: {device.pid}") 13 | print (f"serial_number: {device.serial_number}") 14 | print (f"location: {device.location}") 15 | print (f"manufacturer: {device.manufacturer}") 16 | print (f"product: {device.product}") 17 | print (f"interface: {device.interface}") 18 | print () 19 | 20 | -------------------------------------------------------------------------------- /examples/Fomu/python/demo/dump.py: -------------------------------------------------------------------------------- 1 | def data_dump(data, col=16): 2 | import ctypes 3 | 4 | s = '' 5 | n = 0 6 | lines = [] 7 | 8 | if len(data) == 0: 9 | return '' 10 | 11 | for i in range(0, len(data), col): 12 | line = '' 13 | line += '%04x: ' % (i) 14 | n += col 15 | 16 | for j in range(n-col, n): 17 | if j >= len(data): break 18 | line += '%02x ' % abs(data[j]) 19 | 20 | line += ' ' * (3 * col + 6 - len(line)) + '| ' 21 | 22 | for j in range(n-col, n): 23 | if j >= len(data): break 24 | c = data[j] if not (data[j] < 0x20 or data[j] > 0x7e) else '.' 25 | line += '%c' % c 26 | 27 | lines.append(line) 28 | return '\n'.join(lines) 29 | 30 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/demo/dump.py: -------------------------------------------------------------------------------- 1 | def data_dump(data, col=16): 2 | import ctypes 3 | 4 | s = '' 5 | n = 0 6 | lines = [] 7 | 8 | if len(data) == 0: 9 | return '' 10 | 11 | for i in range(0, len(data), col): 12 | line = '' 13 | line += '%04x: ' % (i) 14 | n += col 15 | 16 | for j in range(n-col, n): 17 | if j >= len(data): break 18 | line += '%02x ' % abs(data[j]) 19 | 20 | line += ' ' * (3 * col + 6 - len(line)) + '| ' 21 | 22 | for j in range(n-col, n): 23 | if j >= len(data): break 24 | c = data[j] if not (data[j] < 0x20 or data[j] > 0x7e) else '.' 25 | line += '%c' % c 26 | 27 | lines.append(line) 28 | return '\n'.join(lines) 29 | 30 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/bootloader/dump.py: -------------------------------------------------------------------------------- 1 | def data_dump(data, col=16): 2 | import ctypes 3 | 4 | s = '' 5 | n = 0 6 | lines = [] 7 | 8 | if len(data) == 0: 9 | return '' 10 | 11 | for i in range(0, len(data), col): 12 | line = '' 13 | line += '%04x: ' % (i) 14 | n += col 15 | 16 | for j in range(n-col, n): 17 | if j >= len(data): break 18 | line += '%02x ' % abs(data[j]) 19 | 20 | line += ' ' * (3 * col + 6 - len(line)) + '| ' 21 | 22 | for j in range(n-col, n): 23 | if j >= len(data): break 24 | c = data[j] if not (data[j] < 0x20 or data[j] > 0x7e) else '.' 25 | line += '%c' % c 26 | 27 | lines.append(line) 28 | return '\n'.join(lines) 29 | 30 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/pcf/fomu-evt2.pcf: -------------------------------------------------------------------------------- 1 | set_io rgb0 39 2 | set_io rgb1 40 3 | set_io rgb2 41 4 | set_io pmoda_1 25 5 | set_io pmoda_2 26 6 | set_io pmoda_3 27 7 | set_io pmoda_4 28 8 | set_io pmod_1 25 9 | set_io pmod_2 26 10 | set_io pmod_3 27 11 | set_io pmod_4 28 12 | set_io clki_alt 20 13 | set_io clki 44 14 | set_io user_1 48 15 | set_io user_2 47 16 | set_io user_3 46 17 | set_io user_4 45 18 | set_io user_5 42 19 | set_io user_6 38 20 | set_io spi_mosi 14 21 | set_io spi_miso 17 22 | set_io spi_clk 15 23 | set_io spi_io2 18 24 | set_io spi_io3 19 25 | set_io spi_cs 16 26 | set_io uart_tx 21 27 | set_io uart_rx 13 28 | set_io usb_dn 37 29 | set_io usb_dp 34 30 | set_io usb_dp_pu 35 31 | set_io usb_dn_pu 36 32 | set_io dbg_1 20 33 | set_io dbg_2 12 34 | set_io dbg_3 11 35 | set_io dbg_4 23 36 | set_io dbg_5 10 37 | set_io dbg_6 9 38 | -------------------------------------------------------------------------------- /examples/Fomu/python/loopback/run.py: -------------------------------------------------------------------------------- 1 | import fomu 2 | import binascii 3 | import time 4 | import os 5 | 6 | 7 | ser = fomu.open() 8 | 9 | length = 1024 10 | i = 10000 11 | while i > 0: 12 | print(f"{str(i).rjust(6)} ", end = "\r") 13 | wr_data = os.urandom(length) 14 | ser.write(wr_data) 15 | rd_data = ser.read(length) 16 | if (rd_data != wr_data): 17 | print(f"\033[91m") 18 | print(f"ERROR: data mismatch!") 19 | print(f" actual:\n{binascii.hexlify(rd_data)}") 20 | print(f" expected:\n{binascii.hexlify(wr_data)}") 21 | print(f"\033[0m") 22 | i = 0 23 | i -= 1 24 | 25 | time.sleep(1) 26 | if (ser.inWaiting() != 0): 27 | print(f"\033[91m") 28 | print(f"ERROR: read buffer not empty!") 29 | print(f"{binascii.hexlify(ser.read(ser.inWaiting()))}") 30 | print(f"\033[0m") 31 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/pcf/fomu-evt3.pcf: -------------------------------------------------------------------------------- 1 | set_io rgb0 39 2 | set_io rgb1 40 3 | set_io rgb2 41 4 | set_io pmod_1 28 5 | set_io pmod_2 27 6 | set_io pmod_3 26 7 | set_io pmod_4 23 8 | set_io pmoda_1 28 9 | set_io pmoda_2 27 10 | set_io pmoda_3 26 11 | set_io pmoda_4 23 12 | set_io clki_alt 20 13 | set_io clki 44 14 | set_io user_1 48 15 | set_io user_2 47 16 | set_io user_3 46 17 | set_io user_4 45 18 | set_io user_5 42 19 | set_io user_6 38 20 | set_io pmodb_1 48 21 | set_io pmodb_2 47 22 | set_io pmodb_3 46 23 | set_io pmodb_4 45 24 | set_io spi_mosi 14 25 | set_io spi_miso 17 26 | set_io spi_clk 15 27 | set_io spi_io2 18 28 | set_io spi_io3 19 29 | set_io spi_cs 16 30 | set_io uart_tx 21 31 | set_io uart_rx 13 32 | set_io usb_dn 37 33 | set_io usb_dp 34 34 | set_io usb_dp_pu 35 35 | set_io usb_dn_pu 36 36 | set_io dbg_1 20 37 | set_io dbg_2 12 38 | set_io dbg_3 11 39 | set_io dbg_4 25 40 | set_io dbg_5 10 41 | set_io dbg_6 9 42 | -------------------------------------------------------------------------------- /examples/Fomu/python/loopback/fomu.py: -------------------------------------------------------------------------------- 1 | import serial.tools.list_ports 2 | 3 | class bcolors: 4 | HEADER = '\033[95m' 5 | OKBLUE = '\033[94m' 6 | OKCYAN = '\033[96m' 7 | OKGREEN = '\033[92m' 8 | WARNING = '\033[93m' 9 | FAIL = '\033[91m' 10 | ENDC = '\033[0m' 11 | BOLD = '\033[1m' 12 | UNDERLINE = '\033[4m' 13 | 14 | def port(): 15 | VID = 0x1209 16 | PID = 0x5BF0 17 | device_list = serial.tools.list_ports.comports() 18 | portValue = None 19 | for device in device_list: 20 | if (device.vid != None or device.pid != None): 21 | if (device.vid == VID and device.pid == PID): 22 | portValue = device.device 23 | break 24 | return portValue 25 | 26 | 27 | def open(): 28 | portValue = port() 29 | if (portValue != None): 30 | ser = serial.Serial() 31 | ser.port = portValue 32 | ser.timeout = 1 #non-block read 33 | ser.writeTimeout = 2 #timeout for write 34 | ser.open() 35 | return ser 36 | else: 37 | return None 38 | -------------------------------------------------------------------------------- /examples/common/hdl/prescaler_rtl.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity prescaler is 6 | port ( 7 | clk_i : in std_logic; 8 | rstn_i : in std_logic; 9 | clk_div16_o : out std_logic; 10 | clk_div8_o : out std_logic; 11 | clk_div4_o : out std_logic; 12 | clk_div2_o : out std_logic); 13 | end entity prescaler; 14 | 15 | architecture rtl of prescaler is 16 | signal prescaler_cnt : unsigned(3 downto 0); 17 | begin 18 | 19 | p_prescaler : process (clk_i, rstn_i) is 20 | begin 21 | if rstn_i = '0' then 22 | prescaler_cnt <= (others => '0'); 23 | elsif clk_i'event and clk_i = '1' then 24 | prescaler_cnt <= prescaler_cnt + 1; 25 | end if; 26 | end process p_prescaler; 27 | 28 | clk_div16_o <= prescaler_cnt(3); 29 | clk_div8_o <= prescaler_cnt(2); 30 | clk_div4_o <= prescaler_cnt(1); 31 | clk_div2_o <= prescaler_cnt(0); 32 | 33 | end architecture rtl; 34 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clk} -period [expr 1000 / 16.0] [get_ports {clk}] 8 | create_clock -name {clk_usb} -period $CLK_PERIOD [get_nets {clk_pll}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_app} -source [get_ports {clk}] [get_nets {clk_div8}] -divide_by 8 12 | create_clock -name {clk_app} -period [expr 1000 / 2.0] [get_nets {clk_div8}] 13 | 14 | set_clock_groups -asynchronous -group {clk} -group {clk_app} -group {clk_usb} 15 | 16 | set_false_path -to [get_ports {led usb_pu}] 17 | 18 | set root_path "u_usb_cdc" 19 | source ../../../../common/synplifypro/usb_cdc.sdc 20 | 21 | set fid [open all_registers.txt w] 22 | file_puts $fid "all_registers:" [all_registers] 23 | close $fid 24 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/soc/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clk} -period [expr 1000 / 16.0] [get_ports {clk}] 8 | create_clock -name {clk_usb} -period $CLK_PERIOD [get_nets {clk_pll}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_app} -source [get_ports {clk}] [get_nets {clk_2mhz}] -divide_by 8 12 | create_clock -name {clk_app} -period [expr 1000 / 2.0] [get_nets {clk_2mhz}] 13 | 14 | set_clock_groups -asynchronous -group {clk} -group {clk_app} -group {clk_usb} 15 | 16 | set_false_path -to [get_ports {led usb_pu}] 17 | 18 | set root_path "u_usb_cdc" 19 | source ../../../../common/synplifypro/usb_cdc.sdc 20 | 21 | set fid [open all_registers.txt w] 22 | file_puts $fid "all_registers:" [all_registers] 23 | close $fid 24 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clk} -period [expr 1000 / 16.0] [get_ports {clk}] 8 | #create_clock -name {clk_app} -period [expr $CLK_PERIOD / 4.0] [get_nets {clk_pll}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_usb} -source [get_nets {clk_pll}] [get_nets {clk_div4}] -divide_by 4 12 | create_clock -name {clk_usb} -period [expr $CLK_PERIOD] [get_nets {clk_pll}] 13 | 14 | set_clock_groups -asynchronous -group {clk} -group {clk_usb} 15 | 16 | set_false_path -to [get_ports {led usb_pu}] 17 | 18 | set root_path "u_usb_cdc" 19 | source ../../../../common/synplifypro/usb_cdc.sdc 20 | 21 | set fid [open all_registers.txt w] 22 | file_puts $fid "all_registers:" [all_registers] 23 | close $fid 24 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo_allverilog/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clk} -period [expr 1000 / 16.0] [get_ports {clk}] 8 | create_clock -name {clk_usb} -period $CLK_PERIOD [get_nets {clk_pll}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_app} -source [get_ports {clk}] [get_nets {clk_div8}] -divide_by 8 12 | create_clock -name {clk_app} -period [expr 1000 / 2.0] [get_nets {clk_div8}] 13 | 14 | set_clock_groups -asynchronous -group {clk} -group {clk_app} -group {clk_usb} 15 | 16 | set_false_path -to [get_ports {led usb_pu}] 17 | 18 | set root_path "u_usb_cdc" 19 | source ../../../../common/synplifypro/usb_cdc.sdc 20 | 21 | set fid [open all_registers.txt w] 22 | file_puts $fid "all_registers:" [all_registers] 23 | close $fid 24 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_7ch/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clk} -period [expr 1000 / 16.0] [get_ports {clk}] 8 | create_clock -name {clk_usb} -period [expr $CLK_PERIOD] [get_nets {clk_pll}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_usb} -source [get_nets {clk_pll}] [get_nets {clk_div4}] -divide_by 4 12 | create_clock -name {clk_app} -period [expr 1000 / 12.0] [get_nets {clk_div4}] 13 | 14 | set_clock_groups -asynchronous -group {clk} -group {clk_app} -group {clk_usb} 15 | 16 | set_false_path -to [get_ports {led usb_pu}] 17 | 18 | set root_path "u_usb_cdc" 19 | source ../../../../common/synplifypro/usb_cdc.sdc 20 | 21 | set fid [open all_registers.txt w] 22 | file_puts $fid "all_registers:" [all_registers] 23 | close $fid 24 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_2ch/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clk} -period [expr 1000 / 16.0] [get_ports {clk}] 8 | create_clock -name {clk_app} -period [expr $CLK_PERIOD / 4.0] [get_nets {clk_pll}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_usb} -source [get_nets {clk_pll}] [get_nets {clk_div4}] -divide_by 4 12 | create_clock -name {clk_usb} -period [expr $CLK_PERIOD] [get_nets {clk_div4}] 13 | 14 | set_clock_groups -asynchronous -group {clk} -group {clk_app} -group {clk_usb} 15 | 16 | set_false_path -to [get_ports {led usb_pu}] 17 | 18 | set root_path "u_usb_cdc" 19 | source ../../../../common/synplifypro/usb_cdc.sdc 20 | 21 | set fid [open all_registers.txt w] 22 | file_puts $fid "all_registers:" [all_registers] 23 | close $fid 24 | -------------------------------------------------------------------------------- /examples/Fomu/python/demo/run.py: -------------------------------------------------------------------------------- 1 | import fomu 2 | import time 3 | import os 4 | import base64 5 | 6 | 7 | ser = fomu.open() 8 | fomu.wait(0, ser) 9 | fomu.lfsr_write(0, ser) 10 | fomu.lfsr_read(ser) 11 | 12 | data = b'\x00\x01\x02\x03' 13 | fomu.outdata(data, ser) 14 | fomu.outdata(os.urandom(100000), ser) 15 | 16 | fomu.indata(100000, ser) 17 | 18 | ser.write(bytearray([0x31]*10)) 19 | print(ser.read(10)) 20 | 21 | ser.write(b'Hello World!' * 100) 22 | print(ser.read(1200)) 23 | 24 | fomu.ram_read(1028, ser, 2) 25 | fomu.rom_read(1028, ser, 1) 26 | 27 | length = 1024 28 | RAM_DATA = bytearray((base64.b64encode(os.urandom(length)).decode('utf-8')[0:length]).encode()) 29 | ser.write(RAM_DATA) 30 | time.sleep(1) 31 | ser.read(ser.inWaiting()) 32 | ser.write(b'\x00\x08' + (length-1).to_bytes(3, 'little')) 33 | data = bytearray(length) 34 | data = ser.read(length) 35 | if (data != RAM_DATA): 36 | print(f"\033[91mERROR: RAM data mismatch!\033[0m") 37 | 38 | time.sleep(1) 39 | if (ser.inWaiting() != 0): 40 | print(f"\033[91mERROR: read buffer not empty!\033[0m") 41 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 ulixxe 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/loopback/run.py: -------------------------------------------------------------------------------- 1 | import tinyfpga 2 | import binascii 3 | import time 4 | import os 5 | import random 6 | 7 | #tinyfpga.boot() 8 | 9 | ser = tinyfpga.open() 10 | 11 | def b2verilog(data): 12 | return str(len(data)) + "'h" + binascii.hexlify(data).decode().upper() 13 | 14 | def run(ser, runs): 15 | i = runs 16 | max_length = 4*1024 17 | while i > 0: 18 | length = int(min(random.expovariate(6/max_length), random.randint(int(max_length/2), max_length))) 19 | print(f"{str(ser.name).rjust(20)}: {str(i).rjust(6)}: {str(length).rjust(6)} ", end = "\r") 20 | wr_data = os.urandom(length) 21 | ser.write(wr_data) 22 | rd_data = ser.read(length) 23 | if (rd_data != wr_data): 24 | print(f"\033[91m") 25 | print(f"ERROR: data mismatch!") 26 | print(f" actual:\n{b2verilog(rd_data)}") 27 | print(f" expected:\n{b2verilog(wr_data)}") 28 | print(f"\033[0m") 29 | break 30 | i -= 1 31 | 32 | run(ser, 1000) 33 | 34 | time.sleep(1) 35 | if (ser.inWaiting() != 0): 36 | data = ser.read(ser.inWaiting()) 37 | print(f"\033[91m") 38 | print(f"ERROR: read buffer not empty!") 39 | print(f"{b2verilog(data)}") 40 | print(f"\033[0m") 41 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/loopback/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clki} -period [expr 1000 / 48.0] [get_ports {clki}] 8 | create_clock -name {clk_usb} -period [expr 1000 / 48.0] [get_nets {clk}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_3mhz} -source [get_nets {clk}] [get_nets {clk_3mhz}] -divide_by 16 12 | #create_generated_clock -name {clk_app} -source [get_nets {clk}] [get_nets {clk_12mhz}] -divide_by 4 13 | #create_clock -name {clk_3mhz} -period [expr 1000 / 3.0] [get_nets {clk_3mhz}] 14 | create_clock -name {clk_app} -period [expr 1000 / 12.0] [get_nets {clk_12mhz}] 15 | 16 | set_clock_groups -asynchronous -group {clki} -group {clk_app} -group {clk_usb} 17 | 18 | set_false_path -to [get_ports {rgb* usb_dp_pu}] 19 | 20 | set root_path "u_usb_cdc" 21 | source ../../../../common/synplifypro/usb_cdc.sdc 22 | 23 | set fid [open all_registers.txt w] 24 | file_puts $fid "all_registers:" [all_registers] 25 | close $fid 26 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clki} -period [expr 1000 / 48.0] [get_ports {clki}] 8 | create_clock -name {clk_usb} -period [expr 1000 / 48.0] [get_nets {clk}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_3mhz} -source [get_nets {clk}] [get_nets {clk_3mhz}] -divide_by 16 12 | #create_generated_clock -name {clk_app} -source [get_nets {clk}] [get_nets {clk_12mhz}] -divide_by 4 13 | create_clock -name {clk_3mhz} -period [expr 1000 / 3.0] [get_nets {clk_3mhz}] 14 | create_clock -name {clk_app} -period [expr 1000 / 12.0] [get_nets {clk_12mhz}] 15 | 16 | set_clock_groups -asynchronous -group {clki} -group {clk_3mhz} -group {clk_app} -group {clk_usb} 17 | 18 | set_false_path -to [get_ports {rgb* usb_dp_pu}] 19 | 20 | set root_path "u_usb_cdc" 21 | source ../../../../common/synplifypro/usb_cdc.sdc 22 | 23 | set fid [open all_registers.txt w] 24 | file_puts $fid "all_registers:" [all_registers] 25 | close $fid 26 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/soc/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clki} -period [expr 1000 / 48.0] [get_ports {clki}] 8 | create_clock -name {clk_usb} -period [expr 1000 / 48.0] [get_nets {clk}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_3mhz} -source [get_nets {clk}] [get_nets {clk_3mhz}] -divide_by 16 12 | #create_generated_clock -name {clk_app} -source [get_nets {clk}] [get_nets {clk_12mhz}] -divide_by 4 13 | create_clock -name {clk_3mhz} -period [expr 1000 / 3.0] [get_nets {clk_3mhz}] 14 | create_clock -name {clk_app} -period [expr 1000 / 12.0] [get_nets {clk_12mhz}] 15 | 16 | set_clock_groups -asynchronous -group {clki} -group {clk_3mhz} -group {clk_app} -group {clk_usb} 17 | 18 | set_false_path -to [get_ports {rgb* usb_dp_pu}] 19 | 20 | set root_path "u_usb_cdc" 21 | source ../../../../common/synplifypro/usb_cdc.sdc 22 | 23 | set fid [open all_registers.txt w] 24 | file_puts $fid "all_registers:" [all_registers] 25 | close $fid 26 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo_allverilog/constraints/clk.sdc: -------------------------------------------------------------------------------- 1 | ####---- CreateClock list ---- 2 | set BIT_SAMPLES 4 3 | set BIT_PERIOD [expr 1000 / 12.0] 4 | set CLK_PERIOD [expr $BIT_PERIOD / $BIT_SAMPLES] 5 | set BYTE_PERIOD [expr $BIT_PERIOD * 8] 6 | 7 | create_clock -name {clki} -period [expr 1000 / 48.0] [get_ports {clki}] 8 | create_clock -name {clk_usb} -period [expr 1000 / 48.0] [get_nets {clk}] 9 | 10 | # Somehow "create_generated_clock" confuses SynplifyPro and induces it to mess with global buffers. 11 | #create_generated_clock -name {clk_3mhz} -source [get_nets {clk}] [get_nets {clk_3mhz}] -divide_by 16 12 | #create_generated_clock -name {clk_app} -source [get_nets {clk}] [get_nets {clk_12mhz}] -divide_by 4 13 | create_clock -name {clk_3mhz} -period [expr 1000 / 3.0] [get_nets {clk_3mhz}] 14 | create_clock -name {clk_app} -period [expr 1000 / 12.0] [get_nets {clk_12mhz}] 15 | 16 | set_clock_groups -asynchronous -group {clki} -group {clk_3mhz} -group {clk_app} -group {clk_usb} 17 | 18 | set_false_path -to [get_ports {rgb* usb_dp_pu}] 19 | 20 | set root_path "u_usb_cdc" 21 | source ../../../../common/synplifypro/usb_cdc.sdc 22 | 23 | set fid [open all_registers.txt w] 24 | file_puts $fid "all_registers:" [all_registers] 25 | close $fid 26 | -------------------------------------------------------------------------------- /examples/common/hdl/ice40/cells_sim.v.patch: -------------------------------------------------------------------------------- 1 | --- cells_sim.v.orig 2021-11-15 22:28:52.006942786 +0100 2 | +++ cells_sim.v 2021-12-07 18:51:55.789342565 +0100 3 | @@ -2394,37 +2394,6 @@ 4 | // SiliconBlue PLL Cells 5 | 6 | (* blackbox *) 7 | -module SB_PLL40_CORE ( 8 | - input REFERENCECLK, 9 | - output PLLOUTCORE, 10 | - output PLLOUTGLOBAL, 11 | - input EXTFEEDBACK, 12 | - input [7:0] DYNAMICDELAY, 13 | - output LOCK, 14 | - input BYPASS, 15 | - input RESETB, 16 | - input LATCHINPUTVALUE, 17 | - output SDO, 18 | - input SDI, 19 | - input SCLK 20 | -); 21 | - parameter FEEDBACK_PATH = "SIMPLE"; 22 | - parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; 23 | - parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; 24 | - parameter SHIFTREG_DIV_MODE = 1'b0; 25 | - parameter FDA_FEEDBACK = 4'b0000; 26 | - parameter FDA_RELATIVE = 4'b0000; 27 | - parameter PLLOUT_SELECT = "GENCLK"; 28 | - parameter DIVR = 4'b0000; 29 | - parameter DIVF = 7'b0000000; 30 | - parameter DIVQ = 3'b000; 31 | - parameter FILTER_RANGE = 3'b000; 32 | - parameter ENABLE_ICEGATE = 1'b0; 33 | - parameter TEST_MODE = 1'b0; 34 | - parameter EXTERNAL_DIVIDE_FACTOR = 1; 35 | -endmodule 36 | - 37 | -(* blackbox *) 38 | module SB_PLL40_PAD ( 39 | input PACKAGEPIN, 40 | output PLLOUTCORE, 41 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/input/demo/gtkwave/procs.tcl: -------------------------------------------------------------------------------- 1 | proc app {} { 2 | gtkwave::/Edit/Insert_Comment "APP" 3 | set sigFilterList [list \ 4 | {app\.cmd_q} \ 5 | {app\.byte_cnt_q} \ 6 | {app\.mem_addr_q} \ 7 | {app\.crc32_q} \ 8 | {app\.data_q} \ 9 | {app\.lfsr_q} \ 10 | {app\.state_q}\ 11 | ] 12 | addSignals $sigFilterList 13 | wavesFormat input/demo/gtkwave 14 | setData { {app\.byte_cnt_} } Decimal 15 | setData { {app\.mem_addr_} } Decimal 16 | } 17 | 18 | 19 | proc top {} { 20 | gtkwave::/Edit/Insert_Comment "TOP" 21 | set sigFilterList [list \ 22 | {^[^.]*\.test\[.*\]$} \ 23 | {^[^.]*\.dp_sense$} \ 24 | {^[^.]*\.dn_sense$} \ 25 | {^[^.]*\.errors$} \ 26 | ] 27 | addSignals $sigFilterList 28 | wavesFormat input/demo/gtkwave 29 | setData { {^[^.]*\.test\[.*\]$} } ASCII 30 | setColor { {^[^.]*\.test\[.*\]$} } Blue 31 | setColor { {^[^.]*\.errors$} } Red 32 | } 33 | 34 | set cmds "app top $cmds" 35 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/loopback/tinyfpga.py: -------------------------------------------------------------------------------- 1 | import serial.tools.list_ports 2 | 3 | class bcolors: 4 | HEADER = '\033[95m' 5 | OKBLUE = '\033[94m' 6 | OKCYAN = '\033[96m' 7 | OKGREEN = '\033[92m' 8 | WARNING = '\033[93m' 9 | FAIL = '\033[91m' 10 | ENDC = '\033[0m' 11 | BOLD = '\033[1m' 12 | UNDERLINE = '\033[4m' 13 | 14 | def port(): 15 | VID = 0x1D50 16 | PID = 0x6130 17 | device_list = serial.tools.list_ports.comports() 18 | portValue = None 19 | for device in device_list: 20 | if (device.vid != None or device.pid != None): 21 | if (device.vid == VID and device.pid == PID): 22 | portValue = device.device 23 | break 24 | return portValue 25 | 26 | 27 | def boot(): 28 | portValue = port() 29 | if (portValue != None): 30 | print(f"TinyFPGA is on {portValue}") 31 | ser = serial.Serial(portValue) 32 | ser.timeout = 1 #non-block read 33 | ser.write(b'\x00') 34 | ser.close() 35 | else: 36 | print(f"{bcolors.FAIL}TinyFPGA not found!{bcolors.ENDC}") 37 | 38 | def open(): 39 | portValue = port() 40 | if (portValue != None): 41 | ser = serial.Serial() 42 | ser.port = portValue 43 | ser.timeout = 1 #non-block read 44 | ser.write_timeout = 10 #timeout for write 45 | ser.open() 46 | return ser 47 | else: 48 | return None 49 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/bootloader/run.py: -------------------------------------------------------------------------------- 1 | import tinyfpga 2 | import time 3 | import os 4 | import base64 5 | import dump 6 | import filecmp 7 | 8 | #tinyfpga.boot() 9 | 10 | ser = tinyfpga.open() 11 | tinyfpga.wake(ser) 12 | 13 | with open("out.bin", "wb") as binary_file: 14 | binary_file.write(bytes(tinyfpga.read_data(0xA0, 135100, ser))) 15 | 16 | #with open("out.bin", "wb") as binary_file: 17 | # binary_file.write(bytes(tinyfpga.read_data(0x28000, 135100, ser))) 18 | 19 | #with open("out.bin", "wb") as binary_file: 20 | # binary_file.write(bytes(tinyfpga.read_data(0x0, 298940, ser))) 21 | 22 | if (filecmp.cmp("out.bin", "./bootloader-1.0.1.bin")): 23 | print(f"\033[94mOK: data is correct!\033[0m") 24 | else: 25 | print(f"\033[91mERROR: file missmatch!\033[0m") 26 | 27 | #tinyfpga.write_data(0x28000, tinyfpga.slurp("../../OSS_CAD_Suite/output/bootloader/bootloader.bin"), ser) 28 | #tinyfpga.write_data(0x0, tinyfpga.slurp("../../OSS_CAD_Suite/output/bootloader/fw_bootloader.bin"), ser) 29 | 30 | #tinyfpga.read_data(0x28000, 8*1024, ser, 2) 31 | tinyfpga.read_security_register(1, ser, 2) 32 | tinyfpga.read_security_register(2, ser, 2) 33 | 34 | #tinyfpga.write_data(0x70FFF, tinyfpga.slurp("out.hex"), ser) 35 | 36 | 37 | tinyfpga.sleep(ser) 38 | 39 | time.sleep(1) 40 | if (ser.inWaiting() != 0): 41 | print(f"\033[91mERROR: read buffer not empty!\033[0m") 42 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/loopback_nch/tinyfpga.py: -------------------------------------------------------------------------------- 1 | import serial.tools.list_ports 2 | 3 | class bcolors: 4 | HEADER = '\033[95m' 5 | OKBLUE = '\033[94m' 6 | OKCYAN = '\033[96m' 7 | OKGREEN = '\033[92m' 8 | WARNING = '\033[93m' 9 | FAIL = '\033[91m' 10 | ENDC = '\033[0m' 11 | BOLD = '\033[1m' 12 | UNDERLINE = '\033[4m' 13 | 14 | def ports(): 15 | VID = 0x1D50 16 | PID = 0x6130 17 | device_list = serial.tools.list_ports.comports() 18 | port_list = [] 19 | for device in device_list: 20 | if (device.vid != None or device.pid != None): 21 | if (device.vid == VID and device.pid == PID): 22 | port_list.append(device.device) 23 | return port_list 24 | 25 | 26 | def boot(): 27 | port_list = ports() 28 | if (len(port_list) > 0): 29 | for port in port_list: 30 | print(f"TinyFPGA is on {port}") 31 | ser = serial.Serial(port) 32 | ser.timeout = 1 #non-block read 33 | ser.write(b'\x00') 34 | ser.close() 35 | else: 36 | print(f"{bcolors.FAIL}TinyFPGA not found!{bcolors.ENDC}") 37 | 38 | def open(): 39 | port_list = ports() 40 | ser_list = [] 41 | if (len(port_list) > 0): 42 | for port in port_list: 43 | ser = serial.Serial() 44 | ser.port = port 45 | ser.timeout = 1 #non-block read 46 | ser.write_timeout = 10 #timeout for write 47 | ser.open() 48 | ser_list.append(ser) 49 | return ser_list 50 | else: 51 | return [] 52 | -------------------------------------------------------------------------------- /examples/common/hdl/usb_monitor.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/10 ps // time-unit/precision 2 | `define BIT_TIME (1000/12) 3 | 4 | module usb_monitor 5 | #(parameter MAX_BITS = 128, 6 | parameter MAX_BYTES = 8*1024) 7 | ( 8 | input usb_dp_i, 9 | input usb_dn_i 10 | ); 11 | 12 | localparam MAX_STRING = 8; 13 | 14 | integer errors; 15 | integer warnings; 16 | 17 | wire dp_sense; 18 | wire dn_sense; 19 | 20 | `include "usb_rx_tasks.v" 21 | 22 | reg [3:0] pid; 23 | reg [6:0] addr; 24 | reg [3:0] endp; 25 | reg [10:0] frame; 26 | reg [8*MAX_BYTES-1:0] data; 27 | reg [8*MAX_STRING-1:0] info; 28 | 29 | integer bytes; 30 | 31 | assign dp_sense = usb_dp_i; 32 | assign dn_sense = usb_dn_i; 33 | 34 | initial begin 35 | errors = 0; 36 | warnings = 0; 37 | forever begin 38 | packet_rx(pid, addr, endp, frame, data, bytes, 39 | `BIT_TIME, 1000000); 40 | case (pid) 41 | PID_OUT : info = "OUT"; 42 | PID_IN : info = "IN"; 43 | PID_SOF : info = "SOF"; 44 | PID_SETUP : info = "SETUP"; 45 | PID_DATA0 : info = "DATA0"; 46 | PID_DATA1 : info = "DATA1"; 47 | PID_ACK : info = "ACK"; 48 | PID_NAK : info = "NAK"; 49 | PID_STALL : info = "STALL"; 50 | default : info = ""; 51 | endcase 52 | end 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback/gtkwave/procs.tcl: -------------------------------------------------------------------------------- 1 | proc monitor {} { 2 | gtkwave::/Edit/Insert_Comment "MONITOR" 3 | set sigFilterList [list \ 4 | {u_usb_monitor\.info} \ 5 | {u_usb_monitor\.pid} \ 6 | {u_usb_monitor\.frame} \ 7 | {u_usb_monitor\.addr} \ 8 | {u_usb_monitor\.endp} \ 9 | {u_usb_monitor\.bytes} \ 10 | {u_usb_monitor\.data} \ 11 | {u_usb_monitor\.warnings}\ 12 | ] 13 | addSignals $sigFilterList 14 | #wavesFormat input/loopback/gtkwave 15 | setData { {u_usb_monitor\.info} } ASCII 16 | setColor { {u_usb_monitor\.info} } Blue 17 | setColor { {u_usb_monitor\.warnings} } Yellow 18 | } 19 | 20 | proc top {} { 21 | gtkwave::/Edit/Insert_Comment "TOP" 22 | set sigFilterList [list \ 23 | {^[^.]*\.test\[.*\]$} \ 24 | {^[^.]*\.dp_sense$} \ 25 | {^[^.]*\.dn_sense$} \ 26 | {^[^.]*\.usb_pu$} \ 27 | {^[^.]*\.errors$} \ 28 | ] 29 | addSignals $sigFilterList 30 | #wavesFormat input/loopback/gtkwave 31 | setData { {^[^.]*\.test\[.*\]$} } ASCII 32 | setColor { {^[^.]*\.test\[.*\]$} } Blue 33 | setColor { {^[^.]*\.errors$} } Red 34 | } 35 | 36 | set cmds "monitor top $cmds" 37 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback_2ch/gtkwave/procs.tcl: -------------------------------------------------------------------------------- 1 | proc monitor {} { 2 | gtkwave::/Edit/Insert_Comment "MONITOR" 3 | set sigFilterList [list \ 4 | {u_usb_monitor\.info} \ 5 | {u_usb_monitor\.pid} \ 6 | {u_usb_monitor\.frame} \ 7 | {u_usb_monitor\.addr} \ 8 | {u_usb_monitor\.endp} \ 9 | {u_usb_monitor\.bytes} \ 10 | {u_usb_monitor\.data} \ 11 | {u_usb_monitor\.warnings}\ 12 | ] 13 | addSignals $sigFilterList 14 | #wavesFormat input/loopback_2ch/gtkwave 15 | setData { {u_usb_monitor\.info} } ASCII 16 | setColor { {u_usb_monitor\.info} } Blue 17 | setColor { {u_usb_monitor\.warnings} } Yellow 18 | } 19 | 20 | proc top {} { 21 | gtkwave::/Edit/Insert_Comment "TOP" 22 | set sigFilterList [list \ 23 | {^[^.]*\.test\[.*\]$} \ 24 | {^[^.]*\.dp_sense$} \ 25 | {^[^.]*\.dn_sense$} \ 26 | {^[^.]*\.usb_pu$} \ 27 | {^[^.]*\.errors$} \ 28 | ] 29 | addSignals $sigFilterList 30 | #wavesFormat input/loopback_2ch/gtkwave 31 | setData { {^[^.]*\.test\[.*\]$} } ASCII 32 | setColor { {^[^.]*\.test\[.*\]$} } Blue 33 | setColor { {^[^.]*\.errors$} } Red 34 | } 35 | 36 | set cmds "monitor top $cmds" 37 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/loopback_7ch/gtkwave/procs.tcl: -------------------------------------------------------------------------------- 1 | proc monitor {} { 2 | gtkwave::/Edit/Insert_Comment "MONITOR" 3 | set sigFilterList [list \ 4 | {u_usb_monitor\.info} \ 5 | {u_usb_monitor\.pid} \ 6 | {u_usb_monitor\.frame} \ 7 | {u_usb_monitor\.addr} \ 8 | {u_usb_monitor\.endp} \ 9 | {u_usb_monitor\.bytes} \ 10 | {u_usb_monitor\.data} \ 11 | {u_usb_monitor\.warnings}\ 12 | ] 13 | addSignals $sigFilterList 14 | #wavesFormat input/loopback_2ch/gtkwave 15 | setData { {u_usb_monitor\.info} } ASCII 16 | setColor { {u_usb_monitor\.info} } Blue 17 | setColor { {u_usb_monitor\.warnings} } Yellow 18 | } 19 | 20 | proc top {} { 21 | gtkwave::/Edit/Insert_Comment "TOP" 22 | set sigFilterList [list \ 23 | {^[^.]*\.test\[.*\]$} \ 24 | {^[^.]*\.dp_sense$} \ 25 | {^[^.]*\.dn_sense$} \ 26 | {^[^.]*\.usb_pu$} \ 27 | {^[^.]*\.errors$} \ 28 | ] 29 | addSignals $sigFilterList 30 | #wavesFormat input/loopback_2ch/gtkwave 31 | setData { {^[^.]*\.test\[.*\]$} } ASCII 32 | setColor { {^[^.]*\.test\[.*\]$} } Blue 33 | setColor { {^[^.]*\.errors$} } Red 34 | } 35 | 36 | set cmds "monitor top $cmds" 37 | -------------------------------------------------------------------------------- /examples/common/hdl/sync.v: -------------------------------------------------------------------------------- 1 | 2 | module sync 3 | ( 4 | input rstn_i, 5 | 6 | input iclk_i, 7 | input [7:0] idata_i, 8 | input ivalid_i, 9 | output iready_o, 10 | 11 | input oclk_i, 12 | output [7:0] odata_o, 13 | output ovalid_o, 14 | input oready_i 15 | ); 16 | 17 | reg [1:0] iready_sq; 18 | reg iready_mask_q; 19 | reg [7:0] idata_q; 20 | 21 | assign iready_o = iready_sq[0] & ~iready_mask_q; 22 | 23 | always @(posedge iclk_i or negedge rstn_i) begin 24 | if (~rstn_i) begin 25 | iready_sq <= 2'b00; 26 | iready_mask_q <= 1'b0; 27 | idata_q <= 8'd0; 28 | end else begin 29 | iready_sq <= {~ovalid_mask_q, iready_sq[1]}; 30 | if (~iready_sq[0]) 31 | iready_mask_q <= 1'b0; 32 | else if (ivalid_i & ~iready_mask_q) begin 33 | idata_q <= idata_i; 34 | iready_mask_q <= 1'b1; 35 | end 36 | end 37 | end 38 | 39 | reg [1:0] ovalid_sq; 40 | reg ovalid_mask_q; 41 | 42 | assign ovalid_o = ovalid_sq[0] & ~ovalid_mask_q; 43 | assign odata_o = idata_q; 44 | 45 | always @(posedge oclk_i or negedge rstn_i) begin 46 | if (~rstn_i) begin 47 | ovalid_sq <= 2'b00; 48 | ovalid_mask_q <= 1'b0; 49 | end else begin 50 | ovalid_sq <= {iready_mask_q, ovalid_sq[1]}; 51 | if (~ovalid_sq[0]) 52 | ovalid_mask_q <= 1'b0; 53 | else if (oready_i & ~ovalid_mask_q) 54 | ovalid_mask_q <= 1'b1; 55 | end 56 | end 57 | endmodule 58 | 59 | 60 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/loopback_nch/pyusb.py: -------------------------------------------------------------------------------- 1 | import usb.core 2 | import usb.control 3 | import usb.util 4 | import usb.backend.libusb1 5 | import binascii 6 | 7 | 8 | def b2verilog(data): 9 | return str(len(data)) + "'h" + binascii.hexlify(data).decode().upper() 10 | 11 | backend = usb.backend.libusb1.get_backend(find_library=lambda x: "/opt/local/lib/libusb-1.0.dylib") 12 | dev = usb.core.find(idVendor=0x1D50, idProduct=0x6130) 13 | if dev is None: 14 | raise ValueError('Our device is not connected') 15 | 16 | print(dev) 17 | print() 18 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_DEVICE, 0))) 19 | print() 20 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_CONFIG, 0))) 21 | print() 22 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_STRING, 1)) + " --> " + usb.util.get_string(dev, 1)) 23 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_STRING, 2)) + " --> " + usb.util.get_string(dev, 2)) 24 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_STRING, 3)) + " --> " + usb.util.get_string(dev, 3)) 25 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_STRING, 4)) + " --> " + usb.util.get_string(dev, 4)) 26 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_STRING, 5)) + " --> " + usb.util.get_string(dev, 5)) 27 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_STRING, 6)) + " --> " + usb.util.get_string(dev, 6)) 28 | print(b2verilog(usb.control.get_descriptor(dev, 0x400, usb.util.DESC_TYPE_STRING, 7)) + " --> " + usb.util.get_string(dev, 7)) 29 | 30 | 31 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/loopback_nch/run.py: -------------------------------------------------------------------------------- 1 | import tinyfpga 2 | import binascii 3 | import time 4 | import os 5 | import random 6 | import threading 7 | import sys 8 | 9 | #tinyfpga.boot() 10 | 11 | 12 | def b2verilog(data): 13 | return str(len(data)) + "'h" + binascii.hexlify(data).decode().upper() 14 | 15 | def run(ser, runs, lock): 16 | i = runs 17 | max_length = 4*1024 18 | while i > 0: 19 | length = int(min(random.expovariate(6/max_length), random.randint(int(max_length/2), max_length))) 20 | with lock: 21 | print(f"{str(ser.name).rjust(20)}: {str(i).rjust(6)}: {str(length).rjust(6)} ", end = "\r") 22 | sys.stdout.flush() 23 | wr_data = os.urandom(length) 24 | ser.write(wr_data) 25 | rd_data = ser.read(length) 26 | if (rd_data != wr_data): 27 | print(f"\033[91m") 28 | print(f"ERROR: data mismatch!") 29 | print(f" actual:\n{b2verilog(rd_data)}") 30 | print(f" expected:\n{b2verilog(wr_data)}") 31 | print(f"\033[0m") 32 | break 33 | i -= 1 34 | 35 | def main(): 36 | ser_list = tinyfpga.open() 37 | lock = threading.Lock() 38 | print("Number of CDC channels:", len(ser_list)) 39 | threads = [] 40 | 41 | for ser in ser_list: 42 | thread = threading.Thread(target=run, args=(ser, 1000, lock)) 43 | threads.append(thread) 44 | for thread in threads: 45 | thread.start() 46 | for thread in threads: 47 | thread.join() 48 | 49 | time.sleep(1) 50 | for ser in ser_list: 51 | if (ser.inWaiting() != 0): 52 | data = ser.read(ser.inWaiting()) 53 | print(f"\033[91m") 54 | print(f"ERROR: read buffer not empty!") 55 | print(f"{b2verilog(data)}") 56 | print(f"\033[0m") 57 | return True 58 | 59 | if __name__ == '__main__': 60 | main() 61 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/python/demo/run.py: -------------------------------------------------------------------------------- 1 | import tinyfpga 2 | import time 3 | import os 4 | import base64 5 | import dump 6 | 7 | #tinyfpga.boot() 8 | 9 | ser = tinyfpga.open() 10 | tinyfpga.wait(0, ser) 11 | tinyfpga.lfsr_write(0, ser) 12 | tinyfpga.lfsr_read(ser) 13 | 14 | #data = b'\x00\x01\x02\x03' 15 | #tinyfpga.outdata(data, ser) 16 | for i in range(0, 20): 17 | tinyfpga.wait(i, ser) 18 | print(f"wait = {i}") 19 | tinyfpga.outdata(os.urandom(100000), ser) 20 | tinyfpga.indata(100000, ser) 21 | 22 | #ser.write(bytearray([0x31]*10)) 23 | #print(ser.read(10)) 24 | 25 | #ser.write(b'Hello World!' * 100) 26 | #print(ser.read(1200)) 27 | 28 | #tinyfpga.addr_write(0, ser) 29 | #tinyfpga.ram_read(1028, ser, 2) 30 | 31 | #tinyfpga.addr_write(0, ser) 32 | #tinyfpga.rom_read(1028, ser, 1) 33 | 34 | #length = 1024 35 | #RAM_DATA = bytearray((base64.b64encode(os.urandom(length)).decode('utf-8')[0:length]).encode()) 36 | 37 | #tinyfpga.addr_write(0, ser) 38 | #ser.write(RAM_DATA) 39 | #time.sleep(1) 40 | #ser.read(ser.inWaiting()) 41 | 42 | #tinyfpga.addr_write(0, ser) 43 | #ser.write(b'\x00\x08' + (length-1).to_bytes(3, 'little')) 44 | #data = bytearray(length) 45 | #data = ser.read(length) 46 | #if (data != RAM_DATA): 47 | # print(f"\033[91mERROR: RAM data mismatch!\033[0m") 48 | 49 | #tinyfpga.flash_status_read(ser) 50 | #tinyfpga.flash_clear_status(ser) 51 | 52 | #tinyfpga.addr_write(0xFF000, ser) 53 | #tinyfpga.flash_read(1024*4, ser, 2) 54 | 55 | #data = os.urandom(1024*4+0) 56 | #print(dump.data_dump(data)) 57 | #tinyfpga.addr_write(0xFF000, ser) 58 | #tinyfpga.flash_write(data, ser) 59 | 60 | #tinyfpga.flash_status_read(ser) 61 | 62 | tinyfpga.addr_write(0xFF000, ser) 63 | tinyfpga.flash_read(1024*4, ser, 2) 64 | 65 | tinyfpga.flash_status_read(ser) 66 | 67 | time.sleep(1) 68 | if (ser.inWaiting() != 0): 69 | print(f"\033[91mERROR: read buffer not empty!\033[0m") 70 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/hdl/bootloader/bootloader_tasks.v: -------------------------------------------------------------------------------- 1 | 2 | task automatic test_cmd 3 | ( 4 | input [7:0] opcode, 5 | input integer wr_length, 6 | input integer rd_length, 7 | input [6:0] address, 8 | input integer wMaxPacketSize, 9 | input time timeout, 10 | inout [15:0] dataout_toggle 11 | ); 12 | integer wr_total_length; 13 | begin : u_test_cmd_task 14 | wr_total_length = wr_length + 1; // add opcode 15 | 16 | test_data_out(address, ENDP_BULK, 17 | {8'h01, 18 | wr_total_length[7:0], wr_total_length[15:8], 19 | rd_length[7:0], rd_length[15:8], 20 | opcode}, 21 | 6, PID_ACK, wMaxPacketSize, timeout, 0, dataout_toggle); 22 | end 23 | endtask 24 | 25 | task automatic test_read 26 | ( 27 | input integer rd_addr, 28 | input [8*MAX_BYTES-1:0] data, 29 | input integer bytes, 30 | input [6:0] address, 31 | input integer in_wMaxPacketSize, 32 | input integer out_wMaxPacketSize, 33 | input time timeout, 34 | inout [15:0] datain_toggle, 35 | inout [15:0] dataout_toggle 36 | ); 37 | integer wr_length; 38 | integer rd_length; 39 | begin : u_test_read_task 40 | wr_length = 5; 41 | rd_length = bytes; 42 | 43 | test_data_out(address, ENDP_BULK, 44 | {8'h01, wr_length[7:0], wr_length[15:8], rd_length[7:0], rd_length[15:8], 45 | 8'h0B, rd_addr[23:16], rd_addr[15:8], rd_addr[7:0], 8'd0}, 46 | 10, PID_ACK, out_wMaxPacketSize, timeout, 0, dataout_toggle); 47 | test_data_in(address, ENDP_BULK, 48 | data, 49 | bytes, PID_ACK, in_wMaxPacketSize, timeout, 0, datain_toggle, ZLP); 50 | end 51 | endtask 52 | -------------------------------------------------------------------------------- /examples/common/hdl/sim_tasks.v: -------------------------------------------------------------------------------- 1 | 2 | `define assert_error(msg, signal, value) \ 3 | if ((signal) !== (value)) begin \ 4 | errors = errors + 1; \ 5 | $display("%c[1;31m",27); \ 6 | $display("ERROR @ %t: %s", $time, msg); \ 7 | $display(" actual: %x", signal); \ 8 | $display(" expected: %x", value); \ 9 | $display("%c[0m",27); \ 10 | #(1*`BIT_TIME); \ 11 | $finish; \ 12 | end 13 | 14 | `define report_error(msg) \ 15 | errors = errors + 1; \ 16 | $display("%c[1;31m",27); \ 17 | $display("ERROR @ %t\n %s", $time, msg); \ 18 | $display("%c[0m",27); \ 19 | #(1*`BIT_TIME); \ 20 | $finish; 21 | 22 | `define assert_warning(msg, signal, value) \ 23 | if ((signal) !== (value)) begin \ 24 | warnings = warnings + 1; \ 25 | $display("%c[1;31m",27); \ 26 | $display("WARNING @ %t: %s", $time, msg); \ 27 | $display(" actual: %x", signal); \ 28 | $display(" expected: %x", value); \ 29 | $display("%c[0m",27); \ 30 | end 31 | 32 | `define report_warning(msg) \ 33 | warnings = warnings + 1; \ 34 | $display("%c[1;33m",27); \ 35 | $display("WARNING @ %t\n %s", $time, msg); \ 36 | $display("%c[0m",27); 37 | 38 | `define report_end(msg) \ 39 | $display("%c[1;32m",27); \ 40 | $display("@ %t\n %s", $time, msg); \ 41 | $display("%c[0m",27); \ 42 | $finish; 43 | 44 | `define progress_bar(msg, end_ms) \ 45 | integer time_ms; \ 46 | initial begin \ 47 | time_ms = 0; \ 48 | forever begin \ 49 | #(1000000/83*`BIT_TIME); \ 50 | time_ms = time_ms + 1; \ 51 | $write("%4d ms", time_ms); \ 52 | if (end_ms > 0) \ 53 | $write(" (%3d%%)", 100*time_ms/end_ms); \ 54 | if (msg != "") \ 55 | $write(": %0s", msg); \ 56 | $write(" \015"); \ 57 | $fflush(32'h8000_0001); // flush STDOUT \ 58 | end \ 59 | end 60 | -------------------------------------------------------------------------------- /examples/README.md: -------------------------------------------------------------------------------- 1 | # USB_CDC Examples 2 | 3 | All the examples are built with both [Lattice iCEcube2](https://www.latticesemi.com/iCEcube2) and [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build) design flows. 4 | 5 | * Lattice design flow 6 | * Open `examples//iCEcube2//usb_cdc_sbt.project` file with iCEcube2. 7 | * OSS CAD Suite flow 8 | * inside `examples//OSS_CAD_Suite` run `make all PROJ=` 9 | 10 | Testbenches can be simulated with iverilog/GTKWave. 11 | To run them, inside `examples//OSS_CAD_Suite` run `make sim PROJ=`. Or run `make wave PROJ=` to show waveforms too. 12 | 13 | The GTKWave console makes available a few commands (such as `top`, `out`, `phy_rx`, etc.) to show various waveforms inside the design. 14 | 15 | ## `bootloader` 16 | The `bootloader` example implements an equivalent of the original TinyFPGA bootloader. It is fully compatible with the `tinyprog` programmer. 17 | 18 | ## `demo` 19 | Purpose of `demo` example is to test reliability and speed of USB CDC data transmission. 20 | These tests are executed with python script `examples//python/demo/run.py`. 21 | 22 | Here, RAM and ROM are instantiated to check USB IN/OUT transmissions. 23 | `demo` example allows to read and program TinyFPGA-BX FLASH memory too. 24 | 25 | ## `loopback` 26 | This is an example with minimal logic outside USB_CDC to test its functionality. 27 | 28 | A python script is provided to check it (`examples//python/loopback/run.py`). 29 | 30 | ## `soc` 31 | In `soc` example a FIFO interface is instantiated to allow USB_CDC interfacing to a cpu bus. 32 | 33 | `fifo_if` module has a bus protocol similar to RAM. Data to be written to `fifo_if` is provided on the same rising edge of write address/control signals. Data to be read from `fifo_if` is available on following rising edge after read address/control signals. 34 | 35 | 36 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/bootloader/gtkwave/procs.tcl: -------------------------------------------------------------------------------- 1 | proc app {} { 2 | gtkwave::/Edit/Insert_Comment "APP" 3 | set sigFilterList [list \ 4 | {app\.wr_length_q} \ 5 | {app\.rd_length_q} \ 6 | {app\.timer_q} \ 7 | {app\.state_q}\ 8 | ] 9 | addSignals $sigFilterList 10 | wavesFormat input/demo/gtkwave 11 | setData { {app\.timer_} } Decimal 12 | } 13 | 14 | proc monitor {} { 15 | gtkwave::/Edit/Insert_Comment "MONITOR" 16 | set sigFilterList [list \ 17 | {u_usb_monitor\.info} \ 18 | {u_usb_monitor\.pid} \ 19 | {u_usb_monitor\.frame} \ 20 | {u_usb_monitor\.addr} \ 21 | {u_usb_monitor\.endp} \ 22 | {u_usb_monitor\.bytes} \ 23 | {u_usb_monitor\.data} \ 24 | {u_usb_monitor\.warnings}\ 25 | ] 26 | addSignals $sigFilterList 27 | wavesFormat input/demo/gtkwave 28 | setData { {u_usb_monitor\.info} } ASCII 29 | setColor { {u_usb_monitor\.info} } Blue 30 | setColor { {u_usb_monitor\.warnings} } Yellow 31 | } 32 | 33 | proc top {} { 34 | gtkwave::/Edit/Insert_Comment "TOP" 35 | set sigFilterList [list \ 36 | {^[^.]*\.test\[.*\]$} \ 37 | {^[^.]*\.dp_sense$} \ 38 | {^[^.]*\.dn_sense$} \ 39 | {^[^.]*\.errors$} \ 40 | {^[^.]*\.csn$} \ 41 | {^[^.]*\.sck$} \ 42 | {^[^.]*\.mosi$} \ 43 | {^[^.]*\.miso$} \ 44 | ] 45 | addSignals $sigFilterList 46 | wavesFormat input/demo/gtkwave 47 | setData { {^[^.]*\.test\[.*\]$} } ASCII 48 | setColor { {^[^.]*\.test\[.*\]$} } Blue 49 | setColor { {^[^.]*\.errors$} } Red 50 | } 51 | 52 | set cmds "app monitor top $cmds" 53 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/input/demo/gtkwave/procs.tcl: -------------------------------------------------------------------------------- 1 | proc app {} { 2 | gtkwave::/Edit/Insert_Comment "APP" 3 | set sigFilterList [list \ 4 | {app\.cmd_q} \ 5 | {app\.byte_cnt_q} \ 6 | {app\.mem_addr_q} \ 7 | {app\.crc32_q} \ 8 | {app\.data_q} \ 9 | {app\.lfsr_q} \ 10 | {app\.state_q}\ 11 | ] 12 | addSignals $sigFilterList 13 | wavesFormat input/demo/gtkwave 14 | setData { {app\.byte_cnt_} } Decimal 15 | setData { {app\.mem_addr_} } Decimal 16 | } 17 | 18 | proc monitor {} { 19 | gtkwave::/Edit/Insert_Comment "MONITOR" 20 | set sigFilterList [list \ 21 | {u_usb_monitor\.info} \ 22 | {u_usb_monitor\.pid} \ 23 | {u_usb_monitor\.frame} \ 24 | {u_usb_monitor\.addr} \ 25 | {u_usb_monitor\.endp} \ 26 | {u_usb_monitor\.bytes} \ 27 | {u_usb_monitor\.data} \ 28 | {u_usb_monitor\.warnings}\ 29 | ] 30 | addSignals $sigFilterList 31 | wavesFormat input/demo/gtkwave 32 | setData { {u_usb_monitor\.info} } ASCII 33 | setColor { {u_usb_monitor\.info} } Blue 34 | setColor { {u_usb_monitor\.warnings} } Yellow 35 | } 36 | 37 | proc top {} { 38 | gtkwave::/Edit/Insert_Comment "TOP" 39 | set sigFilterList [list \ 40 | {^[^.]*\.test\[.*\]$} \ 41 | {^[^.]*\.dp_sense$} \ 42 | {^[^.]*\.dn_sense$} \ 43 | {^[^.]*\.errors$} \ 44 | {^[^.]*\.csn$} \ 45 | {^[^.]*\.sck$} \ 46 | {^[^.]*\.mosi$} \ 47 | {^[^.]*\.miso$} \ 48 | ] 49 | addSignals $sigFilterList 50 | wavesFormat input/demo/gtkwave 51 | setData { {^[^.]*\.test\[.*\]$} } ASCII 52 | setColor { {^[^.]*\.test\[.*\]$} } Blue 53 | setColor { {^[^.]*\.errors$} } Red 54 | } 55 | 56 | set cmds "app monitor top $cmds" 57 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../hdl/loopback/loopback.v" 15 | add_file -constraint -lib work "constraints/clk.sdc" 16 | #implementation: "usb_cdc_Implmnt" 17 | impl -add usb_cdc_Implmnt -type fpga 18 | 19 | #implementation attributes 20 | set_option -vlog_std v2001 21 | set_option -project_relative_includes 1 22 | 23 | #device options 24 | set_option -technology SBTiCE40 25 | set_option -part iCE40LP8K 26 | set_option -package CM81 27 | set_option -speed_grade 28 | set_option -part_companion "" 29 | 30 | #compilation/mapping options 31 | set_option -top_module "loopback" 32 | 33 | # mapper_options 34 | set_option -frequency auto 35 | set_option -write_verilog 0 36 | set_option -write_vhdl 0 37 | 38 | # Silicon Blue iCE40 39 | set_option -maxfan 10000 40 | set_option -disable_io_insertion 0 41 | set_option -pipe 1 42 | set_option -retiming 0 43 | set_option -update_models_cp 0 44 | set_option -fixgatedclocks 2 45 | set_option -fixgeneratedclocks 0 46 | 47 | # NFilter 48 | set_option -popfeed 0 49 | set_option -constprop 0 50 | set_option -createhierarchy 0 51 | 52 | # sequential_optimization_options 53 | set_option -symbolic_fsm_compiler 1 54 | 55 | # Compiler Options 56 | set_option -compiler_compatible 0 57 | set_option -resource_sharing 1 58 | 59 | #automatic place and route (vendor) options 60 | set_option -write_apr_constraint 1 61 | 62 | #set result format/file last 63 | project -result_format "edif" 64 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 65 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 66 | impl -active usb_cdc_Implmnt 67 | project -run synthesis -clean 68 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_2ch/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../hdl/loopback_2ch/loopback_2ch.v" 15 | add_file -constraint -lib work "constraints/clk.sdc" 16 | #implementation: "usb_cdc_Implmnt" 17 | impl -add usb_cdc_Implmnt -type fpga 18 | 19 | #implementation attributes 20 | set_option -vlog_std v2001 21 | set_option -project_relative_includes 1 22 | 23 | #device options 24 | set_option -technology SBTiCE40 25 | set_option -part iCE40LP8K 26 | set_option -package CM81 27 | set_option -speed_grade 28 | set_option -part_companion "" 29 | 30 | #compilation/mapping options 31 | set_option -top_module "loopback_2ch" 32 | 33 | # mapper_options 34 | set_option -frequency auto 35 | set_option -write_verilog 0 36 | set_option -write_vhdl 0 37 | 38 | # Silicon Blue iCE40 39 | set_option -maxfan 10000 40 | set_option -disable_io_insertion 0 41 | set_option -pipe 1 42 | set_option -retiming 0 43 | set_option -update_models_cp 0 44 | set_option -fixgatedclocks 2 45 | set_option -fixgeneratedclocks 0 46 | 47 | # NFilter 48 | set_option -popfeed 0 49 | set_option -constprop 0 50 | set_option -createhierarchy 0 51 | 52 | # sequential_optimization_options 53 | set_option -symbolic_fsm_compiler 1 54 | 55 | # Compiler Options 56 | set_option -compiler_compatible 0 57 | set_option -resource_sharing 1 58 | 59 | #automatic place and route (vendor) options 60 | set_option -write_apr_constraint 1 61 | 62 | #set result format/file last 63 | project -result_format "edif" 64 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 65 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 66 | impl -active usb_cdc_Implmnt 67 | project -run synthesis -clean 68 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_7ch/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../hdl/loopback_7ch/loopback_7ch.v" 15 | add_file -constraint -lib work "constraints/clk.sdc" 16 | #implementation: "usb_cdc_Implmnt" 17 | impl -add usb_cdc_Implmnt -type fpga 18 | 19 | #implementation attributes 20 | set_option -vlog_std v2001 21 | set_option -project_relative_includes 1 22 | 23 | #device options 24 | set_option -technology SBTiCE40 25 | set_option -part iCE40LP8K 26 | set_option -package CM81 27 | set_option -speed_grade 28 | set_option -part_companion "" 29 | 30 | #compilation/mapping options 31 | set_option -top_module "loopback_7ch" 32 | 33 | # mapper_options 34 | set_option -frequency auto 35 | set_option -write_verilog 0 36 | set_option -write_vhdl 0 37 | 38 | # Silicon Blue iCE40 39 | set_option -maxfan 10000 40 | set_option -disable_io_insertion 0 41 | set_option -pipe 1 42 | set_option -retiming 0 43 | set_option -update_models_cp 0 44 | set_option -fixgatedclocks 2 45 | set_option -fixgeneratedclocks 0 46 | 47 | # NFilter 48 | set_option -popfeed 0 49 | set_option -constprop 0 50 | set_option -createhierarchy 0 51 | 52 | # sequential_optimization_options 53 | set_option -symbolic_fsm_compiler 1 54 | 55 | # Compiler Options 56 | set_option -compiler_compatible 0 57 | set_option -resource_sharing 1 58 | 59 | #automatic place and route (vendor) options 60 | set_option -write_apr_constraint 1 61 | 62 | #set result format/file last 63 | project -result_format "edif" 64 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 65 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 66 | impl -active usb_cdc_Implmnt 67 | project -run synthesis -clean 68 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/loopback/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../hdl/loopback/loopback.v" 15 | add_file -constraint -lib work "constraints/clk.sdc" 16 | #implementation: "usb_cdc_Implmnt" 17 | impl -add usb_cdc_Implmnt -type fpga 18 | 19 | #implementation attributes 20 | set_option -vlog_std v2001 21 | set_option -project_relative_includes 1 22 | set_option -hdl_define -set PVT=1 23 | 24 | #device options 25 | set_option -technology SBTiCE40UP 26 | set_option -part iCE40UP5K 27 | set_option -package UWG30 28 | set_option -speed_grade 29 | set_option -part_companion "" 30 | 31 | #compilation/mapping options 32 | set_option -top_module "loopback" 33 | 34 | # mapper_options 35 | set_option -frequency auto 36 | set_option -write_verilog 0 37 | set_option -write_vhdl 0 38 | 39 | # Silicon Blue iCE40 40 | set_option -maxfan 10000 41 | set_option -disable_io_insertion 0 42 | set_option -pipe 1 43 | set_option -retiming 0 44 | set_option -update_models_cp 0 45 | set_option -fixgatedclocks 2 46 | set_option -fixgeneratedclocks 0 47 | 48 | # NFilter 49 | set_option -popfeed 0 50 | set_option -constprop 0 51 | set_option -createhierarchy 0 52 | 53 | # sequential_optimization_options 54 | set_option -symbolic_fsm_compiler 1 55 | 56 | # Compiler Options 57 | set_option -compiler_compatible 0 58 | set_option -resource_sharing 1 59 | 60 | #automatic place and route (vendor) options 61 | set_option -write_apr_constraint 1 62 | 63 | #set result format/file last 64 | project -result_format "edif" 65 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 66 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 67 | impl -active usb_cdc_Implmnt 68 | project -run synthesis -clean 69 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/bootloader/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/flash/spi.v" 14 | add_file -verilog -lib work "../../hdl/bootloader/app.v" 15 | add_file -verilog -lib work "../../hdl/bootloader/bootloader.v" 16 | add_file -constraint -lib work "constraints/clk.sdc" 17 | #implementation: "usb_cdc_Implmnt" 18 | impl -add usb_cdc_Implmnt -type fpga 19 | 20 | #implementation attributes 21 | set_option -vlog_std v2001 22 | set_option -project_relative_includes 1 23 | 24 | #device options 25 | set_option -technology SBTiCE40 26 | set_option -part iCE40LP8K 27 | set_option -package CM81 28 | set_option -speed_grade 29 | set_option -part_companion "" 30 | 31 | #compilation/mapping options 32 | set_option -top_module "bootloader" 33 | 34 | # mapper_options 35 | set_option -frequency auto 36 | set_option -write_verilog 0 37 | set_option -write_vhdl 0 38 | 39 | # Silicon Blue iCE40 40 | set_option -maxfan 10000 41 | set_option -disable_io_insertion 0 42 | set_option -pipe 1 43 | set_option -retiming 0 44 | set_option -update_models_cp 0 45 | set_option -fixgatedclocks 2 46 | set_option -fixgeneratedclocks 0 47 | 48 | # NFilter 49 | set_option -popfeed 0 50 | set_option -constprop 0 51 | set_option -createhierarchy 0 52 | 53 | # sequential_optimization_options 54 | set_option -symbolic_fsm_compiler 1 55 | 56 | # Compiler Options 57 | set_option -compiler_compatible 0 58 | set_option -resource_sharing 1 59 | 60 | #automatic place and route (vendor) options 61 | set_option -write_apr_constraint 1 62 | 63 | #set result format/file last 64 | project -result_format "edif" 65 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 66 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 67 | impl -active usb_cdc_Implmnt 68 | project -run synthesis -clean 69 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../../common/hdl/fifo_if.v" 15 | add_file -verilog -lib work "../../hdl/soc/app.v" 16 | add_file -verilog -lib work "../../hdl/soc/soc.v" 17 | add_file -constraint -lib work "constraints/clk.sdc" 18 | #implementation: "usb_cdc_Implmnt" 19 | impl -add usb_cdc_Implmnt -type fpga 20 | 21 | #implementation attributes 22 | set_option -vlog_std v2001 23 | set_option -project_relative_includes 1 24 | 25 | #device options 26 | set_option -technology SBTiCE40 27 | set_option -part iCE40LP8K 28 | set_option -package CM81 29 | set_option -speed_grade 30 | set_option -part_companion "" 31 | 32 | #compilation/mapping options 33 | set_option -top_module "soc" 34 | 35 | # mapper_options 36 | set_option -frequency auto 37 | set_option -write_verilog 0 38 | set_option -write_vhdl 0 39 | 40 | # Silicon Blue iCE40 41 | set_option -maxfan 10000 42 | set_option -disable_io_insertion 0 43 | set_option -pipe 1 44 | set_option -retiming 0 45 | set_option -update_models_cp 0 46 | set_option -fixgatedclocks 2 47 | set_option -fixgeneratedclocks 0 48 | 49 | # NFilter 50 | set_option -popfeed 0 51 | set_option -constprop 0 52 | set_option -createhierarchy 0 53 | 54 | # sequential_optimization_options 55 | set_option -symbolic_fsm_compiler 1 56 | 57 | # Compiler Options 58 | set_option -compiler_compatible 0 59 | set_option -resource_sharing 1 60 | 61 | #automatic place and route (vendor) options 62 | set_option -write_apr_constraint 1 63 | 64 | #set result format/file last 65 | project -result_format "edif" 66 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 67 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 68 | impl -active usb_cdc_Implmnt 69 | project -run synthesis -clean 70 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/soc/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../../common/hdl/fifo_if.v" 15 | add_file -verilog -lib work "../../hdl/soc/app.v" 16 | add_file -verilog -lib work "../../hdl/soc/soc.v" 17 | add_file -constraint -lib work "constraints/clk.sdc" 18 | #implementation: "usb_cdc_Implmnt" 19 | impl -add usb_cdc_Implmnt -type fpga 20 | 21 | #implementation attributes 22 | set_option -vlog_std v2001 23 | set_option -project_relative_includes 1 24 | set_option -hdl_define -set PVT=1 25 | 26 | #device options 27 | set_option -technology SBTiCE40UP 28 | set_option -part iCE40UP5K 29 | set_option -package UWG30 30 | set_option -speed_grade 31 | set_option -part_companion "" 32 | 33 | #compilation/mapping options 34 | set_option -top_module "soc" 35 | 36 | # mapper_options 37 | set_option -frequency auto 38 | set_option -write_verilog 0 39 | set_option -write_vhdl 0 40 | 41 | # Silicon Blue iCE40 42 | set_option -maxfan 10000 43 | set_option -disable_io_insertion 0 44 | set_option -pipe 1 45 | set_option -retiming 0 46 | set_option -update_models_cp 0 47 | set_option -fixgatedclocks 2 48 | set_option -fixgeneratedclocks 0 49 | 50 | # NFilter 51 | set_option -popfeed 0 52 | set_option -constprop 0 53 | set_option -createhierarchy 0 54 | 55 | # sequential_optimization_options 56 | set_option -symbolic_fsm_compiler 1 57 | 58 | # Compiler Options 59 | set_option -compiler_compatible 0 60 | set_option -resource_sharing 1 61 | 62 | #automatic place and route (vendor) options 63 | set_option -write_apr_constraint 1 64 | 65 | #set result format/file last 66 | project -result_format "edif" 67 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 68 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 69 | impl -active usb_cdc_Implmnt 70 | project -run synthesis -clean 71 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -vhdl -lib work "../../../common/hdl/prescaler_rtl.vhd" 14 | add_file -verilog -lib work "../../../common/hdl/ice40/rom.v" 15 | add_file -verilog -lib work "../../../common/hdl/ice40/ram.v" 16 | add_file -verilog -lib work "../../hdl/demo/app.v" 17 | add_file -vhdl -lib work "../../hdl/demo/demo_fpga.vhd" 18 | add_file -constraint -lib work "constraints/clk.sdc" 19 | #implementation: "usb_cdc_Implmnt" 20 | impl -add usb_cdc_Implmnt -type fpga 21 | 22 | #implementation attributes 23 | set_option -vlog_std v2001 24 | set_option -project_relative_includes 1 25 | set_option -hdl_define -set PVT=1 26 | 27 | #device options 28 | set_option -technology SBTiCE40UP 29 | set_option -part iCE40UP5K 30 | set_option -package UWG30 31 | set_option -speed_grade 32 | set_option -part_companion "" 33 | 34 | #compilation/mapping options 35 | set_option -top_module "demo" 36 | 37 | # mapper_options 38 | set_option -frequency auto 39 | set_option -write_verilog 0 40 | set_option -write_vhdl 0 41 | 42 | # Silicon Blue iCE40 43 | set_option -maxfan 10000 44 | set_option -disable_io_insertion 0 45 | set_option -pipe 1 46 | set_option -retiming 0 47 | set_option -update_models_cp 0 48 | set_option -fixgatedclocks 2 49 | set_option -fixgeneratedclocks 0 50 | 51 | # NFilter 52 | set_option -popfeed 0 53 | set_option -constprop 0 54 | set_option -createhierarchy 0 55 | 56 | # sequential_optimization_options 57 | set_option -symbolic_fsm_compiler 1 58 | 59 | # Compiler Options 60 | set_option -compiler_compatible 0 61 | set_option -resource_sharing 1 62 | 63 | #automatic place and route (vendor) options 64 | set_option -write_apr_constraint 1 65 | 66 | #set result format/file last 67 | project -result_format "edif" 68 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 69 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 70 | impl -active usb_cdc_Implmnt 71 | project -run synthesis -clean 72 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo_allverilog/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../../common/hdl/ice40/rom.v" 15 | add_file -verilog -lib work "../../../common/hdl/ice40/ram.v" 16 | add_file -verilog -lib work "../../hdl/demo/app.v" 17 | add_file -verilog -lib work "../../hdl/demo/demo.v" 18 | add_file -constraint -lib work "constraints/clk.sdc" 19 | #implementation: "usb_cdc_Implmnt" 20 | impl -add usb_cdc_Implmnt -type fpga 21 | 22 | #implementation attributes 23 | set_option -vlog_std v2001 24 | set_option -project_relative_includes 1 25 | set_option -hdl_define -set PVT=1 26 | 27 | #device options 28 | set_option -technology SBTiCE40UP 29 | set_option -part iCE40UP5K 30 | set_option -package UWG30 31 | set_option -speed_grade 32 | set_option -part_companion "" 33 | 34 | #compilation/mapping options 35 | set_option -top_module "demo" 36 | 37 | # mapper_options 38 | set_option -frequency auto 39 | set_option -write_verilog 0 40 | set_option -write_vhdl 0 41 | 42 | # Silicon Blue iCE40 43 | set_option -maxfan 10000 44 | set_option -disable_io_insertion 0 45 | set_option -pipe 1 46 | set_option -retiming 0 47 | set_option -update_models_cp 0 48 | set_option -fixgatedclocks 2 49 | set_option -fixgeneratedclocks 0 50 | 51 | # NFilter 52 | set_option -popfeed 0 53 | set_option -constprop 0 54 | set_option -createhierarchy 0 55 | 56 | # sequential_optimization_options 57 | set_option -symbolic_fsm_compiler 1 58 | 59 | # Compiler Options 60 | set_option -compiler_compatible 0 61 | set_option -resource_sharing 1 62 | 63 | #automatic place and route (vendor) options 64 | set_option -write_apr_constraint 1 65 | 66 | #set result format/file last 67 | project -result_format "edif" 68 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 69 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 70 | impl -active usb_cdc_Implmnt 71 | project -run synthesis -clean 72 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -vhdl -lib work "../../../common/hdl/prescaler_rtl.vhd" 14 | add_file -verilog -lib work "../../../common/hdl/ice40/rom.v" 15 | add_file -verilog -lib work "../../../common/hdl/ice40/ram.v" 16 | add_file -verilog -lib work "../../../common/hdl/flash/spi.v" 17 | add_file -verilog -lib work "../../../common/hdl/flash/flash_spi.v" 18 | add_file -verilog -lib work "../../hdl/demo/app.v" 19 | add_file -vhdl -lib work "../../hdl/demo/demo_fpga.vhd" 20 | add_file -constraint -lib work "constraints/clk.sdc" 21 | #implementation: "usb_cdc_Implmnt" 22 | impl -add usb_cdc_Implmnt -type fpga 23 | 24 | #implementation attributes 25 | set_option -vlog_std v2001 26 | set_option -project_relative_includes 1 27 | 28 | #device options 29 | set_option -technology SBTiCE40 30 | set_option -part iCE40LP8K 31 | set_option -package CM81 32 | set_option -speed_grade 33 | set_option -part_companion "" 34 | 35 | #compilation/mapping options 36 | set_option -top_module "demo" 37 | 38 | # mapper_options 39 | set_option -frequency auto 40 | set_option -write_verilog 0 41 | set_option -write_vhdl 0 42 | 43 | # Silicon Blue iCE40 44 | set_option -maxfan 10000 45 | set_option -disable_io_insertion 0 46 | set_option -pipe 1 47 | set_option -retiming 0 48 | set_option -update_models_cp 0 49 | set_option -fixgatedclocks 2 50 | set_option -fixgeneratedclocks 0 51 | 52 | # NFilter 53 | set_option -popfeed 0 54 | set_option -constprop 0 55 | set_option -createhierarchy 0 56 | 57 | # sequential_optimization_options 58 | set_option -symbolic_fsm_compiler 1 59 | 60 | # Compiler Options 61 | set_option -compiler_compatible 0 62 | set_option -resource_sharing 1 63 | 64 | #automatic place and route (vendor) options 65 | set_option -write_apr_constraint 1 66 | 67 | #set result format/file last 68 | project -result_format "edif" 69 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 70 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 71 | impl -active usb_cdc_Implmnt 72 | project -run synthesis -clean 73 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo_allverilog/usb_cdc_syn.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Project file /mnt/hgfs/Projects/Bitbucket/uf16/libs/uf16/fpga/TinyFPGA-BX/usb_cdc/usb_cdc_syn.prj 3 | #project files 4 | 5 | add_file -verilog -lib work "../../../../usb_cdc/phy_tx.v" 6 | add_file -verilog -lib work "../../../../usb_cdc/phy_rx.v" 7 | add_file -verilog -lib work "../../../../usb_cdc/sie.v" 8 | add_file -verilog -lib work "../../../../usb_cdc/ctrl_endp.v" 9 | add_file -verilog -lib work "../../../../usb_cdc/in_fifo.v" 10 | add_file -verilog -lib work "../../../../usb_cdc/out_fifo.v" 11 | add_file -verilog -lib work "../../../../usb_cdc/bulk_endp.v" 12 | add_file -verilog -lib work "../../../../usb_cdc/usb_cdc.v" 13 | add_file -verilog -lib work "../../../common/hdl/prescaler.v" 14 | add_file -verilog -lib work "../../../common/hdl/ice40/rom.v" 15 | add_file -verilog -lib work "../../../common/hdl/ice40/ram.v" 16 | add_file -verilog -lib work "../../../common/hdl/flash/spi.v" 17 | add_file -verilog -lib work "../../../common/hdl/flash/flash_spi.v" 18 | add_file -verilog -lib work "../../hdl/demo/app.v" 19 | add_file -verilog -lib work "../../hdl/demo/demo.v" 20 | add_file -constraint -lib work "constraints/clk.sdc" 21 | #implementation: "usb_cdc_Implmnt" 22 | impl -add usb_cdc_Implmnt -type fpga 23 | 24 | #implementation attributes 25 | set_option -vlog_std v2001 26 | set_option -project_relative_includes 1 27 | 28 | #device options 29 | set_option -technology SBTiCE40 30 | set_option -part iCE40LP8K 31 | set_option -package CM81 32 | set_option -speed_grade 33 | set_option -part_companion "" 34 | 35 | #compilation/mapping options 36 | set_option -top_module "demo" 37 | 38 | # mapper_options 39 | set_option -frequency auto 40 | set_option -write_verilog 0 41 | set_option -write_vhdl 0 42 | 43 | # Silicon Blue iCE40 44 | set_option -maxfan 10000 45 | set_option -disable_io_insertion 0 46 | set_option -pipe 1 47 | set_option -retiming 0 48 | set_option -update_models_cp 0 49 | set_option -fixgatedclocks 2 50 | set_option -fixgeneratedclocks 0 51 | 52 | # NFilter 53 | set_option -popfeed 0 54 | set_option -constprop 0 55 | set_option -createhierarchy 0 56 | 57 | # sequential_optimization_options 58 | set_option -symbolic_fsm_compiler 1 59 | 60 | # Compiler Options 61 | set_option -compiler_compatible 0 62 | set_option -resource_sharing 1 63 | 64 | #automatic place and route (vendor) options 65 | set_option -write_apr_constraint 1 66 | 67 | #set result format/file last 68 | project -result_format "edif" 69 | project -result_file ./usb_cdc_Implmnt/usb_cdc.edf 70 | project -log_file "./usb_cdc_Implmnt/usb_cdc.srr" 71 | impl -active usb_cdc_Implmnt 72 | project -run synthesis -clean 73 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/loopback/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../hdl/loopback/loopback.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40UP 63 | Device=5K 64 | DevicePackage=UWG30 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-loopback 70 | DesignView=_rt 71 | DesignCell=loopback 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 86 | derValue=1.32445 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../hdl/loopback/loopback.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40 63 | Device=LP8K 64 | DevicePackage=CM81 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-loopback 70 | DesignView=_rt 71 | DesignCell=loopback 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_2ch/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../hdl/loopback_2ch/loopback_2ch.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40 63 | Device=LP8K 64 | DevicePackage=CM81 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-loopback_2ch 70 | DesignView=_rt 71 | DesignCell=loopback_2ch 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_7ch/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../hdl/loopback_7ch/loopback_7ch.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40 63 | Device=LP8K 64 | DevicePackage=CM81 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-loopback_7ch 70 | DesignView=_rt 71 | DesignCell=loopback_7ch 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/soc/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../../common/hdl/fifo_if.v=work,../../hdl/soc/app.v=work,../../hdl/soc/soc.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40UP 63 | Device=5K 64 | DevicePackage=UWG30 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-soc 70 | DesignView=_rt 71 | DesignCell=soc 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../../common/hdl/fifo_if.v=work,../../hdl/soc/app.v=work,../../hdl/soc/soc.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40 63 | Device=LP8K 64 | DevicePackage=CM81 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-soc 70 | DesignView=_rt 71 | DesignCell=soc 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/bootloader/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/flash/spi.v=work,../../hdl/bootloader/app.v=work,../../hdl/bootloader/bootloader.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40 63 | Device=LP8K 64 | DevicePackage=CM81 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-bootloader 70 | DesignView=_rt 71 | DesignCell=bootloader 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler_rtl.vhd=work,../../../common/hdl/ice40/rom.v=work,../../../common/hdl/ice40/ram.v=work,../../hdl/demo/app.v=work,../../hdl/demo/demo_fpga.vhd=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40UP 63 | Device=5K 64 | DevicePackage=UWG30 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-demo 70 | DesignView=_rt 71 | DesignCell=demo 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/Fomu/iCEcube2/demo_allverilog/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../../common/hdl/ice40/rom.v=work,../../../common/hdl/ice40/ram.v=work,../../hdl/demo/app.v=work,../../hdl/demo/demo.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40UP 63 | Device=5K 64 | DevicePackage=UWG30 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-demo 70 | DesignView=_rt 71 | DesignCell=demo 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/common/hdl/ice40/SB_RAM256x16.v: -------------------------------------------------------------------------------- 1 | 2 | module SB_RAM256x16 3 | #(parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 4 | parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 5 | parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 6 | parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 7 | parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 8 | parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 9 | parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 10 | parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 11 | parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 12 | parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000, 13 | parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000, 14 | parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000, 15 | parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000, 16 | parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000, 17 | parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000, 18 | parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000) 19 | ( 20 | output [15:0] RDATA, 21 | input RCLK, 22 | input RCLKE, 23 | input RE, 24 | input [7:0] RADDR, 25 | input WCLK, 26 | input WCLKE, 27 | input WE, 28 | input [7:0] WADDR, 29 | input [15:0] MASK, 30 | input [15:0] WDATA 31 | ); 32 | 33 | SB_RAM40_4K #(.INIT_0(INIT_0), 34 | .INIT_1(INIT_1), 35 | .INIT_2(INIT_2), 36 | .INIT_3(INIT_3), 37 | .INIT_4(INIT_4), 38 | .INIT_5(INIT_5), 39 | .INIT_6(INIT_6), 40 | .INIT_7(INIT_7), 41 | .INIT_8(INIT_8), 42 | .INIT_9(INIT_9), 43 | .INIT_A(INIT_A), 44 | .INIT_B(INIT_B), 45 | .INIT_C(INIT_C), 46 | .INIT_D(INIT_D), 47 | .INIT_E(INIT_E), 48 | .INIT_F(INIT_F)) 49 | u_ram40_4k (.RDATA(RDATA), 50 | .RADDR({3'b0, RADDR}), 51 | .RCLK(RCLK), 52 | .RCLKE(RCLKE), 53 | .RE(RE), 54 | .WADDR({3'b0, WADDR}), 55 | .WCLK(WCLK), 56 | .WCLKE(WCLKE), 57 | .WDATA(WDATA), 58 | .WE(WE), 59 | .MASK(MASK)); 60 | endmodule 61 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo_allverilog/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler.v=work,../../../common/hdl/ice40/rom.v=work,../../../common/hdl/ice40/ram.v=work,../../../common/hdl/flash/spi.v=work,../../../common/hdl/flash/flash_spi.v=work,../../hdl/demo/app.v=work,../../hdl/demo/demo.v=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40 63 | Device=LP8K 64 | DevicePackage=CM81 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-demo 70 | DesignView=_rt 71 | DesignCell=demo 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/demo/usb_cdc_sbt.project: -------------------------------------------------------------------------------- 1 | [Project] 2 | ProjectVersion=2.0 3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29 4 | ProjectName=usb_cdc 5 | Vendor=SiliconBlue 6 | Synthesis=synplify 7 | ProjectVFiles=../../../../usb_cdc/phy_tx.v=work,../../../../usb_cdc/phy_rx.v=work,../../../../usb_cdc/sie.v=work,../../../../usb_cdc/ctrl_endp.v=work,../../../../usb_cdc/in_fifo.v=work,../../../../usb_cdc/out_fifo.v=work,../../../../usb_cdc/bulk_endp.v=work,../../../../usb_cdc/usb_cdc.v=work,../../../common/hdl/prescaler_rtl.vhd=work,../../../common/hdl/ice40/rom.v=work,../../../common/hdl/ice40/ram.v=work,../../../common/hdl/flash/spi.v=work,../../../common/hdl/flash/flash_spi.v=work,../../hdl/demo/app.v=work,../../hdl/demo/demo_fpga.vhd=work 8 | ProjectCFiles=constraints/clk.sdc 9 | CurImplementation=usb_cdc_Implmnt 10 | Implementations=usb_cdc_Implmnt 11 | StartFromSynthesis=yes 12 | IPGeneration=false 13 | 14 | [lse options] 15 | CarryChain=True 16 | CarryChainLength=0 17 | CommandLineOptions= 18 | EBRUtilization=100.00 19 | FSMEncodingStyle=Auto 20 | FixGatedClocks=True 21 | I/OInsertion=True 22 | IntermediateFileDump=False 23 | LoopLimit=1950 24 | MaximalFanout=10000 25 | MemoryInitialValueFileSearchPath= 26 | NumberOfCriticalPaths=3 27 | OptimizationGoal=Area 28 | PropagateConstants=True 29 | RAMStyle=Auto 30 | ROMStyle=Auto 31 | RWCheckOnRam=False 32 | RemoveDuplicateRegisters=True 33 | ResolvedMixedDrivers=False 34 | ResourceSharing=True 35 | TargetFrequency= 36 | TopLevelUnit= 37 | UseIORegister=Auto 38 | VHDL2008=False 39 | VerilogIncludeSearchPath= 40 | 41 | [tool options] 42 | PlacerEffortLevel=std 43 | PlacerAutoLutCascade=yes 44 | PlacerAutoRamCascade=yes 45 | PlacerPowerDriven=no 46 | PlacerAreaDriven=no 47 | RouteWithTimingDriven=yes 48 | RouteWithPinPermutation=yes 49 | BitmapSPIFlashMode=yes 50 | BitmapRAM4KInit=yes 51 | BitmapInitRamBank=1111 52 | BitmapOscillatorFR=low 53 | BitmapEnableWarmBoot=yes 54 | BitmapDisableHeader=no 55 | BitmapSetSecurity=no 56 | BitmapSetNoUsedIONoPullup=no 57 | FloorPlannerShowFanInNets=yes 58 | FloorPlannerShowFanOutNets=yes 59 | HookTo3rdPartyTextEditor=no 60 | 61 | [usb_cdc_Implmnt] 62 | DeviceFamily=iCE40 63 | Device=LP8K 64 | DevicePackage=CM81 65 | DevicePower= 66 | NetlistFile=usb_cdc_Implmnt/usb_cdc.edf 67 | AdditionalEDIFFile= 68 | IPEDIFFile= 69 | DesignLib=usb_cdc_Implmnt/sbt/netlist/oadb-demo 70 | DesignView=_rt 71 | DesignCell=demo 72 | SynthesisSDCFile=usb_cdc_Implmnt/usb_cdc.scf 73 | UserPinConstraintFile= 74 | UserSDCFile= 75 | PhysicalConstraintFile=constraints/pins.pcf 76 | BackendImplPathName= 77 | Devicevoltage=1.14 78 | DevicevoltagePerformance=+/-5%(datasheet default) 79 | DeviceTemperature=85 80 | TimingAnalysisBasedOn=Worst 81 | OperationRange=Commercial 82 | TypicalCustomTemperature=25 83 | WorstCustomTemperature=85 84 | BestCustomTemperature=0 85 | IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3 86 | derValue=1.03369 87 | TimingPathNumberStick=0 88 | 89 | -------------------------------------------------------------------------------- /examples/common/hdl/ice40/SB_PLL40_CORE.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps/1 ps 2 | `define abs(a)((a) >= 0 ? (a) : (-a)) 3 | 4 | module SB_PLL40_CORE ( 5 | input REFERENCECLK, 6 | output PLLOUTCORE, 7 | output PLLOUTGLOBAL, 8 | input EXTFEEDBACK, 9 | input [7:0] DYNAMICDELAY, 10 | output LOCK, 11 | input BYPASS, 12 | input RESETB, 13 | input LATCHINPUTVALUE, 14 | output SDO, 15 | input SDI, 16 | input SCLK 17 | ); 18 | parameter FEEDBACK_PATH = "SIMPLE"; 19 | parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; 20 | parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; 21 | parameter SHIFTREG_DIV_MODE = 1'b0; 22 | parameter FDA_FEEDBACK = 4'b0000; 23 | parameter FDA_RELATIVE = 4'b0000; 24 | parameter PLLOUT_SELECT = "GENCLK"; 25 | parameter DIVR = 4'b0000; 26 | parameter DIVF = 7'b0000000; 27 | parameter DIVQ = 3'b000; 28 | parameter FILTER_RANGE = 3'b000; 29 | parameter ENABLE_ICEGATE = 1'b0; 30 | parameter TEST_MODE = 1'b0; 31 | parameter EXTERNAL_DIVIDE_FACTOR = 1; 32 | 33 | localparam CLK_RATIO = (DIVF+1)/(2**DIVQ*(DIVR+1)); 34 | 35 | time ref_per; 36 | time clk_per; 37 | time last_ref_rising; 38 | 39 | integer timeout; 40 | 41 | reg clk; 42 | reg lock_reg; 43 | 44 | assign #(clk_per/4) PLLOUTGLOBAL = clk; // glitch filter 45 | assign #(clk_per+ref_per) LOCK = lock_reg; // glitch filter 46 | 47 | initial begin 48 | ref_per = 0; 49 | clk_per = 10; 50 | last_ref_rising = $time; 51 | clk = 0; 52 | lock_reg = 1; 53 | timeout = 4*CLK_RATIO; 54 | #1 lock_reg = 0; // negedge to trigger reset 55 | #100; 56 | ref_per = 0; 57 | clk_per = 100000000; 58 | end 59 | 60 | always @(posedge REFERENCECLK) begin 61 | if (`abs($time - last_ref_rising - ref_per)*100/ref_per < 1) 62 | lock_reg = 1; 63 | else 64 | lock_reg = 0; 65 | ref_per = $time - last_ref_rising; 66 | last_ref_rising = $time; 67 | if (clk_per != 2**DIVQ * (DIVR + 1) * ref_per / (DIVF + 1)) begin 68 | clk_per = 2**DIVQ * (DIVR + 1) * ref_per / (DIVF + 1); 69 | clk <= ~clk; 70 | end 71 | timeout = 4*CLK_RATIO; 72 | end 73 | 74 | always @(clk) 75 | if (timeout > 0) begin 76 | clk <= #(clk_per/2) ~clk; 77 | if (clk) 78 | timeout = timeout - 1; 79 | end else 80 | lock_reg = 0; 81 | endmodule 82 | 83 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # override the default with: make all PROJ=loopback 3 | PROJ = demo 4 | 5 | PIN_DEF = pins.pcf 6 | DEVICE = lp8k 7 | PKG = cm81 8 | IN_DIR = input/$(PROJ) 9 | OUT_DIR = output/$(PROJ) 10 | INC_DIRS = -I../../common/hdl -I../hdl/$(PROJ) 11 | ICE40_LIB = $(shell yosys-config --datdir/ice40/cells_sim.v) 12 | RUN_ONCE = 13 | run = $(if $(RUN_ONCE),$(1),until $$($(1)) ; do true ; done) 14 | 15 | include $(IN_DIR)/hdl_files.mk 16 | 17 | all: $(OUT_DIR)/$(PROJ).rpt $(OUT_DIR)/$(PROJ).bin 18 | fw: $(OUT_DIR)/fw_$(PROJ).bin 19 | 20 | $(OUT_DIR): 21 | mkdir -p $@ 22 | 23 | $(OUT_DIR)/%.json: $(HDL_FILES) | $(OUT_DIR) 24 | yosys -l $(OUT_DIR)/log_yosys_$(PROJ).txt -p '$(foreach file,$^,read_verilog $(file);)' -p 'synth_ice40 -top $(PROJ); write_json $@' 25 | 26 | $(OUT_DIR)/%.asc: $(OUT_DIR)/%.json $(IN_DIR)/$(PIN_DEF) 27 | $(call run,nextpnr-ice40 --randomize-seed --$(DEVICE) --package $(PKG) -l $(OUT_DIR)/log_nextpnr_$*.txt --pcf $(IN_DIR)/$(PIN_DEF) --json $< --pre-pack $(IN_DIR)/pre-pack.py --asc $@) 28 | 29 | $(OUT_DIR)/%.rpt: $(OUT_DIR)/%.asc 30 | icetime -d $(DEVICE) -mtr $@ $< 31 | 32 | $(OUT_DIR)/%.bin: $(OUT_DIR)/%.asc 33 | icepack $< $@ 34 | 35 | $(OUT_DIR)/fw_%.bin: $(OUT_DIR)/%.bin 36 | cp $< $(OUT_DIR)/$*_0.bin 37 | cp $< $(OUT_DIR)/$*_1.bin 38 | icemulti -v -o $@ -a15 -p0 $(OUT_DIR)/$*_0.bin $(OUT_DIR)/$*_1.bin 39 | rm $(OUT_DIR)/$*_0.bin $(OUT_DIR)/$*_1.bin 40 | 41 | prog: $(OUT_DIR)/$(PROJ).bin 42 | tinyprog -p $< 43 | 44 | lint: $(HDL_FILES) 45 | verilator --lint-only --default-language 1364-2001 -Wall -Wno-UNUSED -Wno-UNDRIVEN -Wno-TIMESCALEMOD -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS --top $(PROJ) $(INC_DIRS) -v $(ICE40_LIB) $^ 46 | 47 | $(OUT_DIR)/cells_sim.v: 48 | patch $(ICE40_LIB) -o $(OUT_DIR)/cells_sim.v < ../../common/hdl/ice40/cells_sim.v.patch 49 | 50 | $(OUT_DIR)/%.vvp: $(HDL_FILES) $(TB_HDL_FILES) | $(OUT_DIR) $(OUT_DIR)/cells_sim.v 51 | iverilog -g2001 -DNO_ICE40_DEFAULT_ASSIGNMENTS -t vvp -s tb_$(PROJ) $(INC_DIRS) -l $(OUT_DIR)/cells_sim.v -o $@ $^ 52 | 53 | $(OUT_DIR)/%.fst: $(OUT_DIR)/%.vvp 54 | vvp -N $< -fst && mv tb.dump $@ 55 | 56 | sim: $(OUT_DIR)/$(PROJ).fst 57 | 58 | $(OUT_DIR)/%.xml: $(HDL_FILES) $(TB_HDL_FILES) | $(OUT_DIR) $(OUT_DIR)/cells_sim.v 59 | verilator --no-timing -xml-only --bbox-unsup --bbox-sys -Wno-lint -Wno-MULTIDRIVEN -Wno-TIMESCALEMOD -Wno-STMTDLY -Wno-INFINITELOOP -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS --top tb_$(PROJ) $(INC_DIRS) -v $(OUT_DIR)/cells_sim.v $^ --xml-output $@ 60 | 61 | $(OUT_DIR)/%.stems: $(OUT_DIR)/%.xml 62 | xml2stems $< $@ 63 | 64 | wave: $(OUT_DIR)/$(PROJ).stems $(OUT_DIR)/$(PROJ).fst 65 | gtkwave --autosavename --saveonexit --tcl_init=../../common/gtkwave/procs.tcl --wish --stems $^ --rcvar 'do_initial_zoom_fit yes' --rcvar 'splash_disable yes' 66 | 67 | $(OUT_DIR)/%.fst: $(OUT_DIR)/tb.dump 68 | vcd2fst $< $@ 69 | 70 | fst: $(OUT_DIR)/$(PROJ).stems $(OUT_DIR)/tb.fst 71 | gtkwave --autosavename --saveonexit --tcl_init=../../common/gtkwave/procs.tcl --wish --stems $^ --rcvar 'do_initial_zoom_fit yes' --rcvar 'splash_disable yes' 72 | 73 | clean: 74 | rm -rf $(OUT_DIR) 75 | 76 | .SECONDARY: 77 | .PHONY: all prog lint sim wave clean 78 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # override the default with: make all PROJ=loopback 3 | PROJ = demo 4 | FOMU_REV = pvt 5 | 6 | PCF_PATH = ./pcf 7 | 8 | ifeq ($(FOMU_REV),evt1) 9 | DEFINES ?= -DEVT -DEVT1 -DHAVE_PMOD 10 | DEVICE ?= up5k 11 | PKG ?= sg48 12 | PCF ?= $(PCF_PATH)/fomu-evt2.pcf 13 | else ifeq ($(FOMU_REV),evt2) 14 | DEFINES ?= -DEVT -DEVT2 -DHAVE_PMOD 15 | DEVICE ?= up5k 16 | PKG ?= sg48 17 | PCF ?= $(PCF_PATH)/fomu-evt2.pcf 18 | else ifeq ($(FOMU_REV),evt3) 19 | DEFINES ?= -DEVT -DEVT3 -DHAVE_PMOD 20 | DEVICE ?= up5k 21 | PKG ?= sg48 22 | PCF ?= $(PCF_PATH)/fomu-evt3.pcf 23 | else ifeq ($(FOMU_REV),hacker) 24 | DEFINES ?= -DHACKER 25 | DEVICE ?= up5k 26 | PKG ?= uwg30 27 | PCF ?= $(PCF_PATH)/fomu-hacker.pcf 28 | else ifeq ($(FOMU_REV),pvt) 29 | DEFINES ?= -DPVT 30 | DEVICE ?= up5k 31 | PKG ?= uwg30 32 | PCF ?= $(PCF_PATH)/fomu-pvt.pcf 33 | else 34 | $(error Unrecognized FOMU_REV value. must be "evt1", "evt2", "evt3", "pvt", or "hacker") 35 | endif 36 | 37 | IN_DIR = input/$(PROJ) 38 | OUT_DIR = output/$(PROJ) 39 | INC_DIRS = -I../../common/hdl -I../hdl/$(PROJ) 40 | ICE40_LIB = $(shell yosys-config --datdir/ice40/cells_sim.v) 41 | 42 | include $(IN_DIR)/hdl_files.mk 43 | 44 | all: $(OUT_DIR)/$(PROJ).rpt $(OUT_DIR)/$(PROJ).bin 45 | 46 | $(OUT_DIR): 47 | mkdir -p $@ 48 | 49 | $(OUT_DIR)/%.json: $(HDL_FILES) | $(OUT_DIR) 50 | yosys $(DEFINES) -l $(OUT_DIR)/log_yosys_$(PROJ).txt -p '$(foreach file,$^,read_verilog $(file);)' -p 'synth_ice40 -top $(PROJ); write_json $@' 51 | 52 | $(OUT_DIR)/%.asc: $(OUT_DIR)/%.json $(PCF) 53 | nextpnr-ice40 --timing-allow-fail --randomize-seed --$(DEVICE) --package $(PKG) -l $(OUT_DIR)/log_nextpnr_$*.txt --pcf $(PCF) --json $< --pre-pack $(IN_DIR)/pre-pack.py --asc $@ 54 | 55 | $(OUT_DIR)/%.rpt: $(OUT_DIR)/%.asc 56 | icetime -d $(DEVICE) -mtr $@ $< 57 | 58 | $(OUT_DIR)/%.bin: $(OUT_DIR)/%.asc 59 | icepack $< $@ 60 | 61 | $(OUT_DIR)/%.dfu: $(OUT_DIR)/%.bin 62 | cp -a $< $@ && dfu-suffix -v 1209 -p 70b1 -a $@ 63 | 64 | prog: $(OUT_DIR)/$(PROJ).dfu 65 | dfu-util -D $< 66 | 67 | lint: $(HDL_FILES) 68 | verilator --lint-only --default-language 1364-2001 -Wall -Wno-UNUSED -Wno-UNDRIVEN -Wno-TIMESCALEMOD -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS $(DEFINES) --top $(PROJ) $(INC_DIRS) -v $(ICE40_LIB) $^ 69 | 70 | $(OUT_DIR)/cells_sim.v: 71 | patch $(ICE40_LIB) -o $(OUT_DIR)/cells_sim.v < ../../common/hdl/ice40/cells_sim.v.patch 72 | 73 | $(OUT_DIR)/%.vvp: $(HDL_FILES) $(TB_HDL_FILES) | $(OUT_DIR) $(OUT_DIR)/cells_sim.v 74 | iverilog -g2001 -DNO_ICE40_DEFAULT_ASSIGNMENTS $(DEFINES) -t vvp -s tb_$(PROJ) $(INC_DIRS) -l $(OUT_DIR)/cells_sim.v -o $@ $^ 75 | 76 | $(OUT_DIR)/%.fst: $(OUT_DIR)/%.vvp 77 | vvp -N $< -fst && mv tb.dump $@ 78 | 79 | sim: $(OUT_DIR)/$(PROJ).fst 80 | 81 | $(OUT_DIR)/%.xml: $(HDL_FILES) $(TB_HDL_FILES) | $(OUT_DIR) $(OUT_DIR)/cells_sim.v 82 | verilator --no-timing -xml-only --bbox-unsup --bbox-sys -Wno-lint -Wno-MULTIDRIVEN -Wno-TIMESCALEMOD -Wno-STMTDLY -Wno-INFINITELOOP -DBLACKBOX -DNO_ICE40_DEFAULT_ASSIGNMENTS $(DEFINES) --top tb_$(PROJ) $(INC_DIRS) -v $(OUT_DIR)/cells_sim.v $^ --xml-output $@ 83 | 84 | $(OUT_DIR)/%.stems: $(OUT_DIR)/%.xml 85 | xml2stems $< $@ 86 | 87 | wave: $(OUT_DIR)/$(PROJ).stems $(OUT_DIR)/$(PROJ).fst 88 | gtkwave --autosavename --saveonexit --tcl_init=../../common/gtkwave/procs.tcl --wish --stems $^ --rcvar 'do_initial_zoom_fit yes' --rcvar 'splash_disable yes' 89 | 90 | clean: 91 | rm -rf $(OUT_DIR) 92 | 93 | .SECONDARY: 94 | .PHONY: all prog lint sim wave clean 95 | -------------------------------------------------------------------------------- /examples/common/hdl/fifo_if.v: -------------------------------------------------------------------------------- 1 | // FIFO_IF module shall implement an interface for MCUs to USB_CDC FIFO. 2 | // FIFO_IF shall: 3 | // - Store FIFO consumed OUT data into an internal 8bit buffer waiting 4 | // for the MCU to get it. 5 | // - Store MCU output data into an internal 8bit buffer waiting to be 6 | // consumed as IN data by USB_CDC FIFO. 7 | // - Provide internal IN/OUT buffers status to MCU. 8 | // - Provide pulsed IRQ to signal when IN data is consumed. 9 | // - Provide pulsed IRQ to signal when OUT data is consumed. 10 | 11 | module fifo_if 12 | ( 13 | input clk_i, 14 | input rstn_i, 15 | 16 | // ---- to/from uC ----------------------------------------------- 17 | input sel_i, 18 | input read_i, 19 | input write_i, 20 | input [1:0] addr_i, 21 | input [7:0] data_i, 22 | output [7:0] data_o, 23 | output in_irq_o, 24 | output out_irq_o, 25 | 26 | // ---- to/from USB_CDC ------------------------------------------ 27 | output [7:0] in_data_o, 28 | output in_valid_o, 29 | // While in_valid_o is high, in_data_o shall be valid and both 30 | // in_valid_o and in_data_o shall not change until consumed. 31 | input in_ready_i, 32 | // When both in_ready_i and in_valid_o are high, in_data_o shall 33 | // be consumed. 34 | input [7:0] out_data_i, 35 | input out_valid_i, 36 | // While out_valid_i is high, the out_data_i shall be valid. 37 | output out_ready_o 38 | // When both out_valid_i and out_ready_o are high, the out_data_i shall 39 | // be consumed. 40 | ); 41 | 42 | reg [7:0] in_buffer_q; 43 | reg in_valid_q; 44 | reg in_irq_q; 45 | 46 | assign in_data_o = in_buffer_q; 47 | assign in_valid_o = in_valid_q; 48 | assign in_irq_o = in_irq_q; 49 | 50 | always @(posedge clk_i or negedge rstn_i) begin 51 | if (~rstn_i) begin 52 | in_buffer_q <= 8'd0; 53 | in_valid_q <= 1'b0; 54 | in_irq_q <= 1'b0; 55 | end else begin 56 | in_irq_q <= 1'b0; 57 | if (in_valid_q == 1'b1) begin 58 | if (in_ready_i == 1'b1) begin 59 | in_valid_q <= 1'b0; 60 | in_irq_q <= 1'b1; 61 | end 62 | end else 63 | if (write_i == 1'b1 && sel_i == 1'b1 && addr_i == 2'b01) begin 64 | in_buffer_q <= data_i; 65 | in_valid_q <= 1'b1; 66 | end 67 | end 68 | end 69 | 70 | reg [1:0] addr_q; 71 | reg [7:0] out_buffer_q; 72 | reg out_ready_q; 73 | reg out_irq_q; 74 | reg started_q; 75 | 76 | assign out_ready_o = out_ready_q; 77 | assign out_irq_o = out_irq_q; 78 | 79 | always @(posedge clk_i or negedge rstn_i) begin 80 | if (~rstn_i) begin 81 | started_q <= 1'b0; 82 | addr_q <= 2'd0; 83 | out_buffer_q <= 8'd0; 84 | out_ready_q <= 1'b0; 85 | out_irq_q <= 1'b0; 86 | end else begin 87 | started_q <= 1'b1; 88 | if (read_i == 1'b1 && sel_i == 1'b1) 89 | addr_q <= addr_i; 90 | out_irq_q <= 1'b0; 91 | if ((read_i == 1'b1 && sel_i == 1'b1 && addr_i == 2'b11) || ~started_q) 92 | out_ready_q <= 1'b1; 93 | if (out_valid_i == 1'b1 && out_ready_q == 1'b1) begin 94 | out_buffer_q <= out_data_i; 95 | out_ready_q <= 1'b0; 96 | out_irq_q <= 1'b1; 97 | end 98 | end 99 | end 100 | 101 | reg [7:0] rdata; 102 | assign data_o = rdata; 103 | 104 | always @(/*AS*/addr_q or in_valid_q or out_buffer_q or out_ready_q) begin 105 | case (addr_q) 106 | 2'b01: begin 107 | rdata = {7'b0, ~in_valid_q}; 108 | end 109 | 2'b10: begin 110 | rdata = {7'b0, ~out_ready_q}; 111 | end 112 | 2'b11: begin 113 | rdata = out_buffer_q; 114 | end 115 | default: begin 116 | rdata = 8'b0; 117 | end 118 | endcase 119 | end 120 | endmodule 121 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/output/soc/soc.rpt: -------------------------------------------------------------------------------- 1 | 2 | icetime topological timing analysis report 3 | ========================================== 4 | 5 | Info: max_span_hack is enabled: estimate is conservative. 6 | 7 | Report for critical path: 8 | ------------------------- 9 | 10 | lc40_7_27_0 (LogicCell40) [clk] -> lcout: 0.896 ns 11 | 0.896 ns net_27768 (u_usb_cdc.u_ctrl_endp.byte_cnt_q[0]) 12 | odrv_7_27_27768_31980 (Odrv4) I -> O: 0.548 ns 13 | t3740 (Span4Mux_v4) I -> O: 0.548 ns 14 | t3739 (LocalMux) I -> O: 0.486 ns 15 | inmux_10_30_43837_43859 (InMux) I -> O: 0.382 ns 16 | lc40_10_30_2 (LogicCell40) in1 -> lcout: 0.589 ns 17 | 3.449 ns net_39697 (u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0]) 18 | t4753 (LocalMux) I -> O: 0.486 ns 19 | inmux_9_30_39762_39787 (InMux) I -> O: 0.382 ns 20 | lc40_9_30_3 (LogicCell40) in0 -> lcout: 0.662 ns 21 | 4.979 ns net_35654 (u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O_SB_LUT4_O_1_I0_SB_LUT4_O_I0[0]) 22 | t4276 (LocalMux) I -> O: 0.486 ns 23 | inmux_9_29_39616_39673 (InMux) I -> O: 0.382 ns 24 | lc40_9_29_4 (LogicCell40) in3 -> lcout: 0.465 ns 25 | 6.312 ns net_35553 (u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O_SB_LUT4_O_1_I0[0]) 26 | odrv_9_29_35553_35408 (Odrv4) I -> O: 0.548 ns 27 | t4273 (Span4Mux_v4) I -> O: 0.548 ns 28 | t4272 (Span4Mux_h4) I -> O: 0.465 ns 29 | t4271 (LocalMux) I -> O: 0.486 ns 30 | inmux_9_21_38637_38699 (InMux) I -> O: 0.382 ns 31 | lc40_9_21_6 (LogicCell40) in1 -> lcout: 0.589 ns 32 | 9.331 ns net_34739 (u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O[0]) 33 | t4012 (LocalMux) I -> O: 0.486 ns 34 | inmux_10_22_42859_42906 (InMux) I -> O: 0.382 ns 35 | t858 (CascadeMux) I -> O: 0.000 ns 36 | lc40_10_22_7 (LogicCell40) in2 -> lcout: 0.558 ns 37 | 10.757 ns net_38718 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_5_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1]) 38 | t4578 (LocalMux) I -> O: 0.486 ns 39 | inmux_9_21_38660_38674 (InMux) I -> O: 0.382 ns 40 | lc40_9_21_2 (LogicCell40) in0 -> lcout: 0.662 ns 41 | 12.287 ns net_34735 (u_usb_cdc.u_ctrl_endp.dev_state_qq_SB_DFFER_Q_E_SB_LUT4_O_I0[1]) 42 | t4008 (LocalMux) I -> O: 0.486 ns 43 | inmux_9_22_38754_38809 (InMux) I -> O: 0.382 ns 44 | lc40_9_22_4 (LogicCell40) in0 -> lcout: 0.662 ns 45 | 13.817 ns net_34839 (u_usb_cdc.ctrl_stall_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_I3_O[0]) 46 | odrv_9_22_34839_38735 (Odrv4) I -> O: 0.548 ns 47 | t4048 (Span4Mux_v4) I -> O: 0.548 ns 48 | t4047 (Span4Mux_h4) I -> O: 0.465 ns 49 | t4046 (LocalMux) I -> O: 0.486 ns 50 | inmux_7_28_32012_32084 (InMux) I -> O: 0.382 ns 51 | lc40_7_28_7 (LogicCell40) in0 -> lcout: 0.662 ns 52 | 16.908 ns net_27898 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_I1_O) 53 | odrv_7_28_27898_27794 (Odrv4) I -> O: 0.548 ns 54 | t3876 (Span4Mux_h4) I -> O: 0.465 ns 55 | t3875 (LocalMux) I -> O: 0.486 ns 56 | inmux_9_29_39640_39692 (CEMux) I -> O: 0.889 ns 57 | 19.296 ns net_39692 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_I1_O) 58 | lc40_9_29_6 (LogicCell40) ce [setup]: 0.000 ns 59 | 19.296 ns net_35555 (u_usb_cdc.u_ctrl_endp.byte_cnt_q[5]) 60 | 61 | Resolvable net names on path: 62 | 0.896 ns .. 2.860 ns u_usb_cdc.u_ctrl_endp.byte_cnt_q[0] 63 | 3.449 ns .. 4.317 ns u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0] 64 | 4.979 ns .. 5.847 ns u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O_SB_LUT4_O_1_I0_SB_LUT4_O_I0[0] 65 | 6.312 ns .. 8.742 ns u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O_SB_LUT4_O_1_I0[0] 66 | 9.331 ns .. 10.199 ns u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O[0] 67 | 10.757 ns .. 11.626 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_5_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] 68 | 12.287 ns .. 13.156 ns u_usb_cdc.u_ctrl_endp.dev_state_qq_SB_DFFER_Q_E_SB_LUT4_O_I0[1] 69 | 13.817 ns .. 16.246 ns u_usb_cdc.ctrl_stall_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_I3_O[0] 70 | 16.908 ns .. 19.296 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_I1_O 71 | lcout -> u_usb_cdc.u_ctrl_endp.byte_cnt_q[5] 72 | 73 | Total number of logic levels: 9 74 | Total path delay: 19.30 ns (51.83 MHz) 75 | 76 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/output/demo/demo.rpt: -------------------------------------------------------------------------------- 1 | 2 | icetime topological timing analysis report 3 | ========================================== 4 | 5 | Info: max_span_hack is enabled: estimate is conservative. 6 | 7 | Report for critical path: 8 | ------------------------- 9 | 10 | lc40_10_6_5 (LogicCell40) [clk] -> lcout: 1.491 ns 11 | 1.491 ns net_38076 (u_usb_cdc.u_sie.crc16_q_SB_DFFER_Q_D_SB_LUT4_O_I3[0]) 12 | odrv_10_6_38076_41690 (Odrv4) I -> O: 0.649 ns 13 | t4988 (LocalMux) I -> O: 1.099 ns 14 | inmux_10_3_41604_41610 (InMux) I -> O: 0.662 ns 15 | lc40_10_3_0 (LogicCell40) in3 -> lcout: 0.874 ns 16 | 4.775 ns net_37702 (u_usb_cdc.u_ctrl_endp.addr_q_SB_DFFER_Q_E_SB_LUT4_O_I0[1]) 17 | t4717 (LocalMux) I -> O: 1.099 ns 18 | inmux_11_3_45413_45451 (InMux) I -> O: 0.662 ns 19 | lc40_11_3_2 (LogicCell40) in1 -> lcout: 1.232 ns 20 | 7.769 ns net_41535 (u_usb_cdc.u_sie.out_eop_q_SB_LUT4_I1_O[0]) 21 | odrv_11_3_41535_45512 (Odrv4) I -> O: 0.649 ns 22 | t5263 (Span4Mux_v4) I -> O: 0.649 ns 23 | t5262 (LocalMux) I -> O: 1.099 ns 24 | inmux_12_10_50100_50138 (InMux) I -> O: 0.662 ns 25 | t1132 (CascadeMux) I -> O: 0.000 ns 26 | lc40_12_10_1 (LogicCell40) in2 -> lcout: 1.205 ns 27 | 12.033 ns net_46226 (u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2[0]) 28 | t6117 (LocalMux) I -> O: 1.099 ns 29 | inmux_13_11_54068_54121 (InMux) I -> O: 0.662 ns 30 | lc40_13_11_6 (LogicCell40) in1 -> lcout: 1.232 ns 31 | 15.027 ns net_50185 (u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I3_O_SB_LUT4_O_I1[1]) 32 | t6500 (LocalMux) I -> O: 1.099 ns 33 | inmux_12_12_50349_50388 (InMux) I -> O: 0.662 ns 34 | lc40_12_12_2 (LogicCell40) in0 -> lcout: 1.285 ns 35 | 18.073 ns net_46473 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_4_D_SB_LUT4_O_I2_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]) 36 | t6157 (LocalMux) I -> O: 1.099 ns 37 | inmux_12_12_50361_50419 (InMux) I -> O: 0.662 ns 38 | lc40_12_12_7 (LogicCell40) in1 -> lcout: 1.232 ns 39 | 21.066 ns net_46478 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_O_1_I2[0]) 40 | odrv_12_12_46478_46628 (Odrv4) I -> O: 0.649 ns 41 | t6194 (LocalMux) I -> O: 1.099 ns 42 | inmux_12_14_50603_50630 (InMux) I -> O: 0.662 ns 43 | t1157 (CascadeMux) I -> O: 0.000 ns 44 | lc40_12_14_1 (LogicCell40) in2 -> lcout: 1.205 ns 45 | 24.682 ns net_46718 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_I3_O[3]) 46 | odrv_12_14_46718_46498 (Odrv4) I -> O: 0.649 ns 47 | t6233 (Span4Mux_h4) I -> O: 0.543 ns 48 | t6232 (LocalMux) I -> O: 1.099 ns 49 | inmux_13_10_53938_53974 (InMux) I -> O: 0.662 ns 50 | lc40_13_10_2 (LogicCell40) in1 -> lcout: 1.232 ns 51 | 28.867 ns net_50058 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_O_1_I2[2]) 52 | t6485 (LocalMux) I -> O: 1.099 ns 53 | inmux_13_11_54061_54085 (InMux) I -> O: 0.662 ns 54 | lc40_13_11_0 (LogicCell40) in1 -> lcout: 1.232 ns 55 | 31.860 ns net_50179 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_1_D_SB_LUT4_O_I1[2]) 56 | t6489 (LocalMux) I -> O: 1.099 ns 57 | inmux_13_11_54051_54091 (InMux) I -> O: 0.662 ns 58 | 33.622 ns net_54091 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_1_D_SB_LUT4_O_I1[2]) 59 | lc40_13_11_1 (LogicCell40) in1 [setup]: 1.007 ns 60 | 34.629 ns net_50180 (u_usb_cdc.ctrl_stall_SB_LUT4_I2_O[1]) 61 | 62 | Resolvable net names on path: 63 | 1.491 ns .. 3.901 ns u_usb_cdc.u_sie.crc16_q_SB_DFFER_Q_D_SB_LUT4_O_I3[0] 64 | 4.775 ns .. 6.537 ns u_usb_cdc.u_ctrl_endp.addr_q_SB_DFFER_Q_E_SB_LUT4_O_I0[1] 65 | 7.769 ns .. 10.828 ns u_usb_cdc.u_sie.out_eop_q_SB_LUT4_I1_O[0] 66 | 12.033 ns .. 13.795 ns u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I3_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2[0] 67 | 15.027 ns .. 16.788 ns u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I3_O_SB_LUT4_O_I1[1] 68 | 18.073 ns .. 19.834 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_4_D_SB_LUT4_O_I2_SB_LUT4_I0_I3_SB_LUT4_O_I2[3] 69 | 21.066 ns .. 23.477 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_O_1_I2[0] 70 | 24.682 ns .. 27.635 ns u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_I3_O[3] 71 | 28.867 ns .. 30.629 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_1_D_SB_LUT4_O_I1_SB_LUT4_O_1_I2[2] 72 | 31.860 ns .. 33.622 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_1_D_SB_LUT4_O_I1[2] 73 | lcout -> u_usb_cdc.ctrl_stall_SB_LUT4_I2_O[1] 74 | 75 | Total number of logic levels: 10 76 | Total path delay: 34.63 ns (28.88 MHz) 77 | 78 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/output/soc/soc.rpt: -------------------------------------------------------------------------------- 1 | 2 | icetime topological timing analysis report 3 | ========================================== 4 | 5 | Info: max_span_hack is enabled: estimate is conservative. 6 | 7 | Report for critical path: 8 | ------------------------- 9 | 10 | lc40_10_16_7 (LogicCell40) [clk] -> lcout: 1.491 ns 11 | 1.491 ns net_39308 (u_usb_cdc.ctrl_stall_SB_LUT4_I1_O[1]) 12 | odrv_10_16_39308_43036 (Odrv4) I -> O: 0.649 ns 13 | t4293 (LocalMux) I -> O: 1.099 ns 14 | inmux_11_14_46781_46792 (InMux) I -> O: 0.662 ns 15 | lc40_11_14_0 (LogicCell40) in1 -> lcout: 1.232 ns 16 | 5.133 ns net_42886 (u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_I2[2]) 17 | t4743 (LocalMux) I -> O: 1.099 ns 18 | inmux_11_14_46782_46799 (InMux) I -> O: 0.662 ns 19 | t918 (CascadeMux) I -> O: 0.000 ns 20 | lc40_11_14_1 (LogicCell40) in2 -> lcout: 1.205 ns 21 | 8.100 ns net_42887 (u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_1_I3[0]) 22 | t4745 (LocalMux) I -> O: 1.099 ns 23 | inmux_12_15_50729_50765 (InMux) I -> O: 0.662 ns 24 | t1029 (CascadeMux) I -> O: 0.000 ns 25 | lc40_12_15_3 (LogicCell40) in2 -> lcout: 1.205 ns 26 | 11.066 ns net_46843 (u_usb_cdc.ctrl_stall_SB_LUT4_I1_O[3]) 27 | t5191 (LocalMux) I -> O: 1.099 ns 28 | inmux_11_16_47007_47081 (InMux) I -> O: 0.662 ns 29 | t936 (CascadeMux) I -> O: 0.000 ns 30 | lc40_11_16_7 (LogicCell40) in2 -> lcout: 1.205 ns 31 | 14.033 ns net_43139 (u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O[1]) 32 | odrv_11_16_43139_43289 (Odrv4) I -> O: 0.649 ns 33 | t4860 (LocalMux) I -> O: 1.099 ns 34 | inmux_11_19_47384_47425 (InMux) I -> O: 0.662 ns 35 | lc40_11_19_3 (LogicCell40) in1 -> lcout: 1.232 ns 36 | 17.676 ns net_43504 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_10_D_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I2[1]) 37 | t4955 (LocalMux) I -> O: 1.099 ns 38 | inmux_12_19_51207_51243 (InMux) I -> O: 0.662 ns 39 | lc40_12_19_1 (LogicCell40) in0 -> lcout: 1.285 ns 40 | 20.722 ns net_47333 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_10_D_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I3[0]) 41 | t5237 (LocalMux) I -> O: 1.099 ns 42 | inmux_12_18_51090_51152 (InMux) I -> O: 0.662 ns 43 | t1047 (CascadeMux) I -> O: 0.000 ns 44 | lc40_12_18_6 (LogicCell40) in2 -> lcout: 1.205 ns 45 | 23.689 ns net_47215 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_5_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1]) 46 | t5218 (LocalMux) I -> O: 1.099 ns 47 | inmux_12_18_51095_51134 (InMux) I -> O: 0.662 ns 48 | t1045 (CascadeMux) I -> O: 0.000 ns 49 | lc40_12_18_3 (LogicCell40) in2 -> lcout: 1.205 ns 50 | 26.655 ns net_47212 (u_usb_cdc.u_ctrl_endp.dev_state_q_SB_DFFES_Q_E_SB_LUT4_O_I2[2]) 51 | odrv_12_18_47212_47347 (Odrv4) I -> O: 0.649 ns 52 | t5224 (Span4Mux_v4) I -> O: 0.649 ns 53 | t5223 (LocalMux) I -> O: 1.099 ns 54 | inmux_11_22_47753_47784 (InMux) I -> O: 0.662 ns 55 | lc40_11_22_1 (LogicCell40) in3 -> lcout: 0.874 ns 56 | 30.589 ns net_43871 (u_usb_cdc.u_ctrl_endp.max_length_q_SB_DFFER_Q_E) 57 | odrv_11_22_43871_43777 (Odrv4) I -> O: 0.649 ns 58 | t5038 (Span4Mux_h4) I -> O: 0.543 ns 59 | t5037 (LocalMux) I -> O: 1.099 ns 60 | inmux_10_23_44052_44113 (CEMux) I -> O: 0.702 ns 61 | 33.582 ns net_44113 (u_usb_cdc.u_ctrl_endp.max_length_q_SB_DFFER_Q_E) 62 | lc40_10_23_3 (LogicCell40) ce [setup]: 0.000 ns 63 | 33.582 ns net_40165 (u_usb_cdc.u_ctrl_endp.max_length_q[1]) 64 | 65 | Resolvable net names on path: 66 | 1.491 ns .. 3.901 ns u_usb_cdc.ctrl_stall_SB_LUT4_I1_O[1] 67 | 5.133 ns .. 6.894 ns u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_I2[2] 68 | 8.100 ns .. 9.861 ns u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_1_I3[0] 69 | 11.066 ns .. 12.828 ns u_usb_cdc.ctrl_stall_SB_LUT4_I1_O[3] 70 | 14.033 ns .. 16.444 ns u_usb_cdc.u_sie.in_req_q_SB_LUT4_I3_2_O[1] 71 | 17.676 ns .. 19.437 ns u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_10_D_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I2[1] 72 | 20.722 ns .. 22.483 ns u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_10_D_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I3[0] 73 | 23.689 ns .. 25.450 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_5_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] 74 | 26.655 ns .. 29.715 ns u_usb_cdc.u_ctrl_endp.dev_state_q_SB_DFFES_Q_E_SB_LUT4_O_I2[2] 75 | 30.589 ns .. 33.582 ns u_usb_cdc.u_ctrl_endp.max_length_q_SB_DFFER_Q_E 76 | lcout -> u_usb_cdc.u_ctrl_endp.max_length_q[1] 77 | 78 | Total number of logic levels: 10 79 | Total path delay: 33.58 ns (29.78 MHz) 80 | 81 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback/usb_cdc_Implmnt/sbt/outputs/loopback_sbt.rpt: -------------------------------------------------------------------------------- 1 | * ****************************************************************************** 2 | 3 | * iCEcube Report 4 | 5 | * Version: 2020.12.27943 6 | 7 | * Build Date: Dec 10 2020 17:24:17 8 | 9 | * File Generated: Feb 17 2024 15:37:59 10 | 11 | * Purpose: General info of design implementation 12 | 13 | * Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved. 14 | 15 | * ****************************************************************************** 16 | 17 | Synthesis/Placement Summary: 18 | ---------------------------- 19 | Status: Successful 20 | Runtime: 2 seconds 21 | 22 | Device Info: 23 | ------------ 24 | Device Family: iCE40 25 | Device: iCE40LP8K 26 | Package: CM81 27 | 28 | Design statistics: 29 | ------------------ 30 | FFs: 424 31 | LUTs: 1152 32 | RAMs: 0 33 | IOBs: 5 34 | GBs: 4 35 | PLLs: 1 36 | Warm Boots: 0 37 | 38 | Logic Resource Utilization: 39 | --------------------------- 40 | Total Logic Cells: 1158/7680 41 | Combinational Logic Cells: 734 out of 7680 9.55729% 42 | Sequential Logic Cells: 424 out of 7680 5.52083% 43 | Logic Tiles: 212 out of 960 22.0833% 44 | Registers: 45 | Logic Registers: 424 out of 7680 5.52083% 46 | IO Registers: 0 out of 1280 0 47 | Block RAMs: 0 out of 32 0% 48 | Warm Boots: 0 out of 1 0% 49 | Pins: 50 | Input Pins: 1 out of 63 1.5873% 51 | Output Pins: 2 out of 63 3.1746% 52 | InOut Pins: 2 out of 63 3.1746% 53 | Global Buffers: 4 out of 8 50% 54 | PLLs: 1 out of 1 100% 55 | 56 | IO Bank Utilization: 57 | -------------------- 58 | Bank 3: 1 out of 18 5.55556% 59 | Bank 1: 0 out of 15 0% 60 | Bank 0: 4 out of 17 23.5294% 61 | Bank 2: 0 out of 13 0% 62 | 63 | Detailed I/O Info: 64 | ------------------ 65 | Input Pins: 66 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 67 | ---------- --------- ----------- ------- ------- ----------- ----------- 68 | B2 Input SB_LVCMOS No 3 Simple Input clk 69 | 70 | Output Pins: 71 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 72 | ---------- --------- ----------- ------- ------- ----------- ----------- 73 | A3 Output SB_LVCMOS No 0 Output Tristatable by Enable usb_pu 74 | B3 Output SB_LVCMOS No 0 Simple Output led 75 | 76 | Inoutput Pins: 77 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 78 | ---------- --------- ----------- ------- ------- ----------- ----------- 79 | A4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_n 80 | B4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_p 81 | 82 | Detailed Global Buffer Info: 83 | ---------------------------- 84 | Buffer Number IO Bank Driven By Fanout Signal Name 85 | ------------- ------- --------- ------ ----------- 86 | 3 3 38 u_usb_cdc.u_sie.N_588_0_g 87 | 2 1 350 u_usb_cdc.rstn_i_g 88 | 4 0 72 u_usb_cdc.rstn_sq_i_g_0 89 | 1 0 102 u_usb_cdc.clk_gate_g 90 | 91 | 92 | Router Summary: 93 | --------------- 94 | Status: Successful 95 | Runtime: 15 seconds 96 | 97 | Routing Resource Utilization: 98 | ----------------------------- 99 | Local line of tile 7936 out of 146184 5.42877% 100 | Span 4 2015 out of 29696 6.78543% 101 | Span 12 262 out of 5632 4.65199% 102 | Global network 5 out of 8 62.5% 103 | Vertical Inter-LUT Connect 303 out of 6720 4.50893% 104 | 105 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/OSS_CAD_Suite/output/demo/demo.rpt: -------------------------------------------------------------------------------- 1 | 2 | icetime topological timing analysis report 3 | ========================================== 4 | 5 | Info: max_span_hack is enabled: estimate is conservative. 6 | 7 | Report for critical path: 8 | ------------------------- 9 | 10 | lc40_2_19_5 (LogicCell40) [clk] -> lcout: 0.896 ns 11 | 0.896 ns net_6223 (u_usb_cdc.endp[1]) 12 | t3009 (LocalMux) I -> O: 0.486 ns 13 | inmux_2_20_10653_10709 (InMux) I -> O: 0.382 ns 14 | lc40_2_20_6 (LogicCell40) in0 -> lcout: 0.662 ns 15 | 2.426 ns net_6359 (u_usb_cdc.u_sie.in_req_q_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0]) 16 | odrv_2_20_6359_10755 (Odrv4) I -> O: 0.548 ns 17 | t3033 (Span4Mux_v4) I -> O: 0.548 ns 18 | t3032 (LocalMux) I -> O: 0.486 ns 19 | inmux_3_26_15468_15512 (InMux) I -> O: 0.382 ns 20 | lc40_3_26_4 (LogicCell40) in0 -> lcout: 0.662 ns 21 | 5.051 ns net_11341 (u_usb_cdc.u_sie.pid_q_SB_DFFER_Q_D_SB_LUT4_O_I1[3]) 22 | t3879 (LocalMux) I -> O: 0.486 ns 23 | inmux_4_27_19675_19697 (InMux) I -> O: 0.382 ns 24 | lc40_4_27_1 (LogicCell40) in3 -> lcout: 0.465 ns 25 | 6.385 ns net_15538 (u_usb_cdc.u_sie.in_req_q_SB_DFFER_Q_D_SB_LUT4_O_I3[0]) 26 | odrv_4_27_15538_18394 (Odrv12) I -> O: 0.796 ns 27 | t4743 (Sp12to4) I -> O: 0.662 ns 28 | t4742 (LocalMux) I -> O: 0.486 ns 29 | inmux_3_16_14255_14271 (InMux) I -> O: 0.382 ns 30 | lc40_3_16_2 (LogicCell40) in1 -> lcout: 0.589 ns 31 | 9.300 ns net_10109 (u_usb_cdc.u_sie.u_phy_rx.rx_eop_qq_SB_LUT4_I3_I0_SB_LUT4_I3_O[2]) 32 | t3585 (LocalMux) I -> O: 0.486 ns 33 | inmux_3_15_14112_14138 (InMux) I -> O: 0.382 ns 34 | lc40_3_15_0 (LogicCell40) in3 -> lcout: 0.465 ns 35 | 10.633 ns net_9984 (u_usb_cdc.u_sie.u_phy_rx.rx_eop_qq_SB_LUT4_I3_I0_SB_LUT4_I3_O_SB_LUT4_I2_O[1]) 36 | odrv_3_15_9984_12719 (Odrv12) I -> O: 0.796 ns 37 | t3559 (LocalMux) I -> O: 0.486 ns 38 | inmux_3_8_13272_13274 (InMux) I -> O: 0.382 ns 39 | lc40_3_8_0 (LogicCell40) in0 -> lcout: 0.662 ns 40 | 12.959 ns net_9123 (u_usb_cdc.ctrl_stall_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3[0]) 41 | t3392 (LocalMux) I -> O: 0.486 ns 42 | inmux_3_9_13372_13405 (InMux) I -> O: 0.382 ns 43 | t352 (CascadeMux) I -> O: 0.000 ns 44 | lc40_3_9_1 (LogicCell40) in2 -> lcout: 0.558 ns 45 | 14.386 ns net_9247 (u_usb_cdc.ctrl_stall_SB_DFFR_Q_D_SB_LUT4_O_I1[1]) 46 | odrv_3_9_9247_9027 (Odrv4) I -> O: 0.548 ns 47 | t3442 (LocalMux) I -> O: 0.486 ns 48 | inmux_2_6_8941_8952 (InMux) I -> O: 0.382 ns 49 | lc40_2_6_0 (LogicCell40) in1 -> lcout: 0.589 ns 50 | 16.391 ns net_4463 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2]) 51 | t2662 (LocalMux) I -> O: 0.486 ns 52 | inmux_3_5_12888_12929 (InMux) I -> O: 0.382 ns 53 | lc40_3_5_4 (LogicCell40) in0 -> lcout: 0.662 ns 54 | 17.921 ns net_8758 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]) 55 | t3351 (LocalMux) I -> O: 0.486 ns 56 | inmux_3_4_12761_12802 (InMux) I -> O: 0.382 ns 57 | t320 (CascadeMux) I -> O: 0.000 ns 58 | lc40_3_4_3 (LogicCell40) in2 -> lcout: 0.558 ns 59 | 19.347 ns net_8634 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_6_D_SB_LUT4_O_I1[0]) 60 | t3335 (LocalMux) I -> O: 0.486 ns 61 | inmux_2_4_8691_8711 (InMux) I -> O: 0.382 ns 62 | 20.216 ns net_8711 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_6_D_SB_LUT4_O_I1[0]) 63 | lc40_2_4_1 (LogicCell40) in0 [setup]: 0.589 ns 64 | 20.805 ns net_4194 (u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2[1]) 65 | 66 | Resolvable net names on path: 67 | 0.896 ns .. 1.764 ns u_usb_cdc.endp[1] 68 | 2.426 ns .. 4.390 ns u_usb_cdc.u_sie.in_req_q_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I3[0] 69 | 5.051 ns .. 5.920 ns u_usb_cdc.u_sie.pid_q_SB_DFFER_Q_D_SB_LUT4_O_I1[3] 70 | 6.385 ns .. 8.711 ns u_usb_cdc.u_sie.in_req_q_SB_DFFER_Q_D_SB_LUT4_O_I3[0] 71 | 9.300 ns .. 10.168 ns u_usb_cdc.u_sie.u_phy_rx.rx_eop_qq_SB_LUT4_I3_I0_SB_LUT4_I3_O[2] 72 | 10.633 ns .. 12.298 ns u_usb_cdc.u_sie.u_phy_rx.rx_eop_qq_SB_LUT4_I3_I0_SB_LUT4_I3_O_SB_LUT4_I2_O[1] 73 | 12.959 ns .. 13.827 ns u_usb_cdc.ctrl_stall_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3[0] 74 | 14.386 ns .. 15.802 ns u_usb_cdc.ctrl_stall_SB_DFFR_Q_D_SB_LUT4_O_I1[1] 75 | 16.391 ns .. 17.259 ns u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I3[2] 76 | 17.921 ns .. 18.789 ns u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2] 77 | 19.347 ns .. 20.216 ns u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_6_D_SB_LUT4_O_I1[0] 78 | lcout -> u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2[1] 79 | 80 | Total number of logic levels: 11 81 | Total path delay: 20.80 ns (48.07 MHz) 82 | 83 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/hdl/soc/tb_soc.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/10 ps // time-unit/precision 2 | `define BIT_TIME (1000/12) 3 | `define CLK_PER (1000/16) 4 | 5 | module tb_soc ( ); 6 | `define USB_CDC_INST tb_soc.u_soc.u_usb_cdc 7 | 8 | localparam MAX_BITS = 128; 9 | localparam MAX_BYTES = 128; 10 | localparam MAX_STRING = 128; 11 | 12 | reg dp_force; 13 | reg dn_force; 14 | reg power_on; 15 | reg [8*MAX_STRING-1:0] test; 16 | 17 | wire dp_sense; 18 | wire dn_sense; 19 | 20 | integer errors; 21 | integer warnings; 22 | 23 | localparam IN_BULK_MAXPACKETSIZE = 'd8; 24 | localparam OUT_BULK_MAXPACKETSIZE = 'd8; 25 | localparam VENDORID = 16'h1D50; 26 | localparam PRODUCTID = 16'h6130; 27 | 28 | `include "usb_test_1ch.v" 29 | 30 | `progress_bar(test, 37) 31 | 32 | reg clk; 33 | 34 | initial begin 35 | clk = 0; 36 | end 37 | 38 | always @(clk or power_on) begin 39 | if (power_on | clk) 40 | #(`CLK_PER/2) clk <= ~clk; 41 | end 42 | 43 | wire led; 44 | wire usb_p; 45 | wire usb_n; 46 | wire usb_pu; 47 | 48 | soc u_soc (.clk(clk), 49 | .led(led), 50 | .usb_p(usb_p), 51 | .usb_n(usb_n), 52 | .usb_pu(usb_pu)); 53 | 54 | assign usb_p = dp_force; 55 | assign usb_n = dn_force; 56 | 57 | assign (pull1, highz0) usb_p = usb_pu; // 1.5kOhm device pull-up resistor 58 | //pullup (usb_p); // to speedup simulation don't wait for usb_pu 59 | 60 | //pulldown (weak0) dp_pd (usb_p), dn_pd (usb_n); // 15kOhm host pull-down resistors 61 | assign (highz1, weak0) usb_p = 1'b0; // to bypass verilator error on above pulldown 62 | assign (highz1, weak0) usb_n = 1'b0; // to bypass verilator error on above pulldown 63 | 64 | assign dp_sense = usb_p; 65 | assign dn_sense = usb_n; 66 | 67 | reg [6:0] address; 68 | reg [15:0] datain_toggle; 69 | reg [15:0] dataout_toggle; 70 | 71 | initial begin : u_host 72 | $timeformat(-6, 3, "us", 3); 73 | $dumpfile("tb.dump"); 74 | $dumpvars; 75 | 76 | power_on = 1'b1; 77 | dp_force = 1'bZ; 78 | dn_force = 1'bZ; 79 | errors = 0; 80 | warnings = 0; 81 | address = 'd0; 82 | dataout_toggle = 'd0; 83 | datain_toggle = 'd0; 84 | wait_idle(20000000/83*`BIT_TIME); 85 | #(100000/83*`BIT_TIME); 86 | 87 | test_usb(address, datain_toggle, dataout_toggle); 88 | 89 | test = "OUT BULK DATA"; 90 | test_data_out(address, ENDP_BULK, 91 | {8'h01, 8'h02, 8'h03, 8'h04, 8'h05, 8'h06, 8'h07}, 92 | 7, PID_ACK, OUT_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, dataout_toggle); 93 | 94 | test = "IN BULK DATA"; 95 | test_data_in(address, ENDP_BULK, 96 | {8'h01, 8'h02, 8'h03, 8'h04, 8'h05, 8'h06, 8'h07}, 97 | 7, PID_ACK, IN_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, datain_toggle, ZLP); 98 | 99 | test = "IN BULK DATA with NAK"; 100 | test_data_in(address, ENDP_BULK, 101 | {8'h01, 8'h02, 8'h03, 8'h04, 8'h05, 8'h06, 8'h07}, 102 | 7, PID_NAK, IN_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, datain_toggle, ZLP); 103 | 104 | test = "OUT BULK DATA"; 105 | test_data_out(address, ENDP_BULK, 106 | {8'h11, 8'h12, 8'h13, 8'h14, 8'h15, 8'h16, 8'h17, 8'h18}, 107 | 8, PID_ACK, OUT_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, dataout_toggle); 108 | 109 | test = "IN BULK DATA with ZLP"; 110 | test_data_in(address, ENDP_BULK, 111 | {8'h11, 8'h12, 8'h13, 8'h14, 8'h15, 8'h16, 8'h17, 8'h18}, 112 | 8, PID_ACK, IN_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, datain_toggle, ZLP); 113 | 114 | test = "OUT BULK DATA"; 115 | test_data_out(address, ENDP_BULK, 116 | {8'h21, 8'h22, 8'h23, 8'h24, 8'h25, 8'h26, 8'h27, 8'h28, 117 | "12345678"}, 118 | 16, PID_ACK, OUT_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, dataout_toggle); 119 | 120 | test = "IN BULK DATA with ZLP"; 121 | test_data_in(address, ENDP_BULK, 122 | {8'h21, 8'h22, 8'h23, 8'h24, 8'h25, 8'h26, 8'h27, 8'h28, 123 | "23456789"}, 124 | 16, PID_ACK, IN_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, datain_toggle, ZLP); 125 | 126 | test = "OUT BULK DATA"; 127 | test_data_out(address, ENDP_BULK, 128 | {"ABCDEFGH", 129 | "QRSTUVWX", 130 | "abcdefgh"}, 131 | 24, PID_NAK, OUT_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, dataout_toggle); 132 | 133 | test = "IN BULK DATA with ZLP"; 134 | test_data_in(address, ENDP_BULK, 135 | {"abcdefgh", 136 | "qrstuvwx"}, 137 | 16, PID_ACK, IN_BULK_MAXPACKETSIZE, 100000/83*`BIT_TIME, 0, datain_toggle, ZLP); 138 | 139 | test = "Test END"; 140 | #(100*`BIT_TIME); 141 | `report_end("All tests correctly executed!") 142 | end 143 | endmodule 144 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_2ch/usb_cdc_Implmnt/sbt/outputs/loopback_2ch_sbt.rpt: -------------------------------------------------------------------------------- 1 | * ****************************************************************************** 2 | 3 | * iCEcube Report 4 | 5 | * Version: 2020.12.27943 6 | 7 | * Build Date: Dec 10 2020 17:24:17 8 | 9 | * File Generated: Feb 19 2024 22:33:13 10 | 11 | * Purpose: General info of design implementation 12 | 13 | * Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved. 14 | 15 | * ****************************************************************************** 16 | 17 | Synthesis/Placement Summary: 18 | ---------------------------- 19 | Status: Successful 20 | Runtime: 2 seconds 21 | 22 | Device Info: 23 | ------------ 24 | Device Family: iCE40 25 | Device: iCE40LP8K 26 | Package: CM81 27 | 28 | Design statistics: 29 | ------------------ 30 | FFs: 647 31 | LUTs: 1720 32 | RAMs: 0 33 | IOBs: 5 34 | GBs: 6 35 | PLLs: 1 36 | Warm Boots: 0 37 | 38 | Logic Resource Utilization: 39 | --------------------------- 40 | Total Logic Cells: 1720/7680 41 | Combinational Logic Cells: 1073 out of 7680 13.9714% 42 | Sequential Logic Cells: 647 out of 7680 8.42448% 43 | Logic Tiles: 283 out of 960 29.4792% 44 | Registers: 45 | Logic Registers: 647 out of 7680 8.42448% 46 | IO Registers: 0 out of 1280 0 47 | Block RAMs: 0 out of 32 0% 48 | Warm Boots: 0 out of 1 0% 49 | Pins: 50 | Input Pins: 1 out of 63 1.5873% 51 | Output Pins: 2 out of 63 3.1746% 52 | InOut Pins: 2 out of 63 3.1746% 53 | Global Buffers: 6 out of 8 75% 54 | PLLs: 1 out of 1 100% 55 | 56 | IO Bank Utilization: 57 | -------------------- 58 | Bank 3: 1 out of 18 5.55556% 59 | Bank 1: 0 out of 15 0% 60 | Bank 0: 4 out of 17 23.5294% 61 | Bank 2: 0 out of 13 0% 62 | 63 | Detailed I/O Info: 64 | ------------------ 65 | Input Pins: 66 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 67 | ---------- --------- ----------- ------- ------- ----------- ----------- 68 | B2 Input SB_LVCMOS No 3 Simple Input clk 69 | 70 | Output Pins: 71 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 72 | ---------- --------- ----------- ------- ------- ----------- ----------- 73 | A3 Output SB_LVCMOS No 0 Output Tristatable by Enable usb_pu 74 | B3 Output SB_LVCMOS No 0 Simple Output led 75 | 76 | Inoutput Pins: 77 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 78 | ---------- --------- ----------- ------- ------- ----------- ----------- 79 | A4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_n 80 | B4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_p 81 | 82 | Detailed Global Buffer Info: 83 | ---------------------------- 84 | Buffer Number IO Bank Driven By Fanout Signal Name 85 | ------------- ------- --------- ------ ----------- 86 | 3 3 37 u_usb_cdc.u_sie.in_zlp_q_0_sqmuxa_g 87 | 0 2 535 u_usb_cdc.rstn_i_g 88 | 2 1 28 u_usb_cdc.app_rstn_sq_i_g_0 89 | 4 0 72 u_usb_cdc.rstn_sq_i_g_0 90 | 1 0 140 u_usb_cdc.clk_gate_g 91 | 7 1 615 clk_div4_g 92 | 93 | 94 | Router Summary: 95 | --------------- 96 | Status: Successful 97 | Runtime: 17 seconds 98 | 99 | Routing Resource Utilization: 100 | ----------------------------- 101 | Local line of tile 11203 out of 146184 7.66363% 102 | Span 4 2780 out of 29696 9.36153% 103 | Span 12 421 out of 5632 7.47514% 104 | Global network 7 out of 8 87.5% 105 | Vertical Inter-LUT Connect 395 out of 6720 5.87798% 106 | 107 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/soc/usb_cdc_Implmnt/sbt/outputs/soc_sbt.rpt: -------------------------------------------------------------------------------- 1 | * ****************************************************************************** 2 | 3 | * iCEcube Report 4 | 5 | * Version: 2020.12.27943 6 | 7 | * Build Date: Dec 10 2020 17:24:17 8 | 9 | * File Generated: Feb 19 2024 22:40:17 10 | 11 | * Purpose: General info of design implementation 12 | 13 | * Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved. 14 | 15 | * ****************************************************************************** 16 | 17 | Synthesis/Placement Summary: 18 | ---------------------------- 19 | Status: Successful 20 | Runtime: 2 seconds 21 | 22 | Device Info: 23 | ------------ 24 | Device Family: iCE40 25 | Device: iCE40LP8K 26 | Package: CM81 27 | 28 | Design statistics: 29 | ------------------ 30 | FFs: 529 31 | LUTs: 1381 32 | RAMs: 0 33 | IOBs: 5 34 | GBs: 7 35 | PLLs: 1 36 | Warm Boots: 0 37 | 38 | Logic Resource Utilization: 39 | --------------------------- 40 | Total Logic Cells: 1381/7680 41 | Combinational Logic Cells: 852 out of 7680 11.0938% 42 | Sequential Logic Cells: 529 out of 7680 6.88802% 43 | Logic Tiles: 252 out of 960 26.25% 44 | Registers: 45 | Logic Registers: 529 out of 7680 6.88802% 46 | IO Registers: 0 out of 1280 0 47 | Block RAMs: 0 out of 32 0% 48 | Warm Boots: 0 out of 1 0% 49 | Pins: 50 | Input Pins: 1 out of 63 1.5873% 51 | Output Pins: 2 out of 63 3.1746% 52 | InOut Pins: 2 out of 63 3.1746% 53 | Global Buffers: 7 out of 8 87.5% 54 | PLLs: 1 out of 1 100% 55 | 56 | IO Bank Utilization: 57 | -------------------- 58 | Bank 3: 1 out of 18 5.55556% 59 | Bank 1: 0 out of 15 0% 60 | Bank 0: 4 out of 17 23.5294% 61 | Bank 2: 0 out of 13 0% 62 | 63 | Detailed I/O Info: 64 | ------------------ 65 | Input Pins: 66 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 67 | ---------- --------- ----------- ------- ------- ----------- ----------- 68 | B2 Input SB_LVCMOS No 3 Simple Input clk 69 | 70 | Output Pins: 71 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 72 | ---------- --------- ----------- ------- ------- ----------- ----------- 73 | A3 Output SB_LVCMOS No 0 Output Tristatable by Enable usb_pu 74 | B3 Output SB_LVCMOS No 0 Simple Output led 75 | 76 | Inoutput Pins: 77 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 78 | ---------- --------- ----------- ------- ------- ----------- ----------- 79 | A4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_n 80 | B4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_p 81 | 82 | Detailed Global Buffer Info: 83 | ---------------------------- 84 | Buffer Number IO Bank Driven By Fanout Signal Name 85 | ------------- ------- --------- ------ ----------- 86 | 5 2 30 clk_0_c_g 87 | 3 3 43 u_usb_cdc.u_sie.in_zlp_q_0_sqmuxa_g 88 | 0 2 361 u_usb_cdc.rstn_i_g 89 | 2 1 72 u_usb_cdc.rstn_sq_i_g_0 90 | 1 0 92 u_usb_cdc.clk_gate_g 91 | 4 0 43 u_app.rstn_sq_i_g_0 92 | 7 1 68 clk_2mhz_g 93 | 94 | 95 | Router Summary: 96 | --------------- 97 | Status: Successful 98 | Runtime: 16 seconds 99 | 100 | Routing Resource Utilization: 101 | ----------------------------- 102 | Local line of tile 9842 out of 146184 6.73261% 103 | Span 4 2409 out of 29696 8.1122% 104 | Span 12 308 out of 5632 5.46875% 105 | Global network 8 out of 8 100% 106 | Vertical Inter-LUT Connect 317 out of 6720 4.71726% 107 | 108 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/iCEcube2/loopback_7ch/usb_cdc_Implmnt/sbt/outputs/loopback_7ch_sbt.rpt: -------------------------------------------------------------------------------- 1 | * ****************************************************************************** 2 | 3 | * iCEcube Report 4 | 5 | * Version: 2020.12.27943 6 | 7 | * Build Date: Dec 10 2020 17:24:17 8 | 9 | * File Generated: Mar 10 2024 17:58:31 10 | 11 | * Purpose: General info of design implementation 12 | 13 | * Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved. 14 | 15 | * ****************************************************************************** 16 | 17 | Synthesis/Placement Summary: 18 | ---------------------------- 19 | Status: Successful 20 | Runtime: 6 seconds 21 | 22 | Device Info: 23 | ------------ 24 | Device Family: iCE40 25 | Device: iCE40LP8K 26 | Package: CM81 27 | 28 | Design statistics: 29 | ------------------ 30 | FFs: 1838 31 | LUTs: 4611 32 | RAMs: 0 33 | IOBs: 5 34 | GBs: 7 35 | PLLs: 1 36 | Warm Boots: 0 37 | 38 | Logic Resource Utilization: 39 | --------------------------- 40 | Total Logic Cells: 4612/7680 41 | Combinational Logic Cells: 2774 out of 7680 36.1198% 42 | Sequential Logic Cells: 1838 out of 7680 23.9323% 43 | Logic Tiles: 704 out of 960 73.3333% 44 | Registers: 45 | Logic Registers: 1838 out of 7680 23.9323% 46 | IO Registers: 0 out of 1280 0 47 | Block RAMs: 0 out of 32 0% 48 | Warm Boots: 0 out of 1 0% 49 | Pins: 50 | Input Pins: 1 out of 63 1.5873% 51 | Output Pins: 2 out of 63 3.1746% 52 | InOut Pins: 2 out of 63 3.1746% 53 | Global Buffers: 7 out of 8 87.5% 54 | PLLs: 1 out of 1 100% 55 | 56 | IO Bank Utilization: 57 | -------------------- 58 | Bank 3: 1 out of 18 5.55556% 59 | Bank 1: 0 out of 15 0% 60 | Bank 0: 4 out of 17 23.5294% 61 | Bank 2: 0 out of 13 0% 62 | 63 | Detailed I/O Info: 64 | ------------------ 65 | Input Pins: 66 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 67 | ---------- --------- ----------- ------- ------- ----------- ----------- 68 | B2 Input SB_LVCMOS No 3 Simple Input clk 69 | 70 | Output Pins: 71 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 72 | ---------- --------- ----------- ------- ------- ----------- ----------- 73 | A3 Output SB_LVCMOS No 0 Output Tristatable by Enable usb_pu 74 | B3 Output SB_LVCMOS No 0 Simple Output led 75 | 76 | Inoutput Pins: 77 | Pin Number Direction IO Standard Pull Up IO Bank IO Function Signal Name 78 | ---------- --------- ----------- ------- ------- ----------- ----------- 79 | A4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_n 80 | B4 InOut SB_LVCMOS No 0 Simple Input Output Tristatable by Enable usb_p 81 | 82 | Detailed Global Buffer Info: 83 | ---------------------------- 84 | Buffer Number IO Bank Driven By Fanout Signal Name 85 | ------------- ------- --------- ------ ----------- 86 | 3 3 52 u_usb_cdc.u_sie.in_zlp_q_0_sqmuxa_g 87 | 0 2 1621 u_usb_cdc.rstn_i_g 88 | 1 0 70 u_usb_cdc.N_165_0_g 89 | 2 1 140 u_usb_cdc.app_rstn_sq_i_g_0 90 | 4 0 73 u_usb_cdc.rstn_sq_i_g_0 91 | 7 1 260 u_usb_cdc.clk_gate_q_g 92 | 5 2 142 clk_div4_g 93 | 94 | 95 | Router Summary: 96 | --------------- 97 | Status: Successful 98 | Runtime: 41 seconds 99 | 100 | Routing Resource Utilization: 101 | ----------------------------- 102 | Local line of tile 30896 out of 146184 21.135% 103 | Span 4 8640 out of 29696 29.0948% 104 | Span 12 1415 out of 5632 25.1243% 105 | Global network 8 out of 8 100% 106 | Vertical Inter-LUT Connect 974 out of 6720 14.494% 107 | 108 | -------------------------------------------------------------------------------- /examples/TinyFPGA-BX/hdl/bootloader/bootloader.v: -------------------------------------------------------------------------------- 1 | 2 | module bootloader 3 | ( 4 | input clk, // 16MHz Clock 5 | output led, // User LED ON=1, OFF=0 6 | inout usb_p, // USB+ 7 | inout usb_n, // USB- 8 | output usb_pu, // USB 1.5kOhm Pullup EN 9 | output sck, 10 | output ss, 11 | output sdo, 12 | input sdi 13 | ); 14 | 15 | localparam CHANNELS = 'd1; 16 | localparam BIT_SAMPLES = 'd4; 17 | localparam [6:0] DIVF = 12*BIT_SAMPLES-1; 18 | 19 | wire clk_pll; 20 | wire lock; 21 | wire dp_pu; 22 | wire dp_rx; 23 | wire dn_rx; 24 | wire dp_tx; 25 | wire dn_tx; 26 | wire tx_en; 27 | wire [7:0] out_data; 28 | wire out_valid; 29 | wire in_ready; 30 | wire [7:0] in_data; 31 | wire in_valid; 32 | wire out_ready; 33 | wire boot; 34 | wire [10:0] frame; 35 | wire configured; 36 | 37 | assign led = (configured) ? frame[9] : ~&frame[4:3]; 38 | 39 | // if FEEDBACK_PATH = SIMPLE: 40 | // clk_freq = (ref_freq * (DIVF + 1)) / (2**DIVQ * (DIVR + 1)); 41 | SB_PLL40_CORE #(.DIVR(4'd0), 42 | .DIVF(DIVF), 43 | .DIVQ(3'd4), 44 | .FILTER_RANGE(3'b001), 45 | .FEEDBACK_PATH("SIMPLE"), 46 | .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), 47 | .FDA_FEEDBACK(4'b0000), 48 | .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), 49 | .FDA_RELATIVE(4'b0000), 50 | .SHIFTREG_DIV_MODE(2'b00), 51 | .PLLOUT_SELECT("GENCLK"), 52 | .ENABLE_ICEGATE(1'b0)) 53 | u_pll (.REFERENCECLK(clk), // 16MHz 54 | .PLLOUTCORE(), 55 | .PLLOUTGLOBAL(clk_pll), // 48MHz 56 | .EXTFEEDBACK(1'b0), 57 | .DYNAMICDELAY(8'd0), 58 | .LOCK(lock), 59 | .BYPASS(1'b0), 60 | .RESETB(1'b1), 61 | .SDI(1'b0), 62 | .SDO(), 63 | .SCLK(1'b0), 64 | .LATCHINPUTVALUE(1'b1)); 65 | 66 | app u_app (.clk_i(clk), 67 | .rstn_i(lock), 68 | .out_data_i(out_data), 69 | .out_valid_i(out_valid), 70 | .in_ready_i(in_ready), 71 | .out_ready_o(out_ready), 72 | .in_data_o(in_data), 73 | .in_valid_o(in_valid), 74 | .heartbeat_i(configured & frame[0]), 75 | .boot_o(boot), 76 | .sck_o(sck), 77 | .csn_o(ss), 78 | .mosi_o(sdo), 79 | .miso_i(sdi)); 80 | 81 | usb_cdc #(.VENDORID(16'h1D50), 82 | .PRODUCTID(16'h6130), 83 | .CHANNELS(CHANNELS), 84 | .IN_BULK_MAXPACKETSIZE('d8), 85 | .OUT_BULK_MAXPACKETSIZE('d8), 86 | .BIT_SAMPLES(BIT_SAMPLES), 87 | .USE_APP_CLK(1), 88 | .APP_CLK_FREQ(16)) // 16MHz 89 | u_usb_cdc (.frame_o(frame), 90 | .configured_o(configured), 91 | .app_clk_i(clk), 92 | .clk_i(clk_pll), 93 | .rstn_i(lock), 94 | .out_ready_i(out_ready), 95 | .in_data_i(in_data), 96 | .in_valid_i(in_valid), 97 | .dp_rx_i(dp_rx), 98 | .dn_rx_i(dn_rx), 99 | .out_data_o(out_data), 100 | .out_valid_o(out_valid), 101 | .in_ready_o(in_ready), 102 | .dp_pu_o(dp_pu), 103 | .tx_en_o(tx_en), 104 | .dp_tx_o(dp_tx), 105 | .dn_tx_o(dn_tx)); 106 | 107 | SB_WARMBOOT u_warmboot (.S1(1'b0), 108 | .S0(1'b1), 109 | .BOOT(boot)); 110 | 111 | SB_IO #(.PIN_TYPE(6'b101001), 112 | .PULLUP(1'b0)) 113 | u_usb_p (.PACKAGE_PIN(usb_p), 114 | .OUTPUT_ENABLE(tx_en), 115 | .D_OUT_0(dp_tx), 116 | .D_IN_0(dp_rx), 117 | .D_OUT_1(1'b0), 118 | .D_IN_1(), 119 | .CLOCK_ENABLE(1'b0), 120 | .LATCH_INPUT_VALUE(1'b0), 121 | .INPUT_CLK(1'b0), 122 | .OUTPUT_CLK(1'b0)); 123 | 124 | SB_IO #(.PIN_TYPE(6'b101001), 125 | .PULLUP(1'b0)) 126 | u_usb_n (.PACKAGE_PIN(usb_n), 127 | .OUTPUT_ENABLE(tx_en), 128 | .D_OUT_0(dn_tx), 129 | .D_IN_0(dn_rx), 130 | .D_OUT_1(1'b0), 131 | .D_IN_1(), 132 | .CLOCK_ENABLE(1'b0), 133 | .LATCH_INPUT_VALUE(1'b0), 134 | .INPUT_CLK(1'b0), 135 | .OUTPUT_CLK(1'b0)); 136 | 137 | // drive usb_pu to 3.3V or to high impedance 138 | SB_IO #(.PIN_TYPE(6'b101001), 139 | .PULLUP(1'b0)) 140 | u_usb_pu (.PACKAGE_PIN(usb_pu), 141 | .OUTPUT_ENABLE(dp_pu), 142 | .D_OUT_0(1'b1), 143 | .D_IN_0(), 144 | .D_OUT_1(1'b0), 145 | .D_IN_1(), 146 | .CLOCK_ENABLE(1'b0), 147 | .LATCH_INPUT_VALUE(1'b0), 148 | .INPUT_CLK(1'b0), 149 | .OUTPUT_CLK(1'b0)); 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /examples/Fomu/OSS_CAD_Suite/output/loopback/loopback.rpt: -------------------------------------------------------------------------------- 1 | 2 | icetime topological timing analysis report 3 | ========================================== 4 | 5 | Info: max_span_hack is enabled: estimate is conservative. 6 | 7 | Report for critical path: 8 | ------------------------- 9 | 10 | lc40_7_8_2 (LogicCell40) [clk] -> lcout: 1.491 ns 11 | 1.491 ns net_27279 (u_usb_cdc.u_sie.delay_cnt_q[2]) 12 | t2696 (LocalMux) I -> O: 1.099 ns 13 | inmux_7_8_30714_30753 (InMux) I -> O: 0.662 ns 14 | lc40_7_8_4 (LogicCell40) in0 -> lcout: 1.285 ns 15 | 4.537 ns net_27281 (u_usb_cdc.u_sie.out_eop_q_SB_LUT4_I1_I2[2]) 16 | t2698 (LocalMux) I -> O: 1.099 ns 17 | inmux_8_9_34670_34719 (InMux) I -> O: 0.662 ns 18 | lc40_8_9_6 (LogicCell40) in0 -> lcout: 1.285 ns 19 | 7.583 ns net_30784 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0]) 20 | odrv_8_9_30784_30807 (Odrv4) I -> O: 0.649 ns 21 | t3239 (Span4Mux_h4) I -> O: 0.543 ns 22 | t3238 (Span4Mux_v4) I -> O: 0.649 ns 23 | t3237 (Span4Mux_v4) I -> O: 0.649 ns 24 | t3236 (LocalMux) I -> O: 1.099 ns 25 | inmux_11_18_47276_47313 (InMux) I -> O: 0.662 ns 26 | lc40_11_18_5 (LogicCell40) in0 -> lcout: 1.285 ns 27 | 13.119 ns net_43383 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_O_I2[3]) 28 | t4696 (LocalMux) I -> O: 1.099 ns 29 | inmux_11_19_47386_47437 (InMux) I -> O: 0.662 ns 30 | lc40_11_19_5 (LogicCell40) in1 -> lcout: 1.232 ns 31 | 16.113 ns net_43506 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_I2_O[1]) 32 | t4714 (LocalMux) I -> O: 1.099 ns 33 | inmux_10_20_43670_43716 (InMux) I -> O: 0.662 ns 34 | lc40_10_20_3 (LogicCell40) in0 -> lcout: 1.285 ns 35 | 19.159 ns net_39796 (u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_I1_I0[2]) 36 | odrv_10_20_39796_39942 (Odrv4) I -> O: 0.649 ns 37 | t4487 (LocalMux) I -> O: 1.099 ns 38 | inmux_9_23_40214_40255 (InMux) I -> O: 0.662 ns 39 | lc40_9_23_3 (LogicCell40) in1 -> lcout: 1.232 ns 40 | 22.801 ns net_36334 (u_usb_cdc.u_sie.out_eop_q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]) 41 | t4114 (LocalMux) I -> O: 1.099 ns 42 | inmux_9_23_40206_40239 (InMux) I -> O: 0.662 ns 43 | lc40_9_23_0 (LogicCell40) in3 -> lcout: 0.874 ns 44 | 25.437 ns net_36331 (u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_I1_I0_SB_LUT4_I3_O[1]) 45 | t4103 (LocalMux) I -> O: 1.099 ns 46 | inmux_8_23_36396_36406 (InMux) I -> O: 0.662 ns 47 | lc40_8_23_0 (LogicCell40) in1 -> lcout: 1.232 ns 48 | 28.430 ns net_32500 (u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_LUT4_O_2_I1[1]) 49 | odrv_8_23_32500_28961 (Odrv4) I -> O: 0.649 ns 50 | t3619 (Span4Mux_v4) I -> O: 0.649 ns 51 | t3618 (LocalMux) I -> O: 1.099 ns 52 | inmux_5_22_25416_25427 (InMux) I -> O: 0.662 ns 53 | lc40_5_22_1 (LogicCell40) in1 -> lcout: 1.232 ns 54 | 32.721 ns net_21516 (u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_I1_I0_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I3_O[2]) 55 | odrv_5_22_21516_21659 (Odrv4) I -> O: 0.649 ns 56 | t2643 (Span4Mux_v4) I -> O: 0.649 ns 57 | t2642 (LocalMux) I -> O: 1.099 ns 58 | inmux_7_25_32813_32840 (InMux) I -> O: 0.662 ns 59 | t571 (CascadeMux) I -> O: 0.000 ns 60 | lc40_7_25_3 (LogicCell40) in2 -> lcout: 1.205 ns 61 | 36.986 ns net_29014 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_D_SB_LUT4_O_I0[0]) 62 | t3202 (LocalMux) I -> O: 1.099 ns 63 | inmux_7_25_32806_32833 (InMux) I -> O: 0.662 ns 64 | 38.748 ns net_32833 (u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_D_SB_LUT4_O_I0[0]) 65 | lc40_7_25_2 (LogicCell40) in1 [setup]: 1.007 ns 66 | 39.754 ns net_29013 (u_usb_cdc.u_ctrl_endp.req_q[11]) 67 | 68 | Resolvable net names on path: 69 | 1.491 ns .. 3.252 ns u_usb_cdc.u_sie.delay_cnt_q[2] 70 | 4.537 ns .. 6.298 ns u_usb_cdc.u_sie.out_eop_q_SB_LUT4_I1_I2[2] 71 | 7.583 ns .. 11.835 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0] 72 | 13.119 ns .. 14.881 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_O_I2[3] 73 | 16.113 ns .. 17.874 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_I2_O[1] 74 | 19.159 ns .. 21.569 ns u_usb_cdc.u_ctrl_endp.state_q_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_I1_I0[2] 75 | 22.801 ns .. 24.563 ns u_usb_cdc.u_sie.out_eop_q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1] 76 | 25.437 ns .. 27.198 ns u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_I1_I0_SB_LUT4_I3_O[1] 77 | 28.430 ns .. 31.490 ns u_usb_cdc.u_ctrl_endp.class_q_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_LUT4_O_2_I1[1] 78 | 32.721 ns .. 35.781 ns u_usb_cdc.ctrl_stall_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_I1_I0_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I3_O[2] 79 | 36.986 ns .. 38.748 ns u_usb_cdc.u_ctrl_endp.req_q_SB_DFFR_Q_D_SB_LUT4_O_I0[0] 80 | lcout -> u_usb_cdc.u_ctrl_endp.req_q[11] 81 | 82 | Total number of logic levels: 11 83 | Total path delay: 39.75 ns (25.15 MHz) 84 | 85 | -------------------------------------------------------------------------------- /examples/Fomu/hdl/loopback/loopback.v: -------------------------------------------------------------------------------- 1 | // Correctly map pins for the iCE40UP5K SB_RGBA_DRV hard macro. 2 | // The variables EVT, PVT and HACKER are set from the Makefile. 3 | `ifdef EVT 4 | `define BLUEPWM RGB0PWM 5 | `define REDPWM RGB1PWM 6 | `define GREENPWM RGB2PWM 7 | `elsif HACKER 8 | `define BLUEPWM RGB0PWM 9 | `define GREENPWM RGB1PWM 10 | `define REDPWM RGB2PWM 11 | `elsif PVT 12 | `define GREENPWM RGB0PWM 13 | `define REDPWM RGB1PWM 14 | `define BLUEPWM RGB2PWM 15 | `endif 16 | 17 | module loopback 18 | ( 19 | input clki, // 48MHz Clock 20 | output rgb0, // Red LED 21 | output rgb1, // Green LED 22 | output rgb2, // Blue LED 23 | inout usb_dp, // USB+ 24 | inout usb_dn, // USB- 25 | output usb_dp_pu // USB 1.5kOhm Pullup EN 26 | ); 27 | 28 | wire clk_3mhz; 29 | wire clk_6mhz; 30 | wire clk_12mhz; 31 | wire clk_24mhz; 32 | wire dp_pu; 33 | wire dp_rx; 34 | wire dn_rx; 35 | wire dp_tx; 36 | wire dn_tx; 37 | wire tx_en; 38 | wire [7:0] out_data; 39 | wire out_valid; 40 | wire in_ready; 41 | wire [7:0] in_data; 42 | wire in_valid; 43 | wire out_ready; 44 | wire [2:0] led; 45 | 46 | assign led = {2'b00, ~dp_pu}; 47 | 48 | // Connect to system clock (with buffering) 49 | wire clk; 50 | SB_GB clk_gb (.USER_SIGNAL_TO_GLOBAL_BUFFER(clki), 51 | .GLOBAL_BUFFER_OUTPUT(clk)); 52 | 53 | reg [1:0] rstn_sync = 0; 54 | 55 | wire rstn; 56 | 57 | assign rstn = rstn_sync[0]; 58 | 59 | always @(posedge clk) begin 60 | rstn_sync <= {1'b1, rstn_sync[1]}; 61 | end 62 | 63 | prescaler u_prescaler (.clk_i(clk), 64 | .rstn_i(rstn), 65 | .clk_div16_o(clk_3mhz), 66 | .clk_div8_o(clk_6mhz), 67 | .clk_div4_o(clk_12mhz), 68 | .clk_div2_o(clk_24mhz)); 69 | 70 | // Instantiate iCE40 LED driver hard logic. 71 | // 72 | // Note that it's possible to drive the LEDs directly, 73 | // however that is not current-limited and results in 74 | // overvolting the red LED. 75 | // 76 | // See also: 77 | // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK/ICE40LEDDriverUsageGuide.ashx?document_id=50668 78 | SB_RGBA_DRV #(.CURRENT_MODE("0b1"), // half current 79 | .RGB0_CURRENT("0b000011"), // 4 mA 80 | .RGB1_CURRENT("0b000011"), // 4 mA 81 | .RGB2_CURRENT("0b000011")) // 4 mA 82 | RGBA_DRIVER (.CURREN(1'b1), 83 | .RGBLEDEN(1'b1), 84 | .`REDPWM(led[0]), // Red 85 | .`GREENPWM(led[1]), // Green 86 | .`BLUEPWM(led[2]), // Blue 87 | .RGB0(rgb0), 88 | .RGB1(rgb1), 89 | .RGB2(rgb2)); 90 | 91 | usb_cdc #(.VENDORID(16'h1209), 92 | .PRODUCTID(16'h5BF0), 93 | .IN_BULK_MAXPACKETSIZE('d8), 94 | .OUT_BULK_MAXPACKETSIZE('d8), 95 | .BIT_SAMPLES('d4), 96 | .USE_APP_CLK(1), 97 | .APP_CLK_FREQ(12)) // 12MHz 98 | u_usb_cdc (.frame_o(), 99 | .configured_o(), 100 | .app_clk_i(clk_12mhz), 101 | .clk_i(clk), 102 | .rstn_i(rstn), 103 | .out_ready_i(in_ready), 104 | .in_data_i(out_data), 105 | .in_valid_i(out_valid), 106 | .dp_rx_i(dp_rx), 107 | .dn_rx_i(dn_rx), 108 | .out_data_o(out_data), 109 | .out_valid_o(out_valid), 110 | .in_ready_o(in_ready), 111 | .dp_pu_o(dp_pu), 112 | .tx_en_o(tx_en), 113 | .dp_tx_o(dp_tx), 114 | .dn_tx_o(dn_tx)); 115 | 116 | SB_IO #(.PIN_TYPE(6'b101001), 117 | .PULLUP(1'b0)) 118 | u_usb_dp (.PACKAGE_PIN(usb_dp), 119 | .OUTPUT_ENABLE(tx_en), 120 | .D_OUT_0(dp_tx), 121 | .D_IN_0(dp_rx), 122 | .D_OUT_1(1'b0), 123 | .D_IN_1(), 124 | .CLOCK_ENABLE(1'b0), 125 | .LATCH_INPUT_VALUE(1'b0), 126 | .INPUT_CLK(1'b0), 127 | .OUTPUT_CLK(1'b0)); 128 | 129 | SB_IO #(.PIN_TYPE(6'b101001), 130 | .PULLUP(1'b0)) 131 | u_usb_dn (.PACKAGE_PIN(usb_dn), 132 | .OUTPUT_ENABLE(tx_en), 133 | .D_OUT_0(dn_tx), 134 | .D_IN_0(dn_rx), 135 | .D_OUT_1(1'b0), 136 | .D_IN_1(), 137 | .CLOCK_ENABLE(1'b0), 138 | .LATCH_INPUT_VALUE(1'b0), 139 | .INPUT_CLK(1'b0), 140 | .OUTPUT_CLK(1'b0)); 141 | 142 | // drive usb_pu to 3.3V or to high impedance 143 | SB_IO #(.PIN_TYPE(6'b101001), 144 | .PULLUP(1'b0)) 145 | u_usb_pu (.PACKAGE_PIN(usb_dp_pu), 146 | .OUTPUT_ENABLE(dp_pu), 147 | .D_OUT_0(1'b1), 148 | .D_IN_0(), 149 | .D_OUT_1(1'b0), 150 | .D_IN_1(), 151 | .CLOCK_ENABLE(1'b0), 152 | .LATCH_INPUT_VALUE(1'b0), 153 | .INPUT_CLK(1'b0), 154 | .OUTPUT_CLK(1'b0)); 155 | 156 | endmodule 157 | --------------------------------------------------------------------------------