├── LICENSE ├── README.md ├── boards └── digilent_digital_discovery │ ├── README.md │ ├── dcm12_100.v │ ├── dcm12_48.v │ ├── fpga.ucf │ ├── fpga_top.v │ ├── ipcore_dir │ ├── coregen.cgp │ ├── mig.gise │ ├── mig.prj │ ├── mig.xco │ ├── mig.xise │ └── mig │ │ └── user_design │ │ ├── datasheet.txt │ │ ├── mig.prj │ │ ├── par │ │ ├── create_ise.sh │ │ ├── icon_coregen.xco │ │ ├── ila_coregen.xco │ │ ├── ise_flow.sh │ │ ├── ise_run.txt │ │ ├── makeproj.sh │ │ ├── mem_interface_top.ut │ │ ├── mig.ucf │ │ ├── readme.txt │ │ ├── rem_files.sh │ │ ├── set_ise_prop.tcl │ │ └── vio_coregen.xco │ │ ├── rtl │ │ ├── axi │ │ │ ├── a_upsizer.v │ │ │ ├── axi_mcb.v │ │ │ ├── axi_mcb_ar_channel.v │ │ │ ├── axi_mcb_aw_channel.v │ │ │ ├── axi_mcb_b_channel.v │ │ │ ├── axi_mcb_cmd_arbiter.v │ │ │ ├── axi_mcb_cmd_fsm.v │ │ │ ├── axi_mcb_cmd_translator.v │ │ │ ├── axi_mcb_incr_cmd.v │ │ │ ├── axi_mcb_r_channel.v │ │ │ ├── axi_mcb_simple_fifo.v │ │ │ ├── axi_mcb_w_channel.v │ │ │ ├── axi_mcb_wrap_cmd.v │ │ │ ├── axi_register_slice.v │ │ │ ├── axi_upsizer.v │ │ │ ├── axic_register_slice.v │ │ │ ├── carry.v │ │ │ ├── carry_and.v │ │ │ ├── carry_latch_and.v │ │ │ ├── carry_latch_or.v │ │ │ ├── carry_or.v │ │ │ ├── command_fifo.v │ │ │ ├── comparator.v │ │ │ ├── comparator_mask.v │ │ │ ├── comparator_mask_static.v │ │ │ ├── comparator_sel.v │ │ │ ├── comparator_sel_mask.v │ │ │ ├── comparator_sel_mask_static.v │ │ │ ├── comparator_sel_static.v │ │ │ ├── comparator_static.v │ │ │ ├── mcb_ui_top_synch.v │ │ │ ├── mux_enc.v │ │ │ ├── r_upsizer.v │ │ │ └── w_upsizer.v │ │ ├── infrastructure.v │ │ ├── mcb_controller │ │ │ ├── iodrp_controller.v │ │ │ ├── iodrp_mcb_controller.v │ │ │ ├── mcb_raw_wrapper.v │ │ │ ├── mcb_soft_calibration.v │ │ │ ├── mcb_soft_calibration_top.v │ │ │ └── mcb_ui_top.v │ │ ├── memc_wrapper.v │ │ └── mig.v │ │ ├── sim │ │ ├── axi4_tg.v │ │ ├── axi4_wrapper.v │ │ ├── cmd_prbs_gen_axi.v │ │ ├── data_gen_chk.v │ │ ├── ddr3_model_c3.v │ │ ├── ddr3_model_parameters_c3.vh │ │ ├── isim.sh │ │ ├── isim.tcl │ │ ├── mig.prj │ │ ├── readme.txt │ │ ├── s6_axi4_tg.v │ │ ├── sim.do │ │ ├── sim_tb_top.v │ │ └── tg.v │ │ └── synth │ │ ├── mem_interface_top_synp.sdc │ │ ├── mig.lso │ │ ├── mig.prj │ │ └── script_synp.tcl │ ├── prebuilt │ └── fpga.bit │ ├── reset_gen.v │ ├── spartan6_pll.v │ └── top.v ├── core ├── capture │ ├── capture_rle.v │ ├── capture_rle_cdc.v │ ├── logic_capture.v │ ├── logic_capture_defs.v │ ├── logic_capture_fifo.v │ ├── logic_capture_mem.v │ ├── logic_capture_mem_axi.v │ ├── logic_capture_mem_axi_axi.v │ ├── logic_capture_mem_fifo_ram.v │ └── logic_capture_mem_track_fifo.v ├── fabric │ ├── axi4_arb.v │ ├── axi4_cdc.v │ ├── axi4_cdc_fifo37.v │ ├── axi4_cdc_fifo39.v │ ├── axi4_cdc_fifo46.v │ ├── axi4_cdc_fifo6.v │ ├── axi4_lite_tap.v │ └── axi4_retime.v └── ft245 │ ├── ft245_axi.v │ ├── ft245_axi_retime.v │ └── ft245_fifo.v └── docs ├── pulseview_counter.png ├── pulseview_spdif.png └── pulseview_uart.png /README.md: -------------------------------------------------------------------------------- 1 | # open-logic-bit 2 | *Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.* 3 | 4 | Github: [https://github.com/ultraembedded/openlogicbit](https://github.com/ultraembedded/openlogicbit) 5 | 6 | ![Demo-uart](docs/pulseview_uart.png) 7 | 8 | ## Aims 9 | A logic analyzer project which aims to provide reliable, high speed (100MHz+), large capture depth, open-source gateware that can be used on a FPGA development board you already own, or as replacement gateware for commercial logic analysers that do not work with open-source tools such as [sigrok](https://sigrok.org/). 10 | 11 | This project aims to support FPGA boards with 10's MBs of capture memory (such as DDR3), which also have high-speed USB interfaces from which to download the captured data. 12 | 13 | There are a number of other open-source logic analyzer projects, but these mostly focus on using limited internal FPGA memories (embedded block RAMs), and low-performance host interfaces (UART). 14 | 15 | ## Features 16 | * 16, 24, 32 input channels supported. 17 | * Run-length encoded (RLE) compression to extend the sample buffer depth. 18 | * Support for boards with large memories (DDR, SDRAM). 19 | * Up to 32 triggers supporting edge, level, value match modes. 20 | * Support for boards with FTDI sync FIFO mode support (FT232H, FT2232H). 21 | * Support for external clock sources. 22 | * Continuous or one-shot capture modes. 23 | * libsigrok support available (enabling support for Sigrok, Pulseview). 24 | 25 | *A screenshot of Sigrok capturing a SPDIF signal at 100MHz with open-logic-bit running on a Digilent Digital Discovery;* 26 | ![Demo-spdif](docs/pulseview_spdif.png) 27 | 28 | ## Supported Boards 29 | * [Digilent Digital Discovery](https://reference.digilentinc.com/test-and-measurement/digital-discovery/start) 30 | * More to come... 31 | 32 | ## Software 33 | Compatible with Sigrok (via libsigrok), based on the following fork; 34 | * [https://github.com/ultraembedded/libsigrok](https://github.com/ultraembedded/libsigrok) 35 | 36 | *open-logic-bit also contains a built in test mode;* 37 | ![Demo-counter](docs/pulseview_counter.png) 38 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/README.md: -------------------------------------------------------------------------------- 1 | # Digilent Digital Discovery 2 | 3 | The Digilent Digital Discovery is a 24-channel digital logic analyzer that comes with some free but proprietary software called WaveForms. 4 | 5 | The device does not have persistent flash storage for FPGA bitstreams, so one must be loaded each time the power is applied. 6 | 7 | ## Loading bitstreams 8 | ``` 9 | # Acquire openFPGALoader from https://github.com/trabucayre/openFPGALoader 10 | 11 | # Load the open-logic-bit gateware onto the device 12 | sudo openFPGALoader -c digilent_ad prebuilt/fpga.bit 13 | ``` 14 | 15 | ## Disclaimer 16 | I have used the Digilent Digital Discovery reference manual schematics, and a bit of reverse engineering to guess the clock and FTDI connections. 17 | Nothing should be persistently changed on the device, but use at your own risk - it works well for me, but if some magic smoke should escape, do not blame me, etc... -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/dcm12_100.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------- 2 | // open-logic-bit 3 | // V0.1 4 | // Copyright 2021 5 | // github.com/ultraembedded/openlogicbit 6 | // 7 | // admin@ultra-embedded.com 8 | // 9 | // License: Apache 2.0 10 | //----------------------------------------------------------------- 11 | // Copyright 2021 Ultra-Embedded.com 12 | // 13 | // Licensed under the Apache License, Version 2.0 (the "License"); 14 | // you may not use this file except in compliance with the License. 15 | // You may obtain a copy of the License at 16 | // 17 | // http://www.apache.org/licenses/LICENSE-2.0 18 | // 19 | // Unless required by applicable law or agreed to in writing, software 20 | // distributed under the License is distributed on an "AS IS" BASIS, 21 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | // See the License for the specific language governing permissions and 23 | // limitations under the License. 24 | //----------------------------------------------------------------- 25 | module dcm12_100 26 | ( 27 | // Inputs 28 | input clkref_i 29 | 30 | // Outputs 31 | ,output clkout0_o 32 | ); 33 | 34 | wire clkref_buffered_w; 35 | wire clkfb; 36 | wire clk0; 37 | wire clkfx; 38 | 39 | // Clocking primitive 40 | DCM_SP 41 | #( 42 | .CLKDV_DIVIDE(2.000), 43 | .CLKFX_DIVIDE(3), 44 | .CLKFX_MULTIPLY(25), 45 | .CLKIN_PERIOD(83.3333333333), 46 | .CLKOUT_PHASE_SHIFT("NONE"), 47 | .CLK_FEEDBACK("1X"), 48 | .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), 49 | .PHASE_SHIFT(0) 50 | ) 51 | dcm_sp_inst 52 | ( 53 | .CLKIN(clkref_i), 54 | .CLKFB(clkfb), 55 | // Output clocks 56 | .CLK0(clk0), // 100MHz 57 | .CLK90(), 58 | .CLK180(), 59 | .CLK270(), 60 | .CLK2X(), 61 | .CLK2X180(), 62 | .CLKFX(clkfx), 63 | .CLKFX180(), 64 | .CLKDV(), 65 | // Ports for dynamic phase shift 66 | .PSCLK(1'b0), 67 | .PSEN(1'b0), 68 | .PSINCDEC(1'b0), 69 | .PSDONE(), 70 | // Other control and status signals, 71 | .LOCKED(), 72 | .STATUS(), 73 | .RST(1'b0), 74 | // Unused pin, tie low 75 | .DSSEN(1'b0) 76 | ); 77 | 78 | BUFG clkfb_buf 79 | ( 80 | .I(clk0), 81 | .O(clkfb) 82 | ); 83 | 84 | //----------------------------------------------------------------- 85 | // CLK_OUT0 86 | //----------------------------------------------------------------- 87 | BUFG clkout0_buf 88 | ( 89 | .I(clkfx), 90 | .O(clkout0_o) 91 | ); 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/dcm12_48.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------- 2 | // open-logic-bit 3 | // V0.1 4 | // Copyright 2021 5 | // github.com/ultraembedded/openlogicbit 6 | // 7 | // admin@ultra-embedded.com 8 | // 9 | // License: Apache 2.0 10 | //----------------------------------------------------------------- 11 | // Copyright 2021 Ultra-Embedded.com 12 | // 13 | // Licensed under the Apache License, Version 2.0 (the "License"); 14 | // you may not use this file except in compliance with the License. 15 | // You may obtain a copy of the License at 16 | // 17 | // http://www.apache.org/licenses/LICENSE-2.0 18 | // 19 | // Unless required by applicable law or agreed to in writing, software 20 | // distributed under the License is distributed on an "AS IS" BASIS, 21 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | // See the License for the specific language governing permissions and 23 | // limitations under the License. 24 | //----------------------------------------------------------------- 25 | module dcm12_48 26 | ( 27 | // Inputs 28 | input clkref_i 29 | 30 | // Outputs 31 | ,output clkout0_o 32 | ); 33 | 34 | wire clkref_buffered_w; 35 | wire clkfb; 36 | wire clk0; 37 | wire clkfx; 38 | 39 | // Clocking primitive 40 | DCM_SP 41 | #( 42 | .CLKDV_DIVIDE(2.000), 43 | .CLKFX_DIVIDE(1), 44 | .CLKFX_MULTIPLY(4), 45 | .CLKIN_PERIOD(83.3333333333), 46 | .CLKOUT_PHASE_SHIFT("NONE"), 47 | .CLK_FEEDBACK("1X"), 48 | .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), 49 | .PHASE_SHIFT(0) 50 | ) 51 | dcm_sp_inst 52 | ( 53 | .CLKIN(clkref_i), 54 | .CLKFB(clkfb), 55 | // Output clocks 56 | .CLK0(clk0), // 48MHz 57 | .CLK90(), 58 | .CLK180(), 59 | .CLK270(), 60 | .CLK2X(), 61 | .CLK2X180(), 62 | .CLKFX(clkfx), 63 | .CLKFX180(), 64 | .CLKDV(), 65 | // Ports for dynamic phase shift 66 | .PSCLK(1'b0), 67 | .PSEN(1'b0), 68 | .PSINCDEC(1'b0), 69 | .PSDONE(), 70 | // Other control and status signals, 71 | .LOCKED(), 72 | .STATUS(), 73 | .RST(1'b0), 74 | // Unused pin, tie low 75 | .DSSEN(1'b0) 76 | ); 77 | 78 | BUFG clkfb_buf 79 | ( 80 | .I(clk0), 81 | .O(clkfb) 82 | ); 83 | 84 | //----------------------------------------------------------------- 85 | // CLK_OUT0 86 | //----------------------------------------------------------------- 87 | BUFG clkout0_buf 88 | ( 89 | .I(clkfx), 90 | .O(clkout0_o) 91 | ); 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = Verilog 3 | SET device = xc6slx25 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = csg324 7 | SET speedgrade = -2 8 | SET verilogsim = true 9 | SET vhdlsim = false 10 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig.prj: -------------------------------------------------------------------------------- 1 | 2 | 3 | mig 4 | xc6slx25-csg324/-2 5 | 3.92 6 | 7 | DDR3_SDRAM/Components/MT41J128M16XX-125 8 | 3205 9 | 0 10 | 1 11 | FALSE 12 | 13 | 14 14 | 10 15 | 3 16 | 17 | 18 | 19 | 8(00) 20 | 6 21 | Enable 22 | RZQ/6 23 | RZQ/4 24 | 0 25 | Disabled 26 | Disabled 27 | Full Array 28 | 5 29 | Enabled 30 | Normal 31 | AXI,AXI,AXI,AXI,AXI,AXI 32 | 33 | 32 34 | 32 35 | 0 36 | 4 37 | 0 38 | 0 39 | 40 | Class II 41 | Class II 42 | CALIB_TERM 43 | 25 Ohms 44 | 45 | 46 | 47 | Single-Ended 48 | 1 49 | Disable 50 | Single-Ended 51 | Two 32-bit bi-directional and four 32-bit unidirectional ports 52 | N4 53 | P4 54 | Port0 55 | Bi-directional,none,none,none,none,none 56 | ROW_BANK_COLUMN 57 | Round Robin 58 | 0 59 | 0 60 | 0 61 | 0 62 | 0 63 | 0 64 | 0 65 | 0 66 | 0 67 | 0 68 | 0 69 | 0 70 | 71 | 72 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Sun Jun 6 17:31:57 2021 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:mig:3.92 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx25 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = csg324 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92 40 | # END Select 41 | # BEGIN Parameters 42 | CSET component_name=mig 43 | CSET xml_input_file=./mig/user_design/mig.prj 44 | # END Parameters 45 | # BEGIN Extra information 46 | MISC pkg_timestamp=2013-10-13T18:46:09Z 47 | # END Extra information 48 | GENERATE 49 | # CRC: 5bb663a8 50 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/datasheet.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | CORE Generator Options: 4 | Target Device : xc6slx25-csg324 5 | Speed Grade : -2 6 | HDL : verilog 7 | Synthesis Tool : Foundation_ISE 8 | 9 | MIG Output Options: 10 | Component Name : mig 11 | No of Controllers : 1 12 | Hardware Test Bench : disabled 13 | 14 | 15 | /*******************************************************/ 16 | /* Controller 3 */ 17 | /*******************************************************/ 18 | Controller Options : 19 | Memory : DDR3_SDRAM 20 | Interface : AXI 21 | Design Clock Frequency : 3205 ps (312.01 MHz) 22 | Memory Type : Components 23 | Memory Part : MT41J128M16XX-125 24 | Equivalent Part(s) : MT41J128M16HA-125 25 | Row Address : 14 26 | Column Address : 10 27 | Bank Address : 3 28 | Data Mask : enabled 29 | 30 | Memory Options : 31 | Burst Length : 8(00) 32 | CAS Latency : 6 33 | TDQS enable : Disabled 34 | DLL Enable : Enable 35 | Write Leveling Enable : Disabled 36 | Output Drive Strength : RZQ/6 37 | Additive Latency (AL) : 0 38 | RTT (nominal) - ODT : RZQ/4 39 | Auto Self Refresh : Enabled 40 | CAS write latency : 5 41 | Partial-Array Self Refresh : Full Array 42 | High Temparature Self Refresh Rate : Normal 43 | 44 | User Interface Parameters : 45 | Configuration Type : Two 32-bit bi-directional and four 32-bit unidirectional ports 46 | Ports Selected : Port0 47 | Memory Address Mapping : ROW_BANK_COLUMN 48 | 49 | Arbitration Algorithm : Round Robin 50 | 51 | Arbitration : 52 | Time Slot0 : 0 53 | Time Slot1 : 0 54 | Time Slot2 : 0 55 | Time Slot3 : 0 56 | Time Slot4 : 0 57 | Time Slot5 : 0 58 | Time Slot6 : 0 59 | Time Slot7 : 0 60 | Time Slot8 : 0 61 | Time Slot9 : 0 62 | Time Slot10: 0 63 | Time Slot11: 0 64 | 65 | FPGA Options : 66 | Class for Address and Control : II 67 | Class for Data : II 68 | Memory Interface Pin Termination : CALIB_TERM 69 | DQ/DQS : 25 Ohms 70 | Bypass Calibration : enabled 71 | Debug Signals for Memory Controller : Disable 72 | Input Clock Type : Single-Ended 73 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/mig.prj: -------------------------------------------------------------------------------- 1 | 2 | 3 | mig 4 | xc6slx25-csg324/-2 5 | 3.92 6 | 7 | DDR3_SDRAM/Components/MT41J128M16XX-125 8 | 3205 9 | 0 10 | 1 11 | FALSE 12 | 13 | 14 14 | 10 15 | 3 16 | 17 | 18 | 19 | 8(00) 20 | 6 21 | Enable 22 | RZQ/6 23 | RZQ/4 24 | 0 25 | Disabled 26 | Disabled 27 | Full Array 28 | 5 29 | Enabled 30 | Normal 31 | AXI,AXI,AXI,AXI,AXI,AXI 32 | 33 | 32 34 | 32 35 | 0 36 | 4 37 | 0 38 | 0 39 | 40 | Class II 41 | Class II 42 | CALIB_TERM 43 | 25 Ohms 44 | 45 | 46 | 47 | Single-Ended 48 | 1 49 | Disable 50 | Single-Ended 51 | Two 32-bit bi-directional and four 32-bit unidirectional ports 52 | N4 53 | P4 54 | Port0 55 | Bi-directional,none,none,none,none,none 56 | ROW_BANK_COLUMN 57 | Round Robin 58 | 0 59 | 0 60 | 0 61 | 0 62 | 0 63 | 0 64 | 0 65 | 0 66 | 0 67 | 0 68 | 0 69 | 0 70 | 71 | 72 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/create_ise.sh: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | #***************************************************************************** 3 | # (c) Copyright 2009 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | # **************************************************************************** 50 | # ____ ____ 51 | # / /\/ / 52 | # /___/ \ / Vendor : Xilinx 53 | # \ \ \/ Version : 3.92 54 | # \ \ Application : MIG 55 | # / / Filename : create_ise.bat 56 | # /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $ 57 | # \ \ / \ Date Created : Fri Feb 06 2009 58 | # \___\/\___\ 59 | # 60 | # Device : Spartan-6 61 | # Design Name : DDR/DDR2/DDR3/LPDDR 62 | # Purpose : Batch file to run PAR through ISE 63 | # Reference : 64 | # Revision History : 65 | # **************************************************************************** 66 | 67 | ./rem_files.sh 68 | 69 | 70 | 71 | 72 | xtclsh set_ise_prop.tcl 73 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/icon_coregen.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 11.1 4 | # Date: Wed Mar 11 07:09:11 2009 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = True 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = verilog 21 | SET device = xc6slx25 22 | SET devicefamily = spartan6 23 | SET flowvendor = Foundation_ISE 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = csg324 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -2 31 | SET verilogsim = False 32 | SET vhdlsim = False 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a 36 | # END Select 37 | # BEGIN Parameters 38 | CSET component_name=icon 39 | CSET enable_jtag_bufg=true 40 | CSET number_control_ports=2 41 | CSET use_ext_bscan=false 42 | CSET use_softbscan=false 43 | CSET use_unused_bscan=false 44 | CSET user_scan_chain=USER1 45 | # END Parameters 46 | GENERATE 47 | # CRC: 7da1f376 48 | 49 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ila_coregen.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 11.1 4 | # Date: Wed Mar 11 06:55:40 2009 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = verilog 21 | SET device = xc6slx25 22 | SET devicefamily = spartan6 23 | SET flowvendor = Foundation_ISE 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = csg324 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -2 31 | SET verilogsim = False 32 | SET vhdlsim = False 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a 36 | # END Select 37 | # BEGIN Parameters 38 | CSET component_name=ila 39 | CSET counter_width_1=Disabled 40 | CSET counter_width_10=Disabled 41 | CSET counter_width_11=Disabled 42 | CSET counter_width_12=Disabled 43 | CSET counter_width_13=Disabled 44 | CSET counter_width_14=Disabled 45 | CSET counter_width_15=Disabled 46 | CSET counter_width_16=Disabled 47 | CSET counter_width_2=Disabled 48 | CSET counter_width_3=Disabled 49 | CSET counter_width_4=Disabled 50 | CSET counter_width_5=Disabled 51 | CSET counter_width_6=Disabled 52 | CSET counter_width_7=Disabled 53 | CSET counter_width_8=Disabled 54 | CSET counter_width_9=Disabled 55 | CSET data_port_width=256 56 | CSET data_same_as_trigger=false 57 | CSET enable_storage_qualification=true 58 | CSET enable_trigger_output_port=false 59 | CSET exclude_from_data_storage_1=true 60 | CSET exclude_from_data_storage_10=true 61 | CSET exclude_from_data_storage_11=true 62 | CSET exclude_from_data_storage_12=true 63 | CSET exclude_from_data_storage_13=true 64 | CSET exclude_from_data_storage_14=true 65 | CSET exclude_from_data_storage_15=true 66 | CSET exclude_from_data_storage_16=true 67 | CSET exclude_from_data_storage_2=true 68 | CSET exclude_from_data_storage_3=true 69 | CSET exclude_from_data_storage_4=true 70 | CSET exclude_from_data_storage_5=true 71 | CSET exclude_from_data_storage_6=true 72 | CSET exclude_from_data_storage_7=true 73 | CSET exclude_from_data_storage_8=true 74 | CSET exclude_from_data_storage_9=true 75 | CSET match_type_1=basic_with_edges 76 | CSET match_type_10=basic 77 | CSET match_type_11=basic 78 | CSET match_type_12=basic 79 | CSET match_type_13=basic 80 | CSET match_type_14=basic 81 | CSET match_type_15=basic 82 | CSET match_type_16=basic 83 | CSET match_type_2=basic 84 | CSET match_type_3=basic 85 | CSET match_type_4=basic 86 | CSET match_type_5=basic 87 | CSET match_type_6=basic 88 | CSET match_type_7=basic 89 | CSET match_type_8=basic 90 | CSET match_type_9=basic 91 | CSET match_units_1=1 92 | CSET match_units_10=1 93 | CSET match_units_11=1 94 | CSET match_units_12=1 95 | CSET match_units_13=1 96 | CSET match_units_14=1 97 | CSET match_units_15=1 98 | CSET match_units_16=1 99 | CSET match_units_2=1 100 | CSET match_units_3=1 101 | CSET match_units_4=1 102 | CSET match_units_5=1 103 | CSET match_units_6=1 104 | CSET match_units_7=1 105 | CSET match_units_8=1 106 | CSET match_units_9=1 107 | CSET max_sequence_levels=1 108 | CSET number_of_trigger_ports=1 109 | CSET sample_data_depth=1024 110 | CSET sample_on=Rising 111 | CSET trigger_port_width_1=2 112 | CSET trigger_port_width_10=8 113 | CSET trigger_port_width_11=8 114 | CSET trigger_port_width_12=8 115 | CSET trigger_port_width_13=8 116 | CSET trigger_port_width_14=8 117 | CSET trigger_port_width_15=8 118 | CSET trigger_port_width_16=8 119 | CSET trigger_port_width_2=8 120 | CSET trigger_port_width_3=8 121 | CSET trigger_port_width_4=8 122 | CSET trigger_port_width_5=8 123 | CSET trigger_port_width_6=8 124 | CSET trigger_port_width_7=8 125 | CSET trigger_port_width_8=8 126 | CSET trigger_port_width_9=8 127 | CSET use_rpms=true 128 | # END Parameters 129 | GENERATE 130 | # CRC: eff89f81 131 | 132 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ise_flow.sh: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | #***************************************************************************** 3 | # (c) Copyright 2009 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | # **************************************************************************** 50 | # ____ ____ 51 | # / /\/ / 52 | # /___/ \ / Vendor : Xilinx 53 | # \ \ \/ Version : 3.92 54 | # \ \ Application : MIG 55 | # / / Filename : ise_flow.bat 56 | # /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $ 57 | # \ \ / \ Date Created : Fri Feb 06 2009 58 | # \___\/\___\ 59 | # 60 | # Device : Spartan-6 61 | # Design Name : DDR/DDR2/DDR3/LPDDR 62 | # Purpose : Batch file to run PAR through ISE batch mode 63 | # Reference : 64 | # Revision History : 65 | # **************************************************************************** 66 | 67 | ./rem_files.sh 68 | 69 | 70 | 71 | 72 | echo Synthesis Tool: XST 73 | 74 | mkdir "../synth/__projnav" > ise_flow_results.txt 75 | mkdir "../synth/xst" >> ise_flow_results.txt 76 | mkdir "../synth/xst/work" >> ise_flow_results.txt 77 | 78 | xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt 79 | ngdbuild -intstyle ise -dd ../synth/_ngo -uc mig.ucf -p xc6slx25csg324-2 mig.ngc mig.ngd >> ise_flow_results.txt 80 | 81 | map -intstyle ise -detail -w -pr off -c 100 -o mig_map.ncd mig.ngd mig.pcf >> ise_flow_results.txt 82 | par -w -intstyle ise -ol std mig_map.ncd mig.ncd mig.pcf >> ise_flow_results.txt 83 | trce -e 100 mig.ncd mig.pcf >> ise_flow_results.txt 84 | bitgen -intstyle ise -f mem_interface_top.ut mig.ncd >> ise_flow_results.txt 85 | 86 | echo done! 87 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ise_run.txt: -------------------------------------------------------------------------------- 1 | set -tmpdir ../synth/__projnav 2 | set -xsthdpdir ../synth/xst 3 | run 4 | #Source Parameters 5 | -ifn ../synth/mig.prj 6 | -ifmt mixed 7 | -iuc No 8 | #Target Parameters 9 | -ofn mig 10 | -ofmt NGC 11 | -p xc6slx25-2csg324 12 | -define AXI_ENABLE 13 | #Source Options 14 | -top mig 15 | -fsm_extract Yes 16 | -fsm_encoding one-hot 17 | -safe_implementation No 18 | -fsm_style lut 19 | -ram_extract Yes 20 | -ram_style Auto 21 | -rom_extract Yes 22 | -rom_style Auto 23 | -shreg_extract Yes 24 | -resource_sharing Yes 25 | -async_to_sync no 26 | -mult_style auto 27 | -register_balancing No 28 | #Target Options 29 | -iobuf Yes 30 | #Max fanout value shouldn't be set below 64 for MCB design 31 | -max_fanout 500 32 | -bufg 16 33 | -register_duplication yes 34 | -optimize_primitives No 35 | -use_clock_enable Auto 36 | -use_sync_set Auto 37 | -use_sync_reset Auto 38 | -iob auto 39 | -equivalent_register_removal yes 40 | #General Options 41 | -opt_mode Speed 42 | -opt_level 1 43 | -lso ../synth/mig.lso 44 | -keep_hierarchy NO 45 | -netlist_hierarchy as_optimized 46 | -rtlview Yes 47 | -glob_opt allclocknets 48 | -read_cores Yes 49 | -write_timing_constraints No 50 | -cross_clock_analysis No 51 | -hierarchy_separator / 52 | -bus_delimiter <> 53 | -case maintain 54 | -slice_utilization_ratio 100 55 | -bram_utilization_ratio 100 56 | -auto_bram_packing No 57 | -slice_utilization_ratio_maxmargin 5 58 | quit 59 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/makeproj.sh: -------------------------------------------------------------------------------- 1 | NEWPROJECT . 2 | SETPROJECT . 3 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/mem_interface_top.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g M2Pin:PullUp 6 | -g ProgPin:PullUp 7 | -g DonePin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullNone 13 | -g UserID:0xFFFFFFFF 14 | -g StartUpClk:CClk 15 | -g DONE_cycle:4 16 | -g GTS_cycle:5 17 | -g GWE_cycle:6 18 | -g LCK_cycle:NoWait 19 | -g Security:None 20 | -g DonePipe:No 21 | -g DriveDone:No 22 | -g ConfigRate:6 23 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/readme.txt: -------------------------------------------------------------------------------- 1 | ::**************************************************************************** 2 | :: (c) Copyright 2009 Xilinx, Inc. All rights reserved. 3 | :: 4 | :: This file contains confidential and proprietary information 5 | :: of Xilinx, Inc. and is protected under U.S. and 6 | :: international copyright and other intellectual property 7 | :: laws. 8 | :: 9 | :: DISCLAIMER 10 | :: This disclaimer is not a license and does not grant any 11 | :: rights to the materials distributed herewith. Except as 12 | :: otherwise provided in a valid license issued to you by 13 | :: Xilinx, and to the maximum extent permitted by applicable 14 | :: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | :: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | :: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | :: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | :: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | :: (2) Xilinx shall not be liable (whether in contract or tort, 20 | :: including negligence, or under any other theory of 21 | :: liability) for any loss or damage of any kind or nature 22 | :: related to, arising under or in connection with these 23 | :: materials, including for any direct, or any indirect, 24 | :: special, incidental, or consequential loss or damage 25 | :: (including loss of data, profits, goodwill, or any type of 26 | :: loss or damage suffered as a result of any action brought 27 | :: by a third party) even if such damage or loss was 28 | :: reasonably foreseeable or Xilinx had been advised of the 29 | :: possibility of the same. 30 | :: 31 | :: CRITICAL APPLICATIONS 32 | :: Xilinx products are not designed or intended to be fail- 33 | :: safe, or for use in any application requiring fail-safe 34 | :: performance, such as life-support or safety devices or 35 | :: systems, Class III medical devices, nuclear facilities, 36 | :: applications related to the deployment of airbags, or any 37 | :: other applications that could lead to death, personal 38 | :: injury, or severe property or environmental damage 39 | :: (individually and collectively, "Critical 40 | :: Applications"). Customer assumes the sole risk and 41 | :: liability of any use of Xilinx products in Critical 42 | :: Applications, subject only to applicable laws and 43 | :: regulations governing limitations on product liability. 44 | :: 45 | :: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | :: PART OF THIS FILE AT ALL TIMES. 47 | :: 48 | ::**************************************************************************** 49 | :: ____ ____ 50 | :: / /\/ / 51 | :: /___/ \ / Vendor : Xilinx 52 | :: \ \ \/ Version : 3.92 53 | :: \ \ Application : MIG 54 | :: / / Filename : readme.txt 55 | :: /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $ 56 | :: \ \ / \ Date Created : Fri Feb 06 2009 57 | :: \___\/\___\ 58 | :: 59 | :: Device : Spartan-6 60 | :: Design Name : DDR/DDR2/DDR3/LPDDR 61 | :: Purpose : Information about par folder 62 | :: Reference : 63 | :: Revision History : 64 | ::**************************************************************************** 65 | 66 | This folder has the batch files to synthesize using XST or Synplify Pro and 67 | implement the design either in "Command Line Mode" or in "GUI Mode". 68 | 69 | Steps to run the design using the ise_flow (batch mode): 70 | 71 | 1. Executing the "ise_flow.bat" file synthesizes the design using XST or 72 | Synplify Pro and does implement the design. 73 | a. First it removes the XST/Synplify Pro report files, implementation 74 | files, supporting scripts, the generated chipscope designs (if 75 | enabled) and the ISE project files (if exist any on previous runs) 76 | b. Synthesizes the design either with XST or Synplicity 77 | c. Implements the design with ISE. 78 | 79 | 2. After the design is run, it creates ise_flow_results.txt file that will have 80 | the ISE log information. 81 | 82 | Steps to run the design using the create_ise (GUI mode - for XST cases only): 83 | 84 | 1. This file will appear for XST cases only. 85 | 86 | 2. On executing the "create_ise.bat" file creates "test.xise" project file 87 | and set all the properties of the design selected. 88 | 89 | 3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file. 90 | 91 | 4. In Linux operating systems, test.xise project can be invoked by executing the command 92 | 'ise test.xise' from the terminal. 93 | 94 | Other files in PAR folder : 95 | 96 | * "mig.ucf" file is the constraint file for the design. 97 | It has clock constraints, location constraints and IO standards. 98 | 99 | * "mem_interface_top.ut" file has the options for the Configuration file 100 | generation i.e. the "mig.bit" file to run in batch mode. 101 | 102 | * "rem_files.bat" file has all the ISE/Synplify Pro generated report files, 103 | implementation files, supporting scripts, the generated chipscope designs 104 | (if enabled) and the ISE project files. 105 | 106 | * "set_ise_prop.tcl" file has all the properties that are to be 107 | set in GUI mode. 108 | 109 | * "ise_run.txt" file has synthesis options for the XST tool. 110 | This file is used for batch mode. 111 | 112 | * "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to 113 | generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the 114 | EDIF/NGC files, you must execute the following commands before starting 115 | synthesis and PAR. 116 | 117 | coregen -b ila_coregen.xco 118 | coregen -b icon_coregen.xco 119 | coregen -b vio_coregen.xco 120 | 121 | Note : When you generate the design using "Debug Signals for Memory Controller" 122 | option Enable, the above mentioned ChipScope coregen commands are printed 123 | into ise_flow.bat and create_ise.bat files. The mig rtl file 124 | will have the design debug signals portmapped to vio and icon 125 | ChipScope modules. 126 | 127 | * At the start of a Chip Scope Analyzer project, all of the signals in 128 | every core have generic names. "mig.cdc" is a file that contains 129 | all the signal names of all cores. Upon importing this file, signal names are 130 | renamed to the specified names in "mig.cdc" file. This file will work 131 | for the generated designs from MIG. If any of the design parameter values 132 | are changed after generating the design, this file will not work. 133 | For Multiple Controller designs, signal names provided in CDC file are of 134 | the controller that is enabled for Debug in the GUI. 135 | 136 | synth folder: 137 | 138 | 1. mem_interface_top_synp.sdc 139 | 2. script_synp.tcl 140 | 3. mig.prj 141 | 4. mig.lso 142 | 143 | mem_interface_top_synp.sdc and script_synp.tcl files are being used by 144 | Synplify Pro and mig.prj and mig.lso are being used by XST. 145 | 146 | 147 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/rem_files.sh: -------------------------------------------------------------------------------- 1 | ##!/bin/csh -f 2 | ##**************************************************************************** 3 | ## (c) Copyright 2009 Xilinx, Inc. All rights reserved. 4 | ## 5 | ## This file contains confidential and proprietary information 6 | ## of Xilinx, Inc. and is protected under U.S. and 7 | ## international copyright and other intellectual property 8 | ## laws. 9 | ## 10 | ## DISCLAIMER 11 | ## This disclaimer is not a license and does not grant any 12 | ## rights to the materials distributed herewith. Except as 13 | ## otherwise provided in a valid license issued to you by 14 | ## Xilinx, and to the maximum extent permitted by applicable 15 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | ## (2) Xilinx shall not be liable (whether in contract or tort, 21 | ## including negligence, or under any other theory of 22 | ## liability) for any loss or damage of any kind or nature 23 | ## related to, arising under or in connection with these 24 | ## materials, including for any direct, or any indirect, 25 | ## special, incidental, or consequential loss or damage 26 | ## (including loss of data, profits, goodwill, or any type of 27 | ## loss or damage suffered as a result of any action brought 28 | ## by a third party) even if such damage or loss was 29 | ## reasonably foreseeable or Xilinx had been advised of the 30 | ## possibility of the same. 31 | ## 32 | ## CRITICAL APPLICATIONS 33 | ## Xilinx products are not designed or intended to be fail- 34 | ## safe, or for use in any application requiring fail-safe 35 | ## performance, such as life-support or safety devices or 36 | ## systems, Class III medical devices, nuclear facilities, 37 | ## applications related to the deployment of airbags, or any 38 | ## other applications that could lead to death, personal 39 | ## injury, or severe property or environmental damage 40 | ## (individually and collectively, "Critical 41 | ## Applications"). Customer assumes the sole risk and 42 | ## liability of any use of Xilinx products in Critical 43 | ## Applications, subject only to applicable laws and 44 | ## regulations governing limitations on product liability. 45 | ## 46 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | ## PART OF THIS FILE AT ALL TIMES. 48 | ## 49 | ##**************************************************************************** 50 | ## ____ ____ 51 | ## / /\/ / 52 | ## /___/ \ / Vendor : Xilinx 53 | ## \ \ \/ Version : 3.92 54 | ## \ \ Application : MIG 55 | ## / / Filename : rem_files.bat 56 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $ 57 | ## \ \ / \ Date Created : Fri Feb 06 2009 58 | ## \___\/\___\ 59 | ## 60 | ## Device : Spartan-6 61 | ## Design Name : DDR/DDR2/DDR3/LPDDR 62 | ## Purpose : Batch file to remove files generated from ISE 63 | ## Reference : 64 | ## Revision History : 65 | ##**************************************************************************** 66 | 67 | rm -rf "../synth/__projnav" 68 | rm -rf "../synth/xst" 69 | rm -rf "../synth/_ngo" 70 | 71 | rm -rf tmp 72 | rm -rf _xmsgs 73 | rm -rf ila_xdb 74 | rm -rf icon_xdb 75 | rm -rf vio_xdb 76 | 77 | rm -rf xlnx_auto_0_xdb 78 | 79 | rm -rf vio_xmdf.tcl 80 | rm -rf vio_readme.txt 81 | rm -rf vio_flist.txt 82 | rm -rf vio.xise del 83 | rm -rf vio.xco del 84 | rm -rf vio.ngc del 85 | rm -rf vio.ise del 86 | rm -rf vio.gise del 87 | rm -rf vio.cdc del 88 | 89 | rm -rf coregen.cgp 90 | rm -rf coregen.cgc 91 | rm -rf coregen.log 92 | rm -rf ila.cdc 93 | rm -rf ila.gise 94 | rm -rf ila.ise 95 | rm -rf ila.ngc 96 | rm -rf ila.xco 97 | rm -rf ila.xise 98 | rm -rf ila_flist.txt 99 | rm -rf ila_readme.txt 100 | rm -rf ila_xmdf.tcl 101 | 102 | rm -rf icon.asy 103 | rm -rf icon.gise 104 | rm -rf icon.ise 105 | rm -rf icon.ncf 106 | rm -rf icon.ngc 107 | rm -rf icon.xco 108 | rm -rf icon.xise 109 | rm -rf icon_flist.txt 110 | rm -rf icon_readme.txt 111 | rm -rf icon_xmdf.tcl 112 | 113 | rm -rf ise_flow_results.txt 114 | rm -rf mig_vhdl.prj 115 | rm -rf mem_interface_top.syr 116 | rm -rf mig.ngc 117 | rm -rf mig.ngr 118 | rm -rf mig_xst.xrpt 119 | rm -rf mig.bld 120 | rm -rf mig.ngd 121 | rm -rf mig_ngdbuild.xrpt 122 | rm -rf mig_map.map 123 | rm -rf mig_map.mrp 124 | rm -rf mig_map.ngm 125 | rm -rf mig.pcf 126 | rm -rf mig_map.ncd 127 | rm -rf mig_map.xrpt 128 | rm -rf mig_summary.xml 129 | rm -rf mig_usage.xml 130 | rm -rf mig.ncd 131 | rm -rf mig.par 132 | rm -rf mig.xpi 133 | rm -rf mig.ptwx 134 | rm -rf mig.pad 135 | rm -rf mig.unroutes 136 | rm -rf mig_pad.csv 137 | rm -rf mig_pad.txt 138 | rm -rf mig_par.xrpt 139 | rm -rf mig.twx 140 | rm -rf mig.bgn 141 | rm -rf mig.twr 142 | rm -rf mig.drc 143 | rm -rf mig_bitgen.xwbt 144 | rm -rf mig.bit 145 | 146 | # Files and folders generated by create ise 147 | rm -rf test_xdb 148 | rm -rf _xmsgs 149 | rm -rf test.gise 150 | rm -rf test.xise 151 | rm -rf test.xise 152 | 153 | # Files and folders generated by ISE through GUI mode 154 | rm -rf _ngo 155 | rm -rf xst 156 | rm -rf mig.lso 157 | rm -rf mig.prj 158 | rm -rf mig.xst 159 | rm -rf mig.stx 160 | rm -rf mig_prev_built.ngd 161 | rm -rf test.ntrc_log 162 | rm -rf mig_guide.ncd 163 | rm -rf mig.cmd_log 164 | rm -rf mig_summary.html 165 | rm -rf mig.ut 166 | rm -rf par_usage_statistics.html 167 | rm -rf usage_statistics_webtalk.html 168 | rm -rf webtalk.log 169 | rm -rf device_usage_statistics.html 170 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/set_ise_prop.tcl: -------------------------------------------------------------------------------- 1 | project new test.xise 2 | 3 | project set "Device Family" "spartan6" 4 | 5 | project set "Device" "xc6slx25" 6 | 7 | project set "Package" "csg324" 8 | 9 | project set "Speed Grade" "-2" 10 | 11 | project set "Synthesis Tool" "XST (VHDL/Verilog)" 12 | 13 | project set "Simulator" "ISim (VHDL/Verilog)" 14 | 15 | xfile add "../rtl/infrastructure.v" 16 | xfile add "../rtl/memc_wrapper.v" 17 | xfile add "../rtl/mig.v" 18 | xfile add "../rtl/axi/a_upsizer.v" 19 | xfile add "../rtl/axi/axi_mcb.v" 20 | xfile add "../rtl/axi/axi_mcb_ar_channel.v" 21 | xfile add "../rtl/axi/axi_mcb_aw_channel.v" 22 | xfile add "../rtl/axi/axi_mcb_b_channel.v" 23 | xfile add "../rtl/axi/axi_mcb_cmd_arbiter.v" 24 | xfile add "../rtl/axi/axi_mcb_cmd_fsm.v" 25 | xfile add "../rtl/axi/axi_mcb_cmd_translator.v" 26 | xfile add "../rtl/axi/axi_mcb_incr_cmd.v" 27 | xfile add "../rtl/axi/axi_mcb_r_channel.v" 28 | xfile add "../rtl/axi/axi_mcb_simple_fifo.v" 29 | xfile add "../rtl/axi/axi_mcb_w_channel.v" 30 | xfile add "../rtl/axi/axi_mcb_wrap_cmd.v" 31 | xfile add "../rtl/axi/axi_register_slice.v" 32 | xfile add "../rtl/axi/axi_upsizer.v" 33 | xfile add "../rtl/axi/axic_register_slice.v" 34 | xfile add "../rtl/axi/carry.v" 35 | xfile add "../rtl/axi/carry_and.v" 36 | xfile add "../rtl/axi/carry_latch_and.v" 37 | xfile add "../rtl/axi/carry_latch_or.v" 38 | xfile add "../rtl/axi/carry_or.v" 39 | xfile add "../rtl/axi/command_fifo.v" 40 | xfile add "../rtl/axi/comparator.v" 41 | xfile add "../rtl/axi/comparator_mask.v" 42 | xfile add "../rtl/axi/comparator_mask_static.v" 43 | xfile add "../rtl/axi/comparator_sel.v" 44 | xfile add "../rtl/axi/comparator_sel_mask.v" 45 | xfile add "../rtl/axi/comparator_sel_mask_static.v" 46 | xfile add "../rtl/axi/comparator_sel_static.v" 47 | xfile add "../rtl/axi/comparator_static.v" 48 | xfile add "../rtl/axi/mcb_ui_top_synch.v" 49 | xfile add "../rtl/axi/mux_enc.v" 50 | xfile add "../rtl/axi/r_upsizer.v" 51 | xfile add "../rtl/axi/w_upsizer.v" 52 | xfile add "../rtl/mcb_controller/iodrp_controller.v" 53 | xfile add "../rtl/mcb_controller/iodrp_mcb_controller.v" 54 | xfile add "../rtl/mcb_controller/mcb_raw_wrapper.v" 55 | xfile add "../rtl/mcb_controller/mcb_soft_calibration.v" 56 | xfile add "../rtl/mcb_controller/mcb_soft_calibration_top.v" 57 | xfile add "../rtl/mcb_controller/mcb_ui_top.v" 58 | 59 | xfile add "mig.ucf" 60 | 61 | project set "Verilog Macros" "AXI_ENABLE" -process "Synthesize - XST" 62 | project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST" 63 | project set "Safe Implementation" "No" -process "Synthesize - XST" 64 | project set "FSM Style" "LUT" -process "Synthesize - XST" 65 | project set "RAM Extraction" "True" -process "Synthesize - XST" 66 | project set "RAM Style" "Auto" -process "Synthesize - XST" 67 | project set "ROM Extraction" "True" -process "Synthesize - XST" 68 | project set "ROM Style" "Auto" -process "Synthesize - XST" 69 | project set "Resource Sharing" "True" -process "Synthesize - XST" 70 | project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST" 71 | project set "Register Balancing" "No" -process "Synthesize - XST" 72 | project set "Add I/O Buffers" "True" -process "Synthesize - XST" 73 | project set "Max Fanout" "500" -process "Synthesize - XST" 74 | project set "Number of Clock Buffers" "8" -process "Synthesize - XST" 75 | project set "Register Duplication" "True" -process "Synthesize - XST" 76 | project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST" 77 | project set "Use Clock Enable" "Yes" -process "Synthesize - XST" 78 | project set "Use Synchronous Set" "Yes" -process "Synthesize - XST" 79 | project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST" 80 | project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST" 81 | project set "Equivalent Register Removal" "True" -process "Synthesize - XST" 82 | project set "Optimization Goal" "Speed" -process "Synthesize - XST" 83 | project set "Optimization Effort" "Normal" -process "Synthesize - XST" 84 | project set "Library Search Order" "../synth/mig.lso" -process "Synthesize - XST" 85 | project set "Keep Hierarchy" "Soft" -process "Synthesize - XST" 86 | project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST" 87 | project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST" 88 | project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST" 89 | project set "Read Cores" "True" -process "Synthesize - XST" 90 | project set "Write Timing Constraints" "False" -process "Synthesize - XST" 91 | project set "Cross Clock Analysis" "False" -process "Synthesize - XST" 92 | project set "Hierarchy Separator" "/" -process "Synthesize - XST" 93 | project set "Bus Delimiter" "<>" -process "Synthesize - XST" 94 | project set "Case" "Maintain" -process "Synthesize - XST" 95 | project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST" 96 | project set "Automatic BRAM Packing" "False" -process "Synthesize - XST" 97 | project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map 98 | 99 | project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route" 100 | 101 | project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing" 102 | 103 | project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File" 104 | project set "Create Binary Configuration File" "False" -process "Generate Programming File" 105 | project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File" 106 | project set "Configuration Rate" "6" -process "Generate Programming File" 107 | project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File" 108 | project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File" 109 | project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File" 110 | project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File" 111 | project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File" 112 | project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File" 113 | project set "Unused IOB Pins" "Float" -process "Generate Programming File" 114 | project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File" 115 | project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File" 116 | project set "Done (Output Events)" "Default (4)" -process "Generate Programming File" 117 | project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File" 118 | project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File" 119 | project set "Enable Internal Done Pipe" "False" -process "Generate Programming File" 120 | project set "Drive Done Pin High" "False" -process "Generate Programming File" 121 | project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File" 122 | 123 | project close 124 | 125 | 126 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/vio_coregen.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 11.2 4 | # Date: Fri Jun 12 05:42:56 2009 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = verilog 21 | SET device = xc6slx25 22 | SET devicefamily = spartan6 23 | SET flowvendor = Foundation_ISE 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = csg324 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -2 31 | SET verilogsim = False 32 | SET vhdlsim = False 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a 36 | # END Select 37 | # BEGIN Parameters 38 | CSET asynchronous_input_port_width=8 39 | CSET asynchronous_output_port_width=7 40 | CSET component_name=vio 41 | CSET enable_asynchronous_input_port=false 42 | CSET enable_asynchronous_output_port=true 43 | CSET enable_synchronous_input_port=false 44 | CSET enable_synchronous_output_port=false 45 | CSET invert_clock_input=false 46 | CSET synchronous_input_port_width=8 47 | CSET synchronous_output_port_width=8 48 | # END Parameters 49 | GENERATE 50 | # CRC: 66fe39ed 51 | 52 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/a_upsizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/83eae101e173ddcd444730682db83635ae0decc9/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/a_upsizer.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_simple_fifo.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. 3 | //-- 4 | //-- This file contains confidential and proprietary information 5 | //-- of Xilinx, Inc. and is protected under U.S. and 6 | //-- international copyright and other intellectual property 7 | //-- laws. 8 | //-- 9 | //-- DISCLAIMER 10 | //-- This disclaimer is not a license and does not grant any 11 | //-- rights to the materials distributed herewith. Except as 12 | //-- otherwise provided in a valid license issued to you by 13 | //-- Xilinx, and to the maximum extent permitted by applicable 14 | //-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | //-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | //-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | //-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | //-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | //-- (2) Xilinx shall not be liable (whether in contract or tort, 20 | //-- including negligence, or under any other theory of 21 | //-- liability) for any loss or damage of any kind or nature 22 | //-- related to, arising under or in connection with these 23 | //-- materials, including for any direct, or any indirect, 24 | //-- special, incidental, or consequential loss or damage 25 | //-- (including loss of data, profits, goodwill, or any type of 26 | //-- loss or damage suffered as a result of any action brought 27 | //-- by a third party) even if such damage or loss was 28 | //-- reasonably foreseeable or Xilinx had been advised of the 29 | //-- possibility of the same. 30 | //-- 31 | //-- CRITICAL APPLICATIONS 32 | //-- Xilinx products are not designed or intended to be fail- 33 | //-- safe, or for use in any application requiring fail-safe 34 | //-- performance, such as life-support or safety devices or 35 | //-- systems, Class III medical devices, nuclear facilities, 36 | //-- applications related to the deployment of airbags, or any 37 | //-- other applications that could lead to death, personal 38 | //-- injury, or severe property or environmental damage 39 | //-- (individually and collectively, "Critical 40 | //-- Applications"). Customer assumes the sole risk and 41 | //-- liability of any use of Xilinx products in Critical 42 | //-- Applications, subject only to applicable laws and 43 | //-- regulations governing limitations on product liability. 44 | //-- 45 | //-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | //-- PART OF THIS FILE AT ALL TIMES. 47 | //----------------------------------------------------------------------------- 48 | //Purpose: 49 | // Synchronous, shallow FIFO that uses simple as a DP Memory. 50 | // This requires about 1/2 the resources as a Distributed RAM DPRAM 51 | // implementation. 52 | // 53 | // This FIFO will have the current data on the output when data is contained 54 | // in the FIFO. When the FIFO is empty, the output data is invalid. 55 | // 56 | //Reference: 57 | //Revision History: 58 | // 59 | //----------------------------------------------- 60 | // 61 | // MODULE: axi_mcb_simple_fifo 62 | // 63 | // This is the simplest form of inferring the 64 | // simple/SRL(16/32)CE in a Xilinx FPGA. 65 | // 66 | //----------------------------------------------- 67 | `timescale 1ps / 1ps 68 | `default_nettype none 69 | 70 | module axi_mcb_simple_fifo # 71 | ( 72 | parameter C_WIDTH = 8, 73 | parameter C_AWIDTH = 4, 74 | parameter C_DEPTH = 16 75 | ) 76 | ( 77 | input wire clk, // Main System Clock (Sync FIFO) 78 | input wire rst, // FIFO Counter Reset (Clk 79 | input wire wr_en, // FIFO Write Enable (Clk) 80 | input wire rd_en, // FIFO Read Enable (Clk) 81 | input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk) 82 | output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk) 83 | output wire a_full, 84 | output wire full, // FIFO FULL Status (Clk) 85 | output wire a_empty, 86 | output wire empty // FIFO EMPTY Status (Clk) 87 | ); 88 | 89 | /////////////////////////////////////// 90 | // FIFO Local Parameters 91 | /////////////////////////////////////// 92 | localparam [C_AWIDTH-1:0] C_EMPTY = ~(0); 93 | localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0); 94 | localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY - 1'b1; 95 | localparam [C_AWIDTH-1:0] C_FULL_PRE = C_FULL - 1'b1; 96 | 97 | /////////////////////////////////////// 98 | // FIFO Internal Signals 99 | /////////////////////////////////////// 100 | reg [C_WIDTH-1:0] memory [C_DEPTH-1:0]; 101 | reg [C_AWIDTH-1:0] cnt_read; 102 | reg full_r; 103 | reg empty_r; 104 | 105 | /////////////////////////////////////// 106 | // Main simple FIFO Array 107 | /////////////////////////////////////// 108 | always @(posedge clk) begin : BLKSRL 109 | integer i; 110 | if (wr_en) begin 111 | for (i = 0; i < C_DEPTH-1; i = i + 1) begin 112 | memory[i+1] <= memory[i]; 113 | end 114 | memory[0] <= din; 115 | end 116 | end 117 | 118 | /////////////////////////////////////// 119 | // Read Index Counter 120 | // Up/Down Counter 121 | // *** Notice that there is no *** 122 | // *** OVERRUN protection. *** 123 | /////////////////////////////////////// 124 | always @(posedge clk) begin 125 | if (rst) cnt_read <= C_EMPTY; 126 | else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1; 127 | else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1; 128 | end 129 | 130 | /////////////////////////////////////// 131 | // Status Flags / Outputs 132 | /////////////////////////////////////// 133 | always @(posedge clk) begin 134 | if (rst) begin 135 | full_r <= 1'b0; 136 | end 137 | else if ( wr_en & ~rd_en) begin 138 | full_r <= a_full; 139 | end 140 | else if ( ~wr_en & rd_en ) begin 141 | full_r <= 1'b0; 142 | end 143 | end 144 | 145 | always @(posedge clk) begin 146 | if (rst) begin 147 | empty_r <= 1'b1; 148 | end 149 | else if (~wr_en & rd_en) begin 150 | empty_r <= a_empty; 151 | end 152 | else if (wr_en & ~rd_en) begin 153 | empty_r <= 1'b0; 154 | end 155 | end 156 | 157 | 158 | assign full = full_r; 159 | assign empty = empty_r; 160 | assign a_full = (cnt_read == C_FULL); 161 | assign a_empty = (cnt_read == C_EMPTY_PRE); 162 | 163 | assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read]; 164 | 165 | endmodule // axi_mcb_simple_fifo 166 | 167 | `default_nettype wire 168 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_upsizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/83eae101e173ddcd444730682db83635ae0decc9/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_upsizer.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | 61 | module carry # 62 | ( 63 | parameter C_FAMILY = "virtex6" 64 | // FPGA Family. Current version: virtex6 or spartan6. 65 | ) 66 | ( 67 | input wire CIN, 68 | input wire S, 69 | input wire DI, 70 | output wire COUT 71 | ); 72 | 73 | 74 | ///////////////////////////////////////////////////////////////////////////// 75 | // Variables for generating parameter controlled instances. 76 | ///////////////////////////////////////////////////////////////////////////// 77 | 78 | 79 | ///////////////////////////////////////////////////////////////////////////// 80 | // Local params 81 | ///////////////////////////////////////////////////////////////////////////// 82 | 83 | 84 | ///////////////////////////////////////////////////////////////////////////// 85 | // Functions 86 | ///////////////////////////////////////////////////////////////////////////// 87 | 88 | 89 | ///////////////////////////////////////////////////////////////////////////// 90 | // Internal signals 91 | ///////////////////////////////////////////////////////////////////////////// 92 | 93 | 94 | ///////////////////////////////////////////////////////////////////////////// 95 | // Instantiate or use RTL code 96 | ///////////////////////////////////////////////////////////////////////////// 97 | 98 | generate 99 | if ( C_FAMILY == "rtl" ) begin : USE_RTL 100 | assign COUT = (CIN & S) | (DI & ~S); 101 | 102 | end else begin : USE_FPGA 103 | 104 | MUXCY and_inst 105 | ( 106 | .O (COUT), 107 | .CI (CIN), 108 | .DI (DI), 109 | .S (S) 110 | ); 111 | 112 | end 113 | endgenerate 114 | 115 | 116 | endmodule 117 | 118 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_and.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized AND with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | 61 | module carry_and # 62 | ( 63 | parameter C_FAMILY = "virtex6" 64 | // FPGA Family. Current version: virtex6 or spartan6. 65 | ) 66 | ( 67 | input wire CIN, 68 | input wire S, 69 | output wire COUT 70 | ); 71 | 72 | 73 | ///////////////////////////////////////////////////////////////////////////// 74 | // Variables for generating parameter controlled instances. 75 | ///////////////////////////////////////////////////////////////////////////// 76 | 77 | 78 | ///////////////////////////////////////////////////////////////////////////// 79 | // Local params 80 | ///////////////////////////////////////////////////////////////////////////// 81 | 82 | 83 | ///////////////////////////////////////////////////////////////////////////// 84 | // Functions 85 | ///////////////////////////////////////////////////////////////////////////// 86 | 87 | 88 | ///////////////////////////////////////////////////////////////////////////// 89 | // Internal signals 90 | ///////////////////////////////////////////////////////////////////////////// 91 | 92 | 93 | ///////////////////////////////////////////////////////////////////////////// 94 | // Instantiate or use RTL code 95 | ///////////////////////////////////////////////////////////////////////////// 96 | 97 | generate 98 | if ( C_FAMILY == "rtl" ) begin : USE_RTL 99 | assign COUT = CIN & S; 100 | 101 | end else begin : USE_FPGA 102 | MUXCY and_inst 103 | ( 104 | .O (COUT), 105 | .CI (CIN), 106 | .DI (1'b0), 107 | .S (S) 108 | ); 109 | 110 | end 111 | endgenerate 112 | 113 | 114 | endmodule 115 | 116 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_latch_and.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized AND with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | 61 | module carry_latch_and # 62 | ( 63 | parameter C_FAMILY = "virtex6" 64 | // FPGA Family. Current version: virtex6 or spartan6. 65 | ) 66 | ( 67 | input wire CIN, 68 | input wire I, 69 | output wire O 70 | ); 71 | 72 | 73 | ///////////////////////////////////////////////////////////////////////////// 74 | // Variables for generating parameter controlled instances. 75 | ///////////////////////////////////////////////////////////////////////////// 76 | 77 | 78 | ///////////////////////////////////////////////////////////////////////////// 79 | // Local params 80 | ///////////////////////////////////////////////////////////////////////////// 81 | 82 | 83 | ///////////////////////////////////////////////////////////////////////////// 84 | // Functions 85 | ///////////////////////////////////////////////////////////////////////////// 86 | 87 | 88 | ///////////////////////////////////////////////////////////////////////////// 89 | // Internal signals 90 | ///////////////////////////////////////////////////////////////////////////// 91 | 92 | 93 | ///////////////////////////////////////////////////////////////////////////// 94 | // Instantiate or use RTL code 95 | ///////////////////////////////////////////////////////////////////////////// 96 | 97 | generate 98 | if ( C_FAMILY == "rtl" ) begin : USE_RTL 99 | assign O = CIN & ~I; 100 | 101 | end else begin : USE_FPGA 102 | wire I_n; 103 | 104 | assign I_n = ~I; 105 | 106 | AND2B1L and2b1l_inst 107 | ( 108 | .O(O), 109 | .DI(CIN), 110 | .SRI(I_n) 111 | ); 112 | 113 | end 114 | endgenerate 115 | 116 | 117 | endmodule 118 | 119 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_latch_or.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized OR with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | 61 | module carry_latch_or # 62 | ( 63 | parameter C_FAMILY = "virtex6" 64 | // FPGA Family. Current version: virtex6 or spartan6. 65 | ) 66 | ( 67 | input wire CIN, 68 | input wire I, 69 | output wire O 70 | ); 71 | 72 | 73 | ///////////////////////////////////////////////////////////////////////////// 74 | // Variables for generating parameter controlled instances. 75 | ///////////////////////////////////////////////////////////////////////////// 76 | 77 | 78 | ///////////////////////////////////////////////////////////////////////////// 79 | // Local params 80 | ///////////////////////////////////////////////////////////////////////////// 81 | 82 | 83 | ///////////////////////////////////////////////////////////////////////////// 84 | // Functions 85 | ///////////////////////////////////////////////////////////////////////////// 86 | 87 | 88 | ///////////////////////////////////////////////////////////////////////////// 89 | // Internal signals 90 | ///////////////////////////////////////////////////////////////////////////// 91 | 92 | 93 | ///////////////////////////////////////////////////////////////////////////// 94 | // Instantiate or use RTL code 95 | ///////////////////////////////////////////////////////////////////////////// 96 | 97 | generate 98 | if ( C_FAMILY == "rtl" ) begin : USE_RTL 99 | assign O = CIN | I; 100 | 101 | end else begin : USE_FPGA 102 | OR2L or2l_inst1 103 | ( 104 | .O(O), 105 | .DI(CIN), 106 | .SRI(I) 107 | ); 108 | 109 | end 110 | endgenerate 111 | 112 | 113 | endmodule 114 | 115 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_or.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized OR with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | 61 | module carry_or # 62 | ( 63 | parameter C_FAMILY = "virtex6" 64 | // FPGA Family. Current version: virtex6 or spartan6. 65 | ) 66 | ( 67 | input wire CIN, 68 | input wire S, 69 | output wire COUT 70 | ); 71 | 72 | 73 | ///////////////////////////////////////////////////////////////////////////// 74 | // Variables for generating parameter controlled instances. 75 | ///////////////////////////////////////////////////////////////////////////// 76 | 77 | 78 | ///////////////////////////////////////////////////////////////////////////// 79 | // Local params 80 | ///////////////////////////////////////////////////////////////////////////// 81 | 82 | 83 | ///////////////////////////////////////////////////////////////////////////// 84 | // Functions 85 | ///////////////////////////////////////////////////////////////////////////// 86 | 87 | 88 | ///////////////////////////////////////////////////////////////////////////// 89 | // Internal signals 90 | ///////////////////////////////////////////////////////////////////////////// 91 | 92 | 93 | ///////////////////////////////////////////////////////////////////////////// 94 | // Instantiate or use RTL code 95 | ///////////////////////////////////////////////////////////////////////////// 96 | 97 | generate 98 | if ( C_FAMILY == "rtl" ) begin : USE_RTL 99 | assign COUT = CIN | S; 100 | 101 | end else begin : USE_FPGA 102 | wire S_n; 103 | 104 | assign S_n = ~S; 105 | 106 | MUXCY and_inst 107 | ( 108 | .O (COUT), 109 | .CI (CIN), 110 | .DI (1'b1), 111 | .S (S_n) 112 | ); 113 | 114 | end 115 | endgenerate 116 | 117 | 118 | endmodule 119 | 120 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter integer C_DATA_WIDTH = 4 65 | // Data width for comparator. 66 | ) 67 | ( 68 | input wire CIN, 69 | input wire [C_DATA_WIDTH-1:0] A, 70 | input wire [C_DATA_WIDTH-1:0] B, 71 | output wire COUT 72 | ); 73 | 74 | 75 | ///////////////////////////////////////////////////////////////////////////// 76 | // Variables for generating parameter controlled instances. 77 | ///////////////////////////////////////////////////////////////////////////// 78 | 79 | // Generate variable for bit vector. 80 | genvar bit_cnt; 81 | 82 | 83 | ///////////////////////////////////////////////////////////////////////////// 84 | // Local params 85 | ///////////////////////////////////////////////////////////////////////////// 86 | 87 | // Bits per LUT for this architecture. 88 | localparam integer C_BITS_PER_LUT = 3; 89 | 90 | // Constants for packing levels. 91 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 92 | 93 | // 94 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 95 | C_DATA_WIDTH; 96 | 97 | 98 | ///////////////////////////////////////////////////////////////////////////// 99 | // Functions 100 | ///////////////////////////////////////////////////////////////////////////// 101 | 102 | 103 | ///////////////////////////////////////////////////////////////////////////// 104 | // Internal signals 105 | ///////////////////////////////////////////////////////////////////////////// 106 | 107 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 108 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 109 | wire [C_NUM_LUT-1:0] sel; 110 | wire [C_NUM_LUT:0] carry_local; 111 | 112 | 113 | ///////////////////////////////////////////////////////////////////////////// 114 | // 115 | ///////////////////////////////////////////////////////////////////////////// 116 | 117 | generate 118 | // Assign input to local vectors. 119 | assign carry_local[0] = CIN; 120 | 121 | // Extend input data to fit. 122 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 123 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 124 | assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 125 | end else begin : NO_EXTENDED_DATA 126 | assign a_local = A; 127 | assign b_local = B; 128 | end 129 | 130 | // Instantiate one carry and per level. 131 | for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL 132 | // Create the local select signal 133 | assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 134 | b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ); 135 | 136 | // Instantiate each LUT level. 137 | carry_and # 138 | ( 139 | .C_FAMILY(C_FAMILY) 140 | ) compare_inst 141 | ( 142 | .COUT (carry_local[bit_cnt+1]), 143 | .CIN (carry_local[bit_cnt]), 144 | .S (sel[bit_cnt]) 145 | ); 146 | 147 | end // end for bit_cnt 148 | 149 | // Assign output from local vector. 150 | assign COUT = carry_local[C_NUM_LUT]; 151 | 152 | endgenerate 153 | 154 | 155 | endmodule 156 | 157 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_mask.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator_mask # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter integer C_DATA_WIDTH = 4 65 | // Data width for comparator. 66 | ) 67 | ( 68 | input wire CIN, 69 | input wire [C_DATA_WIDTH-1:0] A, 70 | input wire [C_DATA_WIDTH-1:0] B, 71 | input wire [C_DATA_WIDTH-1:0] M, 72 | output wire COUT 73 | ); 74 | 75 | 76 | ///////////////////////////////////////////////////////////////////////////// 77 | // Variables for generating parameter controlled instances. 78 | ///////////////////////////////////////////////////////////////////////////// 79 | 80 | // Generate variable for bit vector. 81 | genvar lut_cnt; 82 | 83 | 84 | ///////////////////////////////////////////////////////////////////////////// 85 | // Local params 86 | ///////////////////////////////////////////////////////////////////////////// 87 | 88 | // Bits per LUT for this architecture. 89 | localparam integer C_BITS_PER_LUT = 2; 90 | 91 | // Constants for packing levels. 92 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 93 | 94 | // 95 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 96 | C_DATA_WIDTH; 97 | 98 | 99 | ///////////////////////////////////////////////////////////////////////////// 100 | // Functions 101 | ///////////////////////////////////////////////////////////////////////////// 102 | 103 | 104 | ///////////////////////////////////////////////////////////////////////////// 105 | // Internal signals 106 | ///////////////////////////////////////////////////////////////////////////// 107 | 108 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 109 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 110 | wire [C_FIX_DATA_WIDTH-1:0] m_local; 111 | wire [C_NUM_LUT-1:0] sel; 112 | wire [C_NUM_LUT:0] carry_local; 113 | 114 | 115 | ///////////////////////////////////////////////////////////////////////////// 116 | // 117 | ///////////////////////////////////////////////////////////////////////////// 118 | 119 | generate 120 | // Assign input to local vectors. 121 | assign carry_local[0] = CIN; 122 | 123 | // Extend input data to fit. 124 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 125 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 126 | assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 127 | assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 128 | end else begin : NO_EXTENDED_DATA 129 | assign a_local = A; 130 | assign b_local = B; 131 | assign m_local = M; 132 | end 133 | 134 | // Instantiate one carry and per level. 135 | for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL 136 | // Create the local select signal 137 | assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 138 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 139 | ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 140 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ); 141 | 142 | // Instantiate each LUT level. 143 | carry_and # 144 | ( 145 | .C_FAMILY(C_FAMILY) 146 | ) compare_inst 147 | ( 148 | .COUT (carry_local[lut_cnt+1]), 149 | .CIN (carry_local[lut_cnt]), 150 | .S (sel[lut_cnt]) 151 | ); 152 | 153 | end // end for lut_cnt 154 | 155 | // Assign output from local vector. 156 | assign COUT = carry_local[C_NUM_LUT]; 157 | 158 | endgenerate 159 | 160 | 161 | endmodule 162 | 163 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_mask_static.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR (against constant) with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator_mask_static # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter C_VALUE = 4'b0, 65 | // Static value to compare against. 66 | parameter integer C_DATA_WIDTH = 4 67 | // Data width for comparator. 68 | ) 69 | ( 70 | input wire CIN, 71 | input wire [C_DATA_WIDTH-1:0] A, 72 | input wire [C_DATA_WIDTH-1:0] M, 73 | output wire COUT 74 | ); 75 | 76 | 77 | ///////////////////////////////////////////////////////////////////////////// 78 | // Variables for generating parameter controlled instances. 79 | ///////////////////////////////////////////////////////////////////////////// 80 | 81 | // Generate variable for bit vector. 82 | genvar lut_cnt; 83 | 84 | 85 | ///////////////////////////////////////////////////////////////////////////// 86 | // Local params 87 | ///////////////////////////////////////////////////////////////////////////// 88 | 89 | // Bits per LUT for this architecture. 90 | localparam integer C_BITS_PER_LUT = 3; 91 | 92 | // Constants for packing levels. 93 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 94 | 95 | // 96 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 97 | C_DATA_WIDTH; 98 | 99 | 100 | ///////////////////////////////////////////////////////////////////////////// 101 | // Functions 102 | ///////////////////////////////////////////////////////////////////////////// 103 | 104 | 105 | ///////////////////////////////////////////////////////////////////////////// 106 | // Internal signals 107 | ///////////////////////////////////////////////////////////////////////////// 108 | 109 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 110 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 111 | wire [C_FIX_DATA_WIDTH-1:0] m_local; 112 | wire [C_NUM_LUT-1:0] sel; 113 | wire [C_NUM_LUT:0] carry_local; 114 | 115 | 116 | ///////////////////////////////////////////////////////////////////////////// 117 | // 118 | ///////////////////////////////////////////////////////////////////////////// 119 | 120 | generate 121 | // Assign input to local vectors. 122 | assign carry_local[0] = CIN; 123 | 124 | // Extend input data to fit. 125 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 126 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 127 | assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 128 | assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 129 | end else begin : NO_EXTENDED_DATA 130 | assign a_local = A; 131 | assign b_local = C_VALUE; 132 | assign m_local = M; 133 | end 134 | 135 | // Instantiate one carry and per level. 136 | for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL 137 | // Create the local select signal 138 | assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 139 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 140 | ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 141 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ); 142 | 143 | // Instantiate each LUT level. 144 | carry_and # 145 | ( 146 | .C_FAMILY(C_FAMILY) 147 | ) compare_inst 148 | ( 149 | .COUT (carry_local[lut_cnt+1]), 150 | .CIN (carry_local[lut_cnt]), 151 | .S (sel[lut_cnt]) 152 | ); 153 | 154 | end // end for lut_cnt 155 | 156 | // Assign output from local vector. 157 | assign COUT = carry_local[C_NUM_LUT]; 158 | 159 | endgenerate 160 | 161 | 162 | endmodule 163 | 164 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator_sel # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter integer C_DATA_WIDTH = 4 65 | // Data width for comparator. 66 | ) 67 | ( 68 | input wire CIN, 69 | input wire S, 70 | input wire [C_DATA_WIDTH-1:0] A, 71 | input wire [C_DATA_WIDTH-1:0] B, 72 | input wire [C_DATA_WIDTH-1:0] V, 73 | output wire COUT 74 | ); 75 | 76 | 77 | ///////////////////////////////////////////////////////////////////////////// 78 | // Variables for generating parameter controlled instances. 79 | ///////////////////////////////////////////////////////////////////////////// 80 | 81 | // Generate variable for bit vector. 82 | genvar bit_cnt; 83 | 84 | 85 | ///////////////////////////////////////////////////////////////////////////// 86 | // Local params 87 | ///////////////////////////////////////////////////////////////////////////// 88 | 89 | // Bits per LUT for this architecture. 90 | localparam integer C_BITS_PER_LUT = 1; 91 | 92 | // Constants for packing levels. 93 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 94 | 95 | // 96 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 97 | C_DATA_WIDTH; 98 | 99 | 100 | ///////////////////////////////////////////////////////////////////////////// 101 | // Functions 102 | ///////////////////////////////////////////////////////////////////////////// 103 | 104 | 105 | ///////////////////////////////////////////////////////////////////////////// 106 | // Internal signals 107 | ///////////////////////////////////////////////////////////////////////////// 108 | 109 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 110 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 111 | wire [C_FIX_DATA_WIDTH-1:0] v_local; 112 | wire [C_NUM_LUT-1:0] sel; 113 | wire [C_NUM_LUT:0] carry_local; 114 | 115 | 116 | ///////////////////////////////////////////////////////////////////////////// 117 | // 118 | ///////////////////////////////////////////////////////////////////////////// 119 | 120 | generate 121 | // Assign input to local vectors. 122 | assign carry_local[0] = CIN; 123 | 124 | // Extend input data to fit. 125 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 126 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 127 | assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 128 | assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 129 | end else begin : NO_EXTENDED_DATA 130 | assign a_local = A; 131 | assign b_local = B; 132 | assign v_local = V; 133 | end 134 | 135 | // Instantiate one carry and per level. 136 | for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL 137 | // Create the local select signal 138 | assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 139 | v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | 140 | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 141 | v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); 142 | 143 | // Instantiate each LUT level. 144 | carry_and # 145 | ( 146 | .C_FAMILY(C_FAMILY) 147 | ) compare_inst 148 | ( 149 | .COUT (carry_local[bit_cnt+1]), 150 | .CIN (carry_local[bit_cnt]), 151 | .S (sel[bit_cnt]) 152 | ); 153 | 154 | end // end for bit_cnt 155 | 156 | // Assign output from local vector. 157 | assign COUT = carry_local[C_NUM_LUT]; 158 | 159 | endgenerate 160 | 161 | 162 | endmodule 163 | 164 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_mask.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator_sel_mask # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter integer C_DATA_WIDTH = 4 65 | // Data width for comparator. 66 | ) 67 | ( 68 | input wire CIN, 69 | input wire S, 70 | input wire [C_DATA_WIDTH-1:0] A, 71 | input wire [C_DATA_WIDTH-1:0] B, 72 | input wire [C_DATA_WIDTH-1:0] M, 73 | input wire [C_DATA_WIDTH-1:0] V, 74 | output wire COUT 75 | ); 76 | 77 | 78 | ///////////////////////////////////////////////////////////////////////////// 79 | // Variables for generating parameter controlled instances. 80 | ///////////////////////////////////////////////////////////////////////////// 81 | 82 | // Generate variable for bit vector. 83 | genvar lut_cnt; 84 | 85 | 86 | ///////////////////////////////////////////////////////////////////////////// 87 | // Local params 88 | ///////////////////////////////////////////////////////////////////////////// 89 | 90 | // Bits per LUT for this architecture. 91 | localparam integer C_BITS_PER_LUT = 1; 92 | 93 | // Constants for packing levels. 94 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 95 | 96 | // 97 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 98 | C_DATA_WIDTH; 99 | 100 | 101 | ///////////////////////////////////////////////////////////////////////////// 102 | // Functions 103 | ///////////////////////////////////////////////////////////////////////////// 104 | 105 | 106 | ///////////////////////////////////////////////////////////////////////////// 107 | // Internal signals 108 | ///////////////////////////////////////////////////////////////////////////// 109 | 110 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 111 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 112 | wire [C_FIX_DATA_WIDTH-1:0] m_local; 113 | wire [C_FIX_DATA_WIDTH-1:0] v_local; 114 | wire [C_NUM_LUT-1:0] sel; 115 | wire [C_NUM_LUT:0] carry_local; 116 | 117 | 118 | ///////////////////////////////////////////////////////////////////////////// 119 | // 120 | ///////////////////////////////////////////////////////////////////////////// 121 | 122 | generate 123 | // Assign input to local vectors. 124 | assign carry_local[0] = CIN; 125 | 126 | // Extend input data to fit. 127 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 128 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 129 | assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 130 | assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 131 | assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 132 | end else begin : NO_EXTENDED_DATA 133 | assign a_local = A; 134 | assign b_local = B; 135 | assign m_local = M; 136 | assign v_local = V; 137 | end 138 | 139 | // Instantiate one carry and per level. 140 | for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL 141 | // Create the local select signal 142 | assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 143 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 144 | ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 145 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) | 146 | ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 147 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 148 | ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 149 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) ); 150 | 151 | // Instantiate each LUT level. 152 | carry_and # 153 | ( 154 | .C_FAMILY(C_FAMILY) 155 | ) compare_inst 156 | ( 157 | .COUT (carry_local[lut_cnt+1]), 158 | .CIN (carry_local[lut_cnt]), 159 | .S (sel[lut_cnt]) 160 | ); 161 | 162 | end // end for lut_cnt 163 | 164 | // Assign output from local vector. 165 | assign COUT = carry_local[C_NUM_LUT]; 166 | 167 | endgenerate 168 | 169 | 170 | endmodule 171 | 172 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_mask_static.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR (against constant) with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator_sel_mask_static # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter C_VALUE = 4'b0, 65 | // Static value to compare against. 66 | parameter integer C_DATA_WIDTH = 4 67 | // Data width for comparator. 68 | ) 69 | ( 70 | input wire CIN, 71 | input wire S, 72 | input wire [C_DATA_WIDTH-1:0] A, 73 | input wire [C_DATA_WIDTH-1:0] B, 74 | input wire [C_DATA_WIDTH-1:0] M, 75 | output wire COUT 76 | ); 77 | 78 | 79 | ///////////////////////////////////////////////////////////////////////////// 80 | // Variables for generating parameter controlled instances. 81 | ///////////////////////////////////////////////////////////////////////////// 82 | 83 | // Generate variable for bit vector. 84 | genvar lut_cnt; 85 | 86 | 87 | ///////////////////////////////////////////////////////////////////////////// 88 | // Local params 89 | ///////////////////////////////////////////////////////////////////////////// 90 | 91 | // Bits per LUT for this architecture. 92 | localparam integer C_BITS_PER_LUT = 1; 93 | 94 | // Constants for packing levels. 95 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 96 | 97 | // 98 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 99 | C_DATA_WIDTH; 100 | 101 | 102 | ///////////////////////////////////////////////////////////////////////////// 103 | // Functions 104 | ///////////////////////////////////////////////////////////////////////////// 105 | 106 | 107 | ///////////////////////////////////////////////////////////////////////////// 108 | // Internal signals 109 | ///////////////////////////////////////////////////////////////////////////// 110 | 111 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 112 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 113 | wire [C_FIX_DATA_WIDTH-1:0] m_local; 114 | wire [C_FIX_DATA_WIDTH-1:0] v_local; 115 | wire [C_NUM_LUT-1:0] sel; 116 | wire [C_NUM_LUT:0] carry_local; 117 | 118 | 119 | ///////////////////////////////////////////////////////////////////////////// 120 | // 121 | ///////////////////////////////////////////////////////////////////////////// 122 | 123 | generate 124 | // Assign input to local vectors. 125 | assign carry_local[0] = CIN; 126 | 127 | // Extend input data to fit. 128 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 129 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 130 | assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 131 | assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 132 | assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 133 | end else begin : NO_EXTENDED_DATA 134 | assign a_local = A; 135 | assign b_local = B; 136 | assign m_local = M; 137 | assign v_local = C_VALUE; 138 | end 139 | 140 | // Instantiate one carry and per level. 141 | for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL 142 | // Create the local select signal 143 | assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 144 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 145 | ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 146 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) | 147 | ( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 148 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) == 149 | ( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] & 150 | m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) ); 151 | 152 | // Instantiate each LUT level. 153 | carry_and # 154 | ( 155 | .C_FAMILY(C_FAMILY) 156 | ) compare_inst 157 | ( 158 | .COUT (carry_local[lut_cnt+1]), 159 | .CIN (carry_local[lut_cnt]), 160 | .S (sel[lut_cnt]) 161 | ); 162 | 163 | end // end for lut_cnt 164 | 165 | // Assign output from local vector. 166 | assign COUT = carry_local[C_NUM_LUT]; 167 | 168 | endgenerate 169 | 170 | 171 | endmodule 172 | 173 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_static.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR (against constant) with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator_sel_static # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter C_VALUE = 4'b0, 65 | // Static value to compare against. 66 | parameter integer C_DATA_WIDTH = 4 67 | // Data width for comparator. 68 | ) 69 | ( 70 | input wire CIN, 71 | input wire S, 72 | input wire [C_DATA_WIDTH-1:0] A, 73 | input wire [C_DATA_WIDTH-1:0] B, 74 | output wire COUT 75 | ); 76 | 77 | 78 | ///////////////////////////////////////////////////////////////////////////// 79 | // Variables for generating parameter controlled instances. 80 | ///////////////////////////////////////////////////////////////////////////// 81 | 82 | // Generate variable for bit vector. 83 | genvar bit_cnt; 84 | 85 | 86 | ///////////////////////////////////////////////////////////////////////////// 87 | // Local params 88 | ///////////////////////////////////////////////////////////////////////////// 89 | 90 | // Bits per LUT for this architecture. 91 | localparam integer C_BITS_PER_LUT = 2; 92 | 93 | // Constants for packing levels. 94 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 95 | 96 | // 97 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 98 | C_DATA_WIDTH; 99 | 100 | 101 | ///////////////////////////////////////////////////////////////////////////// 102 | // Functions 103 | ///////////////////////////////////////////////////////////////////////////// 104 | 105 | 106 | ///////////////////////////////////////////////////////////////////////////// 107 | // Internal signals 108 | ///////////////////////////////////////////////////////////////////////////// 109 | 110 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 111 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 112 | wire [C_FIX_DATA_WIDTH-1:0] v_local; 113 | wire [C_NUM_LUT-1:0] sel; 114 | wire [C_NUM_LUT:0] carry_local; 115 | 116 | 117 | ///////////////////////////////////////////////////////////////////////////// 118 | // 119 | ///////////////////////////////////////////////////////////////////////////// 120 | 121 | generate 122 | // Assign input to local vectors. 123 | assign carry_local[0] = CIN; 124 | 125 | // Extend input data to fit. 126 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 127 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 128 | assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 129 | assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 130 | end else begin : NO_EXTENDED_DATA 131 | assign a_local = A; 132 | assign b_local = B; 133 | assign v_local = C_VALUE; 134 | end 135 | 136 | // Instantiate one carry and per level. 137 | for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL 138 | // Create the local select signal 139 | assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 140 | v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) | 141 | ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 142 | v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) ); 143 | 144 | // Instantiate each LUT level. 145 | carry_and # 146 | ( 147 | .C_FAMILY(C_FAMILY) 148 | ) compare_inst 149 | ( 150 | .COUT (carry_local[bit_cnt+1]), 151 | .CIN (carry_local[bit_cnt]), 152 | .S (sel[bit_cnt]) 153 | ); 154 | 155 | end // end for bit_cnt 156 | 157 | // Assign output from local vector. 158 | assign COUT = carry_local[C_NUM_LUT]; 159 | 160 | endgenerate 161 | 162 | 163 | endmodule 164 | 165 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_static.v: -------------------------------------------------------------------------------- 1 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 2 | // -- 3 | // -- This file contains confidential and proprietary information 4 | // -- of Xilinx, Inc. and is protected under U.S. and 5 | // -- international copyright and other intellectual property 6 | // -- laws. 7 | // -- 8 | // -- DISCLAIMER 9 | // -- This disclaimer is not a license and does not grant any 10 | // -- rights to the materials distributed herewith. Except as 11 | // -- otherwise provided in a valid license issued to you by 12 | // -- Xilinx, and to the maximum extent permitted by applicable 13 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | // -- including negligence, or under any other theory of 20 | // -- liability) for any loss or damage of any kind or nature 21 | // -- related to, arising under or in connection with these 22 | // -- materials, including for any direct, or any indirect, 23 | // -- special, incidental, or consequential loss or damage 24 | // -- (including loss of data, profits, goodwill, or any type of 25 | // -- loss or damage suffered as a result of any action brought 26 | // -- by a third party) even if such damage or loss was 27 | // -- reasonably foreseeable or Xilinx had been advised of the 28 | // -- possibility of the same. 29 | // -- 30 | // -- CRITICAL APPLICATIONS 31 | // -- Xilinx products are not designed or intended to be fail- 32 | // -- safe, or for use in any application requiring fail-safe 33 | // -- performance, such as life-support or safety devices or 34 | // -- systems, Class III medical devices, nuclear facilities, 35 | // -- applications related to the deployment of airbags, or any 36 | // -- other applications that could lead to death, personal 37 | // -- injury, or severe property or environmental damage 38 | // -- (individually and collectively, "Critical 39 | // -- Applications"). Customer assumes the sole risk and 40 | // -- liability of any use of Xilinx products in Critical 41 | // -- Applications, subject only to applicable laws and 42 | // -- regulations governing limitations on product liability. 43 | // -- 44 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // -- PART OF THIS FILE AT ALL TIMES. 46 | //----------------------------------------------------------------------------- 47 | // 48 | // Description: 49 | // Optimized COMPARATOR (against constant) with carry logic. 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // 56 | // 57 | //-------------------------------------------------------------------------- 58 | `timescale 1ps/1ps 59 | 60 | module comparator_static # 61 | ( 62 | parameter C_FAMILY = "virtex6", 63 | // FPGA Family. Current version: virtex6 or spartan6. 64 | parameter C_VALUE = 4'b0, 65 | // Static value to compare against. 66 | parameter integer C_DATA_WIDTH = 4 67 | // Data width for comparator. 68 | ) 69 | ( 70 | input wire CIN, 71 | input wire [C_DATA_WIDTH-1:0] A, 72 | output wire COUT 73 | ); 74 | 75 | 76 | ///////////////////////////////////////////////////////////////////////////// 77 | // Variables for generating parameter controlled instances. 78 | ///////////////////////////////////////////////////////////////////////////// 79 | 80 | // Generate variable for bit vector. 81 | genvar bit_cnt; 82 | 83 | 84 | ///////////////////////////////////////////////////////////////////////////// 85 | // Local params 86 | ///////////////////////////////////////////////////////////////////////////// 87 | 88 | // Bits per LUT for this architecture. 89 | localparam integer C_BITS_PER_LUT = 6; 90 | 91 | // Constants for packing levels. 92 | localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT; 93 | 94 | // 95 | localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT : 96 | C_DATA_WIDTH; 97 | 98 | 99 | ///////////////////////////////////////////////////////////////////////////// 100 | // Functions 101 | ///////////////////////////////////////////////////////////////////////////// 102 | 103 | 104 | ///////////////////////////////////////////////////////////////////////////// 105 | // Internal signals 106 | ///////////////////////////////////////////////////////////////////////////// 107 | 108 | wire [C_FIX_DATA_WIDTH-1:0] a_local; 109 | wire [C_FIX_DATA_WIDTH-1:0] b_local; 110 | wire [C_NUM_LUT-1:0] sel; 111 | wire [C_NUM_LUT:0] carry_local; 112 | 113 | 114 | ///////////////////////////////////////////////////////////////////////////// 115 | // 116 | ///////////////////////////////////////////////////////////////////////////// 117 | 118 | generate 119 | // Assign input to local vectors. 120 | assign carry_local[0] = CIN; 121 | 122 | // Extend input data to fit. 123 | if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA 124 | assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 125 | assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}}; 126 | end else begin : NO_EXTENDED_DATA 127 | assign a_local = A; 128 | assign b_local = C_VALUE; 129 | end 130 | 131 | // Instantiate one carry and per level. 132 | for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL 133 | // Create the local select signal 134 | assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == 135 | b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ); 136 | 137 | // Instantiate each LUT level. 138 | carry_and # 139 | ( 140 | .C_FAMILY(C_FAMILY) 141 | ) compare_inst 142 | ( 143 | .COUT (carry_local[bit_cnt+1]), 144 | .CIN (carry_local[bit_cnt]), 145 | .S (sel[bit_cnt]) 146 | ); 147 | 148 | end // end for bit_cnt 149 | 150 | // Assign output from local vector. 151 | assign COUT = carry_local[C_NUM_LUT]; 152 | 153 | endgenerate 154 | 155 | 156 | endmodule 157 | 158 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/mcb_ui_top_synch.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | //Device: Spartan6 50 | //Design Name: DDR/DDR2/DDR3/LPDDR 51 | //Purpose: 52 | //Reference: 53 | // This module instantiates the clock synchronization logic. It passes the 54 | // incoming signal through two flops to ensure metastability. 55 | // 56 | //***************************************************************************** 57 | `timescale 1ps / 1ps 58 | 59 | module mcb_ui_top_synch # 60 | ( 61 | /////////////////////////////////////////////////////////////////////////////// 62 | // Parameter Definitions 63 | /////////////////////////////////////////////////////////////////////////////// 64 | parameter integer C_SYNCH_WIDTH = 0 65 | ) 66 | ( 67 | /////////////////////////////////////////////////////////////////////////////// 68 | // Port Declarations 69 | /////////////////////////////////////////////////////////////////////////////// 70 | input wire clk, 71 | input wire [C_SYNCH_WIDTH-1:0] synch_in , 72 | output wire [C_SYNCH_WIDTH-1:0] synch_out 73 | ); 74 | 75 | //////////////////////////////////////////////////////////////////////////////// 76 | // Local Parameters 77 | //////////////////////////////////////////////////////////////////////////////// 78 | 79 | //////////////////////////////////////////////////////////////////////////////// 80 | // Wires/Reg declarations 81 | //////////////////////////////////////////////////////////////////////////////// 82 | (* shreg_extract = "no" *) 83 | reg [C_SYNCH_WIDTH-1:0] synch_d1; 84 | (* shreg_extract = "no" *) 85 | reg [C_SYNCH_WIDTH-1:0] synch_d2; 86 | 87 | always @(posedge clk) begin 88 | synch_d1 <= synch_in; 89 | end 90 | 91 | always @(posedge clk) begin 92 | synch_d2 <= synch_d1; 93 | end 94 | 95 | assign synch_out = synch_d2; 96 | 97 | endmodule 98 | 99 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/data_gen_chk.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: data_gen_chk.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:33 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: Virtex6/Spartan6/7series 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module is used LFSR to generate random data for memory 62 | // data write or memory data read comparison. This always 63 | // generates 32-bit data only. This also checks the received 64 | // data 65 | //Reference: 66 | //Revision History: 67 | //***************************************************************************** 68 | 69 | module data_gen_chk # ( 70 | 71 | parameter C_AXI_DATA_WIDTH = 32 // Width of the AXI write and read data 72 | 73 | ) 74 | ( 75 | input clk, 76 | input data_en, 77 | input [2:0] data_pattern, 78 | input pattern_init, // when high the patterns are initialized 79 | input [31:0] prbs_seed_i, 80 | input [C_AXI_DATA_WIDTH-1:0] rdata, 81 | input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld, 82 | input rdata_vld, 83 | input wrd_cntr_rst, 84 | output msmatch_err, // Indicates there is a mismatch error 85 | output reg [7:0] wrd_cntr, // Word count output 86 | output reg [31:0] data_o // generated data 87 | ); 88 | 89 | reg [31:0] prbs; 90 | reg [32:1] lfsr_q; 91 | reg [31:0] walk0; 92 | wire [31:0] walk1; 93 | reg [C_AXI_DATA_WIDTH/32-1:0] msmatch_err_sig; 94 | 95 | //***************************************************************************** 96 | // Data generate segment 97 | //***************************************************************************** 98 | 99 | always @ (posedge clk) begin 100 | if (pattern_init) begin 101 | lfsr_q <= {prbs_seed_i + 32'h55555555}; 102 | end 103 | else if (data_en) begin 104 | lfsr_q[32:9] <= lfsr_q[31:8]; 105 | lfsr_q[8] <= lfsr_q[32] ^ lfsr_q[7]; 106 | lfsr_q[7] <= lfsr_q[32] ^ lfsr_q[6]; 107 | lfsr_q[6:4] <= lfsr_q[5:3]; 108 | 109 | lfsr_q[3] <= lfsr_q[32] ^ lfsr_q[2]; 110 | lfsr_q[2] <= lfsr_q[1] ; 111 | lfsr_q[1] <= lfsr_q[32]; 112 | end 113 | end 114 | 115 | always @(posedge clk) 116 | if (pattern_init) 117 | walk0 <= 32'hFFFF_FFFE; 118 | else if (data_en) 119 | walk0 <= walk0 << 1; 120 | 121 | assign walk1 = ~walk0; 122 | 123 | always @(*) begin 124 | prbs = lfsr_q[32:1]; 125 | end 126 | 127 | always @(*) begin 128 | case (data_pattern) 129 | 3'b001: data_o = prbs; // PRBS pattern 130 | 3'b010: data_o = walk0; // Walking zeros 131 | 3'b011: data_o = walk1; // Walking ones 132 | 3'b100: data_o = 32'hFFFF_FFFF; // All ones 133 | 3'b101: data_o = 32'h0000_0000; // All zeros 134 | default: data_o = 32'h5A5A_A5A5; 135 | endcase 136 | end 137 | 138 | //***************************************************************************** 139 | // Data check segment 140 | //***************************************************************************** 141 | 142 | always @(posedge clk) 143 | if (wrd_cntr_rst) 144 | wrd_cntr <= 8'h00; 145 | else if (rdata_vld & !msmatch_err) 146 | wrd_cntr <= wrd_cntr + 8'h01; 147 | 148 | genvar i; 149 | generate 150 | begin: data_check 151 | for (i = 0; i <= (C_AXI_DATA_WIDTH/32-1); i=i+1) begin: gen_data_check 152 | always @(posedge clk) 153 | if (wrd_cntr_rst) 154 | msmatch_err_sig[i] <= 1'b0; 155 | else if (rdata_vld & 156 | ((rdata[((i*32)+7):i*32] != data_o[7:0] & rdata_bvld[(i*4)]) | 157 | (rdata[((i*32)+15):((i*32)+8)] != data_o[15:8] & rdata_bvld[(i*4)+1]) | 158 | (rdata[((i*32)+23):((i*32)+16)] != data_o[23:16] & rdata_bvld[(i*4)+2]) | 159 | (rdata[((i*32)+31):((i*32)+24)] != data_o[31:24] & rdata_bvld[(i*4)+3]))) 160 | msmatch_err_sig[i] <= 1'b1; 161 | else 162 | msmatch_err_sig[i] <= 1'b0; 163 | end 164 | end 165 | endgenerate 166 | 167 | assign msmatch_err = |msmatch_err_sig; 168 | 169 | // synthesis translate_off 170 | //***************************************************************************** 171 | // Simulation debug signals and messages 172 | //***************************************************************************** 173 | 174 | always @(posedge clk) begin 175 | if (rdata_vld & ({{C_AXI_DATA_WIDTH/32}{data_o}} !== rdata)) begin 176 | $display ("[ERROR] : Written data and read data does not match"); 177 | $display ("Data written : %h", {{C_AXI_DATA_WIDTH/32}{data_o}}); 178 | $display ("Data read : %h", rdata); 179 | $display ("Word number : %h", wrd_cntr); 180 | $display ("Simulation time : %t", $time); 181 | end 182 | end 183 | 184 | // synthesis translate_on 185 | 186 | endmodule 187 | 188 | 189 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/isim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | #***************************************************************************** 3 | # (c) Copyright 2009 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | # **************************************************************************** 50 | # ____ ____ 51 | # / /\/ / 52 | # /___/ \ / Vendor : Xilinx 53 | # \ \ \/ Version : 3.92 54 | # \ \ Application : MIG 55 | # / / Filename : isim.bat 56 | # /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $ 57 | # \ \ / \ Date Created : Fri Feb 06 2009 58 | # \___\/\___\ 59 | # 60 | # Device : Spartan-6 61 | # Design Name : DDR/DDR2/DDR3/LPDDR 62 | # Purpose : Batch file to run Simulation through ISIM 63 | # Reference : 64 | # Revision History : 65 | # **************************************************************************** 66 | 67 | echo Simulation Tool: ISIM 68 | fuse work.sim_tb_top work.glbl -prj mig.prj -L unisims_ver -L secureip -timeprecision_vhdl fs -o mig 69 | ./mig -gui -tclbatch isim.tcl -wdb mig.wdb 70 | echo done 71 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/isim.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 3.92 53 | ## \ \ Application : MIG 54 | ## / / Filename : isim.tcl 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $ 56 | ## \ \ / \ Date Created : Mon Mar 2 2009 57 | ## \___\/\___\ 58 | ## 59 | ## Device : Spartan-6 60 | ## Design Name : DDR/DDR2/DDR3/LPDDR 61 | ## Purpose : To give commands to ISIM Simulator through batch mode 62 | ## Assumptions: 63 | ## - Simulation takes place in \sim folder of MIG output directory 64 | ## Reference : 65 | ## Revision History: 66 | ############################################################################### 67 | 68 | onerror {resume} 69 | isim set radix hex 70 | wave add /sim_tb_top 71 | run 200 us 72 | quit 73 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/mig.prj: -------------------------------------------------------------------------------- 1 | verilog work ../rtl/infrastructure.v 2 | verilog work ../rtl/memc_wrapper.v 3 | verilog work ../rtl/mig.v 4 | verilog work ../rtl/axi/a_upsizer.v 5 | verilog work ../rtl/axi/axi_mcb.v 6 | verilog work ../rtl/axi/axi_mcb_ar_channel.v 7 | verilog work ../rtl/axi/axi_mcb_aw_channel.v 8 | verilog work ../rtl/axi/axi_mcb_b_channel.v 9 | verilog work ../rtl/axi/axi_mcb_cmd_arbiter.v 10 | verilog work ../rtl/axi/axi_mcb_cmd_fsm.v 11 | verilog work ../rtl/axi/axi_mcb_cmd_translator.v 12 | verilog work ../rtl/axi/axi_mcb_incr_cmd.v 13 | verilog work ../rtl/axi/axi_mcb_r_channel.v 14 | verilog work ../rtl/axi/axi_mcb_simple_fifo.v 15 | verilog work ../rtl/axi/axi_mcb_w_channel.v 16 | verilog work ../rtl/axi/axi_mcb_wrap_cmd.v 17 | verilog work ../rtl/axi/axi_register_slice.v 18 | verilog work ../rtl/axi/axi_upsizer.v 19 | verilog work ../rtl/axi/axic_register_slice.v 20 | verilog work ../rtl/axi/carry.v 21 | verilog work ../rtl/axi/carry_and.v 22 | verilog work ../rtl/axi/carry_latch_and.v 23 | verilog work ../rtl/axi/carry_latch_or.v 24 | verilog work ../rtl/axi/carry_or.v 25 | verilog work ../rtl/axi/command_fifo.v 26 | verilog work ../rtl/axi/comparator.v 27 | verilog work ../rtl/axi/comparator_mask.v 28 | verilog work ../rtl/axi/comparator_mask_static.v 29 | verilog work ../rtl/axi/comparator_sel.v 30 | verilog work ../rtl/axi/comparator_sel_mask.v 31 | verilog work ../rtl/axi/comparator_sel_mask_static.v 32 | verilog work ../rtl/axi/comparator_sel_static.v 33 | verilog work ../rtl/axi/comparator_static.v 34 | verilog work ../rtl/axi/mcb_ui_top_synch.v 35 | verilog work ../rtl/axi/mux_enc.v 36 | verilog work ../rtl/axi/r_upsizer.v 37 | verilog work ../rtl/axi/w_upsizer.v 38 | verilog work ../rtl/mcb_controller/iodrp_controller.v 39 | verilog work ../rtl/mcb_controller/iodrp_mcb_controller.v 40 | verilog work ../rtl/mcb_controller/mcb_raw_wrapper.v 41 | verilog work ../rtl/mcb_controller/mcb_soft_calibration.v 42 | verilog work ../rtl/mcb_controller/mcb_soft_calibration_top.v 43 | verilog work ../rtl/mcb_controller/mcb_ui_top.v 44 | verilog work ./axi4_tg.v 45 | verilog work ./axi4_wrapper.v 46 | verilog work ./cmd_prbs_gen_axi.v 47 | verilog work ./data_gen_chk.v 48 | verilog work ./s6_axi4_tg.v 49 | verilog work ./tg.v 50 | verilog work ../rtl/memc_wrapper.v -d AXI_ENABLE 51 | verilog work $XILINX/verilog/src/glbl.v 52 | verilog work ./sim_tb_top.v 53 | verilog work ./ddr3_model_c3.v -d x2Gb -d sg125 -d x16 -i ./ 54 | 55 | 56 | 57 | 58 | 59 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/readme.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 3.92 53 | ## \ \ Application : MIG 54 | ## / / Filename : readme.txt 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $ 56 | ## \ \ / \ Date Created : Mon Oct 19 2009 57 | ## \___\/\___\ 58 | ## 59 | ## Device : Spartan-6 60 | ## Design Name : DDR/DDR2/DDR3/LPDDR 61 | ## Purpose : Steps to run simulation using ISIM/Modelsim simualtor in this folder 62 | ## Assumptions: 63 | ## - Simulation takes place in \sim\ folder of MIG output directory 64 | ## Reference : 65 | ## Revision History: 66 | ############################################################################### 67 | 68 | The sim/functional folder has files to perform functional simulation of the design. 69 | 70 | 1. Simulation using Modelsim simulator 71 | 72 | A) sim.do File : 73 | 74 | 1) The 'sim.do' file has commands to compile and simulate memory interface 75 | design and run the simulation for specified period of time. 76 | 77 | 2) It has the syntax to Map the required libraries. 78 | Also, $XILINX environment variable must be set in order to compile glbl.v file 79 | 80 | 3) Displays the waveforms that are listed with "add wave" command. 81 | 82 | B) Steps to run the Modelsim simulation: 83 | 84 | 1) The user should invoke the Modelsim simulator GUI. 85 | 2) Change the present working directory path to the sim/functional folder. 86 | In Transcript window, at Modelsim prompt, type the following command to 87 | change directory path. 88 | cd 89 | 90 | 2) Run the simulation using sim.do file. 91 | At Modelsim prompt, type the following command: 92 | do sim.do 93 | 94 | 3) To exit simulation, type the following command at Modelsim prompt: 95 | quit -f 96 | 97 | 4) Verify the transcript file for the memory transactions. 98 | 99 | 100 | 2. Simulation using ISIM simulator 101 | 102 | A) Following files are provided : 103 | 104 | 1) The '.prj' file contains the list of all the files associated with the design. 105 | It also contains the hdl, library and the source file name. 106 | 107 | 2) The '.tcl' file contains the Tcl commands for simulation and 108 | resume on error. 109 | 110 | 3) The 'isim.bat' has commands which use '.prj' and '.tcl' files. 111 | 112 | 113 | B) Steps to run the ISIM simulation: 114 | 115 | The user should execute the file isim.bat, which does the following steps: 116 | 1) Compiles, elaborates the design and generates the simulation executable using 117 | the fuse command in 'isim.bat' file. 118 | 119 | 2) Invokes the ISIM GUI. 120 | 121 | 3) User can add required signals from objects window to the waveform viewer and run 122 | simulation for specified time using the command "run