├── LICENSE ├── README.md ├── boards └── digilent_digital_discovery │ ├── README.md │ ├── dcm12_100.v │ ├── dcm12_48.v │ ├── fpga.ucf │ ├── fpga_top.v │ ├── ipcore_dir │ ├── coregen.cgp │ ├── mig.gise │ ├── mig.prj │ ├── mig.xco │ ├── mig.xise │ └── mig │ │ └── user_design │ │ ├── datasheet.txt │ │ ├── mig.prj │ │ ├── par │ │ ├── create_ise.sh │ │ ├── icon_coregen.xco │ │ ├── ila_coregen.xco │ │ ├── ise_flow.sh │ │ ├── ise_run.txt │ │ ├── makeproj.sh │ │ ├── mem_interface_top.ut │ │ ├── mig.ucf │ │ ├── readme.txt │ │ ├── rem_files.sh │ │ ├── set_ise_prop.tcl │ │ └── vio_coregen.xco │ │ ├── rtl │ │ ├── axi │ │ │ ├── a_upsizer.v │ │ │ ├── axi_mcb.v │ │ │ ├── axi_mcb_ar_channel.v │ │ │ ├── axi_mcb_aw_channel.v │ │ │ ├── axi_mcb_b_channel.v │ │ │ ├── axi_mcb_cmd_arbiter.v │ │ │ ├── axi_mcb_cmd_fsm.v │ │ │ ├── axi_mcb_cmd_translator.v │ │ │ ├── axi_mcb_incr_cmd.v │ │ │ ├── axi_mcb_r_channel.v │ │ │ ├── axi_mcb_simple_fifo.v │ │ │ ├── axi_mcb_w_channel.v │ │ │ ├── axi_mcb_wrap_cmd.v │ │ │ ├── axi_register_slice.v │ │ │ ├── axi_upsizer.v │ │ │ ├── axic_register_slice.v │ │ │ ├── carry.v │ │ │ ├── carry_and.v │ │ │ ├── carry_latch_and.v │ │ │ ├── carry_latch_or.v │ │ │ ├── carry_or.v │ │ │ ├── command_fifo.v │ │ │ ├── comparator.v │ │ │ ├── comparator_mask.v │ │ │ ├── comparator_mask_static.v │ │ │ ├── comparator_sel.v │ │ │ ├── comparator_sel_mask.v │ │ │ ├── comparator_sel_mask_static.v │ │ │ ├── comparator_sel_static.v │ │ │ ├── comparator_static.v │ │ │ ├── mcb_ui_top_synch.v │ │ │ ├── mux_enc.v │ │ │ ├── r_upsizer.v │ │ │ └── w_upsizer.v │ │ ├── infrastructure.v │ │ ├── mcb_controller │ │ │ ├── iodrp_controller.v │ │ │ ├── iodrp_mcb_controller.v │ │ │ ├── mcb_raw_wrapper.v │ │ │ ├── mcb_soft_calibration.v │ │ │ ├── mcb_soft_calibration_top.v │ │ │ └── mcb_ui_top.v │ │ ├── memc_wrapper.v │ │ └── mig.v │ │ ├── sim │ │ ├── axi4_tg.v │ │ ├── axi4_wrapper.v │ │ ├── cmd_prbs_gen_axi.v │ │ ├── data_gen_chk.v │ │ ├── ddr3_model_c3.v │ │ ├── ddr3_model_parameters_c3.vh │ │ ├── isim.sh │ │ ├── isim.tcl │ │ ├── mig.prj │ │ ├── readme.txt │ │ ├── s6_axi4_tg.v │ │ ├── sim.do │ │ ├── sim_tb_top.v │ │ └── tg.v │ │ └── synth │ │ ├── mem_interface_top_synp.sdc │ │ ├── mig.lso │ │ ├── mig.prj │ │ └── script_synp.tcl │ ├── prebuilt │ └── fpga.bit │ ├── reset_gen.v │ ├── spartan6_pll.v │ └── top.v ├── core ├── capture │ ├── capture_rle.v │ ├── capture_rle_cdc.v │ ├── logic_capture.v │ ├── logic_capture_defs.v │ ├── logic_capture_fifo.v │ ├── logic_capture_mem.v │ ├── logic_capture_mem_axi.v │ ├── logic_capture_mem_axi_axi.v │ ├── logic_capture_mem_fifo_ram.v │ └── logic_capture_mem_track_fifo.v ├── fabric │ ├── axi4_arb.v │ ├── axi4_cdc.v │ ├── axi4_cdc_fifo37.v │ ├── axi4_cdc_fifo39.v │ ├── axi4_cdc_fifo46.v │ ├── axi4_cdc_fifo6.v │ ├── axi4_lite_tap.v │ └── axi4_retime.v └── ft245 │ ├── ft245_axi.v │ ├── ft245_axi_retime.v │ └── ft245_fifo.v └── docs ├── pulseview_counter.png ├── pulseview_spdif.png └── pulseview_uart.png /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/README.md -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/README.md -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/dcm12_100.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/dcm12_100.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/dcm12_48.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/dcm12_48.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/fpga.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/fpga.ucf -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/fpga_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/fpga_top.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/coregen.cgp -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig.gise -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig.prj -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig.xco -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig.xise -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/datasheet.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/datasheet.txt -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/mig.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/mig.prj -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/create_ise.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/create_ise.sh -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/icon_coregen.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/icon_coregen.xco -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ila_coregen.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ila_coregen.xco -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ise_flow.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ise_flow.sh -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ise_run.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/ise_run.txt -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/makeproj.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/makeproj.sh -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/mem_interface_top.ut: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/mem_interface_top.ut -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/mig.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/mig.ucf -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/readme.txt -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/rem_files.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/rem_files.sh -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/set_ise_prop.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/set_ise_prop.tcl -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/vio_coregen.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/par/vio_coregen.xco -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/a_upsizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/a_upsizer.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_ar_channel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_ar_channel.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_aw_channel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_aw_channel.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_b_channel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_b_channel.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_cmd_arbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_cmd_arbiter.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_cmd_fsm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_cmd_fsm.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_cmd_translator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_cmd_translator.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_incr_cmd.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_incr_cmd.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_r_channel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_r_channel.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_simple_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_simple_fifo.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_w_channel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_w_channel.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_wrap_cmd.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_mcb_wrap_cmd.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_register_slice.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_register_slice.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_upsizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axi_upsizer.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axic_register_slice.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/axic_register_slice.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_and.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_and.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_latch_and.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_latch_and.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_latch_or.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_latch_or.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_or.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/carry_or.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/command_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/command_fifo.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_mask.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_mask.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_mask_static.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_mask_static.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_mask.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_mask.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_mask_static.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_mask_static.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_static.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_sel_static.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_static.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/comparator_static.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/mcb_ui_top_synch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/mcb_ui_top_synch.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/mux_enc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/mux_enc.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/r_upsizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/r_upsizer.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/w_upsizer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/axi/w_upsizer.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/infrastructure.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/infrastructure.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/iodrp_controller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/iodrp_controller.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/iodrp_mcb_controller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/iodrp_mcb_controller.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_raw_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_raw_wrapper.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_soft_calibration.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_soft_calibration.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_ui_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mcb_controller/mcb_ui_top.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/memc_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/memc_wrapper.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mig.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/rtl/mig.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/axi4_tg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/axi4_tg.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/axi4_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/axi4_wrapper.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/cmd_prbs_gen_axi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/cmd_prbs_gen_axi.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/data_gen_chk.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/data_gen_chk.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/ddr3_model_c3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/ddr3_model_c3.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/ddr3_model_parameters_c3.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/ddr3_model_parameters_c3.vh -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/isim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/isim.sh -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/isim.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/isim.tcl -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/mig.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/mig.prj -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/readme.txt -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/s6_axi4_tg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/s6_axi4_tg.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/sim.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/sim.do -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/sim_tb_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/sim_tb_top.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/tg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/sim/tg.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/synth/mem_interface_top_synp.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/synth/mem_interface_top_synp.sdc -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/synth/mig.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/synth/mig.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/synth/mig.prj -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/ipcore_dir/mig/user_design/synth/script_synp.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/ipcore_dir/mig/user_design/synth/script_synp.tcl -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/prebuilt/fpga.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/prebuilt/fpga.bit -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/reset_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/reset_gen.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/spartan6_pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/spartan6_pll.v -------------------------------------------------------------------------------- /boards/digilent_digital_discovery/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/boards/digilent_digital_discovery/top.v -------------------------------------------------------------------------------- /core/capture/capture_rle.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/capture_rle.v -------------------------------------------------------------------------------- /core/capture/capture_rle_cdc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/capture_rle_cdc.v -------------------------------------------------------------------------------- /core/capture/logic_capture.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture.v -------------------------------------------------------------------------------- /core/capture/logic_capture_defs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture_defs.v -------------------------------------------------------------------------------- /core/capture/logic_capture_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture_fifo.v -------------------------------------------------------------------------------- /core/capture/logic_capture_mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture_mem.v -------------------------------------------------------------------------------- /core/capture/logic_capture_mem_axi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture_mem_axi.v -------------------------------------------------------------------------------- /core/capture/logic_capture_mem_axi_axi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture_mem_axi_axi.v -------------------------------------------------------------------------------- /core/capture/logic_capture_mem_fifo_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture_mem_fifo_ram.v -------------------------------------------------------------------------------- /core/capture/logic_capture_mem_track_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/capture/logic_capture_mem_track_fifo.v -------------------------------------------------------------------------------- /core/fabric/axi4_arb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_arb.v -------------------------------------------------------------------------------- /core/fabric/axi4_cdc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_cdc.v -------------------------------------------------------------------------------- /core/fabric/axi4_cdc_fifo37.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_cdc_fifo37.v -------------------------------------------------------------------------------- /core/fabric/axi4_cdc_fifo39.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_cdc_fifo39.v -------------------------------------------------------------------------------- /core/fabric/axi4_cdc_fifo46.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_cdc_fifo46.v -------------------------------------------------------------------------------- /core/fabric/axi4_cdc_fifo6.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_cdc_fifo6.v -------------------------------------------------------------------------------- /core/fabric/axi4_lite_tap.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_lite_tap.v -------------------------------------------------------------------------------- /core/fabric/axi4_retime.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/fabric/axi4_retime.v -------------------------------------------------------------------------------- /core/ft245/ft245_axi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/ft245/ft245_axi.v -------------------------------------------------------------------------------- /core/ft245/ft245_axi_retime.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/ft245/ft245_axi_retime.v -------------------------------------------------------------------------------- /core/ft245/ft245_fifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/core/ft245/ft245_fifo.v -------------------------------------------------------------------------------- /docs/pulseview_counter.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/docs/pulseview_counter.png -------------------------------------------------------------------------------- /docs/pulseview_spdif.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/docs/pulseview_spdif.png -------------------------------------------------------------------------------- /docs/pulseview_uart.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ultraembedded/openlogicbit/HEAD/docs/pulseview_uart.png --------------------------------------------------------------------------------