├── .gitignore ├── AddressMapping.cpp ├── AddressMapping.h ├── Bank.cpp ├── Bank.h ├── BankState.cpp ├── BankState.h ├── BusPacket.cpp ├── BusPacket.h ├── CSVWriter.h ├── Callback.h ├── ClockDomain.cpp ├── ClockDomain.h ├── CommandQueue.cpp ├── CommandQueue.h ├── DRAMSim.h ├── IniReader.cpp ├── IniReader.h ├── Makefile ├── MemoryController.cpp ├── MemoryController.h ├── MemorySystem.cpp ├── MemorySystem.h ├── MultiChannelMemorySystem.cpp ├── MultiChannelMemorySystem.h ├── PrintMacros.cpp ├── PrintMacros.h ├── README ├── README.pdf ├── README.tex ├── README.txt ├── Rank.cpp ├── Rank.h ├── SimulatorObject.cpp ├── SimulatorObject.h ├── SystemConfiguration.h ├── TraceBasedSim.cpp ├── Transaction.cpp ├── Transaction.h ├── addgpl.sh ├── comparison_gen.py ├── docs ├── classes.png └── classes_relationships.dia ├── example_app ├── .gitignore ├── Makefile ├── dramsim_test.cpp └── dramsim_test.h ├── ini ├── DDR2_micron_16M_8b_x8_sg3E.ini ├── DDR2_micron_32M_4B_x4_sg3E.ini ├── DDR2_micron_32M_8B_x4_sg25E.ini ├── DDR3_micron_16M_8B_x8_sg15.ini ├── DDR3_micron_32M_8B_x4_sg125.ini ├── DDR3_micron_32M_8B_x4_sg15.ini ├── DDR3_micron_32M_8B_x8_sg15.ini ├── DDR3_micron_32M_8B_x8_sg25E.ini ├── DDR3_micron_64M_8B_x4_sg15.ini ├── DDR3_micron_8M_8B_x16_sg15.ini ├── ST-1.2x.ini ├── ST-1.5x.ini └── ST-2.0x.ini ├── system.ini.example └── traces ├── .gitignore ├── README ├── k6_aoe_02_short.trc.gz ├── mase_art.trc.gz └── traceParse.py /.gitignore: -------------------------------------------------------------------------------- 1 | results/ 2 | *.o 3 | *.po 4 | *.dep 5 | *.deppo 6 | *.swp 7 | DRAMSim 8 | libdramsim.a 9 | libdramsim.so 10 | -------------------------------------------------------------------------------- /AddressMapping.cpp: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | #include "SystemConfiguration.h" 31 | #include "AddressMapping.h" 32 | 33 | namespace DRAMSim 34 | { 35 | 36 | void addressMapping(uint64_t physicalAddress, unsigned &newTransactionChan, unsigned &newTransactionRank, unsigned &newTransactionBank, unsigned &newTransactionRow, unsigned &newTransactionColumn) 37 | { 38 | uint64_t tempA, tempB; 39 | unsigned transactionSize = TRANSACTION_SIZE; 40 | uint64_t transactionMask = transactionSize - 1; //ex: (64 bit bus width) x (8 Burst Length) - 1 = 64 bytes - 1 = 63 = 0x3f mask 41 | unsigned channelBitWidth = NUM_CHANS_LOG; 42 | unsigned rankBitWidth = NUM_RANKS_LOG; 43 | unsigned bankBitWidth = NUM_BANKS_LOG; 44 | unsigned rowBitWidth = NUM_ROWS_LOG; 45 | unsigned colBitWidth = NUM_COLS_LOG; 46 | // this forces the alignment to the width of a single burst (64 bits = 8 bytes = 3 address bits for DDR parts) 47 | unsigned byteOffsetWidth = BYTE_OFFSET_WIDTH; 48 | // Since we're assuming that a request is for BL*BUS_WIDTH, the bottom bits 49 | // of this address *should* be all zeros if it's not, issue a warning 50 | 51 | if ((physicalAddress & transactionMask) != 0) 52 | { 53 | DEBUG("WARNING: address 0x"<>= byteOffsetWidth; 59 | 60 | // The next thing we have to consider is that when a request is made for a 61 | // we've taken into account the granulaity of a single burst by shifting 62 | // off the bottom 3 bits, but a transaction has to take into account the 63 | // burst length (i.e. the requests will be aligned to cache line sizes which 64 | // should be equal to transactionSize above). 65 | // 66 | // Since the column address increments internally on bursts, the bottom n 67 | // bits of the column (colLow) have to be zero in order to account for the 68 | // total size of the transaction. These n bits should be shifted off the 69 | // address and also subtracted from the total column width. 70 | // 71 | // I am having a hard time explaining the reasoning here, but it comes down 72 | // this: for a 64 byte transaction, the bottom 6 bits of the address must be 73 | // zero. These zero bits must be made up of the byte offset (3 bits) and also 74 | // from the bottom bits of the column 75 | // 76 | // For example: cowLowBits = log2(64bytes) - 3 bits = 3 bits 77 | unsigned colLowBitWidth = COL_LOW_BIT_WIDTH; 78 | 79 | physicalAddress >>= colLowBitWidth; 80 | unsigned colHighBitWidth = colBitWidth - colLowBitWidth; 81 | if (DEBUG_ADDR_MAP) 82 | { 83 | DEBUG("Bit widths: ch:"<> bankBitWidth; 95 | tempB = physicalAddress << bankBitWidth; 96 | newTransactionBank = tempA ^ tempB; 97 | 98 | tempA = physicalAddress; 99 | physicalAddress = physicalAddress >> colHighBitWidth; 100 | tempB = physicalAddress << colHighBitWidth; 101 | newTransactionColumn = tempA ^ tempB; 102 | 103 | tempA = physicalAddress; 104 | physicalAddress = physicalAddress >> rowBitWidth; 105 | tempB = physicalAddress << rowBitWidth; 106 | newTransactionRow = tempA ^ tempB; 107 | 108 | tempA = physicalAddress; 109 | physicalAddress = physicalAddress >> rankBitWidth; 110 | tempB = physicalAddress << rankBitWidth; 111 | newTransactionRank = tempA ^ tempB; 112 | 113 | tempA = physicalAddress; 114 | physicalAddress = physicalAddress >> channelBitWidth; 115 | tempB = physicalAddress << channelBitWidth; 116 | newTransactionChan = tempA ^ tempB; 117 | 118 | } 119 | else if (addressMappingScheme == Scheme2) 120 | { 121 | //chan:row:col:bank:rank 122 | tempA = physicalAddress; 123 | physicalAddress = physicalAddress >> rankBitWidth; 124 | tempB = physicalAddress << rankBitWidth; 125 | newTransactionRank = tempA ^ tempB; 126 | 127 | tempA = physicalAddress; 128 | physicalAddress = physicalAddress >> bankBitWidth; 129 | tempB = physicalAddress << bankBitWidth; 130 | newTransactionBank = tempA ^ tempB; 131 | 132 | tempA = physicalAddress; 133 | physicalAddress = physicalAddress >> colHighBitWidth; 134 | tempB = physicalAddress << colHighBitWidth; 135 | newTransactionColumn = tempA ^ tempB; 136 | 137 | tempA = physicalAddress; 138 | physicalAddress = physicalAddress >> rowBitWidth; 139 | tempB = physicalAddress << rowBitWidth; 140 | newTransactionRow = tempA ^ tempB; 141 | 142 | tempA = physicalAddress; 143 | physicalAddress = physicalAddress >> channelBitWidth; 144 | tempB = physicalAddress << channelBitWidth; 145 | newTransactionChan = tempA ^ tempB; 146 | 147 | } 148 | else if (addressMappingScheme == Scheme3) 149 | { 150 | //chan:rank:bank:col:row 151 | tempA = physicalAddress; 152 | physicalAddress = physicalAddress >> rowBitWidth; 153 | tempB = physicalAddress << rowBitWidth; 154 | newTransactionRow = tempA ^ tempB; 155 | 156 | tempA = physicalAddress; 157 | physicalAddress = physicalAddress >> colHighBitWidth; 158 | tempB = physicalAddress << colHighBitWidth; 159 | newTransactionColumn = tempA ^ tempB; 160 | 161 | tempA = physicalAddress; 162 | physicalAddress = physicalAddress >> bankBitWidth; 163 | tempB = physicalAddress << bankBitWidth; 164 | newTransactionBank = tempA ^ tempB; 165 | 166 | tempA = physicalAddress; 167 | physicalAddress = physicalAddress >> rankBitWidth; 168 | tempB = physicalAddress << rankBitWidth; 169 | newTransactionRank = tempA ^ tempB; 170 | 171 | tempA = physicalAddress; 172 | physicalAddress = physicalAddress >> channelBitWidth; 173 | tempB = physicalAddress << channelBitWidth; 174 | newTransactionChan = tempA ^ tempB; 175 | 176 | } 177 | else if (addressMappingScheme == Scheme4) 178 | { 179 | //chan:rank:bank:row:col 180 | tempA = physicalAddress; 181 | physicalAddress = physicalAddress >> colHighBitWidth; 182 | tempB = physicalAddress << colHighBitWidth; 183 | newTransactionColumn = tempA ^ tempB; 184 | 185 | tempA = physicalAddress; 186 | physicalAddress = physicalAddress >> rowBitWidth; 187 | tempB = physicalAddress << rowBitWidth; 188 | newTransactionRow = tempA ^ tempB; 189 | 190 | tempA = physicalAddress; 191 | physicalAddress = physicalAddress >> bankBitWidth; 192 | tempB = physicalAddress << bankBitWidth; 193 | newTransactionBank = tempA ^ tempB; 194 | 195 | tempA = physicalAddress; 196 | physicalAddress = physicalAddress >> rankBitWidth; 197 | tempB = physicalAddress << rankBitWidth; 198 | newTransactionRank = tempA ^ tempB; 199 | 200 | tempA = physicalAddress; 201 | physicalAddress = physicalAddress >> channelBitWidth; 202 | tempB = physicalAddress << channelBitWidth; 203 | newTransactionChan = tempA ^ tempB; 204 | 205 | } 206 | else if (addressMappingScheme == Scheme5) 207 | { 208 | //chan:row:col:rank:bank 209 | 210 | tempA = physicalAddress; 211 | physicalAddress = physicalAddress >> bankBitWidth; 212 | tempB = physicalAddress << bankBitWidth; 213 | newTransactionBank = tempA ^ tempB; 214 | 215 | tempA = physicalAddress; 216 | physicalAddress = physicalAddress >> rankBitWidth; 217 | tempB = physicalAddress << rankBitWidth; 218 | newTransactionRank = tempA ^ tempB; 219 | 220 | tempA = physicalAddress; 221 | physicalAddress = physicalAddress >> colHighBitWidth; 222 | tempB = physicalAddress << colHighBitWidth; 223 | newTransactionColumn = tempA ^ tempB; 224 | 225 | tempA = physicalAddress; 226 | physicalAddress = physicalAddress >> rowBitWidth; 227 | tempB = physicalAddress << rowBitWidth; 228 | newTransactionRow = tempA ^ tempB; 229 | 230 | tempA = physicalAddress; 231 | physicalAddress = physicalAddress >> channelBitWidth; 232 | tempB = physicalAddress << channelBitWidth; 233 | newTransactionChan = tempA ^ tempB; 234 | 235 | 236 | } 237 | else if (addressMappingScheme == Scheme6) 238 | { 239 | //chan:row:bank:rank:col 240 | 241 | tempA = physicalAddress; 242 | physicalAddress = physicalAddress >> colHighBitWidth; 243 | tempB = physicalAddress << colHighBitWidth; 244 | newTransactionColumn = tempA ^ tempB; 245 | 246 | tempA = physicalAddress; 247 | physicalAddress = physicalAddress >> rankBitWidth; 248 | tempB = physicalAddress << rankBitWidth; 249 | newTransactionRank = tempA ^ tempB; 250 | 251 | tempA = physicalAddress; 252 | physicalAddress = physicalAddress >> bankBitWidth; 253 | tempB = physicalAddress << bankBitWidth; 254 | newTransactionBank = tempA ^ tempB; 255 | 256 | tempA = physicalAddress; 257 | physicalAddress = physicalAddress >> rowBitWidth; 258 | tempB = physicalAddress << rowBitWidth; 259 | newTransactionRow = tempA ^ tempB; 260 | 261 | tempA = physicalAddress; 262 | physicalAddress = physicalAddress >> channelBitWidth; 263 | tempB = physicalAddress << channelBitWidth; 264 | newTransactionChan = tempA ^ tempB; 265 | 266 | 267 | } 268 | // clone of scheme 5, but channel moved to lower bits 269 | else if (addressMappingScheme == Scheme7) 270 | { 271 | //row:col:rank:bank:chan 272 | tempA = physicalAddress; 273 | physicalAddress = physicalAddress >> channelBitWidth; 274 | tempB = physicalAddress << channelBitWidth; 275 | newTransactionChan = tempA ^ tempB; 276 | 277 | tempA = physicalAddress; 278 | physicalAddress = physicalAddress >> bankBitWidth; 279 | tempB = physicalAddress << bankBitWidth; 280 | newTransactionBank = tempA ^ tempB; 281 | 282 | tempA = physicalAddress; 283 | physicalAddress = physicalAddress >> rankBitWidth; 284 | tempB = physicalAddress << rankBitWidth; 285 | newTransactionRank = tempA ^ tempB; 286 | 287 | tempA = physicalAddress; 288 | physicalAddress = physicalAddress >> colHighBitWidth; 289 | tempB = physicalAddress << colHighBitWidth; 290 | newTransactionColumn = tempA ^ tempB; 291 | 292 | tempA = physicalAddress; 293 | physicalAddress = physicalAddress >> rowBitWidth; 294 | tempB = physicalAddress << rowBitWidth; 295 | newTransactionRow = tempA ^ tempB; 296 | 297 | } 298 | 299 | else 300 | { 301 | ERROR("== Error - Unknown Address Mapping Scheme"); 302 | exit(-1); 303 | } 304 | if (DEBUG_ADDR_MAP) 305 | { 306 | DEBUG("Mapped Ch="<row == row) 71 | { 72 | //found it 73 | return head; 74 | } 75 | //keep looking 76 | head = head->next; 77 | } 78 | //if we get here, didn't find it 79 | return NULL; 80 | } 81 | 82 | void Bank::read(BusPacket *busPacket) 83 | { 84 | DataStruct *rowHeadNode = rowEntries[busPacket->column]; 85 | DataStruct *foundNode = NULL; 86 | 87 | if ((foundNode = Bank::searchForRow(busPacket->row, rowHeadNode)) == NULL) 88 | { 89 | // the row hasn't been written before, so it isn't in the list 90 | //if(SHOW_SIM_OUTPUT) DEBUG("== Warning - Read from previously unwritten row " << busPacket->row); 91 | void *garbage = calloc(BL * (JEDEC_DATA_BUS_BITS/8),1); 92 | ((long *)garbage)[0] = 0xdeadbeef; // tracer value 93 | busPacket->data = garbage; 94 | } 95 | else // found it 96 | { 97 | busPacket->data = foundNode->data; 98 | } 99 | 100 | //the return packet should be a data packet, not a read packet 101 | busPacket->busPacketType = DATA; 102 | } 103 | 104 | 105 | void Bank::write(const BusPacket *busPacket) 106 | { 107 | //TODO: move all the error checking to BusPacket so once we have a bus packet, 108 | // we know the fields are all legal 109 | 110 | if (busPacket->column >= NUM_COLS) 111 | { 112 | ERROR("== Error - Bus Packet column "<< busPacket->column <<" out of bounds"); 113 | exit(-1); 114 | } 115 | 116 | // head of the list we need to search 117 | DataStruct *rowHeadNode = rowEntries[busPacket->column]; 118 | DataStruct *foundNode = NULL; 119 | 120 | if ((foundNode = Bank::searchForRow(busPacket->row, rowHeadNode)) == NULL) 121 | { 122 | //not found 123 | DataStruct *newRowNode = (DataStruct *)malloc(sizeof(DataStruct)); 124 | 125 | //insert at the head for speed 126 | //TODO: Optimize this data structure for speedier lookups? 127 | newRowNode->row = busPacket->row; 128 | newRowNode->data = busPacket->data; 129 | newRowNode->next = rowHeadNode; 130 | rowEntries[busPacket->column] = newRowNode; 131 | } 132 | else 133 | { 134 | // found it, just plaster in the new data 135 | foundNode->data = busPacket->data; 136 | if (DEBUG_BANKS) 137 | { 138 | PRINTN(" -- Bank "<bank<<" writing to physical address 0x" << hex << busPacket->physicalAddress<printData(); 140 | PRINT(""); 141 | } 142 | } 143 | } 144 | 145 | -------------------------------------------------------------------------------- /Bank.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | #ifndef BANK_H 39 | #define BANK_H 40 | 41 | //Bank.h 42 | // 43 | //Header file for bank class 44 | // 45 | 46 | #include "SystemConfiguration.h" 47 | #include "SimulatorObject.h" 48 | #include "BankState.h" 49 | #include "BusPacket.h" 50 | #include 51 | 52 | namespace DRAMSim 53 | { 54 | class Bank 55 | { 56 | typedef struct _DataStruct 57 | { 58 | unsigned row; 59 | void *data; 60 | struct _DataStruct *next; 61 | } DataStruct; 62 | 63 | public: 64 | //functions 65 | Bank(ostream &dramsim_log_); 66 | void read(BusPacket *busPacket); 67 | void write(const BusPacket *busPacket); 68 | 69 | //fields 70 | BankState currentState; 71 | 72 | private: 73 | // private member 74 | std::vector rowEntries; 75 | ostream &dramsim_log; 76 | 77 | static DataStruct *searchForRow(unsigned row, DataStruct *head); 78 | }; 79 | } 80 | 81 | #endif 82 | 83 | -------------------------------------------------------------------------------- /BankState.cpp: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | //BankState.cpp 39 | // 40 | //Class file for bank state object 41 | // 42 | 43 | #include "BankState.h" 44 | 45 | using namespace std; 46 | using namespace DRAMSim; 47 | 48 | //All banks start precharged 49 | BankState::BankState(ostream &dramsim_log_): 50 | dramsim_log(dramsim_log_), 51 | currentBankState(Idle), 52 | openRowAddress(0), 53 | nextRead(0), 54 | nextWrite(0), 55 | nextActivate(0), 56 | nextPrecharge(0), 57 | nextPowerUp(0), 58 | lastCommand(READ), 59 | stateChangeCountdown(0) 60 | {} 61 | 62 | void BankState::print() 63 | { 64 | PRINT(" == Bank State "); 65 | if (currentBankState == Idle) 66 | { 67 | PRINT(" State : Idle" ); 68 | } 69 | else if (currentBankState == RowActive) 70 | { 71 | PRINT(" State : Active" ); 72 | } 73 | else if (currentBankState == Refreshing) 74 | { 75 | PRINT(" State : Refreshing" ); 76 | } 77 | else if (currentBankState == PowerDown) 78 | { 79 | PRINT(" State : Power Down" ); 80 | } 81 | 82 | PRINT(" OpenRowAddress : " << openRowAddress ); 83 | PRINT(" nextRead : " << nextRead ); 84 | PRINT(" nextWrite : " << nextWrite ); 85 | PRINT(" nextActivate : " << nextActivate ); 86 | PRINT(" nextPrecharge : " << nextPrecharge ); 87 | PRINT(" nextPowerUp : " << nextPowerUp ); 88 | } 89 | -------------------------------------------------------------------------------- /BankState.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | #ifndef BANKSTATE_H 39 | #define BANKSTATE_H 40 | 41 | //BankState.h 42 | // 43 | //Header file for bank state class 44 | // 45 | 46 | #include "SystemConfiguration.h" 47 | #include "BusPacket.h" 48 | 49 | namespace DRAMSim 50 | { 51 | enum CurrentBankState 52 | { 53 | Idle, 54 | RowActive, 55 | Precharging, 56 | Refreshing, 57 | PowerDown 58 | }; 59 | 60 | class BankState 61 | { 62 | ostream &dramsim_log; 63 | public: 64 | //Fields 65 | CurrentBankState currentBankState; 66 | unsigned openRowAddress; 67 | uint64_t nextRead; 68 | uint64_t nextWrite; 69 | uint64_t nextActivate; 70 | uint64_t nextPrecharge; 71 | uint64_t nextPowerUp; 72 | 73 | BusPacketType lastCommand; 74 | unsigned stateChangeCountdown; 75 | 76 | //Functions 77 | BankState(ostream &dramsim_log_); 78 | void print(); 79 | }; 80 | } 81 | 82 | #endif 83 | 84 | -------------------------------------------------------------------------------- /BusPacket.cpp: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | //BusPacket.cpp 39 | // 40 | //Class file for bus packet object 41 | // 42 | 43 | #include "BusPacket.h" 44 | 45 | using namespace DRAMSim; 46 | using namespace std; 47 | 48 | BusPacket::BusPacket(BusPacketType packtype, uint64_t physicalAddr, 49 | unsigned col, unsigned rw, unsigned r, unsigned b, void *dat, 50 | ostream &dramsim_log_) : 51 | dramsim_log(dramsim_log_), 52 | busPacketType(packtype), 53 | column(col), 54 | row(rw), 55 | bank(b), 56 | rank(r), 57 | physicalAddress(physicalAddr), 58 | data(dat) 59 | {} 60 | 61 | void BusPacket::print(uint64_t currentClockCycle, bool dataStart) 62 | { 63 | if (this == NULL) 64 | { 65 | return; 66 | } 67 | 68 | if (VERIFICATION_OUTPUT) 69 | { 70 | switch (busPacketType) 71 | { 72 | case READ: 73 | cmd_verify_out << currentClockCycle << ": read ("< 34 | #include 35 | #include 36 | #include 37 | #include 38 | 39 | #include 40 | 41 | using std::vector; 42 | using std::ostream; 43 | using std::string; 44 | /* 45 | * CSVWriter: Writes CSV data with headers to an underlying ofstream 46 | * This wrapper is meant to look like an ofstream, but it captures 47 | * the names of each field and prints it out to a header before printing 48 | * the CSV data below. 49 | * 50 | * Note: the first finalize() will not print the values out, only the headers. 51 | * One way to fix this problem would be to use a sstringstream (or something) 52 | * to buffer out the values and flush them all in one go instead of passing them 53 | * directly to the underlying stream as is the case now. 54 | * 55 | * Example usage: 56 | * 57 | * CSVWriter sw(cout); // send output to cout 58 | * sw <<"Bandwidth" << 0.5; // value ignored 59 | * sw <<"Latency" << 5; // value ignored 60 | * sw.finalize(); // flush the header 61 | * sw <<"Bandwidth" << 1.5; // field name ignored 62 | * sw <<"Latency" << 15; // field name ignored 63 | * sw.finalize(); // values printed to csv line 64 | * sw <<"Bandwidth" << 2.5; // field name ignored 65 | * sw <<"Latency" << 25; // field name ignored 66 | * sw.finalize(); // values printed to csv line 67 | * 68 | * The output of this example will be: 69 | * 70 | * Bandwidth,Latency 71 | * 1.5,15 72 | * 2.5,25 73 | * 74 | */ 75 | 76 | 77 | namespace DRAMSim { 78 | 79 | class CSVWriter { 80 | public : 81 | struct IndexedName { 82 | static const size_t MAX_TMP_STR = 64; 83 | static const unsigned SINGLE_INDEX_LEN = 4; 84 | string str; 85 | 86 | // functions 87 | static bool isNameTooLong(const char *baseName, unsigned numIndices) 88 | { 89 | return (strlen(baseName)+(numIndices*SINGLE_INDEX_LEN)) > MAX_TMP_STR; 90 | } 91 | static void checkNameLength(const char *baseName, unsigned numIndices) 92 | { 93 | if (isNameTooLong(baseName, numIndices)) 94 | { 95 | ERROR("Your string "< fieldNames; 125 | bool finalized; 126 | unsigned idx; 127 | public: 128 | 129 | // Functions 130 | void finalize() 131 | { 132 | //TODO: tag unlikely 133 | if (!finalized) 134 | { 135 | for (unsigned i=0; i // uint64_t 34 | 35 | #ifndef CALLBACK_H 36 | #define CALLBACK_H 37 | 38 | namespace DRAMSim 39 | { 40 | 41 | template 43 | class CallbackBase 44 | { 45 | public: 46 | virtual ~CallbackBase() = 0; 47 | virtual ReturnT operator()(Param1T, Param2T, Param3T) = 0; 48 | }; 49 | 50 | template 51 | DRAMSim::CallbackBase::~CallbackBase() {} 52 | 53 | template 55 | class Callback: public CallbackBase 56 | { 57 | private: 58 | typedef ReturnT (ConsumerT::*PtrMember)(Param1T,Param2T,Param3T); 59 | 60 | public: 61 | Callback( ConsumerT* const object, PtrMember member) : 62 | object(object), member(member) 63 | { 64 | } 65 | 66 | Callback( const Callback& e ) : 67 | object(e.object), member(e.member) 68 | { 69 | } 70 | 71 | ReturnT operator()(Param1T param1, Param2T param2, Param3T param3) 72 | { 73 | return (const_cast(object)->*member) 74 | (param1,param2,param3); 75 | } 76 | 77 | private: 78 | 79 | ConsumerT* const object; 80 | const PtrMember member; 81 | }; 82 | 83 | typedef CallbackBase TransactionCompleteCB; 84 | } // namespace DRAMSim 85 | 86 | #endif 87 | -------------------------------------------------------------------------------- /ClockDomain.cpp: -------------------------------------------------------------------------------- 1 | #include "ClockDomain.h" 2 | 3 | using namespace std; 4 | 5 | 6 | 7 | namespace ClockDomain 8 | { 9 | // "Default" crosser with a 1:1 ratio 10 | ClockDomainCrosser::ClockDomainCrosser(ClockUpdateCB *_callback) 11 | : callback(_callback), clock1(1UL), clock2(1UL), counter1(0UL), counter2(0UL) 12 | { 13 | } 14 | ClockDomainCrosser::ClockDomainCrosser(uint64_t _clock1, uint64_t _clock2, ClockUpdateCB *_callback) 15 | : callback(_callback), clock1(_clock1), clock2(_clock2), counter1(0), counter2(0) 16 | { 17 | //cout << "CTOR: callback address: " << (uint64_t)(this->callback) << "\t ratio="<= 0.5 ? ceil(tmp) : floor(tmp); // ghetto implementation of a rounding function 49 | //printf("i=%lu, z=%20f n=%5u d=%5u\n",i,zs[i],ns[i],ds[i]); 50 | } 51 | 52 | //printf("APPROXIMATION= %u/%d\n",ns[i],ds[i]); 53 | this->clock1=ns[i]; 54 | this->clock2=ds[i]; 55 | 56 | //cout << "CTOR: callback address: " << (uint64_t)(this->callback) << "\t ratio="<(this, &TestObj::cb); 100 | 101 | //ClockDomainCrosser x(5,2,&cb); 102 | //ClockDomainCrosser x(2,5,NULL); 103 | //ClockDomainCrosser x(37,41,NULL); 104 | //ClockDomainCrosser x(41,37,NULL); 105 | //cout << "(main) callback address: " << (uint64_t)&cb << endl; 106 | ClockDomainCrosser x(0.5, callback); 107 | cout <<"------------------------------------------\n"; 108 | ClockDomainCrosser y(0.3333, callback); 109 | cout <<"------------------------------------------\n"; 110 | ClockDomainCrosser z(0.9, callback); 111 | cout <<"------------------------------------------\n"; 112 | 113 | 114 | for (int i=0; i<10; i++) 115 | { 116 | 117 | x.update(); 118 | cout << "UPDATE: counter1= " << x.counter1 << "; counter2= " << x.counter2 << "; " << endl; 119 | } 120 | 121 | return 0; 122 | } 123 | 124 | 125 | } 126 | -------------------------------------------------------------------------------- /ClockDomain.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | #include 5 | 6 | namespace ClockDomain 7 | { 8 | 9 | template 10 | class CallbackBase 11 | { 12 | public: 13 | virtual ReturnT operator()() = 0; 14 | }; 15 | 16 | 17 | template 18 | class Callback: public CallbackBase 19 | { 20 | private: 21 | typedef ReturnT (ConsumerT::*PtrMember)(); 22 | 23 | public: 24 | Callback(ConsumerT* const object, PtrMember member) : object(object), member(member) {} 25 | 26 | Callback(const Callback &e) : object(e.object), member(e.member) {} 27 | 28 | ReturnT operator()() 29 | { 30 | return (const_cast(object)->*member)(); 31 | } 32 | 33 | private: 34 | ConsumerT* const object; 35 | const PtrMember member; 36 | }; 37 | 38 | typedef CallbackBase ClockUpdateCB; 39 | 40 | 41 | class ClockDomainCrosser 42 | { 43 | public: 44 | ClockUpdateCB *callback; 45 | uint64_t clock1, clock2; 46 | uint64_t counter1, counter2; 47 | ClockDomainCrosser(ClockUpdateCB *_callback); 48 | ClockDomainCrosser(uint64_t _clock1, uint64_t _clock2, ClockUpdateCB *_callback); 49 | ClockDomainCrosser(double ratio, ClockUpdateCB *_callback); 50 | void update(); 51 | }; 52 | 53 | 54 | class TestObj 55 | { 56 | public: 57 | TestObj() {} 58 | void cb(); 59 | int test(); 60 | }; 61 | } 62 | -------------------------------------------------------------------------------- /CommandQueue.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | 36 | #ifndef CMDQUEUE_H 37 | #define CMDQUEUE_H 38 | 39 | //CommandQueue.h 40 | // 41 | //Header 42 | // 43 | 44 | #include "BusPacket.h" 45 | #include "BankState.h" 46 | #include "Transaction.h" 47 | #include "SystemConfiguration.h" 48 | #include "SimulatorObject.h" 49 | 50 | using namespace std; 51 | 52 | namespace DRAMSim 53 | { 54 | class CommandQueue : public SimulatorObject 55 | { 56 | CommandQueue(); 57 | ostream &dramsim_log; 58 | public: 59 | //typedefs 60 | typedef vector BusPacket1D; 61 | typedef vector BusPacket2D; 62 | typedef vector BusPacket3D; 63 | 64 | //functions 65 | CommandQueue(vector< vector > &states, ostream &dramsim_log); 66 | virtual ~CommandQueue(); 67 | 68 | void enqueue(BusPacket *newBusPacket); 69 | bool pop(BusPacket **busPacket); 70 | bool hasRoomFor(unsigned numberToEnqueue, unsigned rank, unsigned bank); 71 | bool isIssuable(BusPacket *busPacket); 72 | bool isEmpty(unsigned rank); 73 | void needRefresh(unsigned rank); 74 | void print(); 75 | void update(); //SimulatorObject requirement 76 | vector &getCommandQueue(unsigned rank, unsigned bank); 77 | 78 | //fields 79 | 80 | BusPacket3D queues; // 3D array of BusPacket pointers 81 | vector< vector > &bankStates; 82 | private: 83 | void nextRankAndBank(unsigned &rank, unsigned &bank); 84 | //fields 85 | unsigned nextBank; 86 | unsigned nextRank; 87 | 88 | unsigned nextBankPRE; 89 | unsigned nextRankPRE; 90 | 91 | unsigned refreshRank; 92 | bool refreshWaiting; 93 | 94 | vector< vector > tFAWCountdown; 95 | vector< vector > rowAccessCounters; 96 | 97 | bool sendAct; 98 | }; 99 | } 100 | 101 | #endif 102 | 103 | -------------------------------------------------------------------------------- /DRAMSim.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | #ifndef DRAMSIM_H 33 | #define DRAMSIM_H 34 | /* 35 | * This is a public header for DRAMSim including this along with libdramsim.so should 36 | * provide all necessary functionality to talk to an external simulator 37 | */ 38 | #include "Callback.h" 39 | #include 40 | using std::string; 41 | 42 | namespace DRAMSim 43 | { 44 | 45 | class MultiChannelMemorySystem { 46 | public: 47 | bool addTransaction(bool isWrite, uint64_t addr); 48 | void setCPUClockSpeed(uint64_t cpuClkFreqHz); 49 | void update(); 50 | void printStats(bool finalStats); 51 | bool willAcceptTransaction(); 52 | bool willAcceptTransaction(uint64_t addr); 53 | std::ostream &getLogFile(); 54 | 55 | void RegisterCallbacks( 56 | TransactionCompleteCB *readDone, 57 | TransactionCompleteCB *writeDone, 58 | void (*reportPower)(double bgpower, double burstpower, double refreshpower, double actprepower)); 59 | int getIniBool(const std::string &field, bool *val); 60 | int getIniUint(const std::string &field, unsigned int *val); 61 | int getIniUint64(const std::string &field, uint64_t *val); 62 | int getIniFloat(const std::string &field, float *val); 63 | }; 64 | MultiChannelMemorySystem *getMemorySystemInstance(const string &dev, const string &sys, const string &pwd, const string &trc, unsigned megsOfMemory, std::string *visfilename=NULL); 65 | } 66 | 67 | #endif 68 | -------------------------------------------------------------------------------- /IniReader.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | #ifndef INIREADER_H 32 | #define INIREADER_H 33 | 34 | #include 35 | #include 36 | #include 37 | #include 38 | #include 39 | #include "SystemConfiguration.h" 40 | 41 | using namespace std; 42 | 43 | #define DEFINE_UINT_PARAM(name, paramtype) {#name, &name, UINT, paramtype, false} 44 | #define DEFINE_STRING_PARAM(name, paramtype) {#name, &name, STRING, paramtype, false} 45 | #define DEFINE_FLOAT_PARAM(name,paramtype) {#name, &name, FLOAT, paramtype, false} 46 | #define DEFINE_BOOL_PARAM(name, paramtype) {#name, &name, BOOL, paramtype, false} 47 | #define DEFINE_UINT64_PARAM(name, paramtype) {#name, &name, UINT64, paramtype, false} 48 | 49 | namespace DRAMSim 50 | { 51 | 52 | typedef enum _variableType {STRING, UINT, UINT64, FLOAT, BOOL} varType; 53 | typedef enum _paramType {SYS_PARAM, DEV_PARAM} paramType; 54 | typedef struct _configMap 55 | { 56 | string iniKey; //for example "tRCD" 57 | 58 | void *variablePtr; 59 | varType variableType; 60 | paramType parameterType; 61 | bool wasSet; 62 | } ConfigMap; 63 | 64 | class IniReader 65 | { 66 | 67 | public: 68 | typedef std::map OverrideMap; 69 | typedef OverrideMap::const_iterator OverrideIterator; 70 | 71 | static void SetKey(string key, string value, bool isSystemParam = false, size_t lineNumber = 0); 72 | static void OverrideKeys(const OverrideMap *map); 73 | static void ReadIniFile(string filename, bool isSystemParam); 74 | static void InitEnumsFromStrings(); 75 | static bool CheckIfAllSet(); 76 | static void WriteValuesOut(std::ofstream &visDataOut); 77 | static int getBool(const std::string &field, bool *val); 78 | static int getUint(const std::string &field, unsigned int *val); 79 | static int getUint64(const std::string &field, uint64_t *val); 80 | static int getFloat(const std::string &field, float *val); 81 | 82 | private: 83 | static void WriteParams(std::ofstream &visDataOut, paramType t); 84 | static void Trim(string &str); 85 | }; 86 | } 87 | 88 | 89 | #endif 90 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | CXXFLAGS=-DNO_STORAGE -Wall -DDEBUG_BUILD 2 | OPTFLAGS=-O3 3 | 4 | 5 | ifdef DEBUG 6 | ifeq ($(DEBUG), 1) 7 | OPTFLAGS= -O0 -g 8 | endif 9 | endif 10 | CXXFLAGS+=$(OPTFLAGS) 11 | 12 | EXE_NAME=DRAMSim 13 | STATIC_LIB_NAME := libdramsim.a 14 | LIB_NAME=libdramsim.so 15 | LIB_NAME_MACOS=libdramsim.dylib 16 | 17 | SRC = $(wildcard *.cpp) 18 | OBJ = $(addsuffix .o, $(basename $(SRC))) 19 | 20 | LIB_SRC := $(filter-out TraceBasedSim.cpp,$(SRC)) 21 | LIB_OBJ := $(addsuffix .o, $(basename $(LIB_SRC))) 22 | 23 | #build portable objects (i.e. with -fPIC) 24 | POBJ = $(addsuffix .po, $(basename $(LIB_SRC))) 25 | 26 | REBUILDABLES=$(OBJ) ${POBJ} $(EXE_NAME) $(LIB_NAME) $(STATIC_LIB_NAME) 27 | 28 | all: ${EXE_NAME} 29 | 30 | # $@ target name, $^ target deps, $< matched pattern 31 | $(EXE_NAME): $(OBJ) 32 | $(CXX) $(CXXFLAGS) -o $@ $^ 33 | @echo "Built $@ successfully" 34 | 35 | $(LIB_NAME): $(POBJ) 36 | g++ -g -shared -Wl,-soname,$@ -o $@ $^ 37 | @echo "Built $@ successfully" 38 | 39 | $(STATIC_LIB_NAME): $(LIB_OBJ) 40 | $(AR) crs $@ $^ 41 | 42 | $(LIB_NAME_MACOS): $(POBJ) 43 | g++ -dynamiclib -o $@ $^ 44 | @echo "Built $@ successfully" 45 | 46 | #include the autogenerated dependency files for each .o file 47 | -include $(OBJ:.o=.dep) 48 | -include $(POBJ:.po=.deppo) 49 | 50 | # build dependency list via gcc -M and save to a .dep file 51 | %.dep : %.cpp 52 | @$(CXX) -M $(CXXFLAGS) $< > $@ 53 | 54 | %.deppo : %.cpp 55 | @$(CXX) -M $(CXXFLAGS) -MT"$*.po" $< > $@ 56 | 57 | # build all .cpp files to .o files 58 | %.o : %.cpp 59 | g++ $(CXXFLAGS) -o $@ -c $< 60 | 61 | #po = portable object .. for lack of a better term 62 | %.po : %.cpp 63 | g++ $(CXXFLAGS) -DLOG_OUTPUT -fPIC -o $@ -c $< 64 | 65 | clean: 66 | -rm -f $(REBUILDABLES) *.dep *.deppo 67 | -------------------------------------------------------------------------------- /MemoryController.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | #ifndef MEMORYCONTROLLER_H 33 | #define MEMORYCONTROLLER_H 34 | 35 | //MemoryController.h 36 | // 37 | //Header file for memory controller object 38 | // 39 | 40 | #include "SimulatorObject.h" 41 | #include "Transaction.h" 42 | #include "SystemConfiguration.h" 43 | #include "CommandQueue.h" 44 | #include "BusPacket.h" 45 | #include "BankState.h" 46 | #include "Rank.h" 47 | #include "CSVWriter.h" 48 | #include 49 | 50 | using namespace std; 51 | 52 | namespace DRAMSim 53 | { 54 | class MemorySystem; 55 | class MemoryController : public SimulatorObject 56 | { 57 | 58 | public: 59 | //functions 60 | MemoryController(MemorySystem* ms, CSVWriter &csvOut_, ostream &dramsim_log_); 61 | virtual ~MemoryController(); 62 | 63 | bool addTransaction(Transaction *trans); 64 | bool WillAcceptTransaction(); 65 | void returnReadData(const Transaction *trans); 66 | void receiveFromBus(BusPacket *bpacket); 67 | void attachRanks(vector *ranks); 68 | void update(); 69 | void printStats(bool finalStats = false); 70 | void resetStats(); 71 | 72 | 73 | //fields 74 | vector transactionQueue; 75 | private: 76 | ostream &dramsim_log; 77 | vector< vector > bankStates; 78 | //functions 79 | void insertHistogram(unsigned latencyValue, unsigned rank, unsigned bank); 80 | 81 | //fields 82 | MemorySystem *parentMemorySystem; 83 | 84 | CommandQueue commandQueue; 85 | BusPacket *poppedBusPacket; 86 | vectorrefreshCountdown; 87 | vector writeDataToSend; 88 | vector writeDataCountdown; 89 | vector returnTransaction; 90 | vector pendingReadTransactions; 91 | map latencies; // latencyValue -> latencyCount 92 | vector powerDown; 93 | 94 | vector *ranks; 95 | 96 | //output file 97 | CSVWriter &csvOut; 98 | 99 | // these packets are counting down waiting to be transmitted on the "bus" 100 | BusPacket *outgoingCmdPacket; 101 | unsigned cmdCyclesLeft; 102 | BusPacket *outgoingDataPacket; 103 | unsigned dataCyclesLeft; 104 | 105 | uint64_t totalTransactions; 106 | vector grandTotalBankAccesses; 107 | vector totalReadsPerBank; 108 | vector totalWritesPerBank; 109 | 110 | vector totalReadsPerRank; 111 | vector totalWritesPerRank; 112 | 113 | 114 | vector< uint64_t > totalEpochLatency; 115 | 116 | unsigned channelBitWidth; 117 | unsigned rankBitWidth; 118 | unsigned bankBitWidth; 119 | unsigned rowBitWidth; 120 | unsigned colBitWidth; 121 | unsigned byteOffsetWidth; 122 | 123 | 124 | unsigned refreshRank; 125 | 126 | public: 127 | // energy values are per rank -- SST uses these directly, so make these public 128 | vector< uint64_t > backgroundEnergy; 129 | vector< uint64_t > burstEnergy; 130 | vector< uint64_t > actpreEnergy; 131 | vector< uint64_t > refreshEnergy; 132 | 133 | }; 134 | } 135 | 136 | #endif 137 | 138 | -------------------------------------------------------------------------------- /MemorySystem.cpp: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | //MemorySystem.cpp 35 | // 36 | //Class file for JEDEC memory system wrapper 37 | // 38 | 39 | #include "MemorySystem.h" 40 | #include "IniReader.h" 41 | #include 42 | 43 | using namespace std; 44 | 45 | 46 | ofstream cmd_verify_out; //used in Rank.cpp and MemoryController.cpp if VERIFICATION_OUTPUT is set 47 | 48 | unsigned NUM_DEVICES; 49 | unsigned NUM_RANKS; 50 | unsigned NUM_RANKS_LOG; 51 | 52 | namespace DRAMSim { 53 | 54 | powerCallBack_t MemorySystem::ReportPower = NULL; 55 | 56 | MemorySystem::MemorySystem(unsigned id, unsigned int megsOfMemory, CSVWriter &csvOut_, ostream &dramsim_log_) : 57 | dramsim_log(dramsim_log_), 58 | ReturnReadData(NULL), 59 | WriteDataDone(NULL), 60 | systemID(id), 61 | csvOut(csvOut_) 62 | { 63 | currentClockCycle = 0; 64 | 65 | DEBUG("===== MemorySystem "<1 will be valid). 82 | 83 | However, users don't care (or know) about ranks, they care about total 84 | storage, so maybe it's better to let them choose and just throw an error 85 | if they choose something invalid. 86 | 87 | A bit of background: 88 | 89 | Each column contains DEVICE_WIDTH bits. A row contains NUM_COLS columns. 90 | Each bank contains NUM_ROWS rows. Therefore, the total storage per DRAM device is: 91 | PER_DEVICE_STORAGE = NUM_ROWS*NUM_COLS*DEVICE_WIDTH*NUM_BANKS (in bits) 92 | 93 | A rank *must* have a 64 bit output bus (JEDEC standard), so each rank must have: 94 | NUM_DEVICES_PER_RANK = 64/DEVICE_WIDTH 95 | (note: if you have multiple channels ganged together, the bus width is 96 | effectively NUM_CHANS * 64/DEVICE_WIDTH) 97 | 98 | If we multiply these two numbers to get the storage per rank (in bits), we get: 99 | PER_RANK_STORAGE = PER_DEVICE_STORAGE*NUM_DEVICES_PER_RANK = NUM_ROWS*NUM_COLS*NUM_BANKS*64 100 | 101 | Finally, to get TOTAL_STORAGE, we need to multiply by NUM_RANKS 102 | TOTAL_STORAGE = PER_RANK_STORAGE*NUM_RANKS (total storage in bits) 103 | 104 | So one could compute this in reverse -- compute NUM_DEVICES, 105 | PER_DEVICE_STORAGE, and PER_RANK_STORAGE first since all these parameters 106 | are set by the device ini. Then, TOTAL_STORAGE/PER_RANK_STORAGE = NUM_RANKS 107 | 108 | The only way this could run into problems is if TOTAL_STORAGE < PER_RANK_STORAGE, 109 | which could happen for very dense parts. 110 | *********************/ 111 | 112 | // number of bytes per rank 113 | unsigned long megsOfStoragePerRank = ((((long long)NUM_ROWS * (NUM_COLS * DEVICE_WIDTH) * NUM_BANKS) * ((long long)JEDEC_DATA_BUS_BITS / DEVICE_WIDTH)) / 8) >> 20; 114 | 115 | // If this is set, effectively override the number of ranks 116 | if (megsOfMemory != 0) 117 | { 118 | NUM_RANKS = megsOfMemory / megsOfStoragePerRank; 119 | NUM_RANKS_LOG = dramsim_log2(NUM_RANKS); 120 | if (NUM_RANKS == 0) 121 | { 122 | PRINT("WARNING: Cannot create memory system with "<(); 137 | 138 | for (size_t i=0; isetId(i); 142 | r->attachMemoryController(memoryController); 143 | ranks->push_back(r); 144 | } 145 | 146 | memoryController->attachRanks(ranks); 147 | 148 | } 149 | 150 | 151 | 152 | MemorySystem::~MemorySystem() 153 | { 154 | /* the MemorySystem should exist for all time, nothing should be destroying it */ 155 | // ERROR("MEMORY SYSTEM DESTRUCTOR with ID "<clear(); 165 | delete(ranks); 166 | 167 | if (VERIFICATION_OUTPUT) 168 | { 169 | cmd_verify_out.flush(); 170 | cmd_verify_out.close(); 171 | } 172 | } 173 | 174 | bool MemorySystem::WillAcceptTransaction() 175 | { 176 | return memoryController->WillAcceptTransaction(); 177 | } 178 | 179 | bool MemorySystem::addTransaction(bool isWrite, uint64_t addr) 180 | { 181 | TransactionType type = isWrite ? DATA_WRITE : DATA_READ; 182 | Transaction *trans = new Transaction(type,addr,NULL); 183 | // push_back in memoryController will make a copy of this during 184 | // addTransaction so it's kosher for the reference to be local 185 | 186 | if (memoryController->WillAcceptTransaction()) 187 | { 188 | return memoryController->addTransaction(trans); 189 | } 190 | else 191 | { 192 | pendingTransactions.push_back(trans); 193 | return true; 194 | } 195 | } 196 | 197 | bool MemorySystem::addTransaction(Transaction *trans) 198 | { 199 | return memoryController->addTransaction(trans); 200 | } 201 | 202 | //prints statistics 203 | void MemorySystem::printStats(bool finalStats) 204 | { 205 | memoryController->printStats(finalStats); 206 | } 207 | 208 | 209 | //update the memory systems state 210 | void MemorySystem::update() 211 | { 212 | 213 | //PRINT(" ----------------- Memory System Update ------------------"); 214 | 215 | //updates the state of each of the objects 216 | // NOTE - do not change order 217 | for (size_t i=0;iupdate(); 220 | } 221 | 222 | //pendingTransactions will only have stuff in it if MARSS is adding stuff 223 | if (pendingTransactions.size() > 0 && memoryController->WillAcceptTransaction()) 224 | { 225 | memoryController->addTransaction(pendingTransactions.front()); 226 | pendingTransactions.pop_front(); 227 | } 228 | memoryController->update(); 229 | 230 | //simply increments the currentClockCycle field for each object 231 | for (size_t i=0;istep(); 234 | } 235 | memoryController->step(); 236 | this->step(); 237 | 238 | //PRINT("\n"); // two new lines 239 | } 240 | 241 | void MemorySystem::RegisterCallbacks( Callback_t* readCB, Callback_t* writeCB, 242 | void (*reportPower)(double bgpower, double burstpower, 243 | double refreshpower, double actprepower)) 244 | { 245 | ReturnReadData = readCB; 246 | WriteDataDone = writeCB; 247 | ReportPower = reportPower; 248 | } 249 | 250 | } /*namespace DRAMSim */ 251 | 252 | 253 | 254 | // This function can be used by autoconf AC_CHECK_LIB since 255 | // apparently it can't detect C++ functions. 256 | // Basically just an entry in the symbol table 257 | extern "C" 258 | { 259 | void libdramsim_is_present(void) 260 | { 261 | ; 262 | } 263 | } 264 | 265 | -------------------------------------------------------------------------------- /MemorySystem.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | #ifndef MEMORYSYSTEM_H 34 | #define MEMORYSYSTEM_H 35 | 36 | //MemorySystem.h 37 | // 38 | //Header file for JEDEC memory system wrapper 39 | // 40 | 41 | #include "SimulatorObject.h" 42 | #include "SystemConfiguration.h" 43 | #include "MemoryController.h" 44 | #include "Rank.h" 45 | #include "Transaction.h" 46 | #include "Callback.h" 47 | #include "CSVWriter.h" 48 | #include 49 | 50 | namespace DRAMSim 51 | { 52 | typedef CallbackBase Callback_t; 53 | class MemorySystem : public SimulatorObject 54 | { 55 | ostream &dramsim_log; 56 | public: 57 | //functions 58 | MemorySystem(unsigned id, unsigned megsOfMemory, CSVWriter &csvOut_, ostream &dramsim_log_); 59 | virtual ~MemorySystem(); 60 | void update(); 61 | bool addTransaction(Transaction *trans); 62 | bool addTransaction(bool isWrite, uint64_t addr); 63 | void printStats(bool finalStats); 64 | bool WillAcceptTransaction(); 65 | void RegisterCallbacks( 66 | Callback_t *readDone, 67 | Callback_t *writeDone, 68 | void (*reportPower)(double bgpower, double burstpower, double refreshpower, double actprepower)); 69 | 70 | //fields 71 | MemoryController *memoryController; 72 | vector *ranks; 73 | deque pendingTransactions; 74 | 75 | 76 | //function pointers 77 | Callback_t* ReturnReadData; 78 | Callback_t* WriteDataDone; 79 | //TODO: make this a functor as well? 80 | static powerCallBack_t ReportPower; 81 | unsigned systemID; 82 | 83 | private: 84 | CSVWriter &csvOut; 85 | }; 86 | } 87 | 88 | #endif 89 | 90 | -------------------------------------------------------------------------------- /MultiChannelMemorySystem.cpp: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | #include 31 | #include //stringstream 32 | #include // getenv() 33 | // for directory operations 34 | #include 35 | #include 36 | 37 | #include "MultiChannelMemorySystem.h" 38 | #include "AddressMapping.h" 39 | #include "IniReader.h" 40 | 41 | 42 | 43 | using namespace DRAMSim; 44 | 45 | 46 | MultiChannelMemorySystem::MultiChannelMemorySystem(const string &deviceIniFilename_, const string &systemIniFilename_, const string &pwd_, const string &traceFilename_, unsigned megsOfMemory_, string *visFilename_, const IniReader::OverrideMap *paramOverrides) 47 | :megsOfMemory(megsOfMemory_), deviceIniFilename(deviceIniFilename_), 48 | systemIniFilename(systemIniFilename_), traceFilename(traceFilename_), 49 | pwd(pwd_), visFilename(visFilename_), 50 | clockDomainCrosser(new ClockDomain::Callback(this, &MultiChannelMemorySystem::actual_update)), 51 | csvOut(new CSVWriter(visDataOut)) 52 | { 53 | currentClockCycle=0; 54 | if (visFilename) 55 | printf("CC VISFILENAME=%s\n",visFilename->c_str()); 56 | 57 | if (!isPowerOfTwo(megsOfMemory)) 58 | { 59 | ERROR("Please specify a power of 2 memory size"); 60 | abort(); 61 | } 62 | 63 | if (pwd.length() > 0) 64 | { 65 | //ignore the pwd argument if the argument is an absolute path 66 | if (deviceIniFilename[0] != '/') 67 | { 68 | deviceIniFilename = pwd + "/" + deviceIniFilename; 69 | } 70 | 71 | if (systemIniFilename[0] != '/') 72 | { 73 | systemIniFilename = pwd + "/" + systemIniFilename; 74 | } 75 | } 76 | 77 | DEBUG("== Loading device model file '"< 0) 236 | { 237 | path = pwd + "/" + path; 238 | } 239 | 240 | // create the directories if they don't exist 241 | mkdirIfNotExist(path); 242 | path = path + traceFilename + "/"; 243 | mkdirIfNotExist(path); 244 | path = path + deviceName + "/"; 245 | mkdirIfNotExist(path); 246 | 247 | // finally, figure out the filename 248 | string sched = "BtR"; 249 | string queue = "pRank"; 250 | if (schedulingPolicy == RankThenBankRoundRobin) 251 | { 252 | sched = "RtB"; 253 | } 254 | if (queuingStructure == PerRankPerBank) 255 | { 256 | queue = "pRankpBank"; 257 | } 258 | 259 | /* I really don't see how "the C++ way" is better than snprintf() */ 260 | out << (TOTAL_STORAGE>>10) << "GB." << NUM_CHANS << "Ch." << NUM_RANKS <<"R." <printStats(false); 388 | } 389 | csvOut->finalize(); 390 | } 391 | 392 | for (size_t i=0; iupdate(); 395 | } 396 | 397 | 398 | currentClockCycle++; 399 | } 400 | unsigned MultiChannelMemorySystem::findChannelNumber(uint64_t addr) 401 | { 402 | // Single channel case is a trivial shortcut case 403 | if (NUM_CHANS == 1) 404 | { 405 | return 0; 406 | } 407 | 408 | if (!isPowerOfTwo(NUM_CHANS)) 409 | { 410 | ERROR("We can only support power of two # of channels.\n" << 411 | "I don't know what Intel was thinking, but trying to address map half a bit is a neat trick that we're not sure how to do"); 412 | abort(); 413 | } 414 | 415 | // only chan is used from this set 416 | unsigned channelNumber,rank,bank,row,col; 417 | addressMapping(addr, channelNumber, rank, bank, row, col); 418 | if (channelNumber >= NUM_CHANS) 419 | { 420 | ERROR("Got channel index "<printStats(finalStats); 486 | PRINT("//// Channel ["<finalize(); 489 | } 490 | void MultiChannelMemorySystem::RegisterCallbacks( 491 | TransactionCompleteCB *readDone, 492 | TransactionCompleteCB *writeDone, 493 | void (*reportPower)(double bgpower, double burstpower, double refreshpower, double actprepower)) 494 | { 495 | for (size_t i=0; iRegisterCallbacks(readDone, writeDone, reportPower); 498 | } 499 | } 500 | 501 | /* 502 | * The getters below are useful to external simulators interfacing with DRAMSim 503 | * 504 | * Return value: 0 on success, -1 on error 505 | */ 506 | int MultiChannelMemorySystem::getIniBool(const std::string& field, bool *val) 507 | { 508 | if (!IniReader::CheckIfAllSet()) 509 | exit(-1); 510 | return IniReader::getBool(field, val); 511 | } 512 | 513 | int MultiChannelMemorySystem::getIniUint(const std::string& field, unsigned int *val) 514 | { 515 | if (!IniReader::CheckIfAllSet()) 516 | exit(-1); 517 | return IniReader::getUint(field, val); 518 | } 519 | 520 | int MultiChannelMemorySystem::getIniUint64(const std::string& field, uint64_t *val) 521 | { 522 | if (!IniReader::CheckIfAllSet()) 523 | exit(-1); 524 | return IniReader::getUint64(field, val); 525 | } 526 | 527 | int MultiChannelMemorySystem::getIniFloat(const std::string& field, float *val) 528 | { 529 | if (!IniReader::CheckIfAllSet()) 530 | exit(-1); 531 | return IniReader::getFloat(field, val); 532 | } 533 | 534 | namespace DRAMSim { 535 | MultiChannelMemorySystem *getMemorySystemInstance(const string &dev, const string &sys, const string &pwd, const string &trc, unsigned megsOfMemory, string *visfilename) 536 | { 537 | return new MultiChannelMemorySystem(dev, sys, pwd, trc, megsOfMemory, visfilename); 538 | } 539 | } 540 | -------------------------------------------------------------------------------- /MultiChannelMemorySystem.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | #include "SimulatorObject.h" 31 | #include "Transaction.h" 32 | #include "SystemConfiguration.h" 33 | #include "MemorySystem.h" 34 | #include "IniReader.h" 35 | #include "ClockDomain.h" 36 | #include "CSVWriter.h" 37 | 38 | 39 | namespace DRAMSim { 40 | 41 | 42 | class MultiChannelMemorySystem : public SimulatorObject 43 | { 44 | public: 45 | 46 | MultiChannelMemorySystem(const string &dev, const string &sys, const string &pwd, const string &trc, unsigned megsOfMemory, string *visFilename=NULL, const IniReader::OverrideMap *paramOverrides=NULL); 47 | virtual ~MultiChannelMemorySystem(); 48 | bool addTransaction(Transaction *trans); 49 | bool addTransaction(const Transaction &trans); 50 | bool addTransaction(bool isWrite, uint64_t addr); 51 | bool willAcceptTransaction(); 52 | bool willAcceptTransaction(uint64_t addr); 53 | void update(); 54 | void printStats(bool finalStats=false); 55 | ostream &getLogFile(); 56 | void RegisterCallbacks( 57 | TransactionCompleteCB *readDone, 58 | TransactionCompleteCB *writeDone, 59 | void (*reportPower)(double bgpower, double burstpower, double refreshpower, double actprepower)); 60 | int getIniBool(const std::string &field, bool *val); 61 | int getIniUint(const std::string &field, unsigned int *val); 62 | int getIniUint64(const std::string &field, uint64_t *val); 63 | int getIniFloat(const std::string &field, float *val); 64 | 65 | void InitOutputFiles(string tracefilename); 66 | void setCPUClockSpeed(uint64_t cpuClkFreqHz); 67 | 68 | //output file 69 | std::ofstream visDataOut; 70 | ofstream dramsim_log; 71 | 72 | private: 73 | unsigned findChannelNumber(uint64_t addr); 74 | void actual_update(); 75 | vector channels; 76 | unsigned megsOfMemory; 77 | string deviceIniFilename; 78 | string systemIniFilename; 79 | string traceFilename; 80 | string pwd; 81 | string *visFilename; 82 | ClockDomain::ClockDomainCrosser clockDomainCrosser; 83 | static void mkdirIfNotExist(string path); 84 | static bool fileExists(string path); 85 | CSVWriter *csvOut; 86 | 87 | 88 | }; 89 | } 90 | -------------------------------------------------------------------------------- /PrintMacros.cpp: -------------------------------------------------------------------------------- 1 | #include "PrintMacros.h" 2 | 3 | /* 4 | * Enable or disable PRINT() statements. 5 | * 6 | * Set by flag in TraceBasedSim.cpp when compiling standalone DRAMSim tool. 7 | * 8 | * The DRAMSim libraries do not include the TraceBasedSim object and thus 9 | * library users can optionally override the weak definition below. 10 | */ 11 | int __attribute__((weak)) SHOW_SIM_OUTPUT = false; 12 | -------------------------------------------------------------------------------- /PrintMacros.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | #ifndef PRINT_MACROS_H 36 | #define PRINT_MACROS_H 37 | 38 | #include 39 | 40 | extern int SHOW_SIM_OUTPUT; 41 | 42 | #define ERROR(str) std::cerr<<"[ERROR ("<<__FILE__<<":"<<__LINE__<<")]: "<id = id; 65 | } 66 | 67 | // attachMemoryController() must be called before any other Rank functions 68 | // are called 69 | void Rank::attachMemoryController(MemoryController *memoryController) 70 | { 71 | this->memoryController = memoryController; 72 | } 73 | Rank::~Rank() 74 | { 75 | for (size_t i=0; iid << " Receiving On Bus : "); 87 | packet->print(); 88 | } 89 | if (VERIFICATION_OUTPUT) 90 | { 91 | packet->print(currentClockCycle,false); 92 | } 93 | 94 | switch (packet->busPacketType) 95 | { 96 | case READ: 97 | //make sure a read is allowed 98 | if (bankStates[packet->bank].currentBankState != RowActive || 99 | currentClockCycle < bankStates[packet->bank].nextRead || 100 | packet->row != bankStates[packet->bank].openRowAddress) 101 | { 102 | packet->print(); 103 | ERROR("== Error - Rank " << id << " received a READ when not allowed"); 104 | exit(0); 105 | } 106 | 107 | //update state table 108 | bankStates[packet->bank].nextPrecharge = max(bankStates[packet->bank].nextPrecharge, currentClockCycle + READ_TO_PRE_DELAY); 109 | for (size_t i=0;ibank].read(packet); 118 | #else 119 | packet->busPacketType = DATA; 120 | #endif 121 | readReturnPacket.push_back(packet); 122 | readReturnCountdown.push_back(RL); 123 | break; 124 | case READ_P: 125 | //make sure a read is allowed 126 | if (bankStates[packet->bank].currentBankState != RowActive || 127 | currentClockCycle < bankStates[packet->bank].nextRead || 128 | packet->row != bankStates[packet->bank].openRowAddress) 129 | { 130 | ERROR("== Error - Rank " << id << " received a READ_P when not allowed"); 131 | exit(-1); 132 | } 133 | 134 | //update state table 135 | bankStates[packet->bank].currentBankState = Idle; 136 | bankStates[packet->bank].nextActivate = max(bankStates[packet->bank].nextActivate, currentClockCycle + READ_AUTOPRE_DELAY); 137 | for (size_t i=0;ibank].read(packet); 147 | #else 148 | packet->busPacketType = DATA; 149 | #endif 150 | 151 | readReturnPacket.push_back(packet); 152 | readReturnCountdown.push_back(RL); 153 | break; 154 | case WRITE: 155 | //make sure a write is allowed 156 | if (bankStates[packet->bank].currentBankState != RowActive || 157 | currentClockCycle < bankStates[packet->bank].nextWrite || 158 | packet->row != bankStates[packet->bank].openRowAddress) 159 | { 160 | ERROR("== Error - Rank " << id << " received a WRITE when not allowed"); 161 | bankStates[packet->bank].print(); 162 | exit(0); 163 | } 164 | 165 | //update state table 166 | bankStates[packet->bank].nextPrecharge = max(bankStates[packet->bank].nextPrecharge, currentClockCycle + WRITE_TO_PRE_DELAY); 167 | for (size_t i=0;ibank; 175 | incomingWriteRow = packet->row; 176 | incomingWriteColumn = packet->column; 177 | delete(packet); 178 | break; 179 | case WRITE_P: 180 | //make sure a write is allowed 181 | if (bankStates[packet->bank].currentBankState != RowActive || 182 | currentClockCycle < bankStates[packet->bank].nextWrite || 183 | packet->row != bankStates[packet->bank].openRowAddress) 184 | { 185 | ERROR("== Error - Rank " << id << " received a WRITE_P when not allowed"); 186 | exit(0); 187 | } 188 | 189 | //update state table 190 | bankStates[packet->bank].currentBankState = Idle; 191 | bankStates[packet->bank].nextActivate = max(bankStates[packet->bank].nextActivate, currentClockCycle + WRITE_AUTOPRE_DELAY); 192 | for (size_t i=0;ibank; 200 | incomingWriteRow = packet->row; 201 | incomingWriteColumn = packet->column; 202 | delete(packet); 203 | break; 204 | case ACTIVATE: 205 | //make sure activate is allowed 206 | if (bankStates[packet->bank].currentBankState != Idle || 207 | currentClockCycle < bankStates[packet->bank].nextActivate) 208 | { 209 | ERROR("== Error - Rank " << id << " received an ACT when not allowed"); 210 | packet->print(); 211 | bankStates[packet->bank].print(); 212 | exit(0); 213 | } 214 | 215 | bankStates[packet->bank].currentBankState = RowActive; 216 | bankStates[packet->bank].nextActivate = currentClockCycle + tRC; 217 | bankStates[packet->bank].openRowAddress = packet->row; 218 | 219 | //if AL is greater than one, then posted-cas is enabled - handle accordingly 220 | if (AL>0) 221 | { 222 | bankStates[packet->bank].nextWrite = currentClockCycle + (tRCD-AL); 223 | bankStates[packet->bank].nextRead = currentClockCycle + (tRCD-AL); 224 | } 225 | else 226 | { 227 | bankStates[packet->bank].nextWrite = currentClockCycle + (tRCD-AL); 228 | bankStates[packet->bank].nextRead = currentClockCycle + (tRCD-AL); 229 | } 230 | 231 | bankStates[packet->bank].nextPrecharge = currentClockCycle + tRAS; 232 | for (size_t i=0;ibank) 235 | { 236 | bankStates[i].nextActivate = max(bankStates[i].nextActivate, currentClockCycle + tRRD); 237 | } 238 | } 239 | delete(packet); 240 | break; 241 | case PRECHARGE: 242 | //make sure precharge is allowed 243 | if (bankStates[packet->bank].currentBankState != RowActive || 244 | currentClockCycle < bankStates[packet->bank].nextPrecharge) 245 | { 246 | ERROR("== Error - Rank " << id << " received a PRE when not allowed"); 247 | exit(0); 248 | } 249 | 250 | bankStates[packet->bank].currentBankState = Idle; 251 | bankStates[packet->bank].nextActivate = max(bankStates[packet->bank].nextActivate, currentClockCycle + tRP); 252 | delete(packet); 253 | break; 254 | case REFRESH: 255 | refreshWaiting = false; 256 | for (size_t i=0;ibank != incomingWriteBank || 271 | packet->row != incomingWriteRow || 272 | packet->column != incomingWriteColumn) 273 | { 274 | cout << "== Error - Rank " << id << " received a DATA packet to the wrong place" << endl; 275 | packet->print(); 276 | bankStates[packet->bank].print(); 277 | exit(0); 278 | } 279 | */ 280 | #ifndef NO_STORAGE 281 | banks[packet->bank].write(packet); 282 | #else 283 | // end of the line for the write packet 284 | #endif 285 | delete(packet); 286 | break; 287 | default: 288 | ERROR("== Error - Unknown BusPacketType trying to be sent to Bank"); 289 | exit(0); 290 | break; 291 | } 292 | } 293 | 294 | int Rank::getId() const 295 | { 296 | return this->id; 297 | } 298 | 299 | void Rank::update() 300 | { 301 | 302 | // An outgoing packet is one that is currently sending on the bus 303 | // do the book keeping for the packet's time left on the bus 304 | if (outgoingDataPacket != NULL) 305 | { 306 | dataCyclesLeft--; 307 | if (dataCyclesLeft == 0) 308 | { 309 | //if the packet is done on the bus, call receiveFromBus and free up the bus 310 | memoryController->receiveFromBus(outgoingDataPacket); 311 | outgoingDataPacket = NULL; 312 | } 313 | } 314 | 315 | // decrement the counter for all packets waiting to be sent back 316 | for (size_t i=0;i 0 && readReturnCountdown[0]==0) 323 | { 324 | // RL time has passed since the read was issued; this packet is 325 | // ready to go out on the bus 326 | 327 | outgoingDataPacket = readReturnPacket[0]; 328 | dataCyclesLeft = BL/2; 329 | 330 | // remove the packet from the ranks 331 | readReturnPacket.erase(readReturnPacket.begin()); 332 | readReturnCountdown.erase(readReturnCountdown.begin()); 333 | 334 | if (DEBUG_BUS) 335 | { 336 | PRINTN(" -- R" << this->id << " Issuing On Data Bus : "); 337 | outgoingDataPacket->print(); 338 | PRINT(""); 339 | } 340 | 341 | } 342 | } 343 | 344 | //power down the rank 345 | void Rank::powerDown() 346 | { 347 | //perform checks 348 | for (size_t i=0;i currentClockCycle) 377 | { 378 | ERROR("== Error - Trying to power up rank " << id << " before we're allowed to"); 379 | ERROR(bankStates[i].nextPowerUp << " " << currentClockCycle); 380 | exit(0); 381 | } 382 | bankStates[i].nextActivate = currentClockCycle + tXP; 383 | bankStates[i].currentBankState = Idle; 384 | } 385 | } 386 | -------------------------------------------------------------------------------- /Rank.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | #ifndef RANK_H 35 | #define RANK_H 36 | 37 | #include "SimulatorObject.h" 38 | #include "BusPacket.h" 39 | #include "SystemConfiguration.h" 40 | #include "Bank.h" 41 | #include "BankState.h" 42 | 43 | using namespace std; 44 | using namespace DRAMSim; 45 | 46 | namespace DRAMSim 47 | { 48 | class MemoryController; //forward declaration 49 | class Rank : public SimulatorObject 50 | { 51 | private: 52 | int id; 53 | ostream &dramsim_log; 54 | unsigned incomingWriteBank; 55 | unsigned incomingWriteRow; 56 | unsigned incomingWriteColumn; 57 | bool isPowerDown; 58 | 59 | public: 60 | //functions 61 | Rank(ostream &dramsim_log_); 62 | virtual ~Rank(); 63 | void receiveFromBus(BusPacket *packet); 64 | void attachMemoryController(MemoryController *mc); 65 | int getId() const; 66 | void setId(int id); 67 | void update(); 68 | void powerUp(); 69 | void powerDown(); 70 | 71 | //fields 72 | MemoryController *memoryController; 73 | BusPacket *outgoingDataPacket; 74 | unsigned dataCyclesLeft; 75 | bool refreshWaiting; 76 | 77 | //these are vectors so that each element is per-bank 78 | vector readReturnPacket; 79 | vector readReturnCountdown; 80 | vector banks; 81 | vector bankStates; 82 | 83 | }; 84 | } 85 | #endif 86 | 87 | -------------------------------------------------------------------------------- /SimulatorObject.cpp: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | //SimulatorObject.cpp 39 | // 40 | //Base class for all classes in the simulator 41 | // 42 | 43 | #include 44 | #include "SimulatorObject.h" 45 | 46 | using namespace DRAMSim; 47 | using namespace std; 48 | 49 | void SimulatorObject::step() 50 | { 51 | currentClockCycle++; 52 | } 53 | 54 | 55 | -------------------------------------------------------------------------------- /SimulatorObject.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | #ifndef SIMULATOROBJ_H 39 | #define SIMULATOROBJ_H 40 | 41 | //SimulatorObject.h 42 | // 43 | //Header file for simulator object class 44 | // 45 | 46 | #include 47 | 48 | namespace DRAMSim 49 | { 50 | class SimulatorObject 51 | { 52 | public: 53 | uint64_t currentClockCycle; 54 | 55 | void step(); 56 | virtual void update()=0; 57 | }; 58 | } 59 | 60 | #endif 61 | 62 | -------------------------------------------------------------------------------- /SystemConfiguration.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | #ifndef SYSCONFIG_H 34 | #define SYSCONFIG_H 35 | 36 | #include 37 | #include 38 | #include 39 | #include 40 | #include 41 | #include 42 | #include "PrintMacros.h" 43 | 44 | #ifdef __APPLE__ 45 | #include 46 | #endif 47 | 48 | //SystemConfiguration.h 49 | // 50 | //Configuration values for the current system 51 | 52 | 53 | 54 | //number of latencies per bucket in the latency histogram 55 | //TODO: move to system ini file 56 | #define HISTOGRAM_BIN_SIZE 10 57 | 58 | extern std::ofstream cmd_verify_out; //used by BusPacket.cpp if VERIFICATION_OUTPUT is enabled 59 | //extern std::ofstream visDataOut; 60 | 61 | //TODO: namespace these to DRAMSim:: 62 | extern bool VERIFICATION_OUTPUT; // output suitable to feed to modelsim 63 | 64 | extern bool DEBUG_TRANS_Q; 65 | extern bool DEBUG_CMD_Q; 66 | extern bool DEBUG_ADDR_MAP; 67 | extern bool DEBUG_BANKSTATE; 68 | extern bool DEBUG_BUS; 69 | extern bool DEBUG_BANKS; 70 | extern bool DEBUG_POWER; 71 | extern bool USE_LOW_POWER; 72 | extern bool VIS_FILE_OUTPUT; 73 | 74 | extern uint64_t TOTAL_STORAGE; 75 | extern unsigned NUM_BANKS; 76 | extern unsigned NUM_BANKS_LOG; 77 | extern unsigned NUM_RANKS; 78 | extern unsigned NUM_RANKS_LOG; 79 | extern unsigned NUM_CHANS; 80 | extern unsigned NUM_CHANS_LOG; 81 | extern unsigned NUM_ROWS; 82 | extern unsigned NUM_ROWS_LOG; 83 | extern unsigned NUM_COLS; 84 | extern unsigned NUM_COLS_LOG; 85 | extern unsigned DEVICE_WIDTH; 86 | extern unsigned BYTE_OFFSET_WIDTH; 87 | extern unsigned TRANSACTION_SIZE; 88 | extern unsigned THROW_AWAY_BITS; 89 | extern unsigned COL_LOW_BIT_WIDTH; 90 | 91 | //in nanoseconds 92 | extern unsigned REFRESH_PERIOD; 93 | extern float tCK; 94 | 95 | extern unsigned CL; 96 | extern unsigned AL; 97 | #define RL (CL+AL) 98 | #define WL (RL-1) 99 | extern unsigned BL; 100 | extern unsigned tRAS; 101 | extern unsigned tRCD; 102 | extern unsigned tRRD; 103 | extern unsigned tRC; 104 | extern unsigned tRP; 105 | extern unsigned tCCD; 106 | extern unsigned tRTP; 107 | extern unsigned tWTR; 108 | extern unsigned tWR; 109 | extern unsigned tRTRS; 110 | extern unsigned tRFC; 111 | extern unsigned tFAW; 112 | extern unsigned tCKE; 113 | extern unsigned tXP; 114 | 115 | extern unsigned tCMD; 116 | 117 | /* For power parameters (current and voltage), see externs in MemoryController.cpp */ 118 | 119 | extern unsigned NUM_DEVICES; 120 | 121 | //same bank 122 | #define READ_TO_PRE_DELAY (AL+BL/2+ max(tRTP,tCCD)-tCCD) 123 | #define WRITE_TO_PRE_DELAY (WL+BL/2+tWR) 124 | #define READ_TO_WRITE_DELAY (RL+BL/2+tRTRS-WL) 125 | #define READ_AUTOPRE_DELAY (AL+tRTP+tRP) 126 | #define WRITE_AUTOPRE_DELAY (WL+BL/2+tWR+tRP) 127 | #define WRITE_TO_READ_DELAY_B (WL+BL/2+tWTR) //interbank 128 | #define WRITE_TO_READ_DELAY_R (WL+BL/2+tRTRS-RL) //interrank 129 | 130 | extern unsigned JEDEC_DATA_BUS_BITS; 131 | 132 | //Memory Controller related parameters 133 | extern unsigned TRANS_QUEUE_DEPTH; 134 | extern unsigned CMD_QUEUE_DEPTH; 135 | 136 | extern unsigned EPOCH_LENGTH; 137 | 138 | extern unsigned TOTAL_ROW_ACCESSES; 139 | 140 | extern std::string ROW_BUFFER_POLICY; 141 | extern std::string SCHEDULING_POLICY; 142 | extern std::string ADDRESS_MAPPING_SCHEME; 143 | extern std::string QUEUING_STRUCTURE; 144 | 145 | enum TraceType 146 | { 147 | k6, 148 | mase, 149 | misc 150 | }; 151 | 152 | enum AddressMappingScheme 153 | { 154 | Scheme1, 155 | Scheme2, 156 | Scheme3, 157 | Scheme4, 158 | Scheme5, 159 | Scheme6, 160 | Scheme7 161 | }; 162 | 163 | // used in MemoryController and CommandQueue 164 | enum RowBufferPolicy 165 | { 166 | OpenPage, 167 | ClosePage 168 | }; 169 | 170 | // Only used in CommandQueue 171 | enum QueuingStructure 172 | { 173 | PerRank, 174 | PerRankPerBank 175 | }; 176 | 177 | enum SchedulingPolicy 178 | { 179 | RankThenBankRoundRobin, 180 | BankThenRankRoundRobin 181 | }; 182 | 183 | 184 | // set by IniReader.cpp 185 | 186 | 187 | namespace DRAMSim 188 | { 189 | typedef void (*returnCallBack_t)(unsigned id, uint64_t addr, uint64_t clockcycle); 190 | typedef void (*powerCallBack_t)(double bgpower, double burstpower, double refreshpower, double actprepower); 191 | 192 | extern RowBufferPolicy rowBufferPolicy; 193 | extern SchedulingPolicy schedulingPolicy; 194 | extern AddressMappingScheme addressMappingScheme; 195 | extern QueuingStructure queuingStructure; 196 | // 197 | //FUNCTIONS 198 | // 199 | 200 | unsigned inline dramsim_log2(unsigned value) 201 | { 202 | unsigned logbase2 = 0; 203 | unsigned orig = value; 204 | value>>=1; 205 | while (value>0) 206 | { 207 | value >>= 1; 208 | logbase2++; 209 | } 210 | if ((unsigned)1< $f 24 | done 25 | elif [ "$1" == "remove" ] ; then 26 | NUMLINES=`wc -l gpl.txt | cut -f1 -d' '` 27 | for f in $FILES 28 | do 29 | HEADER=`head --lines=$NUMLINES $f | diff -w gpl.txt -` 30 | if [ -z "$HEADER" ] ; then 31 | echo "deleting from $f" 32 | mv $f $f.tmp 33 | tail --lines=+$NUMLINES $f.tmp > $f 34 | else 35 | echo "header does not match, skipping $f" 36 | fi 37 | 38 | done 39 | fi 40 | 41 | 42 | -------------------------------------------------------------------------------- /comparison_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | """ 3 | 4 | This script generates a series of commands to do parameter sweeps. One way to 5 | use this script is to generate a big matrix of configurations and then run them 6 | on different binaries to diff the output. This can be used as a poor man's 7 | regression test when doing code cleanups (i.e. where functionality is not 8 | supposed to change as a result of a commit. 9 | 10 | Or, if you just set a single binary and comment out the diff stuff at the 11 | bottom, it is just a convenient way to do parameter sweeps. 12 | 13 | Since this uses the command line overrides (-o flag), it needs a fairly recent 14 | commit of DRAMSim2 15 | ( see: https://github.com/dramninjasUMD/DRAMSim2/commit/e46f525bd274a0b3312002dce3efe83c769ea2ce ) 16 | 17 | Just redirect the output of this command to a file and then run it in bash. 18 | 19 | """ 20 | 21 | import itertools 22 | 23 | parameters = {'QUEUING_STRUCTURE': ['per_rank', 'per_rank_per_bank'], 24 | 'ROW_BUFFER_POLICY': ['open_page', 'close_page'], 25 | 'SCHEDULING_POLICY': ['rank_then_bank_round_robin','bank_then_rank_round_robin'] 26 | } 27 | 28 | devices = ['DDR3_micron_64M_8B_x4_sg15.ini', 'DDR2_micron_32M_4B_x4_sg3E.ini']; 29 | 30 | traces = ['k6_bsc_vector1.trc', 'k6_video_tracking_128kL2_trace.trc', 'k6_aoe_02_short.trc'] 31 | binaries = ['DRAMSim.master', 'DRAMSim.cleanup'] 32 | 33 | dramsim_flags = '-c 2000000 -n -S 8192 -q ' 34 | 35 | # get the parameter permutations 36 | 37 | master_list = [] 38 | for k,v in parameters.iteritems(): 39 | # print v 40 | master_list.append(v) 41 | 42 | paramOverrideList=[] 43 | for i in itertools.product(*master_list): 44 | tmp=[] 45 | for j,param in enumerate(i): 46 | tmp.append("%s=%s"%(parameters.keys()[j],param)) 47 | paramOverrideList.append(",".join(tmp)) 48 | #print paramOverrideList 49 | 50 | print "#!/bin/bash" 51 | print "rm DRAMSim.*.vis" 52 | i=0 53 | for trace in traces: 54 | for device in devices: 55 | for paramOverrides in paramOverrideList: 56 | for executable in binaries: 57 | output_file = "%s_%d"%(executable, i) 58 | print "./%s -s system.ini -d ini/%s -t traces/%s -o %s %s -v %s &"%(executable, device, trace, paramOverrides, dramsim_flags, output_file) 59 | i+=1 60 | 61 | print "echo -n waiting" 62 | print "wait" 63 | print "echo OK" 64 | print "echo Starting diff phase" 65 | for x in range(i): 66 | diff_args="%s_%d.vis %s_%d.vis"%(binaries[0],x,binaries[1],x) 67 | print "echo %s_%d.vis and %s_%d.vis:"%(binaries[0],x,binaries[1],x) 68 | print "is_different=`diff -q %s`"%(diff_args) 69 | print "if [ -n \"$is_different\" ] ; then" 70 | print "diff -u %s"%(diff_args); 71 | print "fi" 72 | -------------------------------------------------------------------------------- /docs/classes.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/umd-memsys/DRAMSim2/753819a8571d24f01e44915093e62857efafb97f/docs/classes.png -------------------------------------------------------------------------------- /docs/classes_relationships.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/umd-memsys/DRAMSim2/753819a8571d24f01e44915093e62857efafb97f/docs/classes_relationships.dia -------------------------------------------------------------------------------- /example_app/.gitignore: -------------------------------------------------------------------------------- 1 | dramsim_test 2 | -------------------------------------------------------------------------------- /example_app/Makefile: -------------------------------------------------------------------------------- 1 | 2 | #tell the linker the rpath so that we don't have to muck with LD_LIBRARY_PATH, etc 3 | dramsim_test: dramsim_test.cpp 4 | $(CXX) -g -o dramsim_test dramsim_test.cpp -I../ -L../ -ldramsim -Wl,-rpath=../ 5 | 6 | clean: 7 | rm dramsim_test 8 | -------------------------------------------------------------------------------- /example_app/dramsim_test.cpp: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | #include 35 | #include "dramsim_test.h" 36 | 37 | using namespace DRAMSim; 38 | 39 | /* callback functors */ 40 | void some_object::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle) 41 | { 42 | printf("[Callback] read complete: %d 0x%lx cycle=%lu\n", id, address, clock_cycle); 43 | } 44 | 45 | void some_object::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle) 46 | { 47 | printf("[Callback] write complete: %d 0x%lx cycle=%lu\n", id, address, clock_cycle); 48 | } 49 | 50 | /* FIXME: this may be broken, currently */ 51 | void power_callback(double a, double b, double c, double d) 52 | { 53 | // printf("power callback: %0.3f, %0.3f, %0.3f, %0.3f\n",a,b,c,d); 54 | } 55 | 56 | int some_object::add_one_and_run(MultiChannelMemorySystem *mem, uint64_t addr) 57 | { 58 | 59 | /* create a transaction and add it */ 60 | bool isWrite = false; 61 | mem->addTransaction(isWrite, addr); 62 | 63 | // send a read to channel 1 on the same cycle 64 | addr = 1LL<<33 | addr; 65 | mem->addTransaction(isWrite, addr); 66 | 67 | for (int i=0; i<5; i++) 68 | { 69 | mem->update(); 70 | } 71 | 72 | /* add another some time in the future */ 73 | 74 | // send a write to channel 0 75 | addr = 0x900012; 76 | isWrite = true; 77 | mem->addTransaction(isWrite, addr); 78 | 79 | 80 | /* do a bunch of updates (i.e. clocks) -- at some point the callback will fire */ 81 | for (int i=0; i<45; i++) 82 | { 83 | mem->update(); 84 | } 85 | 86 | /* get a nice summary of this epoch */ 87 | mem->printStats(true); 88 | 89 | return 0; 90 | } 91 | 92 | int main() 93 | { 94 | some_object obj; 95 | TransactionCompleteCB *read_cb = new Callback(&obj, &some_object::read_complete); 96 | TransactionCompleteCB *write_cb = new Callback(&obj, &some_object::write_complete); 97 | 98 | /* pick a DRAM part to simulate */ 99 | MultiChannelMemorySystem *mem = getMemorySystemInstance("ini/DDR2_micron_16M_8b_x8_sg3E.ini", "system.ini", "..", "example_app", 16384); 100 | 101 | 102 | mem->RegisterCallbacks(read_cb, write_cb, power_callback); 103 | MultiChannelMemorySystem *mem2 = getMemorySystemInstance("ini/DDR2_micron_16M_8b_x8_sg3E.ini", "system.ini", "..", "example_app", 16384); 104 | 105 | mem2->RegisterCallbacks(read_cb, write_cb, power_callback); 106 | 107 | printf("dramsim_test main()\n"); 108 | printf("-----MEM1------\n"); 109 | obj.add_one_and_run(mem, 0x100001UL); 110 | obj.add_one_and_run(mem, 0x200002UL); 111 | 112 | printf("-----MEM2------\n"); 113 | obj.add_one_and_run(mem2, 0x300002UL); 114 | return 0; 115 | } 116 | 117 | -------------------------------------------------------------------------------- /example_app/dramsim_test.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************* 2 | * Copyright (c) 2010-2011, Elliott Cooper-Balis 3 | * Paul Rosenfeld 4 | * Bruce Jacob 5 | * University of Maryland 6 | * dramninjas [at] gmail [dot] com 7 | * All rights reserved. 8 | * 9 | * Redistribution and use in source and binary forms, with or without 10 | * modification, are permitted provided that the following conditions are met: 11 | * 12 | * * Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 15 | * * Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | *********************************************************************************/ 30 | 31 | 32 | 33 | 34 | #include 35 | #include 36 | #include 37 | 38 | class some_object 39 | { 40 | public: 41 | void read_complete(unsigned, uint64_t, uint64_t); 42 | void write_complete(unsigned, uint64_t, uint64_t); 43 | int add_one_and_run(DRAMSim::MultiChannelMemorySystem *mem, uint64_t addr); 44 | }; 45 | -------------------------------------------------------------------------------- /ini/DDR2_micron_16M_8b_x8_sg3E.ini: -------------------------------------------------------------------------------- 1 | ; blah blah 2 | NUM_BANKS=8 3 | NUM_ROWS=16384 4 | NUM_COLS=1024 5 | DEVICE_WIDTH=8 6 | 7 | ;in nanoseconds 8 | ;#define REFRESH_PERIOD 7800 9 | REFRESH_PERIOD=7800 10 | tCK=3.0 ; 11 | 12 | CL=4 ; 13 | AL=0 ; 14 | ;AL=3; needs to be tRCD-1 or 0 15 | ;RL=(CL+AL) 16 | ;WL=(RL-1) 17 | BL=4 ; 18 | tRAS=14; 19 | tRCD=4 ; 20 | tRRD=3 ; 21 | tRC=18 ; 22 | tRP=4 ; 23 | tCCD=2 ; 24 | tRTP=3 ; 25 | tWTR=3 ; 26 | tWR=5 ; 27 | tRTRS=1; 28 | tRFC=43; 29 | tFAW=13; 30 | tCKE=3 ; 31 | tXP=2 ; 32 | 33 | tCMD=1 ; 34 | 35 | IDD0=85 36 | IDD1=100 37 | IDD2P=7; 38 | IDD2Q=40; 39 | IDD2N=40; 40 | IDD3Pf=30; 41 | IDD3Ps=10; 42 | IDD3N=55; 43 | IDD4W=135; 44 | IDD4R=135; 45 | IDD5=215; 46 | IDD6=7; 47 | IDD6L=5; 48 | IDD7=280; 49 | Vdd=1.8 ; TODO: double check this 50 | -------------------------------------------------------------------------------- /ini/DDR2_micron_32M_4B_x4_sg3E.ini: -------------------------------------------------------------------------------- 1 | ; This is for a micron DDR2, -3E part as per the verilog models 2 | NUM_BANKS=4 3 | NUM_ROWS=16384 4 | NUM_COLS=2048 5 | DEVICE_WIDTH=4 6 | 7 | ;in nanoseconds 8 | ;#define REFRESH_PERIOD 7800 9 | REFRESH_PERIOD=7800 10 | tCK=3.0 ;* 11 | 12 | CL=4 ;* 13 | AL=0 ;* 14 | ;AL=3; needs to be tRCD-1 or 0 15 | ;RL=(CL+AL) 16 | ;WL=(RL-1) 17 | BL=4 ;* 18 | tRAS=14;* 19 | tRCD=4 ;* 20 | tRRD=3 ;* 21 | tRC=18 ;* 22 | tRP=4 ;* 23 | tCCD=2 ;* 24 | tRTP=3 ;* 25 | tWTR=3 ;* 26 | tWR=5 ;* 27 | tRTRS=1; -- RANK PARAMETER, TODO 28 | tRFC=35;* 29 | tFAW=13;* 30 | tCKE=3 ;* 31 | tXP=2 ;* 32 | 33 | tCMD=1 ;* 34 | 35 | IDD0=90; 36 | IDD1=105; 37 | IDD2P=7; 38 | IDD2Q=45; 39 | IDD2N=50; 40 | IDD3Pf=35; 41 | IDD3Ps=12; 42 | IDD3N=65; 43 | IDD4W=170; 44 | IDD4R=180; 45 | IDD5=180; 46 | IDD6=7; 47 | IDD6L=3; 48 | IDD7=240; 49 | 50 | ;same bank 51 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 52 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 53 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 54 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 55 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 56 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 57 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 58 | Vdd=1.8 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/DDR2_micron_32M_8B_x4_sg25E.ini: -------------------------------------------------------------------------------- 1 | ; This is for a micron DDR2, -3E part as per the verilog models 2 | NUM_BANKS=8 3 | NUM_ROWS=16384 4 | NUM_COLS=2048 5 | DEVICE_WIDTH=4 6 | 7 | ;in nanoseconds 8 | ;#define REFRESH_PERIOD 7800 9 | REFRESH_PERIOD=7800 10 | tCK=2.5 ;* 11 | 12 | CL=5 ;* 13 | AL=0 ;* 14 | ;AL=3; needs to be tRCD-1 or 0 15 | ;RL=(CL+AL) 16 | ;WL=(RL-1) 17 | BL=4 ;* 18 | tRAS=18;* 19 | tRCD=5 ;* 20 | tRRD=3 ;* 21 | tRC=23 ;* 22 | tRP=5 ;* 23 | tCCD=2 ;* 24 | tRTP=3 ;* 25 | tWTR=3 ;* 26 | tWR=6 ;* 27 | tRTRS=1; -- RANK PARAMETER, TODO 28 | tRFC=51;* 29 | tFAW=14;* 30 | tCKE=3 ;* 31 | tXP=2 ;* 32 | 33 | tCMD=1 ;* 34 | 35 | IDD0=90; 36 | IDD1=110; 37 | IDD2P=7; 38 | IDD2Q=45; 39 | IDD2N=50; 40 | IDD3Pf=35; 41 | IDD3Ps=12; 42 | IDD3N=60; 43 | IDD4W=145; 44 | IDD4R=145; 45 | IDD5=235; 46 | IDD6=7; 47 | IDD6L=3; 48 | IDD7=335; 49 | 50 | ;same bank 51 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 52 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 53 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 54 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 55 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 56 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 57 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 58 | Vdd=1.8 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/DDR3_micron_16M_8B_x8_sg15.ini: -------------------------------------------------------------------------------- 1 | NUM_BANKS=8 2 | NUM_ROWS=16384 3 | NUM_COLS=1024 4 | DEVICE_WIDTH=16 5 | 6 | ;in nanoseconds 7 | ;#define REFRESH_PERIOD 7800 8 | REFRESH_PERIOD=7800 9 | tCK=1.5 ;* 10 | 11 | CL=10 ;* 12 | AL=0 ;* 13 | ;AL=3; needs to be tRCD-1 or 0 14 | ;RL=(CL+AL) 15 | ;WL=(RL-1) 16 | BL=8 ;* 17 | tRAS=24;* 18 | tRCD=10 ;* 19 | tRRD=4 ;* 20 | tRC=34 ;* 21 | tRP=10 ;* 22 | tCCD=4 ;* 23 | tRTP=5 ;* 24 | tWTR=5 ;* 25 | tWR=10 ;* 26 | tRTRS=1; -- RANK PARAMETER, TODO 27 | tRFC=74;* 28 | tFAW=20;* 29 | tCKE=4 ;* 30 | tXP=4 ;* 31 | 32 | tCMD=1 ;* 33 | 34 | IDD0=110; 35 | IDD1=130; 36 | IDD2P=12; 37 | IDD2Q=60; 38 | IDD2N=65; 39 | IDD3Pf=40; 40 | IDD3Ps=40; 41 | IDD3N=62; 42 | IDD4W=220; 43 | IDD4R=200; 44 | IDD5=240; 45 | IDD6=6; 46 | IDD6L=9; 47 | IDD7=490; 48 | 49 | ;same bank 50 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 51 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 52 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 53 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 54 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 55 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 56 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 57 | 58 | Vdd=1.5 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/DDR3_micron_32M_8B_x4_sg125.ini: -------------------------------------------------------------------------------- 1 | ; This parts is taken from the micron MT41J256M4 datasheet ( http://micron.com/document_download/?documentId=425 ) 2 | 3 | NUM_BANKS=8 4 | NUM_ROWS=16384 5 | NUM_COLS=2048 6 | DEVICE_WIDTH=4 7 | 8 | ;in nanoseconds 9 | REFRESH_PERIOD=7800 10 | tCK=1.25 11 | 12 | CL=11 13 | AL=0 14 | ;AL=3; needs to be tRCD-1 or 0 15 | ;RL=(CL+AL) 16 | ;WL=(RL-1) 17 | BL=8 18 | tRAS=28 19 | tRCD=11 20 | tRRD=5 ; actually 6ns=4.8CK, but rounded up 21 | tRC=39 22 | tRP=11 23 | tCCD=4 24 | tRTP=6 ; 7.5ns 25 | tWTR=6 ; 7.5ns 26 | tWR=12 ; 15ns 27 | tRTRS=1; -- RANK PARAMETER, TODO 28 | tRFC=88 29 | tFAW=24 ; This part has 1KB (2k columns x 4) = 30ns 30 | tCKE=4 ; 5ns 31 | tXP=5 ; 6ns = 4.8CK rounded up 32 | 33 | tCMD=1 ;* 34 | 35 | ; x4 width; DDR3-1660; page 44 36 | IDD0=95 37 | IDD1=115 38 | IDD2P=45 ; assuming 'fast mode' 39 | IDD2Q=67 40 | IDD2N=70 41 | IDD3Pf=45 ; unused -- also DDR3 doesn't have f,s versions 42 | IDD3Ps=45 ; also unused 43 | IDD3N=67 44 | IDD4W=250 45 | IDD4R=250 46 | IDD5=260 47 | IDD6=6 ; this is unused 48 | IDD6L=6 ; this is unused 49 | IDD7=400 ; this is unused 50 | 51 | ;same bank 52 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 53 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 54 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 55 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 56 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 57 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 58 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 59 | 60 | Vdd=1.5 ; TODO: double check this 61 | -------------------------------------------------------------------------------- /ini/DDR3_micron_32M_8B_x4_sg15.ini: -------------------------------------------------------------------------------- 1 | NUM_BANKS=8 2 | NUM_ROWS=16384 3 | NUM_COLS=2048 4 | DEVICE_WIDTH=4 5 | 6 | ;in nanoseconds 7 | ;#define REFRESH_PERIOD 7800 8 | REFRESH_PERIOD=7800 9 | tCK=1.5 ;* 10 | 11 | CL=10 ;* 12 | AL=0 ;* 13 | ;AL=3; needs to be tRCD-1 or 0 14 | ;RL=(CL+AL) 15 | ;WL=(RL-1) 16 | BL=8 ;* 17 | tRAS=24;* 18 | tRCD=10 ;* 19 | tRRD=4 ;* 20 | tRC=34 ;* 21 | tRP=10 ;* 22 | tCCD=4 ;* 23 | tRTP=5 ;* 24 | tWTR=5 ;* 25 | tWR=10 ;* 26 | tRTRS=1; -- RANK PARAMETER, TODO 27 | tRFC=74;* 28 | tFAW=20;* 29 | tCKE=4 ;* 30 | tXP=4 ;* 31 | 32 | tCMD=1 ;* 33 | 34 | IDD0=85; 35 | IDD1=105; 36 | IDD2P=12; 37 | IDD2Q=60; 38 | IDD2N=65; 39 | IDD3Pf=40; 40 | IDD3Ps=40; 41 | IDD3N=62; 42 | IDD4W=220; 43 | IDD4R=200; 44 | IDD5=240; 45 | IDD6=6; 46 | IDD6L=9; 47 | IDD7=315; 48 | 49 | ;same bank 50 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 51 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 52 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 53 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 54 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 55 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 56 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 57 | 58 | Vdd=1.5 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/DDR3_micron_32M_8B_x8_sg15.ini: -------------------------------------------------------------------------------- 1 | NUM_BANKS=8 2 | NUM_ROWS=32768 3 | NUM_COLS=1024 4 | DEVICE_WIDTH=8 5 | 6 | ;in nanoseconds 7 | ;#define REFRESH_PERIOD 7800 8 | REFRESH_PERIOD=7800 9 | tCK=1.5 ;* 10 | 11 | CL=10 ;* 12 | AL=0 ;* 13 | ;AL=3; needs to be tRCD-1 or 0 14 | ;RL=(CL+AL) 15 | ;WL=(RL-1) 16 | BL=8 ;* 17 | tRAS=24;* 18 | tRCD=10 ;* 19 | tRRD=4 ;* 20 | tRC=34 ;* 21 | tRP=10 ;* 22 | tCCD=4 ;* 23 | tRTP=5 ;* 24 | tWTR=5 ;* 25 | tWR=10 ;* 26 | tRTRS=1; -- RANK PARAMETER, TODO 27 | tRFC=107;* 28 | tFAW=20;* 29 | tCKE=4 ;* 30 | tXP=4 ;* 31 | 32 | tCMD=1 ;* 33 | 34 | IDD0=130; 35 | IDD1=155; 36 | IDD2P=10; 37 | IDD2Q=70; 38 | IDD2N=70; 39 | IDD3Pf=60; 40 | IDD3Ps=60; 41 | IDD3N=90; 42 | IDD4W=300; 43 | IDD4R=255; 44 | IDD5=305; 45 | IDD6=9; 46 | IDD6L=12; 47 | IDD7=460; 48 | 49 | ;same bank 50 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 51 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 52 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 53 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 54 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 55 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 56 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 57 | 58 | Vdd=1.5 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/DDR3_micron_32M_8B_x8_sg25E.ini: -------------------------------------------------------------------------------- 1 | NUM_BANKS=8 2 | NUM_ROWS=32768 3 | NUM_COLS=1024 4 | DEVICE_WIDTH=8 5 | 6 | ;in nanoseconds 7 | ;#define REFRESH_PERIOD 7800 8 | REFRESH_PERIOD=7800 9 | tCK=2.5 ;* 10 | 11 | CL=5 ;* 12 | AL=0 ;* 13 | ;AL=3; needs to be tRCD-1 or 0 14 | ;RL=(CL+AL) 15 | ;WL=(RL-1) 16 | BL=8 ;* 17 | tRAS=15;* 18 | tRCD=5 ;* 19 | tRRD=4 ;* 20 | tRC=20 ;* 21 | tRP=5 ;* 22 | tCCD=4 ;* 23 | tRTP=4 ;* 24 | tWTR=4 ;* 25 | tWR=6 ;* 26 | tRTRS=1; -- RANK PARAMETER, TODO 27 | tRFC=64;* 28 | tFAW=16;* 29 | tCKE=3 ;* 30 | tXP=3 ;* 31 | 32 | tCMD=1 ;* 33 | 34 | IDD0=100; 35 | IDD1=115; 36 | IDD2P=10; 37 | IDD2Q=50; 38 | IDD2N=50; 39 | IDD3Pf=45; 40 | IDD3Ps=45; 41 | IDD3N=65; 42 | IDD4W=230; 43 | IDD4R=195; 44 | IDD5=275; 45 | IDD6=9; 46 | IDD6L=12; 47 | IDD7=400; 48 | 49 | ;same bank 50 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 51 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 52 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 53 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 54 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 55 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 56 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 57 | 58 | Vdd=1.5 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/DDR3_micron_64M_8B_x4_sg15.ini: -------------------------------------------------------------------------------- 1 | NUM_BANKS=8 2 | NUM_ROWS=32768 3 | NUM_COLS=2048 4 | DEVICE_WIDTH=4 5 | 6 | ;in nanoseconds 7 | ;#define REFRESH_PERIOD 7800 8 | REFRESH_PERIOD=7800 9 | tCK=1.5 ;* 10 | 11 | CL=10 ;* 12 | AL=0 ;* 13 | ;AL=3; needs to be tRCD-1 or 0 14 | ;RL=(CL+AL) 15 | ;WL=(RL-1) 16 | BL=8 ;* 17 | tRAS=24;* 18 | tRCD=10 ;* 19 | tRRD=4 ;* 20 | tRC=34 ;* 21 | tRP=10 ;* 22 | tCCD=4 ;* 23 | tRTP=5 ;* 24 | tWTR=5 ;* 25 | tWR=10 ;* 26 | tRTRS=1; -- RANK PARAMETER, TODO 27 | tRFC=107;* 28 | tFAW=20;* 29 | tCKE=4 ;* 30 | tXP=4 ;* 31 | 32 | tCMD=1 ;* 33 | 34 | IDD0=100; 35 | IDD1=130; 36 | IDD2P=10; 37 | IDD2Q=70; 38 | IDD2N=70; 39 | IDD3Pf=60; 40 | IDD3Ps=60; 41 | IDD3N=90; 42 | IDD4W=255; 43 | IDD4R=230; 44 | IDD5=305; 45 | IDD6=9; 46 | IDD6L=12; 47 | IDD7=415; 48 | 49 | ;same bank 50 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 51 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 52 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 53 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 54 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 55 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 56 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 57 | 58 | Vdd=1.5 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/DDR3_micron_8M_8B_x16_sg15.ini: -------------------------------------------------------------------------------- 1 | NUM_BANKS=8 2 | NUM_ROWS=8192 3 | NUM_COLS=1024 4 | DEVICE_WIDTH=16 5 | 6 | ;in nanoseconds 7 | ;#define REFRESH_PERIOD 7800 8 | REFRESH_PERIOD=7800 9 | tCK=1.5 ;* 10 | 11 | CL=10 ;* 12 | AL=0 ;* 13 | ;AL=3; needs to be tRCD-1 or 0 14 | ;RL=(CL+AL) 15 | ;WL=(RL-1) 16 | BL=8 ;* 17 | tRAS=24;* 18 | tRCD=10 ;* 19 | tRRD=4 ;* 20 | tRC=34 ;* 21 | tRP=10 ;* 22 | tCCD=4 ;* 23 | tRTP=5 ;* 24 | tWTR=5 ;* 25 | tWR=10 ;* 26 | tRTRS=1; -- RANK PARAMETER, TODO 27 | tRFC=74;* 28 | tFAW=20;* 29 | tCKE=4 ;* 30 | tXP=4 ;* 31 | 32 | tCMD=1 ;* 33 | 34 | IDD0=110; 35 | IDD1=150; 36 | IDD2P=12; 37 | IDD2Q=60; 38 | IDD2N=65; 39 | IDD3Pf=40; 40 | IDD3Ps=40; 41 | IDD3N=60; 42 | IDD4W=355; 43 | IDD4R=290; 44 | IDD5=240; 45 | IDD6=6; 46 | IDD6L=9; 47 | IDD7=420; 48 | 49 | ;same bank 50 | ;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) 51 | ;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) 52 | ;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) 53 | ;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) 54 | ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) 55 | ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank 56 | ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank 57 | 58 | Vdd=1.5 ; TODO: double check this 59 | -------------------------------------------------------------------------------- /ini/ST-1.2x.ini: -------------------------------------------------------------------------------- 1 | ; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) 2 | ; 3 | ;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416 4 | 5 | ;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 6 | 7 | ;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 8 | 9 | ;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 10 | 11 | ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 12 | 13 | ; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. 14 | 15 | NUM_BANKS=8; 16 | NUM_ROWS=32768; 17 | NUM_COLS=1024; 18 | 19 | DEVICE_WIDTH=8; 20 | 21 | REFRESH_PERIOD=7800; 22 | tCK=1.25; 23 | 24 | CL=11; 25 | AL=0; 26 | 27 | BL=4; 28 | tRAS=20; 29 | tRCD=14; 30 | tRRD=6; 31 | tRC=34; 32 | tRP=14; 33 | tCCD=4; 34 | tRTP=6; 35 | tWTR=6; 36 | tWR=12; 37 | tRTRS=1; 38 | tRFC=1; 39 | tFAW=29; 40 | tCKE=4; 41 | tXP=5; 42 | tCMD=1; 43 | 44 | ; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations. 45 | IDD0=1305; 46 | IDD1=1395; 47 | IDD2P=846; 48 | IDD2Q=1030; 49 | IDD2N=1050; 50 | IDD3Pf=60; 51 | IDD3Ps=60; 52 | IDD3N=1310; 53 | IDD4W=1765; 54 | IDD4R=230; 55 | IDD5=1940; 56 | IDD6=246; 57 | IDD6L=246; 58 | IDD7=2160; 59 | 60 | Vdd=1.5; 61 | -------------------------------------------------------------------------------- /ini/ST-1.5x.ini: -------------------------------------------------------------------------------- 1 | ; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) 2 | ; 3 | ;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416 4 | 5 | ;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 6 | 7 | ;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 8 | 9 | ;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 10 | 11 | ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 12 | 13 | ; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.5x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. 14 | 15 | NUM_BANKS=8; 16 | NUM_ROWS=32768; 17 | NUM_COLS=1024; 18 | 19 | DEVICE_WIDTH=8; 20 | 21 | REFRESH_PERIOD=7800; 22 | tCK=1.25; 23 | 24 | CL=11; 25 | AL=0; 26 | 27 | BL=4; 28 | tRAS=23; 29 | tRCD=17; 30 | tRRD=8; 31 | tRC=40; 32 | tRP=17; 33 | tCCD=4; 34 | tRTP=6; 35 | tWTR=6; 36 | tWR=12; 37 | tRTRS=1; 38 | tRFC=1; 39 | tFAW=36; 40 | tCKE=4; 41 | tXP=5; 42 | tCMD=1; 43 | 44 | ; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations. 45 | IDD0=1305; 46 | IDD1=1395; 47 | IDD2P=846; 48 | IDD2Q=1030; 49 | IDD2N=1050; 50 | IDD3Pf=60; 51 | IDD3Ps=60; 52 | IDD3N=1310; 53 | IDD4W=1765; 54 | IDD4R=230; 55 | IDD5=1940; 56 | IDD6=246; 57 | IDD6L=246; 58 | IDD7=2160; 59 | 60 | Vdd=1.5; 61 | 62 | -------------------------------------------------------------------------------- /ini/ST-2.0x.ini: -------------------------------------------------------------------------------- 1 | ; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) 2 | ; 3 | ;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416 4 | 5 | ;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 6 | 7 | ;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 8 | 9 | ;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 10 | 11 | ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 12 | 13 | ; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. 14 | 15 | NUM_BANKS=8; 16 | NUM_ROWS=32768; 17 | NUM_COLS=1024; 18 | 19 | DEVICE_WIDTH=8; 20 | 21 | REFRESH_PERIOD=7800; 22 | tCK=1.25; 23 | 24 | CL=11; 25 | AL=0; 26 | 27 | BL=4; 28 | tRAS=28; 29 | tRCD=22; 30 | tRRD=10; 31 | tRC=50; 32 | tRP=22; 33 | tCCD=4; 34 | tRTP=6; 35 | tWTR=6; 36 | tWR=12; 37 | tRTRS=1; 38 | tRFC=1; 39 | tFAW=48; 40 | tCKE=4; 41 | tXP=5; 42 | tCMD=1; 43 | 44 | ; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations. 45 | IDD0=1305; 46 | IDD1=1395; 47 | IDD2P=846; 48 | IDD2Q=1030; 49 | IDD2N=1050; 50 | IDD3Pf=60; 51 | IDD3Ps=60; 52 | IDD3N=1310; 53 | IDD4W=1765; 54 | IDD4R=230; 55 | IDD5=1940; 56 | IDD6=246; 57 | IDD6L=246; 58 | IDD7=2160; 59 | 60 | Vdd=1.5; 61 | -------------------------------------------------------------------------------- /system.ini.example: -------------------------------------------------------------------------------- 1 | ; COPY THIS FILE AND MODIFY IT TO SUIT YOUR NEEDS 2 | 3 | NUM_CHANS=1 ; number of *logically independent* channels (i.e. each with a separate memory controller); should be a power of 2 4 | JEDEC_DATA_BUS_BITS=64 ; Always 64 for DDRx; if you want multiple *ganged* channels, set this to N*64 5 | TRANS_QUEUE_DEPTH=32 ; transaction queue, i.e., CPU-level commands such as: READ 0xbeef 6 | CMD_QUEUE_DEPTH=32 ; command queue, i.e., DRAM-level commands such as: CAS 544, RAS 4 7 | EPOCH_LENGTH=100000 ; length of an epoch in cycles (granularity of simulation) 8 | ROW_BUFFER_POLICY=open_page ; close_page or open_page 9 | ADDRESS_MAPPING_SCHEME=scheme2 ;valid schemes 1-7; For multiple independent channels, use scheme7 since it has the most parallelism 10 | SCHEDULING_POLICY=rank_then_bank_round_robin ; bank_then_rank_round_robin or rank_then_bank_round_robin 11 | QUEUING_STRUCTURE=per_rank ;per_rank or per_rank_per_bank 12 | 13 | ;for true/false, please use all lowercase 14 | DEBUG_TRANS_Q=false 15 | DEBUG_CMD_Q=false 16 | DEBUG_ADDR_MAP=false 17 | DEBUG_BUS=false 18 | DEBUG_BANKSTATE=false 19 | DEBUG_BANKS=false 20 | DEBUG_POWER=false 21 | VIS_FILE_OUTPUT=true 22 | 23 | USE_LOW_POWER=true ; go into low power mode when idle? 24 | VERIFICATION_OUTPUT=false ; should be false for normal operation 25 | TOTAL_ROW_ACCESSES=4 ; maximum number of open page requests to send to the same row before forcing a row close (to prevent starvation) 26 | -------------------------------------------------------------------------------- /traces/.gitignore: -------------------------------------------------------------------------------- 1 | *.trc 2 | -------------------------------------------------------------------------------- /traces/README: -------------------------------------------------------------------------------- 1 | Before running these traces in DRAMSim, run the preprocessor: 2 | 3 | ./traceParse.py trace.tar.gz 4 | 5 | The resulting .trc file should be used with DRAMSim 6 | -------------------------------------------------------------------------------- /traces/k6_aoe_02_short.trc.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/umd-memsys/DRAMSim2/753819a8571d24f01e44915093e62857efafb97f/traces/k6_aoe_02_short.trc.gz -------------------------------------------------------------------------------- /traces/mase_art.trc.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/umd-memsys/DRAMSim2/753819a8571d24f01e44915093e62857efafb97f/traces/mase_art.trc.gz -------------------------------------------------------------------------------- /traces/traceParse.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import re, os 4 | import string 5 | import sys 6 | import array 7 | 8 | if len(sys.argv) != 2: 9 | sys.exit("Must specify trace file (.gz)") 10 | 11 | 12 | gztrace_filename = sys.argv[1] 13 | tracefile_filename = sys.argv[1][0:len(sys.argv[1])-3] 14 | outfile = open(tracefile_filename,"w") 15 | temp_trace = tracefile_filename + ".temp" 16 | 17 | zcat_cmd = "zcat"; 18 | # accomodate OSX 19 | if os.uname()[0] == "Darwin": 20 | print "Detected OSX, using gzcat..." 21 | zcat_cmd = "gzcat" 22 | 23 | if not os.path.exists(gztrace_filename): 24 | print "Could not find gzipped tracefile either" 25 | quit() 26 | else: 27 | print "Unzipping gz trace...", 28 | os.system("%s %s > %s" % (zcat_cmd, gztrace_filename, temp_trace)) 29 | if not os.path.exists(tracefile_filename): 30 | print "FAILED" 31 | quit() 32 | else: 33 | print "OK" 34 | 35 | print "Parsing ", 36 | tracefile = open(temp_trace,"r") 37 | 38 | if tracefile_filename.startswith("k6"): 39 | print "k6 trace ..." 40 | linePattern = re.compile(r'(0x[0-9A-F]+)\s+([A-Z_]+)\s+([0-9.,]+)\s+(.*)') 41 | for line in tracefile: 42 | searchResult = linePattern.search(line) 43 | if searchResult: 44 | (address,command,time,units) = searchResult.groups() 45 | 46 | length = len(time) 47 | time = time[0:length-5] 48 | temp = len(time) 49 | if temp==0: 50 | time = "0" 51 | time = string.replace(time,",","") 52 | time = string.replace(time,".","") 53 | if command != "BOFF" and command != "P_INT_ACK": 54 | outfile.write("%s %s %s\n" % (address,command,time)) 55 | 56 | elif tracefile_filename.startswith("mase"): 57 | print "mase trace ...", 58 | os.system("cp %s %s"%(temp_trace, tracefile_filename)); 59 | print "OK" 60 | 61 | else: 62 | print "Unknown trace file!!!" 63 | quit() 64 | 65 | os.system("rm %s" % temp_trace); 66 | --------------------------------------------------------------------------------