├── .clang-format ├── .gitignore ├── .gitmodules ├── .travis.yml ├── .vscode ├── .cmaketools.json ├── launch.json ├── settings-backup.json └── tasks.json ├── CMakeLists.txt ├── LICENSE ├── Makefile ├── README.md ├── configs ├── DDR3_1Gb_x8_1333.ini ├── DDR3_4Gb_x16_1600.ini ├── DDR3_4Gb_x16_1866.ini ├── DDR3_4Gb_x4_1600.ini ├── DDR3_4Gb_x4_1866.ini ├── DDR3_4Gb_x8_1600.ini ├── DDR3_4Gb_x8_1866.ini ├── DDR3_8Gb_x16_1600.ini ├── DDR3_8Gb_x16_1866.ini ├── DDR3_8Gb_x4_1600.ini ├── DDR3_8Gb_x4_1866.ini ├── DDR3_8Gb_x8_1600.ini ├── DDR3_8Gb_x8_1866.ini ├── DDR4_4Gb_x16_1866.ini ├── DDR4_4Gb_x16_2133.ini ├── DDR4_4Gb_x16_2133_2.ini ├── DDR4_4Gb_x16_2400.ini ├── DDR4_4Gb_x16_2400_2.ini ├── DDR4_4Gb_x16_2666.ini ├── DDR4_4Gb_x16_2666_2.ini ├── DDR4_4Gb_x4_1866.ini ├── DDR4_4Gb_x4_2133.ini ├── DDR4_4Gb_x4_2133_2.ini ├── DDR4_4Gb_x4_2400.ini ├── DDR4_4Gb_x4_2400_2.ini ├── DDR4_4Gb_x4_2666.ini ├── DDR4_4Gb_x4_2666_2.ini ├── DDR4_4Gb_x8_1866.ini ├── DDR4_4Gb_x8_2133.ini ├── DDR4_4Gb_x8_2133_2.ini ├── DDR4_4Gb_x8_2400.ini ├── DDR4_4Gb_x8_2400_2.ini ├── DDR4_4Gb_x8_2666.ini ├── DDR4_4Gb_x8_2666_2.ini ├── DDR4_8Gb_x16_1866.ini ├── DDR4_8Gb_x16_2133.ini ├── DDR4_8Gb_x16_2133_2.ini ├── DDR4_8Gb_x16_2400.ini ├── DDR4_8Gb_x16_2400_2.ini ├── DDR4_8Gb_x16_2666.ini ├── DDR4_8Gb_x16_2666_2.ini ├── DDR4_8Gb_x16_2933.ini ├── DDR4_8Gb_x16_2933_2.ini ├── DDR4_8Gb_x16_3200.ini ├── DDR4_8Gb_x4_1866.ini ├── DDR4_8Gb_x4_2133.ini ├── DDR4_8Gb_x4_2133_2.ini ├── DDR4_8Gb_x4_2400.ini ├── DDR4_8Gb_x4_2400_2.ini ├── DDR4_8Gb_x4_2666.ini ├── DDR4_8Gb_x4_2666_2.ini ├── DDR4_8Gb_x4_2933.ini ├── DDR4_8Gb_x4_2933_2.ini ├── DDR4_8Gb_x4_3200.ini ├── DDR4_8Gb_x8_1866.ini ├── DDR4_8Gb_x8_2133.ini ├── DDR4_8Gb_x8_2133_2.ini ├── DDR4_8Gb_x8_2400.ini ├── DDR4_8Gb_x8_2400_2.ini ├── DDR4_8Gb_x8_2666.ini ├── DDR4_8Gb_x8_2666_2.ini ├── DDR4_8Gb_x8_2933.ini ├── DDR4_8Gb_x8_2933_2.ini ├── DDR4_8Gb_x8_3200.ini ├── GDDR5X_8Gb_x32.ini ├── GDDR5_1Gb_x32.ini ├── GDDR5_8Gb_x32.ini ├── GDDR6_8Gb_x16.ini ├── HBM1_4Gb_x128.ini ├── HBM2_4Gb_x128.ini ├── HBM2_8Gb_x128.ini ├── HBM_4Gb_x128.ini ├── HMC2_8GB_4Lx16.ini ├── HMC_2GB_4Lx16.ini ├── HMC_2GB_4Lx16_dummy.ini ├── HMC_4GB_4Lx16.ini ├── LPDDR3_8Gb_x32_1333.ini ├── LPDDR3_8Gb_x32_1600.ini ├── LPDDR3_8Gb_x32_1866.ini ├── LPDDR4_8Gb_x16_2400.ini ├── ST-1.2x.ini ├── ST-1.5x.ini ├── ST-2.0x.ini ├── ddr3_debug.ini ├── ddr4_debug.ini └── lpddr_2Gb_x16.ini ├── ext ├── fmt │ ├── LICENSE.rst │ └── include │ │ └── fmt │ │ ├── core.h │ │ ├── format-inl.h │ │ └── format.h └── headers │ ├── INIHLICENSE.txt │ ├── INIReader.h │ ├── args.hxx │ ├── catch.hpp │ └── json.hpp ├── scripts ├── batch_run.py ├── final_PowerTemperature_map.py ├── heatmap.py ├── parse_config.py ├── plot_stats.py ├── trace_gen.py └── validation.py ├── src ├── bankstate.cc ├── bankstate.h ├── channel_state.cc ├── channel_state.h ├── command_queue.cc ├── command_queue.h ├── common.cc ├── common.h ├── configuration.cc ├── configuration.h ├── controller.cc ├── controller.h ├── cpu.cc ├── cpu.h ├── dram_system.cc ├── dram_system.h ├── dramsim3.h ├── hmc.cc ├── hmc.h ├── main.cc ├── memory_system.cc ├── memory_system.h ├── refresh.cc ├── refresh.h ├── simple_stats.cc ├── simple_stats.h ├── sp_ienv.c ├── thermal.cc ├── thermal.h ├── thermal_config.h ├── thermal_replay.cc ├── thermal_replay.h ├── thermal_solver.c ├── timing.cc └── timing.h └── tests ├── example.trace ├── test_config.cc ├── test_dramsys.cc └── test_hmcsys.cc /.clang-format: -------------------------------------------------------------------------------- 1 | --- 2 | Language: Cpp 3 | # BasedOnStyle: Google 4 | AccessModifierOffset: -1 5 | AlignAfterOpenBracket: Align 6 | AlignConsecutiveAssignments: false 7 | AlignConsecutiveDeclarations: false 8 | AlignEscapedNewlines: Left 9 | AlignOperands: true 10 | AlignTrailingComments: true 11 | AllowAllParametersOfDeclarationOnNextLine: true 12 | AllowShortBlocksOnASingleLine: false 13 | AllowShortCaseLabelsOnASingleLine: false 14 | AllowShortFunctionsOnASingleLine: All 15 | AllowShortIfStatementsOnASingleLine: true 16 | AllowShortLoopsOnASingleLine: true 17 | AlwaysBreakAfterDefinitionReturnType: None 18 | AlwaysBreakAfterReturnType: None 19 | AlwaysBreakBeforeMultilineStrings: true 20 | AlwaysBreakTemplateDeclarations: true 21 | BinPackArguments: true 22 | BinPackParameters: true 23 | BraceWrapping: 24 | AfterClass: false 25 | AfterControlStatement: false 26 | AfterEnum: false 27 | AfterFunction: false 28 | AfterNamespace: false 29 | AfterObjCDeclaration: false 30 | AfterStruct: false 31 | AfterUnion: false 32 | AfterExternBlock: false 33 | BeforeCatch: false 34 | BeforeElse: false 35 | IndentBraces: false 36 | SplitEmptyFunction: true 37 | SplitEmptyRecord: true 38 | SplitEmptyNamespace: true 39 | BreakBeforeBinaryOperators: None 40 | BreakBeforeBraces: Attach 41 | BreakBeforeInheritanceComma: false 42 | BreakBeforeTernaryOperators: true 43 | BreakConstructorInitializersBeforeComma: false 44 | BreakConstructorInitializers: BeforeColon 45 | BreakAfterJavaFieldAnnotations: false 46 | BreakStringLiterals: true 47 | ColumnLimit: 80 48 | CommentPragmas: '^ IWYU pragma:' 49 | CompactNamespaces: false 50 | ConstructorInitializerAllOnOneLineOrOnePerLine: true 51 | ConstructorInitializerIndentWidth: 4 52 | ContinuationIndentWidth: 4 53 | Cpp11BracedListStyle: true 54 | DerivePointerAlignment: true 55 | DisableFormat: false 56 | ExperimentalAutoDetectBinPacking: false 57 | FixNamespaceComments: true 58 | ForEachMacros: 59 | - foreach 60 | - Q_FOREACH 61 | - BOOST_FOREACH 62 | IncludeBlocks: Preserve 63 | IncludeCategories: 64 | - Regex: '^' 65 | Priority: 2 66 | - Regex: '^<.*\.h>' 67 | Priority: 1 68 | - Regex: '^<.*' 69 | Priority: 2 70 | - Regex: '.*' 71 | Priority: 3 72 | IncludeIsMainRegex: '([-_](test|unittest))?$' 73 | IndentCaseLabels: true 74 | IndentPPDirectives: None 75 | IndentWidth: 4 76 | IndentWrappedFunctionNames: false 77 | JavaScriptQuotes: Leave 78 | JavaScriptWrapImports: true 79 | KeepEmptyLinesAtTheStartOfBlocks: false 80 | MacroBlockBegin: '' 81 | MacroBlockEnd: '' 82 | MaxEmptyLinesToKeep: 1 83 | NamespaceIndentation: None 84 | ObjCBlockIndentWidth: 2 85 | ObjCSpaceAfterProperty: false 86 | ObjCSpaceBeforeProtocolList: false 87 | PenaltyBreakAssignment: 2 88 | PenaltyBreakBeforeFirstCallParameter: 1 89 | PenaltyBreakComment: 300 90 | PenaltyBreakFirstLessLess: 120 91 | PenaltyBreakString: 1000 92 | PenaltyExcessCharacter: 1000000 93 | PenaltyReturnTypeOnItsOwnLine: 200 94 | PointerAlignment: Left 95 | RawStringFormats: 96 | - Delimiter: pb 97 | Language: TextProto 98 | BasedOnStyle: google 99 | ReflowComments: true 100 | SortIncludes: true 101 | SortUsingDeclarations: true 102 | SpaceAfterCStyleCast: false 103 | SpaceAfterTemplateKeyword: true 104 | SpaceBeforeAssignmentOperators: true 105 | SpaceBeforeParens: ControlStatements 106 | SpaceInEmptyParentheses: false 107 | SpacesBeforeTrailingComments: 2 108 | SpacesInAngles: false 109 | SpacesInContainerLiterals: true 110 | SpacesInCStyleCastParentheses: false 111 | SpacesInParentheses: false 112 | SpacesInSquareBrackets: false 113 | Standard: Auto 114 | TabWidth: 8 115 | UseTab: Never 116 | ... 117 | 118 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # project files 2 | build/ 3 | debug_build/ 4 | data/ 5 | ext/SuperLU_MT_3.1/ 6 | obj 7 | dramsim3 8 | dramsim3test 9 | dramsim3main 10 | *.log 11 | release 12 | .idea 13 | *.pyc 14 | *.vh 15 | .vs/ 16 | 17 | # Compiled Object files 18 | *.slo 19 | *.lo 20 | *.o 21 | *.obj 22 | 23 | # Precompiled Headers 24 | *.gch 25 | *.pch 26 | 27 | # Compiled Dynamic libraries 28 | *.so 29 | *.dylib 30 | *.dll 31 | 32 | # Fortran module files 33 | *.mod 34 | *.smod 35 | 36 | # Compiled Static libraries 37 | *.lai 38 | *.la 39 | *.a 40 | *.lib 41 | 42 | # Executables 43 | *.exe 44 | *.out 45 | *.app 46 | 47 | # IDEs / Editors 48 | .vscode/ 49 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "ext/SuperLU_MT_3.1"] 2 | path = ext/SuperLU_MT_3.1 3 | url = https://github.com/umd-memsys/SuperLU_MT_3.1.git 4 | ignore = dirty 5 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | dist: trusty 2 | #sudo: required 3 | sudo: false 4 | 5 | language: cpp 6 | warnings_are_errors: true 7 | 8 | compiler: 9 | # - gcc 10 | - clang 11 | 12 | #addons: 13 | # apt: 14 | # packages: 15 | # - gcc-4.9 16 | # - clang-3.5 17 | # - cmake 18 | 19 | script: 20 | - mkdir build 21 | - cd build 22 | - cmake .. 23 | - make -j4 24 | -------------------------------------------------------------------------------- /.vscode/.cmaketools.json: -------------------------------------------------------------------------------- 1 | { 2 | "variant": { 3 | "label": "Debug", 4 | "keywordSettings": { 5 | "buildType": "debug" 6 | }, 7 | "description": "Emit debug information without performing optimizations" 8 | }, 9 | "activeEnvironments": [] 10 | } -------------------------------------------------------------------------------- /.vscode/launch.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "0.2.0", 3 | "configurations": [ 4 | 5 | { 6 | "name": "C++ Launch", 7 | "type": "cppdbg", 8 | "request": "launch", 9 | "program": "${workspaceRoot}/build/dramcoremain", 10 | "args": ["-c", "./../configs/ddr4_8G_x8_config.ini", "-n", "100000", "--trace-cpu", "--trace-file", "./../sample_trace.txt"], 11 | "stopAtEntry": true, 12 | "cwd": "${workspaceRoot}/build", 13 | "environment": [], 14 | "externalConsole": true, 15 | "linux": { 16 | "MIMode": "gdb", 17 | "setupCommands": [ 18 | { 19 | "description": "Enable pretty-printing for gdb", 20 | "text": "-enable-pretty-printing", 21 | "ignoreFailures": true 22 | } 23 | ] 24 | }, 25 | "osx": { 26 | "MIMode": "lldb" 27 | }, 28 | "windows": { 29 | "MIMode": "gdb", 30 | "setupCommands": [ 31 | { 32 | "description": "Enable pretty-printing for gdb", 33 | "text": "-enable-pretty-printing", 34 | "ignoreFailures": true 35 | } 36 | ] 37 | } 38 | }, 39 | { 40 | "name": "C++ Attach", 41 | "type": "cppdbg", 42 | "request": "attach", 43 | "program": "enter program name, for example ${workspaceRoot}/a.out", 44 | "processId": "${command.pickProcess}", 45 | "linux": { 46 | "MIMode": "gdb", 47 | "setupCommands": [ 48 | { 49 | "description": "Enable pretty-printing for gdb", 50 | "text": "-enable-pretty-printing", 51 | "ignoreFailures": true 52 | } 53 | ] 54 | }, 55 | "osx": { 56 | "MIMode": "lldb" 57 | }, 58 | "windows": { 59 | "MIMode": "gdb", 60 | "setupCommands": [ 61 | { 62 | "description": "Enable pretty-printing for gdb", 63 | "text": "-enable-pretty-printing", 64 | "ignoreFailures": true 65 | } 66 | ] 67 | } 68 | } 69 | ] 70 | } -------------------------------------------------------------------------------- /.vscode/settings-backup.json: -------------------------------------------------------------------------------- 1 | { 2 | "files.associations": { 3 | "array": "cpp", 4 | "initializer_list": "cpp" 5 | } 6 | } -------------------------------------------------------------------------------- /.vscode/tasks.json: -------------------------------------------------------------------------------- 1 | { 2 | // See https://go.microsoft.com/fwlink/?LinkId=733558 3 | // for the documentation about the tasks.json format 4 | "version": "0.1.0", 5 | "command": "make", 6 | "isShellCommand": true, 7 | "args": ["-j5"], 8 | "showOutput": "always", 9 | "options": { 10 | "cwd": "${workspaceRoot}/build" 11 | } 12 | } -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.0.0) 2 | project(dramsim3) 3 | 4 | set(default_build_type "Release") 5 | if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES) 6 | message(STATUS "Setting build type to '${default_build_type}' as none was specified.") 7 | set(CMAKE_BUILD_TYPE "${default_build_type}" CACHE 8 | STRING "Choose the type of build." FORCE) 9 | # Set the possible values of build type for cmake-gui 10 | set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS 11 | "Debug" "Release" "MinSizeRel" "RelWithDebInfo") 12 | endif() 13 | 14 | add_library(inih INTERFACE) 15 | target_include_directories(inih INTERFACE ext/headers) 16 | 17 | add_library(format INTERFACE) 18 | target_include_directories(format INTERFACE ext/fmt/include) 19 | target_compile_definitions(format INTERFACE FMT_HEADER_ONLY=1) 20 | 21 | # argparsing library, only used in main program not the library 22 | add_library(args INTERFACE) 23 | target_include_directories(args INTERFACE ext/headers) 24 | 25 | add_library(json INTERFACE) 26 | target_include_directories(json INTERFACE ext/headers) 27 | 28 | # Main DRAMSim Lib 29 | add_library(dramsim3 SHARED 30 | src/bankstate.cc 31 | src/channel_state.cc 32 | src/command_queue.cc 33 | src/common.cc 34 | src/configuration.cc 35 | src/controller.cc 36 | src/dram_system.cc 37 | src/hmc.cc 38 | src/refresh.cc 39 | src/simple_stats.cc 40 | src/timing.cc 41 | src/memory_system.cc 42 | ) 43 | 44 | if (THERMAL) 45 | # dependency check 46 | # sudo apt-get install libatlas-base-dev on ubuntu 47 | find_package(BLAS REQUIRED) 48 | find_package(OpenMP REQUIRED) 49 | # YOU need to build superlu on your own. Do the following: 50 | # git submodule update --init 51 | # cd ext/SuperLU_MT_3.1 && make lib 52 | find_library(SUPERLU 53 | NAME superlu_mt_OPENMP libsuperlu_mt_OPENMP 54 | HINTS ${PROJECT_SOURCE_DIR}/ext/SuperLU_MT_3.1/lib/ 55 | ) 56 | 57 | target_link_libraries(dramsim3 58 | PRIVATE ${SUPERLU} f77blas atlas m ${OpenMP_C_FLAGS} 59 | ) 60 | target_sources(dramsim3 61 | PRIVATE src/thermal.cc src/sp_ienv.c src/thermal_solver.c 62 | ) 63 | target_compile_options(dramsim3 PRIVATE -DTHERMAL -D_LONGINT -DAdd_ ${OpenMP_C_FLAGS}) 64 | 65 | add_executable(thermalreplay src/thermal_replay.cc) 66 | target_link_libraries(thermalreplay dramsim3 inih) 67 | target_compile_options(thermalreplay PRIVATE -DTHERMAL -D_LONGINT -DAdd_ ${OpenMP_C_FLAGS}) 68 | endif (THERMAL) 69 | 70 | if (CMD_TRACE) 71 | target_compile_options(dramsim3 PRIVATE -DCMD_TRACE) 72 | endif (CMD_TRACE) 73 | 74 | if (ADDR_TRACE) 75 | target_compile_options(dramsim3 PRIVATE -DADDR_TRACE) 76 | endif (ADDR_TRACE) 77 | 78 | 79 | target_include_directories(dramsim3 INTERFACE src) 80 | target_compile_options(dramsim3 PRIVATE -Wall) 81 | target_link_libraries(dramsim3 PRIVATE inih format) 82 | set_target_properties(dramsim3 PROPERTIES 83 | LIBRARY_OUTPUT_DIRECTORY ${PROJECT_SOURCE_DIR} 84 | CXX_STANDARD 11 85 | CXX_STANDARD_REQUIRED YES 86 | CXX_EXTENSIONS NO 87 | ) 88 | 89 | # trace CPU, .etc 90 | add_executable(dramsim3main src/main.cc src/cpu.cc) 91 | target_link_libraries(dramsim3main PRIVATE dramsim3 args) 92 | target_compile_options(dramsim3main PRIVATE) 93 | set_target_properties(dramsim3main PROPERTIES 94 | CXX_STANDARD 11 95 | CXX_STANDARD_REQUIRED YES 96 | CXX_EXTENSIONS NO 97 | ) 98 | 99 | # Unit testing 100 | add_library(Catch INTERFACE) 101 | target_include_directories(Catch INTERFACE ext/headers) 102 | 103 | add_executable(dramsim3test EXCLUDE_FROM_ALL 104 | tests/test_config.cc 105 | tests/test_dramsys.cc 106 | tests/test_hmcsys.cc # IDK somehow this can literally crush your computer 107 | ) 108 | target_link_libraries(dramsim3test Catch dramsim3) 109 | target_include_directories(dramsim3test PRIVATE src/) 110 | 111 | # We have to use this custome command because there's a bug in cmake 112 | # that if you do `make test` it doesn't build your updated test files 113 | # so we're stucking with `make dramsim3test` for now 114 | add_custom_command( 115 | TARGET dramsim3test POST_BUILD 116 | COMMAND dramsim3test 117 | WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} 118 | DEPENDS dramsim3test dramsim3 119 | ) 120 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2019, University of Maryland Memory-Systems Research 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a 4 | copy of this software and associated documentation files (the 5 | "Software"), to deal in the Software without restriction, including 6 | without limitation the rights to use, copy, modify, merge, publish, 7 | distribute, sublicense, and/or sell copies of the Software, and to 8 | permit persons to whom the Software is furnished to do so, subject to 9 | the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included 12 | in all copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 | OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 16 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 17 | IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 18 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 19 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 20 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # ONLY use this makefile if you do NOT have a cmake 3.0+ version 2 | 3 | CC=gcc 4 | CXX=g++ 5 | 6 | FMT_LIB_DIR=ext/fmt/include 7 | INI_LIB_DIR=ext/headers 8 | JSON_LIB_DIR=ext/headers 9 | ARGS_LIB_DIR=ext/headers 10 | 11 | INC=-Isrc/ -I$(FMT_LIB_DIR) -I$(INI_LIB_DIR) -I$(ARGS_LIB_DIR) -I$(JSON_LIB_DIR) 12 | CXXFLAGS=-Wall -O3 -fPIC -std=c++11 $(INC) -DFMT_HEADER_ONLY=1 13 | 14 | LIB_NAME=libdramsim3.so 15 | EXE_NAME=dramsim3main.out 16 | 17 | SRCS = src/bankstate.cc src/channel_state.cc src/command_queue.cc src/common.cc \ 18 | src/configuration.cc src/controller.cc src/dram_system.cc src/hmc.cc \ 19 | src/memory_system.cc src/refresh.cc src/simple_stats.cc src/timing.cc 20 | 21 | EXE_SRCS = src/cpu.cc src/main.cc 22 | 23 | OBJECTS = $(addsuffix .o, $(basename $(SRCS))) 24 | EXE_OBJS = $(addsuffix .o, $(basename $(EXE_SRCS))) 25 | EXE_OBJS := $(EXE_OBJS) $(OBJECTS) 26 | 27 | 28 | all: $(LIB_NAME) $(EXE_NAME) 29 | 30 | $(EXE_NAME): $(EXE_OBJS) 31 | $(CXX) $(CXXFLAGS) -o $@ $^ 32 | 33 | $(LIB_NAME): $(OBJECTS) 34 | $(CXX) -g -shared -Wl,-soname,$@ -o $@ $^ 35 | 36 | %.o : %.cc 37 | $(CXX) $(CXXFLAGS) -o $@ -c $< 38 | 39 | %.o : %.c 40 | $(CC) -fPIC -O2 -o $@ -c $< 41 | 42 | clean: 43 | -rm -f $(EXE_OBJS) $(LIB_NAME) $(EXE_NAME) -------------------------------------------------------------------------------- /configs/DDR3_1Gb_x8_1333.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 16384 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.5 12 | AL = 0 13 | CL = 10 14 | CWL = 7 15 | tRCD = 10 16 | tRP = 10 17 | tRAS = 24 18 | tRFC = 74 19 | tREFI = 5200 20 | tRPRE = 1 21 | tWPRE = 1 22 | tRRD_S = 4 23 | tWTR_S = 5 24 | tFAW = 20 25 | tWR = 10 26 | tCCD_S = 4 27 | tRTP = 5 28 | tCKE = 4 29 | tCKESR = 1 30 | tXS = 81 31 | tXP = 5 32 | tRTRS = 1 33 | 34 | [power] 35 | VDD = 1.35 36 | IDD0 = 33 37 | IDD2P = 12 38 | IDD2N = 17 39 | IDD3P = 14 40 | IDD3N = 23 41 | IDD4W = 77 42 | IDD4R = 72 43 | IDD5AB = 155 44 | IDD6x = 12 45 | 46 | [system] 47 | channel_size = 2048 48 | channels = 1 49 | bus_width = 64 50 | address_mapping = rochrababgco 51 | queue_structure = PER_BANK 52 | trans_queue_size = 32 53 | row_buf_policy = OPEN_PAGE 54 | cmd_queue_size = 8 55 | 56 | [other] 57 | epoch_period = 666666 58 | output_level = 1 59 | 60 | [thermal] 61 | loc_mapping = 30,30,30,29:27,26:13,12:3 62 | power_epoch_period = 10000; power epoch period (# cycle) 63 | chip_dim_x = 0.008; chip size in x dimension [m] 64 | chip_dim_y = 0.008; chip size in y dimension [m] 65 | amb_temp = 40; The ambient temperature in [C] 66 | mat_dim_x = 512; 67 | mat_dim_y = 512; 68 | bank_order = 1; 0: x direction first, 1: y direction first 69 | 70 | -------------------------------------------------------------------------------- /configs/DDR3_4Gb_x16_1600.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.25 12 | AL = 0 13 | CL = 11 14 | CWL = 8 15 | tRCD = 11 16 | tRP = 11 17 | tRAS = 28 18 | tRFC = 208 19 | tRFC2 = 208 20 | tRFC4 = 208 21 | REFI = 6240 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 5 25 | tRRD_L = 5 26 | tWTR_S = 6 27 | tWTR_L = 6 28 | tFAW = 32 29 | tWR = 12 30 | tWR2 = 12 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 4 35 | tCKESR = 5 36 | tXS = 216 37 | tXP = 5 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 66 43 | IPP0 = 0.0 44 | IDD2P = 18 45 | IDD2N = 32 46 | IDD3P = 38 47 | IDD3N = 47 48 | IDD4W = 171 49 | IDD4R = 235 50 | IDD5AB = 235 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 800000 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_4Gb_x16_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 9 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 243 19 | tRFC2 = 243 20 | tRFC4 = 243 21 | REFI = 7290 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 6 25 | tRRD_L = 6 26 | tWTR_S = 7 27 | tWTR_L = 7 28 | tFAW = 33 29 | tWR = 15 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 253 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 73 43 | IPP0 = 0.0 44 | IDD2P = 18 45 | IDD2N = 35 46 | IDD3P = 41 47 | IDD3N = 49 48 | IDD4W = 190 49 | IDD4R = 252 50 | IDD5AB = 242 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_4Gb_x4_1600.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 2048 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.25 12 | AL = 0 13 | CL = 11 14 | CWL = 8 15 | tRCD = 11 16 | tRP = 11 17 | tRAS = 28 18 | tRFC = 208 19 | tRFC2 = 208 20 | tRFC4 = 208 21 | REFI = 6240 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 5 25 | tRRD_L = 5 26 | tWTR_S = 6 27 | tWTR_L = 6 28 | tFAW = 24 29 | tWR = 12 30 | tWR2 = 12 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 4 35 | tCKESR = 5 36 | tXS = 216 37 | tXP = 5 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 55 43 | IPP0 = 0.0 44 | IDD2P = 18 45 | IDD2N = 32 46 | IDD3P = 38 47 | IDD3N = 38 48 | IDD4W = 118 49 | IDD4R = 147 50 | IDD5AB = 235 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 800000 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_4Gb_x4_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 2048 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 9 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 243 19 | tRFC2 = 243 20 | tRFC4 = 243 21 | REFI = 7290 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 5 25 | tRRD_L = 5 26 | tWTR_S = 7 27 | tWTR_L = 7 28 | tFAW = 26 29 | tWR = 15 30 | tWR2 = 15 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 253 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 62 43 | IPP0 = 0.0 44 | IDD2P = 18 45 | IDD2N = 35 46 | IDD3P = 41 47 | IDD3N = 41 48 | IDD4W = 133 49 | IDD4R = 164 50 | IDD5AB = 242 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_4Gb_x8_1600.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.25 12 | AL = 0 13 | CL = 11 14 | CWL = 8 15 | tRCD = 11 16 | tRP = 11 17 | tRAS = 28 18 | tRFC = 208 19 | tRFC2 = 208 20 | tRFC4 = 208 21 | REFI = 6240 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 5 25 | tRRD_L = 5 26 | tWTR_S = 6 27 | tWTR_L = 6 28 | tFAW = 24 29 | tWR = 12 30 | tWR2 = 12 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 4 35 | tCKESR = 5 36 | tXS = 216 37 | tXP = 5 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 55 43 | IPP0 = 0.0 44 | IDD2P = 18 45 | IDD2N = 32 46 | IDD3P = 38 47 | IDD3N = 38 48 | IDD4W = 125 49 | IDD4R = 157 50 | IDD5AB = 235 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 800000 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_4Gb_x8_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 9 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 243 19 | tRFC2 = 243 20 | tRFC4 = 243 21 | REFI = 7290 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 5 25 | tRRD_L = 5 26 | tWTR_S = 7 27 | tWTR_L = 7 28 | tFAW = 26 29 | tWR = 15 30 | tWR2 = 15 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 253 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 62 43 | IPP0 = 0.0 44 | IDD2P = 18 45 | IDD2N = 35 46 | IDD3P = 41 47 | IDD3N = 41 48 | IDD4W = 141 49 | IDD4R = 174 50 | IDD5AB = 242 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_8Gb_x16_1600.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.25 12 | AL = 0 13 | CL = 11 14 | CWL = 8 15 | tRCD = 11 16 | tRP = 11 17 | tRAS = 28 18 | tRFC = 280 19 | tRFC2 = 280 20 | tRFC4 = 280 21 | REFI = 6240 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 6 25 | tRRD_L = 6 26 | tWTR_S = 6 27 | tWTR_L = 6 28 | tFAW = 32 29 | tWR = 12 30 | tWR2 = 12 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 4 35 | tCKESR = 5 36 | tXS = 288 37 | tXP = 5 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 67 43 | IPP0 = 0.0 44 | IDD2P = 11 45 | IDD2N = 36 46 | IDD3P = 36 47 | IDD3N = 51 48 | IDD4W = 185 49 | IDD4R = 185 50 | IDD5AB = 270 51 | IDD6x = 24 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 800000 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_8Gb_x16_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 9 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 328 19 | tRFC2 = 328 20 | tRFC4 = 328 21 | REFI = 7290 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 6 25 | tRRD_L = 6 26 | tWTR_S = 7 27 | tWTR_L = 7 28 | tFAW = 33 29 | tWR = 15 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 338 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 69 43 | IPP0 = 0.0 44 | IDD2P = 11 45 | IDD2N = 38 46 | IDD3P = 38 47 | IDD3N = 53 48 | IDD4W = 195 49 | IDD4R = 195 50 | IDD5AB = 275 51 | IDD6x = 24 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_8Gb_x4_1600.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 4096 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.25 12 | AL = 0 13 | CL = 11 14 | CWL = 8 15 | tRCD = 11 16 | tRP = 11 17 | tRAS = 28 18 | tRFC = 280 19 | tRFC2 = 280 20 | tRFC4 = 280 21 | REFI = 6240 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 6 25 | tRRD_L = 6 26 | tWTR_S = 6 27 | tWTR_L = 6 28 | tFAW = 32 29 | tWR = 12 30 | tWR2 = 12 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 4 35 | tCKESR = 5 36 | tXS = 288 37 | tXP = 5 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 67 43 | IPP0 = 0.0 44 | IDD2P = 11 45 | IDD2N = 36 46 | IDD3P = 36 47 | IDD3N = 51 48 | IDD4W = 125 49 | IDD4R = 125 50 | IDD5AB = 245 51 | IDD6x = 24 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 800000 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_8Gb_x4_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 4096 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 9 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 328 19 | tRFC2 = 328 20 | tRFC4 = 328 21 | REFI = 7290 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 6 25 | tRRD_L = 6 26 | tWTR_S = 7 27 | tWTR_L = 7 28 | tFAW = 33 29 | tWR = 15 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 338 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 69 43 | IPP0 = 0.0 44 | IDD2P = 11 45 | IDD2N = 38 46 | IDD3P = 38 47 | IDD3N = 53 48 | IDD4W = 135 49 | IDD4R = 135 50 | IDD5AB = 250 51 | IDD6x = 24 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_8Gb_x8_1600.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 2048 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.25 12 | AL = 0 13 | CL = 11 14 | CWL = 8 15 | tRCD = 11 16 | tRP = 11 17 | tRAS = 28 18 | tRFC = 280 19 | tRFC2 = 280 20 | tRFC4 = 280 21 | REFI = 6240 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 6 25 | tRRD_L = 6 26 | tWTR_S = 6 27 | tWTR_L = 6 28 | tFAW = 32 29 | tWR = 12 30 | tWR2 = 12 31 | tRTP = 6 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 4 35 | tCKESR = 5 36 | tXS = 288 37 | tXP = 5 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 67 43 | IPP0 = 0.0 44 | IDD2P = 11 45 | IDD2N = 36 46 | IDD3P = 36 47 | IDD3N = 51 48 | IDD4W = 125 49 | IDD4R = 125 50 | IDD5AB = 245 51 | IDD6x = 24 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 800000 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR3_8Gb_x8_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 65536 6 | columns = 2048 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 9 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 328 19 | tRFC2 = 328 20 | tRFC4 = 328 21 | REFI = 7290 22 | tRPRE = 0 23 | tWPRE = 0 24 | tRRD_S = 6 25 | tRRD_L = 6 26 | tWTR_S = 7 27 | tWTR_L = 7 28 | tFAW = 33 29 | tWR = 15 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 4 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 338 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.35 42 | IDD0 = 69 43 | IPP0 = 0.0 44 | IDD2P = 11 45 | IDD2N = 38 46 | IDD3P = 38 47 | IDD3N = 53 48 | IDD4W = 135 49 | IDD4R = 135 50 | IDD5AB = 250 51 | IDD6x = 24 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x16_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 10 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 243 19 | tRFC2 = 150 20 | tRFC4 = 103 21 | tREFI = 7285 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 5 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 7 28 | tFAW = 28 29 | tWR = 14 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 5 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 253 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.6 44 | IDD2P = 27 45 | IDD2N = 40 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 220 49 | IDD4R = 180 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x16_2133.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 16 14 | CWL = 11 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 36 18 | tRFC = 278 19 | tRFC2 = 171 20 | tRFC4 = 118 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 6 25 | tRRD_L = 7 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 32 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 289 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.6 44 | IDD2P = 27 45 | IDD2N = 42 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 250 49 | IDD4R = 195 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x16_2133_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 15 14 | CWL = 11 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 36 18 | tRFC = 278 19 | tRFC2 = 171 20 | tRFC4 = 118 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 6 25 | tRRD_L = 7 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 32 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 289 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.6 44 | IDD2P = 27 45 | IDD2N = 42 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 250 49 | IDD4R = 195 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x16_2400.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 17 14 | CWL = 12 15 | tRCD = 17 16 | tRP = 17 17 | tRAS = 39 18 | tRFC = 312 19 | tRFC2 = 192 20 | tRFC4 = 132 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 8 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 36 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 324 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.6 44 | IDD2P = 29 45 | IDD2N = 45 46 | IDD3P = 40 47 | IDD3N = 60 48 | IDD4W = 285 49 | IDD4R = 205 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x16_2400_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 16 14 | CWL = 12 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 39 18 | tRFC = 312 19 | tRFC2 = 192 20 | tRFC4 = 132 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 8 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 36 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 324 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.6 44 | IDD2P = 29 45 | IDD2N = 45 46 | IDD3P = 40 47 | IDD3N = 60 48 | IDD4W = 285 49 | IDD4R = 205 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x16_2666.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 19 14 | CWL = 14 15 | tRCD = 19 16 | tRP = 19 17 | tRAS = 43 18 | tRFC = 347 19 | tRFC2 = 214 20 | tRFC4 = 147 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 9 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 40 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 360 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 70 43 | IPP0 = 3.6 44 | IDD2P = 34 45 | IDD2N = 50 46 | IDD3P = 40 47 | IDD3N = 65 48 | IDD4W = 310 49 | IDD4R = 225 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x16_2666_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 18 14 | CWL = 14 15 | tRCD = 18 16 | tRP = 18 17 | tRAS = 43 18 | tRFC = 347 19 | tRFC2 = 214 20 | tRFC4 = 147 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 9 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 40 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 360 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 70 43 | IPP0 = 3.6 44 | IDD2P = 34 45 | IDD2N = 50 46 | IDD3P = 40 47 | IDD3N = 65 48 | IDD4W = 310 49 | IDD4R = 225 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 4096 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x4_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 10 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 243 19 | tRFC2 = 150 20 | tRFC4 = 103 21 | tREFI = 7285 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 5 26 | tWTR_S = 3 27 | tWTR_L = 7 28 | tFAW = 16 29 | tWR = 14 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 5 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 253 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 55 43 | IPP0 = 3.0 44 | IDD2P = 27 45 | IDD2N = 40 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 140 49 | IDD4R = 125 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x4_2133.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 16 14 | CWL = 11 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 36 18 | tRFC = 278 19 | tRFC2 = 171 20 | tRFC4 = 118 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 16 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 289 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 55 43 | IPP0 = 3.0 44 | IDD2P = 27 45 | IDD2N = 42 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 155 49 | IDD4R = 135 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x4_2133_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 15 14 | CWL = 11 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 36 18 | tRFC = 278 19 | tRFC2 = 171 20 | tRFC4 = 118 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 16 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 289 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 55 43 | IPP0 = 3.0 44 | IDD2P = 27 45 | IDD2N = 42 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 155 49 | IDD4R = 135 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x4_2400.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 17 14 | CWL = 12 15 | tRCD = 17 16 | tRP = 17 17 | tRAS = 39 18 | tRFC = 312 19 | tRFC2 = 192 20 | tRFC4 = 132 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 16 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 324 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 60 43 | IPP0 = 3.0 44 | IDD2P = 29 45 | IDD2N = 45 46 | IDD3P = 40 47 | IDD3N = 60 48 | IDD4W = 175 49 | IDD4R = 145 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | cmd_queue_size = 8 60 | trans_queue_size = 32 61 | refresh_policy = RANK_LEVEL_STAGGERED 62 | row_buf_policy = OPEN_PAGE 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x4_2400_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 16 14 | CWL = 12 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 39 18 | tRFC = 312 19 | tRFC2 = 192 20 | tRFC4 = 132 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 16 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 324 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 60 43 | IPP0 = 3.0 44 | IDD2P = 29 45 | IDD2N = 45 46 | IDD3P = 40 47 | IDD3N = 60 48 | IDD4W = 175 49 | IDD4R = 145 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x4_2666.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 19 14 | CWL = 14 15 | tRCD = 19 16 | tRP = 19 17 | tRAS = 43 18 | tRFC = 347 19 | tRFC2 = 214 20 | tRFC4 = 147 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 16 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 360 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.0 44 | IDD2P = 34 45 | IDD2N = 50 46 | IDD3P = 40 47 | IDD3N = 65 48 | IDD4W = 195 49 | IDD4R = 170 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x4_2666_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 18 14 | CWL = 14 15 | tRCD = 18 16 | tRP = 18 17 | tRAS = 43 18 | tRFC = 347 19 | tRFC2 = 214 20 | tRFC4 = 147 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 16 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 360 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.0 44 | IDD2P = 34 45 | IDD2N = 50 46 | IDD3P = 40 47 | IDD3N = 65 48 | IDD4W = 195 49 | IDD4R = 170 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x8_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 10 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 243 19 | tRFC2 = 150 20 | tRFC4 = 103 21 | tREFI = 7285 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 5 26 | tWTR_S = 3 27 | tWTR_L = 7 28 | tFAW = 22 29 | tWR = 14 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 5 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 253 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 55 43 | IPP0 = 3.0 44 | IDD2P = 27 45 | IDD2N = 40 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 140 49 | IDD4R = 125 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x8_2133.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 16 14 | CWL = 11 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 36 18 | tRFC = 278 19 | tRFC2 = 171 20 | tRFC4 = 118 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 23 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 289 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 55 43 | IPP0 = 3.0 44 | IDD2P = 27 45 | IDD2N = 42 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 155 49 | IDD4R = 135 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x8_2133_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 15 14 | CWL = 11 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 36 18 | tRFC = 278 19 | tRFC2 = 171 20 | tRFC4 = 118 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 23 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 289 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 55 43 | IPP0 = 3.0 44 | IDD2P = 27 45 | IDD2N = 42 46 | IDD3P = 40 47 | IDD3N = 55 48 | IDD4W = 155 49 | IDD4R = 135 50 | IDD5AB = 170 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x8_2400.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 17 14 | CWL = 12 15 | tRCD = 17 16 | tRP = 17 17 | tRAS = 39 18 | tRFC = 312 19 | tRFC2 = 192 20 | tRFC4 = 132 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 26 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 324 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 60 43 | IPP0 = 3.0 44 | IDD2P = 29 45 | IDD2N = 45 46 | IDD3P = 40 47 | IDD3N = 60 48 | IDD4W = 175 49 | IDD4R = 145 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x8_2400_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 16 14 | CWL = 12 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 39 18 | tRFC = 312 19 | tRFC2 = 192 20 | tRFC4 = 132 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 26 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 324 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 60 43 | IPP0 = 3.0 44 | IDD2P = 29 45 | IDD2N = 45 46 | IDD3P = 40 47 | IDD3N = 60 48 | IDD4W = 175 49 | IDD4R = 145 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x8_2666.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 19 14 | CWL = 14 15 | tRCD = 19 16 | tRP = 19 17 | tRAS = 43 18 | tRFC = 347 19 | tRFC2 = 214 20 | tRFC4 = 147 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 28 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 360 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.0 44 | IDD2P = 34 45 | IDD2N = 50 46 | IDD3P = 40 47 | IDD3N = 65 48 | IDD4W = 195 49 | IDD4R = 170 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_4Gb_x8_2666_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 18 14 | CWL = 14 15 | tRCD = 18 16 | tRP = 18 17 | tRAS = 43 18 | tRFC = 347 19 | tRFC2 = 214 20 | tRFC4 = 147 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 28 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 360 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 65 43 | IPP0 = 3.0 44 | IDD2P = 34 45 | IDD2N = 50 46 | IDD3P = 40 47 | IDD3N = 65 48 | IDD4W = 195 49 | IDD4R = 170 50 | IDD5AB = 175 51 | IDD6x = 20 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 10 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 327 19 | tRFC2 = 243 20 | tRFC4 = 150 21 | tREFI = 7285 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 5 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 7 28 | tFAW = 28 29 | tWR = 14 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 5 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 337 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 75 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 39 47 | IDD3N = 44 48 | IDD4W = 225 49 | IDD4R = 225 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2133.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 16 14 | CWL = 11 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 36 18 | tRFC = 374 19 | tRFC2 = 278 20 | tRFC4 = 171 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 6 25 | tRRD_L = 7 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 32 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 385 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 75 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 39 47 | IDD3N = 44 48 | IDD4W = 225 49 | IDD4R = 225 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2133_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 15 14 | CWL = 11 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 36 18 | tRFC = 374 19 | tRFC2 = 278 20 | tRFC4 = 171 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 6 25 | tRRD_L = 7 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 32 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 385 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 75 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 39 47 | IDD3N = 44 48 | IDD4W = 225 49 | IDD4R = 225 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2400.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 17 14 | CWL = 12 15 | tRCD = 17 16 | tRP = 17 17 | tRAS = 39 18 | tRFC = 420 19 | tRFC2 = 312 20 | tRFC4 = 192 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 8 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 36 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 432 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 80 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 34 46 | IDD3P = 41 47 | IDD3N = 47 48 | IDD4W = 228 49 | IDD4R = 243 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2400_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 16 14 | CWL = 12 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 39 18 | tRFC = 420 19 | tRFC2 = 312 20 | tRFC4 = 192 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 8 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 36 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 432 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 80 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 34 46 | IDD3P = 41 47 | IDD3N = 47 48 | IDD4W = 228 49 | IDD4R = 243 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2666.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 19 14 | CWL = 14 15 | tRCD = 19 16 | tRP = 19 17 | tRAS = 43 18 | tRFC = 467 19 | tRFC2 = 347 20 | tRFC4 = 214 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 9 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 40 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 480 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 85 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 35 46 | IDD3P = 43 47 | IDD3N = 50 48 | IDD4W = 244 49 | IDD4R = 263 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2666_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 18 14 | CWL = 14 15 | tRCD = 18 16 | tRP = 18 17 | tRAS = 43 18 | tRFC = 467 19 | tRFC2 = 347 20 | tRFC4 = 214 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 7 25 | tRRD_L = 9 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 40 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 480 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 85 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 35 46 | IDD3P = 43 47 | IDD3N = 50 48 | IDD4W = 244 49 | IDD4R = 263 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2933.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.68 12 | AL = 0 13 | CL = 21 14 | CWL = 16 15 | tRCD = 21 16 | tRP = 21 17 | tRAS = 47 18 | tRFC = 514 19 | tRFC2 = 382 20 | tRFC4 = 235 21 | tREFI = 11439 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 8 25 | tRRD_L = 10 26 | tWTR_S = 4 27 | tWTR_L = 11 28 | tFAW = 44 29 | tWR = 22 30 | tWR2 = 23 31 | tRTP = 11 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 528 37 | tXP = 9 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 90 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 36 46 | IDD3P = 45 47 | IDD3N = 53 48 | IDD4W = 261 49 | IDD4R = 283 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1470588 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_2933_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.68 12 | AL = 0 13 | CL = 20 14 | CWL = 16 15 | tRCD = 20 16 | tRP = 20 17 | tRAS = 47 18 | tRFC = 514 19 | tRFC2 = 382 20 | tRFC4 = 235 21 | tREFI = 11439 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 8 25 | tRRD_L = 10 26 | tWTR_S = 4 27 | tWTR_L = 11 28 | tFAW = 44 29 | tWR = 22 30 | tWR2 = 23 31 | tRTP = 11 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 528 37 | tXP = 9 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 90 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 36 46 | IDD3P = 45 47 | IDD3N = 53 48 | IDD4W = 261 49 | IDD4R = 283 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1470588 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x16_3200.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.63 12 | AL = 0 13 | CL = 22 14 | CWL = 16 15 | tRCD = 22 16 | tRP = 22 17 | tRAS = 52 18 | tRFC = 560 19 | tRFC2 = 416 20 | tRFC4 = 256 21 | tREFI = 12480 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 9 25 | tRRD_L = 11 26 | tWTR_S = 4 27 | tWTR_L = 12 28 | tFAW = 48 29 | tWR = 24 30 | tWR2 = 25 31 | tRTP = 12 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 576 37 | tXP = 10 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 95 43 | IPP0 = 4.0 44 | IDD2P = 25 45 | IDD2N = 37 46 | IDD3P = 47 47 | IDD3N = 56 48 | IDD4W = 278 49 | IDD4R = 302 50 | IDD5AB = 280 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 8192 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1587301 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 10 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 327 19 | tRFC2 = 243 20 | tRFC4 = 150 21 | tREFI = 7285 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 5 26 | tWTR_S = 3 27 | tWTR_L = 7 28 | tFAW = 16 29 | tWR = 14 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 5 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 337 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 40 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 30 47 | IDD3N = 35 48 | IDD4W = 95 49 | IDD4R = 100 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2133.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 16 14 | CWL = 11 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 36 18 | tRFC = 374 19 | tRFC2 = 278 20 | tRFC4 = 171 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 16 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 385 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 40 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 30 47 | IDD3N = 35 48 | IDD4W = 95 49 | IDD4R = 100 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2133_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 15 14 | CWL = 11 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 36 18 | tRFC = 374 19 | tRFC2 = 278 20 | tRFC4 = 171 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 16 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 385 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 40 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 30 47 | IDD3N = 35 48 | IDD4W = 95 49 | IDD4R = 100 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2400.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 17 14 | CWL = 12 15 | tRCD = 17 16 | tRP = 17 17 | tRAS = 39 18 | tRFC = 420 19 | tRFC2 = 312 20 | tRFC4 = 192 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 16 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 432 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 43 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 34 46 | IDD3P = 32 47 | IDD3N = 38 48 | IDD4W = 103 49 | IDD4R = 110 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2400_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 16 14 | CWL = 12 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 39 18 | tRFC = 420 19 | tRFC2 = 312 20 | tRFC4 = 192 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 16 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 432 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 43 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 34 46 | IDD3P = 32 47 | IDD3N = 38 48 | IDD4W = 103 49 | IDD4R = 110 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2666.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 19 14 | CWL = 14 15 | tRCD = 19 16 | tRP = 19 17 | tRAS = 43 18 | tRFC = 467 19 | tRFC2 = 347 20 | tRFC4 = 214 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 16 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 480 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 46 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 35 46 | IDD3P = 34 47 | IDD3N = 41 48 | IDD4W = 112 49 | IDD4R = 121 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2666_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 18 14 | CWL = 14 15 | tRCD = 18 16 | tRP = 18 17 | tRAS = 43 18 | tRFC = 467 19 | tRFC2 = 347 20 | tRFC4 = 214 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 16 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 480 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 46 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 35 46 | IDD3P = 34 47 | IDD3N = 41 48 | IDD4W = 112 49 | IDD4R = 121 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2933.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.68 12 | AL = 0 13 | CL = 21 14 | CWL = 16 15 | tRCD = 21 16 | tRP = 21 17 | tRAS = 47 18 | tRFC = 514 19 | tRFC2 = 382 20 | tRFC4 = 235 21 | tREFI = 11439 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 8 26 | tWTR_S = 4 27 | tWTR_L = 11 28 | tFAW = 16 29 | tWR = 22 30 | tWR2 = 23 31 | tRTP = 11 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 528 37 | tXP = 9 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 49 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 36 46 | IDD3P = 36 47 | IDD3N = 44 48 | IDD4W = 121 49 | IDD4R = 132 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1470588 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_2933_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.68 12 | AL = 0 13 | CL = 20 14 | CWL = 16 15 | tRCD = 20 16 | tRP = 20 17 | tRAS = 47 18 | tRFC = 514 19 | tRFC2 = 382 20 | tRFC4 = 235 21 | tREFI = 11439 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 8 26 | tWTR_S = 4 27 | tWTR_L = 11 28 | tFAW = 16 29 | tWR = 22 30 | tWR2 = 23 31 | tRTP = 11 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 528 37 | tXP = 9 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 49 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 36 46 | IDD3P = 36 47 | IDD3N = 44 48 | IDD4W = 121 49 | IDD4R = 132 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1470588 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x4_3200.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 131072 6 | columns = 1024 7 | device_width = 4 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.63 12 | AL = 0 13 | CL = 22 14 | CWL = 16 15 | tRCD = 22 16 | tRP = 22 17 | tRAS = 52 18 | tRFC = 560 19 | tRFC2 = 416 20 | tRFC4 = 256 21 | tREFI = 12480 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 8 26 | tWTR_S = 4 27 | tWTR_L = 12 28 | tFAW = 16 29 | tWR = 24 30 | tWR2 = 25 31 | tRTP = 12 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 576 37 | tXP = 10 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 52 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 37 46 | IDD3P = 38 47 | IDD3N = 47 48 | IDD4W = 130 49 | IDD4R = 143 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 32768 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1587301 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 13 14 | CWL = 10 15 | tRCD = 13 16 | tRP = 13 17 | tRAS = 32 18 | tRFC = 327 19 | tRFC2 = 243 20 | tRFC4 = 150 21 | tREFI = 7285 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 5 26 | tWTR_S = 3 27 | tWTR_L = 7 28 | tFAW = 22 29 | tWR = 14 30 | tWR2 = 15 31 | tRTP = 7 32 | tCCD_S = 4 33 | tCCD_L = 5 34 | tCKE = 5 35 | tCKESR = 6 36 | tXS = 337 37 | tXP = 6 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 45 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 35 47 | IDD3N = 40 48 | IDD4W = 115 49 | IDD4R = 125 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 934579 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2133.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 16 14 | CWL = 11 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 36 18 | tRFC = 374 19 | tRFC2 = 278 20 | tRFC4 = 171 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 23 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 385 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 45 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 35 47 | IDD3N = 40 48 | IDD4W = 115 49 | IDD4R = 125 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2133_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.94 12 | AL = 0 13 | CL = 15 14 | CWL = 11 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 36 18 | tRFC = 374 19 | tRFC2 = 278 20 | tRFC4 = 171 21 | tREFI = 8328 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 8 28 | tFAW = 23 29 | tWR = 16 30 | tWR2 = 17 31 | tRTP = 8 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 385 37 | tXP = 7 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 45 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 33 46 | IDD3P = 35 47 | IDD3N = 40 48 | IDD4W = 115 49 | IDD4R = 125 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1063829 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2400.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 17 14 | CWL = 12 15 | tRCD = 17 16 | tRP = 17 17 | tRAS = 39 18 | tRFC = 420 19 | tRFC2 = 312 20 | tRFC4 = 192 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 26 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 432 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 48 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 34 46 | IDD3P = 37 47 | IDD3N = 43 48 | IDD4W = 123 49 | IDD4R = 135 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | [thermal] 69 | loc_mapping = 33,33,32-31,30-29,26:13-27-28,12:3 70 | power_epoch_period = 100000; power epoch period (# cycle) 71 | chip_dim_x = 0.008; chip size in x dimension [m] 72 | chip_dim_y = 0.008; chip size in y dimension [m] 73 | amb_temp = 40; The ambient temperature in [C] 74 | mat_dim_x = 512; 75 | mat_dim_y = 512; 76 | bank_order = 0; 0: x direction first, 1: y direction first 77 | 78 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2400_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 16 14 | CWL = 12 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 39 18 | tRFC = 420 19 | tRFC2 = 312 20 | tRFC4 = 192 21 | tREFI = 9360 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 26 29 | tWR = 18 30 | tWR2 = 19 31 | tRTP = 9 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 432 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 48 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 34 46 | IDD3P = 37 47 | IDD3N = 43 48 | IDD4W = 123 49 | IDD4R = 135 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1204819 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2666.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 19 14 | CWL = 14 15 | tRCD = 19 16 | tRP = 19 17 | tRAS = 43 18 | tRFC = 467 19 | tRFC2 = 347 20 | tRFC4 = 214 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 28 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 480 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 51 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 35 46 | IDD3P = 39 47 | IDD3N = 46 48 | IDD4W = 132 49 | IDD4R = 146 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2666_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.75 12 | AL = 0 13 | CL = 18 14 | CWL = 14 15 | tRCD = 18 16 | tRP = 18 17 | tRAS = 43 18 | tRFC = 467 19 | tRFC2 = 347 20 | tRFC4 = 214 21 | tREFI = 10398 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 7 26 | tWTR_S = 4 27 | tWTR_L = 10 28 | tFAW = 28 29 | tWR = 20 30 | tWR2 = 21 31 | tRTP = 10 32 | tCCD_S = 4 33 | tCCD_L = 7 34 | tCKE = 7 35 | tCKESR = 8 36 | tXS = 480 37 | tXP = 8 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 51 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 35 46 | IDD3P = 39 47 | IDD3N = 46 48 | IDD4W = 132 49 | IDD4R = 146 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1333333 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2933.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.68 12 | AL = 0 13 | CL = 21 14 | CWL = 16 15 | tRCD = 21 16 | tRP = 21 17 | tRAS = 47 18 | tRFC = 514 19 | tRFC2 = 382 20 | tRFC4 = 235 21 | tREFI = 11439 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 8 26 | tWTR_S = 4 27 | tWTR_L = 11 28 | tFAW = 31 29 | tWR = 22 30 | tWR2 = 23 31 | tRTP = 11 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 528 37 | tXP = 9 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 54 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 36 46 | IDD3P = 41 47 | IDD3N = 49 48 | IDD4W = 141 49 | IDD4R = 157 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1470588 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_2933_2.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.68 12 | AL = 0 13 | CL = 20 14 | CWL = 16 15 | tRCD = 20 16 | tRP = 20 17 | tRAS = 47 18 | tRFC = 514 19 | tRFC2 = 382 20 | tRFC4 = 235 21 | tREFI = 11439 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 8 26 | tWTR_S = 4 27 | tWTR_L = 11 28 | tFAW = 31 29 | tWR = 22 30 | tWR2 = 23 31 | tRTP = 11 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 528 37 | tXP = 9 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 54 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 36 46 | IDD3P = 41 47 | IDD3N = 49 48 | IDD4W = 141 49 | IDD4R = 157 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1470588 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/DDR4_8Gb_x8_3200.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.63 12 | AL = 0 13 | CL = 22 14 | CWL = 16 15 | tRCD = 22 16 | tRP = 22 17 | tRAS = 52 18 | tRFC = 560 19 | tRFC2 = 416 20 | tRFC4 = 256 21 | tREFI = 12480 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 8 26 | tWTR_S = 4 27 | tWTR_L = 12 28 | tFAW = 34 29 | tWR = 24 30 | tWR2 = 25 31 | tRTP = 12 32 | tCCD_S = 4 33 | tCCD_L = 8 34 | tCKE = 8 35 | tCKESR = 9 36 | tXS = 576 37 | tXP = 10 38 | tRTRS = 1 39 | 40 | [power] 41 | VDD = 1.2 42 | IDD0 = 57 43 | IPP0 = 3.0 44 | IDD2P = 25 45 | IDD2N = 37 46 | IDD3P = 43 47 | IDD3N = 52 48 | IDD4W = 150 49 | IDD4R = 168 50 | IDD5AB = 250 51 | IDD6x = 30 52 | 53 | [system] 54 | channel_size = 16384 55 | channels = 1 56 | bus_width = 64 57 | address_mapping = rochrababgco 58 | queue_structure = PER_BANK 59 | refresh_policy = RANK_LEVEL_STAGGERED 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1587301 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/GDDR5X_8Gb_x32.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = GDDR5X 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 16384 6 | columns = 64 7 | device_width = 32 8 | BL = 16 9 | bankgroup_enable = false 10 | 11 | [timing] 12 | tCK = 0.666 (1/1.5) 13 | CL = 24 14 | CWL = 7 15 | tRCDRD = 18 16 | tRCDWR = 15 17 | tRP = 18 18 | tRAS = 42 19 | tRFC = 98 20 | tREFI = 11699 21 | tRPRE = 1; read preamble 22 | tWPRE = 1; TODO figure this out, should be 1 or 2 23 | tRRD_S = 9 24 | tRRD_L = 9 25 | tWTR_S = 8 26 | tWTR_L = 8 27 | tFAW = 35 28 | tWR = 18 29 | tCCD_S = 2 30 | tCCD_L = 3 31 | tXS = 116 32 | tCKE = 16 33 | tCKSRE = 8 34 | tXP = 12 35 | tRTRS = 0 36 | tRTP_L = 3 37 | tRTP_S = 3 38 | tPPD = 2 39 | t32AW = 280 40 | 41 | [power] 42 | VDD = 1.35 43 | IDD0 = 500 44 | IDD2P = 220 45 | IDD2N = 260 46 | IDD3P = 330 47 | IDD3N = 480 48 | IDD4W = 2320 49 | IDD4R = 2160 50 | IDD5AB = 600 51 | IDD5PB = 60 52 | IDD6x = 65 53 | 54 | [system] 55 | channel_size = 4096 56 | channels = 1 57 | bus_width = 128 58 | address_mapping = rochrababgco 59 | queue_structure = PER_BANK 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1501501 66 | output_level = 1 67 | 68 | [thermal] 69 | power_epoch_period = 1000; power epoch period (# cycle) 70 | chip_dim_x = 0.008; chip size in x dimension [m] 71 | chip_dim_y = 0.008; chip size in y dimension [m] 72 | amb_temp = 40; The ambient temperature in [C] 73 | mat_dim_x = 512; 74 | mat_dim_y = 512; 75 | bank_order = 1; 0: x direction first, 1: y direction first 76 | 77 | -------------------------------------------------------------------------------- /configs/GDDR5_1Gb_x32.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = GDDR5 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 4096 6 | columns = 64 7 | device_width = 32 8 | BL = 8 9 | bankgroup_enable = false 10 | 11 | [timing] 12 | tCK = 0.667 13 | CL = 24 14 | CWL = 7 15 | tRCDRD = 18 16 | tRCDWR = 15 17 | tRP = 18 18 | tRAS = 42 19 | tRFC = 98 20 | tREFI = 11699 21 | tRPRE = 1; read preamble 22 | tWPRE = 1; TODO figure this out, should be 1 or 2 23 | tRRD_S = 9 24 | tRRD_L = 9 25 | tWTR_S = 8 26 | tWTR_L = 8 27 | tFAW = 35 28 | tWR = 18 29 | tCCD_S = 2 30 | tCCD_L = 3 31 | tXS = 116 32 | tCKE = 16 33 | tCKESR = 8 34 | tXP = 12 35 | tRTRS = 0 36 | tRTP_L = 3 37 | tRTP_S = 3 38 | tPPD = 2 39 | t32AW = 280 40 | 41 | [power] 42 | VDD = 1.5 43 | IDD0 = 490 44 | IDD2P = 210 45 | IDD2N = 250 46 | IDD3P = 310 47 | IDD3N = 450 48 | IDD4W = 1160 49 | IDD4R = 1080 50 | IDD5AB = 450 51 | IDD5PB = 45 52 | IDD6x = 60 53 | 54 | [system] 55 | channel_size = 1024 56 | channels = 1 57 | bus_width = 256 58 | address_mapping = rochrababgco 59 | queue_structure = PER_BANK 60 | row_buf_policy = OPEN_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | 64 | [other] 65 | epoch_period = 1499250 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/GDDR5_8Gb_x32.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = GDDR5 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 16384 6 | columns = 128 7 | device_width = 32 8 | BL = 8 9 | bankgroup_enable = false 10 | 11 | [timing] 12 | tCK = 0.667 13 | CL = 24 14 | CWL = 7 15 | tRCDRD = 24 16 | tRCDWR = 20 17 | tRP = 24 18 | tRAS = 56 19 | tRFC = 74 20 | tREFI = 3800 21 | tRPRE = 1; read preamble 22 | tWPRE = 1; TODO figure this out, should be 1 or 2 23 | tRRD_S = 10 24 | tRRD_L = 10 25 | tWTR_S = 10 26 | tWTR_L = 10 27 | tFAW = 40 28 | tWR = 24 29 | tCCD_S = 2 30 | tCCD_L = 3 31 | tXS = 94 32 | tCKESR = 2 33 | tXP = 12 34 | tRTRS = 1 35 | tRTP_L = 2 36 | tRTP_S = 2 37 | tPPD = 5 38 | t32AW = 360 39 | tRFCb = 30 40 | tREFIb = 238 41 | 42 | [power] 43 | VDD = 1.5 44 | IDD0 = 71 45 | IDD2P = 45 46 | IDD2N = 60 47 | IDD3P = 50 48 | IDD3N = 61 49 | IDD4W = 231 50 | IDD4R = 248 51 | IDD5AB = 286 52 | IDD5PB = 45 53 | IDD6x = 35 54 | 55 | [system] 56 | channel_size = 4096 57 | channels = 1 58 | bus_width = 128 59 | address_mapping = rochrababgco 60 | queue_structure = PER_BANK 61 | row_buf_policy = OPEN_PAGE 62 | cmd_queue_size = 8 63 | trans_queue_size = 32 64 | 65 | [other] 66 | epoch_period = 1499250 67 | output_level = 1 68 | 69 | -------------------------------------------------------------------------------- /configs/GDDR6_8Gb_x16.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = GDDR6 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 16384 6 | columns = 128 7 | device_width = 16 8 | BL = 16 9 | bankgroup_enable = false 10 | 11 | [timing] 12 | tCK = 0.66 13 | CL = 24 14 | CWL = 16 15 | tRCDRD = 24 16 | tRCDWR = 20 17 | tRP = 24 18 | tRAS = 54 19 | tRFC = 126 20 | tREFI = 11862 21 | tRPRE = 1; read preamble 22 | tWPRE = 1; TODO figure this out, should be 1 or 2 23 | tRRD_S = 9 24 | tRRD_L = 9 25 | tWTR_S = 7 26 | tWTR_L = 7 27 | tFAW = 32 28 | tWR = 16 29 | tCCD_S = 3 30 | tCCD_L = 4 31 | tXS = 132 32 | tCKESR = 8 33 | tXP = 12 34 | tRTRS = 1 35 | tRTP_L = 3 36 | tRTP_S = 3 37 | tPPD = 2 38 | t32AW = 420 39 | tRFCb = 30 40 | tREFIb = 238 41 | 42 | [power] 43 | VDD = 1.35 44 | IDD0 = 71 45 | IDD2P = 45 46 | IDD2N = 60 47 | IDD3P = 50 48 | IDD3N = 61 49 | IDD4W = 231 50 | IDD4R = 248 51 | IDD5AB = 286 52 | IDD5PB = 45 53 | IDD6x = 35 54 | 55 | [system] 56 | channel_size = 4096 57 | channels = 1 58 | bus_width = 128 59 | address_mapping = rochrababgco 60 | queue_structure = PER_BANK 61 | row_buf_policy = OPEN_PAGE 62 | cmd_queue_size = 8 63 | trans_queue_size = 32 64 | 65 | [other] 66 | epoch_period = 1499250 67 | output_level = 1 68 | 69 | ;16n prefetch -------------------------------------------------------------------------------- /configs/HBM1_4Gb_x128.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = HBM 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 16384 6 | columns = 64 7 | device_width = 128 8 | BL = 4 9 | num_dies = 4 10 | 11 | [timing] 12 | tCK = 2 13 | CL = 7 14 | CWL = 2 15 | tRCDRD = 7 16 | tRCDWR = 7 17 | tRP = 7 18 | tRAS = 17 19 | tRFC = 130 20 | tREFI = 1950 21 | tREFIb = 64 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 2 25 | tRRD_L = 3 26 | tWTR_S = 3 27 | tWTR_L = 4 28 | tFAW = 15 29 | tWR = 8 30 | tCCD_S = 1 31 | tCCD_L = 1 32 | tXS = 134 33 | tCKE = 4 34 | tCKSRE = 5 35 | tXP = 4 36 | tRTP_L = 3 37 | tRTP_S = 2 38 | 39 | [power] 40 | VDD = 1.2 41 | IDD0 = 65 42 | IDD2P = 28 43 | IDD2N = 40 44 | IDD3P = 40 45 | IDD3N = 55 46 | IDD4W = 440 47 | IDD4R = 360 48 | IDD5AB = 250 49 | IDD6x = 31 50 | 51 | [system] 52 | channel_size = 512 53 | channels = 8 54 | bus_width = 128 55 | address_mapping = rorabgbachco 56 | queue_structure = PER_BANK 57 | row_buf_policy = OPEN_PAGE 58 | cmd_queue_size = 8 59 | trans_queue_size = 32 60 | unified_queue = False 61 | 62 | [other] 63 | epoch_period = 500000 64 | output_level = 1 65 | 66 | -------------------------------------------------------------------------------- /configs/HBM2_4Gb_x128.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = HBM 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 16384 6 | columns = 64 7 | device_width = 128 8 | BL = 4 9 | num_dies = 4 10 | 11 | [timing] 12 | tCK = 1 13 | CL = 14 14 | CWL = 4 15 | tRCDRD = 14 16 | tRCDWR = 14 17 | tRP = 14 18 | tRAS = 34 19 | tRFC = 260 20 | tREFI = 3900 21 | tREFIb = 128 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 6 27 | tWTR_L = 8 28 | tFAW = 30 29 | tWR = 16 30 | tCCD_S = 1 31 | tCCD_L = 2 32 | tXS = 268 33 | tCKE = 8 34 | tCKSRE = 10 35 | tXP = 8 36 | tRTP_L = 6 37 | tRTP_S = 4 38 | 39 | [power] 40 | VDD = 1.2 41 | IDD0 = 65 42 | IDD2P = 28 43 | IDD2N = 40 44 | IDD3P = 40 45 | IDD3N = 55 46 | IDD4W = 500 47 | IDD4R = 390 48 | IDD5AB = 250 49 | IDD6x = 31 50 | 51 | [system] 52 | channel_size = 512 53 | channels = 8 54 | bus_width = 128 55 | address_mapping = rorabgbachco 56 | queue_structure = PER_BANK 57 | row_buf_policy = OPEN_PAGE 58 | cmd_queue_size = 8 59 | trans_queue_size = 32 60 | unified_queue = False 61 | 62 | [other] 63 | epoch_period = 1000000 64 | output_level = 1 65 | 66 | -------------------------------------------------------------------------------- /configs/HBM2_8Gb_x128.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = HBM 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 32768 6 | columns = 64 7 | device_width = 128 8 | BL = 4 9 | num_dies = 4 10 | 11 | [timing] 12 | tCK = 1 13 | CL = 14 14 | CWL = 4 15 | tRCDRD = 14 16 | tRCDWR = 14 17 | tRP = 14 18 | tRAS = 34 19 | tRFC = 260 20 | tREFI = 3900 21 | tREFIb = 128 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 6 27 | tWTR_L = 8 28 | tFAW = 30 29 | tWR = 16 30 | tCCD_S = 1 31 | tCCD_L = 2 32 | tXS = 268 33 | tCKE = 8 34 | tCKSRE = 10 35 | tXP = 8 36 | tRTP_L = 6 37 | tRTP_S = 4 38 | 39 | [power] 40 | VDD = 1.2 41 | IDD0 = 65 42 | IDD2P = 28 43 | IDD2N = 40 44 | IDD3P = 40 45 | IDD3N = 55 46 | IDD4W = 500 47 | IDD4R = 390 48 | IDD5AB = 250 49 | IDD6x = 31 50 | 51 | [system] 52 | channel_size = 1024 53 | channels = 8 54 | bus_width = 128 55 | address_mapping = rorabgbachco 56 | queue_structure = PER_BANK 57 | row_buf_policy = OPEN_PAGE 58 | cmd_queue_size = 8 59 | trans_queue_size = 32 60 | unified_queue = False 61 | 62 | [other] 63 | epoch_period = 1000000 64 | output_level = 1 65 | 66 | -------------------------------------------------------------------------------- /configs/HBM_4Gb_x128.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = HBM 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 16384 6 | columns = 64 7 | device_width = 128 8 | BL = 4 9 | num_dies = 4 10 | 11 | [timing] 12 | tCK = 2 13 | AL = 0 14 | CL = 7 15 | CWL = 4 16 | tRCDRD = 7 17 | tRCDWR = 6 18 | tRP = 7 19 | tRAS = 17 20 | tRFC = 21 | tREFI = 1950 22 | tRPRE = 1; read preamble 23 | tWPRE = 1; TODO figure this out, should be 1 or 2 24 | tRRD_S = 4 25 | tRRD_L = 5 26 | tWTR_S = 2 27 | tWTR_L = 4 28 | tFAW = 20 29 | tWR = 8 30 | tCCD_S = 2 31 | tCCD_L = 3 32 | tXS = 0 33 | tCKSRE = 0 34 | tXP = 5 35 | tRTP_L = 7 36 | tRTP_S = 6 37 | tPPD = 5 38 | t32AW = 330 39 | tRFCb = 40 | tREFIb = 41 | tRREFD = 42 | tRFCPB = 43 | 44 | [power] 45 | VDD = 1.2 46 | IDD0 = 48 47 | IDD2P = 25 48 | IDD2N = 34 49 | IDD3P = 37 50 | IDD3N = 43 51 | IDD4W = 123 52 | IDD4R = 135 53 | IDD5AB = 250 54 | IDD6x = 31 55 | 56 | [system] 57 | channel_size = 512 58 | channels = 8 59 | bus_width = 128 60 | address_mapping = rorabgbachco 61 | queue_structure = PER_BANK 62 | row_buf_policy = OPEN_PAGE 63 | cmd_queue_size = 8 64 | trans_queue_size = 32 65 | unified_queue = False 66 | 67 | [other] 68 | epoch_period = 500000 69 | output_level = 1 70 | 71 | [thermal] 72 | power_epoch_period = 10000; power epoch period (# cycle) 73 | logic_bg_power = 5 74 | logic_max_power = 25 75 | chip_dim_x = 0.008; chip size in x dimension [m] 76 | chip_dim_y = 0.008; chip size in y dimension [m] 77 | amb_temp = 40; The ambient temperature in [C] 78 | mat_dim_x = 1024; 79 | mat_dim_y = 1024; 80 | bank_order = 1; 0: x direction first, 1: y direction first 81 | bank_layer_order = 0; 82 | 83 | -------------------------------------------------------------------------------- /configs/HMC2_8GB_4Lx16.ini: -------------------------------------------------------------------------------- 1 | [hmc] 2 | num_links = 4 3 | link_width = 16 4 | link_speed = 25000 5 | block_size = 64 6 | xbar_queue_depth = 32 7 | 8 | [dram_structure] 9 | protocol = HMC 10 | bankgroups = 1 11 | banks_per_group = 16 12 | rows = 65536 13 | columns = 64 14 | device_width = 32 15 | num_dies = 8 16 | 17 | [timing] 18 | tCK = 0.8 19 | CL = 17 20 | CWL = 17 21 | tRCD = 17 22 | tRP = 17 23 | tRAS = 34 24 | tRFC = 420 25 | tREFI = 9364; average periodic refresh interval, 3.9us 26 | tRRD_S = 6 27 | tRRD_L = 6 28 | tWTR_S = 3 29 | tWTR_L = 3 30 | tFAW = 27 31 | tWR = 19 32 | tCCD_S = 6 33 | tCCD_L = 6 34 | tXS = 12 35 | tCKSRE = 1 36 | tXP = 8 37 | tRTP_L = 10 38 | tRTP_S = 10 39 | tRTRS = 0 40 | 41 | [power] 42 | VDD = 1.2 43 | IDD0 = 25 44 | IDD2P = 17 45 | IDD2N = 19 46 | IDD3P = 20 47 | IDD3N = 21 48 | IDD4W = 61 49 | IDD4R = 64 50 | IDD5AB = 150 51 | IDD6x = 21 52 | 53 | [system] 54 | channel_size = 256 55 | channels = 32 56 | bus_width = 32 57 | address_mapping = rocorabgbach 58 | queue_structure = PER_BANK 59 | row_buf_policy = CLOSE_PAGE 60 | cmd_queue_size = 8 61 | trans_queue_size = 32 62 | unified_queue = True 63 | 64 | [thermal] 65 | power_epoch_period = 10000; power epoch period (# cycle) 66 | chip_dim_x = 0.008; chip size in x dimension [m] 67 | chip_dim_y = 0.008; chip size in y dimension [m] 68 | amb_temp = 40; The ambient temperature in [C] 69 | mat_dim_x = 512; 70 | mat_dim_y = 512; 71 | bank_order = 1; 0: x direction first, 1: y direction first 72 | bank_layer_order = 0; 73 | 74 | [other] 75 | epoch_period = 1250000 76 | output_level = 1 77 | 78 | -------------------------------------------------------------------------------- /configs/HMC_2GB_4Lx16.ini: -------------------------------------------------------------------------------- 1 | [hmc] 2 | num_links = 4 3 | link_width = 16 4 | link_speed = 10000 5 | block_size = 64 6 | xbar_queue_depth = 6 7 | 8 | [dram_structure] 9 | protocol = HMC 10 | bankgroups = 1 11 | banks_per_group = 8 12 | rows = 65536 13 | columns = 64 14 | device_width = 32 15 | num_dies = 4 16 | 17 | [timing] 18 | tCK = 0.8 19 | CL = 17 20 | CWL = 17 21 | tRCD = 17 22 | tRP = 17 23 | tRAS = 34 24 | tRFC = 420 25 | tREFI = 9364; average periodic refresh interval, 3.9us 26 | tRRD_S = 4 27 | tRRD_L = 4 28 | tWTR_S = 3 29 | tWTR_L = 3 30 | tFAW = 27 31 | tWR = 17 32 | tCCD_S = 6 33 | tCCD_L = 6 34 | tXS = 12 35 | tCKSRE = 1 36 | tXP = 8 37 | tRTP_L = 8 38 | tRTP_S = 8 39 | tRTRS = 0 40 | 41 | [power] 42 | VDD = 1.2 43 | IDD0 = 25 44 | IDD2P = 17 45 | IDD2N = 19 46 | IDD3P = 20 47 | IDD3N = 21 48 | IDD4W = 61 49 | IDD4R = 64 50 | IDD5AB = 150 51 | IDD6x = 21 52 | 53 | [system] 54 | channel_size = 128 55 | channels = 16 56 | bus_width = 32 57 | address_mapping = rocorabgbach 58 | queue_structure = PER_BANK 59 | row_buf_policy = CLOSE_PAGE 60 | cmd_queue_size = 8 61 | trans_queue_size = 32 62 | unified_queue = True 63 | 64 | [other] 65 | epoch_period = 1250000 66 | output_level = 1 67 | 68 | [thermal] 69 | power_epoch_period = 10000; power epoch period (# cycle) 70 | chip_dim_x = 0.008; chip size in x dimension [m] 71 | chip_dim_y = 0.008; chip size in y dimension [m] 72 | amb_temp = 40; The ambient temperature in [C] 73 | mat_dim_x = 512; 74 | mat_dim_y = 512; 75 | bank_order = 1; 0: x direction first, 1: y direction first 76 | bank_layer_order = 0; 77 | 78 | -------------------------------------------------------------------------------- /configs/HMC_2GB_4Lx16_dummy.ini: -------------------------------------------------------------------------------- 1 | [hmc] 2 | num_links = 4 3 | link_width = 16 4 | link_speed = 10000 5 | block_size = 128 6 | xbar_queue_depth = 6 7 | 8 | [dram_structure] 9 | protocol = HMC 10 | bankgroups = 1 11 | banks_per_group = 8 12 | rows = 65536 13 | columns = 64 14 | device_width = 32 15 | BL = 2 16 | num_dies = 4 17 | 18 | [timing] 19 | tCK = 0.8 20 | CL = 17 21 | CWL = 17 22 | tRCD = 17 23 | tRP = 17 24 | tRAS = 34 25 | tRFC = 420 26 | tREFI = 9364; average periodic refresh interval, 3.9us 27 | tRRD_S = 4 28 | tRRD_L = 4 29 | tWTR_S = 3 30 | tWTR_L = 3 31 | tFAW = 27 32 | tWR = 17 33 | tCCD_S = 6 34 | tCCD_L = 6 35 | tXS = 12 36 | tCKSRE = 1 37 | tXP = 8 38 | tRTP_L = 8 39 | tRTP_S = 8 40 | tRTRS = 0 41 | 42 | [power] 43 | VDD = 1.2 44 | IDD0 = 25 45 | IDD2P = 17 46 | IDD2N = 19 47 | IDD3P = 20 48 | IDD3N = 21 49 | IDD4W = 61 50 | IDD4R = 64 51 | IDD5AB = 150 52 | IDD6x = 21 53 | 54 | [system] 55 | channel_size = 128 56 | channels = 16 57 | bus_width = 32 58 | address_mapping = rocorabgbach 59 | queue_structure = PER_BANK 60 | row_buf_policy = CLOSE_PAGE 61 | cmd_queue_size = 8 62 | trans_queue_size = 32 63 | unified_queue = True 64 | 65 | [other] 66 | epoch_period = 1250000 67 | output_level = 1 68 | 69 | [thermal] 70 | power_epoch_period = 10000; power epoch period (# cycle) 71 | chip_dim_x = 0.008; chip size in x dimension [m] 72 | chip_dim_y = 0.008; chip size in y dimension [m] 73 | amb_temp = 40; The ambient temperature in [C] 74 | mat_dim_x = 512; 75 | mat_dim_y = 512; 76 | bank_order = 1; 0: x direction first, 1: y direction first 77 | bank_layer_order = 0; 78 | 79 | -------------------------------------------------------------------------------- /configs/HMC_4GB_4Lx16.ini: -------------------------------------------------------------------------------- 1 | [hmc] 2 | num_links = 4 3 | link_width = 16 4 | link_speed = 15000 5 | block_size = 64 6 | xbar_queue_depth = 6 7 | 8 | [dram_structure] 9 | protocol = HMC 10 | bankgroups = 1 11 | banks_per_group = 16 12 | rows = 65536 13 | columns = 64 14 | device_width = 32 15 | num_dies = 4 16 | 17 | [timing] 18 | tCK = 0.8 19 | CL = 17 20 | CWL = 17 21 | tRCD = 17 22 | tRP = 17 23 | tRAS = 34 24 | tRFC = 420 25 | tREFI = 9364; average periodic refresh interval, 3.9us 26 | tRRD_S = 4 27 | tRRD_L = 4 28 | tWTR_S = 3 29 | tWTR_L = 3 30 | tFAW = 27 31 | tWR = 17 32 | tCCD_S = 6 33 | tCCD_L = 6 34 | tXS = 12 35 | tCKSRE = 1 36 | tXP = 8 37 | tRTP_L = 8 38 | tRTP_S = 8 39 | tRTRS = 0 40 | 41 | [power] 42 | VDD = 1.2 43 | IDD0 = 25 44 | IDD2P = 17 45 | IDD2N = 19 46 | IDD3P = 20 47 | IDD3N = 21 48 | IDD4W = 61 49 | IDD4R = 64 50 | IDD5AB = 150 51 | IDD6x = 21 52 | 53 | [system] 54 | channel_size = 256 55 | channels = 16 56 | bus_width = 32 57 | address_mapping = rocorabgbach 58 | queue_structure = PER_BANK 59 | row_buf_policy = CLOSE_PAGE 60 | cmd_queue_size = 8 61 | trans_queue_size = 32 62 | unified_queue = True 63 | 64 | [other] 65 | epoch_period = 1250000 66 | output_level = 1 67 | 68 | -------------------------------------------------------------------------------- /configs/LPDDR3_8Gb_x32_1333.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = LPDDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 32768 6 | columns = 1024 7 | device_width = 32 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.5 12 | AL = 0 13 | CL = 10 14 | CWL = 8 15 | tRCD = 12 16 | tRP = 12 17 | tRAS = 28 18 | tRFC = 140 19 | tRFCb = 60 20 | tRFC2 = 140 21 | tRFC4 = 140 22 | REFI = 2600 23 | tREFIb = 325 24 | tRPRE = 1 25 | tWPRE = 1 26 | tRRD_S = 7 27 | tRRD_L = 7 28 | tWTR_S = 5 29 | tWTR_L = 5 30 | tFAW = 34 31 | tWR = 10 32 | tWR2 = 10 33 | tRTP = 5 34 | tCCD_S = 4 35 | tCCD_L = 4 36 | tCKE = 5 37 | tCKESR = 10 38 | tXS = 147 39 | tXP = 5 40 | tRTRS = 1 41 | 42 | [power] 43 | VDD = 1.2 44 | IDD0 = 40.0 45 | IPP0 = 0 46 | IDD2P = 1.3 47 | IDD2N = 20.0 48 | IDD3P = 7 49 | IDD3N = 20.5 50 | IDD4W = 215 51 | IDD4R = 220 52 | IDD5AB = 150 53 | IDD6x = 20.5 54 | 55 | [system] 56 | channel_size = 2048 57 | channels = 1 58 | bus_width = 64 59 | address_mapping = rochrababgco 60 | queue_structure = PER_BANK 61 | refresh_policy = RANK_LEVEL_STAGGERED 62 | row_buf_policy = OPEN_PAGE 63 | cmd_queue_size = 8 64 | trans_queue_size = 32 65 | 66 | [other] 67 | epoch_period = 666666 68 | output_level = 1 69 | 70 | -------------------------------------------------------------------------------- /configs/LPDDR3_8Gb_x32_1600.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = LPDDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 32768 6 | columns = 1024 7 | device_width = 32 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.25 12 | AL = 0 13 | CL = 12 14 | CWL = 9 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 34 18 | tRFC = 168 19 | tRFCb = 72 20 | tRFC2 = 168 21 | tRFC4 = 168 22 | REFI = 3120 23 | tREFIb = 390 24 | tRPRE = 1 25 | tWPRE = 1 26 | tRRD_S = 8 27 | tRRD_L = 8 28 | tWTR_S = 6 29 | tWTR_L = 6 30 | tFAW = 40 31 | tWR = 12 32 | tWR2 = 12 33 | tRTP = 6 34 | tCCD_S = 4 35 | tCCD_L = 4 36 | tCKE = 6 37 | tCKESR = 12 38 | tXS = 176 39 | tXP = 6 40 | tRTRS = 1 41 | 42 | [power] 43 | VDD = 1.2 44 | IDD0 = 40.0 45 | IPP0 = 0 46 | IDD2P = 1.3 47 | IDD2N = 20.5 48 | IDD3P = 7 49 | IDD3N = 21.0 50 | IDD4W = 245 51 | IDD4R = 250 52 | IDD5AB = 150 53 | IDD6x = 21.0 54 | 55 | [system] 56 | channel_size = 2048 57 | channels = 1 58 | bus_width = 64 59 | address_mapping = rochrababgco 60 | queue_structure = PER_BANK 61 | refresh_policy = RANK_LEVEL_STAGGERED 62 | row_buf_policy = OPEN_PAGE 63 | cmd_queue_size = 8 64 | trans_queue_size = 32 65 | 66 | [other] 67 | epoch_period = 800000 68 | output_level = 1 69 | 70 | -------------------------------------------------------------------------------- /configs/LPDDR3_8Gb_x32_1866.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = LPDDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 32768 6 | columns = 1024 7 | device_width = 32 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.07 12 | AL = 0 13 | CL = 14 14 | CWL = 11 15 | tRCD = 17 16 | tRP = 17 17 | tRAS = 40 18 | tRFC = 196 19 | tRFCb = 85 20 | tRFC2 = 196 21 | tRFC4 = 196 22 | REFI = 3645 23 | tREFIb = 456 24 | tRPRE = 1 25 | tWPRE = 1 26 | tRRD_S = 10 27 | tRRD_L = 10 28 | tWTR_S = 7 29 | tWTR_L = 7 30 | tFAW = 47 31 | tWR = 15 32 | tWR2 = 15 33 | tRTP = 7 34 | tCCD_S = 4 35 | tCCD_L = 4 36 | tCKE = 7 37 | tCKESR = 15 38 | tXS = 206 39 | tXP = 7 40 | tRTRS = 1 41 | 42 | [power] 43 | VDD = 1.2 44 | IDD0 = 41.5 45 | IPP0 = 0 46 | IDD2P = 1.3 47 | IDD2N = 21.5 48 | IDD3P = 7 49 | IDD3N = 22.0 50 | IDD4W = 285 51 | IDD4R = 290 52 | IDD5AB = 150 53 | IDD6x = 22.0 54 | 55 | [system] 56 | channel_size = 2048 57 | channels = 1 58 | bus_width = 64 59 | address_mapping = rochrababgco 60 | queue_structure = PER_BANK 61 | refresh_policy = RANK_LEVEL_STAGGERED 62 | row_buf_policy = OPEN_PAGE 63 | cmd_queue_size = 8 64 | trans_queue_size = 32 65 | 66 | [other] 67 | epoch_period = 934579 68 | output_level = 1 69 | 70 | -------------------------------------------------------------------------------- /configs/LPDDR4_8Gb_x16_2400.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = LPDDR4 3 | bankgroups = 2 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 16 8 | BL = 16 9 | 10 | [timing] 11 | tCK = 0.83 12 | AL = 0 13 | CL = 17 14 | CWL = 14 15 | tRCD = 15 16 | tRP = 15 17 | tRAS = 32 18 | tRFC = 392 19 | tRFC2 = 268 20 | tRFC4 = 172 21 | tREFI = 8660 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 8 25 | tRRD_L = 8 26 | tWTR_S = 8 27 | tWTR_L = 16 28 | tFAW = 32 29 | tWR = 30 30 | tWR2 = 32 31 | tRTP = 12 32 | tCCD_S = 4 33 | tCCD_L = 6 34 | tCKE = 6 35 | tCKESR = 7 36 | tXS = 432 37 | tXP = 6 38 | tRTRS = 1 39 | tPPD = 2 40 | 41 | [power] 42 | VDD = 1.2 43 | IDD0 = 80 44 | IPP0 = 4.0 45 | IDD2P = 25 46 | IDD2N = 34 47 | IDD3P = 41 48 | IDD3N = 47 49 | IDD4W = 228 50 | IDD4R = 243 51 | IDD5AB = 280 52 | IDD6x = 30 53 | 54 | [system] 55 | channel_size = 8192 56 | channels = 1 57 | bus_width = 64 58 | address_mapping = rochrababgco 59 | queue_structure = PER_BANK 60 | refresh_policy = RANK_LEVEL_STAGGERED 61 | row_buf_policy = OPEN_PAGE 62 | cmd_queue_size = 8 63 | trans_queue_size = 32 64 | 65 | [other] 66 | epoch_period = 1204819 67 | output_level = 1 68 | 69 | -------------------------------------------------------------------------------- /configs/ST-1.2x.ini: -------------------------------------------------------------------------------- 1 | ; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) 2 | ; 3 | ;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416 4 | 5 | ;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 6 | 7 | ;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 8 | 9 | ;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 10 | 11 | ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 12 | 13 | ; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. 14 | 15 | [dram_structure] 16 | protocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol 17 | bankgroups = 1 18 | banks_per_group = 8 19 | rows = 32768 20 | columns = 1024 21 | device_width = 8 22 | BL=4 23 | 24 | [timing] 25 | tCK = 1.25; 26 | CL = 11; 27 | CWL = 11 28 | AL = 0; 29 | tRCDRD=14 30 | tRCDWR=14 31 | tRP=14 32 | tRAS=20 33 | tRFC = 1 34 | tREFI = 6240 35 | tRRD_S = 6 36 | tRRD_L = 6 37 | tWTR_S = 2 38 | tWTR_L = 2 39 | tFAW = 29 40 | tWR = 12 41 | tCCD_S = 4 42 | tCCD_L = 4 43 | tCKE = 4 44 | tXP = 5 45 | tRTP_L = 6 46 | tRTP_S = 6 47 | ; tRC=34 48 | tRTRS=1 49 | 50 | ; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations. 51 | [power] 52 | VDD = 1.5 53 | IDD0=1305; 54 | IDD1=1395; 55 | IDD2P=846; 56 | IDD2Q=1030; 57 | IDD2N=1050; 58 | IDD3Pf=60; 59 | IDD3Ps=60; 60 | IDD3N=1310; 61 | IDD4W=1765; 62 | IDD4R=230; 63 | IDD5=1940; 64 | IDD6=246; 65 | IDD6L=246; 66 | IDD7=2160; 67 | 68 | [system] 69 | channel_size = 4096 70 | channels = 1 71 | bus_width = 64 72 | address_mapping = rorabgbachco 73 | queue_structure = PER_RANK 74 | row_buf_policy = OPEN_PAGE 75 | cmd_queue_size = 16 76 | trans_queue_size = 32 77 | 78 | [other] 79 | epoch_period = 100000 80 | output_level = 1 81 | -------------------------------------------------------------------------------- /configs/ST-1.5x.ini: -------------------------------------------------------------------------------- 1 | ; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) 2 | ; 3 | ;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416 4 | 5 | ;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 6 | 7 | ;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 8 | 9 | ;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 10 | 11 | ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 12 | 13 | ; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.5x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. 14 | 15 | [dram_structure] 16 | protocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol 17 | bankgroups = 1 18 | banks_per_group = 8 19 | rows = 32768 20 | columns = 1024 21 | device_width = 8 22 | BL=4 23 | 24 | [timing] 25 | tCK = 1.25; 26 | CL = 11; 27 | CWL = 11 28 | AL = 0; 29 | tRCDRD=17 30 | tRCDWR=17 31 | tRP=17 32 | tRAS=23 33 | tRFC = 1 34 | tREFI = 6240 35 | tRRD_S = 8 36 | tRRD_L = 8 37 | tWTR_S = 6 38 | tWTR_L = 6 39 | tFAW = 36 40 | tWR = 12 41 | tCCD_S = 4 42 | tCCD_L = 4 43 | tCKE = 4 44 | tXP = 5 45 | tRTP_L = 6 46 | tRTP_S = 6 47 | ; tRC=40 48 | tRTRS=1 49 | REFRESH_PERIOD=7800; 50 | 51 | ; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations. 52 | [power] 53 | VDD=1.5 54 | IDD0=1305; 55 | IDD1=1395; 56 | IDD2P=846; 57 | IDD2Q=1030; 58 | IDD2N=1050; 59 | IDD3Pf=60; 60 | IDD3Ps=60; 61 | IDD3N=1310; 62 | IDD4W=1765; 63 | IDD4R=230; 64 | IDD5=1940; 65 | IDD6=246; 66 | IDD6L=246; 67 | IDD7=2160; 68 | 69 | [system] 70 | channel_size = 4096 71 | channels = 1 72 | bus_width = 64 73 | address_mapping = rorabgbachco 74 | queue_structure = PER_RANK 75 | row_buf_policy = OPEN_PAGE 76 | cmd_queue_size = 16 77 | trans_queue_size = 32 78 | 79 | [other] 80 | epoch_period = 100000 81 | output_level = 1 82 | -------------------------------------------------------------------------------- /configs/ST-2.0x.ini: -------------------------------------------------------------------------------- 1 | ; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) 2 | ; 3 | ;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416 4 | 5 | ;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 6 | 7 | ;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 8 | 9 | ;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 10 | 11 | ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 12 | 13 | ; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. 14 | 15 | [dram_structure] 16 | protocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol 17 | bankgroups = 1 18 | banks_per_group = 8 19 | rows = 32768 20 | columns = 1024 21 | device_width = 8 22 | BL=4 23 | 24 | [timing] 25 | tCK = 1.25; 26 | CL = 11; 27 | CWL = 11 28 | AL = 0; 29 | tRCDRD=22 30 | tRCDWR=22 31 | tRP=22 32 | tRAS=28 33 | tRFC = 1 34 | tREFI = 6240 35 | tRRD_S = 10 36 | tRRD_L = 10 37 | tWTR_S = 6 38 | tWTR_L = 6 39 | tFAW = 36 40 | tWR = 48 41 | tCCD_S = 4 42 | tCCD_L = 4 43 | tCKE = 4 44 | tXP = 5 45 | tRTP_L = 6 46 | tRTP_S = 6 47 | ; tRC=50 48 | tRTRS=1 49 | REFRESH_PERIOD=7800 50 | 51 | ; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations. 52 | [power] 53 | VDD=1.5; 54 | IDD0=1305; 55 | IDD1=1395; 56 | IDD2P=846; 57 | IDD2Q=1030; 58 | IDD2N=1050; 59 | IDD3Pf=60; 60 | IDD3Ps=60; 61 | IDD3N=1310; 62 | IDD4W=1765; 63 | IDD4R=230; 64 | IDD5=1940; 65 | IDD6=246; 66 | IDD6L=246; 67 | IDD7=2160; 68 | 69 | 70 | [system] 71 | channel_size = 4096 72 | channels = 1 73 | bus_width = 64 74 | address_mapping = rorabgbachco 75 | queue_structure = PER_RANK 76 | row_buf_policy = OPEN_PAGE 77 | cmd_queue_size = 16 78 | trans_queue_size = 32 79 | 80 | [other] 81 | epoch_period = 100000 82 | output_level = 1 -------------------------------------------------------------------------------- /configs/ddr3_debug.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR3 3 | bankgroups = 1 4 | banks_per_group = 8 5 | rows = 16384 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 1.5 12 | AL = 0 13 | CL = 10 14 | CWL = 7 15 | tRCD = 10 16 | tRP = 10 17 | tRAS = 24 18 | tRFC = 74 19 | tREFI = 5200 20 | tRPRE = 1 21 | tWPRE = 1 22 | tRRD_S = 4 23 | tWTR_S = 5 24 | tFAW = 20 25 | tWR = 10 26 | tCCD_S = 4 27 | tRTP = 5 28 | tCKE = 4 29 | tCKESR = 1 30 | tXS = 81 31 | tXP = 5 32 | tRTRS = 1 33 | 34 | [power] 35 | VDD = 1.35 36 | IDD0 = 33 37 | IDD2P = 12 38 | IDD2N = 17 39 | IDD3P = 14 40 | IDD3N = 23 41 | IDD4W = 77 42 | IDD4R = 72 43 | IDD5AB = 155 44 | IDD6x = 12 45 | 46 | [system] 47 | channel_size = 2048 48 | channels = 1 49 | bus_width = 64 50 | address_mapping = rochrababgco 51 | queue_structure = PER_BANK 52 | row_buf_policy = OPEN_PAGE 53 | cmd_queue_size = 8 54 | trans_queue_size = 32 55 | 56 | [other] 57 | epoch_period = 666666 58 | output_level = 1 59 | 60 | -------------------------------------------------------------------------------- /configs/ddr4_debug.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = DDR4 3 | bankgroups = 4 4 | banks_per_group = 4 5 | rows = 65536 6 | columns = 1024 7 | device_width = 8 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 0.833 12 | AL = 0 13 | CL = 16 14 | CWL = 16 15 | tRCD = 16 16 | tRP = 16 17 | tRAS = 39 18 | tRFC = 420 19 | tRFC2 = 312 20 | tRFC4 = 192 21 | tREFI = 9364 22 | tRPRE = 1 23 | tWPRE = 1 24 | tRRD_S = 4 25 | tRRD_L = 6 26 | tWTR_S = 3 27 | tWTR_L = 9 28 | tFAW = 26 29 | tWR = 19 30 | tWR2 = 1 31 | tCCD_S = 4 32 | tCCD_L = 6 33 | tXS = 12 34 | tCKSRE = 12 35 | tXP = 8 36 | tRFCb = 20 37 | tREFIb = 1950 38 | activation_window_depth = 4 39 | tRREFD = 5 40 | tRTRS = 2 41 | tRTP = 10 42 | tCAS = 3 43 | tCWD = 3 44 | 45 | [power] 46 | VDD = 1.2 47 | IDD0 = 48 48 | IDD2P = 25 49 | IDD2N = 34 50 | IDD3P = 37 51 | IDD3N = 44.0 52 | IDD4W = 123 53 | IDD4R = 135 54 | IDD5AB = 250 55 | IDD6x = 31 56 | 57 | [system] 58 | channel_size = 16384 59 | channels = 1 60 | bus_width = 64 61 | address_mapping = rochrababgco 62 | queue_structure = PER_BANK 63 | row_buf_policy = OPEN_PAGE 64 | cmd_queue_size = 8 65 | trans_queue_size = 32 66 | 67 | [other] 68 | validation_output = ddr4_verification.log 69 | epoch_period = 1200480 70 | output_level = 1 71 | 72 | -------------------------------------------------------------------------------- /configs/lpddr_2Gb_x16.ini: -------------------------------------------------------------------------------- 1 | [dram_structure] 2 | protocol = LPDDR 3 | bankgroups = 1 4 | banks_per_group = 4 5 | rows = 16384 6 | columns = 2048 7 | device_width = 16 8 | BL = 8 9 | 10 | [timing] 11 | tCK = 4.8 12 | AL = 0 13 | CL = 3 14 | CWL = 3 15 | tRCD = 4 16 | tRP = 3 17 | tRAS = 9 18 | tRFC = 15 19 | tREFI = 1625 20 | tRPRE = 1 21 | tWPRE = 1 22 | tRRD_L = 3 23 | tWTR_L = 2 24 | tFAW = 4 25 | tWR = 3 26 | tCCD_L = 0 27 | tRTP = 0 28 | tXP = 2 29 | tCKE = 1 30 | tRTRS = 1 31 | tCMD = 1 32 | activation_window_depth = 4 33 | 34 | [system] 35 | channel_size = 1024 36 | channels = 1 37 | bus_width = 64 38 | address_mapping = rochrababgco 39 | queue_structure = PER_BANK 40 | row_buf_policy = OPEN_PAGE 41 | cmd_queue_size = 8 42 | trans_queue_size = 32 43 | 44 | [other] 45 | validation_output = lpddr_verification.log 46 | epoch_period = 208333 47 | output_level = 1 48 | 49 | [thermal] 50 | power_epoch_period = 10000; power epoch period (# cycle) 51 | chip_dim_x = 0.008; chip size in x dimension [m] 52 | chip_dim_y = 0.008; chip size in y dimension [m] 53 | amb_temp = 40; The ambient temperature in [C] 54 | mat_dim_x = 512; 55 | mat_dim_y = 512; 56 | bank_order = 1; 0: x direction first, 1: y direction first 57 | 58 | -------------------------------------------------------------------------------- /ext/fmt/LICENSE.rst: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012 - 2016, Victor Zverovich 2 | 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | 2. Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation 12 | and/or other materials provided with the distribution. 13 | 14 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 15 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 18 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 21 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | -------------------------------------------------------------------------------- /ext/headers/INIHLICENSE.txt: -------------------------------------------------------------------------------- 1 | 2 | The "inih" library is distributed under the New BSD license: 3 | 4 | Copyright (c) 2009, Ben Hoyt 5 | All rights reserved. 6 | 7 | Redistribution and use in source and binary forms, with or without 8 | modification, are permitted provided that the following conditions are met: 9 | * Redistributions of source code must retain the above copyright 10 | notice, this list of conditions and the following disclaimer. 11 | * Redistributions in binary form must reproduce the above copyright 12 | notice, this list of conditions and the following disclaimer in the 13 | documentation and/or other materials provided with the distribution. 14 | * Neither the name of Ben Hoyt nor the names of its contributors 15 | may be used to endorse or promote products derived from this software 16 | without specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY BEN HOYT ''AS IS'' AND ANY 19 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL BEN HOYT BE LIABLE FOR ANY 22 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | -------------------------------------------------------------------------------- /scripts/final_PowerTemperature_map.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | from numpy import genfromtxt 3 | from numpy import amax 4 | import numpy as np 5 | import matplotlib.pyplot as plt 6 | from matplotlib.patches import Rectangle 7 | import sys 8 | 9 | 10 | parser = argparse.ArgumentParser() 11 | parser.add_argument("-m", "--mem_name", help="type of memory") 12 | parser.add_argument("-l", "--layer_str", help="specified layer") 13 | parser.add_argument("-f", "--save_root", help="figure saved file") 14 | args = parser.parse_args() 15 | 16 | if len(sys.argv) != 7: 17 | parser.print_help() 18 | sys.exit(0) 19 | 20 | 21 | PT_file = "../build/" + args.mem_name + "-output-final_power_temperature.csv" 22 | pos_file = "../build/" + args.mem_name + "-output-bank_position.csv" 23 | 24 | print "data file: " + PT_file 25 | print "bank position file: " + pos_file 26 | 27 | 28 | PT_data = genfromtxt(PT_file, delimiter=',') 29 | PT_data = PT_data[1:, :] 30 | 31 | Bpos = genfromtxt(pos_file, delimiter=',') 32 | Bpos = Bpos[1:, :] 33 | 34 | X = int(amax(PT_data[:, 1])) 35 | Y = int(amax(PT_data[:, 2])) 36 | Z = int(amax(PT_data[:, 3])) 37 | 38 | print "Dimension: (" + str(X) + ", " + str(Y) + ", " + str(Z) + ")" 39 | 40 | power = np.empty((X+1, Y+1, Z+1)) 41 | temperature = np.empty((X+1, Y+1, Z+1)) 42 | 43 | for i in range(0, len(PT_data)): 44 | x_ = int(PT_data[i,1]) 45 | y_ = int(PT_data[i,2]) 46 | z_ = int(PT_data[i,3]) 47 | power[x_, y_, z_] = PT_data[i,4] 48 | temperature[x_, y_, z_] = PT_data[i,5] 49 | 50 | layer = int(args.layer_str) 51 | 52 | if layer >= 0 and layer <= Z: 53 | plt.figure() 54 | plt.imshow(power[:,:,layer], aspect='auto') 55 | ca = plt.gca() 56 | for i in range(0, len(Bpos)): 57 | if Bpos[i,6] == layer: 58 | x_ = Bpos[i,2] 59 | y_ = Bpos[i,4] 60 | w_ = Bpos[i,3] - Bpos[i,2] + 1 61 | l_ = Bpos[i,5] - Bpos[i,4] + 1 62 | ca.add_patch(Rectangle((y_-0.5, x_-0.5), l_, w_, fill=None, edgecolor='r')) 63 | if l_ > w_: 64 | rot = 0 65 | else: 66 | rot = 0 67 | 68 | ca.text(y_-0.5+l_/4, x_-0.5+w_/2, 'R'+str(int(Bpos[i,0]))+'B'+str(int(Bpos[i,1])), color='r', rotation=rot) 69 | 70 | 71 | ca.set_xlabel('Y (Column)') 72 | ca.set_ylabel('X (Row)') 73 | title_str = 'Power (layer' + str(layer) + ')' 74 | ca.set_title(title_str) 75 | plt.colorbar() 76 | plt.savefig(args.save_root + args.mem_name + '_final_power_layer' + str(layer) + '.png') 77 | 78 | plt.figure() 79 | plt.imshow(temperature[:,:,layer], aspect='auto') 80 | ca = plt.gca() 81 | for i in range(0, len(Bpos)): 82 | if Bpos[i,6] == layer: 83 | x_ = Bpos[i,2] 84 | y_ = Bpos[i,4] 85 | w_ = Bpos[i,3] - Bpos[i,2] + 1 86 | l_ = Bpos[i,5] - Bpos[i,4] + 1 87 | ca.add_patch(Rectangle((y_-0.5, x_-0.5), l_, w_, fill=None, edgecolor='r')) 88 | if l_ > w_: 89 | rot = 0 90 | else: 91 | rot = 0 92 | 93 | ca.text(y_-0.5+l_/4, x_-0.5+w_/2, 'R'+str(int(Bpos[i,0]))+'B'+str(int(Bpos[i,1])), color='r', rotation=rot) 94 | 95 | 96 | ca.set_xlabel('Y (Column)') 97 | ca.set_ylabel('X (Row)') 98 | title_str = 'Power (layer' + str(layer) + ')' 99 | ca.set_title(title_str) 100 | plt.colorbar() 101 | plt.savefig(args.save_root + args.mem_name + '_final_temperature_layer' + str(layer) + '.png') 102 | 103 | else: 104 | print "You should name a correct layer index" 105 | print "Layer index should be in the range of [" + str(0) + ", " + str(Z) + "]" 106 | 107 | -------------------------------------------------------------------------------- /scripts/parse_config.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import sys 3 | import tempfile 4 | import configparser 5 | 6 | def get_val(config, sec, opt): 7 | """ 8 | get value from a ini file given the section and option 9 | the priority here is int, float, boolean and finally string 10 | """ 11 | try: 12 | val = config.getint(sec, opt) 13 | except ValueError: 14 | try: 15 | val = config.getfloat(sec, opt) 16 | except ValueError: 17 | try: 18 | val = config.getboolean(sec, opt) 19 | except ValueError: 20 | val = config.get(sec, opt) # shouldn't have any exceptions here.. 21 | return val 22 | 23 | def get_val_from_file(config_file, sec, opt): 24 | """ 25 | a quick way to obtain an option from a config file 26 | """ 27 | config = configparser.ConfigParser() 28 | config.read(config_file) 29 | return get_val(config, sec, opt) 30 | 31 | 32 | # a few quick access functions using get_val_from_file 33 | def get_protocol(config_file): 34 | return get_val_from_file(config_file, "dram_structure", "protocol") 35 | 36 | 37 | def get_ddr_speed(config_file): 38 | t_ck = get_val_from_file(config_file, "timing", "tCK") 39 | freq = int(1/t_ck * 2 * 1000.) # to get to MHz 40 | freq_lookup = [800, 1333, 1600, 1866, 2133, 2400, 2666, 2933, 3200] 41 | actual_freq = sys.maxsize 42 | for f in freq_lookup: 43 | freq_diff = abs(actual_freq - f) 44 | if abs(f - freq) < freq_diff: 45 | actual_freq = f 46 | return actual_freq 47 | 48 | 49 | def get_page_size(config_file): 50 | """ 51 | get page size in bytes 52 | """ 53 | cols = get_val_from_file(config_file, "dram_structure", "columns") 54 | width = get_val_from_file(config_file, "dram_structure", "device_width") 55 | page_size = cols * width / 8 56 | return page_size 57 | 58 | 59 | def get_density(config_file): 60 | """ 61 | get device density in mega bytes 62 | """ 63 | bankgroups = get_val_from_file(config_file, "dram_structure", "bankgroups") 64 | banks = get_val_from_file(config_file, "dram_structure", "banks_per_group") 65 | rows = get_val_from_file(config_file, "dram_structure", "rows") 66 | page_size = get_page_size(config_file) 67 | density = bankgroups * banks * rows * page_size 68 | return density / 1024 / 1024 69 | 70 | def get_rank_size_mb(config_file): 71 | dens = get_density(config_file) 72 | dev_width = get_val_from_file(config_file, "dram_structure", "device_width") 73 | bus_width = get_val_from_file(config_file, "system", "bus_width") 74 | num_dev = bus_width / dev_width 75 | rank_size = dens * num_dev 76 | return int(rank_size) 77 | 78 | 79 | def get_dict(config_file): 80 | """ 81 | read a ini file specified by config_file and 82 | return a dict of configs with [section][option] : value structure 83 | """ 84 | _config_dict = {} 85 | config = configparser.ConfigParser() 86 | config.read(config_file) 87 | for sec in config.sections(): 88 | _config_dict[sec] = {} 89 | for opt in config.options(sec): 90 | _config_dict[sec][opt] = get_val(config, sec, opt) 91 | return _config_dict 92 | 93 | 94 | def sub_options(config_file, sec, opt, new_value, inplace=False): 95 | """ 96 | given a config file, replace the specified section, option 97 | with a new value, and the inplace flag decides whether the 98 | config_file will be written or a tempfile handler will be 99 | returned, NOTE if inplace is true all the comments in the 100 | original file will be gone.. 101 | """ 102 | config = configparser.ConfigParser() 103 | config.read(config_file) 104 | if not config.has_section(sec): 105 | config.add_section(sec) 106 | 107 | try: 108 | config.set(sec, opt, str(new_value)) 109 | except configparser.Error: 110 | raise 111 | if not inplace: 112 | temp_fp = tempfile.NamedTemporaryFile() 113 | config.write(temp_fp) 114 | temp_fp.seek(0) 115 | return temp_fp 116 | else: 117 | with open(config_file, "wb") as fp: 118 | config.write(fp) 119 | 120 | -------------------------------------------------------------------------------- /scripts/plot_stats.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | """ 3 | Generate time series graphs of power/bandwidth/energy... 4 | """ 5 | 6 | import argparse 7 | import json 8 | import os 9 | import sys 10 | import numpy as np 11 | import matplotlib.pyplot as plt 12 | 13 | 14 | def extract_epoch_data(json_data, label, merge_channel=True): 15 | """ 16 | TODO enable merge_channel=False option later 17 | """ 18 | if merge_channel: 19 | merged_data = {} 20 | for line in json_data: 21 | epoch_num = line["epoch_num"] 22 | if epoch_num in merged_data: 23 | merged_data[epoch_num] += line[label] 24 | else: 25 | merged_data[epoch_num] = line[label] 26 | return [v for (k, v) in sorted(merged_data.items(), 27 | key=lambda t: t[0])] 28 | 29 | 30 | def plot_epochs(json_data, label, unit="", output=None): 31 | """ 32 | plot the time series of a specified stat serie (e.g. bw, power, etc) 33 | """ 34 | print('ploting {}'.format(label)) 35 | cycles_per_epoch = json_data[0]['num_cycles'] 36 | y_data = extract_epoch_data(json_data, label) 37 | x_ticks = [i * cycles_per_epoch for i in range(len(y_data))] 38 | 39 | plt.plot(x_ticks, y_data) 40 | 41 | plt.title(label) 42 | plt.ticklabel_format(style='sci', axis='x', scilimits=(0, 0)) 43 | plt.xlabel('Cycles') 44 | plt.ylabel('{} ({})'.format(label, unit)) 45 | plt.ylim(bottom=0, top=1.1*max(y_data)) 46 | if output: 47 | plt.savefig(output+'_epochs_{}.pdf'.format(label)) 48 | plt.clf() 49 | else: 50 | plt.show() 51 | return 52 | 53 | 54 | def extract_histo_data(data, label): 55 | array = [] 56 | for chan, channel_data in data.items(): 57 | for key, count in channel_data[label].items(): 58 | val = int(key) 59 | array.extend([val for _ in range(count)]) 60 | return array 61 | 62 | 63 | def plot_histogram(json_data, label, unit='', output=None): 64 | histo_data = extract_histo_data(json_data, label) 65 | histo_data = sorted(histo_data) 66 | total_cnt = len(histo_data) 67 | existing_nums = set() 68 | unique_vals = 0 69 | for i in range(int(0.90 * total_cnt)): 70 | if histo_data[i] in existing_nums: 71 | continue 72 | else: 73 | existing_nums.add(histo_data[i]) 74 | unique_vals += 1 75 | print('90-Percentile unique {} values: {}'.format(label, unique_vals)) 76 | x_min = min(histo_data) 77 | x_max = max(histo_data) 78 | x_99 = int(0.99 * len(histo_data)) 79 | mark_99 = histo_data[x_99] 80 | avg = np.average(histo_data) 81 | histo_data = histo_data[0:x_99] 82 | 83 | # doane seems to provide better esitmates for bins 84 | plt.hist(histo_data, bins='doane', density=True) 85 | 86 | line_avg = plt.axvline(x=avg, linestyle='--', c='g', 87 | label='Average:{0:.1f}'.format(avg)) 88 | line_99 = plt.axvline(x=mark_99, linestyle='-.', c='r', 89 | label='99 Percentile:{0:.1f}'.format(mark_99)) 90 | plt.title(label) 91 | plt.xlabel(label + ' [max: ' + str(x_max) + '](' + unit + ')') 92 | plt.ylabel('Density') 93 | plt.legend(handles=[line_avg, line_99]) 94 | if output: 95 | plt.savefig(output+'_histo_{}.pdf'.format(label)) 96 | plt.clf() 97 | else: 98 | plt.show() 99 | return 100 | 101 | 102 | if __name__ == '__main__': 103 | parser = argparse.ArgumentParser(description='Plot time serie graphs from ' 104 | 'stats outputs, type -h for more options') 105 | parser.add_argument('json', help='stats json file') 106 | parser.add_argument('-d', '--dir', help='output dir', default='.') 107 | parser.add_argument('-o', '--output', 108 | help='output name (withouth extension name)', 109 | default='dramsim') 110 | parser.add_argument('-k', '--key', 111 | help='plot a specific key name in epoch stats, ' 112 | 'use the name in JSON') 113 | args = parser.parse_args() 114 | 115 | with open(args.json, 'r') as j_file: 116 | is_epoch = False 117 | try: 118 | j_data = json.load(j_file) 119 | except: 120 | print('cannot load file ' + args.json) 121 | exit(1) 122 | if isinstance(j_data, list): 123 | is_epoch = True 124 | else: 125 | is_epoch = False 126 | 127 | prefix = os.path.join(args.dir, args.output) 128 | if is_epoch: 129 | data_units = {'average_bandwidth': 'GB/s', 130 | 'average_power': 'mW', 131 | 'average_read_latency': 'cycles'} 132 | if args.key: 133 | data_units[args.key] = '' 134 | for label, unit in data_units.items(): 135 | plot_epochs(j_data, label, unit, prefix) 136 | else: 137 | data_units = {'read_latency': 'cycles', 138 | 'write_latency': 'cycles', 139 | 'interarrival_latency': 'cycles'} 140 | for label, unit in data_units.items(): 141 | plot_histogram(j_data, label, unit, prefix) 142 | -------------------------------------------------------------------------------- /scripts/trace_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import argparse 4 | import os 5 | import random 6 | 7 | 8 | class Generator(): 9 | """ 10 | Format agnostic address stream generator 11 | """ 12 | 13 | def __init__(self, stream_type, interarrival, ratio, gb): 14 | # convert to 0 ~ 1 for easier random generation 15 | self._interval = interarrival 16 | self._ratio = ratio / (ratio + 1.0) 17 | 18 | self._gen = None 19 | 20 | self._range = gb * (2 ** 30) 21 | self._last_clk = 0 22 | self._last_rd_addr = random.randrange(self._range) 23 | self._last_wr_addr = random.randrange(self._range) 24 | if stream_type == 'random': 25 | self._gen = self._rand_gen 26 | elif stream_type == 'stream': 27 | self._gen = self._stream_gen 28 | else: 29 | self._gen = self._mix_gen 30 | 31 | def _get_op(self): 32 | if random.random() > self._ratio: 33 | return 'w' 34 | else: 35 | return 'r' 36 | 37 | def _rand_gen(self): 38 | addr = random.randrange(self._range) 39 | op = self._get_op() 40 | return (op, addr) 41 | 42 | def _stream_gen(self): 43 | op = self._get_op() 44 | if op == 'r': 45 | self._last_rd_addr += 64 46 | return (op, self._last_rd_addr) 47 | else: 48 | self._last_wr_addr += 64 49 | return (op, self._last_wr_addr) 50 | 51 | def _mix_gen(self): 52 | if random.random() > 0.5: 53 | return self._rand_gen() 54 | else: 55 | return self._stream_gen() 56 | 57 | def gen(self): 58 | op, addr = self._gen() 59 | self._last_clk += self._interval 60 | return (op, addr, self._last_clk) 61 | 62 | 63 | def get_string(op, addr, clk, trace_format, interarrival): 64 | op_map = { 65 | 'r': { 66 | 'dramsim2': 'READ', 67 | 'dramsim3': 'READ', 68 | 'ramulator': 'R', 69 | 'usimm': 'R', 70 | 'drsim': 'READ' 71 | }, 72 | 'w': { 73 | 'dramsim2': 'WRITE', 74 | 'dramsim3': 'WRITE', 75 | 'ramulator': 'W', 76 | 'usimm': 'W', 77 | 'drsim': 'WRITE' 78 | } 79 | } 80 | actual_op = op_map[op][trace_format] 81 | if 'dramsim' in trace_format: 82 | return '{} {} {}\n'.format(hex(addr), actual_op, clk) 83 | elif 'ramulator' == trace_format: 84 | return '{} {}\n'.format(hex(addr), actual_op) 85 | elif 'usimm' == trace_format: 86 | # USIMM assumes a 3.2GHz CPU by default, we hard code it here... 87 | # also use clk for pc for convinience 88 | if actual_op == 'R': 89 | return '{} {} {} 0x0\n'.format(interarrival, actual_op, hex(addr)) 90 | else: 91 | return '{} {} {}\n'.format(interarrival, actual_op, hex(addr)) 92 | elif 'drsim' == trace_format: 93 | return '{} {} {} 64B\n'.format(hex(addr), actual_op, clk) 94 | 95 | if __name__ == '__main__': 96 | parser = argparse.ArgumentParser( 97 | description="Trace Generator for Various DRAM Simulators", 98 | formatter_class=argparse.ArgumentDefaultsHelpFormatter) 99 | parser.add_argument('-s', '--stream-type', default='random', 100 | help='Address stream type, (r)andom, (s)tream, (m)ix') 101 | parser.add_argument('-i', '--interarrival', 102 | help='Inter-arrival time in cycles', 103 | type=int, default=10) 104 | parser.add_argument('-f', '--format', default='all', 105 | help='Trace format, dramsim2, dramsim3,' 106 | 'ramulator, usimm, drsim, or all') 107 | parser.add_argument("-o", "--output-dir", 108 | help="output directory", default=".") 109 | parser.add_argument('-r', '--ratio', type=float, default=2, 110 | help='Read to write(1) ratio') 111 | parser.add_argument('-n', '--num-reqs', type=int, default=100, 112 | help='Total number of requests.') 113 | parser.add_argument('-g', '--gb', type=int, default=4, 114 | help='GBs of address space') 115 | 116 | args = parser.parse_args() 117 | 118 | if not os.path.exists(args.output_dir): 119 | try: 120 | os.mkdir(args.output_dir) 121 | except (OSError, ValueError) as e: 122 | print('Cannot use output path:' + args.output_dir) 123 | print(e) 124 | exit(1) 125 | print("Output directory: ", args.output_dir) 126 | 127 | stream_types = {'r': 'random', 'random': 'random', 128 | 's': 'stream', 'stream': 'stream', 129 | 'm': 'mix', 'mix': 'mix'} 130 | stream_type = stream_types.get(args.stream_type, 'random') 131 | print("Address stream type: ", stream_type) 132 | 133 | formats = ['dramsim2', 'dramsim3', 'ramulator', 'usimm', 'drsim'] 134 | if args.format != 'all': 135 | formats = [args.format] 136 | print("Trace format(s):", formats) 137 | 138 | files = {} 139 | for f in formats: 140 | file_name = '{}_{}_i{}_n{}_rw{}.trace'.format( 141 | f, stream_type, args.interarrival, args.num_reqs, int(args.ratio)) 142 | if f == 'dramsim2': 143 | file_name = 'mase_' + file_name 144 | print("Write to file: ", file_name) 145 | files[f] = os.path.join(args.output_dir, file_name) 146 | 147 | # open files 148 | for f, name in files.items(): 149 | fp = open(name, 'w') 150 | files[f] = fp 151 | 152 | g = Generator(stream_type, args.interarrival, args.ratio, args.gb) 153 | for i in range(args.num_reqs): 154 | op, addr, clk = g.gen() 155 | for f in formats: 156 | line = get_string(op, addr, clk, f, args.interarrival) 157 | files[f].write(line) 158 | -------------------------------------------------------------------------------- /src/bankstate.h: -------------------------------------------------------------------------------- 1 | #ifndef __BANKSTATE_H 2 | #define __BANKSTATE_H 3 | 4 | #include 5 | #include "common.h" 6 | 7 | namespace dramsim3 { 8 | 9 | class BankState { 10 | public: 11 | BankState(); 12 | 13 | enum class State { OPEN, CLOSED, SREF, PD, SIZE }; 14 | Command GetReadyCommand(const Command& cmd, uint64_t clk) const; 15 | 16 | // Update the state of the bank resulting after the execution of the command 17 | void UpdateState(const Command& cmd); 18 | 19 | // Update the existing timing constraints for the command 20 | void UpdateTiming(const CommandType cmd_type, uint64_t time); 21 | 22 | bool IsRowOpen() const { return state_ == State::OPEN; } 23 | int OpenRow() const { return open_row_; } 24 | int RowHitCount() const { return row_hit_count_; } 25 | 26 | private: 27 | // Current state of the Bank 28 | // Apriori or instantaneously transitions on a command. 29 | State state_; 30 | 31 | // Earliest time when the particular Command can be executed in this bank 32 | std::vector cmd_timing_; 33 | 34 | // Currently open row 35 | int open_row_; 36 | 37 | // consecutive accesses to one row 38 | int row_hit_count_; 39 | }; 40 | 41 | } // namespace dramsim3 42 | #endif 43 | -------------------------------------------------------------------------------- /src/channel_state.h: -------------------------------------------------------------------------------- 1 | #ifndef __CHANNEL_STATE_H 2 | #define __CHANNEL_STATE_H 3 | 4 | #include 5 | #include "bankstate.h" 6 | #include "common.h" 7 | #include "configuration.h" 8 | #include "timing.h" 9 | 10 | namespace dramsim3 { 11 | 12 | class ChannelState { 13 | public: 14 | ChannelState(const Config& config, const Timing& timing); 15 | Command GetReadyCommand(const Command& cmd, uint64_t clk) const; 16 | void UpdateState(const Command& cmd); 17 | void UpdateTiming(const Command& cmd, uint64_t clk); 18 | void UpdateTimingAndStates(const Command& cmd, uint64_t clk); 19 | bool ActivationWindowOk(int rank, uint64_t curr_time) const; 20 | void UpdateActivationTimes(int rank, uint64_t curr_time); 21 | bool IsRowOpen(int rank, int bankgroup, int bank) const { 22 | return bank_states_[rank][bankgroup][bank].IsRowOpen(); 23 | } 24 | bool IsAllBankIdleInRank(int rank) const; 25 | bool IsRankSelfRefreshing(int rank) const { return rank_is_sref_[rank]; } 26 | bool IsRefreshWaiting() const { return !refresh_q_.empty(); } 27 | bool IsRWPendingOnRef(const Command& cmd) const; 28 | const Command& PendingRefCommand() const {return refresh_q_.front(); } 29 | void BankNeedRefresh(int rank, int bankgroup, int bank, bool need); 30 | void RankNeedRefresh(int rank, bool need); 31 | int OpenRow(int rank, int bankgroup, int bank) const { 32 | return bank_states_[rank][bankgroup][bank].OpenRow(); 33 | } 34 | int RowHitCount(int rank, int bankgroup, int bank) const { 35 | return bank_states_[rank][bankgroup][bank].RowHitCount(); 36 | }; 37 | 38 | std::vector rank_idle_cycles; 39 | 40 | private: 41 | const Config& config_; 42 | const Timing& timing_; 43 | 44 | std::vector rank_is_sref_; 45 | std::vector > > bank_states_; 46 | std::vector refresh_q_; 47 | 48 | std::vector > four_aw_; 49 | std::vector > thirty_two_aw_; 50 | bool IsFAWReady(int rank, uint64_t curr_time) const; 51 | bool Is32AWReady(int rank, uint64_t curr_time) const; 52 | // Update timing of the bank the command corresponds to 53 | void UpdateSameBankTiming( 54 | const Address& addr, 55 | const std::vector >& cmd_timing_list, 56 | uint64_t clk); 57 | 58 | // Update timing of the other banks in the same bankgroup as the command 59 | void UpdateOtherBanksSameBankgroupTiming( 60 | const Address& addr, 61 | const std::vector >& cmd_timing_list, 62 | uint64_t clk); 63 | 64 | // Update timing of banks in the same rank but different bankgroup as the 65 | // command 66 | void UpdateOtherBankgroupsSameRankTiming( 67 | const Address& addr, 68 | const std::vector >& cmd_timing_list, 69 | uint64_t clk); 70 | 71 | // Update timing of banks in a different rank as the command 72 | void UpdateOtherRanksTiming( 73 | const Address& addr, 74 | const std::vector >& cmd_timing_list, 75 | uint64_t clk); 76 | 77 | // Update timing of the entire rank (for rank level commands) 78 | void UpdateSameRankTiming( 79 | const Address& addr, 80 | const std::vector >& cmd_timing_list, 81 | uint64_t clk); 82 | }; 83 | 84 | } // namespace dramsim3 85 | #endif 86 | -------------------------------------------------------------------------------- /src/command_queue.h: -------------------------------------------------------------------------------- 1 | #ifndef __COMMAND_QUEUE_H 2 | #define __COMMAND_QUEUE_H 3 | 4 | #include 5 | #include 6 | #include "channel_state.h" 7 | #include "common.h" 8 | #include "configuration.h" 9 | #include "simple_stats.h" 10 | 11 | namespace dramsim3 { 12 | 13 | using CMDIterator = std::vector::iterator; 14 | using CMDQueue = std::vector; 15 | enum class QueueStructure { PER_RANK, PER_BANK, SIZE }; 16 | 17 | class CommandQueue { 18 | public: 19 | CommandQueue(int channel_id, const Config& config, 20 | const ChannelState& channel_state, SimpleStats& simple_stats); 21 | Command GetCommandToIssue(); 22 | Command FinishRefresh(); 23 | void ClockTick() { clk_ += 1; }; 24 | bool WillAcceptCommand(int rank, int bankgroup, int bank) const; 25 | bool AddCommand(Command cmd); 26 | bool QueueEmpty() const; 27 | int QueueUsage() const; 28 | std::vector rank_q_empty; 29 | 30 | private: 31 | bool ArbitratePrecharge(const CMDIterator& cmd_it, 32 | const CMDQueue& queue) const; 33 | bool HasRWDependency(const CMDIterator& cmd_it, 34 | const CMDQueue& queue) const; 35 | Command GetFirstReadyInQueue(CMDQueue& queue) const; 36 | int GetQueueIndex(int rank, int bankgroup, int bank) const; 37 | CMDQueue& GetQueue(int rank, int bankgroup, int bank); 38 | CMDQueue& GetNextQueue(); 39 | void GetRefQIndices(const Command& ref); 40 | void EraseRWCommand(const Command& cmd); 41 | Command PrepRefCmd(const CMDIterator& it, const Command& ref) const; 42 | 43 | QueueStructure queue_structure_; 44 | const Config& config_; 45 | const ChannelState& channel_state_; 46 | SimpleStats& simple_stats_; 47 | 48 | std::vector queues_; 49 | 50 | // Refresh related data structures 51 | std::unordered_set ref_q_indices_; 52 | bool is_in_ref_; 53 | 54 | int num_queues_; 55 | size_t queue_size_; 56 | int queue_idx_; 57 | uint64_t clk_; 58 | }; 59 | 60 | } // namespace dramsim3 61 | #endif 62 | -------------------------------------------------------------------------------- /src/common.cc: -------------------------------------------------------------------------------- 1 | #include "common.h" 2 | #include "fmt/format.h" 3 | #include 4 | #include 5 | #include 6 | 7 | namespace dramsim3 { 8 | 9 | std::ostream& operator<<(std::ostream& os, const Command& cmd) { 10 | std::vector command_string = { 11 | "read", 12 | "read_p", 13 | "write", 14 | "write_p", 15 | "activate", 16 | "precharge", 17 | "refresh_bank", // verilog model doesn't distinguish bank/rank refresh 18 | "refresh", 19 | "self_refresh_enter", 20 | "self_refresh_exit", 21 | "WRONG"}; 22 | os << fmt::format("{:<20} {:>3} {:>3} {:>3} {:>3} {:>#8x} {:>#8x}", 23 | command_string[static_cast(cmd.cmd_type)], 24 | cmd.Channel(), cmd.Rank(), cmd.Bankgroup(), cmd.Bank(), 25 | cmd.Row(), cmd.Column()); 26 | return os; 27 | } 28 | 29 | std::ostream& operator<<(std::ostream& os, const Transaction& trans) { 30 | const std::string trans_type = trans.is_write ? "WRITE" : "READ"; 31 | os << fmt::format("{:<30} {:>8}", trans.addr, trans_type); 32 | return os; 33 | } 34 | 35 | std::istream& operator>>(std::istream& is, Transaction& trans) { 36 | std::unordered_set write_types = {"WRITE", "write", "P_MEM_WR", 37 | "BOFF"}; 38 | std::string mem_op; 39 | is >> std::hex >> trans.addr >> mem_op >> std::dec >> trans.added_cycle; 40 | trans.is_write = write_types.count(mem_op) == 1; 41 | return is; 42 | } 43 | 44 | int GetBitInPos(uint64_t bits, int pos) { 45 | // given a uint64_t value get the binary value of pos-th bit 46 | // from MSB to LSB indexed as 63 - 0 47 | return (bits >> pos) & 1; 48 | } 49 | 50 | int LogBase2(int power_of_two) { 51 | int i = 0; 52 | while (power_of_two > 1) { 53 | power_of_two /= 2; 54 | i++; 55 | } 56 | return i; 57 | } 58 | 59 | std::vector StringSplit(const std::string& s, char delim) { 60 | std::vector elems; 61 | StringSplit(s, delim, std::back_inserter(elems)); 62 | return elems; 63 | } 64 | 65 | template 66 | void StringSplit(const std::string& s, char delim, Out result) { 67 | std::stringstream ss; 68 | ss.str(s); 69 | std::string item; 70 | while (std::getline(ss, item, delim)) { 71 | if (!item.empty()) { 72 | *(result++) = item; 73 | } 74 | } 75 | } 76 | 77 | void AbruptExit(const std::string& file, int line) { 78 | std::cerr << "Exiting Abruptly - " << file << ":" << line << std::endl; 79 | std::exit(-1); 80 | } 81 | 82 | bool DirExist(std::string dir) { 83 | // courtesy to stackoverflow 84 | struct stat info; 85 | if (stat(dir.c_str(), &info) != 0) { 86 | return false; 87 | } else if (info.st_mode & S_IFDIR) { 88 | return true; 89 | } else { // exists but is file 90 | return false; 91 | } 92 | } 93 | 94 | } // namespace dramsim3 95 | -------------------------------------------------------------------------------- /src/common.h: -------------------------------------------------------------------------------- 1 | #ifndef __COMMON_H 2 | #define __COMMON_H 3 | 4 | #include 5 | #include 6 | #include 7 | 8 | namespace dramsim3 { 9 | 10 | struct Address { 11 | Address() 12 | : channel(-1), rank(-1), bankgroup(-1), bank(-1), row(-1), column(-1) {} 13 | Address(int channel, int rank, int bankgroup, int bank, int row, int column) 14 | : channel(channel), 15 | rank(rank), 16 | bankgroup(bankgroup), 17 | bank(bank), 18 | row(row), 19 | column(column) {} 20 | Address(const Address& addr) 21 | : channel(addr.channel), 22 | rank(addr.rank), 23 | bankgroup(addr.bankgroup), 24 | bank(addr.bank), 25 | row(addr.row), 26 | column(addr.column) {} 27 | int channel; 28 | int rank; 29 | int bankgroup; 30 | int bank; 31 | int row; 32 | int column; 33 | }; 34 | 35 | inline uint32_t ModuloWidth(uint64_t addr, uint32_t bit_width, uint32_t pos) { 36 | addr >>= pos; 37 | auto store = addr; 38 | addr >>= bit_width; 39 | addr <<= bit_width; 40 | return static_cast(store ^ addr); 41 | } 42 | 43 | // extern std::function AddressMapping; 44 | int GetBitInPos(uint64_t bits, int pos); 45 | // it's 2017 and c++ std::string still lacks a split function, oh well 46 | std::vector StringSplit(const std::string& s, char delim); 47 | template 48 | void StringSplit(const std::string& s, char delim, Out result); 49 | 50 | int LogBase2(int power_of_two); 51 | void AbruptExit(const std::string& file, int line); 52 | bool DirExist(std::string dir); 53 | 54 | enum class CommandType { 55 | READ, 56 | READ_PRECHARGE, 57 | WRITE, 58 | WRITE_PRECHARGE, 59 | ACTIVATE, 60 | PRECHARGE, 61 | REFRESH_BANK, 62 | REFRESH, 63 | SREF_ENTER, 64 | SREF_EXIT, 65 | SIZE 66 | }; 67 | 68 | struct Command { 69 | Command() : cmd_type(CommandType::SIZE), hex_addr(0) {} 70 | Command(CommandType cmd_type, const Address& addr, uint64_t hex_addr) 71 | : cmd_type(cmd_type), addr(addr), hex_addr(hex_addr) {} 72 | // Command(const Command& cmd) {} 73 | 74 | bool IsValid() const { return cmd_type != CommandType::SIZE; } 75 | bool IsRefresh() const { 76 | return cmd_type == CommandType::REFRESH || 77 | cmd_type == CommandType::REFRESH_BANK; 78 | } 79 | bool IsRead() const { 80 | return cmd_type == CommandType::READ || 81 | cmd_type == CommandType ::READ_PRECHARGE; 82 | } 83 | bool IsWrite() const { 84 | return cmd_type == CommandType ::WRITE || 85 | cmd_type == CommandType ::WRITE_PRECHARGE; 86 | } 87 | bool IsReadWrite() const { return IsRead() || IsWrite(); } 88 | bool IsRankCMD() const { 89 | return cmd_type == CommandType::REFRESH || 90 | cmd_type == CommandType::SREF_ENTER || 91 | cmd_type == CommandType::SREF_EXIT; 92 | } 93 | CommandType cmd_type; 94 | Address addr; 95 | uint64_t hex_addr; 96 | 97 | int Channel() const { return addr.channel; } 98 | int Rank() const { return addr.rank; } 99 | int Bankgroup() const { return addr.bankgroup; } 100 | int Bank() const { return addr.bank; } 101 | int Row() const { return addr.row; } 102 | int Column() const { return addr.column; } 103 | 104 | friend std::ostream& operator<<(std::ostream& os, const Command& cmd); 105 | }; 106 | 107 | struct Transaction { 108 | Transaction() {} 109 | Transaction(uint64_t addr, bool is_write) 110 | : addr(addr), 111 | added_cycle(0), 112 | complete_cycle(0), 113 | is_write(is_write) {} 114 | Transaction(const Transaction& tran) 115 | : addr(tran.addr), 116 | added_cycle(tran.added_cycle), 117 | complete_cycle(tran.complete_cycle), 118 | is_write(tran.is_write) {} 119 | uint64_t addr; 120 | uint64_t added_cycle; 121 | uint64_t complete_cycle; 122 | bool is_write; 123 | 124 | friend std::ostream& operator<<(std::ostream& os, const Transaction& trans); 125 | friend std::istream& operator>>(std::istream& is, Transaction& trans); 126 | }; 127 | 128 | } // namespace dramsim3 129 | #endif 130 | -------------------------------------------------------------------------------- /src/configuration.h: -------------------------------------------------------------------------------- 1 | #ifndef __CONFIG_H 2 | #define __CONFIG_H 3 | 4 | #include 5 | #include 6 | #include "common.h" 7 | 8 | #include "INIReader.h" 9 | 10 | namespace dramsim3 { 11 | 12 | enum class DRAMProtocol { 13 | DDR3, 14 | DDR4, 15 | GDDR5, 16 | GDDR5X, 17 | GDDR6, 18 | LPDDR, 19 | LPDDR3, 20 | LPDDR4, 21 | HBM, 22 | HBM2, 23 | HMC, 24 | SIZE 25 | }; 26 | 27 | enum class RefreshPolicy { 28 | RANK_LEVEL_SIMULTANEOUS, // impractical due to high power requirement 29 | RANK_LEVEL_STAGGERED, 30 | BANK_LEVEL_STAGGERED, 31 | SIZE 32 | }; 33 | 34 | class Config { 35 | public: 36 | Config(std::string config_file, std::string out_dir); 37 | Address AddressMapping(uint64_t hex_addr) const; 38 | // DRAM physical structure 39 | DRAMProtocol protocol; 40 | int channel_size; 41 | int channels; 42 | int ranks; 43 | int banks; 44 | int bankgroups; 45 | int banks_per_group; 46 | int rows; 47 | int columns; 48 | int device_width; 49 | int bus_width; 50 | int devices_per_rank; 51 | int BL; 52 | 53 | // Address mapping numbers 54 | int shift_bits; 55 | int ch_pos, ra_pos, bg_pos, ba_pos, ro_pos, co_pos; 56 | uint64_t ch_mask, ra_mask, bg_mask, ba_mask, ro_mask, co_mask; 57 | 58 | // Generic DRAM timing parameters 59 | double tCK; 60 | int burst_cycle; // seperate BL with timing since for GDDRx it's not BL/2 61 | int AL; 62 | int CL; 63 | int CWL; 64 | int RL; 65 | int WL; 66 | int tCCD_L; 67 | int tCCD_S; 68 | int tRTRS; 69 | int tRTP; 70 | int tWTR_L; 71 | int tWTR_S; 72 | int tWR; 73 | int tRP; 74 | int tRRD_L; 75 | int tRRD_S; 76 | int tRAS; 77 | int tRCD; 78 | int tRFC; 79 | int tRC; 80 | // tCKSRE and tCKSRX are only useful for changing clock freq after entering 81 | // SRE mode we are not doing that, so tCKESR is sufficient 82 | int tCKE; 83 | int tCKESR; 84 | int tXS; 85 | int tXP; 86 | int tRFCb; 87 | int tREFI; 88 | int tREFIb; 89 | int tFAW; 90 | int tRPRE; // read preamble and write preamble are important 91 | int tWPRE; 92 | int read_delay; 93 | int write_delay; 94 | 95 | // LPDDR4 and GDDR5 96 | int tPPD; 97 | // GDDR5 98 | int t32AW; 99 | int tRCDRD; 100 | int tRCDWR; 101 | 102 | // pre calculated power parameters 103 | double act_energy_inc; 104 | double pre_energy_inc; 105 | double read_energy_inc; 106 | double write_energy_inc; 107 | double ref_energy_inc; 108 | double refb_energy_inc; 109 | double act_stb_energy_inc; 110 | double pre_stb_energy_inc; 111 | double pre_pd_energy_inc; 112 | double sref_energy_inc; 113 | 114 | // HMC 115 | int num_links; 116 | int num_dies; 117 | int link_width; 118 | int link_speed; 119 | int num_vaults; 120 | int block_size; // block size in bytes 121 | int xbar_queue_depth; 122 | 123 | // System 124 | std::string address_mapping; 125 | std::string queue_structure; 126 | std::string row_buf_policy; 127 | RefreshPolicy refresh_policy; 128 | int cmd_queue_size; 129 | bool unified_queue; 130 | int trans_queue_size; 131 | int write_buf_size; 132 | bool enable_self_refresh; 133 | int sref_threshold; 134 | bool aggressive_precharging_enabled; 135 | bool enable_hbm_dual_cmd; 136 | 137 | 138 | int epoch_period; 139 | int output_level; 140 | std::string output_dir; 141 | std::string output_prefix; 142 | std::string json_stats_name; 143 | std::string json_epoch_name; 144 | std::string txt_stats_name; 145 | 146 | // Computed parameters 147 | int request_size_bytes; 148 | 149 | bool IsGDDR() const { 150 | return (protocol == DRAMProtocol::GDDR5 || 151 | protocol == DRAMProtocol::GDDR5X || 152 | protocol == DRAMProtocol::GDDR6); 153 | } 154 | bool IsHBM() const { 155 | return (protocol == DRAMProtocol::HBM || 156 | protocol == DRAMProtocol::HBM2); 157 | } 158 | bool IsHMC() const { return (protocol == DRAMProtocol::HMC); } 159 | // yzy: add another function 160 | bool IsDDR4() const { return (protocol == DRAMProtocol::DDR4); } 161 | 162 | int ideal_memory_latency; 163 | 164 | #ifdef THERMAL 165 | std::string loc_mapping; 166 | int num_row_refresh; // number of rows to be refreshed for one time 167 | double amb_temp; // the ambient temperature in [C] 168 | double const_logic_power; 169 | 170 | double chip_dim_x; 171 | double chip_dim_y; 172 | int num_x_grids; 173 | int num_y_grids; 174 | int mat_dim_x; 175 | int mat_dim_y; 176 | // 0: x-direction priority, 1: y-direction priority 177 | int bank_order; 178 | // 0; low-layer priority, 1: high-layer priority 179 | int bank_layer_order; 180 | int row_tile; 181 | int tile_row_num; 182 | double bank_asr; // the aspect ratio of a bank: #row_bits / #col_bits 183 | #endif // THERMAL 184 | 185 | private: 186 | INIReader* reader_; 187 | void CalculateSize(); 188 | DRAMProtocol GetDRAMProtocol(std::string protocol_str); 189 | int GetInteger(const std::string& sec, const std::string& opt, 190 | int default_val) const; 191 | void InitDRAMParams(); 192 | void InitOtherParams(); 193 | void InitPowerParams(); 194 | void InitSystemParams(); 195 | #ifdef THERMAL 196 | void InitThermalParams(); 197 | #endif // THERMAL 198 | void InitTimingParams(); 199 | void SetAddressMapping(); 200 | }; 201 | 202 | } // namespace dramsim3 203 | #endif 204 | -------------------------------------------------------------------------------- /src/controller.h: -------------------------------------------------------------------------------- 1 | #ifndef __CONTROLLER_H 2 | #define __CONTROLLER_H 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include "channel_state.h" 9 | #include "command_queue.h" 10 | #include "common.h" 11 | #include "refresh.h" 12 | #include "simple_stats.h" 13 | 14 | #ifdef THERMAL 15 | #include "thermal.h" 16 | #endif // THERMAL 17 | 18 | namespace dramsim3 { 19 | 20 | enum class RowBufPolicy { OPEN_PAGE, CLOSE_PAGE, SIZE }; 21 | 22 | class Controller { 23 | public: 24 | #ifdef THERMAL 25 | Controller(int channel, const Config &config, const Timing &timing, 26 | ThermalCalculator &thermalcalc); 27 | #else 28 | Controller(int channel, const Config &config, const Timing &timing); 29 | #endif // THERMAL 30 | void ClockTick(); 31 | bool WillAcceptTransaction(uint64_t hex_addr, bool is_write) const; 32 | bool AddTransaction(Transaction trans); 33 | int QueueUsage() const; 34 | // Stats output 35 | void PrintEpochStats(); 36 | void PrintFinalStats(); 37 | void ResetStats() { simple_stats_.Reset(); } 38 | std::pair ReturnDoneTrans(uint64_t clock); 39 | 40 | int channel_id_; 41 | 42 | private: 43 | uint64_t clk_; 44 | const Config &config_; 45 | SimpleStats simple_stats_; 46 | ChannelState channel_state_; 47 | CommandQueue cmd_queue_; 48 | Refresh refresh_; 49 | 50 | #ifdef THERMAL 51 | ThermalCalculator &thermal_calc_; 52 | #endif // THERMAL 53 | 54 | // queue that takes transactions from CPU side 55 | bool is_unified_queue_; 56 | std::vector unified_queue_; 57 | std::vector read_queue_; 58 | std::vector write_buffer_; 59 | 60 | // transactions that are not completed, use map for convenience 61 | std::multimap pending_rd_q_; 62 | std::multimap pending_wr_q_; 63 | 64 | // completed transactions 65 | std::vector return_queue_; 66 | 67 | // row buffer policy 68 | RowBufPolicy row_buf_policy_; 69 | 70 | #ifdef CMD_TRACE 71 | std::ofstream cmd_trace_; 72 | #endif // CMD_TRACE 73 | 74 | // used to calculate inter-arrival latency 75 | uint64_t last_trans_clk_; 76 | 77 | // transaction queueing 78 | int write_draining_; 79 | void ScheduleTransaction(); 80 | void IssueCommand(const Command &tmp_cmd); 81 | Command TransToCommand(const Transaction &trans); 82 | void UpdateCommandStats(const Command &cmd); 83 | }; 84 | } // namespace dramsim3 85 | #endif 86 | -------------------------------------------------------------------------------- /src/cpu.cc: -------------------------------------------------------------------------------- 1 | #include "cpu.h" 2 | 3 | namespace dramsim3 { 4 | 5 | void RandomCPU::ClockTick() { 6 | // Create random CPU requests at full speed 7 | // this is useful to exploit the parallelism of a DRAM protocol 8 | // and is also immune to address mapping and scheduling policies 9 | memory_system_.ClockTick(); 10 | if (get_next_) { 11 | last_addr_ = gen(); 12 | last_write_ = (gen() % 3 == 0); 13 | } 14 | get_next_ = memory_system_.WillAcceptTransaction(last_addr_, last_write_); 15 | if (get_next_) { 16 | memory_system_.AddTransaction(last_addr_, last_write_); 17 | } 18 | clk_++; 19 | return; 20 | } 21 | 22 | void StreamCPU::ClockTick() { 23 | // stream-add, read 2 arrays, add them up to the third array 24 | // this is a very simple approximate but should be able to produce 25 | // enough buffer hits 26 | 27 | // moving on to next set of arrays 28 | memory_system_.ClockTick(); 29 | if (offset_ >= array_size_ || clk_ == 0) { 30 | addr_a_ = gen(); 31 | addr_b_ = gen(); 32 | addr_c_ = gen(); 33 | offset_ = 0; 34 | } 35 | 36 | if (!inserted_a_ && 37 | memory_system_.WillAcceptTransaction(addr_a_ + offset_, false)) { 38 | memory_system_.AddTransaction(addr_a_ + offset_, false); 39 | inserted_a_ = true; 40 | } 41 | if (!inserted_b_ && 42 | memory_system_.WillAcceptTransaction(addr_b_ + offset_, false)) { 43 | memory_system_.AddTransaction(addr_b_ + offset_, false); 44 | inserted_b_ = true; 45 | } 46 | if (!inserted_c_ && 47 | memory_system_.WillAcceptTransaction(addr_c_ + offset_, true)) { 48 | memory_system_.AddTransaction(addr_c_ + offset_, true); 49 | inserted_c_ = true; 50 | } 51 | // moving on to next element 52 | if (inserted_a_ && inserted_b_ && inserted_c_) { 53 | offset_ += stride_; 54 | inserted_a_ = false; 55 | inserted_b_ = false; 56 | inserted_c_ = false; 57 | } 58 | clk_++; 59 | return; 60 | } 61 | 62 | TraceBasedCPU::TraceBasedCPU(const std::string& config_file, 63 | const std::string& output_dir, 64 | const std::string& trace_file) 65 | : CPU(config_file, output_dir) { 66 | trace_file_.open(trace_file); 67 | if (trace_file_.fail()) { 68 | std::cerr << "Trace file does not exist" << std::endl; 69 | AbruptExit(__FILE__, __LINE__); 70 | } 71 | } 72 | 73 | void TraceBasedCPU::ClockTick() { 74 | memory_system_.ClockTick(); 75 | if (!trace_file_.eof()) { 76 | if (get_next_) { 77 | get_next_ = false; 78 | trace_file_ >> trans_; 79 | } 80 | if (trans_.added_cycle <= clk_) { 81 | get_next_ = memory_system_.WillAcceptTransaction(trans_.addr, 82 | trans_.is_write); 83 | if (get_next_) { 84 | memory_system_.AddTransaction(trans_.addr, trans_.is_write); 85 | } 86 | } 87 | } 88 | clk_++; 89 | return; 90 | } 91 | 92 | } // namespace dramsim3 93 | -------------------------------------------------------------------------------- /src/cpu.h: -------------------------------------------------------------------------------- 1 | #ifndef __CPU_H 2 | #define __CPU_H 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include "memory_system.h" 9 | 10 | namespace dramsim3 { 11 | 12 | class CPU { 13 | public: 14 | CPU(const std::string& config_file, const std::string& output_dir) 15 | : memory_system_( 16 | config_file, output_dir, 17 | std::bind(&CPU::ReadCallBack, this, std::placeholders::_1), 18 | std::bind(&CPU::WriteCallBack, this, std::placeholders::_1)), 19 | clk_(0) {} 20 | virtual void ClockTick() = 0; 21 | void ReadCallBack(uint64_t addr) { return; } 22 | void WriteCallBack(uint64_t addr) { return; } 23 | void PrintStats() { memory_system_.PrintStats(); } 24 | 25 | protected: 26 | MemorySystem memory_system_; 27 | uint64_t clk_; 28 | }; 29 | 30 | class RandomCPU : public CPU { 31 | public: 32 | using CPU::CPU; 33 | void ClockTick() override; 34 | 35 | private: 36 | uint64_t last_addr_; 37 | bool last_write_ = false; 38 | std::mt19937_64 gen; 39 | bool get_next_ = true; 40 | }; 41 | 42 | class StreamCPU : public CPU { 43 | public: 44 | using CPU::CPU; 45 | void ClockTick() override; 46 | 47 | private: 48 | uint64_t addr_a_, addr_b_, addr_c_, offset_ = 0; 49 | std::mt19937_64 gen; 50 | bool inserted_a_ = false; 51 | bool inserted_b_ = false; 52 | bool inserted_c_ = false; 53 | const uint64_t array_size_ = 2 << 20; // elements in array 54 | const int stride_ = 64; // stride in bytes 55 | }; 56 | 57 | class TraceBasedCPU : public CPU { 58 | public: 59 | TraceBasedCPU(const std::string& config_file, const std::string& output_dir, 60 | const std::string& trace_file); 61 | ~TraceBasedCPU() { trace_file_.close(); } 62 | void ClockTick() override; 63 | 64 | private: 65 | std::ifstream trace_file_; 66 | Transaction trans_; 67 | bool get_next_ = true; 68 | }; 69 | 70 | } // namespace dramsim3 71 | #endif 72 | -------------------------------------------------------------------------------- /src/dram_system.h: -------------------------------------------------------------------------------- 1 | #ifndef __DRAM_SYSTEM_H 2 | #define __DRAM_SYSTEM_H 3 | 4 | #include 5 | #include 6 | #include 7 | 8 | #include "common.h" 9 | #include "configuration.h" 10 | #include "controller.h" 11 | #include "timing.h" 12 | 13 | #ifdef THERMAL 14 | #include "thermal.h" 15 | #endif // THERMAL 16 | 17 | namespace dramsim3 { 18 | 19 | class BaseDRAMSystem { 20 | public: 21 | BaseDRAMSystem(Config &config, const std::string &output_dir, 22 | std::function read_callback, 23 | std::function write_callback); 24 | virtual ~BaseDRAMSystem() {} 25 | void RegisterCallbacks(std::function read_callback, 26 | std::function write_callback); 27 | void PrintEpochStats(); 28 | void PrintStats(); 29 | void ResetStats(); 30 | 31 | virtual bool WillAcceptTransaction(uint64_t hex_addr, 32 | bool is_write) const = 0; 33 | virtual bool AddTransaction(uint64_t hex_addr, bool is_write) = 0; 34 | virtual void ClockTick() = 0; 35 | int GetChannel(uint64_t hex_addr) const; 36 | 37 | std::function read_callback_, write_callback_; 38 | static int total_channels_; 39 | 40 | protected: 41 | uint64_t id_; 42 | uint64_t last_req_clk_; 43 | Config &config_; 44 | Timing timing_; 45 | uint64_t parallel_cycles_; 46 | uint64_t serial_cycles_; 47 | 48 | #ifdef THERMAL 49 | ThermalCalculator thermal_calc_; 50 | #endif // THERMAL 51 | 52 | uint64_t clk_; 53 | std::vector ctrls_; 54 | 55 | #ifdef ADDR_TRACE 56 | std::ofstream address_trace_; 57 | #endif // ADDR_TRACE 58 | }; 59 | 60 | // hmmm not sure this is the best naming... 61 | class JedecDRAMSystem : public BaseDRAMSystem { 62 | public: 63 | JedecDRAMSystem(Config &config, const std::string &output_dir, 64 | std::function read_callback, 65 | std::function write_callback); 66 | ~JedecDRAMSystem(); 67 | bool WillAcceptTransaction(uint64_t hex_addr, bool is_write) const override; 68 | bool AddTransaction(uint64_t hex_addr, bool is_write) override; 69 | void ClockTick() override; 70 | }; 71 | 72 | // Model a memorysystem with an infinite bandwidth and a fixed latency (possibly 73 | // zero) To establish a baseline for what a 'good' memory standard can and 74 | // cannot do for a given application 75 | class IdealDRAMSystem : public BaseDRAMSystem { 76 | public: 77 | IdealDRAMSystem(Config &config, const std::string &output_dir, 78 | std::function read_callback, 79 | std::function write_callback); 80 | ~IdealDRAMSystem(); 81 | bool WillAcceptTransaction(uint64_t hex_addr, 82 | bool is_write) const override { 83 | return true; 84 | }; 85 | bool AddTransaction(uint64_t hex_addr, bool is_write) override; 86 | void ClockTick() override; 87 | 88 | private: 89 | int latency_; 90 | std::vector infinite_buffer_q_; 91 | }; 92 | 93 | } // namespace dramsim3 94 | #endif // __DRAM_SYSTEM_H 95 | -------------------------------------------------------------------------------- /src/dramsim3.h: -------------------------------------------------------------------------------- 1 | #ifndef __MEMORY_SYSTEM__H 2 | #define __MEMORY_SYSTEM__H 3 | 4 | #include 5 | #include 6 | 7 | namespace dramsim3 { 8 | 9 | // This should be the interface class that deals with CPU 10 | class MemorySystem { 11 | public: 12 | MemorySystem(const std::string &config_file, const std::string &output_dir, 13 | std::function read_callback, 14 | std::function write_callback); 15 | ~MemorySystem(); 16 | void ClockTick(); 17 | void RegisterCallbacks(std::function read_callback, 18 | std::function write_callback); 19 | double GetTCK() const; 20 | int GetBusBits() const; 21 | int GetBurstLength() const; 22 | int GetQueueSize() const; 23 | void PrintStats() const; 24 | void ResetStats(); 25 | 26 | bool WillAcceptTransaction(uint64_t hex_addr, bool is_write) const; 27 | bool AddTransaction(uint64_t hex_addr, bool is_write); 28 | }; 29 | 30 | MemorySystem* GetMemorySystem(const std::string &config_file, const std::string &output_dir, 31 | std::function read_callback, 32 | std::function write_callback); 33 | } // namespace dramsim3 34 | 35 | #endif 36 | -------------------------------------------------------------------------------- /src/hmc.h: -------------------------------------------------------------------------------- 1 | #ifndef __HMC_H 2 | #define __HMC_H 3 | 4 | #include 5 | #include 6 | #include 7 | 8 | #include "dram_system.h" 9 | 10 | namespace dramsim3 { 11 | 12 | enum class HMCReqType { 13 | RD0, 14 | RD16, 15 | RD32, 16 | RD48, 17 | RD64, 18 | RD80, 19 | RD96, 20 | RD112, 21 | RD128, 22 | RD256, 23 | WR0, 24 | WR16, 25 | WR32, 26 | WR48, 27 | WR64, 28 | WR80, 29 | WR96, 30 | WR112, 31 | WR128, 32 | WR256, 33 | P_WR16, 34 | P_WR32, 35 | P_WR48, 36 | P_WR64, 37 | P_WR80, 38 | P_WR96, 39 | P_WR112, 40 | P_WR128, 41 | P_WR256, 42 | // TODO haven't properly implement the following atomic operations 43 | ADD8, // 2ADD8, cannot name it like that in c++... 44 | ADD16, 45 | P_2ADD8, // 2 8Byte imm operands + 8 8Byte mem operands read then write 46 | P_ADD16, 47 | ADDS8R, // 2ADD8, cannot name it like that... 48 | ADDS16R, 49 | INC8, // read, return(the original), then write 50 | P_INC8, // read, return(the original), then posted write 51 | // boolean op on imm operand and mem operand, read update write 52 | XOR16, 53 | OR16, 54 | NOR16, 55 | AND16, 56 | NAND16, 57 | // comparison instructions, not sure if there's write untill read done 58 | CASGT8, 59 | CASGT16, 60 | CASLT8, 61 | CASLT16, 62 | CASEQ8, 63 | CASZERO16, 64 | // eq, only read 65 | EQ8, 66 | EQ16, 67 | BWR, 68 | P_BWR, // bit write, 8B mask, 8B value, read update write 69 | BWR8R, // bit write with return 70 | SWAP16, // swap imm operand and mem operand, read then write 71 | SIZE 72 | }; 73 | 74 | enum class HMCRespType { NONE, RD_RS, WR_RS, ERR, SIZE }; 75 | 76 | // for future use 77 | enum class HMCLinkType { HOST_TO_DEV, DEV_TO_DEV, SIZE }; 78 | 79 | class HMCRequest { 80 | public: 81 | HMCRequest(HMCReqType req_type, uint64_t hex_addr, int vault); 82 | HMCReqType type; 83 | uint64_t mem_operand; 84 | int link; 85 | int quad; 86 | int vault; 87 | int flits; 88 | bool is_write; 89 | // this exit_time is the time to exit xbar to vaults 90 | uint64_t exit_time; 91 | }; 92 | 93 | class HMCResponse { 94 | public: 95 | HMCResponse(uint64_t id, HMCReqType reqtype, int dest_link, int src_quad); 96 | uint64_t resp_id; 97 | HMCRespType type; 98 | int link; 99 | int quad; 100 | int flits; 101 | // this exit_time is the time to exit xbar to cpu 102 | uint64_t exit_time; 103 | }; 104 | 105 | class HMCMemorySystem : public BaseDRAMSystem { 106 | public: 107 | HMCMemorySystem(Config& config, const std::string& output_dir, 108 | std::function read_callback, 109 | std::function write_callback); 110 | ~HMCMemorySystem(); 111 | // assuming there are 2 clock domains one for logic die one for DRAM 112 | // we can unify them as one but then we'll have to convert all the 113 | // slow dram time units to faster logic units... 114 | void ClockTick() override; 115 | 116 | // had to have 3 insert interfaces cuz HMC is so different... 117 | bool WillAcceptTransaction(uint64_t hex_addr, bool is_write) const override; 118 | bool AddTransaction(uint64_t hex_addr, bool is_write) override; 119 | bool InsertReqToLink(HMCRequest* req, int link); 120 | bool InsertHMCReq(HMCRequest* req); 121 | 122 | private: 123 | uint64_t logic_clk_, ps_per_dram_, ps_per_logic_, logic_ps_, dram_ps_; 124 | 125 | void SetClockRatio(); 126 | void DRAMClockTick(); 127 | void DrainRequests(); 128 | void DrainResponses(); 129 | void InsertReqToDRAM(HMCRequest* req); 130 | void VaultCallback(uint64_t req_id); 131 | std::vector BuildAgeQueue(std::vector& age_counter); 132 | void XbarArbitrate(); 133 | inline void IterateNextLink(); 134 | 135 | int next_link_; 136 | int links_; 137 | size_t queue_depth_; 138 | 139 | // number of flits xbar can process per logic cycle 140 | const int xbar_bandwidth_ = 2; 141 | 142 | // had to use a multimap because the controller callback return hex addr 143 | // instead of unique id 144 | std::multimap resp_lookup_table_; 145 | // these are essentially input/output buffers for xbars 146 | std::vector> link_req_queues_; 147 | std::vector> link_resp_queues_; 148 | std::vector> quad_req_queues_; 149 | std::vector> quad_resp_queues_; 150 | 151 | // input/output busy indicators, since each packet could be several 152 | // flits, as long as this != 0 then they're busy 153 | std::vector link_busy_; 154 | std::vector quad_busy_ = {0, 0, 0, 0}; 155 | // used for arbitration 156 | std::vector link_age_counter_; 157 | std::vector quad_age_counter_ = {0, 0, 0, 0}; 158 | }; 159 | 160 | } // namespace dramsim3 161 | 162 | #endif 163 | -------------------------------------------------------------------------------- /src/main.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include "./../ext/headers/args.hxx" 3 | #include "cpu.h" 4 | 5 | using namespace dramsim3; 6 | 7 | int main(int argc, const char **argv) { 8 | args::ArgumentParser parser( 9 | "DRAM Simulator.", 10 | "Examples: \n." 11 | "./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini -c 100 -t " 12 | "sample_trace.txt\n" 13 | "./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini -s random -c 100"); 14 | args::HelpFlag help(parser, "help", "Display the help menu", {'h', "help"}); 15 | args::ValueFlag num_cycles_arg(parser, "num_cycles", 16 | "Number of cycles to simulate", 17 | {'c', "cycles"}, 100000); 18 | args::ValueFlag output_dir_arg( 19 | parser, "output_dir", "Output directory for stats files", 20 | {'o', "output-dir"}, "."); 21 | args::ValueFlag stream_arg( 22 | parser, "stream_type", "address stream generator - (random), stream", 23 | {'s', "stream"}, ""); 24 | args::ValueFlag trace_file_arg( 25 | parser, "trace", 26 | "Trace file, setting this option will ignore -s option", 27 | {'t', "trace"}); 28 | args::Positional config_arg( 29 | parser, "config", "The config file name (mandatory)"); 30 | 31 | try { 32 | parser.ParseCLI(argc, argv); 33 | } catch (args::Help) { 34 | std::cout << parser; 35 | return 0; 36 | } catch (args::ParseError e) { 37 | std::cerr << e.what() << std::endl; 38 | std::cerr << parser; 39 | return 1; 40 | } 41 | 42 | std::string config_file = args::get(config_arg); 43 | if (config_file.empty()) { 44 | std::cerr << parser; 45 | return 1; 46 | } 47 | 48 | uint64_t cycles = args::get(num_cycles_arg); 49 | std::string output_dir = args::get(output_dir_arg); 50 | std::string trace_file = args::get(trace_file_arg); 51 | std::string stream_type = args::get(stream_arg); 52 | 53 | CPU *cpu; 54 | if (!trace_file.empty()) { 55 | cpu = new TraceBasedCPU(config_file, output_dir, trace_file); 56 | } else { 57 | if (stream_type == "stream" || stream_type == "s") { 58 | cpu = new StreamCPU(config_file, output_dir); 59 | } else { 60 | cpu = new RandomCPU(config_file, output_dir); 61 | } 62 | } 63 | 64 | for (uint64_t clk = 0; clk < cycles; clk++) { 65 | cpu->ClockTick(); 66 | } 67 | cpu->PrintStats(); 68 | 69 | delete cpu; 70 | 71 | return 0; 72 | } 73 | -------------------------------------------------------------------------------- /src/memory_system.cc: -------------------------------------------------------------------------------- 1 | #include "memory_system.h" 2 | 3 | namespace dramsim3 { 4 | MemorySystem::MemorySystem(const std::string &config_file, 5 | const std::string &output_dir, 6 | std::function read_callback, 7 | std::function write_callback) 8 | : config_(new Config(config_file, output_dir)) { 9 | // TODO: ideal memory type? 10 | if (config_->IsHMC()) { 11 | dram_system_ = new HMCMemorySystem(*config_, output_dir, read_callback, 12 | write_callback); 13 | } else { 14 | dram_system_ = new JedecDRAMSystem(*config_, output_dir, read_callback, 15 | write_callback); 16 | } 17 | } 18 | 19 | MemorySystem::~MemorySystem() { 20 | delete (dram_system_); 21 | delete (config_); 22 | } 23 | 24 | void MemorySystem::ClockTick() { dram_system_->ClockTick(); } 25 | 26 | double MemorySystem::GetTCK() const { return config_->tCK; } 27 | 28 | int MemorySystem::GetBusBits() const { return config_->bus_width; } 29 | 30 | int MemorySystem::GetBurstLength() const { return config_->BL; } 31 | 32 | int MemorySystem::GetQueueSize() const { return config_->trans_queue_size; } 33 | 34 | void MemorySystem::RegisterCallbacks( 35 | std::function read_callback, 36 | std::function write_callback) { 37 | dram_system_->RegisterCallbacks(read_callback, write_callback); 38 | } 39 | 40 | bool MemorySystem::WillAcceptTransaction(uint64_t hex_addr, 41 | bool is_write) const { 42 | return dram_system_->WillAcceptTransaction(hex_addr, is_write); 43 | } 44 | 45 | bool MemorySystem::AddTransaction(uint64_t hex_addr, bool is_write) { 46 | return dram_system_->AddTransaction(hex_addr, is_write); 47 | } 48 | 49 | void MemorySystem::PrintStats() const { dram_system_->PrintStats(); } 50 | 51 | void MemorySystem::ResetStats() { dram_system_->ResetStats(); } 52 | 53 | MemorySystem* GetMemorySystem(const std::string &config_file, const std::string &output_dir, 54 | std::function read_callback, 55 | std::function write_callback) { 56 | return new MemorySystem(config_file, output_dir, read_callback, write_callback); 57 | } 58 | } // namespace dramsim3 59 | 60 | // This function can be used by autoconf AC_CHECK_LIB since 61 | // apparently it can't detect C++ functions. 62 | // Basically just an entry in the symbol table 63 | extern "C" { 64 | void libdramsim3_is_present(void) { ; } 65 | } 66 | -------------------------------------------------------------------------------- /src/memory_system.h: -------------------------------------------------------------------------------- 1 | #ifndef __MEMORY_SYSTEM__H 2 | #define __MEMORY_SYSTEM__H 3 | 4 | #include 5 | #include 6 | 7 | #include "configuration.h" 8 | #include "dram_system.h" 9 | #include "hmc.h" 10 | 11 | namespace dramsim3 { 12 | 13 | // This should be the interface class that deals with CPU 14 | class MemorySystem { 15 | public: 16 | MemorySystem(const std::string &config_file, const std::string &output_dir, 17 | std::function read_callback, 18 | std::function write_callback); 19 | ~MemorySystem(); 20 | void ClockTick(); 21 | void RegisterCallbacks(std::function read_callback, 22 | std::function write_callback); 23 | double GetTCK() const; 24 | int GetBusBits() const; 25 | int GetBurstLength() const; 26 | int GetQueueSize() const; 27 | void PrintStats() const; 28 | void ResetStats(); 29 | 30 | bool WillAcceptTransaction(uint64_t hex_addr, bool is_write) const; 31 | bool AddTransaction(uint64_t hex_addr, bool is_write); 32 | 33 | private: 34 | // These have to be pointers because Gem5 will try to push this object 35 | // into container which will invoke a copy constructor, using pointers 36 | // here is safe 37 | Config *config_; 38 | BaseDRAMSystem *dram_system_; 39 | }; 40 | 41 | MemorySystem* GetMemorySystem(const std::string &config_file, const std::string &output_dir, 42 | std::function read_callback, 43 | std::function write_callback); 44 | 45 | } // namespace dramsim3 46 | 47 | #endif 48 | -------------------------------------------------------------------------------- /src/refresh.cc: -------------------------------------------------------------------------------- 1 | #include "refresh.h" 2 | 3 | namespace dramsim3 { 4 | Refresh::Refresh(const Config &config, ChannelState &channel_state) 5 | : clk_(0), 6 | config_(config), 7 | channel_state_(channel_state), 8 | refresh_policy_(config.refresh_policy), 9 | next_rank_(0), 10 | next_bg_(0), 11 | next_bank_(0) { 12 | if (refresh_policy_ == RefreshPolicy::RANK_LEVEL_SIMULTANEOUS) { 13 | refresh_interval_ = config_.tREFI; 14 | } else if (refresh_policy_ == RefreshPolicy::BANK_LEVEL_STAGGERED) { 15 | refresh_interval_ = config_.tREFIb; 16 | } else { // default refresh scheme: RANK STAGGERED 17 | refresh_interval_ = config_.tREFI / config_.ranks; 18 | } 19 | } 20 | 21 | void Refresh::ClockTick() { 22 | if (clk_ % refresh_interval_ == 0 && clk_ > 0) { 23 | InsertRefresh(); 24 | } 25 | clk_++; 26 | return; 27 | } 28 | 29 | void Refresh::InsertRefresh() { 30 | switch (refresh_policy_) { 31 | // Simultaneous all rank refresh 32 | case RefreshPolicy::RANK_LEVEL_SIMULTANEOUS: 33 | for (auto i = 0; i < config_.ranks; i++) { 34 | if (!channel_state_.IsRankSelfRefreshing(i)) { 35 | channel_state_.RankNeedRefresh(i, true); 36 | break; 37 | } 38 | } 39 | break; 40 | // Staggered all rank refresh 41 | case RefreshPolicy::RANK_LEVEL_STAGGERED: 42 | if (!channel_state_.IsRankSelfRefreshing(next_rank_)) { 43 | channel_state_.RankNeedRefresh(next_rank_, true); 44 | } 45 | IterateNext(); 46 | break; 47 | // Fully staggered per bank refresh 48 | case RefreshPolicy::BANK_LEVEL_STAGGERED: 49 | if (!channel_state_.IsRankSelfRefreshing(next_rank_)) { 50 | channel_state_.BankNeedRefresh(next_rank_, next_bg_, next_bank_, 51 | true); 52 | } 53 | IterateNext(); 54 | break; 55 | default: 56 | AbruptExit(__FILE__, __LINE__); 57 | break; 58 | } 59 | return; 60 | } 61 | 62 | void Refresh::IterateNext() { 63 | switch (refresh_policy_) { 64 | case RefreshPolicy::RANK_LEVEL_STAGGERED: 65 | next_rank_ = (next_rank_ + 1) % config_.ranks; 66 | return; 67 | case RefreshPolicy::BANK_LEVEL_STAGGERED: 68 | // Note - the order issuing bank refresh commands is static and 69 | // non-configurable as per JEDEC standard 70 | next_bg_ = (next_bg_ + 1) % config_.bankgroups; 71 | if (next_bg_ == 0) { 72 | next_bank_ = (next_bank_ + 1) % config_.banks_per_group; 73 | if (next_bank_ == 0) { 74 | next_rank_ = (next_rank_ + 1) % config_.ranks; 75 | } 76 | } 77 | return; 78 | default: 79 | AbruptExit(__FILE__, __LINE__); 80 | return; 81 | } 82 | } 83 | 84 | } // namespace dramsim3 85 | -------------------------------------------------------------------------------- /src/refresh.h: -------------------------------------------------------------------------------- 1 | #ifndef __REFRESH_H 2 | #define __REFRESH_H 3 | 4 | #include 5 | #include "channel_state.h" 6 | #include "common.h" 7 | #include "configuration.h" 8 | 9 | namespace dramsim3 { 10 | 11 | class Refresh { 12 | public: 13 | Refresh(const Config& config, ChannelState& channel_state); 14 | void ClockTick(); 15 | 16 | private: 17 | uint64_t clk_; 18 | int refresh_interval_; 19 | const Config& config_; 20 | ChannelState& channel_state_; 21 | RefreshPolicy refresh_policy_; 22 | 23 | int next_rank_, next_bg_, next_bank_; 24 | 25 | void InsertRefresh(); 26 | 27 | void IterateNext(); 28 | }; 29 | 30 | } // namespace dramsim3 31 | 32 | #endif -------------------------------------------------------------------------------- /src/simple_stats.h: -------------------------------------------------------------------------------- 1 | #ifndef __SIMPLE_STATS_ 2 | #define __SIMPLE_STATS_ 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | 9 | #include "configuration.h" 10 | #include "json.hpp" 11 | 12 | namespace dramsim3 { 13 | 14 | class SimpleStats { 15 | public: 16 | SimpleStats(const Config& config, int channel_id); 17 | // incrementing counter 18 | void Increment(const std::string name) { epoch_counters_[name] += 1; } 19 | 20 | // incrementing for vec counter 21 | void IncrementVec(const std::string name, int pos) { 22 | epoch_vec_counters_[name][pos] += 1; 23 | } 24 | 25 | // increment vec counter by number 26 | void IncrementVecBy(const std::string name, int pos, int num) { 27 | epoch_vec_counters_[name][pos] += num; 28 | } 29 | 30 | // add historgram value 31 | void AddValue(const std::string name, const int value); 32 | 33 | // return per rank background energy 34 | double RankBackgroundEnergy(const int r) const; 35 | 36 | // Epoch update 37 | void PrintEpochStats(); 38 | 39 | // Final statas output 40 | void PrintFinalStats(); 41 | 42 | // Reset (usually after one phase of simulation) 43 | void Reset(); 44 | 45 | private: 46 | using VecStat = std::unordered_map >; 47 | using HistoCount = std::unordered_map; 48 | using Json = nlohmann::json; 49 | void InitStat(std::string name, std::string stat_type, 50 | std::string description); 51 | void InitVecStat(std::string name, std::string stat_type, 52 | std::string description, std::string part_name, 53 | int vec_len); 54 | void InitHistoStat(std::string name, std::string description, int start_val, 55 | int end_val, int num_bins); 56 | 57 | void UpdateCounters(); 58 | void UpdateHistoBins(); 59 | void UpdatePrints(bool epoch); 60 | double GetHistoAvg(const HistoCount& histo_counts) const; 61 | std::string GetTextHeader(bool is_final) const; 62 | void UpdateEpochStats(); 63 | void UpdateFinalStats(); 64 | 65 | const Config& config_; 66 | int channel_id_; 67 | 68 | // map names to descriptions 69 | std::unordered_map header_descs_; 70 | 71 | // counter stats, indexed by their name 72 | std::unordered_map counters_; 73 | std::unordered_map epoch_counters_; 74 | 75 | // vectored counter stats, first indexed by name then by index 76 | VecStat vec_counters_; 77 | VecStat epoch_vec_counters_; 78 | 79 | // NOTE: doubles_ vec_doubles_ and calculated_ are basically one time 80 | // placeholders after each epoch they store the value for that epoch 81 | // (different from the counters) and in the end updated to the overall value 82 | std::unordered_map doubles_; 83 | 84 | std::unordered_map > vec_doubles_; 85 | 86 | // calculated stats, similar to double, but not the same 87 | std::unordered_map calculated_; 88 | 89 | // histogram stats 90 | std::unordered_map > histo_headers_; 91 | 92 | std::unordered_map > histo_bounds_; 93 | std::unordered_map bin_widths_; 94 | std::unordered_map histo_counts_; 95 | std::unordered_map epoch_histo_counts_; 96 | VecStat histo_bins_; 97 | VecStat epoch_histo_bins_; 98 | 99 | // outputs 100 | Json j_data_; 101 | std::vector > print_pairs_; 102 | }; 103 | 104 | } // namespace dramsim3 105 | #endif -------------------------------------------------------------------------------- /src/sp_ienv.c: -------------------------------------------------------------------------------- 1 | /*! \file 2 | Copyright (c) 2003, The Regents of the University of California, through 3 | Lawrence Berkeley National Laboratory (subject to receipt of any required 4 | approvals from U.S. Dept. of Energy) 5 | 6 | All rights reserved. 7 | 8 | The source code is distributed under BSD license, see the file License.txt 9 | at the top-level directory. 10 | */ 11 | #include "../ext/SuperLU_MT_3.1/SRC/slu_mt_ddefs.h" 12 | #include "../ext/SuperLU_MT_3.1/SRC/slu_mt_machines.h" 13 | 14 | int_t sp_ienv(int_t ispec) { 15 | /* 16 | * -- SuperLU MT routine (version 1.0) -- 17 | * Univ. of California Berkeley, Xerox Palo Alto Research Center, 18 | * and Lawrence Berkeley National Lab. 19 | * August 15, 1997 20 | * 21 | * Purpose 22 | * ======= 23 | * 24 | * sp_ienv() is inquired to choose machine-dependent parameters for the 25 | * local environment. See ISPEC for a description of the parameters. 26 | * 27 | * This version provides a set of parameters which should give good, 28 | * but not optimal, performance on many of the currently available 29 | * computers. Users are encouraged to modify this subroutine to set 30 | * the tuning parameters for their particular machine using the option 31 | * and problem size information in the arguments. 32 | * 33 | * Arguments 34 | * ========= 35 | * 36 | * ISPEC (input) int 37 | * Specifies the parameter to be returned as the value of SP_IENV. 38 | * = 1: the panel size w; a panel consists of w consecutive 39 | * columns of matrix A in the process of Gaussian elimination. 40 | * The best value depends on machine's cache characters. 41 | * = 2: the relaxation parameter relax; if the number of 42 | * nodes (columns) in a subtree of the elimination tree is 43 | * less than relax, this subtree is considered as one supernode, regardless 44 | * of the their row structures. = 3: the maximum size for a 45 | * supernode; = 4: the minimum row dimension for 2-D blocking to be 46 | * used; = 5: the minimum column dimension for 2-D blocking to be 47 | * used; = 6: size of the array to store the values of the L 48 | * supernodes; a negative number represents the fills growth 49 | * factor, i.e., the product of its magnitude and the number 50 | * of nonzeros in the original A will be used to allocate 51 | * storage; a positive number represents the number of 52 | * nonzeros; = 7: size of the array to store the columns in U; 53 | * a negative number represents the fills growth factor, i.e., 54 | * the product of its magnitude and the number of nonzeros in 55 | * the original A will be used to allocate storage; a positive number 56 | * represents the number of nonzeros; = 8: size of the array 57 | * to store the subscripts of the L supernodes; a negative number 58 | * represents the fills growth factor, i.e., the product of 59 | * its magnitude and the number of nonzeros in the original A 60 | * will be used to allocate storage; a positive number 61 | * represents the number of nonzeros; 62 | * 63 | * (SP_IENV) (output) int 64 | * >= 0: the value of the parameter specified by ISPEC 65 | * < 0: if SP_IENV = -k, the k-th argument had an illegal value. 66 | * 67 | * ===================================================================== 68 | */ 69 | int i; 70 | 71 | switch (ispec) { 72 | #if (MACH == SGI) 73 | case 1: 74 | return (20); 75 | case 2: 76 | return (6); 77 | case 3: 78 | return (100); 79 | case 4: 80 | return (800); 81 | case 5: 82 | return (100); 83 | #elif (MACH == ORIGIN) 84 | case 1: 85 | return (12); 86 | case 2: 87 | return (6); 88 | case 3: 89 | return (100); 90 | case 4: 91 | return (400); 92 | case 5: 93 | return (100); 94 | #elif (MACH == DEC) 95 | case 1: 96 | return (16); 97 | case 2: 98 | return (6); 99 | case 3: 100 | return (50); 101 | case 4: 102 | return (100); 103 | case 5: 104 | return (40); 105 | #elif (MACH == CRAY_PVP) 106 | case 1: 107 | return (1); 108 | case 2: 109 | return (6); 110 | case 3: 111 | return (64); 112 | case 4: 113 | return (400); 114 | case 5: 115 | return (200); 116 | #elif (MACH == SUN) 117 | case 1: 118 | return (8); 119 | case 2: 120 | return (6); 121 | case 3: 122 | return (100); 123 | case 4: 124 | return (400); 125 | case 5: 126 | return (40); 127 | #else 128 | case 1: 129 | return (8); 130 | case 2: 131 | return (1); 132 | case 3: 133 | return (200); 134 | case 4: 135 | return (200); 136 | case 5: 137 | return (40); 138 | #endif 139 | case 6: 140 | return (-20); 141 | case 7: 142 | return (-1000000); 143 | case 8: 144 | return (-1000000); 145 | } 146 | 147 | /* Invalid value for ISPEC */ 148 | i = 1; 149 | xerbla_("sp_ienv", &i); 150 | return 0; 151 | 152 | } /* sp_ienv_ */ 153 | -------------------------------------------------------------------------------- /src/thermal.h: -------------------------------------------------------------------------------- 1 | #ifndef __THERMAL_H 2 | #define __THERMAL_H 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include "bankstate.h" 11 | #include "common.h" 12 | #include "configuration.h" 13 | #include "thermal_config.h" 14 | 15 | namespace dramsim3 { 16 | 17 | extern std::function GetPhyAddress; 18 | 19 | class ThermalCalculator { 20 | public: 21 | ThermalCalculator(const Config &config); 22 | ~ThermalCalculator(); 23 | void UpdateCMDPower(const int channel, const Command &cmd, 24 | const uint64_t clk); 25 | void UpdateBackgroundEnergy(const int channel, const int rank, 26 | const double energy); 27 | // assuming evenly distributed logic layer power 28 | void UpdateEpoch(const uint64_t clk); 29 | void SetLogicPower(double logic_power); 30 | void PrintTransPT(uint64_t clk); 31 | void PrintFinalPT(uint64_t clk); 32 | void UpdateLogicPower(double logic_power); 33 | 34 | private: 35 | // Initialization 36 | double ***InitPowerM(int case_id, uint64_t clk); 37 | void InitialParameters(); 38 | 39 | // location mapping functions 40 | void SetPhyAddressMapping(); 41 | std::pair MapToVault(int channel_id); 42 | std::pair MapToBank(int bankgroup_id, int bank_id); 43 | int MapToZ(int channel_id, int bank_id); 44 | std::pair, std::vector> MapToXY(const Command &cmd, 45 | int vault_id_x, 46 | int vault_id_y, 47 | int bank_id_x, 48 | int bank_id_y); 49 | void LocationMappingANDaddEnergy_RF(const int channel, const Command &cmd, 50 | int bank0, int row0, int caseID_, 51 | double add_energy); 52 | void LocationMappingANDaddEnergy(const int channel, const Command &cmd, 53 | int bank0, int row0, int caseID_, 54 | double add_energy); 55 | void UpdatePowerMaps(double add_energy, bool trans, uint64_t clk); 56 | 57 | // calculations 58 | void CalcTransT(int case_id); 59 | void CalcFinalT(int case_id, uint64_t clk); 60 | double GetTotalPower(double ***powerM); 61 | int square_array(int total_grids_); 62 | int determineXY(double xd, double yd, int total_grids_); 63 | double GetMaxTofCase(double **temp_map, int case_id); 64 | double GetMaxTofCaseLayer(double **temp_map, int case_id, int layer); 65 | void calculate_time_step(); 66 | 67 | // print to csv-files 68 | void PrintCSV_trans(std::ofstream &csvfile, 69 | std::vector> P_, double **T_, 70 | int id, uint64_t scale); 71 | void PrintCSV_final(std::ofstream &csvfile, 72 | std::vector> P_, double **T_, 73 | int id, uint64_t scale); 74 | void PrintCSVHeader_final(std::ofstream &csvfile); 75 | void PrintCSV_bank(std::ofstream &csvfile); 76 | 77 | 78 | const Config &config_; 79 | 80 | int time_iter0, time_iter; 81 | double Tamb; // The ambient temperature in Kelvin 82 | const int num_dummy = 2; // dummy cells around the calculatd die 83 | 84 | int dimX, dimY, numP; // Dimension of the memory 85 | double **Midx; // Midx storing thermal conductance 86 | double *Cap; // Cap storing the thermal capacitance 87 | int MidxSize, CapSize; // first dimension size of Midx and Cap 88 | int T_size; 89 | double **T_trans, **T_final; 90 | 91 | int sample_id; // index of the sampling power 92 | 93 | std::vector> accu_Pmap; // accumulative power map 94 | std::vector> cur_Pmap; // current power map 95 | 96 | std::vector> refresh_count; 97 | 98 | // other intermediate parameters 99 | // not need to be defined here but it will be easy to use if it is defined 100 | int vault_x, vault_y, bank_x, bank_y; 101 | int num_case; // number of different cases where the thermal simulation is 102 | // performed 103 | std::vector layerP; 104 | 105 | // Output files 106 | std::ofstream epoch_max_temp_file_csv_; 107 | std::ofstream epoch_temperature_file_csv_; 108 | std::ofstream final_temperature_file_csv_; 109 | std::ofstream bank_position_csv_; 110 | 111 | std::vector> background_energy_; 112 | double avg_logic_power_; 113 | }; 114 | } // namespace dramsim3 115 | 116 | #endif 117 | -------------------------------------------------------------------------------- /src/thermal_config.h: -------------------------------------------------------------------------------- 1 | #ifndef THERMALCONFIG_H 2 | #define THERMALCONFIG_H 3 | 4 | #ifndef M_PI 5 | const double M_PI = 3.141592653; 6 | #endif 7 | 8 | const double T0 = 273.15; // [C] 9 | 10 | const double R_TSV = 5e-6; // [m] 11 | 12 | /* Thermal conductance */ 13 | const double Ksi = 148.0; // Silicon 14 | const double Kcu = 401.0; // Copper 15 | const double Kin = 1.5; // insulator 16 | const double Khs = 4.0; // Heat sink 17 | 18 | /* Thermal capacitance */ 19 | const double Csi = 1.66e6; // Silicon 20 | const double Ccu = 3.2e6; // Copper 21 | const double Cin = 1.65e6; // insulator 22 | const double Chs = 2.42e6; // Heat sink 23 | 24 | /* Layer Hight */ 25 | const double Hsi = 400e-6; // Silicon 26 | const double Hcu = 5e-6; // Copper 27 | const double Hin = 20e-6; // Insulator 28 | const double Hhs = 1000e-6; // Heat sink 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /src/thermal_replay.h: -------------------------------------------------------------------------------- 1 | #ifndef __THERMAL_REPLAY_H 2 | #define __THERMAL_REPLAY_H 3 | 4 | #include 5 | #include 6 | #include 7 | 8 | #include "common.h" 9 | #include "configuration.h" 10 | #include "simple_stats.h" 11 | #include "thermal.h" 12 | 13 | namespace dramsim3 { 14 | 15 | class ThermalReplay { 16 | public: 17 | ThermalReplay(std::string trace_name, std::string config_file, 18 | std::string output_dir, uint64_t repeat); 19 | ~ThermalReplay(); 20 | void Run(); 21 | 22 | private: 23 | std::vector> timed_commands_; 24 | Config config_; 25 | ThermalCalculator thermal_calc_; 26 | uint64_t repeat_; 27 | uint64_t last_clk_; 28 | std::vector channel_stats_; 29 | std::vector>>> bank_active_; 30 | void ParseLine(std::string line, uint64_t &clk, Command &cmd); 31 | void ProcessCMD(Command &cmd, uint64_t clk); 32 | bool IsRankActive(int channel, int rank); 33 | }; 34 | 35 | } // namespace dramsim3 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /src/timing.h: -------------------------------------------------------------------------------- 1 | #ifndef __TIMING_H 2 | #define __TIMING_H 3 | 4 | #include 5 | #include "common.h" 6 | #include "configuration.h" 7 | 8 | namespace dramsim3 { 9 | 10 | class Timing { 11 | public: 12 | Timing(const Config& config); 13 | std::vector > > same_bank; 14 | std::vector > > 15 | other_banks_same_bankgroup; 16 | std::vector > > 17 | other_bankgroups_same_rank; 18 | std::vector > > other_ranks; 19 | std::vector > > same_rank; 20 | }; 21 | 22 | } // namespace dramsim3 23 | #endif 24 | -------------------------------------------------------------------------------- /tests/test_config.cc: -------------------------------------------------------------------------------- 1 | #define CATCH_CONFIG_MAIN 2 | #include "catch.hpp" 3 | #include "configuration.h" 4 | 5 | TEST_CASE("Address Mapping", "[config]") { 6 | dramsim3::Config config("configs/HBM1_4Gb_x128.ini", "."); 7 | 8 | SECTION("TEST address mapping set up") { 9 | REQUIRE(config.address_mapping == "rorabgbachco"); 10 | // COL width is not necessarily the same as col bits because BL 11 | REQUIRE(config.co_pos == 0); 12 | REQUIRE(config.ch_pos == 5); 13 | REQUIRE(config.ba_pos == 8); 14 | REQUIRE(config.bg_pos == 10); 15 | REQUIRE(config.ra_pos == 12); 16 | REQUIRE(config.ro_pos == 12); 17 | } 18 | 19 | SECTION("Test address mapping column") { 20 | uint64_t hex_addr = 0x0; 21 | auto addr = config.AddressMapping(hex_addr); 22 | REQUIRE(addr.column == 0); 23 | 24 | hex_addr = 0b11111000000; 25 | addr = config.AddressMapping(hex_addr); 26 | REQUIRE(addr.column == 31); 27 | } 28 | 29 | SECTION("Test address mapping channel") { 30 | uint64_t hex_addr = 0b11111111111; 31 | auto addr = config.AddressMapping(hex_addr); 32 | REQUIRE(addr.channel == 0); 33 | 34 | hex_addr = 0b111110111111111111; 35 | addr = config.AddressMapping(hex_addr); 36 | REQUIRE(addr.channel == 5); 37 | 38 | hex_addr = 0b000011111111111111; 39 | addr = config.AddressMapping(hex_addr); 40 | REQUIRE(addr.channel == 7); 41 | } 42 | 43 | SECTION("Test address mapping bank") { 44 | uint64_t hex_addr = 0b11111111111111; 45 | auto addr = config.AddressMapping(hex_addr); 46 | REQUIRE(addr.bank == 0); 47 | 48 | hex_addr = 0b1011111111111111; 49 | addr = config.AddressMapping(hex_addr); 50 | REQUIRE(addr.bank == 2); 51 | 52 | hex_addr = 0b1111011111111111111; 53 | addr = config.AddressMapping(hex_addr); 54 | REQUIRE(addr.bank == 2); 55 | } 56 | 57 | SECTION("Test address mapping bankgroup") { 58 | uint64_t hex_addr = 0b1111111111111111; 59 | auto addr = config.AddressMapping(hex_addr); 60 | REQUIRE(addr.bankgroup == 0); 61 | 62 | hex_addr = 0b101111111111111111; 63 | addr = config.AddressMapping(hex_addr); 64 | REQUIRE(addr.bankgroup == 2); 65 | 66 | hex_addr = 0b111101111111111111111; 67 | addr = config.AddressMapping(hex_addr); 68 | REQUIRE(addr.bankgroup == 2); 69 | } 70 | 71 | SECTION("Test address mapping rank") { 72 | uint64_t hex_addr = 0xFFFFFFFFFFFF; 73 | auto addr = config.AddressMapping(hex_addr); 74 | REQUIRE(addr.rank == 0); 75 | } 76 | 77 | SECTION("Test address mapping row") { 78 | uint64_t hex_addr = 0b111111111111111111; 79 | auto addr = config.AddressMapping(hex_addr); 80 | REQUIRE(addr.row == 0); 81 | 82 | hex_addr = 0b10001111111111111111111; 83 | addr = config.AddressMapping(hex_addr); 84 | REQUIRE(addr.row == 17); 85 | 86 | hex_addr = 0b10000000000000111111111111111111; 87 | addr = config.AddressMapping(hex_addr); 88 | REQUIRE(addr.row == 0b10000000000000); 89 | 90 | hex_addr = 0b11110000000000000111111111111111111; 91 | addr = config.AddressMapping(hex_addr); 92 | REQUIRE(addr.row == 0b10000000000000); 93 | } 94 | } 95 | 96 | -------------------------------------------------------------------------------- /tests/test_dramsys.cc: -------------------------------------------------------------------------------- 1 | #include "catch.hpp" 2 | #include "configuration.h" 3 | #include "dram_system.h" 4 | 5 | bool call_back_called = false; 6 | void dummy_call_back(uint64_t addr) { 7 | call_back_called = true; 8 | return; 9 | } 10 | 11 | TEST_CASE("Jedec DRAMSystem Testing", "[dramsim3]") { 12 | dramsim3::Config config("configs/HBM1_4Gb_x128.ini", "."); 13 | 14 | dramsim3::JedecDRAMSystem dramsys(config, ".", dummy_call_back, 15 | dummy_call_back); 16 | 17 | SECTION("TEST interaction with controller") { 18 | dramsys.AddTransaction(1, false); 19 | int clk = 0; 20 | while (true) { 21 | dramsys.ClockTick(); 22 | clk++; 23 | if (call_back_called) { 24 | call_back_called = false; 25 | break; 26 | } 27 | } 28 | 29 | int tRC = config.tRCDRD + config.CL + config.BL; 30 | REQUIRE(clk == tRC); 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /tests/test_hmcsys.cc: -------------------------------------------------------------------------------- 1 | #include "catch.hpp" 2 | #include "configuration.h" 3 | #include "memory_system.h" 4 | 5 | bool hmc_called = false; 6 | 7 | void hmc_callback(uint64_t addr) { 8 | hmc_called = true; 9 | return; 10 | } 11 | 12 | TEST_CASE("HMC System Testing", "[dramsim3][hmc]") { 13 | // but THIS doesn't work? 14 | // dramsim3::Config config("configs/HMC_2GB_4Lx16.ini", "."); 15 | // dramsim3::HMCMemorySystem hmc(config, ".", hmc_callback, hmc_callback); 16 | dramsim3::MemorySystem hmc("configs/HMC_2GB_4Lx16.ini", ".", hmc_callback, hmc_callback); 17 | 18 | SECTION("TEST HMC interaction with controller") { 19 | REQUIRE(hmc.GetBurstLength() == 16); 20 | hmc.AddTransaction(1, false); 21 | int clk = 0; 22 | while (true) { 23 | hmc.ClockTick(); 24 | clk++; 25 | if (hmc_called || clk == 1000) { 26 | break; 27 | } 28 | } 29 | 30 | // For HMC things are complicated, e.g. for a 64B read request and x2 bandwidth xbar 31 | // takes 1 cycle from CPU to Link 32 | // takes 1 cycle from Link to Quad 33 | // takes 1 cycle from Quad to DRAM 34 | // takes xx cycles for DRAM to finish 35 | // takes 1 cycle from DRAM to quad 36 | // takes multiple cycles from quad to CPU 37 | // (depending on packet size, and contention) 38 | int idle_lat = 52; 39 | REQUIRE(clk == idle_lat); 40 | } 41 | } 42 | --------------------------------------------------------------------------------