├── setup-sqed-generator.sh ├── fix-ridecore-bug.sh ├── show-waveform.sh ├── setup-yosys.sh ├── setup-pono.sh ├── generate-qed-files.sh ├── SQED-Generator ├── README.txt ├── Generators │ ├── LICENSE.v │ ├── COSA_OPS │ ├── clean.py │ ├── decoder_generator.py │ ├── qed_generator.py │ ├── generate_sqed.py │ └── constraint_generator.py ├── SICFiles │ ├── single_property_NOP.txt │ ├── single_property_OR.txt │ ├── single_property_ADD.txt │ ├── single_property_AND.txt │ ├── single_property_LW.txt │ ├── single_property_MUL.txt │ ├── single_property_SLL.txt │ ├── single_property_SLT.txt │ ├── single_property_SRA.txt │ ├── single_property_SRL.txt │ ├── single_property_SUB.txt │ ├── single_property_SW.txt │ ├── single_property_MULH.txt │ ├── single_property_ORI.txt │ ├── single_property_SLTU.txt │ ├── single_property_XOR.txt │ ├── single_property_ADDI.txt │ ├── single_property_ANDI.txt │ ├── single_property_MULHU.txt │ ├── single_property_SLLI.txt │ ├── single_property_SLTI.txt │ ├── single_property_SRAI.txt │ ├── single_property_SRLI.txt │ ├── single_property_XORI.txt │ ├── single_property_MULHSU.txt │ └── single_property_SLTIU.txt ├── QEDFiles │ ├── qed_instruction_mux.v │ └── qed_i_cache.v ├── TODO.txt ├── FormatFiles │ ├── BlackParrot_format.txt │ ├── ORBIS32_format.txt │ └── RV32M-ridecore_format.txt ├── LICENSE-Academic ├── LICENSE-GOV ├── Interface │ └── module_interface.py └── FormatParsers │ └── format_parser.py ├── ridecore-src-buggy ├── imem_outa.v ├── dmem.v ├── alu_ops.vh ├── srcopr_manager.v ├── imem.v ├── brimm_gen.v ├── imm_gen.v ├── search_be.v ├── srcsel.v ├── alu.v ├── exunit_mul.v ├── src_manager.v ├── rs_reqgen.v ├── btb.v ├── tag_generator.v ├── main.xdc ├── rrf_freelistmanager.v ├── multiplier.v ├── exunit_alu.v ├── prioenc.v ├── exunit_branch.v ├── dualport_ram.v ├── define.v ├── alloc_issue_ino.v ├── rv32_opcodes.vh ├── LICENSE ├── constants.vh ├── pipeline_if.v ├── exunit_ldst.v ├── topsim.v ├── top.v ├── oldest_finder.v ├── rrf.v ├── gshare.v ├── mpft.v ├── storebuf.v ├── reorderbuf.v ├── system.v ├── ram_sync_nolatch.v └── ram_sync.v ├── qed-wireup-patches ├── step0-dmem-changes-optimization.patch ├── step1-topsim-changes.patch ├── step2-pipeline-changes-optimization.patch ├── step2-topsim-changes.patch ├── step3-topsim-changes.patch ├── step0-arf-changes.patch ├── step0-ram_sync_nolatch-changes.patch ├── step1-pipeline_if-changes-optimization.patch ├── step1-pipeline-changes.patch ├── step0-topsim-changes.patch ├── step0-pipeline_if-changes-optimization.patch └── step0-pipeline-changes.patch ├── docker └── Dockerfile ├── run-pono.sh ├── bug-trace-gtkwave.gtkw ├── ridecore-bugfix-patch ├── ridecore-bugfix-rs_mul.patch └── ridecore-bugfix-rs_mul.patch-BACKUP ├── BSD_LICENSE ├── wire-up-qed-module.sh ├── bug-trace-k10-cosa-log.txt └── gen-btor.ys /setup-sqed-generator.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | git clone https://github.com/upscale-project/sqed-generator.git 4 | -------------------------------------------------------------------------------- /fix-ridecore-bug.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | patch -i ridecore-bugfix-patch/ridecore-bugfix-rs_mul.patch ridecore-src-buggy/rs_mul.v 4 | -------------------------------------------------------------------------------- /show-waveform.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | echo "gtkwave ./bug-trace-k10.vcd bug-trace-gtkwave.gtkw'" 4 | gtkwave ./bug-trace-k10.vcd bug-trace-gtkwave.gtkw 2>/dev/null 5 | -------------------------------------------------------------------------------- /setup-yosys.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Pinning yosys version 4 | YOSYS_VERSION=859e52af59e75689f7b0615899bc3356ba5a7ca1 5 | 6 | git clone https://github.com/YosysHQ/yosys.git 7 | cd yosys 8 | git checkout -f $YOSYS_VERSION 9 | make -j4 10 | cd ../ 11 | 12 | -------------------------------------------------------------------------------- /setup-pono.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | git clone https://github.com/upscale-project/pono.git 4 | cd pono 5 | ./contrib/setup-btor2tools.sh 6 | ./contrib/setup-bison.sh 7 | ./contrib/setup-smt-switch.sh 8 | ./configure.sh 9 | cd build 10 | make -j4 11 | make test 12 | cd ../../ 13 | -------------------------------------------------------------------------------- /generate-qed-files.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd ./sqed-generator/SQED-Generator/Generators/ 4 | 5 | python ./generate_sqed.py ../FormatFiles/RV32M-ridecore_format.txt ../QEDFiles 6 | 7 | cp ../Design_Independent_QED_Files/* ../QEDFiles 8 | 9 | cd .. 10 | 11 | cd .. 12 | 13 | cd .. 14 | -------------------------------------------------------------------------------- /SQED-Generator/README.txt: -------------------------------------------------------------------------------- 1 | This directory will contain the generic SQED module, and the common 2 | submodules that are shared across all the different QED 3 | implementations. 4 | 5 | To come up with the generic SQED module, we analyze common parts of 6 | the custom modules in "../custom-sqed-modules/". 7 | -------------------------------------------------------------------------------- /SQED-Generator/Generators/LICENSE.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) Stanford University 2 | // 3 | // This source code is patent protected and being made available under the 4 | // terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | // 6 | // Author: Mario J Srouji 7 | // Email: msrouji@stanford.edu 8 | -------------------------------------------------------------------------------- /SQED-Generator/Generators/COSA_OPS: -------------------------------------------------------------------------------- 1 | AND:& 2 | OR:| 3 | NOT:! 4 | SL:<< 5 | SR:>> 6 | ASR:a>> 7 | IFF:<-> 8 | IMPLIES:-> 9 | ULTE:u<= 10 | UGTE:u>= 11 | ULT:u< 12 | UGT:u> 13 | SLTE:s<= 14 | SGTE:s>= 15 | SLT:s< 16 | SGT:s> 17 | GTE:>= 18 | LTE:<= 19 | GT:> 20 | LT:< 21 | EQUAL:= 22 | ADD:+ 23 | SUB:- 24 | MUL:* 25 | POW:^ 26 | UDIV:u/ 27 | SDIV:s/ 28 | DIV:/ 29 | SREM:s% 30 | UREM:u% 31 | XOR:xor 32 | -------------------------------------------------------------------------------- /ridecore-src-buggy/imem_outa.v: -------------------------------------------------------------------------------- 1 | module imem_outa 2 | ( 3 | input [27:0] pc, 4 | output reg [127:0] idata 5 | ); 6 | 7 | always @ (*) begin 8 | case(pc) 9 | 28'h0: idata = 128'h00202023001081130010202304100093; 10 | 28'h1: idata = 128'h0000000000000000ffdff06f00202423; 11 | default: idata = 128'h0; 12 | endcase // case (pc) 13 | end 14 | endmodule // imem_outa 15 | 16 | -------------------------------------------------------------------------------- /SQED-Generator/Generators/clean.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) Stanford University 2 | # 3 | # This source code is patent protected and being made available under the 4 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | # Author: Mario J Srouji 7 | # Email: msrouji@stanford.edu 8 | 9 | import os 10 | 11 | os.remove("../QEDFiles/inst_constraints.v") 12 | os.remove("../QEDFiles/modify_instruction.v") 13 | os.remove("../QEDFiles/qed_decoder.v") 14 | os.remove("../QEDFiles/qed.v") 15 | -------------------------------------------------------------------------------- /qed-wireup-patches/step0-dmem-changes-optimization.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 10,16 **** 3 | output reg [`DATA_LEN-1:0] rdata 4 | ); 5 | 6 | ! reg [`DATA_LEN-1:0] mem [0:2047]; 7 | 8 | always @ (posedge clk) begin 9 | rdata <= mem[addr[10:0]]; 10 | --- 10,16 ---- 11 | output reg [`DATA_LEN-1:0] rdata 12 | ); 13 | 14 | ! reg [`DATA_LEN-1:0] mem [0:31]; 15 | 16 | always @ (posedge clk) begin 17 | rdata <= mem[addr[10:0]]; 18 | -------------------------------------------------------------------------------- /ridecore-src-buggy/dmem.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | //8KB Single PORT synchronous BRAM 4 | module dmem 5 | ( 6 | input wire clk, 7 | input wire [`ADDR_LEN-1:0] addr, 8 | input wire [`DATA_LEN-1:0] wdata, 9 | input wire we, 10 | output reg [`DATA_LEN-1:0] rdata 11 | ); 12 | 13 | reg [`DATA_LEN-1:0] mem [0:2047]; 14 | 15 | always @ (posedge clk) begin 16 | rdata <= mem[addr[10:0]]; 17 | if (we) 18 | mem[addr] <= wdata; 19 | end 20 | endmodule // dmem 21 | `default_nettype wire 22 | -------------------------------------------------------------------------------- /docker/Dockerfile: -------------------------------------------------------------------------------- 1 | FROM ubuntu:18.04 2 | WORKDIR /home/sqed-demo 3 | 4 | ENV DEBIAN_FRONTEND=noninteractive 5 | RUN apt-get update 6 | RUN apt-get install -y clang cmake libpcre* wget unzip build-essential automake libgmp-dev curl nano libboost-dev default-jdk libclang-dev llvm llvm-dev lbzip2 libncurses5-dev git libtool iverilog bison flex libreadline-dev gawk tcl-dev libffi-dev graphviz xdot pkg-config gtkwave 7 | 8 | RUN git clone -b pono https://github.com/upscale-project/generic-sqed-demo.git 9 | 10 | RUN cd generic-sqed-demo && ./setup-yosys.sh && ./setup-pono.sh 11 | 12 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_NOP.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for NOP] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.NOP = 1_1);(state_counter = 1_10) -> ((inst_constraint0.NOP = 1_1)); 17 | properties: (state_counter = 7_10) -> -------------------------------------------------------------------------------- /ridecore-src-buggy/alu_ops.vh: -------------------------------------------------------------------------------- 1 | `define ALU_OP_WIDTH 4 2 | 3 | `define ALU_OP_ADD `ALU_OP_WIDTH'd0 4 | `define ALU_OP_SLL `ALU_OP_WIDTH'd1 5 | `define ALU_OP_XOR `ALU_OP_WIDTH'd4 6 | `define ALU_OP_OR `ALU_OP_WIDTH'd6 7 | `define ALU_OP_AND `ALU_OP_WIDTH'd7 8 | `define ALU_OP_SRL `ALU_OP_WIDTH'd5 9 | `define ALU_OP_SEQ `ALU_OP_WIDTH'd8 10 | `define ALU_OP_SNE `ALU_OP_WIDTH'd9 11 | `define ALU_OP_SUB `ALU_OP_WIDTH'd10 12 | `define ALU_OP_SRA `ALU_OP_WIDTH'd11 13 | `define ALU_OP_SLT `ALU_OP_WIDTH'd12 14 | `define ALU_OP_SGE `ALU_OP_WIDTH'd13 15 | `define ALU_OP_SLTU `ALU_OP_WIDTH'd14 16 | `define ALU_OP_SGEU `ALU_OP_WIDTH'd15 17 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_OR.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for OR] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.OR = 1_1);(state_counter = 1_10) -> ((inst_constraint0.OR = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 | val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_ADD.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for ADD] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.ADD = 1_1);(state_counter = 1_10) -> ((inst_constraint0.ADD = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 + val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_AND.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for AND] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.AND = 1_1);(state_counter = 1_10) -> ((inst_constraint0.AND = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 & val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_LW.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for LW] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.LW = 1_1);(state_counter = 1_10) -> ((inst_constraint0.LW = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 8_10) -> (datamemory.mem = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_MUL.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for MUL] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.MUL = 1_1);(state_counter = 1_10) -> ((inst_constraint0.MUL = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 * val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SLL.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SLL] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SLL = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SLL = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 << val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SLT.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SLT] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SLT = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SLT = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 < val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SRA.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SRA] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SRA = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SRA = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 >> val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SRL.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SRL] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SRL = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SRL = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 >> val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SUB.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SUB] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SUB = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SUB = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 - val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SW.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SW] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SW = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SW = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 9_10) -> (datamemory.mem = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_MULH.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for MULH] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.MULH = 1_1);(state_counter = 1_10) -> ((inst_constraint0.MULH = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 * val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_ORI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for ORI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.ORI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.ORI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 | imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SLTU.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SLTU] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SLTU = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SLTU = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 < val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_XOR.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for XOR] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.XOR = 1_1);(state_counter = 1_10) -> ((inst_constraint0.XOR = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 xor val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /qed-wireup-patches/step1-topsim-changes.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 10,15 **** 3 | --- 10,17 ---- 4 | // input RXD, 5 | // output reg [7:0] LED 6 | input clk, 7 | + // EDIT: make instruction a top-level input 8 | + input [`INSN_LEN-1:0] instruction, 9 | input reset_x 10 | ); 11 | 12 | *************** 13 | *** 79,86 **** 14 | --- 81,90 ---- 15 | .RST_X_O(reset_x) 16 | ); 17 | */ 18 | + // EDIT: wire up the instruction to the new inst1 port 19 | pipeline pipe 20 | ( 21 | + .inst1(instruction), 22 | .clk(clk), 23 | .reset(~reset_x | prog_loading), 24 | .pc(pc), 25 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_ADDI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for ADDI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.ADDI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.ADDI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 + imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_ANDI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for ANDI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.ANDI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.ANDI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 & imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_MULHU.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for MULHU] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.MULHU = 1_1);(state_counter = 1_10) -> ((inst_constraint0.MULHU = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 * val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SLLI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SLLI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SLLI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SLLI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 << imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SLTI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SLTI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SLTI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SLTI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 < imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SRAI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SRAI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SRAI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SRAI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 >> imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SRLI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SRLI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SRLI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SRLI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 >> imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_XORI.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for XORI] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.XORI = 1_1);(state_counter = 1_10) -> ((inst_constraint0.XORI = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 xor imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_MULHSU.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for MULHSU] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.MULHSU = 1_1);(state_counter = 1_10) -> ((inst_constraint0.MULHSU = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 * val2) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /SQED-Generator/SICFiles/single_property_SLTIU.txt: -------------------------------------------------------------------------------- 1 | [GENERAL] 2 | default_initial_value: 0 3 | vcd: True 4 | abstract_clock: True 5 | no_arrays: False 6 | model_files: ridecore.vlist[top],init.ssts,nop_m.ssts,state_copy.ssts 7 | 8 | [DEFAULT] 9 | solver_name: btor 10 | prove: False 11 | 12 | [CHECK for SLTIU] 13 | bmc_length: 8 14 | description: "Check for Single Instruction" 15 | verification: safety 16 | assumptions: (reset_x = 1_1);(state_counter = 0_10) -> (inst_constraint0.SLTIU = 1_1);(state_counter = 1_10) -> ((inst_constraint0.SLTIU = 1_1) & (rd != 0_5)); 17 | properties: (state_counter = 7_10) -> ((val1 < imm_copy) = pipe.aregfile.regfile.mem[rd_copy]) 18 | -------------------------------------------------------------------------------- /qed-wireup-patches/step2-pipeline-changes-optimization.patch: -------------------------------------------------------------------------------- 1 | --- ./pipeline.v 2020-09-14 16:30:52.937524433 -0700 2 | +++ ./ridecore-src-buggy/pipeline.v 2020-09-14 16:33:46.616923174 -0700 3 | @@ -557,10 +557,12 @@ 4 | // EDIT: send the output of the QED module through the pipeline. 5 | //inst1_if <= inst1; 6 | inst1_if <= qed_ifu_instruction; 7 | - inst2_if <= inst2; 8 | + //inst2_if <= inst2; 9 | + inst2_if <= 32'd0; 10 | //inv1_if <= 0; 11 | inv1_if <= ~qed_vld_out; // change to vld_out of qed0 12 | - inv2_if <= invalid2_pipe; 13 | + //inv2_if <= invalid2_pipe; 14 | + inv2_if <= 1'b1; 15 | // EDIT END 16 | bhr_if <= bhr; 17 | 18 | -------------------------------------------------------------------------------- /qed-wireup-patches/step2-topsim-changes.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 50,55 **** 3 | --- 50,61 ---- 4 | wire [`ADDR_LEN-1:0] prog_loadaddr = 0; 5 | wire prog_dmem_we = 0; 6 | wire prog_imem_we = 0; 7 | + 8 | + // EDIT: Use the inst_constraint module to constrain instruction to be 9 | + // a valid instruction from the ISA 10 | + inst_constraint inst_constraint0(.clk(clk), 11 | + .instruction(instruction)); 12 | + // EDIT END 13 | /* 14 | assign utx_we = (dmem_we_core && (dmem_addr_core == 32'h0)) ? 1'b1 : 1'b0; 15 | assign finish_we = (dmem_we_core && (dmem_addr_core == 32'h8)) ? 1'b1 : 1'b0; 16 | -------------------------------------------------------------------------------- /run-pono.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # generate the btor 4 | echo "Generating BTOR2 using yosys" 5 | # prefer local version 6 | if [ -f ./yosys/yosys ]; then 7 | YOSYS=./yosys/yosys 8 | elif [ `which yosys` ]; then 9 | YOSYS=yosys 10 | else 11 | echo "Could not find Yosys. Needed to generate BTOR2" 12 | exit 1 13 | fi 14 | 15 | $YOSYS -q -s gen-btor.ys 16 | 17 | # run pono 18 | echo "" 19 | echo "Running pono" 20 | # prefer local version 21 | if [ -f ./pono/build/pono ]; then 22 | PONO=./pono/build/pono 23 | elif [ `which pono` ]; then 24 | PONO=pono 25 | else 26 | echo "Could not find Pono." 27 | exit 1 28 | fi 29 | $PONO -v 1 -k 12 --vcd ridecore-trace.vcd ./ridecore.btor2 30 | -------------------------------------------------------------------------------- /qed-wireup-patches/step3-topsim-changes.patch: -------------------------------------------------------------------------------- 1 | --- ./ridecore-src-buggy/topsim.v 2020-09-14 16:16:24.962164339 -0700 2 | +++ ./topsim.v 2020-09-14 16:15:32.497772534 -0700 3 | @@ -15,6 +15,16 @@ 4 | input reset_x 5 | ); 6 | 7 | + // embed the assumption that there's no reset 8 | + // into the generated BTOR2 9 | + // we will run the reset sequence in Yosys before generating the BTOR2 10 | + // it will complain about the violated assumption, but should work 11 | + // fine otherwise 12 | + // this is a neg-edge reset, so we assume it is 1. 13 | + always @* begin 14 | + no_reset: assume(reset_x); 15 | + end 16 | + 17 | //Active Low SW 18 | // wire clk; 19 | // wire reset_x; 20 | -------------------------------------------------------------------------------- /SQED-Generator/QEDFiles/qed_instruction_mux.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) Stanford University 2 | // 3 | // This source code is patent protected and being made available under the 4 | // terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | module qed_instruction_mux ( 7 | // Outputs 8 | qed_ifu_instruction, 9 | // Inputs 10 | ifu_qed_instruction, 11 | qed_instruction, 12 | ena, 13 | exec_dup 14 | ); 15 | 16 | input [31:0] ifu_qed_instruction; 17 | input [31:0] qed_instruction; 18 | input exec_dup; 19 | input ena; 20 | 21 | output [31:0] qed_ifu_instruction; 22 | 23 | assign qed_ifu_instruction = ena ? ((exec_dup == 1'b0) ? ifu_qed_instruction : qed_instruction) : ifu_qed_instruction; 24 | 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /qed-wireup-patches/step0-arf-changes.patch: -------------------------------------------------------------------------------- 1 | --- ./ridecore-src-buggy/arf.v 2020-09-14 16:15:59.522216010 -0700 2 | +++ ./arf.v 2020-09-14 16:15:45.283908584 -0700 3 | @@ -40,7 +40,9 @@ 4 | input wire prsuccess, 5 | input wire [`SPECTAG_LEN-1:0] prtag, 6 | input wire [`SPECTAG_LEN-1:0] mpft_valid1, 7 | - input wire [`SPECTAG_LEN-1:0] mpft_valid2 8 | + input wire [`SPECTAG_LEN-1:0] mpft_valid2, 9 | + output wire [`DATA_LEN-1:0] mem1, 10 | + output wire [`DATA_LEN-1:0] mem17 11 | ); 12 | 13 | // Set priority on instruction2 WriteBack 14 | @@ -80,7 +82,9 @@ 15 | .wdata2(wdata2), 16 | // .we1(we1_prior2), 17 | .we1(we1_0reg), 18 | - .we2(we2_0reg) 19 | + .we2(we2_0reg), 20 | + .mem1(mem1), 21 | + .mem17(mem17) 22 | ); 23 | 24 | 25 | -------------------------------------------------------------------------------- /qed-wireup-patches/step0-ram_sync_nolatch-changes.patch: -------------------------------------------------------------------------------- 1 | --- ./ridecore-src-buggy/ram_sync_nolatch.v 2020-09-14 16:15:59.534217925 -0700 2 | +++ ./ram_sync_nolatch.v 2020-09-14 16:15:55.397555066 -0700 3 | @@ -128,7 +128,9 @@ 4 | input wire [BRAM_DATA_WIDTH-1:0] wdata1, 5 | input wire [BRAM_DATA_WIDTH-1:0] wdata2, 6 | input wire we1, 7 | - input wire we2 8 | + input wire we2, 9 | + output wire [BRAM_DATA_WIDTH-1:0] mem1, 10 | + output wire [BRAM_DATA_WIDTH-1:0] mem17 11 | ); 12 | 13 | reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1]; 14 | @@ -144,6 +146,9 @@ 15 | if (we2) 16 | mem[waddr2] <= wdata2; 17 | end 18 | + 19 | + assign mem1 = mem[1]; 20 | + assign mem17 = mem[17]; 21 | endmodule // ram_sync_nolatch_4r2w 22 | 23 | /* 24 | -------------------------------------------------------------------------------- /ridecore-src-buggy/srcopr_manager.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module sourceoperand_manager 4 | ( 5 | input wire [`DATA_LEN-1:0] arfdata, 6 | input wire arf_busy, 7 | input wire rrf_valid, 8 | input wire [`RRF_SEL-1:0] rrftag, 9 | input wire [`DATA_LEN-1:0] rrfdata, 10 | input wire [`RRF_SEL-1:0] dst1_renamed, 11 | input wire src_eq_dst1, 12 | input wire src_eq_0, 13 | output wire [`DATA_LEN-1:0] src, 14 | output wire rdy 15 | ); 16 | 17 | assign src = src_eq_0 ? `DATA_LEN'b0 : 18 | src_eq_dst1 ? dst1_renamed : 19 | ~arf_busy ? arfdata : 20 | rrf_valid ? rrfdata : 21 | rrftag; 22 | assign rdy = src_eq_0 | (~src_eq_dst1 & (~arf_busy | rrf_valid)); 23 | 24 | endmodule // sourceoperand_manager 25 | `default_nettype wire 26 | -------------------------------------------------------------------------------- /qed-wireup-patches/step1-pipeline_if-changes-optimization.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 51,56 **** 3 | --- 51,57 ---- 4 | .invalid(invalid2) 5 | ); 6 | 7 | + /* EDIT: remove branch target buffer to get rid of neg-edge behavior 8 | btb brtbl( 9 | .clk(clk), 10 | .reset(reset), 11 | *************** 12 | *** 62,68 **** 13 | .jmpdst(btb_jmpdst), 14 | .invalid2(invalid2) 15 | ); 16 | ! 17 | // EDIT: manually cut predict_cond and bhr and assign it to 0 18 | assign predict_cond = 1'b0; 19 | assign bhr = 1'b0; 20 | --- 63,70 ---- 21 | .jmpdst(btb_jmpdst), 22 | .invalid2(invalid2) 23 | ); 24 | ! */ 25 | ! 26 | // EDIT: manually cut predict_cond and bhr and assign it to 0 27 | assign predict_cond = 1'b0; 28 | assign bhr = 1'b0; 29 | -------------------------------------------------------------------------------- /ridecore-src-buggy/imem.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | // 8KB Instruction Memory (32bit*4way) 4 | module imem( 5 | input wire clk, 6 | input wire [8:0] addr, 7 | output reg [`INSN_LEN*4-1:0] data 8 | ); 9 | reg [`INSN_LEN*4-1:0] mem[0:511]; 10 | always @ (posedge clk) begin 11 | data <= mem[addr]; 12 | end 13 | endmodule // imem 14 | 15 | module imem_ld( 16 | input wire clk, 17 | input wire [8:0] addr, 18 | output reg [4*`INSN_LEN-1:0] rdata, 19 | input wire [4*`INSN_LEN-1:0] wdata, 20 | input wire we 21 | ); 22 | reg [`INSN_LEN*4-1:0] mem[0:511]; 23 | always @ (posedge clk) begin 24 | rdata <= mem[addr]; 25 | if (we) begin 26 | mem[addr] <= wdata; 27 | end 28 | end 29 | endmodule 30 | `default_nettype wire 31 | -------------------------------------------------------------------------------- /SQED-Generator/TODO.txt: -------------------------------------------------------------------------------- 1 | - Add more error detection in parser + generators (maybe). 2 | - Create format file checker that informs user of potential issues - like including fields that are not defined. 3 | - Create a detailed README for tool. 4 | - Clean up and comment code. 5 | - Try out new ISAs and create case study sub-directories in git repo that are complete for a demo (and work). 6 | - Release another public version of the tool. 7 | - Make tool generate the cache and mux files in case instructions are different bit-widths. 8 | - Figure out a method to help wire SQED to a processor (move qed_ready signal logic, think of a new way / automate). 9 | - Is there a way to generate the format file / make a tool that can help the user generate it. 10 | 11 | - Generate .ssts files for SIC 12 | - Fixes in SIC_generator.py 13 | - Need tool to generalize better (try another ISA) 14 | -------------------------------------------------------------------------------- /ridecore-src-buggy/brimm_gen.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `include "rv32_opcodes.vh" 3 | `default_nettype none 4 | module brimm_gen 5 | ( 6 | input wire [`INSN_LEN-1:0] inst, 7 | output wire [`DATA_LEN-1:0] brimm 8 | ); 9 | 10 | wire [`DATA_LEN-1:0] br_offset = { {20{inst[31]}}, inst[7], 11 | inst[30:25], inst[11:8], 1'b0 }; 12 | wire [`DATA_LEN-1:0] jal_offset = { {12{inst[31]}}, inst[19:12], 13 | inst[20], inst[30:25], inst[24:21], 1'b0 }; 14 | wire [`DATA_LEN-1:0] jalr_offset = { {21{inst[31]}}, inst[30:21], 1'b0 }; 15 | 16 | wire [6:0] opcode = inst[6:0]; 17 | 18 | assign brimm = (opcode == `RV32_BRANCH) ? br_offset : 19 | (opcode == `RV32_JAL) ? jal_offset : 20 | (opcode == `RV32_JALR) ? jalr_offset : 21 | `DATA_LEN'b0; 22 | 23 | endmodule // brimm_gen 24 | `default_nettype wire 25 | -------------------------------------------------------------------------------- /ridecore-src-buggy/imm_gen.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module imm_gen( 4 | input wire [`INSN_LEN-1:0] inst, 5 | input wire [`IMM_TYPE_WIDTH-1:0] imm_type, 6 | output reg [`DATA_LEN-1:0] imm 7 | ); 8 | 9 | always @(*) begin 10 | case (imm_type) 11 | `IMM_I : imm = { {21{inst[31]}}, inst[30:25], inst[24:21], inst[20] }; 12 | `IMM_S : imm = { {21{inst[31]}}, inst[30:25], inst[11:8], inst[7] }; 13 | `IMM_U : imm = { inst[31], inst[30:20], inst[19:12], 12'b0 }; 14 | `IMM_J : imm = { {12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], 1'b0 }; 15 | default : imm = { {21{inst[31]}}, inst[30:25], inst[24:21], inst[20] }; 16 | endcase // case (imm_type) 17 | end 18 | 19 | endmodule // imm_gen 20 | 21 | 22 | 23 | 24 | `default_nettype wire 25 | -------------------------------------------------------------------------------- /ridecore-src-buggy/search_be.v: -------------------------------------------------------------------------------- 1 | 2 | module search_begin #( 3 | parameter ENTSEL = 2, 4 | parameter ENTNUM = 4 5 | ) 6 | ( 7 | input wire [ENTNUM-1:0] in, 8 | output reg [ENTSEL-1:0] out, 9 | output reg en 10 | ); 11 | 12 | integer i; 13 | always @ (*) begin 14 | out = 0; 15 | en = 0; 16 | for (i = ENTNUM-1; i >= 0 ; i = i - 1) begin 17 | if (in[i]) begin 18 | out = i; 19 | en = 1; 20 | end 21 | end 22 | end 23 | 24 | endmodule // search_from_top 25 | 26 | module search_end #( 27 | parameter ENTSEL = 2, 28 | parameter ENTNUM = 4 29 | ) 30 | ( 31 | input wire [ENTNUM-1:0] in, 32 | output reg [ENTSEL-1:0] out, 33 | output reg en 34 | ); 35 | 36 | integer i; 37 | always @ (*) begin 38 | out = 0; 39 | en = 0; 40 | for (i = 0 ; i < ENTNUM ; i = i + 1) begin 41 | if (in[i]) begin 42 | out = i; 43 | en = 1; 44 | end 45 | end 46 | end 47 | 48 | endmodule // search_from_bottom 49 | -------------------------------------------------------------------------------- /bug-trace-gtkwave.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Tue Jun 18 07:23:00 2019 4 | [*] 5 | [dumpfile] "/home/florian/git/github/generic-sqed-demo/bug-trace-k10.vcd" 6 | [dumpfile_mtime] "Wed May 29 19:47:10 2019" 7 | [dumpfile_size] 3487407 8 | [savefile] "/home/florian/git/github/generic-sqed-demo/bug-trace-gtkwave.gtkw" 9 | [timestart] 0 10 | [size] 1920 1025 11 | [pos] -1 -1 12 | *0.111031 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] pipe. 14 | [treeopen] pipe.aregfile. 15 | [sst_width] 223 16 | [signals_width] 230 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 427 19 | @28 20 | pipe.clk[0] 21 | @22 22 | pipe.num_orig_insts[15:0] 23 | pipe.num_dup_insts[15:0] 24 | [color] 7 25 | pipe.aregfile.regfile.mem[1][31:0] 26 | [color] 7 27 | pipe.aregfile.regfile.mem[17][31:0] 28 | @28 29 | [color] 1 30 | pipe.dec1.inst[31:0] 31 | pipe.dec1.opcode[6:0] 32 | @22 33 | pipe.dec1.rd[4:0] 34 | pipe.dec1.rs1[4:0] 35 | pipe.dec1.rs2[4:0] 36 | @25 37 | pipe.dec1.funct12[11:0] 38 | [pattern_trace] 1 39 | [pattern_trace] 0 40 | -------------------------------------------------------------------------------- /qed-wireup-patches/step1-pipeline-changes.patch: -------------------------------------------------------------------------------- 1 | --- ./ridecore-src-buggy/pipeline.v 2020-09-14 16:31:19.047685778 -0700 2 | +++ ./pipeline.v 2020-09-14 16:30:52.937524433 -0700 3 | @@ -859,6 +859,8 @@ 4 | .comptr(comptr), 5 | .nextrrfcyc(nextrrfcyc) 6 | ); 7 | + wire [`DATA_LEN-1:0] mem1; 8 | + wire [`DATA_LEN-1:0] mem17; 9 | 10 | arf aregfile( 11 | .clk(clk), 12 | @@ -904,7 +906,9 @@ 13 | (isbranch1_id ? ~sptag1_id : ~(`SPECTAG_LEN'b0)) & 14 | (isbranch2_id ? ~sptag2_id : ~(`SPECTAG_LEN'b0))), 15 | .mpft_valid2(mpft_valid & 16 | - (isbranch2_id ? ~sptag2_id : ~(`SPECTAG_LEN'b0))) 17 | + (isbranch2_id ? ~sptag2_id : ~(`SPECTAG_LEN'b0))), 18 | + .mem1(mem1), 19 | + .mem17(mem17) 20 | ); 21 | 22 | assign rrftagfix = buf_rrftag_branch + 1; 23 | @@ -1994,6 +1998,14 @@ 24 | end 25 | 26 | assign qed_ready = (num_orig_insts == num_dup_insts); 27 | + 28 | + always @(posedge clk) 29 | + begin 30 | + if (qed_ready) begin 31 | + sqed: assert property (mem1 == mem17); 32 | + end 33 | + end 34 | + 35 | 36 | // EDIT END 37 | 38 | -------------------------------------------------------------------------------- /ridecore-bugfix-patch/ridecore-bugfix-rs_mul.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 346,354 **** 3 | .wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2), 4 | .wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2), 5 | .wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2), 6 | ! .wsrc1_signed((we1 && (waddr1 == 0)) ? wsrc1_signed_1 : wsrc1_signed_2), 7 | ! .wsrc2_signed((we1 && (waddr1 == 0)) ? wsrc2_signed_1 : wsrc2_signed_2), 8 | ! .wsel_lohi((we1 && (waddr1 == 0)) ? wsel_lohi_1 : wsel_lohi_2), 9 | .we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))), 10 | .ex_src1(ex_src1_1), 11 | .ex_src2(ex_src2_1), 12 | --- 346,354 ---- 13 | .wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2), 14 | .wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2), 15 | .wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2), 16 | ! .wsrc1_signed((we1 && (waddr1 == 1)) ? wsrc1_signed_1 : wsrc1_signed_2), 17 | ! .wsrc2_signed((we1 && (waddr1 == 1)) ? wsrc2_signed_1 : wsrc2_signed_2), 18 | ! .wsel_lohi((we1 && (waddr1 == 1)) ? wsel_lohi_1 : wsel_lohi_2), 19 | .we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))), 20 | .ex_src1(ex_src1_1), 21 | .ex_src2(ex_src2_1), 22 | -------------------------------------------------------------------------------- /ridecore-src-buggy/srcsel.v: -------------------------------------------------------------------------------- 1 | `include "rv32_opcodes.vh" 2 | `include "constants.vh" 3 | `default_nettype none 4 | module src_a_mux( 5 | input wire [`SRC_A_SEL_WIDTH-1:0] src_a_sel, 6 | input wire [`ADDR_LEN-1:0] pc, 7 | input wire [`DATA_LEN-1:0] rs1, 8 | output reg [`DATA_LEN-1:0] alu_src_a 9 | ); 10 | 11 | 12 | always @(*) begin 13 | case (src_a_sel) 14 | `SRC_A_RS1 : alu_src_a = rs1; 15 | `SRC_A_PC : alu_src_a = pc; 16 | default : alu_src_a = 0; 17 | endcase // case (src_a_sel) 18 | end 19 | 20 | endmodule // src_a_mux 21 | 22 | 23 | module src_b_mux( 24 | input wire [`SRC_B_SEL_WIDTH-1:0] src_b_sel, 25 | input wire [`DATA_LEN-1:0] imm, 26 | input wire [`DATA_LEN-1:0] rs2, 27 | output reg [`DATA_LEN-1:0] alu_src_b 28 | ); 29 | 30 | 31 | always @(*) begin 32 | case (src_b_sel) 33 | `SRC_B_RS2 : alu_src_b = rs2; 34 | `SRC_B_IMM : alu_src_b = imm; 35 | `SRC_B_FOUR : alu_src_b = 4; 36 | default : alu_src_b = 0; 37 | endcase // case (src_b_sel) 38 | end 39 | 40 | endmodule // src_b_mux 41 | `default_nettype wire 42 | -------------------------------------------------------------------------------- /qed-wireup-patches/step0-topsim-changes.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 17,32 **** 3 | // wire clk; 4 | // wire reset_x; 5 | 6 | ! 7 | wire [`ADDR_LEN-1:0] pc; 8 | wire [4*`INSN_LEN-1:0] idata; 9 | wire [8:0] imem_addr; 10 | wire [`DATA_LEN-1:0] dmem_data; 11 | wire [`DATA_LEN-1:0] dmem_wdata; 12 | wire [`ADDR_LEN-1:0] dmem_addr; 13 | wire dmem_we; 14 | wire [`DATA_LEN-1:0] dmem_wdata_core; 15 | wire [`ADDR_LEN-1:0] dmem_addr_core; 16 | wire dmem_we_core; 17 | 18 | wire utx_we; 19 | --- 17,41 ---- 20 | // wire clk; 21 | // wire reset_x; 22 | 23 | ! (* keep *) 24 | wire [`ADDR_LEN-1:0] pc; 25 | + (* keep *) 26 | wire [4*`INSN_LEN-1:0] idata; 27 | + (* keep *) 28 | wire [8:0] imem_addr; 29 | + (* keep *) 30 | wire [`DATA_LEN-1:0] dmem_data; 31 | + (* keep *) 32 | wire [`DATA_LEN-1:0] dmem_wdata; 33 | + (* keep *) 34 | wire [`ADDR_LEN-1:0] dmem_addr; 35 | + (* keep *) 36 | wire dmem_we; 37 | + (* keep *) 38 | wire [`DATA_LEN-1:0] dmem_wdata_core; 39 | + (* keep *) 40 | wire [`ADDR_LEN-1:0] dmem_addr_core; 41 | + (* keep *) 42 | wire dmem_we_core; 43 | 44 | wire utx_we; 45 | -------------------------------------------------------------------------------- /ridecore-src-buggy/alu.v: -------------------------------------------------------------------------------- 1 | `include "alu_ops.vh" 2 | `include "rv32_opcodes.vh" 3 | 4 | `default_nettype none 5 | 6 | module alu( 7 | input wire [`ALU_OP_WIDTH-1:0] op, 8 | input wire [`XPR_LEN-1:0] in1, 9 | input wire [`XPR_LEN-1:0] in2, 10 | output reg [`XPR_LEN-1:0] out 11 | ); 12 | 13 | wire [`SHAMT_WIDTH-1:0] shamt; 14 | 15 | assign shamt = in2[`SHAMT_WIDTH-1:0]; 16 | 17 | always @(*) begin 18 | case (op) 19 | `ALU_OP_ADD : out = in1 + in2; 20 | `ALU_OP_SLL : out = in1 << shamt; 21 | `ALU_OP_XOR : out = in1 ^ in2; 22 | `ALU_OP_OR : out = in1 | in2; 23 | `ALU_OP_AND : out = in1 & in2; 24 | `ALU_OP_SRL : out = in1 >> shamt; 25 | `ALU_OP_SEQ : out = {31'b0, in1 == in2}; 26 | `ALU_OP_SNE : out = {31'b0, in1 != in2}; 27 | `ALU_OP_SUB : out = in1 - in2; 28 | `ALU_OP_SRA : out = $signed(in1) >>> shamt; 29 | `ALU_OP_SLT : out = {31'b0, $signed(in1) < $signed(in2)}; 30 | `ALU_OP_SGE : out = {31'b0, $signed(in1) >= $signed(in2)}; 31 | `ALU_OP_SLTU : out = {31'b0, in1 < in2}; 32 | `ALU_OP_SGEU : out = {31'b0, in1 >= in2}; 33 | default : out = 0; 34 | endcase // case op 35 | end 36 | 37 | 38 | endmodule // alu 39 | 40 | `default_nettype wire 41 | -------------------------------------------------------------------------------- /ridecore-src-buggy/exunit_mul.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module exunit_mul 4 | ( 5 | input wire clk, 6 | input wire reset, 7 | input wire [`DATA_LEN-1:0] ex_src1, 8 | input wire [`DATA_LEN-1:0] ex_src2, 9 | input wire dstval, 10 | input wire [`SPECTAG_LEN-1:0] spectag, 11 | input wire specbit, 12 | input wire src1_signed, 13 | input wire src2_signed, 14 | input wire sel_lohi, 15 | input wire issue, 16 | input wire prmiss, 17 | input wire [`SPECTAG_LEN-1:0] spectagfix, 18 | output wire [`DATA_LEN-1:0] result, 19 | output wire rrf_we, 20 | output wire rob_we, //set finish 21 | output wire kill_speculative 22 | ); 23 | 24 | reg busy; 25 | 26 | assign rob_we = busy; 27 | assign rrf_we = busy & dstval; 28 | assign kill_speculative = ((spectag & spectagfix) != 0) && specbit && prmiss; 29 | 30 | always @ (posedge clk) begin 31 | if (reset) begin 32 | busy <= 0; 33 | end else begin 34 | busy <= issue; 35 | end 36 | end 37 | 38 | multiplier bob 39 | ( 40 | .src1(ex_src1), 41 | .src2(ex_src2), 42 | .src1_signed(src1_signed), 43 | .src2_signed(src2_signed), 44 | .sel_lohi(sel_lohi), 45 | .result(result) 46 | ); 47 | 48 | endmodule // exunit_mul 49 | 50 | 51 | `default_nettype wire 52 | -------------------------------------------------------------------------------- /ridecore-bugfix-patch/ridecore-bugfix-rs_mul.patch-BACKUP: -------------------------------------------------------------------------------- 1 | *** ridecore-src-buggy/rs_mul.v 2019-05-22 11:44:10.971859570 -0700 2 | --- /home/florian/git/github/ride-core-demo/ride-src/rs_mul.v 2019-05-22 16:05:50.514559631 -0700 3 | *************** 4 | *** 346,354 **** 5 | .wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2), 6 | .wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2), 7 | .wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2), 8 | ! .wsrc1_signed((we1 && (waddr1 == 0)) ? wsrc1_signed_1 : wsrc1_signed_2), 9 | ! .wsrc2_signed((we1 && (waddr1 == 0)) ? wsrc2_signed_1 : wsrc2_signed_2), 10 | ! .wsel_lohi((we1 && (waddr1 == 0)) ? wsel_lohi_1 : wsel_lohi_2), 11 | .we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))), 12 | .ex_src1(ex_src1_1), 13 | .ex_src2(ex_src2_1), 14 | --- 346,354 ---- 15 | .wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2), 16 | .wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2), 17 | .wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2), 18 | ! .wsrc1_signed((we1 && (waddr1 == 1)) ? wsrc1_signed_1 : wsrc1_signed_2), 19 | ! .wsrc2_signed((we1 && (waddr1 == 1)) ? wsrc2_signed_1 : wsrc2_signed_2), 20 | ! .wsel_lohi((we1 && (waddr1 == 1)) ? wsel_lohi_1 : wsel_lohi_2), 21 | .we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))), 22 | .ex_src1(ex_src1_1), 23 | .ex_src2(ex_src2_1), 24 | -------------------------------------------------------------------------------- /qed-wireup-patches/step0-pipeline_if-changes-optimization.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 63,75 **** 3 | .invalid2(invalid2) 4 | ); 5 | 6 | gshare_predictor gsh 7 | ( 8 | .clk(clk), 9 | .reset(reset), 10 | .pc(pc), 11 | .hit_bht(hit), 12 | ! .predict_cond(predict_cond), 13 | .we(btbpht_we), 14 | .wcond(pht_wcond), 15 | .went(btbpht_pc[2+:`GSH_BHR_LEN] ^ pht_bhr), 16 | --- 63,80 ---- 17 | .invalid2(invalid2) 18 | ); 19 | 20 | + // EDIT: manually cut predict_cond and bhr and assign it to 0 21 | + assign predict_cond = 1'b0; 22 | + assign bhr = 1'b0; 23 | + wire cut_predict_cond; 24 | + wire cut_bhr; 25 | gshare_predictor gsh 26 | ( 27 | .clk(clk), 28 | .reset(reset), 29 | .pc(pc), 30 | .hit_bht(hit), 31 | ! .predict_cond(cut_predict_cond), 32 | .we(btbpht_we), 33 | .wcond(pht_wcond), 34 | .went(btbpht_pc[2+:`GSH_BHR_LEN] ^ pht_bhr), 35 | *************** 36 | *** 77,83 **** 37 | .prmiss(prmiss), 38 | .prsuccess(prsuccess), 39 | .prtag(prtag), 40 | ! .bhr_master(bhr), 41 | .spectagnow(spectagnow) 42 | ); 43 | 44 | --- 82,88 ---- 45 | .prmiss(prmiss), 46 | .prsuccess(prsuccess), 47 | .prtag(prtag), 48 | ! .bhr_master(cut_bhr), 49 | .spectagnow(spectagnow) 50 | ); 51 | 52 | -------------------------------------------------------------------------------- /ridecore-src-buggy/src_manager.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module src_manager 4 | ( 5 | input wire [`DATA_LEN-1:0] opr, 6 | input wire opr_rdy, 7 | input wire [`DATA_LEN-1:0] exrslt1, 8 | input wire [`RRF_SEL-1:0] exdst1, 9 | input wire kill_spec1, 10 | input wire [`DATA_LEN-1:0] exrslt2, 11 | input wire [`RRF_SEL-1:0] exdst2, 12 | input wire kill_spec2, 13 | input wire [`DATA_LEN-1:0] exrslt3, 14 | input wire [`RRF_SEL-1:0] exdst3, 15 | input wire kill_spec3, 16 | input wire [`DATA_LEN-1:0] exrslt4, 17 | input wire [`RRF_SEL-1:0] exdst4, 18 | input wire kill_spec4, 19 | input wire [`DATA_LEN-1:0] exrslt5, 20 | input wire [`RRF_SEL-1:0] exdst5, 21 | input wire kill_spec5, 22 | output wire [`DATA_LEN-1:0] src, 23 | output wire resolved 24 | ); 25 | 26 | assign src = opr_rdy ? opr : 27 | ~kill_spec1 & (exdst1 == opr) ? exrslt1 : 28 | ~kill_spec2 & (exdst2 == opr) ? exrslt2 : 29 | ~kill_spec3 & (exdst3 == opr) ? exrslt3 : 30 | ~kill_spec4 & (exdst4 == opr) ? exrslt4 : 31 | ~kill_spec5 & (exdst5 == opr) ? exrslt5 : opr; 32 | 33 | assign resolved = opr_rdy | 34 | (~kill_spec1 & (exdst1 == opr)) | 35 | (~kill_spec2 & (exdst2 == opr)) | 36 | (~kill_spec3 & (exdst3 == opr)) | 37 | (~kill_spec4 & (exdst4 == opr)) | 38 | (~kill_spec5 & (exdst5 == opr)); 39 | 40 | endmodule // src_manager 41 | 42 | 43 | `default_nettype wire 44 | -------------------------------------------------------------------------------- /ridecore-src-buggy/rs_reqgen.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module rs_requestgenerator 4 | ( 5 | input wire [`RS_ENT_SEL-1:0] rsent_1, 6 | input wire [`RS_ENT_SEL-1:0] rsent_2, 7 | output wire req1_alu, 8 | output wire req2_alu, 9 | output wire [1:0] req_alunum, 10 | output wire req1_branch, 11 | output wire req2_branch, 12 | output wire [1:0] req_branchnum, 13 | output wire req1_mul, 14 | output wire req2_mul, 15 | output wire [1:0] req_mulnum, 16 | output wire req1_ldst, 17 | output wire req2_ldst, 18 | output wire [1:0] req_ldstnum 19 | ); 20 | 21 | assign req1_alu = (rsent_1 == `RS_ENT_ALU) ? 1'b1 : 1'b0; 22 | assign req2_alu = (rsent_2 == `RS_ENT_ALU) ? 1'b1 : 1'b0; 23 | assign req_alunum = {1'b0, req1_alu} + {1'b0, req2_alu}; 24 | 25 | assign req1_branch = (rsent_1 == `RS_ENT_BRANCH) ? 1'b1 : 1'b0; 26 | assign req2_branch = (rsent_2 == `RS_ENT_BRANCH) ? 1'b1 : 1'b0; 27 | assign req_branchnum = {1'b0, req1_branch} + {1'b0, req2_branch}; 28 | 29 | assign req1_mul = (rsent_1 == `RS_ENT_MUL) ? 1'b1 : 1'b0; 30 | assign req2_mul = (rsent_2 == `RS_ENT_MUL) ? 1'b1 : 1'b0; 31 | assign req_mulnum = {1'b0, req1_mul} + {1'b0, req2_mul}; 32 | 33 | assign req1_ldst = (rsent_1 == `RS_ENT_LDST) ? 1'b1 : 1'b0; 34 | assign req2_ldst = (rsent_2 == `RS_ENT_LDST) ? 1'b1 : 1'b0; 35 | assign req_ldstnum = {1'b0, req1_ldst} + {1'b0, req2_ldst}; 36 | 37 | endmodule // rs_requestgenerator 38 | `default_nettype wire 39 | -------------------------------------------------------------------------------- /BSD_LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2018-2019, Stanford University 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | * Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | * Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | * Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /ridecore-src-buggy/btb.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module btb( 4 | input wire clk, 5 | input wire reset, 6 | input wire [`ADDR_LEN-1:0] pc, 7 | output wire hit, 8 | output wire [`ADDR_LEN-1:0] jmpaddr, 9 | input wire we, 10 | input wire [`ADDR_LEN-1:0] jmpsrc, 11 | input wire [`ADDR_LEN-1:0] jmpdst, 12 | input wire invalid2 13 | ); 14 | 15 | wire [`ADDR_LEN-1:0] tag_data; 16 | reg [`BTB_IDX_NUM-1:0] valid; 17 | wire [`BTB_IDX_SEL-1:0] waddr = jmpsrc[3+:`BTB_IDX_SEL]; 18 | wire [`ADDR_LEN-1:0] pc2 = pc+4; 19 | 20 | wire hit1 = ((tag_data == pc) && valid[pc[3+:`BTB_IDX_SEL]]) ? 21 | 1'b1 : 1'b0; 22 | wire hit2 = ((tag_data == pc2) && ~invalid2 23 | && valid[pc[3+:`BTB_IDX_SEL]]) ? 1'b1 : 1'b0; 24 | assign hit = hit1 | hit2; 25 | 26 | always @ (negedge clk) begin 27 | if (reset) begin 28 | valid <= 0; 29 | end else begin 30 | if (we) begin 31 | valid[waddr] <= 1'b1; 32 | end 33 | end 34 | end 35 | 36 | ram_sync_1r1w #(`BTB_IDX_SEL, `ADDR_LEN, `BTB_IDX_NUM) bia 37 | ( 38 | .clk(~clk), 39 | .raddr1(pc[3+:`BTB_IDX_SEL]), 40 | .rdata1(tag_data), 41 | .waddr(waddr), 42 | // .wdata(jmpsrc[31:3+`BTB_IDX_SEL]), 43 | .wdata(jmpsrc), 44 | .we(we) 45 | ); 46 | 47 | ram_sync_1r1w #(`BTB_IDX_SEL, `ADDR_LEN, `BTB_IDX_NUM) bta 48 | ( 49 | .clk(~clk), 50 | .raddr1(pc[3+:`BTB_IDX_SEL]), 51 | .rdata1(jmpaddr), 52 | .waddr(waddr), 53 | .wdata(jmpdst), 54 | .we(we) 55 | ); 56 | 57 | endmodule // btb 58 | `default_nettype wire 59 | -------------------------------------------------------------------------------- /ridecore-src-buggy/tag_generator.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module tag_generator( 4 | input wire clk, 5 | input wire reset, 6 | input wire branchvalid1, 7 | input wire branchvalid2, 8 | input wire prmiss, 9 | input wire prsuccess, 10 | input wire enable, 11 | input wire [`SPECTAG_LEN-1:0] tagregfix, 12 | output wire [`SPECTAG_LEN-1:0] sptag1, 13 | output wire [`SPECTAG_LEN-1:0] sptag2, 14 | output wire speculative1, 15 | output wire speculative2, 16 | output wire attachable, 17 | output reg [`SPECTAG_LEN-1:0] tagreg 18 | ); 19 | 20 | // reg [`SPECTAG_LEN-1:0] tagreg; 21 | reg [`BRDEPTH_LEN-1:0] brdepth; 22 | 23 | assign sptag1 = (branchvalid1) ? 24 | {tagreg[`SPECTAG_LEN-2:0], tagreg[`SPECTAG_LEN-1]} 25 | : tagreg; 26 | assign sptag2 = (branchvalid2) ? 27 | {sptag1[`SPECTAG_LEN-2:0], sptag1[`SPECTAG_LEN-1]} 28 | : sptag1; 29 | assign speculative1 = (brdepth != 0) ? 1'b1 : 1'b0; 30 | assign speculative2 = ((brdepth != 0) || branchvalid1) ? 1'b1 : 1'b0; 31 | assign attachable = (brdepth + branchvalid1 + branchvalid2) 32 | > (`BRANCH_ENT_NUM + prsuccess) ? 1'b0 : 1'b1; 33 | 34 | always @ (posedge clk) begin 35 | if (reset) begin 36 | tagreg <= `SPECTAG_LEN'b1; 37 | brdepth <= `BRDEPTH_LEN'b0; 38 | end else begin 39 | tagreg <= prmiss ? tagregfix : 40 | ~enable ? tagreg : 41 | sptag2; 42 | brdepth <= prmiss ? `BRDEPTH_LEN'b0 : 43 | ~enable ? brdepth - prsuccess : 44 | brdepth + branchvalid1 + branchvalid2 - prsuccess; 45 | end 46 | end 47 | 48 | endmodule // tag_generator 49 | `default_nettype wire 50 | -------------------------------------------------------------------------------- /ridecore-src-buggy/main.xdc: -------------------------------------------------------------------------------- 1 | # UART 2 | set_property PACKAGE_PIN AU36 [get_ports TXD] 3 | set_property IOSTANDARD LVCMOS18 [get_ports TXD] 4 | set_property PACKAGE_PIN AU33 [get_ports RXD] 5 | set_property IOSTANDARD LVCMOS18 [get_ports RXD] 6 | 7 | # LED 8 | set_property PACKAGE_PIN AM39 [get_ports LED[0]] 9 | set_property IOSTANDARD LVCMOS18 [get_ports LED[0]] 10 | set_property PACKAGE_PIN AN39 [get_ports LED[1]] 11 | set_property IOSTANDARD LVCMOS18 [get_ports LED[1]] 12 | set_property PACKAGE_PIN AR37 [get_ports LED[2]] 13 | set_property IOSTANDARD LVCMOS18 [get_ports LED[2]] 14 | set_property PACKAGE_PIN AT37 [get_ports LED[3]] 15 | set_property IOSTANDARD LVCMOS18 [get_ports LED[3]] 16 | set_property PACKAGE_PIN AR35 [get_ports LED[4]] 17 | set_property IOSTANDARD LVCMOS18 [get_ports LED[4]] 18 | set_property PACKAGE_PIN AP41 [get_ports LED[5]] 19 | set_property IOSTANDARD LVCMOS18 [get_ports LED[5]] 20 | set_property PACKAGE_PIN AP42 [get_ports LED[6]] 21 | set_property IOSTANDARD LVCMOS18 [get_ports LED[6]] 22 | set_property PACKAGE_PIN AU39 [get_ports LED[7]] 23 | set_property IOSTANDARD LVCMOS18 [get_ports LED[7]] 24 | 25 | # CLK 26 | # PadFunction: IO_L12P_T1_MRCC_38 27 | set_property VCCAUX_IO DONTCARE [get_ports {CLK_P}] 28 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK_P}] 29 | set_property PACKAGE_PIN E19 [get_ports {CLK_P}] 30 | 31 | # PadFunction: IO_L12N_T1_MRCC_38 32 | set_property VCCAUX_IO DONTCARE [get_ports {CLK_N}] 33 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK_N}] 34 | set_property PACKAGE_PIN E18 [get_ports {CLK_N}] 35 | 36 | # PadFunction: IO_L13N_T2_MRCC_15 37 | set_property VCCAUX_IO DONTCARE [get_ports {RST_X_IN}] 38 | set_property IOSTANDARD LVCMOS18 [get_ports {RST_X_IN}] 39 | set_property PACKAGE_PIN AW40 [get_ports {RST_X_IN}] 40 | -------------------------------------------------------------------------------- /ridecore-src-buggy/rrf_freelistmanager.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module rrf_freelistmanager 4 | ( 5 | input wire clk, 6 | input wire reset, 7 | input wire invalid1, 8 | input wire invalid2, 9 | input wire [1:0] comnum, 10 | input wire prmiss, 11 | input wire [`RRF_SEL-1:0] rrftagfix, 12 | output wire [`RRF_SEL-1:0] rename_dst1, 13 | output wire [`RRF_SEL-1:0] rename_dst2, 14 | output wire allocatable, 15 | input wire stall_DP, //= ~allocatable && ~prmiss 16 | output reg [`RRF_SEL:0] freenum, 17 | output reg [`RRF_SEL-1:0] rrfptr, 18 | input wire [`RRF_SEL-1:0] comptr, 19 | output reg nextrrfcyc 20 | ); 21 | 22 | wire [1:0] reqnum = {1'b0, ~invalid1} + {1'b0, ~invalid2}; 23 | wire hi = (comptr > rrftagfix) ? 1'b1 : 1'b0; 24 | wire [`RRF_SEL-1:0] rrfptr_next = rrfptr + reqnum; 25 | 26 | assign allocatable = (freenum + comnum) < reqnum ? 1'b0 : 1'b1; 27 | assign rename_dst1 = rrfptr; 28 | assign rename_dst2 = rrfptr + (~invalid1 ? 1 : 0); 29 | 30 | always @ (posedge clk) begin 31 | if (reset) begin 32 | freenum <= `RRF_NUM; 33 | rrfptr <= 0; 34 | nextrrfcyc <= 0; 35 | end else if (prmiss) begin 36 | rrfptr <= rrftagfix; //== prmiss_rrftag+1 37 | freenum <= `RRF_NUM - ({hi, rrftagfix} - {1'b0, comptr}); 38 | nextrrfcyc <= 0; 39 | end else if (stall_DP) begin 40 | rrfptr <= rrfptr; 41 | freenum <= freenum + comnum; 42 | nextrrfcyc <= 0; 43 | end else begin 44 | rrfptr <= rrfptr_next; 45 | freenum <= freenum + comnum - reqnum; 46 | nextrrfcyc <= (rrfptr > rrfptr_next) ? 1'b1 : 1'b0; 47 | end 48 | end 49 | endmodule // rrf_freelistmanager 50 | 51 | 52 | `default_nettype wire 53 | -------------------------------------------------------------------------------- /ridecore-src-buggy/multiplier.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `include "rv32_opcodes.vh" 3 | `include "alu_ops.vh" 4 | `default_nettype none 5 | module mux_4x1( 6 | input wire [1:0] sel, 7 | input wire [2*`DATA_LEN-1:0] dat0, 8 | input wire [2*`DATA_LEN-1:0] dat1, 9 | input wire [2*`DATA_LEN-1:0] dat2, 10 | input wire [2*`DATA_LEN-1:0] dat3, 11 | output reg [2*`DATA_LEN-1:0] out 12 | ); 13 | always @(*) begin 14 | case(sel) 15 | 0: begin 16 | out = dat0; 17 | end 18 | 1: begin 19 | out = dat1; 20 | end 21 | 2: begin 22 | out = dat2; 23 | end 24 | 3: begin 25 | out = dat3; 26 | end 27 | endcase 28 | end 29 | endmodule // mux_4x1 30 | 31 | // sel_lohi = md_req_out_sel[0] 32 | module multiplier( 33 | input wire signed [`DATA_LEN-1:0] src1, 34 | input wire signed [`DATA_LEN-1:0] src2, 35 | input wire src1_signed, 36 | input wire src2_signed, 37 | input wire sel_lohi, 38 | output wire [`DATA_LEN-1:0] result 39 | ); 40 | 41 | wire signed [`DATA_LEN:0] src1_unsign = {1'b0, src1}; 42 | wire signed [`DATA_LEN:0] src2_unsign = {1'b0, src2}; 43 | 44 | wire signed [2*`DATA_LEN-1:0] res_ss = src1 * src2; 45 | wire signed [2*`DATA_LEN-1:0] res_su = src1 * src2_unsign; 46 | wire signed [2*`DATA_LEN-1:0] res_us = src1_unsign * src2; 47 | wire signed [2*`DATA_LEN-1:0] res_uu = src1_unsign * src2_unsign; 48 | 49 | wire [2*`DATA_LEN-1:0] res; 50 | 51 | mux_4x1 mxres( 52 | .sel({src1_signed, src2_signed}), 53 | .dat0(res_uu), 54 | .dat1(res_us), 55 | .dat2(res_su), 56 | .dat3(res_ss), 57 | .out(res) 58 | ); 59 | 60 | assign result = sel_lohi ? res[`DATA_LEN+:`DATA_LEN] : res[`DATA_LEN-1:0]; 61 | 62 | endmodule // multiplier 63 | 64 | 65 | `default_nettype wire 66 | -------------------------------------------------------------------------------- /ridecore-src-buggy/exunit_alu.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `include "alu_ops.vh" 3 | `default_nettype none 4 | module exunit_alu 5 | ( 6 | input wire clk, 7 | input wire reset, 8 | input wire [`DATA_LEN-1:0] ex_src1, 9 | input wire [`DATA_LEN-1:0] ex_src2, 10 | input wire [`ADDR_LEN-1:0] pc, 11 | input wire [`DATA_LEN-1:0] imm, 12 | input wire dstval, 13 | input wire [`SRC_A_SEL_WIDTH-1:0] src_a, 14 | input wire [`SRC_B_SEL_WIDTH-1:0] src_b, 15 | input wire [`ALU_OP_WIDTH-1:0] alu_op, 16 | input wire [`SPECTAG_LEN-1:0] spectag, 17 | input wire specbit, 18 | input wire issue, 19 | input wire prmiss, 20 | input wire [`SPECTAG_LEN-1:0] spectagfix, 21 | output wire [`DATA_LEN-1:0] result, 22 | output wire rrf_we, 23 | output wire rob_we, //set finish 24 | output wire kill_speculative 25 | ); 26 | 27 | wire [`DATA_LEN-1:0] alusrc1; 28 | wire [`DATA_LEN-1:0] alusrc2; 29 | 30 | reg busy; 31 | 32 | assign rob_we = busy; 33 | assign rrf_we = busy & dstval; 34 | assign kill_speculative = ((spectag & spectagfix) != 0) && specbit && prmiss; 35 | 36 | always @ (posedge clk) begin 37 | if (reset) begin 38 | busy <= 0; 39 | end else begin 40 | busy <= issue; 41 | end 42 | end 43 | 44 | src_a_mux samx 45 | ( 46 | .src_a_sel(src_a), 47 | .pc(pc), 48 | .rs1(ex_src1), 49 | .alu_src_a(alusrc1) 50 | ); 51 | 52 | src_b_mux sbmx 53 | ( 54 | .src_b_sel(src_b), 55 | .imm(imm), 56 | .rs2(ex_src2), 57 | .alu_src_b(alusrc2) 58 | ); 59 | 60 | alu alice 61 | ( 62 | .op(alu_op), 63 | .in1(alusrc1), 64 | .in2(alusrc2), 65 | .out(result) 66 | ); 67 | endmodule // exunit_alu 68 | `default_nettype wire 69 | 70 | -------------------------------------------------------------------------------- /SQED-Generator/QEDFiles/qed_i_cache.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) Stanford University 2 | // 3 | // This source code is patent protected and being made available under the 4 | // terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | module qed_i_cache ( 7 | // Outputs 8 | qic_qimux_instruction, 9 | vld_out, 10 | // Inputs 11 | clk, 12 | rst, 13 | exec_dup, 14 | IF_stall, 15 | ifu_qed_instruction 16 | ); 17 | 18 | parameter ICACHESIZE = 256; 19 | 20 | input clk; 21 | input rst; 22 | input exec_dup; 23 | input IF_stall; 24 | input [31:0] ifu_qed_instruction; 25 | 26 | output vld_out; 27 | output [31:0] qic_qimux_instruction; 28 | 29 | reg [31:0] i_cache[ICACHESIZE-1:0]; 30 | reg [6:0] address_tail; 31 | reg [6:0] address_head; 32 | 33 | wire is_empty; 34 | wire is_full; 35 | wire is_nop; 36 | wire insert_cond ; 37 | wire delete_cond; 38 | wire [31:0] instruction; 39 | 40 | assign insert_cond = (~rst) & (~exec_dup) & (~is_nop) & (~IF_stall) & (~is_full); 41 | assign delete_cond = (~rst) & (exec_dup) & (~is_empty) & (~IF_stall); 42 | assign is_nop = (ifu_qed_instruction[6:0] == 7'b1111111); 43 | assign is_empty = (address_tail == address_head); 44 | assign is_full = ((address_tail + 1) == address_head); 45 | assign vld_out = (~insert_cond & ~delete_cond) ? 1'b0 : 1'b1; 46 | 47 | always @(posedge clk) begin 48 | if (rst) begin 49 | address_tail <= 7'b0; 50 | address_head <= 7'b0; 51 | end 52 | else if (insert_cond) begin 53 | i_cache[address_tail] <= ifu_qed_instruction; 54 | address_tail <= address_tail + 1; 55 | end 56 | else if (delete_cond) begin 57 | address_head <= address_head + 1; 58 | end 59 | end 60 | 61 | assign instruction = i_cache[address_head]; 62 | assign qic_qimux_instruction = insert_cond ? ifu_qed_instruction : (delete_cond ? instruction : 32'b1111111); 63 | 64 | endmodule 65 | 66 | 67 | 68 | 69 | 70 | -------------------------------------------------------------------------------- /ridecore-src-buggy/prioenc.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module prioenc #( 3 | parameter REQ_LEN = 4, 4 | parameter GRANT_LEN = 2 5 | ) 6 | ( 7 | input wire [REQ_LEN-1:0] in, 8 | output reg [GRANT_LEN-1:0] out, 9 | output reg en 10 | ); 11 | 12 | integer i; 13 | always @ (*) begin 14 | en = 0; 15 | out = 0; 16 | for (i = REQ_LEN-1 ; i >= 0 ; i = i - 1) begin 17 | if (~in[i]) begin 18 | out = i; 19 | en = 1; 20 | end 21 | end 22 | end 23 | endmodule 24 | 25 | module maskunit #( 26 | parameter REQ_LEN = 4, 27 | parameter GRANT_LEN = 2 28 | ) 29 | ( 30 | input wire [GRANT_LEN-1:0] mask, 31 | input wire [REQ_LEN-1:0] in, 32 | output reg [REQ_LEN-1:0] out 33 | ); 34 | 35 | integer i; 36 | always @ (*) begin 37 | out = 0; 38 | for (i = 0 ; i < REQ_LEN ; i = i+1) begin 39 | out[i] = (mask < i) ? 1'b0 : 1'b1; 40 | end 41 | end 42 | endmodule 43 | 44 | module allocateunit #( 45 | parameter REQ_LEN = 4, 46 | parameter GRANT_LEN = 2 47 | ) 48 | ( 49 | input wire [REQ_LEN-1:0] busy, 50 | output wire en1, 51 | output wire en2, 52 | output wire [GRANT_LEN-1:0] free_ent1, 53 | output wire [GRANT_LEN-1:0] free_ent2, 54 | input wire [1:0] reqnum, 55 | output wire allocatable 56 | ); 57 | 58 | wire [REQ_LEN-1:0] busy_msk; 59 | 60 | prioenc #(REQ_LEN, GRANT_LEN) p1 61 | ( 62 | .in(busy), 63 | .out(free_ent1), 64 | .en(en1) 65 | ); 66 | 67 | maskunit #(REQ_LEN, GRANT_LEN) msku 68 | ( 69 | .mask(free_ent1), 70 | .in(busy), 71 | .out(busy_msk) 72 | ); 73 | 74 | prioenc #(REQ_LEN, GRANT_LEN) p2 75 | ( 76 | .in(busy | busy_msk), 77 | .out(free_ent2), 78 | .en(en2) 79 | ); 80 | 81 | assign allocatable = (reqnum > ({1'b0,en1}+{1'b0,en2})) ? 1'b0 : 1'b1; 82 | endmodule 83 | `default_nettype wire 84 | -------------------------------------------------------------------------------- /ridecore-src-buggy/exunit_branch.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `include "alu_ops.vh" 3 | `include "rv32_opcodes.vh" 4 | `default_nettype none 5 | module exunit_branch 6 | ( 7 | input wire clk, 8 | input wire reset, 9 | input wire [`DATA_LEN-1:0] ex_src1, 10 | input wire [`DATA_LEN-1:0] ex_src2, 11 | input wire [`ADDR_LEN-1:0] pc, 12 | input wire [`DATA_LEN-1:0] imm, 13 | input wire dstval, 14 | input wire [`ALU_OP_WIDTH-1:0] alu_op, 15 | input wire [`SPECTAG_LEN-1:0] spectag, 16 | input wire specbit, 17 | input wire [`ADDR_LEN-1:0] praddr, 18 | input wire [6:0] opcode, 19 | input wire issue, 20 | output wire [`DATA_LEN-1:0] result, 21 | output wire rrf_we, 22 | output wire rob_we, //set finish 23 | output wire prsuccess, 24 | output wire prmiss, 25 | output wire [`ADDR_LEN-1:0] jmpaddr, 26 | output wire [`ADDR_LEN-1:0] jmpaddr_taken, 27 | output wire brcond, 28 | output wire [`SPECTAG_LEN-1:0] tagregfix 29 | ); 30 | 31 | reg busy; 32 | 33 | wire [`DATA_LEN-1:0] comprslt; 34 | wire addrmatch = (jmpaddr == praddr) ? 1'b1 : 1'b0; 35 | 36 | 37 | assign rob_we = busy; 38 | assign rrf_we = busy & dstval; 39 | assign result = pc + 4; 40 | assign prsuccess = busy & addrmatch; 41 | assign prmiss = busy & ~addrmatch; 42 | assign jmpaddr = brcond ? jmpaddr_taken : (pc + 4); 43 | assign jmpaddr_taken = (((opcode == `RV32_JALR) ? ex_src1 : pc) + imm); 44 | 45 | assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ? 46 | 1'b1 : comprslt[0]; 47 | assign tagregfix = {spectag[0], spectag[`SPECTAG_LEN-1:1]}; 48 | 49 | always @ (posedge clk) begin 50 | if (reset) begin 51 | busy <= 0; 52 | end else begin 53 | busy <= issue; 54 | end 55 | end 56 | 57 | alu comparator 58 | ( 59 | .op(alu_op), 60 | .in1(ex_src1), 61 | .in2(ex_src2), 62 | .out(comprslt) 63 | ); 64 | 65 | endmodule // exunit_branch 66 | 67 | `default_nettype wire 68 | -------------------------------------------------------------------------------- /ridecore-src-buggy/dualport_ram.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module true_dualport_ram #( 4 | parameter ADDRLEN = 10, 5 | parameter DATALEN = 2, 6 | parameter DEPTH = 1024 7 | ) 8 | ( 9 | input wire clka, 10 | input wire [ADDRLEN-1:0] addra, 11 | output reg [DATALEN-1:0] rdataa, 12 | input wire [DATALEN-1:0] wdataa, 13 | input wire wea, 14 | input wire clkb, 15 | input wire [ADDRLEN-1:0] addrb, 16 | output reg [DATALEN-1:0] rdatab, 17 | input wire [DATALEN-1:0] wdatab, 18 | input wire web 19 | ); 20 | 21 | 22 | reg [DATALEN-1:0] mem [0:DEPTH-1]; 23 | 24 | always @ (posedge clka) begin 25 | rdataa <= mem[addra]; 26 | if (wea) begin 27 | mem[addra] <= wdataa; 28 | end 29 | end 30 | 31 | always @ (posedge clkb) begin 32 | rdatab <= mem[addrb]; 33 | if (web) begin 34 | mem[addrb] <= wdatab; 35 | end 36 | end 37 | endmodule // true_dualport_ram 38 | 39 | module true_dualport_ram_clear #( 40 | parameter ADDRLEN = 10, 41 | parameter DATALEN = 2, 42 | parameter DEPTH = 1024 43 | ) 44 | ( 45 | input wire clka, 46 | input wire [ADDRLEN-1:0] addra, 47 | output reg [DATALEN-1:0] rdataa, 48 | input wire [DATALEN-1:0] wdataa, 49 | input wire wea, 50 | input wire clkb, 51 | input wire [ADDRLEN-1:0] addrb, 52 | output reg [DATALEN-1:0] rdatab, 53 | input wire [DATALEN-1:0] wdatab, 54 | input wire web, 55 | input wire clear 56 | ); 57 | 58 | reg [DATALEN-1:0] mem [0:DEPTH-1]; 59 | integer i; 60 | 61 | always @ (*) begin 62 | if (clear) begin 63 | for (i=0; i 100 MHz, Nexys4 -> 100 MHz, Virtex7 -> 200 MHz 11 | 12 | `define DCM_CLKIN_PERIOD 5.000 // Atlys -> 10.000 ns 13 | `define DCM_CLKFX_MULTIPLY 3 // CLKFX_MULTIPLY must be 2~32 14 | `define DCM_CLKFX_DIVIDE 25 // CLKFX_DIVIDE must be 1~32 15 | 16 | `define MMCM_CLKIN1_PERIOD 5.000 // Nexys4 -> 10.000 ns, Virtex7 -> 5.000 ns 17 | `define MMCM_VCO_MULTIPLY 8 // for VCO, 800-1600 18 | `define MMCM_VCO_DIVIDE 2 19 | `define MMCM_CLKOUT0_DIVIDE 16 // for user clock, 50 MHz 20 | `define MMCM_CLKOUT1_DIVIDE 4 // for dram clock, 200 MHz 21 | 22 | 23 | /* UART Definition */ 24 | /**************************************************************************************************/ 25 | `define SERIAL_WCNT 'd50 // 24MHz/1.5Mbaud, parameter for UartRx and UartTx 26 | `define APP_SIZE 8*1024 // application program load size in byte (64*16=1024KB) 27 | `define SCD_SIZE 64*1024 // scheduling program load size in byte (64* 1= 64KB) 28 | `define IMG_SIZE 1088*1024 // full image file load size in byte (64*17=1088KB) 29 | 30 | 31 | /**************************************************************************************************/ 32 | //`default_nettype wire 33 | /**************************************************************************************************/ 34 | -------------------------------------------------------------------------------- /wire-up-qed-module.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Update the topsim module to wire up the QED module 4 | 5 | # Add "(* keep *)" pragmas to preserve certain wires for model checking 6 | patch -i ./qed-wireup-patches/step0-topsim-changes.patch ./ridecore-src-buggy/topsim.v 7 | 8 | # Make the instruction signal a top-level input to be selected by the 9 | # model checker 10 | patch -i ./qed-wireup-patches/step1-topsim-changes.patch ./ridecore-src-buggy/topsim.v 11 | 12 | # Instantiate the instruction-constraint module to constrain the 13 | # instruction to be a valid instruction from the ISA 14 | patch -i ./qed-wireup-patches/step2-topsim-changes.patch ./ridecore-src-buggy/topsim.v 15 | 16 | # Use assumption to embed constraint that there's no reset in the BTOR2 17 | # reset sequence will be simulated before BTOR2 generated 18 | patch -i ./qed-wireup-patches/step3-topsim-changes.patch ./ridecore-src-buggy/topsim.v 19 | 20 | # Update the pipeline module to wire up the QED module 21 | 22 | # Drive instruction signal from top-level input, instantiate the QED 23 | # module to modify instructions, send the output instruction of the 24 | # QED module through the pipeline 25 | patch -i ./qed-wireup-patches/step0-pipeline-changes.patch ./ridecore-src-buggy/pipeline.v 26 | 27 | # wire registers 1 and 17 out of regfile so we can access them 28 | # in standard Verilog (Yosys doesn't support . notation for reaching into modules) 29 | patch -i ./qed-wireup-patches/step0-ram_sync_nolatch-changes.patch ./ridecore-src-buggy/ram_sync_nolatch.v 30 | patch -i ./qed-wireup-patches/step0-arf-changes.patch ./ridecore-src-buggy/arf.v 31 | patch -i ./qed-wireup-patches/step1-pipeline-changes.patch ./ridecore-src-buggy/pipeline.v 32 | 33 | # OPTIONAL: make additional modifications to speed up model checking 34 | 35 | # Disable branch prediction 36 | 37 | patch -i ./qed-wireup-patches/step0-pipeline_if-changes-optimization.patch ./ridecore-src-buggy/pipeline_if.v 38 | 39 | # Reduce size of memory 40 | 41 | patch -i ./qed-wireup-patches/step0-dmem-changes-optimization.patch ./ridecore-src-buggy/dmem.v 42 | 43 | # Limit instruction fetch to only one instruction 44 | 45 | patch -i ./qed-wireup-patches/step2-pipeline-changes-optimization.patch ./ridecore-src-buggy/pipeline.v 46 | 47 | # Remove branch target buffer to get rid of neg-edge behavior. This 48 | # optimization allows to abstract the clock and reduce the number of 49 | # unrollings in BMC 50 | patch -i ./qed-wireup-patches/step1-pipeline_if-changes-optimization.patch ./ridecore-src-buggy/pipeline_if.v 51 | -------------------------------------------------------------------------------- /ridecore-src-buggy/alloc_issue_ino.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | 3 | //`default_nettype none 4 | 5 | module alloc_issue_ino #( 6 | parameter ENTSEL = 2, 7 | parameter ENTNUM = 4 8 | ) 9 | ( 10 | input wire clk, 11 | input wire reset, 12 | input wire [1:0] reqnum, 13 | input wire [ENTNUM-1:0] busyvec, 14 | input wire [ENTNUM-1:0] prbusyvec_next, 15 | input wire [ENTNUM-1:0] readyvec, 16 | input wire prmiss, 17 | input wire exunit_busynext, 18 | input wire stall_DP, 19 | input wire kill_DP, 20 | output reg [ENTSEL-1:0] allocptr, 21 | output wire allocatable, 22 | output wire [ENTSEL-1:0] issueptr, 23 | output wire issuevalid 24 | ); 25 | 26 | 27 | wire [ENTSEL-1:0] allocptr2 = allocptr + 1; 28 | wire [ENTSEL-1:0] b0; 29 | wire [ENTSEL-1:0] e0; 30 | wire [ENTSEL-1:0] b1; 31 | wire [ENTSEL-1:0] e1; 32 | wire notfull; 33 | 34 | wire [ENTSEL-1:0] ne1; 35 | wire [ENTSEL-1:0] nb0; 36 | wire [ENTSEL-1:0] nb1; 37 | wire notfull_next; 38 | 39 | search_begin #(ENTSEL, ENTNUM) sb1( 40 | .in(busyvec), 41 | .out(b1), 42 | .en() 43 | ); 44 | 45 | search_end #(ENTSEL, ENTNUM) se1( 46 | .in(busyvec), 47 | .out(e1), 48 | .en() 49 | ); 50 | 51 | search_end #(ENTSEL, ENTNUM) se0( 52 | .in(~busyvec), 53 | .out(e0), 54 | .en(notfull) 55 | ); 56 | 57 | search_begin #(ENTSEL, ENTNUM) snb1( 58 | .in(prbusyvec_next), 59 | .out(nb1), 60 | .en() 61 | ); 62 | 63 | search_end #(ENTSEL, ENTNUM) sne1( 64 | .in(prbusyvec_next), 65 | .out(ne1), 66 | .en() 67 | ); 68 | 69 | search_begin #(ENTSEL, ENTNUM) snb0( 70 | .in(~prbusyvec_next), 71 | .out(nb0), 72 | .en(notfull_next) 73 | ); 74 | 75 | assign issueptr = ~notfull ? allocptr : 76 | ((b1 == 0) && (e1 == ENTNUM-1)) ? (e0+1) : 77 | b1; 78 | 79 | assign issuevalid = readyvec[issueptr] & ~prmiss & ~exunit_busynext; 80 | 81 | assign allocatable = (reqnum == 2'h0) ? 1'b1 : 82 | (reqnum == 2'h1) ? ((~busyvec[allocptr] ? 1'b1 : 1'b0)) : 83 | ((~busyvec[allocptr] && ~busyvec[allocptr2]) ? 1'b1 : 1'b0); 84 | 85 | always @ (posedge clk) begin 86 | if (reset) begin 87 | allocptr <= 0; 88 | end else if (prmiss) begin 89 | allocptr <= ~notfull_next ? allocptr : 90 | (((nb1 == 0) && (ne1 == ENTNUM-1)) ? nb0 : (ne1+1)); 91 | end else if (~stall_DP && ~kill_DP) begin 92 | allocptr <= allocptr + reqnum; 93 | end 94 | end 95 | endmodule // alloc_issue_ino 96 | 97 | //`default_nettype wire 98 | -------------------------------------------------------------------------------- /ridecore-src-buggy/rv32_opcodes.vh: -------------------------------------------------------------------------------- 1 | // Width-related constants 2 | `define INST_WIDTH 32 3 | `define REG_ADDR_WIDTH 5 4 | `define XPR_LEN 32 5 | `define DOUBLE_XPR_LEN 64 6 | `define LOG2_XPR_LEN 5 7 | `define SHAMT_WIDTH 5 8 | 9 | `define RV_NOP `INST_WIDTH'b0010011 10 | 11 | // Opcodes 12 | 13 | `define RV32_LOAD 7'b0000011 14 | `define RV32_STORE 7'b0100011 15 | `define RV32_MADD 7'b1000011 16 | `define RV32_BRANCH 7'b1100011 17 | 18 | `define RV32_LOAD_FP 7'b0000111 19 | `define RV32_STORE_FP 7'b0100111 20 | `define RV32_MSUB 7'b1000111 21 | `define RV32_JALR 7'b1100111 22 | 23 | `define RV32_CUSTOM_0 7'b0001011 24 | `define RV32_CUSTOM_1 7'b0101011 25 | `define RV32_NMSUB 7'b1001011 26 | // 7'b1101011 is reserved 27 | 28 | `define RV32_MISC_MEM 7'b0001111 29 | `define RV32_AMO 7'b0101111 30 | `define RV32_NMADD 7'b1001111 31 | `define RV32_JAL 7'b1101111 32 | 33 | `define RV32_OP_IMM 7'b0010011 34 | `define RV32_OP 7'b0110011 35 | `define RV32_OP_FP 7'b1010011 36 | `define RV32_SYSTEM 7'b1110011 37 | 38 | `define RV32_AUIPC 7'b0010111 39 | `define RV32_LUI 7'b0110111 40 | // 7'b1010111 is reserved 41 | // 7'b1110111 is reserved 42 | 43 | // 7'b0011011 is RV64-specific 44 | // 7'b0111011 is RV64-specific 45 | `define RV32_CUSTOM_2 7'b1011011 46 | `define RV32_CUSTOM_3 7'b1111011 47 | 48 | // Arithmetic FUNCT3 encodings 49 | 50 | `define RV32_FUNCT3_ADD_SUB 0 51 | `define RV32_FUNCT3_SLL 1 52 | `define RV32_FUNCT3_SLT 2 53 | `define RV32_FUNCT3_SLTU 3 54 | `define RV32_FUNCT3_XOR 4 55 | `define RV32_FUNCT3_SRA_SRL 5 56 | `define RV32_FUNCT3_OR 6 57 | `define RV32_FUNCT3_AND 7 58 | 59 | // Branch FUNCT3 encodings 60 | 61 | `define RV32_FUNCT3_BEQ 0 62 | `define RV32_FUNCT3_BNE 1 63 | `define RV32_FUNCT3_BLT 4 64 | `define RV32_FUNCT3_BGE 5 65 | `define RV32_FUNCT3_BLTU 6 66 | `define RV32_FUNCT3_BGEU 7 67 | 68 | // MISC-MEM FUNCT3 encodings 69 | `define RV32_FUNCT3_FENCE 0 70 | `define RV32_FUNCT3_FENCE_I 1 71 | 72 | // SYSTEM FUNCT3 encodings 73 | 74 | `define RV32_FUNCT3_PRIV 0 75 | `define RV32_FUNCT3_CSRRW 1 76 | `define RV32_FUNCT3_CSRRS 2 77 | `define RV32_FUNCT3_CSRRC 3 78 | `define RV32_FUNCT3_CSRRWI 5 79 | `define RV32_FUNCT3_CSRRSI 6 80 | `define RV32_FUNCT3_CSRRCI 7 81 | 82 | // PRIV FUNCT12 encodings 83 | 84 | `define RV32_FUNCT12_ECALL 12'b000000000000 85 | `define RV32_FUNCT12_EBREAK 12'b000000000001 86 | `define RV32_FUNCT12_ERET 12'b000100000000 87 | 88 | // RV32M encodings 89 | `define RV32_FUNCT7_MUL_DIV 7'd1 90 | 91 | `define RV32_FUNCT3_MUL 3'd0 92 | `define RV32_FUNCT3_MULH 3'd1 93 | `define RV32_FUNCT3_MULHSU 3'd2 94 | `define RV32_FUNCT3_MULHU 3'd3 95 | `define RV32_FUNCT3_DIV 3'd4 96 | `define RV32_FUNCT3_DIVU 3'd5 97 | `define RV32_FUNCT3_REM 3'd6 98 | `define RV32_FUNCT3_REMU 3'd7 99 | -------------------------------------------------------------------------------- /bug-trace-k10-cosa-log.txt: -------------------------------------------------------------------------------- 1 | DONE 2 | Parsing file "cosa-problem-files/init.ssts"... DONE 3 | FALSE 4 | 5 | *** SUMMARY *** 6 | 7 | ** Problem QED_0 ** 8 | Description: "Check for Symbolic QED consistency" 9 | Result: FALSE 10 | Counterexample: 11 | ---> INIT <--- 12 | I: clk = 1_1 13 | I: instruction = 15759359_32 14 | I: reset_x = 1_1 15 | I: pipe.num_dup_insts = 0_16 16 | I: pipe.num_orig_insts = 0_16 17 | I: pipe.aregfile.regfile.mem[10] = 0_32 18 | I: pipe.aregfile.regfile.mem[11] = 0_32 19 | I: pipe.aregfile.regfile.mem[12] = 0_32 20 | I: pipe.aregfile.regfile.mem[13] = 0_32 21 | I: pipe.aregfile.regfile.mem[14] = 0_32 22 | I: pipe.aregfile.regfile.mem[15] = 0_32 23 | I: pipe.aregfile.regfile.mem[17] = 0_32 24 | I: pipe.aregfile.regfile.mem[18] = 0_32 25 | I: pipe.aregfile.regfile.mem[19] = 0_32 26 | I: pipe.aregfile.regfile.mem[1] = 0_32 27 | I: pipe.aregfile.regfile.mem[20] = 0_32 28 | I: pipe.aregfile.regfile.mem[21] = 0_32 29 | I: pipe.aregfile.regfile.mem[22] = 0_32 30 | I: pipe.aregfile.regfile.mem[23] = 0_32 31 | I: pipe.aregfile.regfile.mem[24] = 0_32 32 | I: pipe.aregfile.regfile.mem[25] = 0_32 33 | I: pipe.aregfile.regfile.mem[26] = 0_32 34 | I: pipe.aregfile.regfile.mem[27] = 0_32 35 | I: pipe.aregfile.regfile.mem[28] = 0_32 36 | I: pipe.aregfile.regfile.mem[29] = 0_32 37 | I: pipe.aregfile.regfile.mem[2] = 0_32 38 | I: pipe.aregfile.regfile.mem[30] = 0_32 39 | I: pipe.aregfile.regfile.mem[31] = 0_32 40 | I: pipe.aregfile.regfile.mem[3] = 0_32 41 | I: pipe.aregfile.regfile.mem[4] = 0_32 42 | I: pipe.aregfile.regfile.mem[5] = 0_32 43 | I: pipe.aregfile.regfile.mem[6] = 0_32 44 | I: pipe.aregfile.regfile.mem[7] = 0_32 45 | I: pipe.aregfile.regfile.mem[8] = 0_32 46 | I: pipe.aregfile.regfile.mem[9] = 0_32 47 | 48 | ---> STATE 1 <--- 49 | S1: instruction = 3719316115_32 50 | 51 | ---> STATE 2 <--- 52 | S2: instruction = 48414739_32 53 | 54 | ---> STATE 3 <--- 55 | S3: instruction = 38973619_32 56 | 57 | ---> STATE 4 <--- 58 | S4: instruction = 41984051_32 59 | 60 | ---> STATE 5 <--- 61 | S5: instruction = 13639715_32 62 | 63 | ---> STATE 6 <--- 64 | S6: instruction = 44927_32 65 | 66 | ---> STATE 7 <--- 67 | S7: instruction = 2147488895_32 68 | S7: pipe.num_orig_insts = 1_16 69 | S7: pipe.aregfile.regfile.mem[5] = 4294966747_32 70 | 71 | ---> STATE 8 <--- 72 | S8: instruction = 15728767_32 73 | S8: pipe.num_dup_insts = 1_16 74 | S8: pipe.aregfile.regfile.mem[21] = 4294966747_32 75 | 76 | ---> STATE 9 <--- 77 | S9: instruction = 16226227_32 78 | S9: pipe.num_orig_insts = 2_16 79 | S9: pipe.aregfile.regfile.mem[1] = 4294966198_32 80 | 81 | ---> STATE 10 <--- 82 | S10: instruction = 4294967288_32 83 | S10: pipe.num_dup_insts = 2_16 84 | S10: pipe.aregfile.regfile.mem[17] = 301401_32 85 | Counterexamples: [3], [4] 86 | Traces (max) length: 11 87 | 88 | *** TRACES *** 89 | 90 | [1]: trace[1]-QED_0.vcd 91 | -------------------------------------------------------------------------------- /ridecore-src-buggy/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2016 Arch Lab. Tokyo Institute of Technology. 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions 6 | are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 2. Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation 12 | and/or other materials provided with the distribution. 13 | 3. The name of the author may not be used to endorse or promote products 14 | derived from this software without specific prior written permission. 15 | 16 | THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 | IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 | NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 | DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 | THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | 27 | 28 | Copyright (c) 2015-2015, The Regents of the University of California 29 | (Regents). All Rights Reserved. 30 | 31 | Redistribution and use in source and binary forms, with or without 32 | modification, are permitted provided that the following conditions are met: 33 | 1. Redistributions of source code must retain the above copyright 34 | notice, this list of conditions and the following disclaimer. 35 | 2. Redistributions in binary form must reproduce the above copyright 36 | notice, this list of conditions and the following disclaimer in the 37 | documentation and/or other materials provided with the distribution. 38 | 3. Neither the name of the Regents nor the 39 | names of its contributors may be used to endorse or promote products 40 | derived from this software without specific prior written permission. 41 | 42 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 43 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 44 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 45 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 | 47 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 48 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 49 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 50 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 51 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 52 | -------------------------------------------------------------------------------- /SQED-Generator/FormatFiles/BlackParrot_format.txt: -------------------------------------------------------------------------------- 1 | # You can use python style comments with (#) 2 | # to add notes, or comment out lines. 3 | 4 | # Copyright (c) Stanford University 5 | # 6 | # This source code is patent protected and being made available under the 7 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 8 | 9 | # Author: Mario J Srouji 10 | # Email: msrouji@stanford.edu 11 | 12 | SECTIONS = ISA QEDCONSTRAINTS REGISTERS MEMORY BITFIELDS INSTYPES INSFIELDS INSREQS R I NOP 13 | 14 | _ISA 15 | num_registers = 32 16 | instruction_length = 32 17 | 18 | _QEDCONSTRAINTS 19 | half_registers = 1 20 | half_memory = 0 21 | 22 | _REGISTERS 23 | rd 24 | rs1 25 | rs2 26 | 27 | _MEMORY 28 | imm12 29 | imm7 30 | 31 | _BITFIELDS 32 | funct7 = 31 25 33 | funct3 = 14 12 34 | rd = 11 7 35 | rs1 = 19 15 36 | rs2 = 24 20 37 | opcode = 6 0 38 | shamt = 24 20 39 | imm12 = 31 20 40 | imm7 = 31 25 41 | imm5 = 11 7 42 | 43 | _INSTYPES 44 | R 45 | I 46 | NOP 47 | 48 | _INSFIELDS 49 | R = funct7 rs2 rs1 funct3 rd opcode 50 | I = imm12 rs1 funct3 rd opcode 51 | NOP = imm12 rs1 funct3 rd opcode 52 | 53 | _INSREQS 54 | R 55 | opcode = 0110011 56 | 57 | I 58 | opcode = 0010011 59 | 60 | _R 61 | ADD 62 | funct3 = 000 63 | funct7 = 0000000 64 | opcode = 0110011 65 | 66 | SUB 67 | funct3 = 000 68 | funct7 = 0100000 69 | opcode = 0110011 70 | 71 | SLL 72 | funct3 = 001 73 | funct7 = 0000000 74 | opcode = 0110011 75 | 76 | SLT 77 | funct3 = 010 78 | funct7 = 0000000 79 | opcode = 0110011 80 | 81 | SLTU 82 | funct3 = 011 83 | funct7 = 0000000 84 | opcode = 0110011 85 | 86 | XOR 87 | funct3 = 100 88 | funct7 = 0000000 89 | opcode = 0110011 90 | 91 | SRL 92 | funct3 = 101 93 | funct7 = 0000000 94 | opcode = 0110011 95 | 96 | SRA 97 | funct3 = 101 98 | funct7 = 0100000 99 | opcode = 0110011 100 | 101 | OR 102 | funct3 = 110 103 | funct7 = 0000000 104 | opcode = 0110011 105 | 106 | AND 107 | funct3 = 111 108 | funct7 = 0000000 109 | opcode = 0110011 110 | 111 | MUL 112 | funct3 = 000 113 | funct7 = 0000001 114 | opcode = 0110011 115 | 116 | MULH 117 | funct3 = 001 118 | funct7 = 0000001 119 | opcode = 0110011 120 | 121 | MULHSU 122 | funct3 = 010 123 | funct7 = 0000001 124 | opcode = 0110011 125 | 126 | MULHU 127 | funct3 = 011 128 | funct7 = 0000001 129 | opcode = 0110011 130 | 131 | _I 132 | ADDI 133 | funct3 = 000 134 | opcode = 0010011 135 | 136 | SLTI 137 | funct3 = 010 138 | opcode = 0010011 139 | 140 | SLTIU 141 | funct3 = 011 142 | opcode = 0010011 143 | 144 | XORI 145 | funct3 = 100 146 | opcode = 0010011 147 | 148 | ORI 149 | funct3 = 110 150 | opcode = 0010011 151 | 152 | ANDI 153 | funct3 = 111 154 | opcode = 0010011 155 | 156 | SLLI 157 | funct3 = 001 158 | funct7 = 0000000 159 | opcode = 0010011 160 | 161 | SRLI 162 | funct3 = 101 163 | funct7 = 0000000 164 | opcode = 0010011 165 | 166 | SRAI 167 | funct3 = 101 168 | funct7 = 0100000 169 | opcode = 0010011 170 | 171 | _NOP 172 | NOP 173 | opcode = 1111111 174 | 175 | 176 | 177 | 178 | -------------------------------------------------------------------------------- /ridecore-src-buggy/constants.vh: -------------------------------------------------------------------------------- 1 | //Register File 2 | `define REG_SEL 5 3 | //`define REG_NUM 2**`REG_SEL 4 | `define REG_NUM 32 5 | 6 | //Instruction 7 | `define IMM_TYPE_WIDTH 2 8 | `define IMM_I `IMM_TYPE_WIDTH'd0 9 | `define IMM_S `IMM_TYPE_WIDTH'd1 10 | `define IMM_U `IMM_TYPE_WIDTH'd2 11 | `define IMM_J `IMM_TYPE_WIDTH'd3 12 | 13 | //Important Wire 14 | `define DATA_LEN 32 15 | `define INSN_LEN 32 16 | `define ADDR_LEN 32 17 | `define ISSUE_NUM 2 18 | `define ENTRY_POINT `ADDR_LEN'h0 19 | //`define REQDATA_LEN 2 20 | 21 | //Decoder 22 | `define RS_ENT_SEL 3 23 | `define RS_ENT_ALU 1 24 | `define RS_ENT_BRANCH 2 25 | `define RS_ENT_JAL `RS_ENT_BRANCH 26 | `define RS_ENT_JALR `RS_ENT_BRANCH 27 | `define RS_ENT_MUL 3 28 | `define RS_ENT_DIV 3 29 | `define RS_ENT_LDST 4 30 | 31 | //RS 32 | `define ALU_ENT_SEL 3 33 | `define ALU_ENT_NUM 8 34 | `define BRANCH_ENT_SEL 2 35 | `define BRANCH_ENT_NUM 4 36 | `define LDST_ENT_SEL 2 37 | `define LDST_ENT_NUM 4 38 | //`define LDST_ENT_SEL 3 39 | //`define LDST_ENT_NUM 8 40 | `define MUL_ENT_SEL 1 41 | `define MUL_ENT_NUM 2 42 | 43 | //STOREBUFFER 44 | `define STBUF_ENT_SEL 5 45 | `define STBUF_ENT_NUM 32 46 | 47 | //BTB 48 | `define BTB_IDX_SEL 9 49 | `define BTB_IDX_NUM 512 50 | //`define BTB_IDX_NUM 2**`BTB_IDX_SEL 51 | //`define BTB_TAG_LEN `ADDR_LEN-3-`BTB_IDX_SEL 52 | `define BTB_TAG_LEN 20 53 | 54 | //Gshare 55 | `define GSH_BHR_LEN 10 56 | `define GSH_PHT_SEL 10 57 | `define GSH_PHT_NUM 1024 58 | //`define GSH_PHT_NUM 2**`GSH_PHT_SEL 59 | 60 | //TagGenerator 61 | 62 | //`define SPECTAG_LEN 1+`BRANCH_ENT_NUM 63 | `define SPECTAG_LEN 5 64 | //`define BRDEPTH_LEN `SPECTAG_LEN 65 | `define BRDEPTH_LEN 5 66 | 67 | //Re-Order Buffer 68 | `define ROB_SEL 6 69 | //`define ROB_NUM 2**`ROB_SEL 70 | `define ROB_NUM 64 71 | `define RRF_SEL `ROB_SEL 72 | `define RRF_NUM `ROB_NUM 73 | 74 | //src_a 75 | `define SRC_A_SEL_WIDTH 2 76 | `define SRC_A_RS1 `SRC_A_SEL_WIDTH'd0 77 | `define SRC_A_PC `SRC_A_SEL_WIDTH'd1 78 | `define SRC_A_ZERO `SRC_A_SEL_WIDTH'd2 79 | 80 | //src_b 81 | `define SRC_B_SEL_WIDTH 2 82 | `define SRC_B_RS2 `SRC_B_SEL_WIDTH'd0 83 | `define SRC_B_IMM `SRC_B_SEL_WIDTH'd1 84 | `define SRC_B_FOUR `SRC_B_SEL_WIDTH'd2 85 | `define SRC_B_ZERO `SRC_B_SEL_WIDTH'd3 86 | 87 | `define MEM_TYPE_WIDTH 3 88 | `define MEM_TYPE_LB `MEM_TYPE_WIDTH'd0 89 | `define MEM_TYPE_LH `MEM_TYPE_WIDTH'd1 90 | `define MEM_TYPE_LW `MEM_TYPE_WIDTH'd2 91 | `define MEM_TYPE_LD `MEM_TYPE_WIDTH'd3 92 | `define MEM_TYPE_LBU `MEM_TYPE_WIDTH'd4 93 | `define MEM_TYPE_LHU `MEM_TYPE_WIDTH'd5 94 | `define MEM_TYPE_LWU `MEM_TYPE_WIDTH'd6 95 | 96 | `define MEM_TYPE_SB `MEM_TYPE_WIDTH'd0 97 | `define MEM_TYPE_SH `MEM_TYPE_WIDTH'd1 98 | `define MEM_TYPE_SW `MEM_TYPE_WIDTH'd2 99 | `define MEM_TYPE_SD `MEM_TYPE_WIDTH'd3 100 | 101 | `define MD_OP_WIDTH 2 102 | `define MD_OP_MUL `MD_OP_WIDTH'd0 103 | `define MD_OP_DIV `MD_OP_WIDTH'd1 104 | `define MD_OP_REM `MD_OP_WIDTH'd2 105 | 106 | `define MD_OUT_SEL_WIDTH 2 107 | `define MD_OUT_LO `MD_OUT_SEL_WIDTH'd0 108 | `define MD_OUT_HI `MD_OUT_SEL_WIDTH'd1 109 | `define MD_OUT_REM `MD_OUT_SEL_WIDTH'd2 110 | 111 | -------------------------------------------------------------------------------- /gen-btor.ys: -------------------------------------------------------------------------------- 1 | read_verilog -formal ./ridecore-src-buggy/define.v \ 2 | ./ridecore-src-buggy/topsim.v \ 3 | ./ridecore-src-buggy/alloc_issue_ino.v \ 4 | ./ridecore-src-buggy/search_be.v \ 5 | ./ridecore-src-buggy/srcsel.v \ 6 | ./ridecore-src-buggy/alu_ops.vh \ 7 | ./ridecore-src-buggy/arf.v \ 8 | ./ridecore-src-buggy/ram_sync.v \ 9 | ./ridecore-src-buggy/ram_sync_nolatch.v \ 10 | ./ridecore-src-buggy/brimm_gen.v \ 11 | ./ridecore-src-buggy/constants.vh \ 12 | ./ridecore-src-buggy/decoder.v \ 13 | ./ridecore-src-buggy/dmem.v \ 14 | ./ridecore-src-buggy/exunit_alu.v \ 15 | ./ridecore-src-buggy/exunit_branch.v \ 16 | ./ridecore-src-buggy/exunit_ldst.v \ 17 | ./ridecore-src-buggy/exunit_mul.v \ 18 | ./ridecore-src-buggy/imem.v \ 19 | ./ridecore-src-buggy/imm_gen.v \ 20 | ./ridecore-src-buggy/pipeline_if.v \ 21 | ./ridecore-src-buggy/gshare.v \ 22 | ./ridecore-src-buggy/pipeline.v \ 23 | ./ridecore-src-buggy/oldest_finder.v \ 24 | ./ridecore-src-buggy/btb.v \ 25 | ./ridecore-src-buggy/prioenc.v \ 26 | ./ridecore-src-buggy/mpft.v \ 27 | ./ridecore-src-buggy/reorderbuf.v \ 28 | ./ridecore-src-buggy/rrf_freelistmanager.v \ 29 | ./ridecore-src-buggy/rrf.v \ 30 | ./ridecore-src-buggy/rs_alu.v \ 31 | ./ridecore-src-buggy/rs_branch.v \ 32 | ./ridecore-src-buggy/rs_ldst.v \ 33 | ./ridecore-src-buggy/rs_mul.v \ 34 | ./ridecore-src-buggy/rs_reqgen.v \ 35 | ./ridecore-src-buggy/rv32_opcodes.vh \ 36 | ./ridecore-src-buggy/src_manager.v \ 37 | ./ridecore-src-buggy/srcopr_manager.v \ 38 | ./ridecore-src-buggy/storebuf.v \ 39 | ./ridecore-src-buggy/tag_generator.v \ 40 | ./ridecore-src-buggy/dualport_ram.v \ 41 | ./ridecore-src-buggy/alu.v \ 42 | ./ridecore-src-buggy/multiplier.v \ 43 | ./sqed-generator/SQED-Generator/QEDFiles/inst_constraints.v \ 44 | ./sqed-generator/SQED-Generator/QEDFiles/modify_instruction.v \ 45 | ./sqed-generator/SQED-Generator/QEDFiles/qed_decoder.v \ 46 | ./sqed-generator/SQED-Generator/QEDFiles/qed_i_cache.v \ 47 | ./sqed-generator/SQED-Generator/QEDFiles/qed_instruction_mux.v \ 48 | ./sqed-generator/SQED-Generator/QEDFiles/qed.v; 49 | 50 | # prep does a conservative elaboration 51 | # of the top module provided 52 | prep -top top; 53 | 54 | # this command just does a sanity check 55 | # of the hierarchy 56 | hierarchy -check; 57 | 58 | # If an assumption is flopped, you might 59 | # see strange behavior at the last state 60 | # (because the clock hasn't toggled) 61 | # this command ensures that assumptions 62 | # hold at every state 63 | chformal -assume -early; 64 | 65 | # this processes memories 66 | # nomap means it will keep them as arrays 67 | memory; 68 | 69 | # flatten the design hierarchy 70 | flatten; 71 | 72 | # (optional) uncomment and set values to simulate reset signal 73 | # use -resetn for an active low pin 74 | # -n configures the number of cycles to simulate 75 | # -rstlen configures how long the reset is active (recommended to keep it active for the whole simulation) 76 | # -w tells it to write back the final state of the simulation as the initial state in the btor2 file 77 | # another useful option is -zinit which zero initializes any uninitialized state 78 | sim -clock clk -resetn reset_x -n 5 -rstlen 5 -zinit -w top 79 | 80 | # This turns all undriven signals into 81 | # inputs 82 | setundef -undriven -expose; 83 | 84 | # This writes to a file in BTOR2 format 85 | write_btor ridecore.btor2 86 | -------------------------------------------------------------------------------- /ridecore-src-buggy/pipeline_if.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module pipeline_if 4 | ( 5 | input wire clk, 6 | input wire reset, 7 | input wire [`ADDR_LEN-1:0] pc, 8 | output wire predict_cond, 9 | output wire [`ADDR_LEN-1:0] npc, 10 | output wire [`INSN_LEN-1:0] inst1, 11 | output wire [`INSN_LEN-1:0] inst2, 12 | output wire invalid2, 13 | input wire btbpht_we, 14 | input wire [`ADDR_LEN-1:0] btbpht_pc, 15 | input wire [`ADDR_LEN-1:0] btb_jmpdst, 16 | input wire pht_wcond, 17 | input wire [`SPECTAG_LEN-1:0] mpft_valid, 18 | input wire [`GSH_BHR_LEN-1:0] pht_bhr, 19 | input wire prmiss, 20 | input wire prsuccess, 21 | input wire [`SPECTAG_LEN-1:0] prtag, 22 | output wire [`GSH_BHR_LEN-1:0] bhr, 23 | input wire [`SPECTAG_LEN-1:0] spectagnow, 24 | input wire [4*`INSN_LEN-1:0] idata 25 | ); 26 | 27 | wire hit; 28 | wire [`ADDR_LEN-1:0] pred_pc; 29 | 30 | assign npc = (hit && predict_cond) ? pred_pc : 31 | invalid2 ? pc + 4 : 32 | pc + 8; 33 | /* 34 | imem instmem( 35 | .clk(~clk), 36 | .addr(pc[12:4]), 37 | .data(idata) 38 | ); 39 | */ 40 | /* 41 | imem_outa instmem( 42 | .pc(pc[31:4]), 43 | .idata(idata) 44 | ); 45 | */ 46 | select_logic sellog( 47 | .sel(pc[3:2]), 48 | .idata(idata), 49 | .inst1(inst1), 50 | .inst2(inst2), 51 | .invalid(invalid2) 52 | ); 53 | 54 | btb brtbl( 55 | .clk(clk), 56 | .reset(reset), 57 | .pc(pc), 58 | .hit(hit), 59 | .jmpaddr(pred_pc), 60 | .we(btbpht_we), 61 | .jmpsrc(btbpht_pc), 62 | .jmpdst(btb_jmpdst), 63 | .invalid2(invalid2) 64 | ); 65 | 66 | gshare_predictor gsh 67 | ( 68 | .clk(clk), 69 | .reset(reset), 70 | .pc(pc), 71 | .hit_bht(hit), 72 | .predict_cond(predict_cond), 73 | .we(btbpht_we), 74 | .wcond(pht_wcond), 75 | .went(btbpht_pc[2+:`GSH_BHR_LEN] ^ pht_bhr), 76 | .mpft_valid(mpft_valid), 77 | .prmiss(prmiss), 78 | .prsuccess(prsuccess), 79 | .prtag(prtag), 80 | .bhr_master(bhr), 81 | .spectagnow(spectagnow) 82 | ); 83 | 84 | endmodule // pipeline_pc 85 | 86 | 87 | module select_logic 88 | ( 89 | input wire [1:0] sel, 90 | input wire [4*`INSN_LEN-1:0] idata, 91 | output reg [`INSN_LEN-1:0] inst1, 92 | output reg [`INSN_LEN-1:0] inst2, 93 | output wire invalid 94 | ); 95 | 96 | assign invalid = (sel[0] == 1'b1); 97 | 98 | always @ (*) begin 99 | inst1 = `INSN_LEN'h0; 100 | inst2 = `INSN_LEN'h0; 101 | 102 | case(sel) 103 | 2'b00 : begin 104 | inst1 = idata[31:0]; 105 | inst2 = idata[63:32]; 106 | end 107 | 2'b01 : begin 108 | inst1 = idata[63:32]; 109 | inst2 = idata[95:64]; 110 | end 111 | 2'b10 : begin 112 | inst1 = idata[95:64]; 113 | inst2 = idata[127:96]; 114 | end 115 | 2'b11 : begin 116 | inst1 = idata[127:96]; 117 | inst2 = idata[31:0]; 118 | end 119 | endcase // case (sel) 120 | end 121 | 122 | endmodule // select_logic 123 | 124 | `default_nettype wire 125 | -------------------------------------------------------------------------------- /ridecore-src-buggy/exunit_ldst.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `include "alu_ops.vh" 3 | //`default_nettype none 4 | 5 | module exunit_ldst 6 | ( 7 | input wire clk, 8 | input wire reset, 9 | input wire [`DATA_LEN-1:0] ex_src1, 10 | input wire [`DATA_LEN-1:0] ex_src2, 11 | input wire [`ADDR_LEN-1:0] pc, 12 | input wire [`DATA_LEN-1:0] imm, 13 | input wire dstval, 14 | input wire [`SPECTAG_LEN-1:0] spectag, 15 | input wire specbit, 16 | input wire issue, 17 | input wire prmiss, 18 | input wire [`SPECTAG_LEN-1:0] spectagfix, 19 | input wire [`RRF_SEL-1:0] rrftag, 20 | output wire [`DATA_LEN-1:0] result, 21 | output wire rrf_we, 22 | output wire rob_we, //set finish 23 | output wire [`RRF_SEL-1:0] wrrftag, 24 | output wire kill_speculative, 25 | output wire busy_next, 26 | //Signal StoreBuf 27 | output wire stfin, 28 | //Store 29 | output wire memoccupy_ld, 30 | input wire fullsb, 31 | output wire [`DATA_LEN-1:0] storedata, 32 | output wire [`ADDR_LEN-1:0] storeaddr, 33 | //Load 34 | input wire hitsb, 35 | output wire [`ADDR_LEN-1:0] ldaddr, 36 | input wire [`DATA_LEN-1:0] lddatasb, 37 | input wire [`DATA_LEN-1:0] lddatamem 38 | ); 39 | 40 | reg busy; 41 | wire clearbusy; 42 | wire [`ADDR_LEN-1:0] effaddr; 43 | wire killspec1; 44 | 45 | //LATCH 46 | reg dstval_latch; 47 | reg [`RRF_SEL-1:0] rrftag_latch; 48 | reg specbit_latch; 49 | reg [`SPECTAG_LEN-1:0] spectag_latch; 50 | reg [`DATA_LEN-1:0] lddatasb_latch; 51 | reg hitsb_latch; 52 | reg insnvalid_latch; 53 | 54 | assign clearbusy = (killspec1 || dstval || (~dstval && ~fullsb)) ? 1'b1 : 1'b0; 55 | assign killspec1 = ((spectag & spectagfix) != 0) && specbit && prmiss; 56 | assign kill_speculative = ((spectag_latch & spectagfix) != 0) && specbit_latch && prmiss; 57 | assign result = hitsb_latch ? lddatasb_latch : lddatamem; 58 | assign rrf_we = dstval_latch & insnvalid_latch; 59 | assign rob_we = insnvalid_latch; 60 | assign wrrftag = rrftag_latch; 61 | assign busy_next = clearbusy ? 1'b0 : busy; 62 | assign stfin = ~killspec1 & busy & ~dstval; 63 | assign memoccupy_ld = ~killspec1 & busy & dstval; 64 | assign storedata = ex_src2; 65 | assign storeaddr = effaddr; 66 | assign ldaddr = effaddr; 67 | assign effaddr = ex_src1 + imm; 68 | 69 | always @ (posedge clk) begin 70 | if (reset | killspec1 | ~busy | (~dstval & fullsb)) begin 71 | dstval_latch <= 0; 72 | rrftag_latch <= 0; 73 | specbit_latch <= 0; 74 | spectag_latch <= 0; 75 | lddatasb_latch <= 0; 76 | hitsb_latch <= 0; 77 | insnvalid_latch <= 0; 78 | end else begin 79 | dstval_latch <= dstval; 80 | rrftag_latch <= rrftag; 81 | specbit_latch <= specbit; 82 | spectag_latch <= spectag; 83 | lddatasb_latch <= lddatasb; 84 | hitsb_latch <= hitsb; 85 | insnvalid_latch <= ~killspec1 & ((busy & dstval) | 86 | (busy & ~dstval & ~fullsb)); 87 | end 88 | end // always @ (posedge clk) 89 | 90 | always @ (posedge clk) begin 91 | if (reset | killspec1) begin 92 | busy <= 0; 93 | end else begin 94 | busy <= issue | busy_next; 95 | end 96 | end 97 | endmodule // exunit_ldst 98 | 99 | //`default_nettype none 100 | -------------------------------------------------------------------------------- /SQED-Generator/LICENSE-Academic: -------------------------------------------------------------------------------- 1 | STANFORD ACADEMIC USE SOFTWARE LICENSE AGREEMENT FOR 2 | Stanford Docket S15-110 “Symbolic Quick Error Detection (SQED)” 3 | 4 | 1. This is a legal agreement between (“RECIPIENT” or “you”), and THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY (“STANFORD”). By accepting, receiving, and using “SQED,” including any accompanying information, materials or manuals (“Program”), you are agreeing to be bound by the terms of this Agreement. If you do not agree to the terms of this Agreement, promptly return the Program to STANFORD. 5 | 2. STANFORD grants to RECIPIENT a royalty-free, nonexclusive, and nontransferable license to use the Program furnished hereunder, upon the terms and conditions set out below. 6 | 3. RECIPIENT acknowledges that the Program is a research tool still in the development stage and that it is being supplied as is, without any accompanying services, support or improvements from STANFORD. STANFORD MAKES NO REPRESENTATIONS AND EXTENDS NO WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED OTHER THAN SET OUT IN THIS AGREEMENT. 7 | 4. STANFORD does not grant any licenses under any Stanford patent or patent application by this Agreement. Specifically, no license is granted to Stanford’s PCT Patent Application Serial Number PCT/US2016/035987 which is related to the SQED software. 8 | 5. RECIPIENT agrees to use the Program solely for internal non-commercial research purposes and shall not distribute or transfer it to another location or to any other person without prior written permission from STANFORD. In particular, no article in this license grants commercial use rights to RECIPIENT. 9 | 6. RECIPIENT acknowledges that any programs created based on the Program will be considered a derivative of Program and owned by STANFORD. 10 | 7. RECIPIENT may NOT make modifications to the Program. 11 | 8. If permission to transfer the Program is given, under Article 5 above, RECIPIENT warrants that RECIPIENT will not remove or export any part of the software or Program from the United States except in full compliance with all United States and other applicable laws and regulations. 12 | 9. RECIPIENT will use the Program in compliance with all applicable laws, policies and regulations including, but not limited to, any approvals, informed consent and patient confidentiality principles. 13 | 10. RECIPIENT will indemnify, hold harmless, and defend STANFORD against any claim of any kind arising out of or related to the exercise of any rights granted under this Agreement or the breach of this Agreement by RECIPIENT. 14 | 11. Title and copyright to the Program and any derivatives and any associated documentation shall at all times remain with STANFORD, and RECIPIENT agrees to preserve same. 15 | 12. This agreement may be terminated by either party upon thirty (30) days written notice to the other party. In the event of termination, RECIPIENT shall destroy or return immediately all Programs and all copies thereof to STANFORD upon STANFORD’s request. 16 | 13. The parties to this document agree that a copy of the original signature (including an electronic copy) may be used for any and all purposes for which the original signature may have been used. The parties further waive any right to challenge the admissibility or authenticity of this document in a court of law based solely on the absence of an original signature. 17 | 14. The Program contains code for data collection purposes including but not limited to tracking and license purposes. RECIPIENT agrees that removal or otherwise disabling these functions constitutes a direct violation of this license. -------------------------------------------------------------------------------- /ridecore-src-buggy/topsim.v: -------------------------------------------------------------------------------- 1 | `include "define.v" 2 | `include "constants.vh" 3 | 4 | module top 5 | ( 6 | // input CLK_P, 7 | // input CLK_N, 8 | // input RST_X_IN, 9 | // output TXD, 10 | // input RXD, 11 | // output reg [7:0] LED 12 | input clk, 13 | input reset_x 14 | ); 15 | 16 | //Active Low SW 17 | // wire clk; 18 | // wire reset_x; 19 | 20 | 21 | wire [`ADDR_LEN-1:0] pc; 22 | wire [4*`INSN_LEN-1:0] idata; 23 | wire [8:0] imem_addr; 24 | wire [`DATA_LEN-1:0] dmem_data; 25 | wire [`DATA_LEN-1:0] dmem_wdata; 26 | wire [`ADDR_LEN-1:0] dmem_addr; 27 | wire dmem_we; 28 | wire [`DATA_LEN-1:0] dmem_wdata_core; 29 | wire [`ADDR_LEN-1:0] dmem_addr_core; 30 | wire dmem_we_core; 31 | 32 | wire utx_we; 33 | wire finish_we; 34 | wire ready_tx; 35 | wire loaded; 36 | 37 | reg prog_loading; 38 | wire [4*`INSN_LEN-1:0] prog_loaddata = 0; 39 | wire [`ADDR_LEN-1:0] prog_loadaddr = 0; 40 | wire prog_dmem_we = 0; 41 | wire prog_imem_we = 0; 42 | /* 43 | assign utx_we = (dmem_we_core && (dmem_addr_core == 32'h0)) ? 1'b1 : 1'b0; 44 | assign finish_we = (dmem_we_core && (dmem_addr_core == 32'h8)) ? 1'b1 : 1'b0; 45 | 46 | always @ (posedge clk) begin 47 | if (!reset_x) begin 48 | LED <= 0; 49 | end else if (utx_we) begin 50 | LED <= {LED[7], dmem_wdata[6:0]}; 51 | end else if (finish_we) begin 52 | LED <= {1'b1, LED[6:0]}; 53 | end 54 | end 55 | */ 56 | always @ (posedge clk) begin 57 | if (!reset_x) begin 58 | prog_loading <= 1'b1; 59 | end else begin 60 | prog_loading <= 0; 61 | end 62 | end 63 | /* 64 | GEN_MMCM_DS genmmcmds 65 | ( 66 | .CLK_P(CLK_P), 67 | .CLK_N(CLK_N), 68 | .RST_X_I(~RST_X_IN), 69 | .CLK_O(clk), 70 | .RST_X_O(reset_x) 71 | ); 72 | */ 73 | pipeline pipe 74 | ( 75 | .clk(clk), 76 | .reset(~reset_x | prog_loading), 77 | .pc(pc), 78 | .idata(idata), 79 | .dmem_wdata(dmem_wdata_core), 80 | .dmem_addr(dmem_addr_core), 81 | .dmem_we(dmem_we_core), 82 | .dmem_data(dmem_data) 83 | ); 84 | 85 | assign dmem_addr = prog_loading ? prog_loadaddr : dmem_addr_core; 86 | assign dmem_we = prog_loading ? prog_dmem_we : dmem_we_core; 87 | assign dmem_wdata = prog_loading ? prog_loaddata[127:96] : dmem_wdata_core; 88 | dmem datamemory( 89 | .clk(clk), 90 | .addr({2'b0, dmem_addr[`ADDR_LEN-1:2]}), 91 | .wdata(dmem_wdata), 92 | .we(dmem_we), 93 | .rdata(dmem_data) 94 | ); 95 | 96 | assign imem_addr = prog_loading ? prog_loadaddr[12:4] : pc[12:4]; 97 | imem_ld instmemory( 98 | .clk(~clk), 99 | .addr(imem_addr), 100 | .rdata(idata), 101 | .wdata(prog_loaddata), 102 | .we(prog_imem_we) 103 | ); 104 | /* 105 | SingleUartTx sutx 106 | ( 107 | .CLK(clk), 108 | .RST_X(reset_x), 109 | .TXD(TXD), 110 | .ERR(), 111 | .DT01(dmem_wdata[7:0]), 112 | .WE01(utx_we) 113 | ); 114 | 115 | PLOADER loader 116 | ( 117 | .CLK(clk), 118 | .RST_X(reset_x), 119 | .RXD(RXD), 120 | .ADDR(prog_loadaddr), 121 | .DATA(prog_loaddata), 122 | .WE_32(prog_dmem_we), 123 | .WE_128(prog_imem_we), 124 | .DONE(loaded) 125 | ); 126 | */ 127 | endmodule // top 128 | 129 | 130 | -------------------------------------------------------------------------------- /SQED-Generator/LICENSE-GOV: -------------------------------------------------------------------------------- 1 | STANFORD GOVERNMENT PURPOSE RIGHTS SOFTWARE LICENSE AGREEMENT FOR 2 | Stanford Docket S15-110 “Symbolic Quick Error Detection (SQED)” 3 | 4 | 1. This is a legal agreement between (“RECIPIENT” or “you”), and THE BOARD OF 5 | TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY (“STANFORD”). By accepting, 6 | receiving, and using “SQED,” including any accompanying information, materials 7 | or manuals (“Program”), you are agreeing to be bound by the terms of this 8 | Agreement. If you do not agree to the terms of this Agreement, promptly return 9 | the Program to STANFORD. 10 | 2. STANFORD grants to RECIPIENT a royalty-free, nonexclusive, and 11 | nontransferable license to use the Program furnished hereunder, upon the 12 | terms and conditions set out below. 13 | 3. RECIPIENT acknowledges that the Program is a research tool still in the 14 | development stage and that it is being supplied as is, without any 15 | accompanying services, support or improvements from STANFORD. 16 | STANFORD MAKES NO REPRESENTATIONS AND EXTENDS NO WARRANTIES OF ANY KIND, 17 | EITHER EXPRESS OR IMPLIED OTHER THAN SET OUT IN THIS AGREEMENT. 18 | 4. STANFORD does not grant any licenses under any Stanford patent or patent 19 | application by this Agreement. Specifically, no license is granted to Stanford’s 20 | PCT Patent Application Serial Number PCT/US2016/035987 which is related to 21 | the SQED software. 22 | 5. STANFORD grants RECIPIENT a Government Purpose Rights license, as 23 | defined by DFARS 252.227-7014. This license provides RECIPIENT with the 24 | rights to: 25 | i. Use, modify, reproduce, release, perform, display, or disclose the 26 | Program or computer software documentation within the Government 27 | without restriction; and 28 | ii. Release or disclose the Program or computer software documentation 29 | outside the Government and authorize persons to whom release or 30 | disclosure has been made to use, modify, reproduce, release, perform, 31 | display, or disclose the software or documentation for United States 32 | government purposes. 33 | 6. RECIPIENT agrees to use the Program solely for Government Purposes as 34 | defined by DFARS 252.227-7014. This license does not grant Unlimited Rights 35 | as defined by DFARS 252.227-7014. 36 | 7. RECIPIENT acknowledges that any programs created based on the Program 37 | will be considered a derivative of Program and owned by STANFORD. 38 | 8. RECIPIENT warrants that RECIPIENT will not remove or export any part of the 39 | software or Program from the United States except in full compliance with all 40 | United States and other applicable laws and regulations. 41 | 9. RECIPIENT will use the Program in compliance with all applicable laws, 42 | policies and regulations including, but not limited to, any approvals, informed 43 | consent and patient confidentiality principles. 44 | 10. Title and copyright to the Program and any derivatives and any associated 45 | documentation shall at all times remain with STANFORD, and RECIPIENT 46 | agrees to preserve same. 47 | 11. The parties to this document agree that a copy of the original signature 48 | (including an electronic copy) may be used for any and all purposes for which 49 | the original signature may have been used. The parties further waive any right 50 | to challenge the admissibility or authenticity of this document in a court of law 51 | based solely on the absence of an original signature. 52 | 12. The Program contains code for data collection purposes including but not 53 | limited to tracking and license purposes. RECIPIENT agrees that removal 54 | or otherwise disabling these functions constitutes a direct violation of this 55 | license. 56 | -------------------------------------------------------------------------------- /ridecore-src-buggy/top.v: -------------------------------------------------------------------------------- 1 | `include "define.v" 2 | `include "constants.vh" 3 | 4 | module top 5 | ( 6 | input CLK_P, 7 | input CLK_N, 8 | input RST_X_IN, 9 | output TXD, 10 | input RXD, 11 | output reg [7:0] LED 12 | ); 13 | 14 | //Active Low SW 15 | wire clk; 16 | wire reset_x; 17 | 18 | 19 | wire [`ADDR_LEN-1:0] pc; 20 | wire [4*`INSN_LEN-1:0] idata; 21 | wire [8:0] imem_addr; 22 | wire [`DATA_LEN-1:0] dmem_data; 23 | wire [`DATA_LEN-1:0] dmem_wdata; 24 | wire [`ADDR_LEN-1:0] dmem_addr; 25 | wire dmem_we; 26 | wire [`DATA_LEN-1:0] dmem_wdata_core; 27 | wire [`ADDR_LEN-1:0] dmem_addr_core; 28 | wire dmem_we_core; 29 | 30 | wire utx_we; 31 | wire finish_we; 32 | reg finished; 33 | wire ready_tx; 34 | wire loaded; 35 | 36 | reg prog_loading; 37 | wire [4*`INSN_LEN-1:0] prog_loaddata; 38 | wire [`ADDR_LEN-1:0] prog_loadaddr; 39 | wire prog_dmem_we; 40 | wire prog_imem_we; 41 | 42 | assign utx_we = (~finished && dmem_we_core && (dmem_addr_core == 32'h0)) ? 1'b1 : 1'b0; 43 | assign finish_we = (dmem_we_core && (dmem_addr_core == 32'h8)) ? 1'b1 : 1'b0; 44 | 45 | always @ (posedge clk) begin 46 | if (!reset_x) begin 47 | LED <= 0; 48 | end else if (utx_we) begin 49 | LED <= {LED[7], dmem_wdata[6:0]}; 50 | end else if (finish_we) begin 51 | LED <= {1'b1, LED[6:0]}; 52 | end 53 | end 54 | 55 | always @ (posedge clk) begin 56 | if (!reset_x) begin 57 | prog_loading <= 1'b1; 58 | end else begin 59 | prog_loading <= ~loaded; 60 | end 61 | end 62 | 63 | always @ (posedge clk) begin 64 | if (!reset_x) begin 65 | finished <= 0; 66 | end else if (finish_we) begin 67 | finished <= 1; 68 | end 69 | end 70 | 71 | GEN_MMCM_DS genmmcmds 72 | ( 73 | .CLK_P(CLK_P), 74 | .CLK_N(CLK_N), 75 | .RST_X_I(~RST_X_IN), 76 | .CLK_O(clk), 77 | .RST_X_O(reset_x) 78 | ); 79 | 80 | pipeline pipe 81 | ( 82 | .clk(clk), 83 | .reset(~reset_x | prog_loading), 84 | .pc(pc), 85 | .idata(idata), 86 | .dmem_wdata(dmem_wdata_core), 87 | .dmem_addr(dmem_addr_core), 88 | .dmem_we(dmem_we_core), 89 | .dmem_data(dmem_data) 90 | ); 91 | 92 | assign dmem_addr = prog_loading ? prog_loadaddr : dmem_addr_core; 93 | assign dmem_we = prog_loading ? prog_dmem_we : dmem_we_core; 94 | assign dmem_wdata = prog_loading ? prog_loaddata[127:96] : dmem_wdata_core; 95 | dmem datamemory( 96 | .clk(clk), 97 | .addr({2'b0, dmem_addr[`ADDR_LEN-1:2]}), 98 | .wdata(dmem_wdata), 99 | .we(dmem_we), 100 | .rdata(dmem_data) 101 | ); 102 | 103 | assign imem_addr = prog_loading ? prog_loadaddr[12:4] : pc[12:4]; 104 | imem_ld instmemory( 105 | .clk(~clk), 106 | .addr(imem_addr), 107 | .rdata(idata), 108 | .wdata(prog_loaddata), 109 | .we(prog_imem_we) 110 | ); 111 | 112 | SingleUartTx sutx 113 | ( 114 | .CLK(clk), 115 | .RST_X(reset_x), 116 | .TXD(TXD), 117 | .ERR(), 118 | .DT01(dmem_wdata[7:0]), 119 | .WE01(utx_we) 120 | ); 121 | 122 | PLOADER loader 123 | ( 124 | .CLK(clk), 125 | .RST_X(reset_x), 126 | .RXD(RXD), 127 | .ADDR(prog_loadaddr), 128 | .DATA(prog_loaddata), 129 | .WE_32(prog_dmem_we), 130 | .WE_128(prog_imem_we), 131 | .DONE(loaded) 132 | ); 133 | 134 | endmodule // top 135 | 136 | 137 | -------------------------------------------------------------------------------- /ridecore-src-buggy/oldest_finder.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module oldest_finder2 #( 4 | parameter ENTLEN = 1, 5 | parameter VALLEN = 8 6 | ) 7 | ( 8 | input wire [2*ENTLEN-1:0] entvec, 9 | input wire [2*VALLEN-1:0] valvec, 10 | output wire [ENTLEN-1:0] oldent, 11 | output wire [VALLEN-1:0] oldval 12 | ); 13 | //VALLEN = RRF_SEL+sortbit+~rdy 14 | 15 | wire [ENTLEN-1:0] ent1 = entvec[0+:ENTLEN]; 16 | wire [ENTLEN-1:0] ent2 = entvec[ENTLEN+:ENTLEN]; 17 | wire [VALLEN-1:0] val1 = valvec[0+:VALLEN]; 18 | wire [VALLEN-1:0] val2 = valvec[VALLEN+:VALLEN]; 19 | 20 | assign oldent = (val1 < val2) ? ent1 : ent2; 21 | assign oldval = (val1 < val2) ? val1 : val2; 22 | 23 | endmodule // oldest_finder2 24 | 25 | module oldest_finder4 #( 26 | parameter ENTLEN = 2, 27 | parameter VALLEN = 8 28 | ) 29 | ( 30 | input wire [4*ENTLEN-1:0] entvec, 31 | input wire [4*VALLEN-1:0] valvec, 32 | output wire [ENTLEN-1:0] oldent, 33 | output wire [VALLEN-1:0] oldval 34 | ); 35 | //VALLEN = RRF_SEL+sortbit+~rdy 36 | 37 | wire [ENTLEN-1:0] oldent1; 38 | wire [ENTLEN-1:0] oldent2; 39 | wire [VALLEN-1:0] oldval1; 40 | wire [VALLEN-1:0] oldval2; 41 | 42 | oldest_finder2 #(ENTLEN, VALLEN) of2_1 43 | ( 44 | .entvec({entvec[ENTLEN+:ENTLEN], entvec[0+:ENTLEN]}), 45 | .valvec({valvec[VALLEN+:VALLEN], valvec[0+:VALLEN]}), 46 | .oldent(oldent1), 47 | .oldval(oldval1) 48 | ); 49 | 50 | oldest_finder2 #(ENTLEN, VALLEN) of2_2 51 | ( 52 | .entvec({entvec[3*ENTLEN+:ENTLEN], entvec[2*ENTLEN+:ENTLEN]}), 53 | .valvec({valvec[3*VALLEN+:VALLEN], valvec[2*VALLEN+:VALLEN]}), 54 | .oldent(oldent2), 55 | .oldval(oldval2) 56 | ); 57 | 58 | oldest_finder2 #(ENTLEN, VALLEN) ofmas 59 | ( 60 | .entvec({oldent2, oldent1}), 61 | .valvec({oldval2, oldval1}), 62 | .oldent(oldent), 63 | .oldval(oldval) 64 | ); 65 | 66 | endmodule // oldest_finder4 67 | 68 | module oldest_finder8 #( 69 | parameter ENTLEN = 3, 70 | parameter VALLEN = 8 71 | ) 72 | ( 73 | input wire [8*ENTLEN-1:0] entvec, 74 | input wire [8*VALLEN-1:0] valvec, 75 | output wire [ENTLEN-1:0] oldent, 76 | output wire [VALLEN-1:0] oldval 77 | ); 78 | //VALLEN = RRF_SEL+sortbit+~rdy 79 | 80 | wire [ENTLEN-1:0] oldent1; 81 | wire [ENTLEN-1:0] oldent2; 82 | wire [VALLEN-1:0] oldval1; 83 | wire [VALLEN-1:0] oldval2; 84 | 85 | oldest_finder4 #(ENTLEN, VALLEN) of4_1 86 | ( 87 | .entvec({entvec[3*ENTLEN+:ENTLEN], entvec[2*ENTLEN+:ENTLEN], 88 | entvec[ENTLEN+:ENTLEN], entvec[0+:ENTLEN]}), 89 | .valvec({valvec[3*VALLEN+:VALLEN], valvec[2*VALLEN+:VALLEN], 90 | valvec[VALLEN+:VALLEN], valvec[0+:VALLEN]}), 91 | .oldent(oldent1), 92 | .oldval(oldval1) 93 | ); 94 | 95 | oldest_finder4 #(ENTLEN, VALLEN) of4_2 96 | ( 97 | .entvec({entvec[7*ENTLEN+:ENTLEN], entvec[6*ENTLEN+:ENTLEN], 98 | entvec[5*ENTLEN+:ENTLEN], entvec[4*ENTLEN+:ENTLEN]}), 99 | .valvec({valvec[7*VALLEN+:VALLEN], valvec[6*VALLEN+:VALLEN], 100 | valvec[5*VALLEN+:VALLEN], valvec[4*VALLEN+:VALLEN]}), 101 | .oldent(oldent2), 102 | .oldval(oldval2) 103 | ); 104 | 105 | oldest_finder2 #(ENTLEN, VALLEN) ofmas 106 | ( 107 | .entvec({oldent2, oldent1}), 108 | .valvec({oldval2, oldval1}), 109 | .oldent(oldent), 110 | .oldval(oldval) 111 | ); 112 | 113 | endmodule // oldest_finder8 114 | 115 | `default_nettype wire 116 | -------------------------------------------------------------------------------- /ridecore-src-buggy/rrf.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | 3 | /* 4 | clear valid when dpen 5 | set valid when wrrfen 6 | */ 7 | `default_nettype none 8 | module rrf( 9 | input wire clk, 10 | input wire reset, 11 | input wire [`RRF_SEL-1:0] rs1_1tag, 12 | input wire [`RRF_SEL-1:0] rs2_1tag, 13 | input wire [`RRF_SEL-1:0] rs1_2tag, 14 | input wire [`RRF_SEL-1:0] rs2_2tag, 15 | input wire [`RRF_SEL-1:0] com1tag, 16 | input wire [`RRF_SEL-1:0] com2tag, 17 | output wire rs1_1valid, 18 | output wire rs2_1valid, 19 | output wire rs1_2valid, 20 | output wire rs2_2valid, 21 | output wire [`DATA_LEN-1:0] rs1_1data, 22 | output wire [`DATA_LEN-1:0] rs2_1data, 23 | output wire [`DATA_LEN-1:0] rs1_2data, 24 | output wire [`DATA_LEN-1:0] rs2_2data, 25 | output wire [`DATA_LEN-1:0] com1data, 26 | output wire [`DATA_LEN-1:0] com2data, 27 | input wire [`RRF_SEL-1:0] wrrfaddr1, 28 | input wire [`RRF_SEL-1:0] wrrfaddr2, 29 | input wire [`RRF_SEL-1:0] wrrfaddr3, 30 | input wire [`RRF_SEL-1:0] wrrfaddr4, 31 | input wire [`RRF_SEL-1:0] wrrfaddr5, 32 | input wire [`DATA_LEN-1:0] wrrfdata1, 33 | input wire [`DATA_LEN-1:0] wrrfdata2, 34 | input wire [`DATA_LEN-1:0] wrrfdata3, 35 | input wire [`DATA_LEN-1:0] wrrfdata4, 36 | input wire [`DATA_LEN-1:0] wrrfdata5, 37 | input wire wrrfen1, 38 | input wire wrrfen2, 39 | input wire wrrfen3, 40 | input wire wrrfen4, 41 | input wire wrrfen5, 42 | input wire [`RRF_SEL-1:0] dpaddr1, 43 | input wire [`RRF_SEL-1:0] dpaddr2, 44 | input wire dpen1, 45 | input wire dpen2 46 | ); 47 | 48 | reg [`RRF_NUM-1:0] valid; 49 | reg [`DATA_LEN-1:0] datarr [0:`RRF_NUM-1]; 50 | 51 | assign rs1_1data = datarr[rs1_1tag]; 52 | assign rs2_1data = datarr[rs2_1tag]; 53 | assign rs1_2data = datarr[rs1_2tag]; 54 | assign rs2_2data = datarr[rs2_2tag]; 55 | assign com1data = datarr[com1tag]; 56 | assign com2data = datarr[com2tag]; 57 | 58 | assign rs1_1valid = valid[rs1_1tag]; 59 | assign rs2_1valid = valid[rs2_1tag]; 60 | assign rs1_2valid = valid[rs1_2tag]; 61 | assign rs2_2valid = valid[rs2_2tag]; 62 | 63 | wire [`RRF_NUM-1:0] or_valid = 64 | (~wrrfen1 ? `RRF_NUM'b0 : 65 | (`RRF_NUM'b1 << wrrfaddr1)) | 66 | (~wrrfen2 ? `RRF_NUM'b0 : 67 | (`RRF_NUM'b1 << wrrfaddr2)) | 68 | (~wrrfen3 ? `RRF_NUM'b0 : 69 | (`RRF_NUM'b1 << wrrfaddr3)) | 70 | (~wrrfen4 ? `RRF_NUM'b0 : 71 | (`RRF_NUM'b1 << wrrfaddr4)) | 72 | (~wrrfen5 ? `RRF_NUM'b0 : 73 | (`RRF_NUM'b1 << wrrfaddr5)); 74 | 75 | wire [`RRF_NUM-1:0] and_valid = 76 | (~dpen1 ? ~(`RRF_NUM'b0) : 77 | ~(`RRF_NUM'b1 << dpaddr1)) & 78 | (~dpen2 ? ~(`RRF_NUM'b0) : 79 | ~(`RRF_NUM'b1 << dpaddr2)); 80 | 81 | always @ (posedge clk) begin 82 | if (reset) begin 83 | valid <= 0; 84 | end else begin 85 | valid <= (valid | or_valid) & and_valid; 86 | end 87 | end 88 | 89 | always @ (posedge clk) begin 90 | if (~reset) begin 91 | if (wrrfen1) 92 | datarr[wrrfaddr1] <= wrrfdata1; 93 | if (wrrfen2) 94 | datarr[wrrfaddr2] <= wrrfdata2; 95 | if (wrrfen3) 96 | datarr[wrrfaddr3] <= wrrfdata3; 97 | if (wrrfen4) 98 | datarr[wrrfaddr4] <= wrrfdata4; 99 | if (wrrfen5) 100 | datarr[wrrfaddr5] <= wrrfdata5; 101 | end 102 | end 103 | endmodule // rrf 104 | `default_nettype wire 105 | -------------------------------------------------------------------------------- /SQED-Generator/Generators/decoder_generator.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) Stanford University 2 | # 3 | # This source code is patent protected and being made available under the 4 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | # Author: Mario J Srouji 7 | # Email: msrouji@stanford.edu 8 | 9 | import copy 10 | import sys 11 | sys.path.append("../FormatParsers/") 12 | sys.path.append("../Interface/") 13 | 14 | import format_parser as P 15 | import module_interface as I 16 | 17 | def generate_decoder_file(MODULENAME, INPUTS, OUTPUTS, format_dicts): 18 | # Get ISA information 19 | isa_info = format_dicts["ISA"] 20 | # Get register names 21 | registers = format_dicts["REGISTERS"] 22 | # Get memory fields needed for modification 23 | memory = format_dicts["MEMORY"] 24 | # Get constraints for qed module setup 25 | qed_constraints = format_dicts["QEDCONSTRAINTS"] 26 | # Get the instruction types 27 | ins_types = format_dicts["INSTYPES"] 28 | # Get the instruction fields for each type 29 | ins_fields = format_dicts["INSFIELDS"] 30 | # Get instruction types requirements 31 | ins_reqs = format_dicts["INSREQS"] 32 | # Get the bit fields 33 | bit_fields = format_dicts["BITFIELDS"] 34 | # Get all instruction types 35 | instructions = {} 36 | for ins in format_dicts["INSTYPES"].keys(): 37 | if ins != "CONSTRAINT": 38 | instructions[ins] = format_dicts[ins] 39 | 40 | # Verilog file 41 | verilog = "" 42 | 43 | # Fill out the OUTPUTS dict 44 | for bit_field in bit_fields: 45 | if bit_field != "CONSTRAINT": 46 | msb, lsb = bit_fields[bit_field].split() 47 | bits = int(msb) - int(lsb) + 1 48 | OUTPUTS[bit_field] = bits 49 | 50 | for ins_type in instructions: 51 | if ins_type in ins_reqs: 52 | OUTPUTS["IS_"+ins_type] = 1 53 | 54 | # Header for module 55 | verilog += I.module_header(MODULENAME, INPUTS, OUTPUTS) 56 | verilog += I.newline(2) 57 | 58 | # Instantiate inputs 59 | for inp in INPUTS: 60 | verilog += I.signal_def(INPUTS[inp], "input", inp, num_spaces=2) 61 | verilog += I.newline(1) 62 | 63 | # Instantiate outputs 64 | verilog += I.newline(1) 65 | for out in OUTPUTS: 66 | verilog += I.signal_def(OUTPUTS[out], "output", out, num_spaces=2) 67 | verilog += I.newline(1) 68 | 69 | # Assign the bit fields to the correct bits in instruction 70 | verilog += I.newline(1) 71 | for bit_field in bit_fields: 72 | if bit_field != "CONSTRAINT": 73 | msb, lsb = bit_fields[bit_field].split() 74 | verilog += I.assign_def(bit_field, I.signal_index(INPUTS.keys()[0], msb, lsb), num_spaces=2) 75 | verilog += I.newline(1) 76 | 77 | # Assign instruction types requirements 78 | verilog += I.newline(1) 79 | for ins_type in instructions: 80 | if not ins_type in ins_reqs: 81 | continue 82 | ins_req = ins_reqs[ins_type] 83 | reqs = ins_req["CONSTRAINT"] 84 | for field in ins_req: 85 | if field != "CONSTRAINT": 86 | if type(ins_req[field]) == type([]): 87 | first = ins_req[field][0] 88 | req_expression = I._equals(field, I._constant(len(first), first), parens=True) 89 | for req in ins_req[field][1:]: 90 | equality = I._equals(field, I._constant(len(req), req), parens=True) 91 | req_expression = I._or(req_expression, equality, parens=False) 92 | req_expression = "(" + req_expression + ")" 93 | reqs.append(req_expression) 94 | else: 95 | equality = I._equals(field, I._constant(len(ins_req[field]), ins_req[field]), parens=True) 96 | reqs.append(equality) 97 | 98 | reqs_expression = reqs[0] 99 | for i in range(1, len(reqs)): 100 | reqs_expression = I._and(reqs_expression, reqs[i], parens=False) 101 | 102 | verilog += I.assign_def("IS_"+ins_type, reqs_expression, num_spaces=2) 103 | verilog += I.newline(1) 104 | 105 | # Module footer 106 | verilog += I.newline(1) 107 | verilog += I.module_footer() 108 | 109 | return verilog 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | -------------------------------------------------------------------------------- /SQED-Generator/Generators/qed_generator.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) Stanford University 2 | # 3 | # This source code is patent protected and being made available under the 4 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | # Author: Mario J Srouji 7 | # Email: msrouji@stanford.edu 8 | 9 | import copy 10 | import sys 11 | sys.path.append("../FormatParsers/") 12 | sys.path.append("../Interface/") 13 | 14 | import format_parser as P 15 | import module_interface as I 16 | 17 | def generate_qed_file(MODULENAME, INPUTS, OUTPUTS, format_dicts): 18 | # Get ISA information 19 | isa_info = format_dicts["ISA"] 20 | # Get register names 21 | registers = format_dicts["REGISTERS"] 22 | # Get memory fields needed for modification 23 | memory = format_dicts["MEMORY"] 24 | # Get constraints for qed module setup 25 | qed_constraints = format_dicts["QEDCONSTRAINTS"] 26 | # Get the instruction types 27 | ins_types = format_dicts["INSTYPES"] 28 | # Get the instruction fields for each type 29 | ins_fields = format_dicts["INSFIELDS"] 30 | # Get instruction types requirements 31 | ins_reqs = format_dicts["INSREQS"] 32 | # Get the bit fields 33 | bit_fields = format_dicts["BITFIELDS"] 34 | # Get all instruction types 35 | instructions = {} 36 | for ins in format_dicts["INSTYPES"].keys(): 37 | if ins != "CONSTRAINT": 38 | instructions[ins] = format_dicts[ins] 39 | 40 | # Verilog file 41 | verilog = "" 42 | 43 | # Adds module header definition 44 | verilog += I.module_header(MODULENAME, INPUTS, OUTPUTS) 45 | verilog += I.newline(2) 46 | 47 | # Instantiate inputs 48 | for inp in INPUTS: 49 | verilog += I.signal_def(INPUTS[inp], "input", inp, num_spaces=2) 50 | verilog += I.newline(1) 51 | 52 | # Instantiate outputs 53 | verilog += I.newline(1) 54 | for out in OUTPUTS: 55 | verilog += I.signal_def(OUTPUTS[out], "output", out, num_spaces=2) 56 | verilog += I.newline(1) 57 | 58 | # Instantiate bit fields as wires 59 | for bit_field in bit_fields: 60 | if bit_field != "CONSTRAINT": 61 | msb, lsb = bit_fields[bit_field].split() 62 | bits = int(msb) - int(lsb) + 1 63 | verilog += I.signal_def(bits, "wire", bit_field, num_spaces=2) 64 | verilog += I.newline(1) 65 | 66 | # Instantiate new instruction types wires 67 | verilog += I.newline(1) 68 | for ins_type in ins_reqs: 69 | if ins_type != "CONSTRAINT": 70 | verilog += I.signal_def(1, "wire", "IS_"+ins_type, num_spaces=2) 71 | verilog += I.newline(1) 72 | 73 | # Instantiate internal instruction versions 74 | verilog += I.newline(1) 75 | verilog += I.signal_def(int(isa_info["instruction_length"]), "wire", "qed_instruction", num_spaces=2) 76 | verilog += I.newline(1) 77 | verilog += I.signal_def(int(isa_info["instruction_length"]), "wire", "qic_qimux_instruction", num_spaces=2) 78 | verilog += I.newline(2) 79 | 80 | # Decoder module 81 | decoder_args = ["qic_qimux_instruction"] 82 | decoder_args = decoder_args + list(bit_fields.keys()) 83 | decoder_args.remove("CONSTRAINT") 84 | decoder_args = decoder_args + [("IS_"+key) for key in ins_reqs] 85 | decoder_args.remove("IS_CONSTRAINT") 86 | signals = decoder_args 87 | names = copy.deepcopy(signals) 88 | names[0] = "ifu_qed_instruction" 89 | verilog += I.module_def("qed_decoder", "dec", names, signals, num_spaces=2) 90 | verilog += I.newline(2) 91 | 92 | # Modify module 93 | modify_args = ["qed_instruction", "qic_qimux_instruction"] 94 | modify_args = modify_args + list(bit_fields.keys()) 95 | modify_args.remove("CONSTRAINT") 96 | modify_args = modify_args + [("IS_"+key) for key in ins_reqs] 97 | modify_args.remove("IS_CONSTRAINT") 98 | signals = modify_args 99 | names = modify_args 100 | verilog += I.module_def("modify_instruction", "minst", names, signals, num_spaces=2) 101 | verilog += I.newline(2) 102 | 103 | # Mux module 104 | mux_args = ["qed_ifu_instruction", "ifu_qed_instruction", "qed_instruction", "exec_dup", "ena"] 105 | signals = mux_args 106 | names = mux_args 107 | verilog += I.module_def("qed_instruction_mux", "imux", names, signals, num_spaces=2) 108 | verilog += I.newline(2) 109 | 110 | # Cache module 111 | cache_args = ["qic_qimux_instruction", "vld_out", "clk", "rst", "exec_dup", "stall_IF", "ifu_qed_instruction"] 112 | signals = cache_args 113 | names = copy.deepcopy(signals) 114 | names[-2] = "IF_stall" 115 | verilog += I.module_def("qed_i_cache", "qic", names, signals, num_spaces=2) 116 | verilog += I.newline(2) 117 | 118 | verilog += I.module_footer() 119 | 120 | return verilog 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | -------------------------------------------------------------------------------- /SQED-Generator/Interface/module_interface.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) Stanford University 2 | # 3 | # This source code is patent protected and being made available under the 4 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | # Author: Mario J Srouji 7 | # Email: msrouji@stanford.edu 8 | 9 | def module_def(module, name, arg_names, arg_signals, num_spaces=2): 10 | module_definition = " "*num_spaces 11 | module_definition = module_definition + module + " " + name + " (" 12 | 13 | spaces_so_far = len(module_definition) 14 | 15 | args_length = len(arg_names) 16 | assert(len(arg_names) == len(arg_signals)) 17 | 18 | i = 0 19 | for arg_name in arg_names: 20 | module_definition = module_definition + "." + arg_name + "(" + arg_signals[i] + ")" 21 | if i < args_length - 1: 22 | module_definition = module_definition + ",\n" + " "*spaces_so_far 23 | i += 1 24 | 25 | module_definition = module_definition + ");" 26 | 27 | return module_definition 28 | 29 | def signal_def(bits, signal_type, signal_name, num_spaces=2): 30 | if bits == 1: 31 | return " "*num_spaces + signal_type + " " + signal_name + ";" 32 | else: 33 | return " "*num_spaces + signal_type + " [" + str(bits-1) + ":0] " + signal_name + ";" 34 | 35 | def module_header(name, inputs, outputs): 36 | header = "module " + name + " (\n" 37 | 38 | if len(outputs) > 0: 39 | header = header + "// Outputs\n" 40 | 41 | i = 0 42 | for out in outputs: 43 | i += 1 44 | header = header + out 45 | if len(inputs) > 0 or i < len(outputs): 46 | header = header + ",\n" 47 | 48 | if len(inputs) > 0: 49 | header = header + "// Inputs\n" 50 | 51 | i = 0 52 | for inp in inputs: 53 | i += 1 54 | header = header + inp 55 | if i < len(inputs): 56 | header = header + ",\n" 57 | 58 | header = header + ");" 59 | 60 | return header 61 | 62 | def module_footer(): 63 | return "endmodule" 64 | 65 | def direct_assignment_def(name, expression, num_spaces=2): 66 | return " "*num_spaces + name + " = " + expression + ";" 67 | 68 | def assign_def(name, expression, num_spaces=2): 69 | return " "*num_spaces + "assign " + name + " = " + expression + ";" 70 | 71 | def operator(op, left, right, parens): 72 | if parens: 73 | return "(" + left + " " + op + " " + right + ")" 74 | else: 75 | return left + " " + op + " " + right 76 | 77 | def _equals(left, right, parens=False): 78 | return operator("==", left, right, parens) 79 | 80 | def _and(left, right, parens=False): 81 | return operator("&&", left, right, parens) 82 | 83 | def _or(left, right, parens=False): 84 | return operator("||", left, right, parens) 85 | 86 | def _lt(left, right, parens=False): 87 | return operator("<", left, right, parens) 88 | 89 | def _le(left, right, parens=False): 90 | return operator("<=", left, right, parens) 91 | 92 | def _gt(left, right, parens=False): 93 | return operator(">", left, right, parens) 94 | 95 | def _ge(left, right, parens=False): 96 | return operator(">=", left, right, parens) 97 | 98 | def _constant(bits, value): 99 | return str(bits) + "'b" + value 100 | 101 | def bit_vector(signals): 102 | vector = "{" 103 | i = 0 104 | for signal in signals: 105 | i += 1 106 | vector = vector + signal 107 | if i < len(signals): 108 | vector = vector + ", " 109 | 110 | vector = vector + "}" 111 | 112 | return vector 113 | 114 | def always_def(signal, num_spaces=2): 115 | return " "*num_spaces + "always @(posedge " + signal + ")" 116 | 117 | def always_comb_def(num_spaces=2): 118 | return " "*num_spaces + "always_comb begin" 119 | 120 | def property_def(expression, num_spaces=2): 121 | return " "*num_spaces + "assume property " + "(" + expression + ");" 122 | 123 | def begin(num_spaces=1): 124 | return " "*num_spaces + "begin" 125 | 126 | def end(num_spaces=2): 127 | return " "*num_spaces + "end" 128 | 129 | def inline_conditional(check, true, false, endit): 130 | inline = check + " ? " + true + " : " + false 131 | if endit: 132 | inline = inline + ";" 133 | return inline 134 | 135 | def conditional_header(conditional, expression, num_spaces=2): 136 | return " "*num_spaces + conditional + " (" + expression + ") begin" 137 | 138 | def if_header(expression, num_spaces=2): 139 | return conditional_header("if", expression, num_spaces=num_spaces) 140 | 141 | def else_if_header(expression, num_spaces=2): 142 | return conditional_header("else if", expression, num_spaces=num_spaces) 143 | 144 | def else_header(num_spaces=2): 145 | return " "*num_spaces + "else begin" 146 | 147 | def signal_index(signal, msb, lsb): 148 | return signal + "[" + msb + ":" + lsb + "]" 149 | 150 | def newline(n): 151 | return "\n"*n 152 | 153 | 154 | -------------------------------------------------------------------------------- /ridecore-src-buggy/gshare.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | 3 | /* 4 | ATTENTION!!!!!!!!!!!!!!!!! 5 | BHR in this code must change when spectag_len is changed 6 | */ 7 | `default_nettype none 8 | module sel_bhrfix( 9 | input wire [4:0] sel, 10 | input wire [`GSH_BHR_LEN-1:0] bhr0, 11 | input wire [`GSH_BHR_LEN-1:0] bhr1, 12 | input wire [`GSH_BHR_LEN-1:0] bhr2, 13 | input wire [`GSH_BHR_LEN-1:0] bhr3, 14 | input wire [`GSH_BHR_LEN-1:0] bhr4, 15 | output reg [`GSH_BHR_LEN-1:0] out 16 | ); 17 | always @ (*) begin 18 | out = 0; 19 | case (sel) 20 | 5'b00001 : out = bhr0; 21 | 5'b00010 : out = bhr1; 22 | 5'b00100 : out = bhr2; 23 | 5'b01000 : out = bhr3; 24 | 5'b10000 : out = bhr4; 25 | default : out = 0; 26 | endcase // case (sel) 27 | end 28 | 29 | endmodule // sel_bhr 30 | 31 | //PRTAG is tag of prmiss/success branch instruction's 32 | module gshare_predictor 33 | ( 34 | input wire clk, 35 | input wire reset, 36 | input wire [`ADDR_LEN-1:0] pc, 37 | input wire hit_bht, 38 | output wire predict_cond, 39 | input wire we, 40 | input wire wcond, 41 | input wire [`GSH_PHT_SEL-1:0] went, 42 | input wire [`SPECTAG_LEN-1:0] mpft_valid, 43 | input wire prmiss, 44 | input wire prsuccess, 45 | input wire [`SPECTAG_LEN-1:0] prtag, 46 | output reg [`GSH_BHR_LEN-1:0] bhr_master, 47 | input wire [`SPECTAG_LEN-1:0] spectagnow 48 | ); 49 | 50 | reg [`GSH_BHR_LEN-1:0] bhr0; 51 | reg [`GSH_BHR_LEN-1:0] bhr1; 52 | reg [`GSH_BHR_LEN-1:0] bhr2; 53 | reg [`GSH_BHR_LEN-1:0] bhr3; 54 | reg [`GSH_BHR_LEN-1:0] bhr4; 55 | wire [`GSH_BHR_LEN-1:0] bhr_fix; 56 | wire [1:0] rif; 57 | wire [1:0] rex; 58 | wire [1:0] wex; 59 | wire [2:0] wex_calc; 60 | 61 | sel_bhrfix sb( 62 | .sel(prtag), 63 | .bhr0(bhr0), 64 | .bhr1(bhr1), 65 | .bhr2(bhr2), 66 | .bhr3(bhr3), 67 | .bhr4(bhr4), 68 | .out(bhr_fix) 69 | ); 70 | 71 | always @ (posedge clk) begin 72 | if (reset) begin 73 | bhr0 <= 0; 74 | bhr1 <= 0; 75 | bhr2 <= 0; 76 | bhr3 <= 0; 77 | bhr4 <= 0; 78 | bhr_master <= 0; 79 | end else if (prmiss) begin 80 | bhr0 <= bhr_fix; 81 | bhr1 <= bhr_fix; 82 | bhr2 <= bhr_fix; 83 | bhr3 <= bhr_fix; 84 | bhr4 <= bhr_fix; 85 | bhr_master <= bhr_fix; 86 | end else if (prsuccess) begin 87 | bhr0 <= (prtag == 5'b00001) ? {bhr_master[`GSH_BHR_LEN-2:0], predict_cond} : bhr0; 88 | bhr1 <= (prtag == 5'b00010) ? {bhr_master[`GSH_BHR_LEN-2:0], predict_cond} : bhr1; 89 | bhr2 <= (prtag == 5'b00100) ? {bhr_master[`GSH_BHR_LEN-2:0], predict_cond} : bhr2; 90 | bhr3 <= (prtag == 5'b01000) ? {bhr_master[`GSH_BHR_LEN-2:0], predict_cond} : bhr3; 91 | bhr4 <= (prtag == 5'b10000) ? {bhr_master[`GSH_BHR_LEN-2:0], predict_cond} : bhr4; 92 | end else if (hit_bht) begin 93 | if (we & mpft_valid[0]) begin 94 | bhr0 <= {bhr0[`GSH_BHR_LEN-2:0], predict_cond}; 95 | end 96 | if (we & mpft_valid[1]) begin 97 | bhr1 <= {bhr1[`GSH_BHR_LEN-2:0], predict_cond}; 98 | end 99 | if (we & mpft_valid[2]) begin 100 | bhr2 <= {bhr2[`GSH_BHR_LEN-2:0], predict_cond}; 101 | end 102 | if (we & mpft_valid[3]) begin 103 | bhr3 <= {bhr3[`GSH_BHR_LEN-2:0], predict_cond}; 104 | end 105 | if (we & mpft_valid[4]) begin 106 | bhr4 <= {bhr4[`GSH_BHR_LEN-2:0], predict_cond}; 107 | end 108 | if (we) begin 109 | bhr_master <= {bhr_master[`GSH_BHR_LEN-2:0], predict_cond}; 110 | end 111 | end 112 | end 113 | 114 | assign predict_cond = (hit_bht && (rif > 2'b01)) ? 1'b1 : 1'b0; 115 | assign wex_calc = {1'b0, rex} + (wcond ? 3'b001 : 3'b111); 116 | assign wex = ((rex == 2'b00) && ~wcond) ? 2'b00 : 117 | ((rex == 2'b11) && wcond) ? 2'b11 : wex_calc[1:0]; 118 | 119 | pht prhisttbl 120 | ( 121 | .clk(clk), 122 | .raddr_if(pc[2+:`GSH_BHR_LEN] ^ bhr_master), 123 | .raddr_ex(went), 124 | .waddr_ex(went), 125 | .rdata_if(rif), 126 | .rdata_ex(rex), 127 | .wdata_ex(wex), 128 | .we_ex(we) 129 | ); 130 | 131 | 132 | endmodule // gshare_predictor 133 | 134 | module pht( 135 | input wire clk, 136 | input wire [`GSH_PHT_SEL-1:0] raddr_if, 137 | input wire [`GSH_PHT_SEL-1:0] raddr_ex, 138 | input wire [`GSH_PHT_SEL-1:0] waddr_ex, 139 | output wire [1:0] rdata_if, 140 | output wire [1:0] rdata_ex, 141 | input wire [1:0] wdata_ex, 142 | input wire we_ex 143 | ); 144 | 145 | true_dualport_ram #(`GSH_PHT_SEL, 2, `GSH_PHT_NUM) pht0 146 | ( 147 | .clka(~clk), 148 | .addra(raddr_if), 149 | .rdataa(rdata_if), 150 | .wdataa(), 151 | .wea(1'b0), 152 | .clkb(clk), 153 | .addrb(waddr_ex), 154 | .rdatab(), 155 | .wdatab(wdata_ex), 156 | .web(we_ex) 157 | ); 158 | 159 | true_dualport_ram #(`GSH_PHT_SEL, 2, `GSH_PHT_NUM) pht1 160 | ( 161 | .clka(~clk), 162 | .addra(raddr_ex), 163 | .rdataa(rdata_ex), 164 | .wdataa(), 165 | .wea(1'b0), 166 | .clkb(clk), 167 | .addrb(waddr_ex), 168 | .rdatab(), 169 | .wdatab(wdata_ex), 170 | .web(we_ex) 171 | ); 172 | 173 | endmodule // pht 174 | `default_nettype wire 175 | -------------------------------------------------------------------------------- /ridecore-src-buggy/mpft.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module tag_decoder 4 | ( 5 | input wire [`SPECTAG_LEN-1:0] in, 6 | output reg [2:0] out 7 | ); 8 | 9 | always @ (*) begin 10 | out = 0; 11 | case (in) 12 | 5'b00001: out = 0; 13 | 5'b00010: out = 1; 14 | 5'b00100: out = 2; 15 | 5'b01000: out = 3; 16 | 5'b10000: out = 4; 17 | default: out = 0; 18 | endcase // case (in) 19 | end 20 | endmodule // tag_decoder 21 | 22 | module miss_prediction_fix_table 23 | ( 24 | input wire clk, 25 | input wire reset, 26 | output reg [`SPECTAG_LEN-1:0] mpft_valid, 27 | input wire [`SPECTAG_LEN-1:0] value_addr, 28 | output wire [`SPECTAG_LEN-1:0] mpft_value, 29 | input wire prmiss, 30 | input wire prsuccess, 31 | input wire [`SPECTAG_LEN-1:0] prsuccess_tag, 32 | input wire [`SPECTAG_LEN-1:0] setspec1_tag, //inst1_spectag 33 | input wire setspec1_en, //inst1_isbranch & ~inst1_inv 34 | input wire [`SPECTAG_LEN-1:0] setspec2_tag, 35 | input wire setspec2_en 36 | ); 37 | 38 | reg [`SPECTAG_LEN-1:0] value0; 39 | reg [`SPECTAG_LEN-1:0] value1; 40 | reg [`SPECTAG_LEN-1:0] value2; 41 | reg [`SPECTAG_LEN-1:0] value3; 42 | reg [`SPECTAG_LEN-1:0] value4; 43 | 44 | wire [2:0] val_idx; 45 | 46 | tag_decoder td( 47 | .in(value_addr), 48 | .out(val_idx) 49 | ); 50 | 51 | 52 | assign mpft_value = { 53 | value4[val_idx], 54 | value3[val_idx], 55 | value2[val_idx], 56 | value1[val_idx], 57 | value0[val_idx] 58 | }; 59 | 60 | /* 61 | wire [`SPECTAG_LEN-1:0] value0_wdec = 62 | (~setspec1_tag[0] || ~setspec1_en ? 5'b0 : 63 | (setspec1_tag | 64 | ((setspec1_tag == 5'b00001) ? mpft_valid : 5'b0))) | 65 | (~setspec2_tag[0] || ~setspec2_en ? 5'b0 : 66 | (setspec2_tag | 67 | ((setspec2_tag == 5'b00001) ? mpft_valid : 5'b0))); 68 | */ 69 | wire [`SPECTAG_LEN-1:0] wdecdata = mpft_valid | (setspec1_en ? setspec1_tag : 0); 70 | 71 | wire [`SPECTAG_LEN-1:0] value0_wdec = 72 | (~setspec1_tag[0] || ~setspec1_en ? 5'b0 : 73 | (setspec1_tag | 74 | ((setspec1_tag == 5'b00001) ? mpft_valid : 5'b0))) | 75 | (~setspec2_tag[0] || ~setspec2_en ? 5'b0 : 76 | (setspec2_tag | 77 | ((setspec2_tag == 5'b00001) ? wdecdata : 5'b0))); 78 | 79 | wire [`SPECTAG_LEN-1:0] value1_wdec = 80 | (~setspec1_tag[1] || ~setspec1_en ? 5'b0 : 81 | (setspec1_tag | 82 | ((setspec1_tag == 5'b00010) ? mpft_valid : 5'b0))) | 83 | (~setspec2_tag[1] || ~setspec2_en ? 5'b0 : 84 | (setspec2_tag | 85 | ((setspec2_tag == 5'b00010) ? wdecdata : 5'b0))); 86 | 87 | wire [`SPECTAG_LEN-1:0] value2_wdec = 88 | (~setspec1_tag[2] || ~setspec1_en ? 5'b0 : 89 | (setspec1_tag | 90 | ((setspec1_tag == 5'b00100) ? mpft_valid : 5'b0))) | 91 | (~setspec2_tag[2] || ~setspec2_en ? 5'b0 : 92 | (setspec2_tag | 93 | ((setspec2_tag == 5'b00100) ? wdecdata : 5'b0))); 94 | 95 | wire [`SPECTAG_LEN-1:0] value3_wdec = 96 | (~setspec1_tag[3] || ~setspec1_en ? 5'b0 : 97 | (setspec1_tag | 98 | ((setspec1_tag == 5'b01000) ? mpft_valid : 5'b0))) | 99 | (~setspec2_tag[3] || ~setspec2_en ? 5'b0 : 100 | (setspec2_tag | 101 | ((setspec2_tag == 5'b01000) ? wdecdata : 5'b0))); 102 | 103 | wire [`SPECTAG_LEN-1:0] value4_wdec = 104 | (~setspec1_tag[4] || ~setspec1_en ? 5'b0 : 105 | (setspec1_tag | 106 | ((setspec1_tag == 5'b10000) ? mpft_valid : 5'b0))) | 107 | (~setspec2_tag[4] || ~setspec2_en ? 5'b0 : 108 | (setspec2_tag | 109 | ((setspec2_tag == 5'b10000) ? wdecdata : 5'b0))); 110 | 111 | wire [`SPECTAG_LEN-1:0] value0_wprs = 112 | (prsuccess_tag[0] ? 5'b0 : ~prsuccess_tag); 113 | wire [`SPECTAG_LEN-1:0] value1_wprs = 114 | (prsuccess_tag[1] ? 5'b0 : ~prsuccess_tag); 115 | wire [`SPECTAG_LEN-1:0] value2_wprs = 116 | (prsuccess_tag[2] ? 5'b0 : ~prsuccess_tag); 117 | wire [`SPECTAG_LEN-1:0] value3_wprs = 118 | (prsuccess_tag[3] ? 5'b0 : ~prsuccess_tag); 119 | wire [`SPECTAG_LEN-1:0] value4_wprs = 120 | (prsuccess_tag[4] ? 5'b0 : ~prsuccess_tag); 121 | 122 | always @ (posedge clk) begin 123 | if (reset | prmiss) begin 124 | mpft_valid <= 0; 125 | end else if (prsuccess) begin 126 | mpft_valid <= mpft_valid & ~prsuccess_tag; 127 | end else begin 128 | mpft_valid <= mpft_valid | 129 | (setspec1_en ? setspec1_tag : 0) | 130 | (setspec2_en ? setspec2_tag : 0); 131 | end 132 | end 133 | 134 | always @ (posedge clk) begin 135 | if (reset | prmiss) begin 136 | value0 <= 0; 137 | value1 <= 0; 138 | value2 <= 0; 139 | value3 <= 0; 140 | value4 <= 0; 141 | end else begin 142 | value0 <= prsuccess ? (value0 & value0_wprs) : (value0 | value0_wdec); 143 | value1 <= prsuccess ? (value1 & value1_wprs) : (value1 | value1_wdec); 144 | value2 <= prsuccess ? (value2 & value2_wprs) : (value2 | value2_wdec); 145 | value3 <= prsuccess ? (value3 & value3_wprs) : (value3 | value3_wdec); 146 | value4 <= prsuccess ? (value4 & value4_wprs) : (value4 | value4_wdec); 147 | end 148 | end 149 | 150 | endmodule // miss_prediction_fix_table 151 | `default_nettype wire 152 | -------------------------------------------------------------------------------- /ridecore-src-buggy/storebuf.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | 3 | module storebuf 4 | ( 5 | input wire clk, 6 | input wire reset, 7 | input wire prsuccess, 8 | input wire prmiss, 9 | input wire [`SPECTAG_LEN-1:0] prtag, 10 | input wire [`SPECTAG_LEN-1:0] spectagfix, 11 | input wire stfin, 12 | input wire stspecbit, 13 | input wire [`SPECTAG_LEN-1:0] stspectag, 14 | input wire [`DATA_LEN-1:0] stdata, 15 | input wire [`ADDR_LEN-1:0] staddr, 16 | input wire stcom, 17 | output wire stretire, //dmem_we 18 | output wire [`DATA_LEN-1:0] retdata, 19 | output wire [`ADDR_LEN-1:0] retaddr, 20 | input wire memoccupy_ld, 21 | output wire sb_full, 22 | //ReadSigs 23 | input wire [`ADDR_LEN-1:0] ldaddr, 24 | output wire [`DATA_LEN-1:0] lddata, 25 | output wire hit 26 | ); 27 | 28 | reg [`STBUF_ENT_SEL-1:0] finptr; 29 | reg [`STBUF_ENT_SEL-1:0] comptr; 30 | reg [`STBUF_ENT_SEL-1:0] retptr; 31 | 32 | reg [`SPECTAG_LEN-1:0] spectag [0:`STBUF_ENT_NUM-1]; 33 | reg [`STBUF_ENT_NUM-1:0] completed; 34 | reg [`STBUF_ENT_NUM-1:0] valid; 35 | reg [`STBUF_ENT_NUM-1:0] specbit; 36 | reg [`DATA_LEN-1:0] data [0:`STBUF_ENT_NUM-1]; 37 | reg [`ADDR_LEN-1:0] addr [0:`STBUF_ENT_NUM-1]; 38 | 39 | //when prsuccess, specbit_next = specbit & specbitcls 40 | wire [`STBUF_ENT_NUM-1:0] specbit_cls; 41 | wire [`STBUF_ENT_NUM-1:0] valid_cls; 42 | wire notfull_next; 43 | wire notempty_next; 44 | wire [`STBUF_ENT_SEL-1:0] nb1; 45 | wire [`STBUF_ENT_SEL-1:0] ne1; 46 | wire [`STBUF_ENT_SEL-1:0] nb0; 47 | wire [`STBUF_ENT_SEL-1:0] finptr_next; 48 | //For CAM with Priority 49 | wire [`STBUF_ENT_NUM-1:0] hitvec; 50 | wire [2*`STBUF_ENT_NUM-1:0] hitvec_rot; 51 | wire [`STBUF_ENT_SEL-1:0] ldent_rot; 52 | wire [`STBUF_ENT_SEL-1:0] ldent; 53 | wire [`STBUF_ENT_SEL-1:0] vecshamt; 54 | 55 | search_begin #(`STBUF_ENT_SEL, `STBUF_ENT_NUM) 56 | snb1( 57 | .in(valid & valid_cls), 58 | .out(nb1), 59 | .en() 60 | ); 61 | 62 | search_end #(`STBUF_ENT_SEL, `STBUF_ENT_NUM) 63 | sne1( 64 | .in(valid & valid_cls), 65 | .out(ne1), 66 | .en(notempty_next) 67 | ); 68 | 69 | search_begin #(`STBUF_ENT_SEL, `STBUF_ENT_NUM) 70 | snb0( 71 | .in(~(valid & valid_cls)), 72 | .out(nb0), 73 | .en(notfull_next) 74 | ); 75 | 76 | search_end #(`STBUF_ENT_SEL, `STBUF_ENT_NUM) 77 | findhitent( 78 | .in(hitvec_rot[2*`STBUF_ENT_NUM-1:`STBUF_ENT_NUM]), 79 | .out(ldent_rot), 80 | .en(hit) 81 | ); 82 | 83 | assign retdata = data[retptr]; 84 | assign retaddr = addr[retptr]; 85 | assign lddata = data[ldent]; 86 | assign stretire = valid[retptr] && completed[retptr] && ~memoccupy_ld && 87 | ~prmiss; 88 | assign sb_full = ((finptr == retptr) && (valid[finptr] == 1)) ? 1'b1 : 1'b0; 89 | assign finptr_next = (~notfull_next | ~notempty_next) ? finptr : 90 | (((nb1 == 0) && (ne1 == `STBUF_ENT_NUM-1)) ? nb0 : (ne1+1)); 91 | assign vecshamt = (`STBUF_ENT_NUM - finptr); 92 | assign hitvec_rot = {hitvec, hitvec} << vecshamt; 93 | assign ldent = ldent_rot + finptr; 94 | 95 | generate 96 | genvar i; 97 | for (i = 0 ; i < `STBUF_ENT_NUM ; i = i + 1) 98 | begin: L1 99 | assign specbit_cls[i] = (prtag == spectag[i]) ? 1'b0 : 1'b1; 100 | assign valid_cls[i] = (specbit[i] && ((spectagfix & spectag[i]) != 0)) ? 101 | 1'b0 : 1'b1; 102 | assign hitvec[i] = (valid[i] && (addr[i] == ldaddr)) ? 1'b1 : 1'b0; 103 | end 104 | endgenerate 105 | 106 | always @ (posedge clk) begin 107 | if (~reset & stfin) begin 108 | data[finptr] <= stdata; 109 | addr[finptr] <= staddr; 110 | spectag[finptr] <= stspectag; 111 | end 112 | end 113 | 114 | always @ (posedge clk) begin 115 | if (reset) begin 116 | finptr <= 0; 117 | comptr <= 0; 118 | retptr <= 0; 119 | valid <= 0; 120 | completed <= 0; 121 | end else if (prmiss) begin 122 | if (stfin) begin 123 | //KillNotOccur!!! 124 | finptr <= finptr + 1; 125 | valid[finptr] <= 1'b1; 126 | completed[finptr] <= 1'b0; 127 | comptr <= comptr; 128 | retptr <= retptr; 129 | end else begin 130 | valid <= valid & valid_cls; 131 | finptr <= finptr_next; 132 | comptr <= ~notempty_next ? finptr : comptr; 133 | retptr <= ~notempty_next ? finptr : retptr; 134 | end 135 | end else begin 136 | if (stfin) begin 137 | finptr <= finptr + 1; 138 | valid[finptr] <= 1'b1; 139 | completed[finptr] <= 1'b0; 140 | end 141 | if (stcom) begin 142 | comptr <= comptr + 1; 143 | completed[comptr] <= 1'b1; 144 | end 145 | if (stretire) begin 146 | retptr <= retptr + 1; 147 | valid[retptr] <= 1'b0; 148 | completed[retptr] <= 1'b0; 149 | end 150 | end 151 | end // always @ (posedge clk) 152 | 153 | always @ (posedge clk) begin 154 | if (reset | prmiss) begin 155 | specbit <= 0; 156 | end else if (prsuccess) begin 157 | specbit <= (specbit & specbit_cls) | 158 | (stfin ? 159 | ({`STBUF_ENT_NUM{stspecbit}} << finptr) : 160 | `STBUF_ENT_NUM'b0); 161 | end else begin 162 | if (stfin) begin 163 | specbit[finptr] <= stspecbit; 164 | end 165 | end 166 | end 167 | endmodule // storebuf 168 | -------------------------------------------------------------------------------- /SQED-Generator/FormatFiles/ORBIS32_format.txt: -------------------------------------------------------------------------------- 1 | # You can use python style comments with (#) 2 | # to add notes, or comment out lines. 3 | 4 | # Copyright (c) Stanford University 5 | # 6 | # This source code is patent protected and being made available under the 7 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 8 | 9 | # Author: Mario J Srouji 10 | # Email: msrouji@stanford.edu 11 | 12 | SECTIONS = ISA QEDCONSTRAINTS REGISTERS MEMORY BITFIELDS INSTYPES INSFIELDS INSREQS R I LW SW NOP 13 | 14 | _ISA 15 | num_registers = 32 16 | instruction_length = 32 17 | 18 | _QEDCONSTRAINTS 19 | half_registers = 1 20 | half_memory = 1 21 | 22 | _REGISTERS 23 | rD 24 | rA 25 | rB 26 | 27 | # Defines the memory fields to be modified in the 28 | # modify file 29 | _MEMORY 30 | imm12 31 | imm7 32 | 33 | _BITFIELDS 34 | rD = 25 21 35 | rA = 20 16 36 | rB = 15 11 37 | opcode2 = 9 8 38 | opcode4 = 3 0 39 | opcode6 = 31 26 40 | simm16 = 15 0 41 | 42 | opcode4EXT = 9 6 43 | opcodeFP = 7 0 44 | 45 | _INSTYPES 46 | CONSTRAINT MEMORYTYPE: LW SW 47 | 48 | R 49 | I 50 | LW 51 | SW 52 | NOP 53 | 54 | _INSFIELDS 55 | R = funct7 rs2 rs1 funct3 rd opcode 56 | I = imm12 rs1 funct3 rd opcode 57 | LW = imm12 rs1 funct3 rd opcode 58 | SW = imm7 rs2 rs1 funct3 imm5 opcode 59 | NOP = imm12 rs1 funct3 rd opcode 60 | 61 | _INSREQS 62 | R 63 | opcode6 = 111000 64 | 65 | I 66 | opcode6 = 100111 67 | opcode6 = 101001 68 | opcode6 = 101100 69 | opcode6 = 101010 70 | opcode6 = 101011 71 | opcode6 = 101110 72 | 73 | LW 74 | CONSTRAINT (instruction[15:14] == 2'b00) 75 | opcode6 = 100100 76 | opcode6 = 100011 77 | opcode6 = 100110 78 | opcode6 = 100101 79 | opcode6 = 100010 80 | opcode6 = 100001 81 | 82 | SW 83 | opcode6 = 110110 84 | opcode6 = 110111 85 | opcode6 = 110101 86 | 87 | _R 88 | ADD 89 | opcode6 = 111000 90 | opcode2 = 00 91 | opcode4 = 0000 92 | 93 | AND 94 | opcode6 = 111000 95 | opcode2 = 00 96 | opcode4 = 0011 97 | 98 | DIV 99 | opcode6 = 111000 100 | opcode2 = 11 101 | opcode4 = 1001 102 | 103 | DIVU 104 | opcode6 = 111000 105 | opcode2 = 11 106 | opcode4 = 1010 107 | 108 | FF1 109 | opcode6 = 111000 110 | opcode2 = 00 111 | opcode4 = 1111 112 | 113 | FL1 114 | opcode6 = 111000 115 | opcode2 = 01 116 | opcode4 = 1111 117 | 118 | MUL 119 | opcode6 = 111000 120 | opcode2 = 11 121 | opcode4 = 0110 122 | 123 | MULU 124 | opcode6 = 111000 125 | opcode2 = 11 126 | opcode4 = 1011 127 | 128 | OR 129 | opcode6 = 111000 130 | opcode2 = 00 131 | opcode4 = 0100 132 | 133 | ROR 134 | opcode6 = 111000 135 | opcode2 = 11 136 | opcode4 = 1000 137 | 138 | SUB 139 | opcode6 = 111000 140 | opcode2 = 00 141 | opcode4 = 0101 142 | 143 | XOR 144 | opcode6 = 111000 145 | opcode2 = 00 146 | opcode4 = 0101 147 | 148 | SLL 149 | opcode6 = 111000 150 | opcode4EXT = 0000 151 | opcode4 = 1000 152 | 153 | SRA 154 | opcode6 = 111000 155 | opcode4EXT = 0010 156 | opcode4 = 1000 157 | 158 | SRL 159 | opcode6 = 111000 160 | opcode4EXT = 0001 161 | opcode4 = 1000 162 | 163 | EXTBS 164 | opcode6 = 111000 165 | opcode4EXT = 0001 166 | opcode4 = 1100 167 | 168 | EXTBZ 169 | opcode6 = 111000 170 | opcode4EXT = 0011 171 | opcode4 = 1100 172 | 173 | EXTHS 174 | opcode6 = 111000 175 | opcode4EXT = 0000 176 | opcode4 = 1100 177 | 178 | EXTHZ 179 | opcode6 = 111000 180 | opcode4EXT = 0010 181 | opcode4 = 1100 182 | 183 | EXTWS 184 | opcode6 = 111000 185 | opcode4EXT = 0000 186 | opcode4 = 1101 187 | 188 | EXTWZ 189 | opcode6 = 111000 190 | opcode4EXT = 0001 191 | opcode4 = 1101 192 | 193 | _I 194 | ADDI 195 | opcode6 = 100111 196 | 197 | ANDI 198 | opcode6 = 101001 199 | 200 | MULI 201 | opcode6 = 101100 202 | 203 | ORI 204 | opcode6 = 101010 205 | 206 | XORI 207 | opcode6 = 101011 208 | 209 | SLLI 210 | CONSTRAINT (instruction[7:6] == 2'b00) 211 | opcode6 = 101110 212 | 213 | SRAI 214 | CONSTRAINT (instruction[7:6] == 2'b10) 215 | opcode6 = 101110 216 | 217 | SRLI 218 | CONSTRAINT (instruction[7:6] == 2'b01) 219 | opcode6 = 101110 220 | 221 | _LW 222 | LBS 223 | CONSTRAINT (instruction[15:14] == 2'b00) 224 | opcode6 = 100100 225 | rA = 00000 226 | 227 | LBZ 228 | CONSTRAINT (instruction[15:14] == 2'b00) 229 | opcode6 = 100011 230 | rA = 00000 231 | 232 | LHS 233 | CONSTRAINT (instruction[15:14] == 2'b00) 234 | opcode6 = 100110 235 | rA = 00000 236 | 237 | LHZ 238 | CONSTRAINT (instruction[15:14] == 2'b00) 239 | opcode6 = 100101 240 | rA = 00000 241 | 242 | LWS 243 | CONSTRAINT (instruction[15:14] == 2'b00) 244 | opcode6 = 100010 245 | rA = 00000 246 | 247 | LWZ 248 | CONSTRAINT (instruction[15:14] == 2'b00) 249 | opcode6 = 100001 250 | rA = 00000 251 | 252 | _SW 253 | SB 254 | CONSTRAINT (instruction[25:24] == 2'b00) 255 | CONSTRAINT (rB < 16) 256 | opcode6 = 110110 257 | rA = 00000 258 | 259 | SH 260 | CONSTRAINT (instruction[25:24] == 2'b00) 261 | CONSTRAINT (rB < 16) 262 | opcode6 = 110111 263 | rA = 00000 264 | 265 | SW 266 | CONSTRAINT (instruction[25:24] == 2'b00) 267 | CONSTRAINT (rB < 16) 268 | opcode6 = 110101 269 | rA = 00000 270 | 271 | _FP 272 | CONSTRAINT (opcode6 == 6'b110010) 273 | 274 | FADD 275 | opcodeFP = 00000000 276 | 277 | FDIV 278 | opcodeFP = 00000011 279 | 280 | FTOI 281 | opcodeFP = 00000101 282 | rB = 00000 283 | 284 | ITOF 285 | opcodeFP = 00000100 286 | rB = 00000 287 | 288 | FMUL 289 | opcodeFP = 00000010 290 | 291 | FREM 292 | opcodeFP = 00000110 293 | 294 | FSUB 295 | opcodeFP = 00000001 296 | 297 | _NOP 298 | NOP 299 | CONSTRAINT (instruction == {8'b00010101, 24'd0}) 300 | 301 | 302 | 303 | 304 | -------------------------------------------------------------------------------- /SQED-Generator/FormatFiles/RV32M-ridecore_format.txt: -------------------------------------------------------------------------------- 1 | # You can use python style comments with (#) 2 | # to add notes, or comment out lines. 3 | 4 | # Copyright (c) Stanford University 5 | # 6 | # This source code is patent protected and being made available under the 7 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 8 | 9 | # Author: Mario J Srouji 10 | # Email: msrouji@stanford.edu 11 | 12 | SECTIONS = SIC ISA QEDCONSTRAINTS REGISTERS MEMORY BITFIELDS INSTYPES INSFIELDS INSREQS R I LW SW NOP 13 | 14 | _SIC 15 | MODULENAME 16 | inst_constraint0 = NULL 17 | 18 | COUNTER 19 | state_counter = 10 20 | 21 | RESET 22 | reset_x = 1 23 | 24 | REGFILE 25 | pipe.aregfile.regfile.mem = NULL 26 | 27 | MEMORY 28 | datamemory.mem = NULL 29 | 30 | DESTINATIONREG 31 | rd_copy = 5 32 | 33 | IMMEDIATE 34 | imm_copy = 5 35 | 36 | REGVALUE 37 | val1 = 5 38 | val2 = 5 39 | 40 | DELAY 41 | LW = 1 42 | SW = 2 43 | 44 | GENERAL 45 | model_files = ridecore.vlist[top] 46 | model_files = init.ssts 47 | model_files = nop_m.ssts 48 | model_files = state_copy.ssts 49 | abstract_clock = True 50 | vcd = True 51 | no_arrays = False 52 | default_initial_value = 0 53 | 54 | DEFAULT 55 | solver_name = btor 56 | prove = False 57 | 58 | CHECK 59 | description = "Check for Single Instruction" 60 | verification = safety 61 | bmc_length = 8 62 | 63 | ASSUMPTIONS 64 | CONSTRAINT R,I,LW,SW,(rd != 0_5) 65 | 66 | #PROPERTIES 67 | 68 | _ISA 69 | num_registers = 32 70 | instruction_length = 32 71 | pipeline_depth = 6 72 | active_low = 1 73 | 74 | _QEDCONSTRAINTS 75 | # Divides register space in half for duplicate instructions 76 | half_registers = 1 77 | # Divides memory in half and uses unsigned addresses 78 | half_memory = 1 79 | 80 | # Defines which fields are registers for 81 | # both the constraints, and modify file 82 | _REGISTERS 83 | rd 84 | rs1 85 | rs2 86 | 87 | # Defines the memory fields to be modified in the 88 | # modify file 89 | _MEMORY 90 | imm12 91 | imm7 92 | 93 | _BITFIELDS 94 | funct7 = 31 25 95 | funct3 = 14 12 96 | rd = 11 7 97 | rs1 = 19 15 98 | rs2 = 24 20 99 | opcode = 6 0 100 | shamt = 24 20 101 | imm12 = 31 20 102 | imm7 = 31 25 103 | imm5 = 11 7 104 | 105 | # Putting constraints here affects 106 | # the modify file to define the memory 107 | # instructions 108 | _INSTYPES 109 | CONSTRAINT MEMORYTYPE,LW,SW 110 | CONSTRAINT IMMEDIATETYPE,I 111 | CONSTRAINT REGISTERTYPE,R 112 | CONSTRAINT NOPTYPE,NOP 113 | 114 | R 115 | I 116 | LW 117 | SW 118 | NOP 119 | 120 | _INSFIELDS 121 | R = funct7 rs2 rs1 funct3 rd opcode 122 | I = imm12 rs1 funct3 rd opcode 123 | LW = imm12 rs1 funct3 rd opcode 124 | SW = imm7 rs2 rs1 funct3 imm5 opcode 125 | NOP = imm12 rs1 funct3 rd opcode 126 | 127 | # Putting constraints here affects the 128 | # decoder file 129 | _INSREQS 130 | R 131 | # Put the constraints here for each 132 | # instruction type so that they are added 133 | # into the decoder file as part of 134 | # the IS_ins decoding process 135 | opcode = 0110011 136 | 137 | I 138 | opcode = 0010011 139 | 140 | LW 141 | opcode = 0000011 142 | funct3 = 010 143 | 144 | SW 145 | opcode = 0100011 146 | funct3 = 010 147 | 148 | # Adding constraints 149 | # in the instruction types 150 | # below affects the constraints file output 151 | _R 152 | # Adding a constraint here puts it as an 153 | # instruction or "format" type constraint 154 | 155 | ADD 156 | # Putting a constraint here puts it 157 | # as a constraint for the specific instruction 158 | # in the constraints file 159 | funct3 = 000 160 | funct7 = 0000000 161 | opcode = 0110011 162 | 163 | SUB 164 | funct3 = 000 165 | funct7 = 0100000 166 | opcode = 0110011 167 | 168 | SLL 169 | funct3 = 001 170 | funct7 = 0000000 171 | opcode = 0110011 172 | 173 | SLT 174 | funct3 = 010 175 | funct7 = 0000000 176 | opcode = 0110011 177 | 178 | SLTU 179 | funct3 = 011 180 | funct7 = 0000000 181 | opcode = 0110011 182 | 183 | XOR 184 | funct3 = 100 185 | funct7 = 0000000 186 | opcode = 0110011 187 | 188 | SRL 189 | funct3 = 101 190 | funct7 = 0000000 191 | opcode = 0110011 192 | 193 | SRA 194 | funct3 = 101 195 | funct7 = 0100000 196 | opcode = 0110011 197 | 198 | OR 199 | funct3 = 110 200 | funct7 = 0000000 201 | opcode = 0110011 202 | 203 | AND 204 | funct3 = 111 205 | funct7 = 0000000 206 | opcode = 0110011 207 | 208 | MUL 209 | funct3 = 000 210 | funct7 = 0000001 211 | opcode = 0110011 212 | 213 | MULH 214 | funct3 = 001 215 | funct7 = 0000001 216 | opcode = 0110011 217 | 218 | MULHSU 219 | funct3 = 010 220 | funct7 = 0000001 221 | opcode = 0110011 222 | 223 | MULHU 224 | funct3 = 011 225 | funct7 = 0000001 226 | opcode = 0110011 227 | 228 | _I 229 | ADDI 230 | funct3 = 000 231 | opcode = 0010011 232 | 233 | SLTI 234 | funct3 = 010 235 | opcode = 0010011 236 | 237 | SLTIU 238 | funct3 = 011 239 | opcode = 0010011 240 | 241 | XORI 242 | funct3 = 100 243 | opcode = 0010011 244 | 245 | ORI 246 | funct3 = 110 247 | opcode = 0010011 248 | 249 | ANDI 250 | funct3 = 111 251 | opcode = 0010011 252 | 253 | SLLI 254 | funct3 = 001 255 | funct7 = 0000000 256 | opcode = 0010011 257 | 258 | SRLI 259 | funct3 = 101 260 | funct7 = 0000000 261 | opcode = 0010011 262 | 263 | SRAI 264 | funct3 = 101 265 | funct7 = 0100000 266 | opcode = 0010011 267 | 268 | _LW 269 | CONSTRAINT (instruction[31:30] == 00) 270 | 271 | LW 272 | rs1 = 00000 273 | opcode = 0000011 274 | funct3 = 010 275 | 276 | _SW 277 | CONSTRAINT (instruction[31:30] == 00) 278 | 279 | SW 280 | rs1 = 00000 281 | opcode = 0100011 282 | funct3 = 010 283 | 284 | _NOP 285 | NOP 286 | opcode = 1111111 287 | 288 | 289 | 290 | 291 | -------------------------------------------------------------------------------- /qed-wireup-patches/step0-pipeline-changes.patch: -------------------------------------------------------------------------------- 1 | *************** 2 | *** 6,11 **** 3 | --- 6,12 ---- 4 | 5 | module pipeline 6 | ( 7 | + input wire [`INSN_LEN-1:0] inst1, 8 | input wire clk, 9 | input wire reset, 10 | output reg [`ADDR_LEN-1:0] pc, 11 | *************** 12 | *** 27,33 **** 13 | // Signal from pipe_if 14 | wire prcond; 15 | wire [`ADDR_LEN-1:0] npc; 16 | ! wire [`INSN_LEN-1:0] inst1; 17 | wire [`INSN_LEN-1:0] inst2; 18 | wire invalid2_pipe; 19 | wire [`GSH_BHR_LEN-1:0] bhr; 20 | --- 28,35 ---- 21 | // Signal from pipe_if 22 | wire prcond; 23 | wire [`ADDR_LEN-1:0] npc; 24 | ! // EDIT: Make inst1 an input 25 | ! // wire [`INSN_LEN-1:0] inst1; 26 | wire [`INSN_LEN-1:0] inst2; 27 | wire invalid2_pipe; 28 | wire [`GSH_BHR_LEN-1:0] bhr; 29 | *************** 30 | *** 43,48 **** 31 | --- 45,70 ---- 32 | reg bhr_if; 33 | wire attachable; 34 | 35 | + // EDIT- add in the QED module. 36 | + 37 | + wire qed_vld_out; 38 | + (* keep *) 39 | + wire qed_exec_dup; 40 | + wire [31:0] qed_ifu_instruction; 41 | + 42 | + // instruction1 and qed_exec_dup are cutpoints 43 | + qed qed0 ( // Inputs 44 | + .clk(clk), 45 | + .rst(reset), 46 | + .ena(1'b1), 47 | + .ifu_qed_instruction(inst1), 48 | + .exec_dup(qed_exec_dup), 49 | + .stall_IF(stall_IF), 50 | + // outputs 51 | + .qed_ifu_instruction(qed_ifu_instruction), 52 | + .vld_out(qed_vld_out)); 53 | + 54 | + // EDIT 55 | //ID 56 | //Decode Info1 57 | wire [`IMM_TYPE_WIDTH-1:0] imm_type_1; 58 | *************** 59 | *** 490,503 **** 60 | end 61 | end 62 | 63 | ! 64 | pipeline_if pipe_if( 65 | .clk(clk), 66 | .reset(reset), 67 | .pc(pc), 68 | .predict_cond(prcond), 69 | .npc(npc), 70 | ! .inst1(inst1), 71 | .inst2(inst2), 72 | .invalid2(invalid2_pipe), 73 | .btbpht_we(combranch), 74 | --- 512,528 ---- 75 | end 76 | end 77 | 78 | ! // EDIT: manually cut inst1, want to drive this from the top-level 79 | ! // we don't need to include the instruction fetch 80 | ! wire [`INSN_LEN-1:0] cut_inst1; 81 | ! 82 | pipeline_if pipe_if( 83 | .clk(clk), 84 | .reset(reset), 85 | .pc(pc), 86 | .predict_cond(prcond), 87 | .npc(npc), 88 | ! .inst1(cut_inst1), 89 | .inst2(inst2), 90 | .invalid2(invalid2_pipe), 91 | .btbpht_we(combranch), 92 | *************** 93 | *** 529,538 **** 94 | prcond_if <= prcond; 95 | npc_if <= npc; 96 | pc_if <= pc; 97 | ! inst1_if <= inst1; 98 | inst2_if <= inst2; 99 | ! inv1_if <= 0; 100 | inv2_if <= invalid2_pipe; 101 | bhr_if <= bhr; 102 | 103 | end 104 | --- 554,567 ---- 105 | prcond_if <= prcond; 106 | npc_if <= npc; 107 | pc_if <= pc; 108 | ! // EDIT: send the output of the QED module through the pipeline. 109 | ! //inst1_if <= inst1; 110 | ! inst1_if <= qed_ifu_instruction; 111 | inst2_if <= inst2; 112 | ! //inv1_if <= 0; 113 | ! inv1_if <= ~qed_vld_out; // change to vld_out of qed0 114 | inv2_if <= invalid2_pipe; 115 | + // EDIT END 116 | bhr_if <= bhr; 117 | 118 | end 119 | *************** 120 | *** 1925,1931 **** 121 | .rrf_freenum(freenum), 122 | .prmiss(prmiss) 123 | ); 124 | ! 125 | endmodule // pipeline 126 | 127 | `default_nettype wire 128 | --- 1954,2002 ---- 129 | .rrf_freenum(freenum), 130 | .prmiss(prmiss) 131 | ); 132 | ! 133 | ! // EDIT: Insert the qed ready logic -- tracks number of committed instructions 134 | ! (* keep *) 135 | ! wire qed_ready; 136 | ! (* keep *) 137 | ! reg [15:0] num_orig_insts; 138 | ! (* keep *) 139 | ! reg [15:0] num_dup_insts; 140 | ! wire [1:0] num_orig_commits; 141 | ! wire [1:0] num_dup_commits; 142 | ! 143 | ! // Instruction with destination register as 5'b0 is a NOP so ignore those 144 | ! assign num_orig_commits = ((arfwe1 == 1)&&(dstarf1 < 16)&&(dstarf1 != 5'b0) 145 | ! &&(arfwe2 == 1)&&(dstarf2 < 16)&&(dstarf2 != 5'b0)) ? 2'b10 : 146 | ! ((((arfwe1 == 1)&&(dstarf1 < 16)&&(dstarf1 != 5'b0) 147 | ! &&((arfwe2 != 1)||(dstarf2 >= 16)||(dstarf2 == 5'b0))) 148 | ! ||((arfwe2 == 1)&&(dstarf2 < 16)&&(dstarf2 != 5'b0) 149 | ! &&((arfwe1 != 1)||(dstarf1 >= 16)||(dstarf1 == 5'b0)))) ? 2'b01 : 2'b00) ; 150 | ! 151 | ! 152 | ! // When destination register is 5'b0, it remains the same for both original and duplicate 153 | ! assign num_dup_commits = ((arfwe1 == 1)&&(dstarf1 >= 16) 154 | ! &&(arfwe2 == 1)&&(dstarf2 >= 16)) ? 2'b10 : 155 | ! ((((arfwe1 == 1)&&(dstarf1 >= 16) 156 | ! &&((arfwe2 != 1)||(dstarf2 < 16))) 157 | ! ||((arfwe2 == 1)&&(dstarf2 >= 16) 158 | ! &&((arfwe1 != 1)||(dstarf1 < 16)))) ? 2'b01 : 2'b00) ; 159 | ! 160 | ! always @(posedge clk) 161 | ! begin 162 | ! if (reset) begin 163 | ! num_orig_insts <= 16'b0; 164 | ! num_dup_insts <= 16'b0; 165 | ! end else begin 166 | ! num_orig_insts <= num_orig_insts + {14'b0,num_orig_commits}; 167 | ! num_dup_insts <= num_dup_insts + {14'b0,num_dup_commits}; 168 | ! end 169 | ! end 170 | ! 171 | ! assign qed_ready = (num_orig_insts == num_dup_insts); 172 | ! 173 | ! // EDIT END 174 | ! 175 | endmodule // pipeline 176 | 177 | `default_nettype wire 178 | -------------------------------------------------------------------------------- /ridecore-src-buggy/reorderbuf.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module reorderbuf 4 | ( 5 | input wire clk, 6 | input wire reset, 7 | //Write Signal 8 | input wire dp1, 9 | input wire [`RRF_SEL-1:0] dp1_addr, 10 | input wire [`INSN_LEN-1:0] pc_dp1, 11 | input wire storebit_dp1, 12 | input wire dstvalid_dp1, 13 | input wire [`REG_SEL-1:0] dst_dp1, 14 | input wire [`GSH_BHR_LEN-1:0] bhr_dp1, 15 | input wire isbranch_dp1, 16 | input wire dp2, 17 | input wire [`RRF_SEL-1:0] dp2_addr, 18 | input wire [`INSN_LEN-1:0] pc_dp2, 19 | input wire storebit_dp2, 20 | input wire dstvalid_dp2, 21 | input wire [`REG_SEL-1:0] dst_dp2, 22 | input wire [`GSH_BHR_LEN-1:0] bhr_dp2, 23 | input wire isbranch_dp2, 24 | input wire exfin_alu1, 25 | input wire [`RRF_SEL-1:0] exfin_alu1_addr, 26 | input wire exfin_alu2, 27 | input wire [`RRF_SEL-1:0] exfin_alu2_addr, 28 | input wire exfin_mul, 29 | input wire [`RRF_SEL-1:0] exfin_mul_addr, 30 | input wire exfin_ldst, 31 | input wire [`RRF_SEL-1:0] exfin_ldst_addr, 32 | input wire exfin_branch, 33 | input wire [`RRF_SEL-1:0] exfin_branch_addr, 34 | input wire exfin_branch_brcond, 35 | input wire [`ADDR_LEN-1:0] exfin_branch_jmpaddr, 36 | 37 | output reg [`RRF_SEL-1:0] comptr, 38 | output wire [`RRF_SEL-1:0] comptr2, 39 | output wire [1:0] comnum, 40 | output wire stcommit, 41 | output wire arfwe1, 42 | output wire arfwe2, 43 | output wire [`REG_SEL-1:0] dstarf1, 44 | output wire [`REG_SEL-1:0] dstarf2, 45 | output wire [`ADDR_LEN-1:0] pc_combranch, 46 | output wire [`GSH_BHR_LEN-1:0] bhr_combranch, 47 | output wire brcond_combranch, 48 | output wire [`ADDR_LEN-1:0] jmpaddr_combranch, 49 | output wire combranch, 50 | input wire [`RRF_SEL-1:0] dispatchptr, 51 | input wire [`RRF_SEL:0] rrf_freenum, 52 | input wire prmiss 53 | ); 54 | 55 | reg [`RRF_NUM-1:0] finish; 56 | reg [`RRF_NUM-1:0] storebit; 57 | reg [`RRF_NUM-1:0] dstvalid; 58 | reg [`RRF_NUM-1:0] brcond; 59 | reg [`RRF_NUM-1:0] isbranch; 60 | 61 | reg [`ADDR_LEN-1:0] inst_pc [0:`RRF_NUM-1]; 62 | reg [`ADDR_LEN-1:0] jmpaddr [0:`RRF_NUM-1]; 63 | reg [`REG_SEL-1:0] dst [0:`RRF_NUM-1]; 64 | reg [`GSH_BHR_LEN-1:0] bhr [0:`RRF_NUM-1]; 65 | 66 | assign comptr2 = comptr+1; 67 | 68 | wire hidp = (comptr > dispatchptr) || (rrf_freenum == 0) ? 69 | 1'b1 : 1'b0; 70 | wire com_en1 = ({hidp, dispatchptr} - {1'b0, comptr}) > 0 ? 1'b1 : 1'b0; 71 | wire com_en2 = ({hidp, dispatchptr} - {1'b0, comptr}) > 1 ? 1'b1 : 1'b0; 72 | wire commit1 = com_en1 & finish[comptr]; 73 | // wire commit2 = commit1 & com_en2 & finish[comptr2]; 74 | 75 | wire commit2 = 76 | ~(~prmiss & commit1 & isbranch[comptr]) & 77 | ~(commit1 & storebit[comptr] & ~prmiss) & 78 | commit1 & com_en2 & finish[comptr2]; 79 | 80 | assign comnum = {1'b0, commit1} + {1'b0, commit2}; 81 | assign stcommit = (commit1 & storebit[comptr] & ~prmiss) | 82 | (commit2 & storebit[comptr2] & ~prmiss); 83 | assign arfwe1 = ~prmiss & commit1 & dstvalid[comptr]; 84 | assign arfwe2 = ~prmiss & commit2 & dstvalid[comptr2]; 85 | assign dstarf1 = dst[comptr]; 86 | assign dstarf2 = dst[comptr2]; 87 | assign combranch = (~prmiss & commit1 & isbranch[comptr]) | 88 | (~prmiss & commit2 & isbranch[comptr2]); 89 | assign pc_combranch = (~prmiss & commit1 & isbranch[comptr]) ? 90 | inst_pc[comptr] : inst_pc[comptr2]; 91 | assign bhr_combranch = (~prmiss & commit1 & isbranch[comptr]) ? 92 | bhr[comptr] : bhr[comptr2]; 93 | assign brcond_combranch = (~prmiss & commit1 & isbranch[comptr]) ? 94 | brcond[comptr] : brcond[comptr2]; 95 | assign jmpaddr_combranch = (~prmiss & commit1 & isbranch[comptr]) ? 96 | jmpaddr[comptr] : jmpaddr[comptr2]; 97 | 98 | 99 | always @ (posedge clk) begin 100 | if (reset) begin 101 | comptr <= 0; 102 | end else if (~prmiss) begin 103 | comptr <= comptr + commit1 + commit2; 104 | end 105 | end 106 | 107 | always @ (posedge clk) begin 108 | if (reset) begin 109 | finish <= 0; 110 | brcond <= 0; 111 | end else begin 112 | if (dp1) 113 | finish[dp1_addr] <= 1'b0; 114 | if (dp2) 115 | finish[dp2_addr] <= 1'b0; 116 | if (exfin_alu1) 117 | finish[exfin_alu1_addr] <= 1'b1; 118 | if (exfin_alu2) 119 | finish[exfin_alu2_addr] <= 1'b1; 120 | if (exfin_mul) 121 | finish[exfin_mul_addr] <= 1'b1; 122 | if (exfin_ldst) 123 | finish[exfin_ldst_addr] <= 1'b1; 124 | if (exfin_branch) begin 125 | finish[exfin_branch_addr] <= 1'b1; 126 | brcond[exfin_branch_addr] <= exfin_branch_brcond; 127 | jmpaddr[exfin_branch_addr] <= exfin_branch_jmpaddr; 128 | end 129 | end 130 | end // always @ (posedge clk) 131 | 132 | always @ (posedge clk) begin 133 | if (dp1) begin 134 | isbranch[dp1_addr] <= isbranch_dp1; 135 | storebit[dp1_addr] <= storebit_dp1; 136 | dstvalid[dp1_addr] <= dstvalid_dp1; 137 | dst[dp1_addr] <= dst_dp1; 138 | bhr[dp1_addr] <= bhr_dp1; 139 | inst_pc[dp1_addr] <= pc_dp1; 140 | end 141 | if (dp2) begin 142 | isbranch[dp2_addr] <= isbranch_dp2; 143 | storebit[dp2_addr] <= storebit_dp2; 144 | dstvalid[dp2_addr] <= dstvalid_dp2; 145 | dst[dp2_addr] <= dst_dp2; 146 | bhr[dp2_addr] <= bhr_dp2; 147 | inst_pc[dp2_addr] <= pc_dp2; 148 | end 149 | end 150 | endmodule // reorderbuf 151 | `default_nettype wire 152 | -------------------------------------------------------------------------------- /SQED-Generator/FormatParsers/format_parser.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) Stanford University 2 | # 3 | # This source code is patent protected and being made available under the 4 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | # Author: Mario J Srouji 7 | # Email: msrouji@stanford.edu 8 | 9 | def constraint(line): 10 | return line.find("CONSTRAINT") != -1 11 | 12 | def comment(line): 13 | return line.find("#") != -1 14 | 15 | def definition(line): 16 | return line.find("=") != -1 17 | 18 | def field(line): 19 | return line[0] == "_" 20 | 21 | # Main function for parsing data related to a specific section 22 | def get_info(lines): 23 | info = {} 24 | inner_info = {} 25 | constraints = [] 26 | name = None 27 | 28 | # Skip lines 29 | while (comment(lines[0]) or lines[0] == "\n"): 30 | lines = lines[1:] 31 | 32 | while constraint(lines[0]): 33 | line = lines[0] 34 | constraints.append(line[len("CONSTRAINT")+1:-1]) 35 | lines = lines[1:] 36 | 37 | if len(constraints) > 0: 38 | info["CONSTRAINT"] = constraints 39 | constraints = [] 40 | 41 | while (len(lines) > 0 and not field(lines[0])): 42 | line = lines[0] 43 | 44 | if (comment(line) or line == "\n"): 45 | lines = lines[1:] 46 | 47 | elif constraint(line): 48 | constraints.append(line[len("CONSTRAINT")+1:-1]) 49 | lines = lines[1:] 50 | 51 | elif definition(line): 52 | req = line 53 | req_index = req.find("=") 54 | req_name = req[0:req_index-1] 55 | req = req[req_index+2:-1] 56 | if req_name in inner_info: 57 | if type(inner_info[req_name]) == type([]): 58 | inner_info[req_name].append(req) 59 | else: 60 | inner_info[req_name] = [inner_info[req_name], req] 61 | else: 62 | inner_info[req_name] = req 63 | lines = lines[1:] 64 | 65 | else: 66 | if not name is None: 67 | inner_info["CONSTRAINT"] = constraints 68 | info[name] = inner_info 69 | name = line 70 | name = name[0:-1] 71 | inner_info = {} 72 | constraints = [] 73 | lines = lines[1:] 74 | 75 | if not name is None: 76 | inner_info["CONSTRAINT"] = constraints 77 | info[name] = inner_info 78 | if not "CONSTRAINT" in info: 79 | info["CONSTRAINT"] = [] 80 | return info, lines 81 | else: 82 | inner_info["CONSTRAINT"] = constraints 83 | return inner_info, lines 84 | 85 | # Main parsing function 86 | def parse_format(filename): 87 | error = False 88 | try: 89 | # Read in all lines in format file 90 | f = open(filename, 'r') 91 | lines = f.readlines() 92 | except: 93 | print("ERROR: Could not open format file") 94 | error = True 95 | quit() 96 | 97 | try: 98 | # First field in file must define all sections in file 99 | while (comment(lines[0]) or (lines[0] == "\n") or lines[0].find("SECTIONS") == -1): 100 | lines = lines[1:] 101 | format_sections = lines[0] 102 | sections_index = format_sections.find("=") 103 | format_sections = format_sections[sections_index+2:] 104 | format_sections = format_sections.split() 105 | except: 106 | if len(lines) == 0: 107 | print("ERROR: Could not find SECTIONS in Format File") 108 | else: 109 | print("ERROR: Issue in parsing SECTIONS in format file") 110 | error = True 111 | quit() 112 | 113 | format_dicts = {} 114 | 115 | # go through each section in the format file 116 | # and gather the data by section name 117 | i = 0 118 | lines = lines[1:] 119 | while len(lines) > 0: 120 | line = lines[0] 121 | if (comment(line) or line == "\n"): 122 | lines = lines[1:] 123 | elif field(line): 124 | try: 125 | format_name = format_sections[i] 126 | if not line[1:-1] in format_name: 127 | print("CHECK: SECTIONS field "+format_name+" and actual section "+line[1:-1]+" not aligned.") 128 | print("Please make sure to include "+line[1:-1]+" section in SECTIONS.") 129 | raise Exception() 130 | except: 131 | print("ERROR: Please make sure to list all format file sections in SECTIONS") 132 | error = True 133 | quit() 134 | try : 135 | format_dicts[format_name], lines = get_info(lines[1:]) 136 | except: 137 | print("ERROR: Issue while parsing the following section: "+line[1:-1]) 138 | error = True 139 | quit() 140 | 141 | i += 1 142 | else: 143 | print("CHECK: Skipping a line that is not a comment but is in between sections") 144 | error = True 145 | lines = lines[1:] 146 | 147 | f.close() 148 | 149 | if error: 150 | print("MESSAGE: Parser encountered weird lines that were skipped.") 151 | else: 152 | print("MESSAGE: Format File was read in without any issues.") 153 | return format_sections, format_dicts 154 | 155 | # Helps in debugging and viewing 156 | # what the parser is outputting, 157 | # and how it structures the data 158 | def parser_display(f): 159 | sections, info = parse_format(f) 160 | print(sections) 161 | print("\n") 162 | for key in info: 163 | print(key) 164 | print(info[key]) 165 | print("\n") 166 | 167 | #parser_display("../FormatFiles/RV32M-ridecore_format.txt") 168 | 169 | -------------------------------------------------------------------------------- /ridecore-src-buggy/system.v: -------------------------------------------------------------------------------- 1 | /**************************************************************************************************/ 2 | /* Many-core processor project Arch Lab. TOKYO TECH */ 3 | /**************************************************************************************************/ 4 | `default_nettype none 5 | /**************************************************************************************************/ 6 | `include "define.v" 7 | /**************************************************************************************************/ 8 | 9 | module CLKGEN_DCM(CLK_IN, CLK_OUT, LOCKED); 10 | input wire CLK_IN; 11 | output wire CLK_OUT, LOCKED; 12 | 13 | wire clk_ibuf; 14 | wire clk_out; 15 | wire clk0, clk0_fbuf; 16 | 17 | // input buffer 18 | IBUFG ibuf (.I(CLK_IN), 19 | .O(clk_ibuf)); 20 | // output buffer 21 | BUFG obuf (.I(clk_out), 22 | .O(CLK_OUT)); 23 | // feedback buffer 24 | BUFG fbuf (.I(clk0), 25 | .O(clk0_fbuf)); 26 | 27 | // dcm instantiation 28 | DCM_SP dcm (// input 29 | .CLKIN (clk_ibuf), 30 | .RST (1'b0), 31 | // output 32 | .CLKFX (clk_out), 33 | .LOCKED (LOCKED), 34 | // feedback 35 | .CLK0 (clk0), 36 | .CLKFB (clk0_fbuf), 37 | // phase shift 38 | .PSEN (1'b0), 39 | .PSINCDEC(1'b0), 40 | .PSCLK (1'b0), 41 | // digital spread spectrum 42 | .DSSEN (1'b0)); 43 | 44 | defparam dcm.CLKIN_PERIOD = `DCM_CLKIN_PERIOD; 45 | defparam dcm.CLKFX_MULTIPLY = `DCM_CLKFX_MULTIPLY; 46 | defparam dcm.CLKFX_DIVIDE = `DCM_CLKFX_DIVIDE; 47 | endmodule 48 | 49 | /**************************************************************************************************/ 50 | 51 | module CLKGEN_MMCM(CLK_IN, CLK_OUT, LOCKED); 52 | input wire CLK_IN; 53 | output wire CLK_OUT, LOCKED; 54 | 55 | wire clk_out; 56 | wire clkfb, clkfb_fbuf; 57 | 58 | // output buffer 59 | BUFG obuf (.I(clk_out), 60 | .O(CLK_OUT)); 61 | // feedback buffer 62 | BUFG fbuf (.I(clkfb), 63 | .O(clkfb_fbuf)); 64 | 65 | MMCME2_ADV mmcm (// input 66 | .CLKIN1 (CLK_IN), 67 | .CLKIN2 (1'b0), 68 | .CLKINSEL (1'b1), 69 | .RST (1'b0), 70 | .PWRDWN (1'b0), 71 | // output 72 | .CLKOUT0 (clk_out), 73 | .CLKOUT0B (), 74 | .CLKOUT1 (), 75 | .CLKOUT1B (), 76 | .CLKOUT2 (), 77 | .CLKOUT2B (), 78 | .CLKOUT3 (), 79 | .CLKOUT3B (), 80 | .CLKOUT4 (), 81 | .CLKOUT5 (), 82 | .CLKOUT6 (), 83 | .LOCKED (LOCKED), 84 | // feedback 85 | .CLKFBOUT (clkfb), 86 | .CLKFBIN (clkfb_fbuf), 87 | .CLKFBOUTB (), 88 | // dynamic reconfiguration 89 | .DADDR (7'h0), 90 | .DI (16'h0), 91 | .DWE (1'b0), 92 | .DEN (1'b0), 93 | .DCLK (1'b0), 94 | .DO (), 95 | .DRDY (), 96 | // phase shift 97 | .PSCLK (1'b0), 98 | .PSEN (1'b0), 99 | .PSINCDEC (1'b0), 100 | .PSDONE (), 101 | // status 102 | .CLKINSTOPPED (), 103 | .CLKFBSTOPPED ()); 104 | 105 | defparam mmcm.CLKIN1_PERIOD = `MMCM_CLKIN1_PERIOD; 106 | defparam mmcm.CLKFBOUT_MULT_F = `MMCM_VCO_MULTIPLY; 107 | defparam mmcm.DIVCLK_DIVIDE = `MMCM_VCO_DIVIDE; 108 | defparam mmcm.CLKOUT0_DIVIDE_F = `MMCM_CLKOUT0_DIVIDE; 109 | defparam mmcm.CLKOUT1_DIVIDE = `MMCM_CLKOUT1_DIVIDE; 110 | endmodule 111 | 112 | /**************************************************************************************************/ 113 | 114 | module RSTGEN(CLK, RST_X_I, RST_X_O); 115 | input wire CLK, RST_X_I; 116 | output wire RST_X_O; 117 | 118 | reg [7:0] cnt; 119 | assign RST_X_O = cnt[7]; 120 | 121 | always @(posedge CLK or negedge RST_X_I) begin 122 | if (!RST_X_I) cnt <= 0; 123 | else if (~RST_X_O) cnt <= (cnt + 1'b1); 124 | end 125 | endmodule 126 | 127 | /**************************************************************************************************/ 128 | 129 | module GEN_DCM(CLK_I, RST_X_I, CLK_O, RST_X_O); 130 | input wire CLK_I, RST_X_I; 131 | output wire CLK_O, RST_X_O; 132 | 133 | wire LOCKED; 134 | 135 | CLKGEN_DCM clkgen(.CLK_IN (CLK_I), 136 | .CLK_OUT(CLK_O), 137 | .LOCKED (LOCKED)); 138 | RSTGEN rstgen(.CLK (CLK_O), 139 | .RST_X_I(RST_X_I & LOCKED), 140 | .RST_X_O(RST_X_O)); 141 | endmodule 142 | 143 | module GEN_MMCM(CLK_I, RST_X_I, CLK_O, RST_X_O); 144 | input wire CLK_I, RST_X_I; 145 | output wire CLK_O, RST_X_O; 146 | 147 | wire clk_ibuf; 148 | wire LOCKED; 149 | 150 | // input buffer 151 | IBUFG ibuf (.I(CLK_I), 152 | .O(clk_ibuf)); 153 | 154 | CLKGEN_MMCM clkgen(.CLK_IN (clk_ibuf), 155 | .CLK_OUT(CLK_O), 156 | .LOCKED (LOCKED)); 157 | RSTGEN rstgen(.CLK (CLK_O), 158 | .RST_X_I(RST_X_I & LOCKED), 159 | .RST_X_O(RST_X_O)); 160 | endmodule 161 | 162 | module GEN_MMCM_DS(CLK_P, CLK_N, RST_X_I, CLK_O, RST_X_O); 163 | input wire CLK_P, CLK_N, RST_X_I; 164 | output wire CLK_O, RST_X_O; 165 | 166 | wire clk_ibuf; 167 | wire LOCKED; 168 | 169 | // input buffer 170 | IBUFGDS ibuf (.I (CLK_P), 171 | .IB(CLK_N), 172 | .O (clk_ibuf)); 173 | 174 | CLKGEN_MMCM clkgen(.CLK_IN (clk_ibuf), 175 | .CLK_OUT(CLK_O), 176 | .LOCKED (LOCKED)); 177 | RSTGEN rstgen(.CLK (CLK_O), 178 | .RST_X_I(RST_X_I & LOCKED), 179 | .RST_X_O(RST_X_O)); 180 | endmodule 181 | 182 | /**************************************************************************************************/ 183 | `default_nettype wire 184 | /**************************************************************************************************/ 185 | -------------------------------------------------------------------------------- /SQED-Generator/Generators/generate_sqed.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) Stanford University 2 | # 3 | # This source code is patent protected and being made available under the 4 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | # Author: Mario J Srouji 7 | # Email: msrouji@stanford.edu 8 | 9 | import copy 10 | import os 11 | from shutil import copyfile 12 | import sys 13 | sys.path.append("../FormatParsers/") 14 | sys.path.append("../Interface/") 15 | 16 | import format_parser as P 17 | import module_interface as I 18 | 19 | # Format file 20 | try: 21 | INFILE = sys.argv[1] 22 | except: 23 | print("ERROR: Please provide the format file path as the first argument.") 24 | quit() 25 | # Output directory 26 | try: 27 | OUTFILE = sys.argv[2] 28 | if not os.path.isdir(OUTFILE): 29 | os.mkdir(OUTFILE) 30 | if OUTFILE[-1] != "/": 31 | OUTFILE = OUTFILE + "/" 32 | copyfile("../QEDFiles/qed_i_cache.v", OUTFILE+"qed_i_cache.v") 33 | copyfile("../QEDFiles/qed_instruction_mux.v", OUTFILE+"qed_instruction_mux.v") 34 | print("MESSAGE: Created directory "+OUTFILE+" and moved mux and cache files.") 35 | except: 36 | OUTFILE = "../QEDFiles/" 37 | print("MESSAGE: Using default directory QEDFiles as output directory.") 38 | # SIC COSA OPS 39 | try: 40 | OPSFILE = sys.argv[3] 41 | except: 42 | OPSFILE = None 43 | print("MESSAGE: SIC Cosa operator file was not provided. Omitting SIC generation.") 44 | 45 | # LICENSE file to be included as header for all generated files 46 | try: 47 | f = open("LICENSE.v", 'r') 48 | license_header = f.read() + "\n" 49 | f.close() 50 | except: 51 | print("MESSAGE: Unable to read LICENSE.v file, please include user license information.") 52 | quit() 53 | 54 | # Grabs all global ISA format information 55 | format_sections, format_dicts = P.parse_format(INFILE) 56 | 57 | # Currently, these are required for the SQED generators. 58 | needed_sections = ["ISA", "REGISTERS", "MEMORY", 59 | "QEDCONSTRAINTS", "INSTYPES", 60 | "INSFIELDS", "INSREQS", 61 | "BITFIELDS"] 62 | found_sections = [False]*len(needed_sections) 63 | 64 | try: 65 | # Get ISA information 66 | isa_info = format_dicts["ISA"] 67 | found_sections[0] = True 68 | # Get register names 69 | registers = format_dicts["REGISTERS"] 70 | found_sections[1] = True 71 | # Get memory fields needed for modification 72 | memory = format_dicts["MEMORY"] 73 | found_sections[2] = True 74 | # Get constraints for qed module setup 75 | qed_constraints = format_dicts["QEDCONSTRAINTS"] 76 | found_sections[3] = True 77 | # Get the instruction types 78 | ins_types = format_dicts["INSTYPES"] 79 | found_sections[4] = True 80 | # Get the instruction fields for each type 81 | ins_fields = format_dicts["INSFIELDS"] 82 | found_sections[5] = True 83 | # Get instruction types requirements 84 | ins_reqs = format_dicts["INSREQS"] 85 | found_sections[6] = True 86 | # Get the bit fields 87 | bit_fields = format_dicts["BITFIELDS"] 88 | found_sections[7] = True 89 | # Get all instruction types 90 | instructions = {} 91 | for ins in format_dicts["INSTYPES"].keys(): 92 | if ins != "CONSTRAINT": 93 | instructions[ins] = format_dicts[ins] 94 | except: 95 | not_found = found_sections.index(False) 96 | print("ERROR: Format file is missing necessary section: "+needed_sections[not_found]) 97 | quit() 98 | 99 | # SIC files 100 | if not OPSFILE is None: 101 | try: 102 | from SIC_generator import * 103 | generate_SIC_files(format_dicts, OPSFILE) 104 | print("MESSAGE: Generated and wrote single instruction check files.") 105 | except: 106 | print("ERROR: Unable to generate SIC files.") 107 | 108 | # Constraints file 109 | try: 110 | from constraint_generator import * 111 | MODULENAME = "inst_constraint" 112 | INPUTS = {"clk": 1, "instruction": int(isa_info["instruction_length"])} 113 | OUTPUTS = {} 114 | except: 115 | print("ERROR: Missing or non-integer instruction_length field in ISA section.") 116 | quit() 117 | 118 | try: 119 | verilog = generate_constraints_file(MODULENAME, INPUTS, OUTPUTS, format_dicts) 120 | except: 121 | print("ERROR: Unable to generate constraints file.") 122 | 123 | try: 124 | f = open(OUTFILE+"inst_constraints.v", 'w') 125 | f.write(license_header+verilog) 126 | f.close() 127 | print("MESSAGE: Generated and wrote constraints file.") 128 | except: 129 | print("ERROR: Unable to write constraints file.") 130 | 131 | # Decoder file 132 | from decoder_generator import * 133 | 134 | MODULENAME = "qed_decoder" 135 | INPUTS = {"ifu_qed_instruction": int(isa_info["instruction_length"])} 136 | OUTPUTS = {} 137 | 138 | try: 139 | verilog = generate_decoder_file(MODULENAME, INPUTS, OUTPUTS, format_dicts) 140 | except: 141 | print("ERROR: Unable to generate decoder file.") 142 | 143 | try: 144 | f = open(OUTFILE+"qed_decoder.v", 'w') 145 | f.write(license_header+verilog) 146 | f.close() 147 | print("MESSAGE: Generated and wrote decoder file.") 148 | except: 149 | print("ERROR: Unable to write decoder file.") 150 | 151 | # Modify file 152 | from modify_generator import * 153 | 154 | MODULENAME = "modify_instruction" 155 | INPUTS = {"qic_qimux_instruction": int(isa_info["instruction_length"])} 156 | OUTPUTS = {"qed_instruction": int(isa_info["instruction_length"])} 157 | 158 | try: 159 | verilog = generate_modify_file(MODULENAME, INPUTS, OUTPUTS, format_dicts) 160 | except: 161 | print("ERROR: Unable to generate modify file.") 162 | 163 | try: 164 | f = open(OUTFILE+"modify_instruction.v", 'w') 165 | f.write(license_header+verilog) 166 | f.close() 167 | print("MESSAGE: Generated and wrote modify file.") 168 | except: 169 | print("ERROR: Unable to write modify file.") 170 | 171 | # QED top file 172 | from qed_generator import * 173 | 174 | MODULENAME = "qed" 175 | INPUTS = {"clk": 1, "ifu_qed_instruction": int(isa_info["instruction_length"]), 176 | "rst": 1, "ena": 1, "exec_dup": 1, "stall_IF": 1} 177 | OUTPUTS = {"qed_ifu_instruction": int(isa_info["instruction_length"]), "vld_out": 1} 178 | 179 | try: 180 | verilog = generate_qed_file(MODULENAME, INPUTS, OUTPUTS, format_dicts) 181 | except: 182 | print("ERROR: Unable to generate modify file.") 183 | 184 | try: 185 | f = open(OUTFILE+"qed.v", 'w') 186 | f.write(license_header+verilog) 187 | f.close() 188 | print("MESSAGE: Generated and wrote top-level qed file.") 189 | except: 190 | print("ERROR: Unable to write top-level qed file.") 191 | 192 | 193 | 194 | -------------------------------------------------------------------------------- /ridecore-src-buggy/ram_sync_nolatch.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module ram_sync_nolatch_2r1w #( 4 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 5 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 6 | parameter DATA_DEPTH = 32 7 | ) 8 | ( 9 | input wire clk, 10 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 11 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 12 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 13 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 14 | input wire [BRAM_ADDR_WIDTH-1:0] waddr, 15 | input wire [BRAM_DATA_WIDTH-1:0] wdata, 16 | input wire we 17 | ); 18 | 19 | reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1]; 20 | 21 | integer i; 22 | 23 | assign rdata1 = mem[raddr1]; 24 | assign rdata2 = mem[raddr2]; 25 | 26 | always @ (posedge clk) begin 27 | if (we) 28 | mem[waddr] <= wdata; 29 | end 30 | endmodule // ram_sync_nolatch_2r1w 31 | 32 | module ram_sync_nolatch_2r2w #( 33 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 34 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 35 | parameter DATA_DEPTH = 32 36 | ) 37 | ( 38 | input wire clk, 39 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 40 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 41 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 42 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 43 | input wire [BRAM_ADDR_WIDTH-1:0] waddr1, 44 | input wire [BRAM_ADDR_WIDTH-1:0] waddr2, 45 | input wire [BRAM_DATA_WIDTH-1:0] wdata1, 46 | input wire [BRAM_DATA_WIDTH-1:0] wdata2, 47 | input wire we1, 48 | input wire we2 49 | ); 50 | 51 | reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1]; 52 | 53 | assign rdata1 = mem[raddr1]; 54 | assign rdata2 = mem[raddr2]; 55 | 56 | always @ (posedge clk) begin 57 | if (we1) 58 | mem[waddr1] <= wdata1; 59 | if (we2) 60 | mem[waddr2] <= wdata2; 61 | end 62 | endmodule // ram_sync_nolatch_2r2w 63 | 64 | /* 65 | module ram_sync_nolatch_4r1w( 66 | input wire clk, 67 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 68 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 69 | input wire [BRAM_ADDR_WIDTH-1:0] raddr3, 70 | input wire [BRAM_ADDR_WIDTH-1:0] raddr4, 71 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 72 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 73 | output wire [BRAM_DATA_WIDTH-1:0] rdata3, 74 | output wire [BRAM_DATA_WIDTH-1:0] rdata4, 75 | input wire [BRAM_ADDR_WIDTH-1:0] waddr, 76 | input wire [BRAM_DATA_WIDTH-1:0] wdata, 77 | input wire we 78 | ); 79 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN; 80 | parameter BRAM_DATA_WIDTH = `DATA_LEN; 81 | parameter DATA_DEPTH = 32; 82 | 83 | ram_sync_nolatch_2r1w 84 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 85 | mem0( 86 | .clk(clk), 87 | .raddr1(raddr1), 88 | .raddr2(raddr2), 89 | .rdata1(rdata1), 90 | .rdata2(rdata2), 91 | .waddr(waddr), 92 | .wdata(wdata), 93 | .we(we) 94 | ); 95 | 96 | ram_sync_nolatch_2r1w 97 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 98 | mem1( 99 | .clk(clk), 100 | .raddr1(raddr3), 101 | .raddr2(raddr4), 102 | .rdata1(rdata3), 103 | .rdata2(rdata4), 104 | .waddr(waddr), 105 | .wdata(wdata), 106 | .we(we) 107 | ); 108 | 109 | endmodule //ram_sync_nolatch_4r1w 110 | */ 111 | module ram_sync_nolatch_4r2w #( 112 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 113 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 114 | parameter DATA_DEPTH = 32 115 | ) 116 | ( 117 | input wire clk, 118 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 119 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 120 | input wire [BRAM_ADDR_WIDTH-1:0] raddr3, 121 | input wire [BRAM_ADDR_WIDTH-1:0] raddr4, 122 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 123 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 124 | output wire [BRAM_DATA_WIDTH-1:0] rdata3, 125 | output wire [BRAM_DATA_WIDTH-1:0] rdata4, 126 | input wire [BRAM_ADDR_WIDTH-1:0] waddr1, 127 | input wire [BRAM_ADDR_WIDTH-1:0] waddr2, 128 | input wire [BRAM_DATA_WIDTH-1:0] wdata1, 129 | input wire [BRAM_DATA_WIDTH-1:0] wdata2, 130 | input wire we1, 131 | input wire we2 132 | ); 133 | 134 | reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1]; 135 | 136 | assign rdata1 = mem[raddr1]; 137 | assign rdata2 = mem[raddr2]; 138 | assign rdata3 = mem[raddr3]; 139 | assign rdata4 = mem[raddr4]; 140 | 141 | always @ (posedge clk) begin 142 | if (we1) 143 | mem[waddr1] <= wdata1; 144 | if (we2) 145 | mem[waddr2] <= wdata2; 146 | end 147 | endmodule // ram_sync_nolatch_4r2w 148 | 149 | /* 150 | module ram_sync_nolatch_6r2w( 151 | input wire clk, 152 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 153 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 154 | input wire [BRAM_ADDR_WIDTH-1:0] raddr3, 155 | input wire [BRAM_ADDR_WIDTH-1:0] raddr4, 156 | input wire [BRAM_ADDR_WIDTH-1:0] raddr5, 157 | input wire [BRAM_ADDR_WIDTH-1:0] raddr6, 158 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 159 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 160 | output wire [BRAM_DATA_WIDTH-1:0] rdata3, 161 | output wire [BRAM_DATA_WIDTH-1:0] rdata4, 162 | output wire [BRAM_DATA_WIDTH-1:0] rdata5, 163 | output wire [BRAM_DATA_WIDTH-1:0] rdata6, 164 | input wire [BRAM_ADDR_WIDTH-1:0] waddr1, 165 | input wire [BRAM_ADDR_WIDTH-1:0] waddr2, 166 | input wire [BRAM_DATA_WIDTH-1:0] wdata1, 167 | input wire [BRAM_DATA_WIDTH-1:0] wdata2, 168 | input wire we1, 169 | input wire we2 170 | ); 171 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN; 172 | parameter BRAM_DATA_WIDTH = `DATA_LEN; 173 | parameter DATA_DEPTH = 32; 174 | 175 | ram_sync_nolatch_2r2w 176 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 177 | mem0( 178 | .clk(clk), 179 | .raddr1(raddr1), 180 | .raddr2(raddr2), 181 | .rdata1(rdata1), 182 | .rdata2(rdata2), 183 | .waddr1(waddr1), 184 | .waddr2(waddr2), 185 | .wdata1(wdata1), 186 | .wdata2(wdata2), 187 | .we1(we1), 188 | .we2(we2) 189 | ); 190 | 191 | ram_sync_nolatch_2r2w 192 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 193 | mem1( 194 | .clk(clk), 195 | .raddr1(raddr3), 196 | .raddr2(raddr4), 197 | .rdata1(rdata3), 198 | .rdata2(rdata4), 199 | .waddr1(waddr1), 200 | .waddr2(waddr2), 201 | .wdata1(wdata1), 202 | .wdata2(wdata2), 203 | .we1(we1), 204 | .we2(we2) 205 | ); 206 | 207 | ram_sync_nolatch_2r2w 208 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 209 | mem2( 210 | .clk(clk), 211 | .raddr1(raddr5), 212 | .raddr2(raddr6), 213 | .rdata1(rdata5), 214 | .rdata2(rdata6), 215 | .waddr1(waddr1), 216 | .waddr2(waddr2), 217 | .wdata1(wdata1), 218 | .wdata2(wdata2), 219 | .we1(we1), 220 | .we2(we2) 221 | ); 222 | 223 | endmodule // ram_sync_nolatch_6r2w 224 | */ 225 | `default_nettype wire 226 | -------------------------------------------------------------------------------- /SQED-Generator/Generators/constraint_generator.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) Stanford University 2 | # 3 | # This source code is patent protected and being made available under the 4 | # terms explained in the ../LICENSE-Academic and ../LICENSE-GOV files. 5 | 6 | # Author: Mario J Srouji 7 | # Email: msrouji@stanford.edu 8 | 9 | import copy 10 | import sys 11 | sys.path.append("../FormatParsers/") 12 | sys.path.append("../Interface/") 13 | 14 | import format_parser as P 15 | import module_interface as I 16 | 17 | def generate_constraints_file(MODULENAME, INPUTS, OUTPUTS, format_dicts): 18 | # Get ISA information 19 | isa_info = format_dicts["ISA"] 20 | # Get register names 21 | registers = format_dicts["REGISTERS"] 22 | # Get memory fields needed for modification 23 | memory = format_dicts["MEMORY"] 24 | # Get constraints for qed module setup 25 | qed_constraints = format_dicts["QEDCONSTRAINTS"] 26 | # Get the instruction types 27 | ins_types = format_dicts["INSTYPES"] 28 | # Get the instruction fields for each type 29 | ins_fields = format_dicts["INSFIELDS"] 30 | # Get instruction types requirements 31 | ins_reqs = format_dicts["INSREQS"] 32 | # Get the bit fields 33 | bit_fields = format_dicts["BITFIELDS"] 34 | # Get all instruction types 35 | instructions = {} 36 | for ins in format_dicts["INSTYPES"].keys(): 37 | if ins != "CONSTRAINT": 38 | instructions[ins] = format_dicts[ins] 39 | 40 | # Verilog file 41 | verilog = "" 42 | 43 | # Adds module header definition 44 | verilog += I.module_header(MODULENAME, INPUTS, OUTPUTS) 45 | verilog += I.newline(2) 46 | 47 | # Instantiate inputs 48 | for inp in INPUTS: 49 | verilog += I.signal_def(INPUTS[inp], "input", inp, num_spaces=2) 50 | verilog += I.newline(1) 51 | 52 | # Instantiate outputs 53 | for out in OUTPUTS: 54 | verilog += I.signal_def(OUTPUTS[out], "output", out, num_spaces=2) 55 | verilog += I.newline(1) 56 | 57 | # Instantiate bit fields 58 | verilog += I.newline(1) 59 | for bit_field in bit_fields: 60 | if bit_field != "CONSTRAINT": 61 | msb, lsb = bit_fields[bit_field].split() 62 | bits = int(msb) - int(lsb) + 1 63 | verilog += I.signal_def(bits, "wire", bit_field, num_spaces=2) 64 | verilog += I.newline(1) 65 | 66 | # Instantiate instructions 67 | verilog += I.newline(1) 68 | for ins_type in instructions: 69 | if ins_type != "NOP": 70 | verilog += I.signal_def(1, "wire", "FORMAT_"+ins_type, num_spaces=2) 71 | verilog += I.newline(1) 72 | verilog += I.signal_def(1, "wire", "ALLOWED_"+ins_type, num_spaces=2) 73 | verilog += I.newline(1) 74 | for ins in instructions[ins_type]: 75 | if ins != "CONSTRAINT": 76 | verilog += I.signal_def(1, "wire", ins, num_spaces=2) 77 | verilog += I.newline(1) 78 | verilog += I.newline(1) 79 | 80 | # Assign bit fields 81 | for bit_field in bit_fields: 82 | if bit_field != "CONSTRAINT": 83 | msb, lsb = bit_fields[bit_field].split() 84 | verilog += I.assign_def(bit_field, I.signal_index("instruction", msb, lsb), num_spaces=2) 85 | verilog += I.newline(1) 86 | 87 | # Assign instruction types 88 | verilog += I.newline(1) 89 | for ins_type in instructions: 90 | type_constraints = instructions[ins_type]["CONSTRAINT"] 91 | constraints = type_constraints 92 | 93 | if qed_constraints["half_registers"] == "1": 94 | fields = ins_fields[ins_type].split() 95 | for field in fields: 96 | if field in registers: 97 | constraints.append(I._lt(field, str(int(isa_info["num_registers"])/2), parens=True)) 98 | 99 | if ins_type != "NOP" and len(constraints) > 0: 100 | expression = constraints[0] 101 | for i in range(1, len(constraints)): 102 | expression = I._and(expression, constraints[i], parens=False) 103 | 104 | verilog += I.assign_def("FORMAT_"+ins_type, expression, num_spaces=2) 105 | verilog += I.newline(1) 106 | 107 | allowed_expression = "" 108 | for ins in instructions[ins_type]: 109 | if ins != "CONSTRAINT": 110 | fields = instructions[ins_type][ins] 111 | reqs = fields["CONSTRAINT"] 112 | for field in fields: 113 | if field != "CONSTRAINT": 114 | if type(fields[field]) == type([]): 115 | first = fields[field][0] 116 | req_expression = I._equals(field, I._constant(len(first), first), parens=True) 117 | for req in fields[field][1:]: 118 | equality = I._equals(field, I._constant(len(req), req), parens=True) 119 | req_expression = I._or(req_expression, equality, parens=False) 120 | req_expression = "(" + req_expression + ")" 121 | reqs.append(req_expression) 122 | else: 123 | equality = I._equals(field, I._constant(len(fields[field]), fields[field]), parens=True) 124 | reqs.append(equality) 125 | 126 | if ins != "NOP": 127 | reqs_expression = "FORMAT_" + ins_type 128 | for i in range(len(reqs)): 129 | reqs_expression = I._and(reqs_expression, reqs[i], parens=False) 130 | else: 131 | reqs_expression = reqs[0] 132 | for i in range(1, len(reqs)): 133 | reqs_expression = I._and(reqs_expression, reqs[i], parens=False) 134 | 135 | verilog += I.assign_def(ins, reqs_expression, num_spaces=2) 136 | verilog += I.newline(1) 137 | 138 | if allowed_expression == "": 139 | allowed_expression = ins 140 | else: 141 | allowed_expression = I._or(allowed_expression, ins, parens=False) 142 | 143 | verilog += I.assign_def("ALLOWED_"+ins_type, allowed_expression, num_spaces=2) 144 | verilog += I.newline(2) 145 | 146 | # Property assertion 147 | assertions = instructions.keys() 148 | property_expression = "" 149 | for ins_type in assertions: 150 | if property_expression == "": 151 | property_expression = "ALLOWED_" + ins_type 152 | else: 153 | property_expression = I._or(property_expression, "ALLOWED_"+ins_type, parens=False) 154 | 155 | verilog += I.always_def("clk", num_spaces=2) + I.begin(num_spaces=1) 156 | verilog += I.newline(1) 157 | verilog += I.property_def(property_expression, num_spaces=4) 158 | verilog += I.newline(1) 159 | verilog += I.end(num_spaces=2) 160 | verilog += I.newline(1) 161 | 162 | # End module with footer 163 | verilog += I.newline(1) 164 | verilog += I.module_footer() 165 | 166 | return verilog 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | -------------------------------------------------------------------------------- /ridecore-src-buggy/ram_sync.v: -------------------------------------------------------------------------------- 1 | `include "constants.vh" 2 | `default_nettype none 3 | module ram_sync_1r1w #( 4 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 5 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 6 | parameter DATA_DEPTH = 32 7 | ) 8 | ( 9 | input wire clk, 10 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 11 | output reg [BRAM_DATA_WIDTH-1:0] rdata1, 12 | input wire [BRAM_ADDR_WIDTH-1:0] waddr, 13 | input wire [BRAM_DATA_WIDTH-1:0] wdata, 14 | input wire we 15 | ); 16 | 17 | reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1]; 18 | 19 | always @ (posedge clk) begin 20 | rdata1 <= mem[raddr1]; 21 | if (we) 22 | mem[waddr] <= wdata; 23 | end 24 | endmodule // ram_sync_1r1w 25 | 26 | module ram_sync_2r1w #( 27 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 28 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 29 | parameter DATA_DEPTH = 32 30 | ) 31 | ( 32 | input wire clk, 33 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 34 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 35 | output reg [BRAM_DATA_WIDTH-1:0] rdata1, 36 | output reg [BRAM_DATA_WIDTH-1:0] rdata2, 37 | input wire [BRAM_ADDR_WIDTH-1:0] waddr, 38 | input wire [BRAM_DATA_WIDTH-1:0] wdata, 39 | input wire we 40 | ); 41 | 42 | reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1]; 43 | 44 | always @ (posedge clk) begin 45 | rdata1 <= mem[raddr1]; 46 | rdata2 <= mem[raddr2]; 47 | if (we) 48 | mem[waddr] <= wdata; 49 | end 50 | endmodule // ram_sync_2r1w 51 | 52 | module ram_sync_2r2w #( 53 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 54 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 55 | parameter DATA_DEPTH = 32 56 | ) 57 | ( 58 | input wire clk, 59 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 60 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 61 | output reg [BRAM_DATA_WIDTH-1:0] rdata1, 62 | output reg [BRAM_DATA_WIDTH-1:0] rdata2, 63 | input wire [BRAM_ADDR_WIDTH-1:0] waddr1, 64 | input wire [BRAM_ADDR_WIDTH-1:0] waddr2, 65 | input wire [BRAM_DATA_WIDTH-1:0] wdata1, 66 | input wire [BRAM_DATA_WIDTH-1:0] wdata2, 67 | input wire we1, 68 | input wire we2 69 | ); 70 | 71 | reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1]; 72 | 73 | always @ (posedge clk) begin 74 | rdata1 <= mem[raddr1]; 75 | rdata2 <= mem[raddr2]; 76 | if (we1) 77 | mem[waddr1] <= wdata1; 78 | if (we2) 79 | mem[waddr2] <= wdata2; 80 | end 81 | endmodule // ram_sync_2r2w 82 | 83 | module ram_sync_4r1w #( 84 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 85 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 86 | parameter DATA_DEPTH = 32 87 | ) 88 | ( 89 | input wire clk, 90 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 91 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 92 | input wire [BRAM_ADDR_WIDTH-1:0] raddr3, 93 | input wire [BRAM_ADDR_WIDTH-1:0] raddr4, 94 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 95 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 96 | output wire [BRAM_DATA_WIDTH-1:0] rdata3, 97 | output wire [BRAM_DATA_WIDTH-1:0] rdata4, 98 | input wire [BRAM_ADDR_WIDTH-1:0] waddr, 99 | input wire [BRAM_DATA_WIDTH-1:0] wdata, 100 | input wire we 101 | ); 102 | 103 | ram_sync_2r1w 104 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 105 | mem0( 106 | .clk(clk), 107 | .raddr1(raddr1), 108 | .raddr2(raddr2), 109 | .rdata1(rdata1), 110 | .rdata2(rdata2), 111 | .waddr(waddr), 112 | .wdata(wdata), 113 | .we(we) 114 | ); 115 | 116 | ram_sync_2r1w 117 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 118 | mem1( 119 | .clk(clk), 120 | .raddr1(raddr3), 121 | .raddr2(raddr4), 122 | .rdata1(rdata3), 123 | .rdata2(rdata4), 124 | .waddr(waddr), 125 | .wdata(wdata), 126 | .we(we) 127 | ); 128 | 129 | endmodule // ram_sync_4r1w 130 | 131 | module ram_sync_4r2w #( 132 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 133 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 134 | parameter DATA_DEPTH = 32 135 | ) 136 | ( 137 | input wire clk, 138 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 139 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 140 | input wire [BRAM_ADDR_WIDTH-1:0] raddr3, 141 | input wire [BRAM_ADDR_WIDTH-1:0] raddr4, 142 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 143 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 144 | output wire [BRAM_DATA_WIDTH-1:0] rdata3, 145 | output wire [BRAM_DATA_WIDTH-1:0] rdata4, 146 | input wire [BRAM_ADDR_WIDTH-1:0] waddr1, 147 | input wire [BRAM_ADDR_WIDTH-1:0] waddr2, 148 | input wire [BRAM_DATA_WIDTH-1:0] wdata1, 149 | input wire [BRAM_DATA_WIDTH-1:0] wdata2, 150 | input wire we1, 151 | input wire we2 152 | ); 153 | 154 | ram_sync_2r2w 155 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 156 | mem0( 157 | .clk(clk), 158 | .raddr1(raddr1), 159 | .raddr2(raddr2), 160 | .rdata1(rdata1), 161 | .rdata2(rdata2), 162 | .waddr1(waddr1), 163 | .waddr2(waddr2), 164 | .wdata1(wdata1), 165 | .wdata2(wdata2), 166 | .we1(we1), 167 | .we2(we2) 168 | ); 169 | 170 | ram_sync_2r2w 171 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 172 | mem1( 173 | .clk(clk), 174 | .raddr1(raddr3), 175 | .raddr2(raddr4), 176 | .rdata1(rdata3), 177 | .rdata2(rdata4), 178 | .waddr1(waddr1), 179 | .waddr2(waddr2), 180 | .wdata1(wdata1), 181 | .wdata2(wdata2), 182 | .we1(we1), 183 | .we2(we2) 184 | ); 185 | 186 | endmodule // ram_sync_4r2w 187 | 188 | module ram_sync_6r2w #( 189 | parameter BRAM_ADDR_WIDTH = `ADDR_LEN, 190 | parameter BRAM_DATA_WIDTH = `DATA_LEN, 191 | parameter DATA_DEPTH = 32 192 | ) 193 | ( 194 | input wire clk, 195 | input wire [BRAM_ADDR_WIDTH-1:0] raddr1, 196 | input wire [BRAM_ADDR_WIDTH-1:0] raddr2, 197 | input wire [BRAM_ADDR_WIDTH-1:0] raddr3, 198 | input wire [BRAM_ADDR_WIDTH-1:0] raddr4, 199 | input wire [BRAM_ADDR_WIDTH-1:0] raddr5, 200 | input wire [BRAM_ADDR_WIDTH-1:0] raddr6, 201 | output wire [BRAM_DATA_WIDTH-1:0] rdata1, 202 | output wire [BRAM_DATA_WIDTH-1:0] rdata2, 203 | output wire [BRAM_DATA_WIDTH-1:0] rdata3, 204 | output wire [BRAM_DATA_WIDTH-1:0] rdata4, 205 | output wire [BRAM_DATA_WIDTH-1:0] rdata5, 206 | output wire [BRAM_DATA_WIDTH-1:0] rdata6, 207 | input wire [BRAM_ADDR_WIDTH-1:0] waddr1, 208 | input wire [BRAM_ADDR_WIDTH-1:0] waddr2, 209 | input wire [BRAM_DATA_WIDTH-1:0] wdata1, 210 | input wire [BRAM_DATA_WIDTH-1:0] wdata2, 211 | input wire we1, 212 | input wire we2 213 | ); 214 | 215 | ram_sync_2r2w 216 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 217 | mem0( 218 | .clk(clk), 219 | .raddr1(raddr1), 220 | .raddr2(raddr2), 221 | .rdata1(rdata1), 222 | .rdata2(rdata2), 223 | .waddr1(waddr1), 224 | .waddr2(waddr2), 225 | .wdata1(wdata1), 226 | .wdata2(wdata2), 227 | .we1(we1), 228 | .we2(we2) 229 | ); 230 | 231 | ram_sync_2r2w 232 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 233 | mem1( 234 | .clk(clk), 235 | .raddr1(raddr3), 236 | .raddr2(raddr4), 237 | .rdata1(rdata3), 238 | .rdata2(rdata4), 239 | .waddr1(waddr1), 240 | .waddr2(waddr2), 241 | .wdata1(wdata1), 242 | .wdata2(wdata2), 243 | .we1(we1), 244 | .we2(we2) 245 | ); 246 | 247 | ram_sync_2r2w 248 | #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 249 | mem2( 250 | .clk(clk), 251 | .raddr1(raddr5), 252 | .raddr2(raddr6), 253 | .rdata1(rdata5), 254 | .rdata2(rdata6), 255 | .waddr1(waddr1), 256 | .waddr2(waddr2), 257 | .wdata1(wdata1), 258 | .wdata2(wdata2), 259 | .we1(we1), 260 | .we2(we2) 261 | ); 262 | 263 | endmodule // ram_sync_6r2w 264 | `default_nettype wire 265 | --------------------------------------------------------------------------------