├── LICENSE.txt ├── README.md ├── demikernel ├── README.md ├── catnip │ ├── .gitignore │ ├── Cargo.toml │ ├── LICENSE.txt │ ├── Makefile │ ├── NOTICE.md │ ├── README.md │ ├── rust-toolchain │ ├── src │ │ ├── collections │ │ │ ├── async_map.rs │ │ │ ├── async_slab.rs │ │ │ ├── bytes.rs │ │ │ ├── hashttlcache │ │ │ │ ├── mod.rs │ │ │ │ └── tests.rs │ │ │ ├── mod.rs │ │ │ ├── waker_page.rs │ │ │ └── watched.rs │ │ ├── engine.rs │ │ ├── fail.rs │ │ ├── file_table.rs │ │ ├── futures_utility.rs │ │ ├── interop.rs │ │ ├── lib.rs │ │ ├── libos.rs │ │ ├── logging.rs │ │ ├── operations.rs │ │ ├── options.rs │ │ ├── protocols │ │ │ ├── arp │ │ │ │ ├── cache │ │ │ │ │ ├── mod.rs │ │ │ │ │ └── tests.rs │ │ │ │ ├── mod.rs │ │ │ │ ├── msg │ │ │ │ │ └── mod.rs │ │ │ │ ├── options.rs │ │ │ │ ├── pdu │ │ │ │ │ └── mod.rs │ │ │ │ ├── peer.rs │ │ │ │ └── tests.rs │ │ │ ├── ethernet2 │ │ │ │ ├── frame.rs │ │ │ │ ├── mac_address.rs │ │ │ │ └── mod.rs │ │ │ ├── icmpv4 │ │ │ │ ├── datagram.rs │ │ │ │ ├── mod.rs │ │ │ │ └── peer.rs │ │ │ ├── ip │ │ │ │ ├── mod.rs │ │ │ │ └── port.rs │ │ │ ├── ipv4 │ │ │ │ ├── datagram.rs │ │ │ │ ├── endpoint.rs │ │ │ │ ├── mod.rs │ │ │ │ ├── peer.rs │ │ │ │ └── tests.rs │ │ │ ├── mod.rs │ │ │ ├── tcp │ │ │ │ ├── TODO.md │ │ │ │ ├── active_open.rs │ │ │ │ ├── constants.rs │ │ │ │ ├── established │ │ │ │ │ ├── background │ │ │ │ │ │ ├── acknowledger.rs │ │ │ │ │ │ ├── closer.rs │ │ │ │ │ │ ├── mod.rs │ │ │ │ │ │ ├── retransmitter.rs │ │ │ │ │ │ └── sender.rs │ │ │ │ │ ├── mod.rs │ │ │ │ │ └── state │ │ │ │ │ │ ├── congestion_ctrl │ │ │ │ │ │ ├── cubic.rs │ │ │ │ │ │ ├── mod.rs │ │ │ │ │ │ ├── none.rs │ │ │ │ │ │ └── options.rs │ │ │ │ │ │ ├── mod.rs │ │ │ │ │ │ ├── receiver.rs │ │ │ │ │ │ ├── rto.rs │ │ │ │ │ │ └── sender.rs │ │ │ │ ├── isn_generator.rs │ │ │ │ ├── mod.rs │ │ │ │ ├── operations.rs │ │ │ │ ├── options.rs │ │ │ │ ├── passive_open.rs │ │ │ │ ├── peer.rs │ │ │ │ ├── segment.rs │ │ │ │ └── tests │ │ │ │ │ ├── established.rs │ │ │ │ │ ├── mod.rs │ │ │ │ │ └── setup.rs │ │ │ └── udp │ │ │ │ ├── datagram │ │ │ │ ├── header.rs │ │ │ │ └── mod.rs │ │ │ │ ├── listener.rs │ │ │ │ ├── mod.rs │ │ │ │ ├── operations.rs │ │ │ │ ├── options.rs │ │ │ │ ├── peer.rs │ │ │ │ ├── socket.rs │ │ │ │ └── tests.rs │ │ ├── runtime.rs │ │ ├── scheduler.rs │ │ ├── sync │ │ │ ├── mod.rs │ │ │ ├── threadsafe.rs │ │ │ └── threadunsafe.rs │ │ ├── test_helpers.rs │ │ └── timer.rs │ └── tests │ │ ├── common │ │ ├── libos.rs │ │ ├── mod.rs │ │ └── runtime.rs │ │ ├── tcp.rs │ │ └── udp.rs ├── demikernel │ ├── .gitignore │ ├── CONTRIBUTING.md │ ├── LICENSE.txt │ ├── Makefile │ ├── NOTICE.md │ ├── README.md │ ├── default.yaml │ ├── include │ │ └── dmtr │ │ │ ├── annot.h │ │ │ ├── cast.h │ │ │ ├── fail.h │ │ │ ├── latency.h │ │ │ ├── libos.h │ │ │ ├── libos │ │ │ ├── io_queue.hh │ │ │ ├── io_queue_api.hh │ │ │ ├── io_queue_factory.hh │ │ │ ├── mem.h │ │ │ ├── memory_queue.hh │ │ │ ├── raii_guard.hh │ │ │ ├── rdma │ │ │ │ └── rdmacm_router.hh │ │ │ └── user_thread.hh │ │ │ ├── meta.h │ │ │ ├── sga.h │ │ │ ├── sys │ │ │ └── gcc.h │ │ │ └── types.h │ └── src │ │ ├── Cargo.lock │ │ ├── Cargo.toml │ │ ├── catnip-libos │ │ ├── Cargo.toml │ │ ├── examples │ │ │ └── ixy.rs │ │ └── src │ │ │ ├── db.rs │ │ │ ├── dpdk.rs │ │ │ ├── lib.rs │ │ │ ├── memory.rs │ │ │ └── runtime.rs │ │ ├── rust-toolchain │ │ └── rustfmt.toml ├── ixy-rs │ ├── .gitignore │ ├── Cargo.toml │ ├── LICENSE │ ├── README.md │ ├── build.rs │ ├── inlined.c │ ├── src │ │ ├── bin │ │ │ └── init.rs │ │ ├── bindings.rs │ │ └── lib.rs │ └── wrapper.h └── perftools │ ├── .cargo-ok │ ├── .gitignore │ ├── Cargo.toml │ ├── LICENSE │ ├── README.md │ ├── examples │ └── timer.rs │ ├── rust-toolchain │ └── src │ ├── lib.rs │ └── profiler │ ├── mod.rs │ └── tests.rs ├── driver ├── .gitignore ├── CMakeLists.txt ├── LICENSE ├── README.md ├── setup-hugetlbfs.sh ├── src │ ├── app │ │ ├── ixy-throughput.c │ │ └── ixy_testmmio.c │ ├── driver │ │ ├── device.c │ │ ├── device.h │ │ ├── mqnic.c │ │ ├── mqnic.h │ │ └── mqnic_type.h │ ├── interrupts.c │ ├── interrupts.h │ ├── libixy-vfio.c │ ├── libixy-vfio.h │ ├── log.h │ ├── memory.c │ ├── memory.h │ ├── msg.c │ ├── msg.h │ ├── pci.c │ ├── pci.h │ ├── stats.c │ └── stats.h └── vagrant │ ├── README.md │ └── Vagrantfile └── hardware ├── .gitignore ├── AUTHORS ├── COPYING ├── README ├── README.md ├── block.svg ├── fpga ├── app │ └── template │ │ ├── lib │ │ ├── rtl │ │ ├── common │ │ └── mqnic_app_block.v │ │ └── tb │ │ └── mqnic_core_pcie_us │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_mqnic_core_pcie_us.py ├── common │ ├── lib │ ├── rtl │ │ ├── cmac_pad.v │ │ ├── cpl_op_mux.v │ │ ├── cpl_queue_manager.v │ │ ├── cpl_write.v │ │ ├── desc_fetch.v │ │ ├── desc_op_mux.v │ │ ├── event_mux.v │ │ ├── mqnic_core.v │ │ ├── mqnic_core_pcie.v │ │ ├── mqnic_core_pcie_us.v │ │ ├── mqnic_interface.v │ │ ├── mqnic_port.v │ │ ├── mqnic_ptp.v │ │ ├── mqnic_ptp_clock.v │ │ ├── mqnic_ptp_perout.v │ │ ├── mqnic_tx_scheduler_block_rr.v │ │ ├── mqnic_tx_scheduler_block_rr_tdma.v │ │ ├── queue_manager.v │ │ ├── ringleader │ │ │ ├── define.v │ │ │ ├── desc_dispatch.v │ │ │ ├── desc_gen.v │ │ │ ├── desc_sche.v │ │ │ ├── desc_sche_pifo.v │ │ │ ├── find_min.v │ │ │ ├── head_parser.v │ │ │ ├── perf_monitor.v │ │ │ ├── pifo.sv │ │ │ ├── pifo_queue_manager.v │ │ │ ├── pifo_warp.v │ │ │ ├── rand_mem_alloc.v │ │ │ ├── ringleader.v │ │ │ ├── rl_memory_alloc.v │ │ │ └── testbench.v │ │ ├── rx_checksum.v │ │ ├── rx_engine.v │ │ ├── rx_hash.v │ │ ├── stats_collect.v │ │ ├── stats_counter.v │ │ ├── stats_dma_if_pcie.v │ │ ├── stats_dma_latency.v │ │ ├── stats_pcie_if.v │ │ ├── stats_pcie_tlp.v │ │ ├── tdma_ber.v │ │ ├── tdma_ber_ch.v │ │ ├── tdma_scheduler.v │ │ ├── tx_checksum.v │ │ ├── tx_engine.v │ │ ├── tx_scheduler_ctrl_tdma.v │ │ └── tx_scheduler_rr.v │ ├── syn │ │ └── vivado │ │ │ └── tdma_ber_ch.tcl │ └── tb │ │ ├── Makefile │ │ ├── cmac_pad │ │ ├── Makefile │ │ └── test_cmac_pad.py │ │ ├── cpl_queue_manager │ │ ├── Makefile │ │ └── test_cpl_queue_manager.py │ │ ├── mqnic.py │ │ ├── mqnic_core_pcie_us │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_mqnic_core_pcie_us.py │ │ ├── mqnic_core_pcie_us_tdma │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_mqnic_core_pcie_us.py │ │ ├── queue_manager │ │ ├── Makefile │ │ └── test_queue_manager.py │ │ ├── rx_checksum │ │ ├── Makefile │ │ └── test_rx_checksum.py │ │ ├── rx_hash │ │ ├── Makefile │ │ └── test_rx_hash.py │ │ ├── stats_collect │ │ ├── Makefile │ │ └── test_stats_collect.py │ │ ├── stats_counter │ │ ├── Makefile │ │ └── test_stats_counter.py │ │ ├── tdma_ber │ │ ├── Makefile │ │ └── test_tdma_ber.py │ │ ├── tdma_ber_ch │ │ ├── Makefile │ │ └── test_tdma_ber_ch.py │ │ ├── tdma_scheduler │ │ ├── Makefile │ │ └── test_tdma_scheduler.py │ │ └── tx_checksum │ │ ├── Makefile │ │ └── test_tx_checksum.py ├── lib │ ├── axi │ │ ├── .github │ │ │ └── workflows │ │ │ │ └── regression-tests.yml │ │ ├── .gitignore │ │ ├── .test_durations │ │ ├── AUTHORS │ │ ├── COPYING │ │ ├── README.md │ │ ├── rtl │ │ │ ├── arbiter.v │ │ │ ├── axi_adapter.v │ │ │ ├── axi_adapter_rd.v │ │ │ ├── axi_adapter_wr.v │ │ │ ├── axi_axil_adapter.v │ │ │ ├── axi_axil_adapter_rd.v │ │ │ ├── axi_axil_adapter_wr.v │ │ │ ├── axi_cdma.v │ │ │ ├── axi_cdma_desc_mux.v │ │ │ ├── axi_crossbar.v │ │ │ ├── axi_crossbar_addr.v │ │ │ ├── axi_crossbar_rd.v │ │ │ ├── axi_crossbar_wr.v │ │ │ ├── axi_crossbar_wrap.py │ │ │ ├── axi_dma.v │ │ │ ├── axi_dma_desc_mux.v │ │ │ ├── axi_dma_rd.v │ │ │ ├── axi_dma_wr.v │ │ │ ├── axi_dp_ram.v │ │ │ ├── axi_fifo.v │ │ │ ├── axi_fifo_rd.v │ │ │ ├── axi_fifo_wr.v │ │ │ ├── axi_interconnect.v │ │ │ ├── axi_interconnect_wrap.py │ │ │ ├── axi_ram.v │ │ │ ├── axi_ram_rd_if.v │ │ │ ├── axi_ram_wr_if.v │ │ │ ├── axi_ram_wr_rd_if.v │ │ │ ├── axi_register.v │ │ │ ├── axi_register_rd.v │ │ │ ├── axi_register_wr.v │ │ │ ├── axil_adapter.v │ │ │ ├── axil_adapter_rd.v │ │ │ ├── axil_adapter_wr.v │ │ │ ├── axil_cdc.v │ │ │ ├── axil_cdc_rd.v │ │ │ ├── axil_cdc_wr.v │ │ │ ├── axil_crossbar.v │ │ │ ├── axil_crossbar_addr.v │ │ │ ├── axil_crossbar_rd.v │ │ │ ├── axil_crossbar_wr.v │ │ │ ├── axil_crossbar_wrap.py │ │ │ ├── axil_dp_ram.v │ │ │ ├── axil_interconnect.v │ │ │ ├── axil_interconnect_wrap.py │ │ │ ├── axil_ram.v │ │ │ ├── axil_reg_if.v │ │ │ ├── axil_reg_if_rd.v │ │ │ ├── axil_reg_if_wr.v │ │ │ ├── axil_register.v │ │ │ ├── axil_register_rd.v │ │ │ ├── axil_register_wr.v │ │ │ └── priority_encoder.v │ │ ├── syn │ │ │ └── vivado │ │ │ │ └── axil_cdc.tcl │ │ ├── tb │ │ │ ├── Makefile │ │ │ ├── axi.py │ │ │ ├── axi_adapter │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_adapter.py │ │ │ ├── axi_axil_adapter │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_axil_adapter.py │ │ │ ├── axi_cdma │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_cdma.py │ │ │ ├── axi_crossbar │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_crossbar.py │ │ │ ├── axi_dma │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_dma.py │ │ │ ├── axi_dma_rd │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_dma_rd.py │ │ │ ├── axi_dma_wr │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_dma_wr.py │ │ │ ├── axi_dp_ram │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_dp_ram.py │ │ │ ├── axi_fifo │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_fifo.py │ │ │ ├── axi_interconnect │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_interconnect.py │ │ │ ├── axi_ram │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_ram.py │ │ │ ├── axi_register │ │ │ │ ├── Makefile │ │ │ │ └── test_axi_register.py │ │ │ ├── axil.py │ │ │ ├── axil_adapter │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_adapter.py │ │ │ ├── axil_cdc │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_cdc.py │ │ │ ├── axil_crossbar │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_crossbar.py │ │ │ ├── axil_dp_ram │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_dp_ram.py │ │ │ ├── axil_interconnect │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_interconnect.py │ │ │ ├── axil_ram │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_ram.py │ │ │ ├── axil_reg_if │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_reg_if.py │ │ │ ├── axil_register │ │ │ │ ├── Makefile │ │ │ │ └── test_axil_register.py │ │ │ ├── axis_ep.py │ │ │ ├── test_axi.py │ │ │ ├── test_axi_adapter_16_32.py │ │ │ ├── test_axi_adapter_16_32.v │ │ │ ├── test_axi_adapter_32_16.py │ │ │ ├── test_axi_adapter_32_16.v │ │ │ ├── test_axi_adapter_32_32.py │ │ │ ├── test_axi_adapter_32_32.v │ │ │ ├── test_axi_axil_adapter_16_32.py │ │ │ ├── test_axi_axil_adapter_16_32.v │ │ │ ├── test_axi_axil_adapter_32_16.py │ │ │ ├── test_axi_axil_adapter_32_16.v │ │ │ ├── test_axi_axil_adapter_32_32.py │ │ │ ├── test_axi_axil_adapter_32_32.v │ │ │ ├── test_axi_cdma_32.py │ │ │ ├── test_axi_cdma_32.v │ │ │ ├── test_axi_cdma_32_unaligned.py │ │ │ ├── test_axi_cdma_32_unaligned.v │ │ │ ├── test_axi_crossbar_4x4.py │ │ │ ├── test_axi_crossbar_4x4.v │ │ │ ├── test_axi_dma_32_32.py │ │ │ ├── test_axi_dma_32_32.v │ │ │ ├── test_axi_dma_rd_32_32.py │ │ │ ├── test_axi_dma_rd_32_32.v │ │ │ ├── test_axi_dma_rd_32_32_unaligned.py │ │ │ ├── test_axi_dma_rd_32_32_unaligned.v │ │ │ ├── test_axi_dma_wr_32_32.py │ │ │ ├── test_axi_dma_wr_32_32.v │ │ │ ├── test_axi_dma_wr_32_32_unaligned.py │ │ │ ├── test_axi_dma_wr_32_32_unaligned.v │ │ │ ├── test_axi_dp_ram.py │ │ │ ├── test_axi_dp_ram.v │ │ │ ├── test_axi_fifo.py │ │ │ ├── test_axi_fifo.v │ │ │ ├── test_axi_fifo_delay.py │ │ │ ├── test_axi_fifo_delay.v │ │ │ ├── test_axi_interconnect_4x4.py │ │ │ ├── test_axi_interconnect_4x4.v │ │ │ ├── test_axi_ram.py │ │ │ ├── test_axi_ram.v │ │ │ ├── test_axi_register.py │ │ │ ├── test_axi_register.v │ │ │ ├── test_axil.py │ │ │ ├── test_axil_adapter_16_32.py │ │ │ ├── test_axil_adapter_16_32.v │ │ │ ├── test_axil_adapter_32_16.py │ │ │ ├── test_axil_adapter_32_16.v │ │ │ ├── test_axil_adapter_32_32.py │ │ │ ├── test_axil_adapter_32_32.v │ │ │ ├── test_axil_cdc.py │ │ │ ├── test_axil_cdc.v │ │ │ ├── test_axil_dp_ram.py │ │ │ ├── test_axil_dp_ram.v │ │ │ ├── test_axil_interconnect_4x4.py │ │ │ ├── test_axil_interconnect_4x4.v │ │ │ ├── test_axil_ram.py │ │ │ ├── test_axil_ram.v │ │ │ ├── test_axil_register.py │ │ │ └── test_axil_register.v │ │ └── tox.ini │ ├── axis │ ├── eth │ │ ├── .github │ │ │ └── workflows │ │ │ │ └── regression-tests.yml │ │ ├── .gitignore │ │ ├── .test_durations │ │ ├── AUTHORS │ │ ├── COPYING │ │ ├── README.md │ │ ├── example │ │ │ ├── ADM_PCIE_9V3 │ │ │ │ ├── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ └── fpga_25g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ATLYS │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── clock.ucf │ │ │ │ │ ├── common │ │ │ │ │ └── xilinx.mk │ │ │ │ │ ├── fpga.ucf │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU200 │ │ │ │ └── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU250 │ │ │ │ └── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU280 │ │ │ │ └── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU50 │ │ │ │ └── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── Arty │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── C10LP │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── quartus.mk │ │ │ │ │ ├── fpga.qsf │ │ │ │ │ ├── fpga.sdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── DE2-115 │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── quartus.mk │ │ │ │ │ ├── fpga.qsf │ │ │ │ │ ├── fpga.sdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── hex_display.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── DE5-Net │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── altera.mk │ │ │ │ │ ├── cores │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── phy.v │ │ │ │ │ └── phy_reconfig.v │ │ │ │ │ ├── fpga.qsf │ │ │ │ │ ├── fpga.sdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── i2c_master.v │ │ │ │ │ ├── si570_i2c_init.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ExaNIC_X10 │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ExaNIC_X25 │ │ │ │ └── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── HTG9200 │ │ │ │ └── fpga_10g │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ ├── gtwiz_qsfp_1.tcl │ │ │ │ │ ├── gtwiz_qsfp_2.tcl │ │ │ │ │ ├── gtwiz_qsfp_3.tcl │ │ │ │ │ ├── gtwiz_qsfp_4.tcl │ │ │ │ │ ├── gtwiz_qsfp_5.tcl │ │ │ │ │ ├── gtwiz_qsfp_6.tcl │ │ │ │ │ ├── gtwiz_qsfp_7.tcl │ │ │ │ │ ├── gtwiz_qsfp_8.tcl │ │ │ │ │ └── gtwiz_qsfp_9.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── Si5341-RevD-fpga-161-osc-Registers.txt │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── i2c_master.v │ │ │ │ │ ├── si5341_i2c_init.py │ │ │ │ │ ├── si5341_i2c_init.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── HXT100G │ │ │ │ ├── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ │ └── xilinx.mk │ │ │ │ │ ├── coregen │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── coregen.cgp │ │ │ │ │ │ ├── ten_gig_eth_pcs_pma_v2_6.xco │ │ │ │ │ │ └── ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco │ │ │ │ │ ├── fpga.ucf │ │ │ │ │ ├── fpga │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── eth_gth_phy_quad.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ ├── gth_i2c_init.v │ │ │ │ │ │ ├── i2c_master.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ └── fpga_cxpt16 │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── xilinx.mk │ │ │ │ │ ├── coregen │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── coregen.cgp │ │ │ │ │ ├── ten_gig_eth_pcs_pma_v2_6.xco │ │ │ │ │ └── ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco │ │ │ │ │ ├── fpga.ucf │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── eth_gth_phy_quad.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── gth_i2c_init.v │ │ │ │ │ ├── i2c_master.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── KC705 │ │ │ │ ├── fpga_gmii │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── clock.xdc │ │ │ │ │ ├── common │ │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ ├── fpga_rgmii │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── generate_bit_iodelay.tcl │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ └── fpga_sgmii │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ML605 │ │ │ │ ├── fpga_gmii │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── clock.ucf │ │ │ │ │ ├── common │ │ │ │ │ │ └── xilinx.mk │ │ │ │ │ ├── fpga.ucf │ │ │ │ │ ├── fpga_130t │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── fpga_240t │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ ├── fpga_rgmii │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── clock.ucf │ │ │ │ │ ├── common │ │ │ │ │ │ └── xilinx.mk │ │ │ │ │ ├── fpga.ucf │ │ │ │ │ ├── fpga_130t │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── fpga_240t │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ └── fpga_sgmii │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── clock.ucf │ │ │ │ │ ├── common │ │ │ │ │ └── xilinx.mk │ │ │ │ │ ├── coregen │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── coregen.cgp │ │ │ │ │ └── gig_eth_pcs_pma_v11_5.xco │ │ │ │ │ ├── fpga.ucf │ │ │ │ │ ├── fpga_130t │ │ │ │ │ └── Makefile │ │ │ │ │ ├── fpga_240t │ │ │ │ │ └── Makefile │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── NetFPGA_SUME │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ ├── ten_gig_eth_pcs_pma_0.tcl │ │ │ │ │ └── ten_gig_eth_pcs_pma_1.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── i2c_master.v │ │ │ │ │ └── si5324_i2c_init.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── NexysVideo │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ └── generate_bit_iodelay.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── S10DX_DK │ │ │ │ └── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── quartus_pro.mk │ │ │ │ │ ├── fpga.qsf │ │ │ │ │ ├── fpga.sdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ ├── mac.tcl │ │ │ │ │ └── reset_release.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── avst2axis.v │ │ │ │ │ ├── axis2avst.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── eth_mac_quad_wrapper.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_signal.v │ │ │ │ │ └── xcvr_ctrl.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── S10MX_DK │ │ │ │ └── fpga_10g │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── quartus_pro.mk │ │ │ │ │ ├── fpga.qsf │ │ │ │ │ ├── fpga.sdc │ │ │ │ │ ├── fpga_1sm21b │ │ │ │ │ └── Makefile │ │ │ │ │ ├── fpga_1sm21c │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ ├── eth_xcvr.tcl │ │ │ │ │ ├── eth_xcvr_pll.tcl │ │ │ │ │ ├── eth_xcvr_reset.tcl │ │ │ │ │ └── reset_release.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── eth_xcvr_phy_quad_wrapper.v │ │ │ │ │ ├── eth_xcvr_phy_wrapper.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── VCU108 │ │ │ │ ├── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ │ ├── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ └── fpga_1g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── eth.xdc │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── VCU118 │ │ │ │ ├── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ │ ├── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ ├── mdio_master.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ ├── fpga_1g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ │ ├── fpga.v │ │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ │ ├── mdio_master.v │ │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ │ └── fpga_core │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_fpga_core.py │ │ │ │ └── fpga_25g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ ├── gig_ethernet_pcs_pma_0.tcl │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── mdio_master.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── VCU1525 │ │ │ │ └── fpga_10g │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ZCU102 │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ZCU106 │ │ │ │ └── fpga │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── eth │ │ │ │ │ ├── rtl │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ └── fb2CG │ │ │ │ └── fpga_10g │ │ │ │ ├── Makefile │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── ip │ │ │ │ └── gtwizard_ultrascale_0.tcl │ │ │ │ ├── led.tcl │ │ │ │ ├── lib │ │ │ │ └── eth │ │ │ │ ├── rtl │ │ │ │ ├── fpga.v │ │ │ │ ├── fpga_core.v │ │ │ │ ├── led_sreg_driver.v │ │ │ │ └── sync_signal.v │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ └── test_fpga_core.py │ │ ├── lib │ │ │ ├── axis │ │ │ │ ├── .github │ │ │ │ │ └── workflows │ │ │ │ │ │ └── regression-tests.yml │ │ │ │ ├── .gitignore │ │ │ │ ├── .test_durations │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING │ │ │ │ ├── README │ │ │ │ ├── README.md │ │ │ │ ├── rtl │ │ │ │ │ ├── arbiter.v │ │ │ │ │ ├── axis_adapter.v │ │ │ │ │ ├── axis_arb_mux.v │ │ │ │ │ ├── axis_arb_mux_wrap.py │ │ │ │ │ ├── axis_async_fifo.v │ │ │ │ │ ├── axis_async_fifo_adapter.v │ │ │ │ │ ├── axis_broadcast.v │ │ │ │ │ ├── axis_broadcast_wrap.py │ │ │ │ │ ├── axis_cobs_decode.v │ │ │ │ │ ├── axis_cobs_encode.v │ │ │ │ │ ├── axis_crosspoint.v │ │ │ │ │ ├── axis_crosspoint_wrap.py │ │ │ │ │ ├── axis_demux.v │ │ │ │ │ ├── axis_demux_wrap.py │ │ │ │ │ ├── axis_fifo.v │ │ │ │ │ ├── axis_fifo_adapter.v │ │ │ │ │ ├── axis_frame_join.v │ │ │ │ │ ├── axis_frame_join_wrap.py │ │ │ │ │ ├── axis_frame_len.v │ │ │ │ │ ├── axis_frame_length_adjust.v │ │ │ │ │ ├── axis_frame_length_adjust_fifo.v │ │ │ │ │ ├── axis_ll_bridge.v │ │ │ │ │ ├── axis_mux.v │ │ │ │ │ ├── axis_mux_wrap.py │ │ │ │ │ ├── axis_pipeline_fifo.v │ │ │ │ │ ├── axis_pipeline_register.v │ │ │ │ │ ├── axis_ram_switch.v │ │ │ │ │ ├── axis_ram_switch_wrap.py │ │ │ │ │ ├── axis_rate_limit.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── axis_srl_fifo.v │ │ │ │ │ ├── axis_srl_register.v │ │ │ │ │ ├── axis_stat_counter.v │ │ │ │ │ ├── axis_switch.v │ │ │ │ │ ├── axis_switch_wrap.py │ │ │ │ │ ├── axis_tap.v │ │ │ │ │ ├── ll_axis_bridge.v │ │ │ │ │ ├── priority_encoder.v │ │ │ │ │ └── sync_reset.v │ │ │ │ ├── syn │ │ │ │ │ ├── quartus │ │ │ │ │ │ ├── axis_async_fifo.sdc │ │ │ │ │ │ └── sync_reset.sdc │ │ │ │ │ ├── quartus_pro │ │ │ │ │ │ ├── axis_async_fifo.sdc │ │ │ │ │ │ └── sync_reset.sdc │ │ │ │ │ └── vivado │ │ │ │ │ │ ├── axis_async_fifo.tcl │ │ │ │ │ │ └── sync_reset.tcl │ │ │ │ ├── tb │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── axis_adapter │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_adapter.py │ │ │ │ │ ├── axis_arb_mux │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_arb_mux.py │ │ │ │ │ ├── axis_async_fifo │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_async_fifo.py │ │ │ │ │ ├── axis_async_fifo_adapter │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_async_fifo_adapter.py │ │ │ │ │ ├── axis_broadcast │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_broadcast.py │ │ │ │ │ ├── axis_cobs_decode │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_cobs_decode.py │ │ │ │ │ ├── axis_cobs_encode │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_cobs_encode.py │ │ │ │ │ ├── axis_demux │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_demux.py │ │ │ │ │ ├── axis_ep.py │ │ │ │ │ ├── axis_fifo │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_fifo.py │ │ │ │ │ ├── axis_fifo_adapter │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_fifo_adapter.py │ │ │ │ │ ├── axis_frame_length_adjust │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_frame_length_adjust.py │ │ │ │ │ ├── axis_frame_length_adjust_fifo │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_frame_length_adjust_fifo.py │ │ │ │ │ ├── axis_mux │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_mux.py │ │ │ │ │ ├── axis_pipeline_fifo │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_pipeline_fifo.py │ │ │ │ │ ├── axis_pipeline_register │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_pipeline_register.py │ │ │ │ │ ├── axis_ram_switch │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_ram_switch.py │ │ │ │ │ ├── axis_rate_limit │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_rate_limit.py │ │ │ │ │ ├── axis_register │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_register.py │ │ │ │ │ ├── axis_srl_fifo │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_srl_fifo.py │ │ │ │ │ ├── axis_srl_register │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_srl_register.py │ │ │ │ │ ├── axis_switch │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── test_axis_switch.py │ │ │ │ │ ├── ll_ep.py │ │ │ │ │ ├── test_arbiter.py │ │ │ │ │ ├── test_arbiter.v │ │ │ │ │ ├── test_arbiter_rr.py │ │ │ │ │ ├── test_arbiter_rr.v │ │ │ │ │ ├── test_axis_adapter_64_8.py │ │ │ │ │ ├── test_axis_adapter_64_8.v │ │ │ │ │ ├── test_axis_adapter_8_64.py │ │ │ │ │ ├── test_axis_adapter_8_64.v │ │ │ │ │ ├── test_axis_arb_mux_4.py │ │ │ │ │ ├── test_axis_arb_mux_4.v │ │ │ │ │ ├── test_axis_arb_mux_4_64.py │ │ │ │ │ ├── test_axis_arb_mux_4_64.v │ │ │ │ │ ├── test_axis_async_fifo.py │ │ │ │ │ ├── test_axis_async_fifo.v │ │ │ │ │ ├── test_axis_async_fifo_64.py │ │ │ │ │ ├── test_axis_async_fifo_64.v │ │ │ │ │ ├── test_axis_async_fifo_adapter_64_8.py │ │ │ │ │ ├── test_axis_async_fifo_adapter_64_8.v │ │ │ │ │ ├── test_axis_async_fifo_adapter_8_64.py │ │ │ │ │ ├── test_axis_async_fifo_adapter_8_64.v │ │ │ │ │ ├── test_axis_async_frame_fifo.py │ │ │ │ │ ├── test_axis_async_frame_fifo.v │ │ │ │ │ ├── test_axis_async_frame_fifo_64.py │ │ │ │ │ ├── test_axis_async_frame_fifo_64.v │ │ │ │ │ ├── test_axis_broadcast_4.py │ │ │ │ │ ├── test_axis_broadcast_4.v │ │ │ │ │ ├── test_axis_cobs_decode.py │ │ │ │ │ ├── test_axis_cobs_decode.v │ │ │ │ │ ├── test_axis_cobs_encode.py │ │ │ │ │ ├── test_axis_cobs_encode.v │ │ │ │ │ ├── test_axis_cobs_encode_zero_frame.py │ │ │ │ │ ├── test_axis_cobs_encode_zero_frame.v │ │ │ │ │ ├── test_axis_crosspoint_4x4.py │ │ │ │ │ ├── test_axis_crosspoint_4x4.v │ │ │ │ │ ├── test_axis_crosspoint_4x4_64.py │ │ │ │ │ ├── test_axis_crosspoint_4x4_64.v │ │ │ │ │ ├── test_axis_demux_4.py │ │ │ │ │ ├── test_axis_demux_4.v │ │ │ │ │ ├── test_axis_demux_4_64.py │ │ │ │ │ ├── test_axis_demux_4_64.v │ │ │ │ │ ├── test_axis_fifo.py │ │ │ │ │ ├── test_axis_fifo.v │ │ │ │ │ ├── test_axis_fifo_64.py │ │ │ │ │ ├── test_axis_fifo_64.v │ │ │ │ │ ├── test_axis_fifo_adapter_64_8.py │ │ │ │ │ ├── test_axis_fifo_adapter_64_8.v │ │ │ │ │ ├── test_axis_fifo_adapter_8_64.py │ │ │ │ │ ├── test_axis_fifo_adapter_8_64.v │ │ │ │ │ ├── test_axis_frame_fifo.py │ │ │ │ │ ├── test_axis_frame_fifo.v │ │ │ │ │ ├── test_axis_frame_fifo_64.py │ │ │ │ │ ├── test_axis_frame_fifo_64.v │ │ │ │ │ ├── test_axis_frame_join_4.py │ │ │ │ │ ├── test_axis_frame_join_4.v │ │ │ │ │ ├── test_axis_frame_len_64.py │ │ │ │ │ ├── test_axis_frame_len_64.v │ │ │ │ │ ├── test_axis_frame_len_8.py │ │ │ │ │ ├── test_axis_frame_len_8.v │ │ │ │ │ ├── test_axis_frame_length_adjust_64.py │ │ │ │ │ ├── test_axis_frame_length_adjust_64.v │ │ │ │ │ ├── test_axis_frame_length_adjust_8.py │ │ │ │ │ ├── test_axis_frame_length_adjust_8.v │ │ │ │ │ ├── test_axis_frame_length_adjust_fifo.py │ │ │ │ │ ├── test_axis_frame_length_adjust_fifo.v │ │ │ │ │ ├── test_axis_frame_length_adjust_fifo_64.py │ │ │ │ │ ├── test_axis_frame_length_adjust_fifo_64.v │ │ │ │ │ ├── test_axis_ll_bridge.py │ │ │ │ │ ├── test_axis_ll_bridge.v │ │ │ │ │ ├── test_axis_mux_4.py │ │ │ │ │ ├── test_axis_mux_4.v │ │ │ │ │ ├── test_axis_mux_4_64.py │ │ │ │ │ ├── test_axis_mux_4_64.v │ │ │ │ │ ├── test_axis_ram_switch_1x4_256_64.py │ │ │ │ │ ├── test_axis_ram_switch_1x4_256_64.v │ │ │ │ │ ├── test_axis_ram_switch_4x1_64_256.py │ │ │ │ │ ├── test_axis_ram_switch_4x1_64_256.v │ │ │ │ │ ├── test_axis_ram_switch_4x4_64_64.py │ │ │ │ │ ├── test_axis_ram_switch_4x4_64_64.v │ │ │ │ │ ├── test_axis_rate_limit.py │ │ │ │ │ ├── test_axis_rate_limit.v │ │ │ │ │ ├── test_axis_rate_limit_64.py │ │ │ │ │ ├── test_axis_rate_limit_64.v │ │ │ │ │ ├── test_axis_register.py │ │ │ │ │ ├── test_axis_register.v │ │ │ │ │ ├── test_axis_register_64.py │ │ │ │ │ ├── test_axis_register_64.v │ │ │ │ │ ├── test_axis_srl_fifo.py │ │ │ │ │ ├── test_axis_srl_fifo.v │ │ │ │ │ ├── test_axis_srl_fifo_64.py │ │ │ │ │ ├── test_axis_srl_fifo_64.v │ │ │ │ │ ├── test_axis_srl_register.py │ │ │ │ │ ├── test_axis_srl_register.v │ │ │ │ │ ├── test_axis_srl_register_64.py │ │ │ │ │ ├── test_axis_srl_register_64.v │ │ │ │ │ ├── test_axis_stat_counter.py │ │ │ │ │ ├── test_axis_stat_counter.v │ │ │ │ │ ├── test_axis_switch_4x4.py │ │ │ │ │ ├── test_axis_switch_4x4.v │ │ │ │ │ ├── test_axis_switch_4x4_64.py │ │ │ │ │ ├── test_axis_switch_4x4_64.v │ │ │ │ │ ├── test_axis_tap.py │ │ │ │ │ ├── test_axis_tap.v │ │ │ │ │ ├── test_axis_tap_64.py │ │ │ │ │ ├── test_axis_tap_64.v │ │ │ │ │ ├── test_ll_axis_bridge.py │ │ │ │ │ ├── test_ll_axis_bridge.v │ │ │ │ │ ├── test_priority_encoder.py │ │ │ │ │ └── test_priority_encoder.v │ │ │ │ └── tox.ini │ │ │ └── update-axis.sh │ │ ├── rtl │ │ │ ├── arp.v │ │ │ ├── arp_cache.v │ │ │ ├── arp_eth_rx.v │ │ │ ├── arp_eth_tx.v │ │ │ ├── axis_baser_rx_64.v │ │ │ ├── axis_baser_tx_64.v │ │ │ ├── axis_eth_fcs.v │ │ │ ├── axis_eth_fcs_check.v │ │ │ ├── axis_eth_fcs_check_64.v │ │ │ ├── axis_eth_fcs_insert.v │ │ │ ├── axis_eth_fcs_insert_64.v │ │ │ ├── axis_gmii_rx.v │ │ │ ├── axis_gmii_tx.v │ │ │ ├── axis_xgmii_rx_32.v │ │ │ ├── axis_xgmii_rx_64.v │ │ │ ├── axis_xgmii_tx_32.v │ │ │ ├── axis_xgmii_tx_64.v │ │ │ ├── eth_arb_mux.v │ │ │ ├── eth_axis_rx.v │ │ │ ├── eth_axis_tx.v │ │ │ ├── eth_demux.v │ │ │ ├── eth_mac_10g.v │ │ │ ├── eth_mac_10g_fifo.v │ │ │ ├── eth_mac_1g.v │ │ │ ├── eth_mac_1g_fifo.v │ │ │ ├── eth_mac_1g_gmii.v │ │ │ ├── eth_mac_1g_gmii_fifo.v │ │ │ ├── eth_mac_1g_rgmii.v │ │ │ ├── eth_mac_1g_rgmii_fifo.v │ │ │ ├── eth_mac_mii.v │ │ │ ├── eth_mac_mii_fifo.v │ │ │ ├── eth_mac_phy_10g.v │ │ │ ├── eth_mac_phy_10g_fifo.v │ │ │ ├── eth_mac_phy_10g_rx.v │ │ │ ├── eth_mac_phy_10g_tx.v │ │ │ ├── eth_mux.v │ │ │ ├── eth_phy_10g.v │ │ │ ├── eth_phy_10g_rx.v │ │ │ ├── eth_phy_10g_rx_ber_mon.v │ │ │ ├── eth_phy_10g_rx_frame_sync.v │ │ │ ├── eth_phy_10g_rx_if.v │ │ │ ├── eth_phy_10g_tx.v │ │ │ ├── eth_phy_10g_tx_if.v │ │ │ ├── gmii_phy_if.v │ │ │ ├── iddr.v │ │ │ ├── ip.v │ │ │ ├── ip_64.v │ │ │ ├── ip_arb_mux.v │ │ │ ├── ip_complete.v │ │ │ ├── ip_complete_64.v │ │ │ ├── ip_demux.v │ │ │ ├── ip_eth_rx.v │ │ │ ├── ip_eth_rx_64.v │ │ │ ├── ip_eth_tx.v │ │ │ ├── ip_eth_tx_64.v │ │ │ ├── ip_mux.v │ │ │ ├── lfsr.v │ │ │ ├── mii_phy_if.v │ │ │ ├── oddr.v │ │ │ ├── ptp_clock.v │ │ │ ├── ptp_clock_cdc.v │ │ │ ├── ptp_perout.v │ │ │ ├── ptp_tag_insert.v │ │ │ ├── ptp_ts_extract.v │ │ │ ├── rgmii_phy_if.v │ │ │ ├── ssio_ddr_in.v │ │ │ ├── ssio_ddr_in_diff.v │ │ │ ├── ssio_ddr_out.v │ │ │ ├── ssio_ddr_out_diff.v │ │ │ ├── ssio_sdr_in.v │ │ │ ├── ssio_sdr_in_diff.v │ │ │ ├── ssio_sdr_out.v │ │ │ ├── ssio_sdr_out_diff.v │ │ │ ├── udp.v │ │ │ ├── udp_64.v │ │ │ ├── udp_arb_mux.v │ │ │ ├── udp_checksum_gen.v │ │ │ ├── udp_checksum_gen_64.v │ │ │ ├── udp_complete.v │ │ │ ├── udp_complete_64.v │ │ │ ├── udp_demux.v │ │ │ ├── udp_ip_rx.v │ │ │ ├── udp_ip_rx_64.v │ │ │ ├── udp_ip_tx.v │ │ │ ├── udp_ip_tx_64.v │ │ │ ├── udp_mux.v │ │ │ ├── xgmii_baser_dec_64.v │ │ │ ├── xgmii_baser_enc_64.v │ │ │ ├── xgmii_deinterleave.v │ │ │ └── xgmii_interleave.v │ │ ├── scripts │ │ │ ├── dev-netns-shell.sh │ │ │ └── udp_test.py │ │ ├── syn │ │ │ ├── quartus │ │ │ │ ├── eth_mac_1g_gmii.sdc │ │ │ │ ├── eth_mac_1g_rgmii.sdc │ │ │ │ ├── gmii_phy_if.sdc │ │ │ │ ├── mii_phy_if.sdc │ │ │ │ ├── rgmii_io.sdc │ │ │ │ └── rgmii_phy_if.sdc │ │ │ ├── quartus_pro │ │ │ │ ├── eth_mac_1g_gmii.sdc │ │ │ │ ├── eth_mac_1g_rgmii.sdc │ │ │ │ ├── eth_mac_fifo.sdc │ │ │ │ ├── gmii_phy_if.sdc │ │ │ │ ├── mii_phy_if.sdc │ │ │ │ └── rgmii_phy_if.sdc │ │ │ └── vivado │ │ │ │ ├── eth_mac_1g_gmii.tcl │ │ │ │ ├── eth_mac_1g_rgmii.tcl │ │ │ │ ├── eth_mac_fifo.tcl │ │ │ │ ├── gmii_phy_if.tcl │ │ │ │ ├── mii_phy_if.tcl │ │ │ │ ├── ptp_clock_cdc.tcl │ │ │ │ └── rgmii_phy_if.tcl │ │ ├── tb │ │ │ ├── arp │ │ │ │ ├── Makefile │ │ │ │ └── test_arp.py │ │ │ ├── arp_cache │ │ │ │ ├── Makefile │ │ │ │ └── test_arp_cache.py │ │ │ ├── arp_ep.py │ │ │ ├── arp_eth_rx │ │ │ │ ├── Makefile │ │ │ │ └── test_arp_eth_rx.py │ │ │ ├── arp_eth_tx │ │ │ │ ├── Makefile │ │ │ │ └── test_arp_eth_tx.py │ │ │ ├── axis_ep.py │ │ │ ├── axis_gmii_rx │ │ │ │ ├── Makefile │ │ │ │ └── test_axis_gmii_rx.py │ │ │ ├── axis_gmii_tx │ │ │ │ ├── Makefile │ │ │ │ └── test_axis_gmii_tx.py │ │ │ ├── axis_xgmii_rx_32 │ │ │ │ ├── Makefile │ │ │ │ └── test_axis_xgmii_rx_32.py │ │ │ ├── axis_xgmii_rx_64 │ │ │ │ ├── Makefile │ │ │ │ └── test_axis_xgmii_rx_64.py │ │ │ ├── axis_xgmii_tx_32 │ │ │ │ ├── Makefile │ │ │ │ └── test_axis_xgmii_tx_32.py │ │ │ ├── axis_xgmii_tx_64 │ │ │ │ ├── Makefile │ │ │ │ └── test_axis_xgmii_tx_64.py │ │ │ ├── baser_serdes_ep.py │ │ │ ├── eth_axis_rx │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_axis_rx.py │ │ │ ├── eth_axis_tx │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_axis_tx.py │ │ │ ├── eth_ep.py │ │ │ ├── eth_mac_10g │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_10g.py │ │ │ ├── eth_mac_10g_fifo │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_10g_fifo.py │ │ │ ├── eth_mac_1g │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_1g.py │ │ │ ├── eth_mac_1g_fifo │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_1g_fifo.py │ │ │ ├── eth_mac_1g_gmii │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_1g_gmii.py │ │ │ ├── eth_mac_1g_gmii_fifo │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_1g_gmii_fifo.py │ │ │ ├── eth_mac_1g_rgmii │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_1g_rgmii.py │ │ │ ├── eth_mac_1g_rgmii_fifo │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_1g_rgmii_fifo.py │ │ │ ├── eth_mac_mii │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_mii.py │ │ │ ├── eth_mac_mii_fifo │ │ │ │ ├── Makefile │ │ │ │ └── test_eth_mac_mii_fifo.py │ │ │ ├── gmii_ep.py │ │ │ ├── ip_ep.py │ │ │ ├── mii_ep.py │ │ │ ├── ptp.py │ │ │ ├── ptp_clock │ │ │ │ ├── Makefile │ │ │ │ └── test_ptp_clock.py │ │ │ ├── ptp_clock_cdc │ │ │ │ ├── Makefile │ │ │ │ └── test_ptp_clock_cdc.py │ │ │ ├── ptp_perout │ │ │ │ ├── Makefile │ │ │ │ └── test_ptp_perout.py │ │ │ ├── rgmii_ep.py │ │ │ ├── test_arp.py │ │ │ ├── test_arp.v │ │ │ ├── test_arp_64.py │ │ │ ├── test_arp_64.v │ │ │ ├── test_arp_cache.py │ │ │ ├── test_arp_cache.v │ │ │ ├── test_arp_eth_rx.py │ │ │ ├── test_arp_eth_rx.v │ │ │ ├── test_arp_eth_rx_64.py │ │ │ ├── test_arp_eth_rx_64.v │ │ │ ├── test_arp_eth_tx.py │ │ │ ├── test_arp_eth_tx.v │ │ │ ├── test_arp_eth_tx_64.py │ │ │ ├── test_arp_eth_tx_64.v │ │ │ ├── test_axis_baser_rx_64.py │ │ │ ├── test_axis_baser_rx_64.v │ │ │ ├── test_axis_baser_tx_64.py │ │ │ ├── test_axis_baser_tx_64.v │ │ │ ├── test_axis_eth_fcs.py │ │ │ ├── test_axis_eth_fcs.v │ │ │ ├── test_axis_eth_fcs_64.py │ │ │ ├── test_axis_eth_fcs_64.v │ │ │ ├── test_axis_eth_fcs_check.py │ │ │ ├── test_axis_eth_fcs_check.v │ │ │ ├── test_axis_eth_fcs_check_64.py │ │ │ ├── test_axis_eth_fcs_check_64.v │ │ │ ├── test_axis_eth_fcs_insert.py │ │ │ ├── test_axis_eth_fcs_insert.v │ │ │ ├── test_axis_eth_fcs_insert_64.py │ │ │ ├── test_axis_eth_fcs_insert_64.v │ │ │ ├── test_axis_eth_fcs_insert_64_pad.py │ │ │ ├── test_axis_eth_fcs_insert_64_pad.v │ │ │ ├── test_axis_eth_fcs_insert_pad.py │ │ │ ├── test_axis_eth_fcs_insert_pad.v │ │ │ ├── test_axis_gmii_rx.py │ │ │ ├── test_axis_gmii_rx.v │ │ │ ├── test_axis_gmii_tx.py │ │ │ ├── test_axis_gmii_tx.v │ │ │ ├── test_axis_xgmii_rx_32.py │ │ │ ├── test_axis_xgmii_rx_32.v │ │ │ ├── test_axis_xgmii_rx_64.py │ │ │ ├── test_axis_xgmii_rx_64.v │ │ │ ├── test_axis_xgmii_tx_32.py │ │ │ ├── test_axis_xgmii_tx_32.v │ │ │ ├── test_axis_xgmii_tx_64.py │ │ │ ├── test_axis_xgmii_tx_64.v │ │ │ ├── test_eth_arb_mux_4.py │ │ │ ├── test_eth_arb_mux_4.v │ │ │ ├── test_eth_arb_mux_64_4.py │ │ │ ├── test_eth_arb_mux_64_4.v │ │ │ ├── test_eth_axis_rx.py │ │ │ ├── test_eth_axis_rx.v │ │ │ ├── test_eth_axis_rx_64.py │ │ │ ├── test_eth_axis_rx_64.v │ │ │ ├── test_eth_axis_tx.py │ │ │ ├── test_eth_axis_tx.v │ │ │ ├── test_eth_axis_tx_64.py │ │ │ ├── test_eth_axis_tx_64.v │ │ │ ├── test_eth_demux_4.py │ │ │ ├── test_eth_demux_4.v │ │ │ ├── test_eth_demux_64_4.py │ │ │ ├── test_eth_demux_64_4.v │ │ │ ├── test_eth_mac_10g_32.py │ │ │ ├── test_eth_mac_10g_32.v │ │ │ ├── test_eth_mac_10g_64.py │ │ │ ├── test_eth_mac_10g_64.v │ │ │ ├── test_eth_mac_10g_fifo_32.py │ │ │ ├── test_eth_mac_10g_fifo_32.v │ │ │ ├── test_eth_mac_10g_fifo_64.py │ │ │ ├── test_eth_mac_10g_fifo_64.v │ │ │ ├── test_eth_mac_10g_fifo_ptp_32.py │ │ │ ├── test_eth_mac_10g_fifo_ptp_32.v │ │ │ ├── test_eth_mac_10g_fifo_ptp_64.py │ │ │ ├── test_eth_mac_10g_fifo_ptp_64.v │ │ │ ├── test_eth_mac_1g.py │ │ │ ├── test_eth_mac_1g.v │ │ │ ├── test_eth_mac_1g_fifo.py │ │ │ ├── test_eth_mac_1g_fifo.v │ │ │ ├── test_eth_mac_1g_gmii.py │ │ │ ├── test_eth_mac_1g_gmii.v │ │ │ ├── test_eth_mac_1g_gmii_fifo.py │ │ │ ├── test_eth_mac_1g_gmii_fifo.v │ │ │ ├── test_eth_mac_1g_rgmii.py │ │ │ ├── test_eth_mac_1g_rgmii.v │ │ │ ├── test_eth_mac_1g_rgmii_fifo.py │ │ │ ├── test_eth_mac_1g_rgmii_fifo.v │ │ │ ├── test_eth_mac_mii.py │ │ │ ├── test_eth_mac_mii.v │ │ │ ├── test_eth_mac_mii_fifo.py │ │ │ ├── test_eth_mac_mii_fifo.v │ │ │ ├── test_eth_mac_phy_10g.py │ │ │ ├── test_eth_mac_phy_10g.v │ │ │ ├── test_eth_mac_phy_10g_fifo.py │ │ │ ├── test_eth_mac_phy_10g_fifo.v │ │ │ ├── test_eth_mac_phy_10g_fifo_ptp.py │ │ │ ├── test_eth_mac_phy_10g_fifo_ptp.v │ │ │ ├── test_eth_mux_4.py │ │ │ ├── test_eth_mux_4.v │ │ │ ├── test_eth_mux_64_4.py │ │ │ ├── test_eth_mux_64_4.v │ │ │ ├── test_eth_phy_10g_64.py │ │ │ ├── test_eth_phy_10g_64.v │ │ │ ├── test_eth_phy_10g_rx_64.py │ │ │ ├── test_eth_phy_10g_rx_64.v │ │ │ ├── test_eth_phy_10g_tx_64.py │ │ │ ├── test_eth_phy_10g_tx_64.v │ │ │ ├── test_ip.py │ │ │ ├── test_ip.v │ │ │ ├── test_ip_64.py │ │ │ ├── test_ip_64.v │ │ │ ├── test_ip_arb_mux_4.py │ │ │ ├── test_ip_arb_mux_4.v │ │ │ ├── test_ip_arb_mux_64_4.py │ │ │ ├── test_ip_arb_mux_64_4.v │ │ │ ├── test_ip_complete.py │ │ │ ├── test_ip_complete.v │ │ │ ├── test_ip_complete_64.py │ │ │ ├── test_ip_complete_64.v │ │ │ ├── test_ip_demux_4.py │ │ │ ├── test_ip_demux_4.v │ │ │ ├── test_ip_demux_64_4.py │ │ │ ├── test_ip_demux_64_4.v │ │ │ ├── test_ip_eth_rx.py │ │ │ ├── test_ip_eth_rx.v │ │ │ ├── test_ip_eth_rx_64.py │ │ │ ├── test_ip_eth_rx_64.v │ │ │ ├── test_ip_eth_tx.py │ │ │ ├── test_ip_eth_tx.v │ │ │ ├── test_ip_eth_tx_64.py │ │ │ ├── test_ip_eth_tx_64.v │ │ │ ├── test_ip_mux_4.py │ │ │ ├── test_ip_mux_4.v │ │ │ ├── test_ip_mux_64_4.py │ │ │ ├── test_ip_mux_64_4.v │ │ │ ├── test_ptp_clock.py │ │ │ ├── test_ptp_clock.v │ │ │ ├── test_ptp_clock_cdc_64.py │ │ │ ├── test_ptp_clock_cdc_64.v │ │ │ ├── test_ptp_clock_cdc_96.py │ │ │ ├── test_ptp_clock_cdc_96.v │ │ │ ├── test_ptp_perout.py │ │ │ ├── test_ptp_perout.v │ │ │ ├── test_udp.py │ │ │ ├── test_udp.v │ │ │ ├── test_udp_64.py │ │ │ ├── test_udp_64.v │ │ │ ├── test_udp_arb_mux_4.py │ │ │ ├── test_udp_arb_mux_4.v │ │ │ ├── test_udp_arb_mux_64_4.py │ │ │ ├── test_udp_arb_mux_64_4.v │ │ │ ├── test_udp_checksum_gen.py │ │ │ ├── test_udp_checksum_gen.v │ │ │ ├── test_udp_checksum_gen_64.py │ │ │ ├── test_udp_checksum_gen_64.v │ │ │ ├── test_udp_complete.py │ │ │ ├── test_udp_complete.v │ │ │ ├── test_udp_complete_64.py │ │ │ ├── test_udp_complete_64.v │ │ │ ├── test_udp_demux_4.py │ │ │ ├── test_udp_demux_4.v │ │ │ ├── test_udp_demux_64_4.py │ │ │ ├── test_udp_demux_64_4.v │ │ │ ├── test_udp_ip_rx.py │ │ │ ├── test_udp_ip_rx.v │ │ │ ├── test_udp_ip_rx_64.py │ │ │ ├── test_udp_ip_rx_64.v │ │ │ ├── test_udp_ip_tx.py │ │ │ ├── test_udp_ip_tx.v │ │ │ ├── test_udp_ip_tx_64.py │ │ │ ├── test_udp_ip_tx_64.v │ │ │ ├── test_udp_mux_4.py │ │ │ ├── test_udp_mux_4.v │ │ │ ├── test_udp_mux_64_4.py │ │ │ ├── test_udp_mux_64_4.v │ │ │ ├── test_xgmii_baser_dec_64.py │ │ │ ├── test_xgmii_baser_dec_64.v │ │ │ ├── test_xgmii_baser_enc_64.py │ │ │ ├── test_xgmii_baser_enc_64.v │ │ │ ├── udp_ep.py │ │ │ └── xgmii_ep.py │ │ └── tox.ini │ ├── pcie │ │ ├── .github │ │ │ └── workflows │ │ │ │ └── regression-tests.yml │ │ ├── .gitignore │ │ ├── .test_durations │ │ ├── AUTHORS │ │ ├── COPYING │ │ ├── README │ │ ├── README.md │ │ ├── dma_block.svg │ │ ├── example │ │ │ ├── ADM_PCIE_9V3 │ │ │ │ └── fpga_axi_x8 │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU200 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU250 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU280 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4c_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── AU50 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4c_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ExaNIC_X10 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie3_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ExaNIC_X25 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── VCU108 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie3_ultrascale_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── VCU118 │ │ │ │ └── fpga_axi_x8 │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── VCU1525 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── ZCU106 │ │ │ │ └── fpga_axi │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── README.md │ │ │ │ │ ├── common │ │ │ │ │ └── vivado.mk │ │ │ │ │ ├── driver │ │ │ │ │ ├── fpga.xdc │ │ │ │ │ ├── fpga │ │ │ │ │ └── Makefile │ │ │ │ │ ├── ip │ │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ │ ├── lib │ │ │ │ │ └── pcie │ │ │ │ │ ├── rtl │ │ │ │ │ ├── axi_ram.v │ │ │ │ │ ├── axis_register.v │ │ │ │ │ ├── debounce_switch.v │ │ │ │ │ ├── fpga.v │ │ │ │ │ ├── fpga_core.v │ │ │ │ │ ├── sync_reset.v │ │ │ │ │ └── sync_signal.v │ │ │ │ │ └── tb │ │ │ │ │ └── fpga_core │ │ │ │ │ ├── Makefile │ │ │ │ │ └── test_fpga_core.py │ │ │ ├── common │ │ │ │ └── driver │ │ │ │ │ └── example │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── example_driver.c │ │ │ │ │ └── example_driver.h │ │ │ └── fb2CG │ │ │ │ └── fpga_axi │ │ │ │ ├── Makefile │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── driver │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── ip │ │ │ │ └── pcie4_uscale_plus_0.tcl │ │ │ │ ├── led.tcl │ │ │ │ ├── lib │ │ │ │ └── pcie │ │ │ │ ├── rtl │ │ │ │ ├── axi_ram.v │ │ │ │ ├── axis_register.v │ │ │ │ ├── fpga.v │ │ │ │ ├── fpga_core.v │ │ │ │ ├── led_sreg_driver.v │ │ │ │ ├── sync_reset.v │ │ │ │ └── sync_signal.v │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ └── test_fpga_core.py │ │ ├── rtl │ │ │ ├── arbiter.v │ │ │ ├── axis_arb_mux.v │ │ │ ├── dma_client_axis_sink.v │ │ │ ├── dma_client_axis_source.v │ │ │ ├── dma_if_desc_mux.v │ │ │ ├── dma_if_mux.v │ │ │ ├── dma_if_mux_rd.v │ │ │ ├── dma_if_mux_wr.v │ │ │ ├── dma_if_pcie.v │ │ │ ├── dma_if_pcie_rd.v │ │ │ ├── dma_if_pcie_us.v │ │ │ ├── dma_if_pcie_us_rd.v │ │ │ ├── dma_if_pcie_us_wr.v │ │ │ ├── dma_if_pcie_wr.v │ │ │ ├── dma_psdpram.v │ │ │ ├── dma_psdpram_async.v │ │ │ ├── dma_ram_demux.v │ │ │ ├── dma_ram_demux_rd.v │ │ │ ├── dma_ram_demux_wr.v │ │ │ ├── pcie_axi_dma_desc_mux.v │ │ │ ├── pcie_axil_master.v │ │ │ ├── pcie_tlp_demux.v │ │ │ ├── pcie_tlp_demux_bar.v │ │ │ ├── pcie_tlp_mux.v │ │ │ ├── pcie_us_axi_dma.v │ │ │ ├── pcie_us_axi_dma_rd.v │ │ │ ├── pcie_us_axi_dma_wr.v │ │ │ ├── pcie_us_axi_master.v │ │ │ ├── pcie_us_axi_master_rd.v │ │ │ ├── pcie_us_axi_master_wr.v │ │ │ ├── pcie_us_axil_master.v │ │ │ ├── pcie_us_axis_cq_demux.v │ │ │ ├── pcie_us_axis_rc_demux.v │ │ │ ├── pcie_us_cfg.v │ │ │ ├── pcie_us_if.v │ │ │ ├── pcie_us_if_cc.v │ │ │ ├── pcie_us_if_cq.v │ │ │ ├── pcie_us_if_rc.v │ │ │ ├── pcie_us_if_rq.v │ │ │ ├── pcie_us_msi.v │ │ │ ├── priority_encoder.v │ │ │ └── pulse_merge.v │ │ ├── scripts │ │ │ ├── pcie_disable_fatal_err.sh │ │ │ ├── pcie_ext_tag.sh │ │ │ ├── pcie_flr.sh │ │ │ ├── pcie_hot_reset.sh │ │ │ ├── pcie_rescan.sh │ │ │ ├── pcie_reset.sh │ │ │ └── pcie_set_speed.sh │ │ ├── tb │ │ │ ├── Makefile │ │ │ ├── axi.py │ │ │ ├── axil.py │ │ │ ├── axis_ep.py │ │ │ ├── dma_client_axis_sink │ │ │ │ ├── Makefile │ │ │ │ ├── dma_psdp_ram.py │ │ │ │ └── test_dma_client_axis_sink.py │ │ │ ├── dma_client_axis_source │ │ │ │ ├── Makefile │ │ │ │ ├── dma_psdp_ram.py │ │ │ │ └── test_dma_client_axis_source.py │ │ │ ├── dma_if_pcie_rd │ │ │ │ ├── Makefile │ │ │ │ ├── dma_psdp_ram.py │ │ │ │ ├── pcie_if.py │ │ │ │ └── test_dma_if_pcie_rd.py │ │ │ ├── dma_if_pcie_us │ │ │ │ ├── Makefile │ │ │ │ ├── dma_psdp_ram.py │ │ │ │ └── test_dma_if_pcie_us.py │ │ │ ├── dma_if_pcie_us_rd │ │ │ │ ├── Makefile │ │ │ │ ├── dma_psdp_ram.py │ │ │ │ └── test_dma_if_pcie_us_rd.py │ │ │ ├── dma_if_pcie_us_wr │ │ │ │ ├── Makefile │ │ │ │ ├── dma_psdp_ram.py │ │ │ │ └── test_dma_if_pcie_us_wr.py │ │ │ ├── dma_if_pcie_wr │ │ │ │ ├── Makefile │ │ │ │ ├── dma_psdp_ram.py │ │ │ │ ├── pcie_if.py │ │ │ │ └── test_dma_if_pcie_wr.py │ │ │ ├── dma_psdp_ram.py │ │ │ ├── dma_ram.py │ │ │ ├── pcie.py │ │ │ ├── pcie_axil_master │ │ │ │ ├── Makefile │ │ │ │ ├── pcie_if.py │ │ │ │ └── test_pcie_axil_master.py │ │ │ ├── pcie_if.py │ │ │ ├── pcie_us.py │ │ │ ├── pcie_us_axi_dma │ │ │ │ ├── Makefile │ │ │ │ └── test_pcie_us_axi_dma.py │ │ │ ├── pcie_us_axi_dma_rd │ │ │ │ ├── Makefile │ │ │ │ └── test_pcie_us_axi_dma_rd.py │ │ │ ├── pcie_us_axi_dma_wr │ │ │ │ ├── Makefile │ │ │ │ └── test_pcie_us_axi_dma_wr.py │ │ │ ├── pcie_us_axi_master │ │ │ │ ├── Makefile │ │ │ │ └── test_pcie_us_axi_master.py │ │ │ ├── pcie_us_axi_master_rd │ │ │ │ ├── Makefile │ │ │ │ └── test_pcie_us_axi_master_rd.py │ │ │ ├── pcie_us_axi_master_wr │ │ │ │ ├── Makefile │ │ │ │ └── test_pcie_us_axi_master_wr.py │ │ │ ├── pcie_us_axil_master │ │ │ │ ├── Makefile │ │ │ │ └── test_pcie_us_axil_master.py │ │ │ ├── pcie_us_if │ │ │ │ ├── Makefile │ │ │ │ ├── pcie_if.py │ │ │ │ └── test_pcie_us_if.py │ │ │ ├── pcie_usp.py │ │ │ ├── test_dma_client_axis_sink_128_64.py │ │ │ ├── test_dma_client_axis_sink_128_64.v │ │ │ ├── test_dma_client_axis_sink_512_64.py │ │ │ ├── test_dma_client_axis_sink_512_64.v │ │ │ ├── test_dma_client_axis_source_128_64.py │ │ │ ├── test_dma_client_axis_source_128_64.v │ │ │ ├── test_dma_client_axis_source_512_64.py │ │ │ ├── test_dma_client_axis_source_512_64.v │ │ │ ├── test_dma_if_pcie_us_256.py │ │ │ ├── test_dma_if_pcie_us_256.v │ │ │ ├── test_dma_if_pcie_us_rd_128.py │ │ │ ├── test_dma_if_pcie_us_rd_128.v │ │ │ ├── test_dma_if_pcie_us_rd_256.py │ │ │ ├── test_dma_if_pcie_us_rd_256.v │ │ │ ├── test_dma_if_pcie_us_rd_512.py │ │ │ ├── test_dma_if_pcie_us_rd_512.v │ │ │ ├── test_dma_if_pcie_us_rd_64.py │ │ │ ├── test_dma_if_pcie_us_rd_64.v │ │ │ ├── test_dma_if_pcie_us_wr_128.py │ │ │ ├── test_dma_if_pcie_us_wr_128.v │ │ │ ├── test_dma_if_pcie_us_wr_256.py │ │ │ ├── test_dma_if_pcie_us_wr_256.v │ │ │ ├── test_dma_if_pcie_us_wr_512.py │ │ │ ├── test_dma_if_pcie_us_wr_512.v │ │ │ ├── test_dma_if_pcie_us_wr_64.py │ │ │ ├── test_dma_if_pcie_us_wr_64.v │ │ │ ├── test_pcie.py │ │ │ ├── test_pcie_us.py │ │ │ ├── test_pcie_us_axi_dma_256.py │ │ │ ├── test_pcie_us_axi_dma_256.v │ │ │ ├── test_pcie_us_axi_dma_rd_128.py │ │ │ ├── test_pcie_us_axi_dma_rd_128.v │ │ │ ├── test_pcie_us_axi_dma_rd_256.py │ │ │ ├── test_pcie_us_axi_dma_rd_256.v │ │ │ ├── test_pcie_us_axi_dma_rd_512.py │ │ │ ├── test_pcie_us_axi_dma_rd_512.v │ │ │ ├── test_pcie_us_axi_dma_rd_64.py │ │ │ ├── test_pcie_us_axi_dma_rd_64.v │ │ │ ├── test_pcie_us_axi_dma_wr_128.py │ │ │ ├── test_pcie_us_axi_dma_wr_128.v │ │ │ ├── test_pcie_us_axi_dma_wr_256.py │ │ │ ├── test_pcie_us_axi_dma_wr_256.v │ │ │ ├── test_pcie_us_axi_dma_wr_512.py │ │ │ ├── test_pcie_us_axi_dma_wr_512.v │ │ │ ├── test_pcie_us_axi_dma_wr_64.py │ │ │ ├── test_pcie_us_axi_dma_wr_64.v │ │ │ ├── test_pcie_us_axi_master_128.py │ │ │ ├── test_pcie_us_axi_master_128.v │ │ │ ├── test_pcie_us_axi_master_256.py │ │ │ ├── test_pcie_us_axi_master_256.v │ │ │ ├── test_pcie_us_axi_master_64.py │ │ │ ├── test_pcie_us_axi_master_64.v │ │ │ ├── test_pcie_us_axi_master_rd_128.py │ │ │ ├── test_pcie_us_axi_master_rd_128.v │ │ │ ├── test_pcie_us_axi_master_rd_256.py │ │ │ ├── test_pcie_us_axi_master_rd_256.v │ │ │ ├── test_pcie_us_axi_master_rd_512.py │ │ │ ├── test_pcie_us_axi_master_rd_512.v │ │ │ ├── test_pcie_us_axi_master_rd_64.py │ │ │ ├── test_pcie_us_axi_master_rd_64.v │ │ │ ├── test_pcie_us_axi_master_wr_128.py │ │ │ ├── test_pcie_us_axi_master_wr_128.v │ │ │ ├── test_pcie_us_axi_master_wr_256.py │ │ │ ├── test_pcie_us_axi_master_wr_256.v │ │ │ ├── test_pcie_us_axi_master_wr_512.py │ │ │ ├── test_pcie_us_axi_master_wr_512.v │ │ │ ├── test_pcie_us_axi_master_wr_64.py │ │ │ ├── test_pcie_us_axi_master_wr_64.v │ │ │ ├── test_pcie_us_axil_master_128.py │ │ │ ├── test_pcie_us_axil_master_128.v │ │ │ ├── test_pcie_us_axil_master_256.py │ │ │ ├── test_pcie_us_axil_master_256.v │ │ │ ├── test_pcie_us_axil_master_512.py │ │ │ ├── test_pcie_us_axil_master_512.v │ │ │ ├── test_pcie_us_axil_master_64.py │ │ │ ├── test_pcie_us_axil_master_64.v │ │ │ └── test_pcie_usp.py │ │ └── tox.ini │ ├── update-axi.sh │ ├── update-eth.sh │ └── update-pcie.sh └── mqnic │ ├── ADM_PCIE_9V3 │ ├── fpga_100g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── fpga_tdma │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── cmac_usplus_0.tcl │ │ │ ├── cmac_usplus_1.tcl │ │ │ ├── ila_0.tcl │ │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ ├── test_fpga_core.py │ │ │ └── wave.gtkw │ ├── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── fpga_tdma │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── gtwizard_ultrascale_0.tcl │ │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ └── test_fpga_core.py │ └── fpga_25g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── fpga_tdma │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── AU200 │ ├── fpga_100g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── cfgmclk.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── cmac_usplus_0.tcl │ │ │ ├── cmac_usplus_1.tcl │ │ │ ├── cms.tcl │ │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ └── test_fpga_core.py │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── cfgmclk.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── cms.tcl │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── AU250 │ ├── fpga_100g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── cfgmclk.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── cmac_usplus_0.tcl │ │ │ ├── cmac_usplus_1.tcl │ │ │ ├── cms.tcl │ │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ └── test_fpga_core.py │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── cfgmclk.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── cms.tcl │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── AU280 │ ├── fpga_100g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── cmac_usplus_0.tcl │ │ │ ├── cmac_usplus_1.tcl │ │ │ ├── cms.tcl │ │ │ ├── ila_0.tcl │ │ │ └── pcie4c_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ ├── signal.gtkw │ │ │ └── test_fpga_core.py │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── cms.tcl │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4c_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ ├── common │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── AU50 │ ├── fpga_100g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── cmac_usplus_0.tcl │ │ │ ├── cms.tcl │ │ │ └── pcie4c_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ └── test_fpga_core.py │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── cms.tcl │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4c_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ ├── common │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── ExaNIC_X10 │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie3_ultrascale_0.tcl │ │ ├── lib │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── ExaNIC_X25 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── NetFPGA_SUME │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── pcie3_7x_0.tcl │ │ ├── ten_gig_eth_pcs_pma_0.tcl │ │ └── ten_gig_eth_pcs_pma_1.tcl │ │ ├── lib │ │ ├── pcie.xdc │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── i2c_master.v │ │ ├── si5324_i2c_init.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── VCU108 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie3_ultrascale_0.tcl │ │ ├── lib │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── VCU118 │ ├── fpga_100g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── cmac_usplus_0.tcl │ │ │ ├── cmac_usplus_1.tcl │ │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ └── test_fpga_core.py │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── VCU1525 │ ├── fpga_100g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── cfgmclk.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── config.tcl │ │ ├── ip │ │ │ ├── cmac_usplus_0.tcl │ │ │ ├── cmac_usplus_1.tcl │ │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ │ ├── common │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── mqnic.py │ │ │ └── test_fpga_core.py │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── boot.xdc │ │ ├── cfgmclk.xdc │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── placement.xdc │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── ZCU106 │ └── fpga_pcie │ │ ├── Makefile │ │ ├── README.md │ │ ├── app │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── lib │ │ ├── rtl │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ └── fb2CG │ ├── fpga_100g │ ├── Makefile │ ├── README.md │ ├── app │ ├── boot.xdc │ ├── common │ │ └── vivado.mk │ ├── fpga.xdc │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ ├── fpga_tdma │ │ ├── Makefile │ │ └── config.tcl │ ├── ip │ │ ├── cmac_usplus_0.tcl │ │ ├── cmac_usplus_1.tcl │ │ └── pcie4_uscale_plus_0.tcl │ ├── led.tcl │ ├── lib │ ├── placement.xdc │ ├── rtl │ │ ├── bmc_spi.v │ │ ├── common │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── led_sreg_driver.v │ │ └── sync_signal.v │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ ├── fpga_10g │ ├── Makefile │ ├── README.md │ ├── app │ ├── boot.xdc │ ├── common │ │ └── vivado.mk │ ├── fpga.xdc │ ├── fpga │ │ ├── Makefile │ │ └── config.tcl │ ├── fpga_tdma │ │ ├── Makefile │ │ └── config.tcl │ ├── ip │ │ ├── gtwizard_ultrascale_0.tcl │ │ └── pcie4_uscale_plus_0.tcl │ ├── led.tcl │ ├── lib │ ├── placement.xdc │ ├── rtl │ │ ├── bmc_spi.v │ │ ├── common │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── led_sreg_driver.v │ │ └── sync_signal.v │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ ├── mqnic.py │ │ └── test_fpga_core.py │ └── fpga_25g │ ├── Makefile │ ├── README.md │ ├── app │ ├── boot.xdc │ ├── common │ └── vivado.mk │ ├── fpga.xdc │ ├── fpga │ ├── Makefile │ └── config.tcl │ ├── fpga_tdma │ ├── Makefile │ └── config.tcl │ ├── ip │ ├── gtwizard_ultrascale_0.tcl │ └── pcie4_uscale_plus_0.tcl │ ├── led.tcl │ ├── lib │ ├── placement.xdc │ ├── rtl │ ├── bmc_spi.v │ ├── common │ ├── fpga.v │ ├── fpga_core.v │ ├── led_sreg_driver.v │ └── sync_signal.v │ └── tb │ └── fpga_core │ ├── Makefile │ ├── mqnic.py │ └── test_fpga_core.py ├── modules └── mqnic │ ├── Makefile │ ├── mqnic.h │ ├── mqnic_board.c │ ├── mqnic_cq.c │ ├── mqnic_dev.c │ ├── mqnic_eq.c │ ├── mqnic_ethtool.c │ ├── mqnic_hw.h │ ├── mqnic_i2c.c │ ├── mqnic_ioctl.h │ ├── mqnic_main.c │ ├── mqnic_netdev.c │ ├── mqnic_port.c │ ├── mqnic_ptp.c │ ├── mqnic_rx.c │ ├── mqnic_tx.c │ └── user │ ├── Makefile │ ├── test_user │ └── test_user.c ├── tox.ini └── utils ├── Makefile ├── bitfile.c ├── bitfile.h ├── flash.c ├── flash.h ├── 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