├── .github └── workflows │ └── dockerimage.yml ├── .gitignore ├── .gitlab-ci.yml ├── LICENSE ├── README.md ├── info.rkt ├── scripts ├── Dockerfile └── Makefile.lib ├── serval ├── arm32.rkt ├── arm32 │ ├── base.rkt │ ├── interp.rkt │ └── interp │ │ ├── branch-immediate.rkt │ │ ├── common.rkt │ │ ├── define.rkt │ │ ├── extend-and-add.rkt │ │ ├── integer-data-processing-immediate.rkt │ │ ├── integer-data-processing-register.rkt │ │ ├── integer-test-and-compare-immediate.rkt │ │ ├── integer-test-and-compare-register.rkt │ │ ├── load-store-dual-half-signed-byte-immediate.rkt │ │ ├── load-store-multiple.rkt │ │ ├── load-store-word-unsigned-byte-immediate.rkt │ │ ├── logical-arithmetic-immediate.rkt │ │ ├── logical-arithmetic-register-shifted-register.rkt │ │ ├── logical-arithmetic-register.rkt │ │ ├── miscellaneous.rkt │ │ ├── move-halfword-immediate.rkt │ │ ├── multiply-and-accumulate.rkt │ │ ├── reverse.rkt │ │ └── signed-multiply-divide.rkt ├── arm64.rkt ├── arm64 │ ├── base.rkt │ ├── decode.rkt │ ├── interp.rkt │ └── interp │ │ ├── arithmetic-immediate.rkt │ │ ├── arithmetic-shifted-register.rkt │ │ ├── atomic.rkt │ │ ├── bit-operation.rkt │ │ ├── bitfield-move.rkt │ │ ├── common.rkt │ │ ├── conditional-branch.rkt │ │ ├── define.rkt │ │ ├── divide.rkt │ │ ├── load-store-register-pair.rkt │ │ ├── load-store-register.rkt │ │ ├── logical-immediate.rkt │ │ ├── logical-shifted-register.rkt │ │ ├── move-wide-immediate.rkt │ │ ├── multiply.rkt │ │ ├── shift-register.rkt │ │ ├── unconditional-branch-immediate.rkt │ │ └── unconditional-branch-register.rkt ├── bin │ └── serval-llvm.rkt ├── bpf.rkt ├── guide │ └── scribble │ │ ├── refs.scrbl │ │ └── serval.scrbl ├── info.rkt ├── lang │ ├── dwarf.rkt │ └── nm.rkt ├── lib │ ├── bvarith.rkt │ ├── core.rkt │ ├── cpu.rkt │ ├── debug.rkt │ ├── memmgr.rkt │ ├── memory │ │ ├── flat.rkt │ │ ├── manager.rkt │ │ ├── mblock.rkt │ │ ├── mregion.rkt │ │ └── typed-bv.rkt │ ├── solver.rkt │ ├── symopt.rkt │ ├── uf.rkt │ └── unittest.rkt ├── llvm.rkt ├── llvm │ ├── base.rkt │ ├── capi │ │ ├── core.rkt │ │ ├── irreader.rkt │ │ └── target.rkt │ ├── lang.rkt │ ├── parse.rkt │ └── print.rkt ├── riscv │ ├── base.rkt │ ├── decode.rkt │ ├── interp.rkt │ ├── interp │ │ ├── b-type.rkt │ │ ├── c-type.rkt │ │ ├── common.rkt │ │ ├── define.rkt │ │ ├── i-type.rkt │ │ ├── j-type.rkt │ │ ├── r-type.rkt │ │ ├── s-type.rkt │ │ └── u-type.rkt │ ├── objdump.rkt │ ├── pmp.rkt │ ├── shims.rkt │ ├── spec.rkt │ └── symopt.rkt ├── sha256.rkt ├── spec │ ├── ni.rkt │ ├── refcnt.rkt │ └── refinement.rkt ├── ubsan.rkt ├── unicorn.rkt ├── unicorn │ ├── arm.rkt │ ├── arm64.rkt │ ├── const │ │ ├── arm.rkt │ │ ├── arm64.rkt │ │ ├── unicorn.rkt │ │ └── x86.rkt │ ├── const_generator.py │ ├── engine.rkt │ ├── gen.sh │ ├── python │ │ ├── arm64_const.py │ │ ├── arm_const.py │ │ ├── unicorn_const.py │ │ └── x86_const.py │ └── x86.rkt ├── x86.rkt └── x86 │ ├── base.rkt │ ├── decode.rkt │ ├── interp.rkt │ ├── interp │ ├── adc.rkt │ ├── add.rkt │ ├── and.rkt │ ├── bswap.rkt │ ├── call.rkt │ ├── cmp.rkt │ ├── common.rkt │ ├── div.rkt │ ├── encoding.rkt │ ├── jcc.rkt │ ├── jmp.rkt │ ├── mov.rkt │ ├── movzx.rkt │ ├── mul.rkt │ ├── neg.rkt │ ├── or.rkt │ ├── pop.rkt │ ├── push.rkt │ ├── ret.rkt │ ├── rotate.rkt │ ├── sbb.rkt │ ├── shift.rkt │ ├── shld.rkt │ ├── shrd.rkt │ ├── sub.rkt │ ├── test.rkt │ ├── xchg.rkt │ └── xor.rkt │ └── register.rkt └── test ├── .gitignore ├── Makefile ├── arm32 ├── branch-immediate.rkt ├── extend-and-add.rkt ├── integer-data-processing-immediate.rkt ├── integer-data-processing-register.rkt ├── integer-test-and-compare-immediate.rkt ├── integer-test-and-compare-register.rkt ├── lib.rkt ├── logical-arithmetic-immediate.rkt ├── logical-arithmetic-register-shifted-register.rkt ├── logical-arithmetic-register.rkt ├── miscellaneous.rkt ├── move-halfword-immediate.rkt ├── multiply-and-accumulate.rkt ├── reverse.tex └── signed-multiply-divide.rkt ├── arm64 ├── arithmetic-immediate.rkt ├── arithmetic-shifted-register.rkt ├── bit-operation.rkt ├── bitfield-move.rkt ├── branches.rkt ├── lib.rkt ├── load-store-register.rkt ├── logical-immediate.rkt ├── logical-shifted-register.rkt ├── move-wide-immediate.rkt ├── multiply-and-divide.rkt └── shift-register.rkt ├── array.c ├── array.rkt ├── bext.c ├── bext.rkt ├── bpf ├── .gitignore ├── COPYING ├── bpf.mk ├── bpftests.rkt ├── gen.py ├── jmp32.rkt └── test_bpf.c ├── bugs.rkt ├── config.h ├── constantexpr.c ├── empty-dwarf.rkt ├── fd.c ├── fd.rkt ├── generated └── racket │ └── test ├── global.c ├── global.rkt ├── info.rkt ├── inttoptr.c ├── inttoptr.rkt ├── jumptable.c ├── jumptable.rkt ├── llvm.rkt ├── memset.c ├── memset.rkt ├── noop.S ├── noop.rkt ├── riscv-tests ├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── isa │ ├── .gitignore │ ├── Makefile │ ├── macros │ │ └── scalar │ │ │ └── test_macros.h │ ├── rv32mi │ │ ├── Makefrag │ │ ├── breakpoint.S │ │ ├── csr.S │ │ ├── illegal.S │ │ ├── ma_addr.S │ │ ├── ma_fetch.S │ │ ├── mcsr.S │ │ ├── sbreak.S │ │ ├── scall.S │ │ └── shamt.S │ ├── rv32si │ │ ├── Makefrag │ │ ├── csr.S │ │ ├── dirty.S │ │ ├── ma_fetch.S │ │ ├── sbreak.S │ │ ├── scall.S │ │ └── wfi.S │ ├── rv32ua │ │ ├── Makefrag │ │ ├── amoadd_w.S │ │ ├── amoand_w.S │ │ ├── amomax_w.S │ │ ├── amomaxu_w.S │ │ ├── amomin_w.S │ │ ├── amominu_w.S │ │ ├── amoor_w.S │ │ ├── amoswap_w.S │ │ ├── amoxor_w.S │ │ └── lrsc.S │ ├── rv32uc │ │ ├── Makefrag │ │ └── rvc.S │ ├── rv32ud │ │ ├── Makefrag │ │ ├── fadd.S │ │ ├── fclass.S │ │ ├── fcmp.S │ │ ├── fcvt.S │ │ ├── fcvt_w.S │ │ ├── fdiv.S │ │ ├── fmadd.S │ │ ├── fmin.S │ │ ├── ldst.S │ │ ├── move.S │ │ └── recoding.S │ ├── rv32uf │ │ ├── Makefrag │ │ ├── fadd.S │ │ ├── fclass.S │ │ ├── fcmp.S │ │ ├── fcvt.S │ │ ├── fcvt_w.S │ │ ├── fdiv.S │ │ ├── fmadd.S │ │ ├── fmin.S │ │ ├── ldst.S │ │ ├── move.S │ │ └── recoding.S │ ├── rv32ui │ │ ├── Makefrag │ │ ├── add.S │ │ ├── addi.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── sub.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S │ ├── rv32um │ │ ├── Makefrag │ │ ├── div.S │ │ ├── divu.S │ │ ├── mul.S │ │ ├── mulh.S │ │ ├── mulhsu.S │ │ ├── mulhu.S │ │ ├── rem.S │ │ └── remu.S │ ├── rv64mi │ │ ├── Makefrag │ │ ├── access.S │ │ ├── breakpoint.S │ │ ├── csr.S │ │ ├── illegal.S │ │ ├── ma_addr.S │ │ ├── ma_fetch.S │ │ ├── mcsr.S │ │ ├── sbreak.S │ │ └── scall.S │ ├── rv64si │ │ ├── Makefrag │ │ ├── csr.S │ │ ├── dirty.S │ │ ├── ma_fetch.S │ │ ├── sbreak.S │ │ ├── scall.S │ │ └── wfi.S │ ├── rv64ua │ │ ├── Makefrag │ │ ├── amoadd_d.S │ │ ├── amoadd_w.S │ │ ├── amoand_d.S │ │ ├── amoand_w.S │ │ ├── amomax_d.S │ │ ├── amomax_w.S │ │ ├── amomaxu_d.S │ │ ├── amomaxu_w.S │ │ ├── amomin_d.S │ │ ├── amomin_w.S │ │ ├── amominu_d.S │ │ ├── amominu_w.S │ │ ├── amoor_d.S │ │ ├── amoor_w.S │ │ ├── amoswap_d.S │ │ ├── amoswap_w.S │ │ ├── amoxor_d.S │ │ ├── amoxor_w.S │ │ └── lrsc.S │ ├── rv64uc │ │ ├── Makefrag │ │ └── rvc.S │ ├── rv64ud │ │ ├── Makefrag │ │ ├── fadd.S │ │ ├── fclass.S │ │ ├── fcmp.S │ │ ├── fcvt.S │ │ ├── fcvt_w.S │ │ ├── fdiv.S │ │ ├── fmadd.S │ │ ├── fmin.S │ │ ├── ldst.S │ │ ├── move.S │ │ ├── recoding.S │ │ └── structural.S │ ├── rv64uf │ │ ├── Makefrag │ │ ├── fadd.S │ │ ├── fclass.S │ │ ├── fcmp.S │ │ ├── fcvt.S │ │ ├── fcvt_w.S │ │ ├── fdiv.S │ │ ├── fmadd.S │ │ ├── fmin.S │ │ ├── ldst.S │ │ ├── move.S │ │ └── recoding.S │ ├── rv64ui │ │ ├── Makefrag │ │ ├── add.S │ │ ├── addi.S │ │ ├── addiw.S │ │ ├── addw.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── ld.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── lwu.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sd.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slliw.S │ │ ├── sllw.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── sraiw.S │ │ ├── sraw.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── srliw.S │ │ ├── srlw.S │ │ ├── sub.S │ │ ├── subw.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S │ └── rv64um │ │ ├── Makefrag │ │ ├── div.S │ │ ├── divu.S │ │ ├── divuw.S │ │ ├── divw.S │ │ ├── mul.S │ │ ├── mulh.S │ │ ├── mulhsu.S │ │ ├── mulhu.S │ │ ├── mulw.S │ │ ├── rem.S │ │ ├── remu.S │ │ ├── remuw.S │ │ └── remw.S ├── riscv-tests.mk ├── riscv-tests.rkt └── riscv_test.h ├── riscv.rkt ├── riscv └── test.rkt ├── test-flat.rkt ├── udiv.c ├── udiv.rkt └── x86 ├── adc.rkt ├── add.rkt ├── and.rkt ├── bswap.rkt ├── cmp.rkt ├── div.rkt ├── jcc.rkt ├── jmp.rkt ├── lib.rkt ├── mov.rkt ├── movzx.rkt ├── mul.rkt ├── neg.rkt ├── or.rkt ├── rotate.rkt ├── sbb.rkt ├── shift.rkt ├── shld.rkt ├── shrd.rkt ├── sub.rkt ├── test.rkt ├── xchg.rkt └── xor.rkt /.github/workflows/dockerimage.yml: -------------------------------------------------------------------------------- 1 | name: Docker Image CI 2 | 3 | on: [push] 4 | 5 | jobs: 6 | 7 | build: 8 | 9 | runs-on: ubuntu-latest 10 | 11 | steps: 12 | - uses: actions/checkout@v1 13 | - name: Build the Docker image 14 | env: 15 | COMMIT: ${{github.sha}} 16 | run: docker build . --file scripts/Dockerfile --tag "unsat/serval-tools:$COMMIT" 17 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # OS generated files # 2 | ###################### 3 | .DS_Store 4 | .DS_Store? 5 | ._* 6 | .Spotlight-V100 7 | .Trashes 8 | ehthumbs.db 9 | Thumbs.db 10 | 11 | **/doc 12 | **/doc/** 13 | **/bin/** 14 | **/compiled 15 | **/compiled/** 16 | *~ 17 | -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | image: unsat/serval-tools:latest 2 | 3 | variables: 4 | GIT_SUBMODULE_STRATEGY: recursive 5 | 6 | before_script: 7 | - raco pkg install --auto 8 | 9 | run-tests: 10 | script: 11 | # Add /usr/lib64 for libunicorn 12 | - export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/usr/lib64" 13 | - make -C test all 14 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 The UNSAT Group 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Serval 2 | 3 | This repository contains the actively developed version of 4 | Serval. It may be unstable and break backward compatibility 5 | with previous versions of Serval. We recommend using this version 6 | unless you have a specific need to use an older version. 7 | 8 | 9 | You can obtain older, stable snapshots of previous versions of Serval 10 | in two ways. Note that these snapshots are not under active development. 11 | 12 | - The [SOSP'19 artifact repository](https://github.com/uw-unsat/serval-sosp19) 13 | contains a version of Serval used to verify the security monitors described 14 | in the [paper](https://unsat.cs.washington.edu/papers/nelson-serval.pdf). 15 | 16 | - The [SOSP'19 tutorial materials](https://github.com/uw-unsat/serval-tutorial-sosp19) 17 | contains a version of Serval that is used to verify a toy system. This version 18 | is useful for learning, but we do not recommend using it to verify a real system. 19 | 20 | ## Installing 21 | 22 | To install serval, first install [Racket](https://racket-lang.org), then run 23 | 24 | ```sh 25 | raco pkg install 26 | ``` 27 | 28 | from the root directory of this repository. -------------------------------------------------------------------------------- /info.rkt: -------------------------------------------------------------------------------- 1 | #lang info 2 | 3 | (define collection 'multi) 4 | 5 | (define deps '("rosette" "base" "rackunit-lib" "scribble-lib" "racket-doc")) 6 | 7 | (define pkg-desc "Serval verification framework") 8 | (define version "0.0.1a") 9 | 10 | -------------------------------------------------------------------------------- /serval/arm32.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "arm32/base.rkt" 4 | "arm32/interp.rkt") 5 | 6 | (provide (all-from-out "arm32/base.rkt") 7 | (all-from-out "arm32/interp.rkt")) 8 | -------------------------------------------------------------------------------- /serval/arm32/interp.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "interp/branch-immediate.rkt" 5 | "interp/extend-and-add.rkt" 6 | "interp/integer-data-processing-immediate.rkt" 7 | "interp/integer-data-processing-register.rkt" 8 | "interp/integer-test-and-compare-immediate.rkt" 9 | "interp/integer-test-and-compare-register.rkt" 10 | "interp/load-store-dual-half-signed-byte-immediate.rkt" 11 | "interp/load-store-multiple.rkt" 12 | "interp/load-store-word-unsigned-byte-immediate.rkt" 13 | "interp/logical-arithmetic-immediate.rkt" 14 | "interp/logical-arithmetic-register.rkt" 15 | "interp/logical-arithmetic-register-shifted-register.rkt" 16 | "interp/miscellaneous.rkt" 17 | "interp/move-halfword-immediate.rkt" 18 | "interp/multiply-and-accumulate.rkt" 19 | "interp/reverse.rkt" 20 | "interp/signed-multiply-divide.rkt") 21 | 22 | (provide (all-from-out 23 | "interp/branch-immediate.rkt" 24 | "interp/extend-and-add.rkt" 25 | "interp/integer-data-processing-immediate.rkt" 26 | "interp/integer-data-processing-register.rkt" 27 | "interp/integer-test-and-compare-immediate.rkt" 28 | "interp/integer-test-and-compare-register.rkt" 29 | "interp/load-store-dual-half-signed-byte-immediate.rkt" 30 | "interp/load-store-multiple.rkt" 31 | "interp/load-store-word-unsigned-byte-immediate.rkt" 32 | "interp/logical-arithmetic-immediate.rkt" 33 | "interp/logical-arithmetic-register.rkt" 34 | "interp/logical-arithmetic-register-shifted-register.rkt" 35 | "interp/miscellaneous.rkt" 36 | "interp/move-halfword-immediate.rkt" 37 | "interp/multiply-and-accumulate.rkt" 38 | "interp/reverse.rkt" 39 | "interp/signed-multiply-divide.rkt")) 40 | -------------------------------------------------------------------------------- /serval/arm32/interp/branch-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | b) 8 | 9 | 10 | (define (decode imm24) 11 | (define imm32 (sign-extend (concat imm24 (bv #b00 2)) (bitvector 32))) 12 | (values imm32)) 13 | 14 | (define (interpret-b cpu imm24) 15 | (define-values (imm32) (decode imm24)) 16 | (branch-write-pc cpu (bvadd (cpu-gpr-ref cpu (integer->gpr 15)) imm32) 'DIR)) 17 | 18 | 19 | (define-insn (imm24) 20 | #:encode (lambda (H) (list (bv #b101 3) (bv H 1) imm24)) 21 | [(#b0) b interpret-b]) 22 | -------------------------------------------------------------------------------- /serval/arm32/interp/integer-test-and-compare-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | tst-immediate 8 | teq-immediate 9 | cmp-immediate 10 | cmn-immediate) 11 | 12 | 13 | (define (decode cpu Rn imm12) 14 | (define n Rn) 15 | (define-values (imm32 carry) (a32-expand-imm_c imm12 (cpu-pstate.c cpu))) 16 | (values n imm32 carry)) 17 | 18 | (define (interpret-t* proc cpu Rn imm12) 19 | (define-values (n imm32 carry) (decode cpu Rn imm12)) 20 | (define result (proc (cpu-gpr-ref cpu n) imm32)) 21 | (cpu-pstate.n-set! cpu (bit 31 result)) 22 | (cpu-pstate.z-set! cpu (is-zero-bit result)) 23 | (cpu-pstate.c-set! cpu carry) 24 | ; PSTATE.V unchanged 25 | ) 26 | 27 | (define interpret-tst 28 | (curry interpret-t* bvand)) 29 | 30 | (define interpret-teq 31 | (curry interpret-t* bvxor)) 32 | 33 | (define (interpret-c* proc cpu Rn imm12) 34 | (define-values (n imm32 _) (decode cpu Rn imm12)) 35 | (define-values (result nzcv) (add-with-carry (cpu-gpr-ref cpu n) (proc imm32) (proc (bv #b0 1)))) 36 | (cpu-pstate.nzcv-set! cpu nzcv)) 37 | 38 | (define interpret-cmp 39 | (curry interpret-c* bvnot)) 40 | 41 | (define interpret-cmn 42 | (curry interpret-c* identity)) 43 | 44 | 45 | (define-insn (Rn imm12) 46 | #:encode (lambda (opc) (list (bv #b00110 5) (bv opc 2) (bv #b1 1) Rn (bv #b0000 4) imm12)) 47 | [(#b00) tst-immediate interpret-tst] 48 | [(#b01) teq-immediate interpret-teq] 49 | [(#b10) cmp-immediate interpret-cmp] 50 | [(#b11) cmn-immediate interpret-cmn]) 51 | -------------------------------------------------------------------------------- /serval/arm32/interp/miscellaneous.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | blx-register) 8 | 9 | 10 | (define (interpret-blx-register cpu Rm) 11 | (define m Rm) 12 | (when (r15? m) 13 | (unpredictable)) 14 | 15 | (define target (cpu-gpr-ref cpu Rm)) 16 | 17 | (define next-instr-addr (bvsub (pc-store-value cpu) (bv 4 32))) 18 | (cpu-gpr-set! cpu (integer->gpr 14) next-instr-addr) 19 | (bx-write-pc cpu target 'INDCALL)) 20 | 21 | 22 | (define-insn (Rm) 23 | #:encode (lambda (op0 op1) (list (bv #b00010 5) (bv op0 2) (bv 0 1) (bv -1 12) (bv 0 1) (bv op1 3) Rm)) 24 | [(#b01 #b011) blx-register interpret-blx-register]) 25 | -------------------------------------------------------------------------------- /serval/arm32/interp/move-halfword-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | movw movt) 8 | 9 | 10 | (define (decode imm4 Rd imm12) 11 | (define d Rd) 12 | (define imm16 (concat imm4 imm12)) 13 | (when (r15? d) 14 | (unpredictable)) 15 | (values d imm16)) 16 | 17 | (define (interpret-movw cpu imm4 Rd imm12) 18 | (define-values (d imm16) (decode imm4 Rd imm12)) 19 | (cpu-gpr-set! cpu d (zero-extend imm16 (bitvector 32)))) 20 | 21 | (define (interpret-movt cpu imm4 Rd imm12) 22 | (define-values (d imm16) (decode imm4 Rd imm12)) 23 | ; R[d]<15:0> unchanged 24 | (define lower (extract 15 0 (cpu-gpr-ref cpu d))) 25 | (cpu-gpr-set! cpu d (concat imm16 lower))) 26 | 27 | 28 | (define-insn (imm4 Rd imm12) 29 | #:encode (lambda (H) (list (bv #b00110 5) (bv H 1) (bv #b00 2) imm4 Rd imm12)) 30 | [(#b0) movw interpret-movw] 31 | [(#b1) movt interpret-movt]) 32 | -------------------------------------------------------------------------------- /serval/arm32/interp/reverse.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | rev 8 | rev16) 9 | 10 | 11 | (define (decode Rd Rm) 12 | (define d Rd) 13 | (define m Rm) 14 | (when (|| (r15? d) (r15? m)) 15 | (unpredictable)) 16 | (values d m)) 17 | 18 | (define (interpret-rev cpu Rd Rm) 19 | (define-values (d m) (decode Rd Rm)) 20 | (define x (cpu-gpr-ref cpu m)) 21 | (define result (concat (extract 7 0 x) (extract 15 8 x) (extract 23 16 x) (extract 31 24 x))) 22 | (cpu-gpr-set! cpu d result)) 23 | 24 | (define (interpret-rev16 cpu Rd Rm) 25 | (define-values (d m) (decode Rd Rm)) 26 | (define x (cpu-gpr-ref cpu m)) 27 | (define result (concat (extract 23 16 x) (extract 31 24 x) (extract 7 0 x) (extract 15 8 x))) 28 | (cpu-gpr-set! cpu d result)) 29 | 30 | 31 | (define-insn (Rd Rm) 32 | #:encode (lambda (o1 o2) (list (bv #b01101 5) (bv o1 1) (bv #b11 2) (bv #b1111 4) Rd (bv #b1111 4) (bv o2 1) (bv #b011 3) Rm)) 33 | [(#b0 #b0) rev interpret-rev] 34 | [(#b0 #b1) rev16 interpret-rev16]) 35 | -------------------------------------------------------------------------------- /serval/arm32/interp/signed-multiply-divide.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | sdiv 8 | udiv) 9 | 10 | 11 | (define (decode Rd Rm Rn) 12 | (define d Rd) 13 | (define n Rn) 14 | (define m Rm) 15 | (when (|| (r15? d) (r15? n) (r15? m)) 16 | (unpredictable)) 17 | (values d n m)) 18 | 19 | (define (interpret-sdiv/udiv proc cpu Rd Rm Rn) 20 | (define-values (d n m) (decode Rd Rm Rn)) 21 | (define operand1 (cpu-gpr-ref cpu n)) 22 | (define operand2 (cpu-gpr-ref cpu m)) 23 | (define result (if (bvzero? operand2) (bv 0 32) ((proc) operand1 operand2))) 24 | (cpu-gpr-set! cpu d result)) 25 | 26 | (define interpret-sdiv 27 | (curry interpret-sdiv/udiv core:bvsdiv-proc)) 28 | 29 | (define interpret-udiv 30 | (curry interpret-sdiv/udiv core:bvudiv-proc)) 31 | 32 | 33 | (define-insn (Rd Rm Rn) 34 | #:encode (lambda (op1 Ra op2) (list (bv #b01110 5) (bv op1 3) Rd (bv Ra 4) Rm (bv op2 3) (bv #b1 1) Rn)) 35 | [(#b001 #b1111 #b000) sdiv interpret-sdiv] 36 | [(#b011 #b1111 #b000) udiv interpret-udiv]) 37 | -------------------------------------------------------------------------------- /serval/arm64.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "arm64/base.rkt" 5 | "arm64/decode.rkt" 6 | "arm64/interp.rkt") 7 | 8 | (provide (all-from-out 9 | "arm64/base.rkt" 10 | "arm64/decode.rkt" 11 | "arm64/interp.rkt")) 12 | -------------------------------------------------------------------------------- /serval/arm64/interp.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | ; The encodings and semantics are organized following the ARM manual. 4 | ; 5 | ; The semantics closely follows the pseudocode in the manual, but carefully 6 | ; avoids the use of integers in order to avoid integers in SMT constraints. 7 | ; The only exception is for instruction fields that will be concrete upon use, 8 | ; such as datasize (sf for 32/64-bit instructions). 9 | 10 | (require 11 | "interp/arithmetic-immediate.rkt" 12 | "interp/arithmetic-shifted-register.rkt" 13 | "interp/atomic.rkt" 14 | "interp/bit-operation.rkt" 15 | "interp/bitfield-move.rkt" 16 | "interp/conditional-branch.rkt" 17 | "interp/divide.rkt" 18 | "interp/load-store-register.rkt" 19 | "interp/load-store-register-pair.rkt" 20 | "interp/logical-immediate.rkt" 21 | "interp/logical-shifted-register.rkt" 22 | "interp/move-wide-immediate.rkt" 23 | "interp/multiply.rkt" 24 | "interp/shift-register.rkt" 25 | "interp/unconditional-branch-immediate.rkt" 26 | "interp/unconditional-branch-register.rkt") 27 | 28 | (provide (all-from-out 29 | "interp/arithmetic-immediate.rkt" 30 | "interp/arithmetic-shifted-register.rkt" 31 | "interp/atomic.rkt" 32 | "interp/bit-operation.rkt" 33 | "interp/bitfield-move.rkt" 34 | "interp/conditional-branch.rkt" 35 | "interp/divide.rkt" 36 | "interp/load-store-register.rkt" 37 | "interp/load-store-register-pair.rkt" 38 | "interp/logical-immediate.rkt" 39 | "interp/logical-shifted-register.rkt" 40 | "interp/move-wide-immediate.rkt" 41 | "interp/multiply.rkt" 42 | "interp/shift-register.rkt" 43 | "interp/unconditional-branch-immediate.rkt" 44 | "interp/unconditional-branch-register.rkt")) 45 | -------------------------------------------------------------------------------- /serval/arm64/interp/conditional-branch.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | b.cond) 8 | 9 | 10 | (define (decode imm19) 11 | (sign-extend (concat imm19 (bv #b00 2)) (bitvector 64))) 12 | 13 | (define (interpret-b.cond cpu imm19 cond) 14 | (define offset (decode imm19)) 15 | (when (condition-holds cpu cond) 16 | (branch-to cpu (bvadd (cpu-pc-ref cpu) offset)))) 17 | 18 | 19 | (define-insn (imm19 cond) 20 | #:encode (lambda (o1 o0) (list (bv #b0101010 7) (bv o1 1) imm19 (bv o0 1) cond)) 21 | [(#b0 #b0) b.cond interpret-b.cond]) 22 | -------------------------------------------------------------------------------- /serval/arm64/interp/divide.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | udiv sdiv) 8 | 9 | 10 | (define (interpret-udiv/sdiv cpu sf Rm Rn Rd proc) 11 | (define d Rd) 12 | (define n Rn) 13 | (define m Rm) 14 | (define datasize (if (bveq sf (bv #b1 1)) 64 32)) 15 | 16 | (define operand1 (trunc datasize (cpu-gpr-ref cpu n))) 17 | (define operand2 (trunc datasize (cpu-gpr-ref cpu m))) 18 | 19 | (define result 20 | (if (is-zero operand2) 21 | (zeros datasize) 22 | (proc operand1 operand2))) 23 | 24 | (cpu-gpr-set! cpu d result)) 25 | 26 | (define (interpret-udiv cpu sf Rm Rn Rd) 27 | (interpret-udiv/sdiv cpu sf Rm Rn Rd (core:bvudiv-proc))) 28 | 29 | (define (interpret-sdiv cpu sf Rm Rn Rd) 30 | (interpret-udiv/sdiv cpu sf Rm Rn Rd (core:bvsdiv-proc))) 31 | 32 | 33 | (define-insn (sf Rm Rn Rd) 34 | #:encode (lambda (o1) (list sf (bv #b0 1) (bv #b0 1) (bv #b11010110 8) Rm (bv #b00001 5) (bv o1 1) Rn Rd)) 35 | [(#b0) udiv interpret-udiv] 36 | [(#b1) sdiv interpret-sdiv]) 37 | -------------------------------------------------------------------------------- /serval/arm64/interp/multiply.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | madd msub) 8 | 9 | 10 | (define (interpret-madd/msub cpu sf Rm Ra Rn Rd sub_op) 11 | (define d Rd) 12 | (define n Rn) 13 | (define m Rm) 14 | (define a Ra) 15 | (define destsize (if (bveq sf (bv #b1 1)) 64 32)) 16 | 17 | (define operand1 (trunc destsize (cpu-gpr-ref cpu n))) 18 | (define operand2 (trunc destsize (cpu-gpr-ref cpu m))) 19 | (define operand3 (trunc destsize (cpu-gpr-ref cpu a))) 20 | 21 | (define result (sub_op operand3 ((core:bvmul-proc) operand1 operand2))) 22 | (cpu-gpr-set! cpu d result)) 23 | 24 | (define (interpret-madd cpu sf Rm Ra Rn Rd) 25 | (interpret-madd/msub cpu sf Rm Ra Rn Rd bvadd)) 26 | 27 | (define (interpret-msub cpu sf Rm Ra Rn Rd) 28 | (interpret-madd/msub cpu sf Rm Ra Rn Rd bvsub)) 29 | 30 | 31 | (define-insn (sf Rm Ra Rn Rd) 32 | #:encode (lambda (o0) (list sf (bv #b00 2) (bv #b11011 5) (bv #b00 3) Rm (bv o0 1) Ra Rn Rd)) 33 | [(#b0) madd interpret-madd] 34 | [(#b1) msub interpret-msub]) 35 | -------------------------------------------------------------------------------- /serval/arm64/interp/shift-register.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | lslv lsrv asrv rorv) 8 | 9 | 10 | (define (interpret-shift-variable cpu sf Rm op2 Rn Rd) 11 | (define d Rd) 12 | (define n Rn) 13 | (define m Rm) 14 | (define datasize (if (bveq sf (bv #b1 1)) 64 32)) 15 | (define shift_type (decode-shift op2)) 16 | 17 | (define operand1 (trunc datasize (cpu-gpr-ref cpu n))) 18 | (define operand2 (trunc datasize (cpu-gpr-ref cpu m))) 19 | 20 | ; The ARM manual uses (operand2 MOD datasize); use bit masking instead. 21 | (define mask (bv (sub1 datasize) datasize)) 22 | (define result (shift-reg cpu n shift_type (bvand operand2 mask))) 23 | (cpu-gpr-set! cpu d result)) 24 | 25 | 26 | (define-insn (sf Rm op2 Rn Rd) 27 | #:encode (lambda () (list sf (bv #b0 1) (bv #b0 1) (bv #b11010110 8) Rm (bv #b0010 4) op2 Rn Rd)) 28 | [() shift-variable interpret-shift-variable]) 29 | 30 | (define (lslv sf Rm Rn Rd) 31 | (shift-variable sf Rm (bv #b00 2) Rn Rd)) 32 | 33 | (define (lsrv sf Rm Rn Rd) 34 | (shift-variable sf Rm (bv #b01 2) Rn Rd)) 35 | 36 | (define (asrv sf Rm Rn Rd) 37 | (shift-variable sf Rm (bv #b10 2) Rn Rd)) 38 | 39 | (define (rorv sf Rm Rn Rd) 40 | (shift-variable sf Rm (bv #b11 2) Rn Rd)) 41 | -------------------------------------------------------------------------------- /serval/arm64/interp/unconditional-branch-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | b bl) 8 | 9 | 10 | (define (decode imm26) 11 | (sign-extend (concat imm26 (bv #b00 2)) (bitvector 64))) 12 | 13 | (define (interpret-b cpu imm26) 14 | (define offset (decode imm26)) 15 | (branch-to cpu (bvadd (cpu-pc-ref cpu) offset))) 16 | 17 | (define (interpret-bl cpu imm26) 18 | (define offset (decode imm26)) 19 | (cpu-gpr-set! cpu (integer->gpr 30) (bvadd (cpu-pc-ref cpu) (bv 4 64))) 20 | (branch-to cpu (bvadd (cpu-pc-ref cpu) offset))) 21 | 22 | 23 | (define-insn (imm26) 24 | #:encode (lambda (op) (list (bv op 1) (bv #b00101 5) imm26)) 25 | [(#b0) b interpret-b] 26 | [(#b1) bl interpret-bl]) 27 | -------------------------------------------------------------------------------- /serval/arm64/interp/unconditional-branch-register.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | ret br blr) 8 | 9 | 10 | (define (interpret-br cpu Rn) 11 | (define target (cpu-gpr-ref cpu Rn)) 12 | (branch-to cpu target)) 13 | 14 | (define (interpret-blr cpu Rn) 15 | (define target (cpu-gpr-ref cpu Rn)) 16 | (define pc (cpu-pc-ref cpu)) 17 | (cpu-gpr-set! cpu (integer->gpr 30) (bvadd pc (bv 4 (type-of pc)))) 18 | (branch-to cpu target)) 19 | 20 | 21 | (define-insn (Rn) 22 | #:encode (lambda (opc op2 op3 op4) (list (bv #b1101011 7) (bv opc 4) (bv op2 5) (bv op3 6) Rn (bv op4 5))) 23 | [(#b0010 #b11111 #b000000 #b00000) ret interpret-br] 24 | [(#b0000 #b11111 #b000000 #b00000) br interpret-br] 25 | [(#b0001 #b11111 #b000000 #b00000) blr interpret-blr]) 26 | -------------------------------------------------------------------------------- /serval/bin/serval-llvm.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require racket/port 4 | racket/file 5 | racket/cmdline 6 | serval/llvm/parse 7 | serval/llvm/print) 8 | 9 | (define extra-requires (make-parameter null)) 10 | 11 | (define filename 12 | (command-line #:program "serval-llvm" 13 | #:multi [("-R" "--extra-require") 14 | path 15 | "Add additional requires to add to Racket file" 16 | (extra-requires (cons path (extra-requires)))] 17 | #:args ([input "-"]) 18 | input)) 19 | 20 | (define input-bytes (if (equal? filename "-") (port->bytes) (file->bytes filename #:mode 'binary))) 21 | 22 | (define m (bytes->module input-bytes)) 23 | (print-module m #:extra-requires (extra-requires)) 24 | -------------------------------------------------------------------------------- /serval/guide/scribble/refs.scrbl: -------------------------------------------------------------------------------- 1 | #lang scribble/manual 2 | 3 | @(require scriblib/autobib) 4 | @(provide (all-defined-out)) 5 | 6 | @(define-cite ~cite citet generate-bibliography #:style number-style) 7 | 8 | @(abbreviate-given-names #t) 9 | 10 | @(define nelson:hyperkernel 11 | (make-bib 12 | #:title @hyperlink["https://unsat.cs.washington.edu/papers/nelson-hyperkernel.pdf"]{Hyperkernel: Push-Button Verification of an OS Kernel} 13 | #:author (authors "Luke Nelson" "Helgi Sigurbjarnarson" "Kaiyuan Zhang" "Dylan Johnson" "James Bornholt" "Emina Torlak" "Xi Wang") 14 | #:date 2017 15 | #:location (proceedings-location "SOSP"))) 16 | 17 | @(define nelson:serval 18 | (make-bib 19 | #:title @hyperlink["https://unsat.cs.washington.edu/papers/nelson-serval.pdf"]{Scaling symbolic evaluation for automated verification of systems code with Serval} 20 | #:author (authors "Luke Nelson" "James Bornholt" "Ronghui Gu" "Andrew Baumann" "Emina Torlak" "Xi Wang") 21 | #:date 2019 22 | #:location (proceedings-location "SOSP"))) 23 | 24 | @(define sigurbjarnarson:nickel 25 | (make-bib 26 | #:title @hyperlink["https://unsat.cs.washington.edu/papers/sigurbjarnarson-nickel.pdf"]{Nickel: A Framework for Design and Verification of Information Flow Control Systems} 27 | #:author (authors "Helgi Sigurbjarnarson" "Luke Nelson" "Bruno Castro-Karney" "James Bornholt" "Emina Torlak" "Xi Wang") 28 | #:date 2018 29 | #:location (proceedings-location "OSDI"))) 30 | -------------------------------------------------------------------------------- /serval/info.rkt: -------------------------------------------------------------------------------- 1 | #lang info 2 | 3 | (define collection 'use-pkg-name) 4 | 5 | (define scribblings '(("guide/scribble/serval.scrbl" (multi-page) (experimental)))) 6 | 7 | (define raco-commands 8 | '(("serval-llvm" serval/bin/serval-llvm "Convert LLVM .ll file to .rkt using Serval" #f))) 9 | -------------------------------------------------------------------------------- /serval/lang/nm.rkt: -------------------------------------------------------------------------------- 1 | #lang racket 2 | 3 | (require 4 | racket/list 5 | racket/match 6 | racket/port 7 | racket/string 8 | syntax/strip-context) 9 | 10 | (provide (rename-out [literal-read read] 11 | [literal-read-syntax read-syntax])) 12 | 13 | (define (literal-read in) 14 | (syntax->datum 15 | (literal-read-syntax #f in))) 16 | 17 | (define (read-syms in) 18 | (datum->syntax #f 19 | (filter (compose not false?) 20 | (for/list ([l (filter non-empty-string? (port->lines in))]) 21 | (match l 22 | ; Two addrs 23 | [(pregexp #px"^([0-9a-f]+) ([0-9a-f]+) (\\S) (\\S+)$" (list _ begin size type name)) 24 | (with-syntax ([begin (string->number begin 16)] 25 | [end (+ (string->number begin 16) 26 | (string->number size 16))] 27 | [type (string->symbol type)] 28 | [name (string->symbol name)]) 29 | #'(begin end type name))] 30 | 31 | ; No size 32 | [(pregexp #px"^([0-9a-f]+) (\\S) (\\S+)$" (list _ begin type name)) 33 | (with-syntax ([begin (string->number begin 16)] 34 | [type (string->symbol type)] 35 | [name (string->symbol name)]) 36 | #'(begin begin type name))] 37 | [_ #f]))))) 38 | 39 | 40 | (define (literal-read-syntax src in) 41 | (strip-context 42 | #`(module anything racket/base 43 | (provide symbols) 44 | (define symbols '#,(read-syms in))))) 45 | -------------------------------------------------------------------------------- /serval/lib/core.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "bvarith.rkt" 5 | "cpu.rkt" 6 | "debug.rkt" 7 | "memmgr.rkt" 8 | "memory/mblock.rkt" 9 | "memory/mregion.rkt" 10 | "solver.rkt" 11 | "symopt.rkt" 12 | "uf.rkt" 13 | "unittest.rkt" 14 | (only-in rosette [list var])) 15 | 16 | (provide 17 | (all-defined-out) 18 | (all-from-out "bvarith.rkt") 19 | (all-from-out "cpu.rkt") 20 | (all-from-out "debug.rkt") 21 | (all-from-out "memmgr.rkt") 22 | (all-from-out "memory/mblock.rkt") 23 | (all-from-out "memory/mregion.rkt") 24 | (all-from-out "solver.rkt") 25 | (all-from-out "symopt.rkt") 26 | (all-from-out "uf.rkt") 27 | (all-from-out "unittest.rkt") 28 | var) 29 | -------------------------------------------------------------------------------- /serval/lib/cpu.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "memmgr.rkt") 4 | 5 | (provide (except-out (all-defined-out) __gen-cpu-memmgr)) 6 | 7 | (define (__gen-cpu-memmgr gen-cpu) 8 | (gen-cpu-memmgr gen-cpu)) 9 | 10 | (define-generics gen-cpu 11 | (gen-cpu-memmgr gen-cpu) 12 | (gen-cpu-bitwidth gen-cpu) 13 | (gen-cpu-pc gen-cpu) 14 | #:fallbacks [ 15 | ; By default, get bitwidth from underlying memmgr 16 | (define (gen-cpu-bitwidth gen-cpu) 17 | (memmgr-bitwidth (__gen-cpu-memmgr gen-cpu))) 18 | ]) -------------------------------------------------------------------------------- /serval/lib/memmgr.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "memory/manager.rkt" "memory/typed-bv.rkt" "memory/flat.rkt") 4 | 5 | (provide 6 | (all-from-out "memory/manager.rkt") 7 | (all-from-out "memory/typed-bv.rkt") 8 | (all-from-out "memory/flat.rkt")) 9 | -------------------------------------------------------------------------------- /serval/lib/memory/manager.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../debug.rkt") 4 | 5 | (provide (all-defined-out)) 6 | 7 | (define target-pointer-bitwidth (make-parameter 64)) 8 | 9 | (define-generics memmgr 10 | (memmgr-alloc! memmgr size alignment proc) 11 | (memmgr-load memmgr addr off size) 12 | (memmgr-store! memmgr addr off data size) 13 | (memmgr-memset! memmgr addr value len) 14 | (memmgr-bitwidth memmgr) 15 | (memmgr-invariants memmgr) 16 | (memmgr-atomic-begin memmgr) 17 | (memmgr-atomic-end memmgr) 18 | #:fallbacks [ 19 | (define (memmgr-alloc! memmgr size alignment proc) 20 | (bug #:msg (format "memmgr: ~v does not provide an allocator" memmgr))) 21 | (define (memmgr-memset! memmgr addr value len) 22 | (bug #:msg (format "memmgr: ~v does not implement memset" memmgr))) 23 | (define (memmgr-atomic-begin memmgr) (void)) 24 | (define (memmgr-atomic-end memmgr) (void)) 25 | (define (memmgr-invariants memmgr) #t) 26 | ]) 27 | -------------------------------------------------------------------------------- /serval/lib/symopt.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "debug.rkt" "unittest.rkt") 4 | 5 | (provide (all-defined-out)) 6 | 7 | ; Generic symbolic optimizations for users of Serval library. 8 | 9 | (define (split-cases value cases func) 10 | (define newvalue 11 | (foldr (lambda (a result) (if (equal? a value) a result)) value cases)) 12 | (for/all ([v newvalue #:exhaustive]) (begin 13 | (check-unsat? (verify (assert (equal? v value)))) 14 | (func v)))) 15 | 16 | (define-syntax (split-pc stx) 17 | (define (build-name id . parts) 18 | (datum->syntax id 19 | (string->symbol 20 | (apply string-append 21 | (map (lambda (p) 22 | (if (syntax? p) 23 | (symbol->string (syntax-e p)) 24 | p)) 25 | parts))) 26 | id)) 27 | (syntax-case stx () 28 | [(_ (struct-name field) obj body ...) 29 | (with-syntax ([getter (build-name #'obj #'struct-name "-" #'field)] 30 | [setter! (build-name #'obj "set-" #'struct-name "-" #'field "!")]) 31 | (syntax/loc stx 32 | (for/all ([pc (getter obj) #:exhaustive]) 33 | (begin 34 | (setter! obj pc) 35 | body ...))))])) 36 | -------------------------------------------------------------------------------- /serval/lib/uf.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | ; Helper procedures for dealing with uninterpreted functions. 4 | 5 | (provide (all-defined-out)) 6 | 7 | ; update a function map with a path, which can be 8 | ; an index, a predicate, or a list of indices/predicates. 9 | (define (update func path value) 10 | (define (normalize-path e) 11 | (if (procedure? e) e (lambda (x) (equal? x e)))) 12 | (define pred (map normalize-path (if (list? path) path (list path)))) 13 | (lambda args (if (apply && (map (lambda (f x) (f x)) pred args)) value (apply func args)))) 14 | 15 | (define (update-fn func indices newfn) 16 | (define (index-yes? args indices) 17 | (apply && (for/list ([x args] [y indices]) (equal? x y)))) 18 | (define proc (if (list? indices) (lambda args (index-yes? args indices)) indices)) 19 | (lambda args (if (apply proc args) (apply newfn args) (apply func args)))) 20 | -------------------------------------------------------------------------------- /serval/llvm/base.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (provide (all-defined-out)) 4 | 5 | (struct module (globals functions) #:transparent) 6 | 7 | (struct value (name type) #:transparent) 8 | 9 | (struct function value (arguments blocks) #:transparent) 10 | 11 | (struct argument value () #:transparent) 12 | 13 | (struct basic-block value (instructions) #:transparent) 14 | 15 | (struct instruction value (opcode operands attributes) #:transparent) 16 | 17 | (struct array-offset (index size) #:transparent) 18 | (struct struct-offset (value) #:transparent) 19 | 20 | (struct asm (template constraint) #:transparent) 21 | 22 | (struct nullptr () #:transparent) 23 | 24 | (struct undef (type) #:transparent) 25 | -------------------------------------------------------------------------------- /serval/llvm/capi/irreader.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require ffi/unsafe 4 | ffi/unsafe/alloc 5 | "core.rkt") 6 | 7 | (provide LLVMParseIRInContext) 8 | 9 | ; allocate a new _LLVMMemoryBufferRef, which is consumed by this function 10 | (define-llvm LLVMParseIRInContext 11 | (_fun [_LLVMContextRef = (LLVMGetGlobalContext)] 12 | [data : _?] 13 | [_LLVMMemoryBufferRef = (LLVMCreateMemoryBufferWithMemoryRangeCopy data "" 0)] 14 | [m : (_ptr o (_or-null _LLVMModuleRef))] 15 | [msg : (_ptr o _pointer)] 16 | -> [r : _LLVMBool] 17 | -> (begin (check r msg) m)) 18 | #:wrap (allocator LLVMDisposeModule)) 19 | 20 | ; no allocator here 21 | (define-llvm LLVMCreateMemoryBufferWithMemoryRangeCopy 22 | (_fun [data : _bytes] 23 | [length : _size = (bytes-length data)] 24 | [buffer-name : _string] 25 | [requires-null-terminator? : _LLVMBool] 26 | -> _LLVMMemoryBufferRef)) 27 | -------------------------------------------------------------------------------- /serval/llvm/capi/target.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require ffi/unsafe 4 | ffi/unsafe/alloc 5 | "core.rkt") 6 | 7 | (provide (all-defined-out)) 8 | 9 | (define _LLVMByteOrdering 10 | (_enum 11 | '(big = 0 12 | little))) 13 | 14 | (struct _data-layout (pointer module) #:transparent) 15 | 16 | (define _LLVMTargetDataRef 17 | (make-ctype _pointer 18 | _data-layout-pointer 19 | #f)) 20 | 21 | (define-llvm LLVMGetModuleDataLayout 22 | (_fun (m : _LLVMModuleRef) 23 | -> (cptr : _pointer) 24 | -> (_data-layout cptr m))) 25 | 26 | (define-llvm LLVMCopyStringRepOfTargetData 27 | (_fun _LLVMTargetDataRef 28 | -> _LLVMMessageRef)) 29 | 30 | (define-llvm LLVMByteOrder 31 | (_fun _LLVMTargetDataRef 32 | -> _LLVMByteOrdering)) 33 | 34 | (define-llvm LLVMPointerSize 35 | (_fun _LLVMTargetDataRef 36 | -> _uint)) 37 | 38 | (define-llvm LLVMABISizeOfType 39 | (_fun _LLVMTargetDataRef 40 | _LLVMTypeRef 41 | -> _ullong)) 42 | 43 | (define-llvm LLVMOffsetOfElement 44 | (_fun _LLVMTargetDataRef 45 | _LLVMTypeRef 46 | _uint 47 | -> _ullong)) 48 | -------------------------------------------------------------------------------- /serval/llvm/lang.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | ;(require ffi/unsafe 4 | ; ffi/unsafe/alloc 5 | ; racket/port 6 | ; racket/sequence 7 | ; syntax/strip-context 8 | ; "capi/core.rkt" 9 | ; "util.rkt") 10 | 11 | ; (provide #%module-begin #%datum #%top-interaction #%app define quote) 12 | 13 | ; (define (llvm-read-syntax path port) 14 | ; (define m (bytes->module (context) (port->bytes port))) 15 | 16 | ; (define fns (for/list ([f (in-functions m)]) (read-function f))) 17 | 18 | ; (strip-context 19 | ; (quasisyntax 20 | ; (module anything serval/llvm/lang 21 | ; #,@fns 22 | ; )))) 23 | 24 | ; (provide (rename-out [llvm-read-syntax read-syntax])) 25 | 26 | ; (define (read-function f) 27 | ; (define bbs (for/list ([bb (in-basic-blocks f)]) (read-basic-block bb))) 28 | ; (with-syntax ([fnname (string->symbol (value-name f))]) 29 | ; (quasisyntax 30 | ; (define (fnname) '#,@bbs)))) 31 | 32 | ; (define (read-basic-block bb) 33 | ; (define insns (for/list ([insn (in-instructions bb)]) (read-instruction insn))) 34 | 35 | ; (with-syntax ([name (string->symbol (value->string bb))]) 36 | ; (quasisyntax 37 | ; (name #,@insns)))) 38 | 39 | ; (define (read-instruction insn) 40 | ; (with-syntax ([s (value->string insn)]) 41 | ; (quasisyntax 42 | ; s))) 43 | -------------------------------------------------------------------------------- /serval/riscv/interp/b-type.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "common.rkt") 4 | 5 | (provide (all-defined-out)) 6 | 7 | (define ((interpret-b-type op) cpu insn imm12&10:5 rs2 rs1 imm4:1&11) 8 | (define xlen (cpu-xlen cpu)) 9 | (define off 10 | (concat (extract 6 6 imm12&10:5) 11 | (extract 0 0 imm4:1&11) 12 | (extract 5 0 imm12&10:5) 13 | (extract 4 1 imm4:1&11) 14 | (bv 0 1))) 15 | 16 | (define a (gpr-ref cpu (decode-gpr rs1))) 17 | (define b (gpr-ref cpu (decode-gpr rs2))) 18 | 19 | (define branch (op a b)) 20 | 21 | (if branch 22 | (set-cpu-pc! cpu (bvadd (cpu-pc cpu) (sign-extend off (bitvector xlen)))) 23 | (cpu-next! cpu insn))) 24 | 25 | (define-insn (imm12&10:5 rs2 rs1 imm4:1&11) 26 | #:encode (lambda (funct3 opcode) 27 | (list imm12&10:5 rs2 rs1 (bv funct3 3) imm4:1&11 (bv opcode 7))) 28 | [(#b000 #b1100011) beq (interpret-b-type bveq)] 29 | [(#b001 #b1100011) bne (interpret-b-type (lambda (a b) (! (bveq a b))))] 30 | [(#b100 #b1100011) blt (interpret-b-type bvslt)] 31 | [(#b101 #b1100011) bge (interpret-b-type bvsge)] 32 | [(#b110 #b1100011) bltu (interpret-b-type bvult)] 33 | [(#b111 #b1100011) bgeu (interpret-b-type bvuge)]) 34 | -------------------------------------------------------------------------------- /serval/riscv/interp/j-type.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "common.rkt") 4 | 5 | (provide (all-defined-out)) 6 | 7 | (define (interpret-jal cpu insn imm20&10:1&11&19:12 rd) 8 | (define off 9 | (concat (extract 19 19 imm20&10:1&11&19:12) 10 | (extract 7 0 imm20&10:1&11&19:12) 11 | (extract 8 8 imm20&10:1&11&19:12) 12 | (extract 18 9 imm20&10:1&11&19:12) 13 | (bv 0 1))) 14 | 15 | (define next (bvadd (cpu-pc cpu) (bv 4 (cpu-xlen cpu)))) 16 | (gpr-set! cpu (decode-gpr rd) next) 17 | 18 | (set-cpu-pc! cpu (bvadd (cpu-pc cpu) (sign-extend off (bitvector (cpu-xlen cpu)))))) 19 | 20 | (define-insn (imm20&10:1&11&19:12 rd) 21 | #:encode (lambda (opcode) 22 | (list imm20&10:1&11&19:12 rd (bv opcode 7))) 23 | [(#b1101111) jal interpret-jal]) -------------------------------------------------------------------------------- /serval/riscv/interp/s-type.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "common.rkt") 4 | 5 | (provide (all-defined-out)) 6 | 7 | (define ((interpret-store-insn size) cpu insn imm11:5 rs2 rs1 imm4:0) 8 | (define mm (cpu-memmgr cpu)) 9 | (define xlen (cpu-xlen cpu)) 10 | 11 | (define addr (bvadd (gpr-ref cpu (decode-gpr rs1)) 12 | (sign-extend (concat imm11:5 imm4:0) (bitvector xlen)))) 13 | (define value (trunc (* 8 size) (gpr-ref cpu (decode-gpr rs2)))) 14 | 15 | (core:memmgr-store! mm addr (bv 0 xlen) value (bv size xlen)) 16 | (cpu-next! cpu insn)) 17 | 18 | (define-insn (imm11:5 rs2 rs1 imm4:0) 19 | #:encode (lambda (funct3 opcode) 20 | (list imm11:5 rs2 rs1 (bv funct3 3) imm4:0 (bv opcode 7))) 21 | 22 | [(#b000 #b0100011) sb (interpret-store-insn 1)] 23 | [(#b001 #b0100011) sh (interpret-store-insn 2)] 24 | [(#b010 #b0100011) sw (interpret-store-insn 4)] 25 | [(#b011 #b0100011) sd (interpret-store-insn 8)]) 26 | -------------------------------------------------------------------------------- /serval/riscv/interp/u-type.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "common.rkt") 4 | 5 | (provide (all-defined-out)) 6 | 7 | (define (interpret-lui cpu insn imm31:12 rd) 8 | (gpr-set! cpu (decode-gpr rd) 9 | (sign-extend (concat imm31:12 (bv 0 12)) 10 | (bitvector (cpu-xlen cpu)))) 11 | (cpu-next! cpu insn)) 12 | 13 | (define (interpret-auipc cpu insn imm31:12 rd) 14 | (gpr-set! cpu (decode-gpr rd) 15 | (bvadd 16 | (sign-extend (concat imm31:12 (bv 0 12)) (bitvector (cpu-xlen cpu))) 17 | (cpu-pc cpu))) 18 | (cpu-next! cpu insn)) 19 | 20 | (define-insn (imm31:12 rd) 21 | #:encode (lambda (opcode) 22 | (list imm31:12 rd (bv opcode 7))) 23 | [(#b0110111) lui interpret-lui] 24 | [(#b0010111) auipc interpret-auipc] 25 | ) -------------------------------------------------------------------------------- /serval/riscv/shims.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "base.rkt" 4 | "../lib/memmgr.rkt" 5 | (prefix-in core: "../lib/core.rkt")) 6 | 7 | (provide (all-defined-out)) 8 | 9 | ; void *memset(void *p, int c, size_t len) 10 | (define (memset-shim cpu) 11 | (define ptr (gpr-ref cpu 'a0)) 12 | (define c (extract 7 0 (gpr-ref cpu 'a1))) 13 | (define len (gpr-ref cpu 'a2)) 14 | 15 | ; Use memmgr to implement memset. 16 | (define memmgr (cpu-memmgr cpu)) 17 | (memmgr-memset! memmgr ptr c len) 18 | 19 | ; Fake a 'ret' instruction to return control to calling function. 20 | (set-cpu-pc! cpu (gpr-ref cpu 'x1)) 21 | (havoc-caller-saved! cpu) 22 | (gpr-set! cpu 'a0 ptr)) 23 | -------------------------------------------------------------------------------- /serval/riscv/symopt.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "base.rkt" 4 | (prefix-in core: "../lib/core.rkt")) 5 | 6 | (provide (all-defined-out)) 7 | 8 | ; Jalr masks out the lowest bit of the PC. 9 | ; This symbolic optimizations kills the mask and emits an assertion that 10 | ; the rewrite is sound; to be used in situations where the target is known 11 | ; to be aligned and the resulting PC must be as concrete as possible. 12 | (define (kill-jalr-mask cpu) 13 | (define mask (bvnot (bv 1 (cpu-xlen cpu)))) 14 | (define newpc 15 | (match (cpu-pc cpu) 16 | [(expression (== bvand) x y) #:when (and (! (term? x)) (equal? x mask)) y] 17 | [pc pc])) 18 | (core:bug-on (! (equal? newpc (cpu-pc cpu))) 19 | #:msg "kill-jalr-mask: symbolic optimization must be sound") 20 | (set-cpu-pc! cpu newpc)) 21 | -------------------------------------------------------------------------------- /serval/spec/refinement.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette/safe 2 | 3 | (require 4 | "../lib/core.rkt" 5 | "../lib/unittest.rkt" 6 | ) 7 | 8 | (provide (all-defined-out)) 9 | 10 | (define 11 | (verify-refinement 12 | #:implstate impl-state 13 | #:impl impl-func 14 | #:specstate spec-state 15 | #:spec spec-func 16 | #:abs abs-function 17 | #:ri rep-invariant 18 | [args null] 19 | [ce-handler (lambda (sol) (void))]) 20 | 21 | (define ri0 (rep-invariant impl-state)) 22 | 23 | (define pre (check-vc (equal? spec-state (abs-function impl-state)))) 24 | 25 | (assume ri0) 26 | (assume pre) 27 | 28 | ; spec state transition 29 | (apply spec-func spec-state args) 30 | 31 | ; impl state transition 32 | (apply impl-func impl-state args) 33 | 34 | (define ri1 (rep-invariant impl-state)) 35 | (assert ri1) 36 | 37 | (define post (equal? spec-state (abs-function impl-state))) 38 | (assert post)) 39 | -------------------------------------------------------------------------------- /serval/unicorn/arm.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require ffi/unsafe) 4 | 5 | (provide (all-defined-out)) 6 | 7 | (require "const/arm.rkt" 8 | "engine.rkt") 9 | 10 | (struct arm-engine (ptr mode) 11 | #:methods gen:engine 12 | [(define (engine-ptr engine) 13 | (arm-engine-ptr engine)) 14 | (define (engine-reg-enum engine) 15 | _uc_arm_reg) 16 | (define (engine-reg-type engine reg) 17 | (case reg 18 | [else _uint32]))]) 19 | -------------------------------------------------------------------------------- /serval/unicorn/arm64.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require ffi/unsafe) 4 | 5 | (provide (all-defined-out)) 6 | 7 | (require "const/arm64.rkt" 8 | "engine.rkt") 9 | 10 | (struct arm64-engine (ptr mode) 11 | #:methods gen:engine 12 | [(define (engine-ptr engine) 13 | (arm64-engine-ptr engine)) 14 | (define (engine-reg-enum engine) 15 | _uc_arm64_reg) 16 | (define (engine-reg-type engine reg) 17 | (case reg 18 | ; FIXME: VFP/Neon registers 19 | [else _uint64]))]) 20 | -------------------------------------------------------------------------------- /serval/unicorn/engine.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require racket/generic) 4 | 5 | (provide (all-defined-out)) 6 | 7 | (define-generics engine 8 | (engine-ptr engine) 9 | (engine-reg-enum engine) 10 | (engine-reg-type engine reg)) 11 | -------------------------------------------------------------------------------- /serval/unicorn/gen.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ./const_generator.py python/unicorn_const.py \ 4 | --enum UC_ARCH \ 5 | --enum UC_ERR \ 6 | --enum UC_MEM \ 7 | --enum UC_HOOK \ 8 | --bitmask UC_MODE \ 9 | --bitmask UC_PROT \ 10 | > const/unicorn.rkt 11 | 12 | ./const_generator.py python/x86_const.py \ 13 | --enum UC_X86_REG \ 14 | --enum UC_X86_INS \ 15 | > const/x86.rkt 16 | 17 | ./const_generator.py python/arm64_const.py \ 18 | --enum UC_ARM64_REG \ 19 | > const/arm64.rkt 20 | 21 | ./const_generator.py python/arm_const.py \ 22 | --enum UC_ARM_REG \ 23 | > const/arm.rkt 24 | -------------------------------------------------------------------------------- /serval/unicorn/x86.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require ffi/unsafe) 4 | 5 | (provide (all-defined-out)) 6 | 7 | (require "const/x86.rkt" 8 | "engine.rkt") 9 | 10 | (define-cstruct _uc_x86_mmr ([selector _uint16] [base _uint64] [limit _uint32] [flags _uint32])) 11 | 12 | (define-cstruct _uc_x86_msr ([rid _uint32] [value _uint64])) 13 | 14 | (struct x86-engine (ptr mode) 15 | #:methods gen:engine 16 | [(define (engine-ptr engine) 17 | (x86-engine-ptr engine)) 18 | (define (engine-reg-enum engine) 19 | _uc_x86_reg) 20 | (define (engine-reg-type engine reg) 21 | (case reg 22 | [(idtr gdtr ldtr tr) _uc_x86_mmr] 23 | [(msr) _uc_x86_msr] 24 | ; FIXME: FP/SEE registers 25 | ; be safe - default to 64-bit 26 | [else _uint64]))]) 27 | -------------------------------------------------------------------------------- /serval/x86.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "x86/base.rkt" 4 | "x86/decode.rkt" 5 | "x86/interp.rkt" 6 | "x86/register.rkt") 7 | 8 | (provide 9 | (all-from-out 10 | "x86/base.rkt" 11 | "x86/decode.rkt" 12 | "x86/interp.rkt" 13 | "x86/register.rkt")) 14 | -------------------------------------------------------------------------------- /serval/x86/decode.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | (prefix-in core: "../lib/core.rkt") 5 | (only-in "base.rkt" instruction-encode)) 6 | 7 | (provide 8 | add-decoder decode) 9 | 10 | 11 | (define debug (make-parameter (getenv "DEBUG_X86"))) 12 | (define decoders null) 13 | 14 | (define (add-decoder proc) 15 | (set! decoders (cons proc decoders))) 16 | 17 | (define (decode lst) 18 | (cond 19 | [(null? lst) null] 20 | [else 21 | (define result (filter-map (lambda (proc) (proc lst)) decoders)) 22 | ; JIT might produce infeasible bytes under symbolic evaluation. 23 | ; Use assert to prune such cases. 24 | (when (null? result) 25 | (when (debug) 26 | (disassemble lst)) 27 | (core:bug #:msg (format "no decoder for ~a" lst))) 28 | (core:bug-on (! (= (length result) 1)) #:msg (format "ambiguity in decoding for ~a" lst)) 29 | (define insn (car (first result))) 30 | (define rest (cdr (first result))) 31 | (define act-bytes (take lst (- (length lst) (length rest)))) 32 | (define exp-bytes (instruction-encode insn)) 33 | (assert (equal? act-bytes exp-bytes) 34 | "encoded bytes must match original bytes") 35 | (cons insn (decode rest))])) 36 | 37 | (define (disassemble lst) 38 | (eprintf "no decoder for ~a\n" lst) 39 | (set! lst (evaluate lst (complete-solution (sat) (symbolics lst)))) 40 | (define in (open-input-string (string-join (map (lambda (x) (format "0x~x " (bitvector->natural x))) lst)))) 41 | (define out (open-output-string)) 42 | (parameterize ([current-input-port in] 43 | [current-output-port out]) 44 | (system* (find-executable-path "llvm-mc") "--disassemble")) 45 | (displayln (get-output-string out)) 46 | (exit 1)) 47 | -------------------------------------------------------------------------------- /serval/x86/interp.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "interp/adc.rkt" 5 | "interp/add.rkt" 6 | "interp/and.rkt" 7 | "interp/bswap.rkt" 8 | "interp/call.rkt" 9 | "interp/cmp.rkt" 10 | "interp/div.rkt" 11 | "interp/jcc.rkt" 12 | "interp/jmp.rkt" 13 | "interp/mov.rkt" 14 | "interp/movzx.rkt" 15 | "interp/mul.rkt" 16 | "interp/neg.rkt" 17 | "interp/or.rkt" 18 | "interp/pop.rkt" 19 | "interp/push.rkt" 20 | "interp/ret.rkt" 21 | "interp/rotate.rkt" 22 | "interp/sbb.rkt" 23 | "interp/shift.rkt" 24 | "interp/shld.rkt" 25 | "interp/shrd.rkt" 26 | "interp/sub.rkt" 27 | "interp/test.rkt" 28 | "interp/xchg.rkt" 29 | "interp/xor.rkt" 30 | ) 31 | 32 | (provide (all-from-out 33 | "interp/adc.rkt" 34 | "interp/add.rkt" 35 | "interp/and.rkt" 36 | "interp/bswap.rkt" 37 | "interp/call.rkt" 38 | "interp/cmp.rkt" 39 | "interp/div.rkt" 40 | "interp/jcc.rkt" 41 | "interp/jmp.rkt" 42 | "interp/mov.rkt" 43 | "interp/movzx.rkt" 44 | "interp/mul.rkt" 45 | "interp/neg.rkt" 46 | "interp/or.rkt" 47 | "interp/pop.rkt" 48 | "interp/push.rkt" 49 | "interp/ret.rkt" 50 | "interp/rotate.rkt" 51 | "interp/sbb.rkt" 52 | "interp/shift.rkt" 53 | "interp/shld.rkt" 54 | "interp/shrd.rkt" 55 | "interp/sub.rkt" 56 | "interp/test.rkt" 57 | "interp/xchg.rkt" 58 | "interp/xor.rkt" 59 | )) 60 | -------------------------------------------------------------------------------- /serval/x86/interp/bswap.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | bswap-r32 8 | bswap-r64) 9 | 10 | 11 | (define (interpret-bswap cpu dst) 12 | (define v (cpu-gpr-ref cpu dst)) 13 | (define result (core:list->bitvector/le (reverse (core:bitvector->list/le v)))) 14 | (cpu-gpr-set! cpu dst result)) 15 | 16 | ; 0F C8+rd 17 | (define-insn bswap-r32 (dst) 18 | #:decode [((byte #x0F) (+r #xC8 reg)) 19 | (list (gpr32-no-rex reg))] 20 | [((rex/r b) (byte #x0F) (+r #xC8 reg)) 21 | (list (gpr32 b reg))] 22 | #:encode (list (rex/r dst) (byte #x0F) (+r #xC8 dst)) 23 | interpret-bswap) 24 | 25 | ; REX.W + 0F C8+rd 26 | (define-insn bswap-r64 (dst) 27 | #:decode [((rex.w/r b) (byte #x0F) (+r #xC8 reg)) 28 | (list (gpr64 b reg))] 29 | #:encode (list (rex.w/r dst) (byte #x0F) (+r #xC8 dst)) 30 | interpret-bswap) 31 | -------------------------------------------------------------------------------- /serval/x86/interp/call.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | call-rel32) 8 | 9 | 10 | ; E8 cd 11 | (define (interpret-relative-call cpu rel) 12 | (define mm (cpu-memmgr cpu)) 13 | (define n (core:memmgr-bitwidth mm)) 14 | (define size (bv (quotient n 8) n)) 15 | (define pc (cpu-pc-ref cpu)) 16 | 17 | ; Add 5 bytes for this instruction 18 | (define ret-addr (bvadd pc (bv 5 (type-of pc)))) 19 | 20 | ; Push return address to stack 21 | (define sp (bvsub (trunc n (cpu-gpr-ref cpu rsp)) size)) 22 | (cpu-gpr-set! cpu rsp (zero-extend sp (bitvector 64))) 23 | (core:memmgr-store! mm sp (bv 0 n) ret-addr size) 24 | 25 | ; Jump to offset 26 | (cpu-pc-next! cpu (sign-extend rel (bitvector 64)))) 27 | 28 | (define-insn call-rel32 (rel32) 29 | #:decode [((byte #xE8) i0 i1 i2 i3) 30 | (call-rel32 (decode-imm i0 i1 i2 i3))] 31 | #:encode (list (byte #xE8) (encode-imm rel32)) 32 | (lambda (cpu rel32) 33 | (interpret-relative-call cpu rel32))) 34 | -------------------------------------------------------------------------------- /serval/x86/interp/common.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | (for-syntax (only-in racket/syntax format-id)) 5 | "../base.rkt" 6 | "../decode.rkt" 7 | "../register.rkt" 8 | "encoding.rkt" 9 | (prefix-in core: serval/lib/core)) 10 | 11 | (provide 12 | (for-syntax format-id) 13 | (all-defined-out) 14 | (all-from-out 15 | "../base.rkt" 16 | "../register.rkt" 17 | "encoding.rkt" 18 | serval/lib/core)) 19 | 20 | 21 | ; The main macro for defining instructions. 22 | 23 | (define-syntax (define-insn stx) 24 | (syntax-case stx () 25 | [(_ op (arg ...) #:decode [(pat ...) result] ... #:encode (encode ...) interp) 26 | #'(begin 27 | (add-decoder 28 | (lambda (lst) 29 | (define (ctor x) (if (list? x) (apply op x) x)) 30 | (match lst 31 | [(list pat ... rest ___) (cons (ctor result) rest)] ... 32 | [_ #f]))) 33 | (struct op (arg ...) 34 | #:transparent 35 | #:methods gen:instruction 36 | [(define (instruction-encode insn) 37 | (match-let ([(op arg ...) insn]) 38 | (flatten (encode ...)))) 39 | (define (instruction-run insn cpu) 40 | (match-let ([(op arg ...) insn]) 41 | (interp cpu arg ...)))]))])) 42 | 43 | 44 | ; flags 45 | 46 | (define (parity x) 47 | (bvnot (apply bvxor (for/list ([i (in-range (core:bv-size x))]) (bit i x))))) 48 | 49 | (define (cpu-pf+zf+sf-set! cpu val) 50 | (cpu-flag-set! cpu 'PF (parity (extract 7 0 val))) 51 | (cpu-flag-set! cpu 'ZF (bool->bitvector (bvzero? val))) 52 | (cpu-flag-set! cpu 'SF (msb val))) 53 | -------------------------------------------------------------------------------- /serval/x86/interp/div.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | div-r/m32 8 | div-r/m64) 9 | 10 | 11 | (define (interpret-div cpu src n) 12 | (define lower (trunc n (cpu-gpr-ref cpu rax))) 13 | (define upper (trunc n (cpu-gpr-ref cpu rdx))) 14 | (define v (trunc n (cpu-gpr-ref cpu src))) 15 | (core:bug-on (bvzero? v) 16 | #:msg "divide by zero") 17 | (define result 18 | (cond 19 | [(bvzero? upper) 20 | (cons ((core:bvudiv-proc) lower v) 21 | ((core:bvurem-proc) lower v))] 22 | [else 23 | (define v1 (concat upper lower)) 24 | (define v2 (concat (bv 0 n) v)) 25 | (define q ((core:bvudiv-proc) v1 v2)) 26 | (define r ((core:bvurem-proc) v1 v2)) 27 | (core:bug-on (bvugt q (concat (bv 0 n) (bv -1 n))) 28 | #:msg "divide overflow") 29 | (cons (trunc n q) 30 | (trunc n r))])) 31 | (cpu-gpr-set! cpu rax (zero-extend (car result) (bitvector 64))) 32 | (cpu-gpr-set! cpu rdx (zero-extend (cdr result) (bitvector 64))) 33 | ; CF, OF, SF, ZF, AF, and PF are undefined 34 | (cpu-flag-havoc! cpu 'CF 'OF 'SF 'ZF 'AF 'PF)) 35 | 36 | ; F7 /6 37 | (define-insn div-r/m32 (src) 38 | #:decode [((byte #xF7) (/6 r/m)) 39 | (list (gpr32-no-rex r/m))] 40 | [((rex/r b) (byte #xF7) (/6 r/m)) 41 | (list (gpr32 b r/m))] 42 | #:encode (list (rex/r src) (byte #xF7) (/6 src)) 43 | (lambda (cpu src) 44 | (interpret-div cpu src 32))) 45 | 46 | ; REX.W + F7 /6 47 | (define-insn div-r/m64 (src) 48 | #:decode [((rex.w/r b) (byte #xF7) (/6 r/m)) 49 | (list (gpr64 b r/m))] 50 | #:encode (list (rex.w/r src) (byte #xF7) (/6 src)) 51 | (lambda (cpu src) 52 | (interpret-div cpu src 64))) 53 | -------------------------------------------------------------------------------- /serval/x86/interp/jmp.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | jmp-rel8 8 | jmp-rel32 9 | jmp-r/m64-no-rex) 10 | 11 | 12 | ; EB cb 13 | (define-insn jmp-rel8 (rel8) 14 | #:decode [((byte #xEB) i0) 15 | (list (decode-imm i0))] 16 | #:encode (list (byte #xEB) (encode-imm rel8)) 17 | (lambda (cpu rel8) 18 | (cpu-pc-next! cpu (sign-extend rel8 (bitvector 64))))) 19 | 20 | 21 | ; E9 cd 22 | (define-insn jmp-rel32 (rel32) 23 | #:decode [((byte #xE9) i0 i1 i2 i3) 24 | (list (decode-imm i0 i1 i2 i3))] 25 | #:encode (list (byte #xE9) (encode-imm rel32)) 26 | (lambda (cpu rel32) 27 | (cpu-pc-next! cpu (sign-extend rel32 (bitvector 64))))) 28 | 29 | 30 | ; FF /4 31 | (define-insn jmp-r/m64-no-rex (src) 32 | #:decode [((byte #xFF) (/4 r/m)) 33 | (list (gpr64-no-rex r/m))] 34 | #:encode (list (byte #xFF) (/4 src)) 35 | (lambda (cpu src) 36 | ; deduct the instruction length for interpret-insn 37 | (cpu-pc-set! cpu (bvsub (cpu-gpr-ref cpu src) (bv 2 64))))) 38 | -------------------------------------------------------------------------------- /serval/x86/interp/neg.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | neg-r/m32 8 | neg-r/m64) 9 | 10 | 11 | (define (interpret-neg cpu dst) 12 | (define v (cpu-gpr-ref cpu dst)) 13 | (define n (core:bv-size v)) 14 | (define result (bvneg v)) 15 | (cpu-gpr-set! cpu dst result) 16 | (cpu-pf+zf+sf-set! cpu result) 17 | (cpu-flag-set! cpu 'CF (bool->bitvector (core:bvusub-overflow? (bv 0 n) v))) 18 | (cpu-flag-set! cpu 'OF (bool->bitvector (core:bvssub-overflow? (bv 0 n) v))) 19 | (cpu-flag-set! cpu 'AF (bool->bitvector (core:bvusub-overflow? (bv 0 4) (trunc 4 v))))) 20 | 21 | ; F7 /3 22 | (define-insn neg-r/m32 (dst) 23 | #:decode [((byte #xF7) (/3 r/m)) 24 | (list (gpr32-no-rex r/m))] 25 | [((rex/r b) (byte #xF7) (/3 r/m)) 26 | (list (gpr32 b r/m))] 27 | #:encode (list (rex/r dst) (byte #xF7) (/3 dst)) 28 | (lambda (cpu dst) 29 | (interpret-neg cpu dst))) 30 | 31 | ; REX.W + F7 /3 32 | (define-insn neg-r/m64 (dst) 33 | #:decode [((rex.w/r b) (byte #xF7) (/3 r/m)) 34 | (list (gpr64 b r/m))] 35 | #:encode (list (rex.w/r dst) (byte #xF7) (/3 dst)) 36 | (lambda (cpu dst) 37 | (interpret-neg cpu dst))) 38 | -------------------------------------------------------------------------------- /serval/x86/interp/pop.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | pop-r pop-r64 leave) 8 | 9 | (define (interpret-pop cpu dst) 10 | (define mm (cpu-memmgr cpu)) 11 | (define n (core:memmgr-bitwidth mm)) 12 | (define size (bv (quotient n 8) n)) 13 | (define sp (trunc n (cpu-gpr-ref cpu rsp))) 14 | (define v (core:memmgr-load mm sp (bv 0 n) size)) 15 | (cpu-gpr-set! cpu rsp (zero-extend (bvadd sp size) (bitvector 64))) 16 | (cpu-gpr-set! cpu dst (zero-extend v (bitvector 64)))) 17 | 18 | ; 58+rd 19 | (define-insn pop-r (dst) 20 | #:decode [((+r #x58 reg)) 21 | (list (gpr64-no-rex reg))] 22 | #:encode (list (+r #x58 dst)) 23 | interpret-pop) 24 | 25 | ; REX + 58+rd 26 | (define-insn pop-r64 (dst) 27 | #:decode [((rex/r b) (+r #x58 reg)) 28 | (list (gpr64 b reg))] 29 | #:encode (list (rex/r dst) (+r #x58 dst)) 30 | interpret-pop) 31 | 32 | ; C9 33 | (define-insn leave () 34 | #:decode [((byte #xC9)) 35 | (leave)] 36 | #:encode (list (byte #xC9)) 37 | (lambda (cpu) 38 | (cpu-gpr-set! cpu rsp (cpu-gpr-ref cpu rbp)) 39 | (interpret-pop cpu rbp))) -------------------------------------------------------------------------------- /serval/x86/interp/push.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | push-r push-r64) 8 | 9 | (define (interpret-push cpu src) 10 | (define mm (cpu-memmgr cpu)) 11 | (define n (core:memmgr-bitwidth mm)) 12 | (define size (bv (quotient n 8) n)) 13 | (define v (trunc n (cpu-gpr-ref cpu src))) 14 | (define sp (bvsub (trunc n (cpu-gpr-ref cpu rsp)) size)) 15 | (cpu-gpr-set! cpu rsp (zero-extend sp (bitvector 64))) 16 | (core:memmgr-store! mm sp (bv 0 n) v size)) 17 | 18 | ; 50+rd 19 | (define-insn push-r (src) 20 | #:decode [((+r #x50 reg)) 21 | (list (gpr64-no-rex reg))] 22 | #:encode (list (+r #x50 src)) 23 | interpret-push) 24 | 25 | ; REX + 50+rd 26 | (define-insn push-r64 (src) 27 | #:decode [((rex/r b) (+r #x50 src)) 28 | (list (gpr64 b src))] 29 | #:encode (list (rex/r src) (+r #x50 src)) 30 | interpret-push) 31 | -------------------------------------------------------------------------------- /serval/x86/interp/ret.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | ret-near) 8 | 9 | 10 | ; C3 11 | (define (interpret-return cpu) 12 | (define mm (cpu-memmgr cpu)) 13 | (define n (core:memmgr-bitwidth mm)) 14 | (define size (bv (quotient n 8) n)) 15 | (define pc (cpu-pc-ref cpu)) 16 | 17 | ; Load return address 18 | (define ret-addr 19 | (core:memmgr-load mm (trunc n (cpu-gpr-ref cpu rsp)) (bv 0 n) size)) 20 | 21 | ; Pop addr from stack 22 | (define sp (bvadd (trunc n (cpu-gpr-ref cpu rsp)) size)) 23 | (cpu-gpr-set! cpu rsp (zero-extend sp (bitvector 64))) 24 | 25 | ; Jump to return address 26 | ; Subtract 1 to adjust for cpu-next! in interpret-insn 27 | (set-cpu-pc! cpu (bvsub1 ret-addr))) 28 | 29 | (define-insn ret-near () 30 | #:decode [((byte #xC3)) 31 | (ret-near)] 32 | #:encode (list (byte #xC3)) 33 | (lambda (cpu) 34 | (interpret-return cpu))) 35 | -------------------------------------------------------------------------------- /serval/x86/interp/xchg.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "common.rkt") 5 | 6 | (provide 7 | xchg-r/m32-r32 8 | xchg-r/m64-r64) 9 | 10 | 11 | (define (interpret-xchg cpu dst src) 12 | (define mm (cpu-memmgr cpu)) 13 | (when mm 14 | (core:memmgr-atomic-begin mm)) 15 | (define temp (cpu-gpr-ref cpu dst)) 16 | (cpu-gpr-set! cpu dst (cpu-gpr-ref cpu src)) 17 | (cpu-gpr-set! cpu src temp) 18 | (when mm 19 | (core:memmgr-atomic-end mm))) 20 | 21 | ; 87 /r 22 | (define-insn xchg-r/m32-r32 (dst src) 23 | #:decode [((byte #x87) (/r reg r/m)) 24 | (list (gpr32-no-rex r/m) (gpr32-no-rex reg))] 25 | [((rex/r r b) (byte #x87) (/r reg r/m)) 26 | (list (gpr32 b r/m) (gpr32 r reg))] 27 | #:encode (list (rex/r src dst) (byte #x87) (/r src dst)) 28 | interpret-xchg) 29 | 30 | (define-insn xchg-m32-r32 (dst src) 31 | #:decode [((byte #x87) (modr/m (== (bv #b00 2)) reg r/m)) 32 | (list (register-indirect (gpr64-no-rex r/m) #f 32) (gpr32-no-rex reg))] 33 | #:encode (let ([ed (register-encode dst)] 34 | [es (register-encode src)]) 35 | (list (rex/r (car es) (first ed)) (byte #x87) (modr/m (second ed) (cdr es) (third ed)) (fourth ed))) 36 | interpret-xchg) 37 | 38 | ; REX.W + 87 /r 39 | (define-insn xchg-r/m64-r64 (dst src) 40 | #:decode [((rex.w/r r b) (byte #x87) (/r reg r/m)) 41 | (list (gpr64 b r/m) (gpr64 r reg))] 42 | #:encode (list (rex.w/r src dst) (byte #x87) (/r src dst)) 43 | interpret-xchg) 44 | -------------------------------------------------------------------------------- /test/.gitignore: -------------------------------------------------------------------------------- 1 | o.riscv64/ 2 | -------------------------------------------------------------------------------- /test/arm32/branch-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Branch (immediate)" 8 | (arm32-case* [choose-imm24] 9 | b) 10 | )) 11 | 12 | (module+ test 13 | (time (run-tests tests))) 14 | -------------------------------------------------------------------------------- /test/arm32/extend-and-add.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Extend and Add" 8 | (arm32-case* [choose-reg/no-r15 choose-rotate choose-reg/no-r15] 9 | sxtb16 sxtb sxth 10 | uxtb16 uxtb uxth) 11 | )) 12 | 13 | (module+ test 14 | (time (run-tests tests))) 15 | -------------------------------------------------------------------------------- /test/arm32/integer-data-processing-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Integer Data Processing (two register and immediate)" 8 | (arm32-case* [choose-reg choose-reg choose-imm12] 9 | and-immediate 10 | eor-immediate 11 | sub-immediate 12 | rsb-immediate 13 | add-immediate 14 | adc-immediate 15 | sbc-immediate 16 | rsc-immediate) 17 | (arm32-case* [choose-reg choose-reg/no-r15 choose-imm12] 18 | ands-immediate 19 | eors-immediate 20 | subs-immediate 21 | rsbs-immediate 22 | adds-immediate 23 | adcs-immediate 24 | sbcs-immediate 25 | rscs-immediate) 26 | )) 27 | 28 | (module+ test 29 | (time (run-tests tests))) 30 | -------------------------------------------------------------------------------- /test/arm32/integer-data-processing-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Integer Data Processing (three register, immediate shift)" 8 | (arm32-case* [choose-reg choose-reg choose-imm5 choose-stype choose-reg] 9 | and-register 10 | eor-register 11 | sub-register 12 | rsb-register 13 | add-register 14 | adc-register 15 | sbc-register 16 | rsc-register) 17 | (arm32-case* [choose-reg choose-reg/no-r15 choose-imm5 choose-stype choose-reg] 18 | ands-register 19 | eors-register 20 | subs-register 21 | rsbs-register 22 | adds-register 23 | adcs-register 24 | sbcs-register 25 | rscs-register) 26 | )) 27 | 28 | (module+ test 29 | (time (run-tests tests))) 30 | -------------------------------------------------------------------------------- /test/arm32/integer-test-and-compare-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Integer Test and Compare (one register and immediate)" 8 | (arm32-case* [choose-reg choose-imm12] 9 | tst-immediate 10 | teq-immediate 11 | cmp-immediate 12 | cmn-immediate) 13 | )) 14 | 15 | (module+ test 16 | (time (run-tests tests))) 17 | -------------------------------------------------------------------------------- /test/arm32/integer-test-and-compare-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Integer Test and Compare (two register, immediate shift)" 8 | (arm32-case* [choose-reg choose-imm5 choose-stype choose-reg] 9 | tst-register 10 | teq-register 11 | cmp-register 12 | cmn-register) 13 | )) 14 | 15 | (module+ test 16 | (time (run-tests tests))) 17 | -------------------------------------------------------------------------------- /test/arm32/logical-arithmetic-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Logical Arithmetic (two register and immediate)" 8 | (arm32-case* [choose-reg choose-reg choose-imm12] 9 | orr-immediate) 10 | (arm32-case* [choose-reg choose-reg/no-r15 choose-imm12] 11 | orrs-immediate) 12 | (arm32-case* [choose-reg choose-imm12] 13 | mov-immediate) 14 | (arm32-case* [choose-reg/no-r15 choose-imm12] 15 | movs-immediate) 16 | )) 17 | 18 | (module+ test 19 | (time (run-tests tests))) 20 | -------------------------------------------------------------------------------- /test/arm32/logical-arithmetic-register-shifted-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Logical Arithmetic (three register, register shift)" 8 | (arm32-case* [choose-reg/no-r15 choose-reg/no-r15 choose-reg/no-r15 choose-stype choose-reg/no-r15] 9 | orr-register-shifted-register 10 | orrs-register-shifted-register) 11 | (arm32-case* [choose-reg/no-r15 choose-reg/no-r15 choose-stype choose-reg/no-r15] 12 | mov-register-shifted-register 13 | movs-register-shifted-register) 14 | )) 15 | 16 | (module+ test 17 | (time (run-tests tests))) 18 | -------------------------------------------------------------------------------- /test/arm32/logical-arithmetic-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Logical Arithmetic (three register, immediate shift)" 8 | (arm32-case* [choose-reg choose-reg choose-imm5 choose-stype choose-reg] 9 | orr-register) 10 | (arm32-case* [choose-reg choose-imm5 choose-stype choose-reg] 11 | mov-register) 12 | (arm32-case* [choose-reg choose-reg/no-r15 choose-imm5 choose-stype choose-reg] 13 | orrs-register) 14 | (arm32-case* [choose-reg/no-r15 choose-imm5 choose-stype choose-reg] 15 | movs-register) 16 | )) 17 | 18 | (module+ test 19 | (time (run-tests tests))) 20 | -------------------------------------------------------------------------------- /test/arm32/miscellaneous.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Miscellaneous" 8 | (arm32-case* [choose-reg/no-r15] 9 | blx-register) 10 | )) 11 | 12 | (module+ test 13 | (time (run-tests tests))) 14 | -------------------------------------------------------------------------------- /test/arm32/move-halfword-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Move Halfword (immediate)" 8 | (arm32-case* [choose-imm4 choose-reg/no-r15 choose-imm12] 9 | movt 10 | movw) 11 | )) 12 | 13 | (module+ test 14 | (time (run-tests tests))) 15 | -------------------------------------------------------------------------------- /test/arm32/multiply-and-accumulate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | ; avoid RdHi == RdLo 7 | (define (fixup-umuls/umulls ctor) 8 | (lambda (RdHi RdLo Rm Rn) 9 | (when (equal? RdHi RdLo) 10 | (define r0 (arm32:integer->gpr 0)) 11 | (define r1 (arm32:integer->gpr 1)) 12 | (set! RdLo (if (equal? RdLo r0) r1 r0))) 13 | (ctor RdHi RdLo Rm Rn))) 14 | 15 | (define tests 16 | (test-suite+ "Multiply and Accumulate" 17 | (arm32-case* [choose-reg/no-r15 choose-reg/no-r15 choose-reg/no-r15] 18 | mul 19 | muls) 20 | (arm32-case* [choose-reg/no-r15 choose-reg/no-r15 choose-reg/no-r15 choose-reg/no-r15] 21 | mls) 22 | (arm32-case* [choose-reg/no-r15 choose-reg/no-r15 choose-reg/no-r15 choose-reg/no-r15] 23 | (fixup-umuls/umulls arm32:umull) 24 | (fixup-umuls/umulls arm32:umulls)) 25 | )) 26 | 27 | (module+ test 28 | (time (run-tests tests))) 29 | -------------------------------------------------------------------------------- /test/arm32/reverse.tex: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Reverse Bit/Byte" 8 | (arm32-case* [choose-reg/no-r15 choose-reg/no-r15] 9 | rev 10 | rev16) 11 | )) 12 | 13 | (module+ test 14 | (time (run-tests tests))) 15 | -------------------------------------------------------------------------------- /test/arm32/signed-multiply-divide.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (test-suite+ "Signed multiply, Divide" 8 | (arm32-case* [choose-reg/no-r15 choose-reg/no-r15 choose-reg/no-r15] 9 | sdiv 10 | udiv) 11 | )) 12 | 13 | (module+ test 14 | (time (run-tests tests))) 15 | -------------------------------------------------------------------------------- /test/arm64/arithmetic-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Arithmetic (immediate)" 7 | (arm64-case* [choose-sf choose-sh choose-imm12 choose-reg choose-reg] 8 | add-immediate 9 | adds-immediate 10 | sub-immediate 11 | subs-immediate) 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/arm64/arithmetic-shifted-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Arithmetic (shifted register)" 7 | (arm64-case* [choose-sf choose-shift choose-reg choose-imm6 choose-reg choose-reg] 8 | add-shifted-register 9 | adds-shifted-register 10 | sub-shifted-register 11 | subs-shifted-register) 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/arm64/bit-operation.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Bit operation" 7 | (arm64-case* [choose-sf choose-reg choose-reg] 8 | rev 9 | rev16) 10 | (arm64-case* [choose-reg choose-reg] 11 | rev32) 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/arm64/bitfield-move.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Bitfield move" 7 | (arm64-case* [choose-sf choose-imm6 choose-imm6 choose-reg choose-reg] 8 | sbfm 9 | bfm 10 | ubfm) 11 | ; Shift (immediate), aliases of sbfm/ubfm 12 | (arm64-case* [choose-sf choose-imm6 choose-reg choose-reg] 13 | ; no ror yet 14 | asr 15 | lsl 16 | lsr) 17 | ; Sign-extend and Zero-extend, aliaes of sbfm/ubfm 18 | (arm64-case* [choose-sf choose-reg choose-reg] 19 | sxtb 20 | sxth) 21 | (arm64-case* [choose-reg choose-reg] 22 | sxtw 23 | uxtb 24 | uxth) 25 | )) 26 | 27 | (module+ test 28 | (time (run-tests tests))) 29 | -------------------------------------------------------------------------------- /test/arm64/branches.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Arithmetic (immediate)" 7 | ; Conditional branch 8 | (arm64-case* [choose-imm19 choose-cond] 9 | b.cond) 10 | ; Unconditional branch (immediate) 11 | (arm64-case* [choose-imm26] 12 | b 13 | bl) 14 | )) 15 | 16 | (module+ test 17 | (time (run-tests tests))) 18 | -------------------------------------------------------------------------------- /test/arm64/load-store-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Shift (register)" 7 | ; test only with Rm=0 (offset) and Rn=sp for now 8 | (arm64-case* [choose-sp choose-option choose-sf choose-sp choose-reg] 9 | strb 10 | strh 11 | str32 12 | str64 13 | ldrb 14 | ldrh 15 | ldr32 16 | ldr64) 17 | )) 18 | 19 | (module+ test 20 | (time (run-tests tests))) 21 | -------------------------------------------------------------------------------- /test/arm64/logical-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Logical (immediate)" 7 | (arm64-case* [choose-sf choose-sf choose-imm6 choose-imm6 choose-reg choose-reg] 8 | and-immediate 9 | ands-immediate 10 | eor-immediate 11 | orr-immediate) 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/arm64/logical-shifted-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Logical (shifted register)" 7 | (arm64-case* [choose-sf choose-shift choose-reg choose-imm6 choose-reg choose-reg] 8 | and-shifted-register 9 | bic-shifted-register 10 | orr-shifted-register 11 | orn-shifted-register 12 | eor-shifted-register 13 | eon-shifted-register 14 | ands-shifted-register 15 | bics-shifted-register) 16 | )) 17 | 18 | (module+ test 19 | (time (run-tests tests))) 20 | -------------------------------------------------------------------------------- /test/arm64/move-wide-immediate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Move (wide immediate)" 7 | (arm64-case* [choose-sf choose-hw choose-imm16 choose-reg] 8 | movn 9 | movz 10 | movk) 11 | )) 12 | 13 | (module+ test 14 | (time (run-tests tests))) 15 | -------------------------------------------------------------------------------- /test/arm64/multiply-and-divide.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Multiply and divide" 7 | ; Multiply 8 | (arm64-case* [choose-sf choose-reg choose-reg choose-reg choose-reg] 9 | madd 10 | msub) 11 | ; Divide 12 | (arm64-case* [choose-sf choose-reg choose-reg choose-reg] 13 | udiv 14 | sdiv) 15 | )) 16 | 17 | (module+ test 18 | (time (run-tests tests))) 19 | -------------------------------------------------------------------------------- /test/arm64/shift-register.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require "lib.rkt") 4 | 5 | (define tests 6 | (test-suite+ "Shift (register)" 7 | (arm64-case* [choose-sf choose-reg choose-reg choose-reg] 8 | lslv 9 | lsrv 10 | asrv 11 | rorv) 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/array.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | struct A { uint32_t x, y; } as[4]; 4 | uint32_t arr[4]; 5 | 6 | uint32_t test(uint32_t x) 7 | { 8 | uint32_t idx = x % 4; 9 | 10 | as[idx].y = 9; 11 | arr[(idx + 1) % 4] = as[idx].y; 12 | return arr[(idx + 1) % 4]; 13 | } 14 | -------------------------------------------------------------------------------- /test/array.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require (except-in rackunit fail) 4 | rackunit/text-ui 5 | rosette/lib/roseunit 6 | (prefix-in llvm: serval/llvm) 7 | serval/lib/unittest 8 | serval/lib/core) 9 | 10 | (require "generated/racket/test/array.globals.rkt" 11 | "generated/racket/test/array.map.rkt") 12 | 13 | (require "generated/racket/test/array.ll.rkt") 14 | 15 | (define N 4) 16 | 17 | (define (inv) 18 | (define-symbolic i (bitvector 64)) 19 | (define b0 (llvm:symbol->block 'as)) 20 | (define b1 (llvm:symbol->block 'arr)) 21 | (forall (list i) (=> (bvult i (bv N 64)) 22 | (equal? (mblock-iload b0 (list i 'y)) 23 | (mblock-iload b1 (list (bvurem (bvadd1 i) (bv 4 64)))))))) 24 | 25 | (define (check-array-spec) 26 | (parameterize ([llvm:current-machine (llvm:make-machine symbols globals)]) 27 | (define-symbolic x (bitvector 32)) 28 | (assume (inv)) 29 | (@test x) 30 | (assert (inv)))) 31 | 32 | (define array-tests 33 | (test-suite+ 34 | "Tests for array.c" 35 | (test-case+ "check-array-spec" (check-array-spec)))) 36 | 37 | (module+ test 38 | (time (run-tests array-tests))) 39 | -------------------------------------------------------------------------------- /test/bext.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | typedef uint32_t uint_xlen_t; 4 | #define uint_xlen_t(n) ((uint_xlen_t) (n)) 5 | #define XLEN 32 6 | 7 | uint_xlen_t bext(uint_xlen_t rs1, uint_xlen_t rs2) 8 | { 9 | uint_xlen_t r = 0; 10 | for (int i = 0, j = 0; i < XLEN; i++) 11 | if ((rs2 >> i) & 1) { 12 | if ((rs1 >> i) & 1) 13 | r |= uint_xlen_t(1) << j; 14 | j++; 15 | } 16 | return r; 17 | } 18 | -------------------------------------------------------------------------------- /test/bext.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require serval/lib/core 4 | (prefix-in llvm: serval/llvm) 5 | serval/lib/unittest) 6 | 7 | (require "generated/racket/test/bext.ll.rkt") 8 | 9 | ; Racket implementation 10 | (define (bext_rkt rs1 rs2) 11 | (define r (bv 0 32)) 12 | (define j (bv 0 32)) 13 | (for ([i (range 32)]) 14 | (when (! (bveq (bv 0 32) (bvand (bv 1 32) (bvashr rs2 (bv i 32))))) 15 | (when (! (bveq (bv 0 32) (bvand (bv 1 32) (bvashr rs1 (bv i 32))))) 16 | (set! r (bvor r (bvshl (bv 1 32) j)))) 17 | (set! j (bvadd (bv 1 32) j)))) 18 | r) 19 | 20 | (define (check-bext) 21 | (parameterize ([llvm:current-machine (llvm:make-machine null null)]) 22 | (define-symbolic* rs1 rs2 (bitvector 32)) 23 | (displayln "executing...") 24 | (define val (@bext rs1 rs2)) 25 | (displayln "solving...") 26 | 27 | ; The generated terms are too complicated to prove things about directly, 28 | ; so just prove it's equal for one particular value of rs2 as a sanity check. 29 | (assert (=> (bveq rs2 (bv #xfffdfffe 32)) (bveq val (bext_rkt rs1 rs2)))))) 30 | 31 | (define bext-tests 32 | (test-suite+ 33 | "Tests for bext merging" 34 | (test-case+ "bext check" (check-bext)) 35 | )) 36 | 37 | ;;; (module+ test 38 | ;;; (time (run-tests bext-tests))) 39 | -------------------------------------------------------------------------------- /test/bpf/.gitignore: -------------------------------------------------------------------------------- 1 | test_bpf.rkt 2 | -------------------------------------------------------------------------------- /test/bpf/COPYING: -------------------------------------------------------------------------------- 1 | The Linux Kernel is provided under: 2 | 3 | SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 4 | 5 | Being under the terms of the GNU General Public License version 2 only, 6 | according with: 7 | 8 | LICENSES/preferred/GPL-2.0 9 | 10 | With an explicit syscall exception, as stated at: 11 | 12 | LICENSES/exceptions/Linux-syscall-note 13 | 14 | In addition, other licenses may also apply. Please see: 15 | 16 | Documentation/process/license-rules.rst 17 | 18 | for more details. 19 | 20 | All contributions to the Linux Kernel are subject to this COPYING file. 21 | -------------------------------------------------------------------------------- /test/bpf/bpf.mk: -------------------------------------------------------------------------------- 1 | check-bpf: bpf/test_bpf.rkt bpf/jmp32.rkt 2 | $(RACO_TEST) $^ 3 | 4 | bpf/test_bpf.rkt: bpf/test_bpf.c bpf/gen.py 5 | bpf/gen.py < $< > $@~ 6 | mv $@~ $@ 7 | -------------------------------------------------------------------------------- /test/bpf/bpftests.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | serval/bpf 5 | serval/lib/unittest) 6 | 7 | (provide (all-defined-out) (all-from-out serval/bpf serval/lib/unittest)) 8 | 9 | (define R0 BPF_REG_0) 10 | (define R1 BPF_REG_1) 11 | (define R2 BPF_REG_2) 12 | (define R3 BPF_REG_3) 13 | (define R4 BPF_REG_4) 14 | (define R5 BPF_REG_5) 15 | (define R6 BPF_REG_6) 16 | (define R7 BPF_REG_7) 17 | (define R8 BPF_REG_8) 18 | (define R9 BPF_REG_9) 19 | (define R10 BPF_REG_10) 20 | 21 | (define (cpu_to_be16 x) 22 | (integer-bytes->integer (integer->integer-bytes x 2 #f #t) #f)) 23 | 24 | (define (cpu_to_be32 x) 25 | (integer-bytes->integer (integer->integer-bytes x 4 #f #t) #f)) 26 | 27 | (define (cpu_to_be64 x) 28 | (integer-bytes->integer (integer->integer-bytes x 8 #f #t) #f)) 29 | 30 | (define (cpu_to_le16 x) 31 | (integer-bytes->integer (integer->integer-bytes x 2 #f #f) #f)) 32 | 33 | (define (cpu_to_le32 x) 34 | (integer-bytes->integer (integer->integer-bytes x 4 #f #f) #f)) 35 | 36 | (define (cpu_to_le64 x) 37 | (integer-bytes->integer (integer->integer-bytes x 8 #f #f) #f)) 38 | 39 | (define (run-insns result . insns) 40 | (define cpu (init-cpu #f)) 41 | (define actual (interpret-program cpu (make-insns insns))) 42 | (check-unsat? (verify (assert (equal? actual (bv result 32)))))) 43 | 44 | (define-syntax-rule (bpf-test-case name #:result result ...) 45 | (test-case+ name (run-insns result ...))) 46 | -------------------------------------------------------------------------------- /test/bpf/jmp32.rkt: -------------------------------------------------------------------------------- 1 | #lang racket 2 | 3 | (require "bpftests.rkt") 4 | 5 | (define jmp32-tests (test-suite+ "Tests for BPF (jmp32)" 6 | (bpf-test-case "JMP32: JLT X" 7 | #:result #x2 8 | (BPF_ALU64_IMM BPF_MOV R0 0) 9 | (BPF_ALU64_IMM BPF_MOV R2 2) 10 | (BPF_ALU64_IMM BPF_LSH R2 40) 11 | (BPF_JMP32_REG BPF_JEQ R0 R2 1) 12 | (BPF_EXIT_INSN) 13 | (BPF_ALU64_IMM BPF_MOV R0 2) 14 | (BPF_EXIT_INSN)) 15 | 16 | (bpf-test-case "JMP32: JLT K" 17 | #:result #x2 18 | (BPF_ALU64_IMM BPF_MOV R0 0) 19 | (BPF_ALU64_IMM BPF_MOV R1 2) 20 | (BPF_ALU64_IMM BPF_LSH R1 40) 21 | (BPF_JMP32_IMM BPF_JEQ R1 0 1) 22 | (BPF_EXIT_INSN) 23 | (BPF_ALU64_IMM BPF_MOV R0 2) 24 | (BPF_EXIT_INSN)))) 25 | 26 | (module+ test 27 | (time (run-tests jmp32-tests))) 28 | -------------------------------------------------------------------------------- /test/bugs.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require (except-in rackunit fail) 4 | rackunit/text-ui 5 | rosette/lib/roseunit 6 | serval/lib/unittest 7 | serval/lib/debug 8 | serval/lib/core) 9 | 10 | (define (check-bug-info) 11 | (define-symbolic a b boolean?) 12 | (bug-assert a #:msg (lambda (sol) (format "a is ~v" (evaluate a sol)))) 13 | (bug-assert a #:msg "another assertion about a") 14 | (bug-assert b #:msg (lambda (sol) (format "b is ~v" (evaluate b sol)))) 15 | (bug-assert b #:msg "another assertion about b") 16 | (void)) 17 | 18 | (define bug-info-tests 19 | (test-suite+ 20 | "Tests for bug info" 21 | (test-failure-case+ "check-bug-info" (check-bug-info)))) 22 | 23 | (module+ test 24 | (time (run-tests bug-info-tests))) 25 | -------------------------------------------------------------------------------- /test/config.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #define NR_PROCS 64 4 | #define NR_FDS 16 5 | #define NR_FILES 128 6 | -------------------------------------------------------------------------------- /test/constantexpr.c: -------------------------------------------------------------------------------- 1 | struct A { 2 | int x, y; 3 | }; 4 | 5 | struct A a; 6 | 7 | void set_x(int x) 8 | { 9 | a.x = x; 10 | } 11 | -------------------------------------------------------------------------------- /test/empty-dwarf.rkt: -------------------------------------------------------------------------------- 1 | #lang reader serval/lang/dwarf 2 | 3 | o.riscv64/global.elf: file format elf64-littleriscv 4 | 5 | -------------------------------------------------------------------------------- /test/fd.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "config.h" 3 | 4 | struct proc { 5 | uint64_t fds[NR_FDS]; 6 | }; 7 | 8 | struct file { 9 | uint64_t refcount; 10 | }; 11 | 12 | struct proc procs[NR_PROCS]; 13 | struct file files[NR_FILES]; 14 | uint64_t current; 15 | 16 | int close(long fd) 17 | { 18 | struct proc *proc; 19 | uint64_t fileid; 20 | struct file *file; 21 | 22 | proc = &procs[current]; 23 | if (fd < 0 || fd >= NR_FDS) 24 | return -1; 25 | fileid = proc->fds[fd]; 26 | if (fileid >= NR_FILES) 27 | return -1; 28 | file = &files[fileid]; 29 | --file->refcount; 30 | return 0; 31 | } 32 | -------------------------------------------------------------------------------- /test/generated/racket/test: -------------------------------------------------------------------------------- 1 | ../../o.riscv64/ -------------------------------------------------------------------------------- /test/global.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #define N 4096 5 | 6 | uint64_t val; 7 | uint32_t vals[N]; 8 | 9 | uint64_t get_value(void) 10 | { 11 | return val; 12 | } 13 | 14 | uint32_t get_value_i(size_t i) 15 | { 16 | return (i < N) ? vals[i] : -1; 17 | } 18 | 19 | void set_value(uint64_t x) 20 | { 21 | val = x; 22 | } 23 | 24 | void set_value_i(size_t i, uint32_t x) 25 | { 26 | if (i < N) 27 | vals[i] = x; 28 | } 29 | -------------------------------------------------------------------------------- /test/info.rkt: -------------------------------------------------------------------------------- 1 | #lang info 2 | 3 | (define compile-omit-paths 'all) 4 | -------------------------------------------------------------------------------- /test/inttoptr.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int global; 4 | volatile int *volatile pointer; 5 | 6 | __attribute__((noinline)) uintptr_t getglobal(void) 7 | { 8 | return (uintptr_t)&global; 9 | } 10 | 11 | /* Try to hide pointer arithmetic. */ 12 | __attribute__((noinline)) uintptr_t add1(uintptr_t x) {return x + 1;} 13 | __attribute__((noinline)) uintptr_t sub1(uintptr_t x) {return x - 1;} 14 | 15 | int test1(void) 16 | { 17 | uintptr_t a, b; 18 | 19 | a = getglobal(); 20 | b = getglobal(); 21 | 22 | *(volatile int *)(add1(sub1(a))) = 5; 23 | return *(volatile int *)(sub1(add1(b))) - 5; 24 | } 25 | 26 | int test2(void) 27 | { 28 | global = 0x42; 29 | 30 | pointer = &global; 31 | 32 | return *pointer - 0x42; 33 | } 34 | -------------------------------------------------------------------------------- /test/inttoptr.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require (except-in rackunit fail) 4 | rackunit/text-ui 5 | rosette/lib/roseunit 6 | serval/lib/core 7 | serval/lib/unittest 8 | (prefix-in llvm: serval/llvm)) 9 | 10 | (require "generated/racket/test/inttoptr.globals.rkt" 11 | "generated/racket/test/inttoptr.map.rkt") 12 | 13 | (require "generated/racket/test/inttoptr.ll.rkt") 14 | 15 | (define (check-test test-fn) 16 | (parameterize ([llvm:current-machine (llvm:make-machine symbols globals)]) 17 | (define ret (test-fn)) 18 | (check-true (bvzero? ret)) 19 | )) 20 | 21 | (define inttoptr-tests 22 | (test-suite+ 23 | "Tests for inttoptr.c" 24 | 25 | (test-case+ "test1" (check-test @test1)) 26 | (test-case+ "test2" (check-test @test2)) 27 | 28 | )) 29 | 30 | (module+ test 31 | (time (run-tests inttoptr-tests))) 32 | -------------------------------------------------------------------------------- /test/jumptable.c: -------------------------------------------------------------------------------- 1 | 2 | #define N 8 3 | 4 | typedef long (*function)(long); 5 | 6 | function table[N]; 7 | 8 | long add0(long x) {return x + 0;} 9 | long add1(long x) {return x + 1;} 10 | long add2(long x) {return x + 2;} 11 | long add3(long x) {return x + 3;} 12 | long add4(long x) {return x + 4;} 13 | long add5(long x) {return x + 5;} 14 | long add6(long x) {return x + 6;} 15 | long add7(long x) {return x + 7;} 16 | 17 | 18 | void init_table(void) 19 | { 20 | table[0] = add0; 21 | table[1] = add1; 22 | table[2] = add2; 23 | table[3] = add3; 24 | table[4] = add4; 25 | table[5] = add5; 26 | table[6] = add6; 27 | table[7] = add7; 28 | } 29 | 30 | void __attribute__((naked)) mret(void) 31 | { 32 | asm volatile("mret"); 33 | } 34 | 35 | long call_func(long x, unsigned long y) { 36 | y = y & 0x7; 37 | return table[y](x); 38 | } 39 | -------------------------------------------------------------------------------- /test/jumptable.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette/safe 2 | 3 | (require 4 | serval/lib/unittest 5 | serval/lib/core 6 | (prefix-in riscv: serval/riscv/objdump) 7 | (prefix-in jumptable: "generated/racket/test/jumptable.map.rkt") 8 | (prefix-in jumptable: "generated/racket/test/jumptable.globals.rkt") 9 | (prefix-in jumptable: "generated/racket/test/jumptable.asm.rkt") 10 | ) 11 | 12 | (define (find-symbol-start name) 13 | (define sym (find-symbol-by-name jumptable:symbols name)) 14 | (bv (car sym) (riscv:XLEN))) 15 | 16 | (define (check-jumptable) 17 | (define cpu (riscv:init-cpu jumptable:symbols jumptable:globals)) 18 | (define mret (find-symbol-start 'mret)) 19 | (define init-table (find-symbol-start 'init_table)) 20 | (define call-func (find-symbol-start 'call_func)) 21 | 22 | (riscv:gpr-set! cpu 'ra mret) 23 | (riscv:set-cpu-pc! cpu init-table) 24 | (check-vc (riscv:interpret-objdump-program cpu jumptable:instructions)) 25 | 26 | (define-symbolic* x y (bitvector 64)) 27 | 28 | (riscv:gpr-set! cpu 'a0 x) 29 | (riscv:gpr-set! cpu 'a1 y) 30 | (riscv:gpr-set! cpu 'a5 (make-bv64)) 31 | (riscv:gpr-set! cpu 'ra mret) 32 | (riscv:set-cpu-pc! cpu call-func) 33 | 34 | (check-vc (riscv:interpret-objdump-program cpu jumptable:instructions)) 35 | 36 | (define result (riscv:gpr-ref cpu 'a0)) 37 | 38 | (check-unsat? (verify (assert (bveq result (bvadd x (bvand y (bv 7 64))))))) 39 | 40 | (void)) 41 | 42 | (define jumptable-tests 43 | (test-suite+ 44 | "Tests for RISC-V jumptable" 45 | (test-case+ "check jumptable" (check-jumptable)) 46 | )) 47 | 48 | (module+ test 49 | (time (run-tests jumptable-tests))) 50 | -------------------------------------------------------------------------------- /test/memset.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #define N 10 5 | 6 | struct A { 7 | int x; 8 | struct B { 9 | int y, z; 10 | } b; 11 | }; 12 | 13 | struct A a[N]; 14 | 15 | uint8_t pages[N][4096]; 16 | uint8_t buffer[N]; 17 | 18 | __attribute__((naked)) 19 | void mret(void) 20 | { 21 | asm volatile("mret"); 22 | } 23 | 24 | __attribute__((noinline)) 25 | void *memset(void *p, int c, size_t len) 26 | { 27 | char *s = p; 28 | size_t i; 29 | 30 | for (i = 0; i < len; ++i) 31 | s[i] = c; 32 | 33 | return p; 34 | } 35 | 36 | void test_byte_buffer(void) 37 | { 38 | memset(buffer, 0, N); 39 | } 40 | 41 | void test_a0(void) 42 | { 43 | memset(a, 0, sizeof(struct A)); 44 | } 45 | 46 | void test_ai(size_t i) 47 | { 48 | if (i < N) 49 | memset(&a[i], 0, sizeof(struct A)); 50 | } 51 | 52 | void test_an(void) 53 | { 54 | memset(a, 0, sizeof(a)); 55 | } 56 | 57 | void test_b(size_t i) 58 | { 59 | if (i < N) 60 | memset(&a[i].b, 0, sizeof(struct B)); 61 | } 62 | 63 | void test_b_z(size_t i) 64 | { 65 | if (i < N) 66 | memset(&a[i].b.z, 0, sizeof(int)); 67 | } 68 | 69 | void test_pages(size_t lower, size_t upper) 70 | { 71 | if (lower <= upper && upper <= N) 72 | memset(&pages[lower], 0, (upper - lower) * 4096); 73 | } 74 | 75 | void test_buggy_too_large_a(void) 76 | { 77 | memset(a, 0, sizeof(a) + sizeof(struct A)); 78 | } 79 | 80 | void test_buggy_too_large_b(void) 81 | { 82 | memset(&a[0].b.z, 0, sizeof(struct B)); 83 | } 84 | 85 | void test_buggy_out_of_bounds(size_t i) 86 | { 87 | memset(&a[i], 0, sizeof(struct A)); 88 | } 89 | -------------------------------------------------------------------------------- /test/noop.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette/safe 2 | 3 | (require 4 | serval/lib/unittest 5 | serval/riscv/interp 6 | (prefix-in riscv: serval/riscv/objdump) 7 | (prefix-in noop: "generated/racket/test/noop.asm.rkt") 8 | ) 9 | 10 | (define (check-noop-riscv) 11 | (define cpu (riscv:init-cpu)) 12 | (riscv:interpret-objdump-program cpu noop:instructions) 13 | (check-true (vc-true? (vc)))) 14 | 15 | (define noop-tests 16 | (test-suite+ 17 | "Tests for RISC-V noop" 18 | (test-case+ "noop" (check-noop-riscv)) 19 | )) 20 | 21 | (module+ test 22 | (time (run-tests noop-tests))) 23 | -------------------------------------------------------------------------------- /test/riscv-tests/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.riscv 3 | *.host 4 | *.o 5 | *.dump 6 | *.out 7 | *.hex 8 | .*.swp 9 | *.pyc 10 | /autom4te.cache 11 | /Makefile 12 | /config.log 13 | /config.status 14 | /build 15 | -------------------------------------------------------------------------------- /test/riscv-tests/.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "env"] 2 | path = env 3 | url = https://github.com/riscv/riscv-test-env.git 4 | -------------------------------------------------------------------------------- /test/riscv-tests/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012-2015, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/.gitignore: -------------------------------------------------------------------------------- 1 | rv*-* 2 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32mi tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32mi_sc_tests = \ 6 | breakpoint \ 7 | csr \ 8 | mcsr \ 9 | illegal \ 10 | ma_fetch \ 11 | ma_addr \ 12 | scall \ 13 | sbreak \ 14 | shamt \ 15 | 16 | rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests)) 17 | 18 | spike32_tests += $(rv32mi_p_tests) 19 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/breakpoint.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/breakpoint.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/csr.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/illegal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/illegal.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/ma_addr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/ma_addr.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/ma_fetch.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/mcsr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/mcsr.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/sbreak.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/scall.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32mi/shamt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # csr.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test CSRRx and CSRRxI instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32M 14 | RVTEST_CODE_BEGIN 15 | 16 | # Make sure slli with shamt[4] set is legal. 17 | TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); 18 | 19 | # Make sure slli with shamt[5] set is not legal. 20 | TEST_CASE( 3, x0, 1, .word 0x02051513); # slli a0, a0, 32 21 | 22 | TEST_PASSFAIL 23 | 24 | .global mtvec_handler 25 | mtvec_handler: 26 | # Trapping on test 3 is good. 27 | # Note that since the test didn't complete, TESTNUM is smaller by 1. 28 | li t0, 2 29 | bne TESTNUM, t0, fail 30 | 31 | # Make sure CAUSE indicates an illegal instructino. 32 | csrr t0, mcause 33 | li t1, CAUSE_ILLEGAL_INSTRUCTION 34 | bne t0, t1, fail 35 | j pass 36 | 37 | RVTEST_CODE_END 38 | 39 | .data 40 | RVTEST_DATA_BEGIN 41 | 42 | TEST_DATA 43 | 44 | RVTEST_DATA_END 45 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32si/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32si tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32si_sc_tests = \ 6 | csr \ 7 | dirty \ 8 | ma_fetch \ 9 | scall \ 10 | sbreak \ 11 | wfi \ 12 | 13 | rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests)) 14 | 15 | spike32_tests += $(rv32si_p_tests) 16 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32si/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/csr.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32si/dirty.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #undef SATP_MODE_SV39 8 | #define SATP_MODE_SV39 SATP_MODE_SV32 9 | 10 | #include "../rv64si/dirty.S" 11 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32si/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/ma_fetch.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32si/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/sbreak.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32si/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/scall.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32si/wfi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/wfi.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ua tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ua_sc_tests = \ 6 | amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ 7 | # lrsc \ 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amoadd_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoadd_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amoand_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoand_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amomax_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomax_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amomaxu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomaxu_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amomin_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomin_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amominu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amominu_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amoor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoor_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amoswap_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoswap_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/amoxor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoxor_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ua/lrsc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/lrsc.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uc/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uc_sc_tests = \ 6 | rvc \ 7 | 8 | rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests)) 9 | rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests)) 10 | 11 | spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests) 12 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uc/rvc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uc/rvc.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ud tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ud_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst recoding \ 8 | 9 | # TODO: use this line instead of the last of the previous once move and structural tests have been implemented 10 | # ldst move structural recoding \ 11 | 12 | rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests)) 13 | rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests)) 14 | 15 | spike32_tests += $(rv32ud_p_tests) $(rv32ud_v_tests) 16 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fadd.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fclass.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fcmp.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fcvt.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fcvt_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcvt_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fdiv.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fmadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fmadd.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/fmin.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fmin.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32UF 14 | RVTEST_CODE_BEGIN 15 | 16 | la s0, tdat 17 | TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 18 | TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 19 | TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 20 | TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 21 | TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 22 | 23 | TEST_PASSFAIL 24 | 25 | RVTEST_CODE_END 26 | 27 | .data 28 | RVTEST_DATA_BEGIN 29 | 30 | TEST_DATA 31 | 32 | tdat: 33 | .word 0xbf800000 34 | .word 0x40000000 35 | .word 0x40400000 36 | .word 0xc0800000 37 | .word 0xdeadbeef 38 | .word 0xcafebabe 39 | .word 0xabad1dea 40 | .word 0x1337d00d 41 | 42 | RVTEST_DATA_END 43 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/move.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ud/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/recoding.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uf tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uf_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests)) 10 | rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests)) 11 | 12 | spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests) 13 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fadd.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fclass.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcmp.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcvt.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fcvt_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcvt_w.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fdiv.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fmadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fmadd.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/fmin.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fmin.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32UF 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1)) 17 | TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1)) 18 | 19 | TEST_PASSFAIL 20 | 21 | RVTEST_CODE_END 22 | 23 | .data 24 | RVTEST_DATA_BEGIN 25 | 26 | TEST_DATA 27 | 28 | tdat: 29 | .word 0xbf800000 30 | .word 0x40000000 31 | .word 0x40400000 32 | .word 0xc0800000 33 | .word 0xdeadbeef 34 | .word 0xcafebabe 35 | .word 0xabad1dea 36 | .word 0x1337d00d 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/move.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32uf/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/recoding.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ui tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ui_sc_tests = \ 6 | simple \ 7 | add addi \ 8 | and andi \ 9 | auipc \ 10 | beq bge bgeu blt bltu bne \ 11 | jal jalr \ 12 | lui \ 13 | or ori \ 14 | sll slli \ 15 | slt slti sltiu sltu \ 16 | sra srai \ 17 | srl srli \ 18 | sub \ 19 | xor xori \ 20 | sw \ 21 | # fence_i \ 22 | # sb sh sw \ 23 | # lb lbu lh lhu lw \ -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/add.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/add.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/addi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/addi.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/and.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/and.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/andi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/andi.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/auipc.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/beq.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/beq.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/bge.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bge.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/bgeu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bgeu.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/blt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/blt.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/bltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bltu.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/bne.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bne.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/fence_i.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/fence_i.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/jal.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/jalr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/jalr.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/lb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lb.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/lbu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lbu.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/lh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lh.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/lhu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lhu.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lui.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/lw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lw.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/or.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/or.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/ori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/ori.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sb.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sh.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/simple.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sll.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sll.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/slli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slli.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/slt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slt.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/slti.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slti.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sltiu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sltiu.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sltu.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sra.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sra.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/srai.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srai.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/srl.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srl.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/srli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srli.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sub.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sub.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/sw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sw.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/xor.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/xor.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32ui/xori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/xori.S" 8 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32um/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32um tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32um_sc_tests = \ 6 | div divu \ 7 | mul mulh mulhsu mulhu \ 8 | rem remu \ 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32um/div.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # div.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test div instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, div, 3, 20, 6 ); 21 | TEST_RR_OP( 3, div, -3, -20, 6 ); 22 | TEST_RR_OP( 4, div, -3, 20, -6 ); 23 | TEST_RR_OP( 5, div, 3, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, div, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, div, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, div, -1, 1, 0 ); 30 | TEST_RR_OP(10, div, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32um/divu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divu, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divu, 715827879, -20, 6 ); 22 | TEST_RR_OP( 4, divu, 0, 20, -6 ); 23 | TEST_RR_OP( 5, divu, 0, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, divu, -1, 1, 0 ); 30 | TEST_RR_OP(10, divu, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32um/rem.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # rem.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test rem instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, rem, 2, 20, 6 ); 21 | TEST_RR_OP( 3, rem, -2, -20, 6 ); 22 | TEST_RR_OP( 4, rem, 2, 20, -6 ); 23 | TEST_RR_OP( 5, rem, -2, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, rem, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, rem, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, rem, 1, 1, 0 ); 30 | TEST_RR_OP(10, rem, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv32um/remu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remu, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remu, 2, -20, 6 ); 22 | TEST_RR_OP( 4, remu, 20, 20, -6 ); 23 | TEST_RR_OP( 5, remu, -20, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remu, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, remu, 1, 1, 0 ); 30 | TEST_RR_OP(10, remu, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64mi/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64mi tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64mi_sc_tests = \ 6 | access \ 7 | breakpoint \ 8 | csr \ 9 | mcsr \ 10 | illegal \ 11 | ma_fetch \ 12 | ma_addr \ 13 | scall \ 14 | sbreak \ 15 | 16 | rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) 17 | 18 | spike_tests += $(rv64mi_p_tests) 19 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64mi/access.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # access.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test access-exception behavior. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64M 14 | RVTEST_CODE_BEGIN 15 | 16 | .align 2 17 | 18 | # Flipping just the MSB should result in an illegal address for RV64. 19 | la t2, fail 20 | li t0, 1 << (__riscv_xlen - 1) 21 | xor t0, t0, t2 22 | 23 | # jalr to an illegal address should commit (hence should write rd). 24 | # after the pc is set to rs1, an access exception should be raised. 25 | li TESTNUM, 2 26 | li t1, CAUSE_FETCH_ACCESS 27 | la t3, 1f 28 | li t2, 0 29 | jalr t2, t0 30 | 1: 31 | 32 | # A load to an illegal address should not commit. 33 | li TESTNUM, 3 34 | li t1, CAUSE_LOAD_ACCESS 35 | la t3, 1f 36 | mv t2, t3 37 | lb t2, (t0) 38 | j fail 39 | 1: 40 | 41 | j pass 42 | 43 | TEST_PASSFAIL 44 | 45 | .align 2 46 | .global mtvec_handler 47 | mtvec_handler: 48 | li a0, 2 49 | beq TESTNUM, a0, 2f 50 | li a0, 3 51 | beq TESTNUM, a0, 2f 52 | j fail 53 | 54 | 2: 55 | bne t2, t3, fail 56 | 57 | csrr t2, mcause 58 | bne t2, t1, fail 59 | 60 | csrw mepc, t3 61 | mret 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64mi/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/csr.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64mi/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/ma_fetch.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64mi/mcsr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # mcsr.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test various M-mode CSRs. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64M 14 | RVTEST_CODE_BEGIN 15 | 16 | # Check that mcpuid reports the correct XLEN 17 | #if __riscv_xlen == 64 18 | TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) 19 | #else 20 | TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) 21 | #endif 22 | 23 | # Check that mhartid reports 0 24 | TEST_CASE(3, a0, 0x0, csrr a0, mhartid) 25 | 26 | # Check that reading the following CSRs doesn't cause an exception 27 | csrr a0, mimpid 28 | csrr a0, marchid 29 | csrr a0, mvendorid 30 | 31 | # Check that writing hte following CSRs doesn't cause an exception 32 | li t0, 0 33 | csrs mtvec, t0 34 | csrs mepc, t0 35 | 36 | TEST_PASSFAIL 37 | 38 | RVTEST_CODE_END 39 | 40 | .data 41 | RVTEST_DATA_BEGIN 42 | 43 | TEST_DATA 44 | 45 | RVTEST_DATA_END 46 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64mi/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/sbreak.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64mi/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/scall.S" 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64si/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64si tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64si_sc_tests = \ 6 | csr \ 7 | dirty \ 8 | ma_fetch \ 9 | scall \ 10 | wfi \ 11 | sbreak \ 12 | 13 | rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) 14 | 15 | spike_tests += $(rv64si_p_tests) 16 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64si/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # scall.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test syscall trap. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64S 14 | RVTEST_CODE_BEGIN 15 | 16 | #ifdef __MACHINE_MODE 17 | #define sscratch mscratch 18 | #define sstatus mstatus 19 | #define scause mcause 20 | #define sepc mepc 21 | #define sret mret 22 | #define stvec_handler mtvec_handler 23 | #endif 24 | 25 | li TESTNUM, 2 26 | 27 | do_break: 28 | sbreak 29 | j fail 30 | 31 | TEST_PASSFAIL 32 | 33 | .align 2 34 | .global stvec_handler 35 | stvec_handler: 36 | li t1, CAUSE_BREAKPOINT 37 | csrr t0, scause 38 | bne t0, t1, fail 39 | la t1, do_break 40 | csrr t0, sepc 41 | bne t0, t1, fail 42 | j pass 43 | 44 | RVTEST_CODE_END 45 | 46 | .data 47 | RVTEST_DATA_BEGIN 48 | 49 | TEST_DATA 50 | 51 | RVTEST_DATA_END 52 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64si/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # scall.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test syscall trap. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64S 14 | RVTEST_CODE_BEGIN 15 | 16 | #ifdef __MACHINE_MODE 17 | #define sscratch mscratch 18 | #define sstatus mstatus 19 | #define scause mcause 20 | #define sepc mepc 21 | #define sret mret 22 | #define stvec_handler mtvec_handler 23 | #undef SSTATUS_SPP 24 | #define SSTATUS_SPP MSTATUS_MPP 25 | #endif 26 | 27 | li TESTNUM, 2 28 | 29 | # This is the expected trap code. 30 | li t1, CAUSE_USER_ECALL 31 | 32 | #ifdef __MACHINE_MODE 33 | # If running in M mode, use mstatus.MPP to check existence of U mode. 34 | # Otherwise, if in S mode, then U mode must exist and we don't need to check. 35 | li t0, MSTATUS_MPP 36 | csrc mstatus, t0 37 | csrr t2, mstatus 38 | and t0, t0, t2 39 | beqz t0, 1f 40 | 41 | # If U mode doesn't exist, mcause should indicate ECALL from M mode. 42 | li t1, CAUSE_MACHINE_ECALL 43 | #endif 44 | 45 | 1: 46 | li t0, SSTATUS_SPP 47 | csrc sstatus, t0 48 | la t0, 1f 49 | csrw sepc, t0 50 | sret 51 | 1: 52 | 53 | li TESTNUM, 1 54 | do_scall: 55 | scall 56 | j fail 57 | 58 | TEST_PASSFAIL 59 | 60 | .align 2 61 | .global stvec_handler 62 | stvec_handler: 63 | csrr t0, scause 64 | bne t0, t1, fail 65 | la t2, do_scall 66 | csrr t0, sepc 67 | bne t0, t2, fail 68 | j pass 69 | 70 | RVTEST_CODE_END 71 | 72 | .data 73 | RVTEST_DATA_BEGIN 74 | 75 | TEST_DATA 76 | 77 | RVTEST_DATA_END 78 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64si/wfi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # wfi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test wait-for-interrupt instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64S 14 | RVTEST_CODE_BEGIN 15 | 16 | # Make sure wfi doesn't halt the hart, even if interrupts are disabled 17 | csrc sstatus, SSTATUS_SIE 18 | csrs sie, SIP_SSIP 19 | csrs sip, SIP_SSIP 20 | wfi 21 | 22 | RVTEST_PASS 23 | 24 | TEST_PASSFAIL 25 | 26 | RVTEST_CODE_END 27 | 28 | .data 29 | RVTEST_DATA_BEGIN 30 | 31 | TEST_DATA 32 | 33 | RVTEST_DATA_END 34 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ua tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ua_sc_tests = \ 6 | amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ 7 | amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ 8 | # lrsc \ 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoadd_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoadd_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoadd.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoadd.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xffffffff7ffff800, \ 28 | amoadd.d a4, a1, 0(a3); \ 29 | ) 30 | 31 | TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) 32 | 33 | TEST_PASSFAIL 34 | 35 | RVTEST_CODE_END 36 | 37 | .data 38 | RVTEST_DATA_BEGIN 39 | 40 | TEST_DATA 41 | 42 | RVTEST_DATA_END 43 | 44 | .bss 45 | .align 3 46 | amo_operand: 47 | .dword 0 48 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoadd_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoadd_w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoadd.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoadd.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0x000000007ffff800, \ 28 | li a1, 0xffffffff80000000; \ 29 | amoadd.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoand_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoand_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoand.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoand.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xffffffff80000000, \ 28 | li a1, 0x0000000080000000; \ 29 | amoand.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoand_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoand.w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoand.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoand.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xffffffff80000000, \ 28 | li a1, 0x0000000080000000; \ 29 | amoand.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amomax_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomax_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomax.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amomax.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 1; \ 28 | sd x0, 0(a3); \ 29 | amomax.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 1, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amomax_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomax_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomax.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amomax.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 1; \ 28 | sw x0, 0(a3); \ 29 | amomax.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 1, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amomaxu_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomaxu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomaxu.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amomaxu.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sd x0, 0(a3); \ 29 | amomaxu.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amomaxu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomaxu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomaxu.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amomaxu.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sw x0, 0(a3); \ 29 | amomaxu.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amomin_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomin_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomin.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amomin.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sd x0, 0(a3); \ 29 | amomin.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amomin_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomin_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomin.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amomin.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sw x0, 0(a3); \ 29 | amomin.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amominu_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amominu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amominu.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amominu.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sd x0, 0(a3); \ 29 | amominu.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | 50 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amominu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amominu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amominu.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amominu.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sw x0, 0(a3); \ 29 | amominu.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | 50 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoor_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoor_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoor.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoor.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 1; \ 29 | amoor.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoor.w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoor.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoor.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 1; \ 29 | amoor.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoswap_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoswap.d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoswap.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoswap.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 0x0000000080000000; \ 29 | amoswap.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoswap_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoswap_w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoswap.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoswap.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 0x0000000080000000; \ 29 | amoswap.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoxor_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoxor_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoxor.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoxor.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0x000000007ffff800, \ 28 | li a1, 1; \ 29 | amoxor.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ua/amoxor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoxor_w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoxor.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoxor.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0x7ffff800, \ 28 | li a1, 0xc0000001; \ 29 | amoxor.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uc/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uc_sc_tests = \ 6 | rvc \ 7 | 8 | rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests)) 9 | rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests)) 10 | 11 | spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests) 12 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ud/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ud tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ud_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move structural recoding \ 8 | 9 | rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests)) 10 | rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests)) 11 | 12 | spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests) 13 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ud/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fclass.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fclass.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #if __riscv_xlen == 32 17 | # Replace the function with the 32-bit variant defined in test_macros.h 18 | #undef TEST_FCLASS_D 19 | #define TEST_FCLASS_D TEST_FCLASS_D32 20 | #endif 21 | 22 | #------------------------------------------------------------- 23 | # Arithmetic tests 24 | #------------------------------------------------------------- 25 | 26 | TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 ) 27 | TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 ) 28 | TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff ) 29 | TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 ) 30 | TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 ) 31 | TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff ) 32 | TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 ) 33 | TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 ) 34 | TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 ) 35 | TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 ) 36 | 37 | TEST_PASSFAIL 38 | 39 | RVTEST_CODE_END 40 | 41 | .data 42 | RVTEST_DATA_BEGIN 43 | 44 | TEST_DATA 45 | 46 | RVTEST_DATA_END 47 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ud/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fdiv.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{div|sqrt}.d instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #if __riscv_xlen == 32 17 | # Replace the functions with the 32-bit variants defined in test_macros.h 18 | #undef TEST_FP_OP2_D 19 | #define TEST_FP_OP2_D TEST_FP_OP2_D32 20 | 21 | #undef TEST_FP_OP1_D 22 | #define TEST_FP_OP1_D TEST_FP_OP1_D32 23 | 24 | #undef TEST_FP_OP1_D_DWORD_RESULT 25 | #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT 26 | #endif 27 | 28 | #------------------------------------------------------------- 29 | # Arithmetic tests 30 | #------------------------------------------------------------- 31 | 32 | TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); 33 | TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); 34 | TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); 35 | 36 | TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); 37 | TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 ); 38 | 39 | TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); 40 | 41 | TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0); 42 | 43 | TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); 44 | 45 | TEST_PASSFAIL 46 | 47 | RVTEST_CODE_END 48 | 49 | .data 50 | RVTEST_DATA_BEGIN 51 | 52 | TEST_DATA 53 | 54 | RVTEST_DATA_END 55 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ud/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | la s0, tdat 17 | TEST_CASE(2, a0, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); ld a0, 16(s0)) 18 | TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) 19 | TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) 20 | TEST_CASE(5, a0, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) 21 | TEST_CASE(6, a0, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) 22 | 23 | TEST_PASSFAIL 24 | 25 | RVTEST_CODE_END 26 | 27 | .data 28 | RVTEST_DATA_BEGIN 29 | 30 | TEST_DATA 31 | 32 | tdat: 33 | .word 0xbf800000 34 | .word 0x40000000 35 | .word 0x40400000 36 | .word 0xc0800000 37 | .word 0xdeadbeef 38 | .word 0xcafebabe 39 | .word 0xabad1dea 40 | .word 0x1337d00d 41 | 42 | RVTEST_DATA_END 43 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ud/structural.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # structural.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that the FPU correctly obviates structural hazards on its 8 | # writeback port (e.g. fadd followed by fsgnj) 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64UF 15 | RVTEST_CODE_BEGIN 16 | 17 | li x25, 1 18 | 19 | li x2, 0x3FF0000000000000 20 | li x1, 0x3F800000 21 | 22 | #define TEST(nops, errcode) \ 23 | fmv.d.x f4, x0 ;\ 24 | fmv.s.x f3, x0 ;\ 25 | fmv.d.x f2, x2 ;\ 26 | fmv.s.x f1, x1 ;\ 27 | j 1f ;\ 28 | .align 5 ;\ 29 | 1:fmul.d f4, f2, f2 ;\ 30 | nops ;\ 31 | fsgnj.s f3, f1, f1 ;\ 32 | fmv.x.d x4, f4 ;\ 33 | fmv.x.s x5, f3 ;\ 34 | beq x1, x5, 2f ;\ 35 | RVTEST_FAIL ;\ 36 | 2:beq x2, x4, 2f ;\ 37 | RVTEST_FAIL; \ 38 | 2:fmv.d.x f2, zero ;\ 39 | fmv.s.x f1, zero ;\ 40 | 41 | TEST(;,2) 42 | TEST(nop,4) 43 | TEST(nop;nop,6) 44 | TEST(nop;nop;nop,8) 45 | TEST(nop;nop;nop;nop,10) 46 | TEST(nop;nop;nop;nop;nop,12) 47 | TEST(nop;nop;nop;nop;nop;nop,14) 48 | 49 | RVTEST_PASS 50 | 51 | RVTEST_CODE_END 52 | 53 | .data 54 | RVTEST_DATA_BEGIN 55 | 56 | TEST_DATA 57 | 58 | RVTEST_DATA_END 59 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uf tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uf_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) 10 | rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) 11 | 12 | spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) 13 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fadd.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{add|sub|mul}.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_OP2_S( 2, fadd.s, 0, 3.5, 2.5, 1.0 ); 21 | TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 ); 22 | TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 ); 23 | 24 | TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 ); 25 | TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 ); 26 | TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); 27 | 28 | TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 ); 29 | TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 ); 30 | TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); 31 | 32 | # Is the canonical NaN generated for Inf - Inf? 33 | TEST_FP_OP2_S(11, fsub.s, 0x10, qNaNf, Inf, Inf); 34 | 35 | TEST_PASSFAIL 36 | 37 | RVTEST_CODE_END 38 | 39 | .data 40 | RVTEST_DATA_BEGIN 41 | 42 | TEST_DATA 43 | 44 | RVTEST_DATA_END 45 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fclass.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fclass.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FCLASS_S( 2, 1 << 0, 0xff800000 ) 21 | TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 ) 22 | TEST_FCLASS_S( 4, 1 << 2, 0x807fffff ) 23 | TEST_FCLASS_S( 5, 1 << 3, 0x80000000 ) 24 | TEST_FCLASS_S( 6, 1 << 4, 0x00000000 ) 25 | TEST_FCLASS_S( 7, 1 << 5, 0x007fffff ) 26 | TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 ) 27 | TEST_FCLASS_S( 9, 1 << 7, 0x7f800000 ) 28 | TEST_FCLASS_S(10, 1 << 8, 0x7f800001 ) 29 | TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 ) 30 | 31 | TEST_PASSFAIL 32 | 33 | RVTEST_CODE_END 34 | 35 | .data 36 | RVTEST_DATA_BEGIN 37 | 38 | TEST_DATA 39 | 40 | RVTEST_DATA_END 41 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fcmp.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{eq|lt|le}.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36) 21 | TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36) 22 | TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36) 23 | 24 | TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36) 25 | TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36) 26 | TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36) 27 | 28 | # Only sNaN should signal invalid for feq. 29 | TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0) 30 | TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN) 31 | TEST_FP_CMP_OP_S(10, feq.s, 0x10, 0, sNaNf, 0) 32 | 33 | # qNaN should signal invalid for fle/flt. 34 | TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0) 35 | TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN) 36 | TEST_FP_CMP_OP_S(13, flt.s, 0x10, 0, sNaNf, 0) 37 | TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0) 38 | TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN) 39 | TEST_FP_CMP_OP_S(16, fle.s, 0x10, 0, sNaNf, 0) 40 | 41 | TEST_PASSFAIL 42 | 43 | RVTEST_CODE_END 44 | 45 | .data 46 | RVTEST_DATA_BEGIN 47 | 48 | TEST_DATA 49 | 50 | RVTEST_DATA_END 51 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fcvt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_INT_FP_OP_S( 2, fcvt.s.w, 2.0, 2); 21 | TEST_INT_FP_OP_S( 3, fcvt.s.w, -2.0, -2); 22 | 23 | TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2); 24 | TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2); 25 | 26 | #if __riscv_xlen >= 64 27 | TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2); 28 | TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2); 29 | 30 | TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2); 31 | TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2); 32 | #endif 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fdiv.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{div|sqrt}.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); 21 | TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); 22 | TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); 23 | 24 | TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); 25 | TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 ); 26 | 27 | TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); 28 | 29 | TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0); 30 | 31 | TEST_PASSFAIL 32 | 33 | RVTEST_CODE_END 34 | 35 | .data 36 | RVTEST_DATA_BEGIN 37 | 38 | TEST_DATA 39 | 40 | RVTEST_DATA_END 41 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) 17 | TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) 18 | 19 | TEST_PASSFAIL 20 | 21 | RVTEST_CODE_END 22 | 23 | .data 24 | RVTEST_DATA_BEGIN 25 | 26 | TEST_DATA 27 | 28 | tdat: 29 | .word 0xbf800000 30 | .word 0x40000000 31 | .word 0x40400000 32 | .word 0xc0800000 33 | .word 0xdeadbeef 34 | .word 0xcafebabe 35 | .word 0xabad1dea 36 | .word 0x1337d00d 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # move.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions 8 | # and the fcsr work properly. 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64UF 15 | RVTEST_CODE_BEGIN 16 | 17 | TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0) 18 | TEST_CASE(3, a0, 0x34, frsr a0) 19 | TEST_CASE(4, a0, 0x14, frflags a0) 20 | TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2) 21 | TEST_CASE(6, a0, 0x54, frsr a0) 22 | TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4) 23 | TEST_CASE(8, a0, 0x50, frsr a0) 24 | 25 | #define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \ 26 | TEST_CASE(n, a0, 0x12345678 | (-(new_sign) << 31), \ 27 | li a1, ((rs1_sign) << 31) | 0x12345678; \ 28 | li a2, -(rs2_sign); \ 29 | fmv.s.x f1, a1; \ 30 | fmv.s.x f2, a2; \ 31 | insn f0, f1, f2; \ 32 | fmv.x.s a0, f0) 33 | 34 | TEST_FSGNJS(10, fsgnj.s, 0, 0, 0) 35 | TEST_FSGNJS(11, fsgnj.s, 1, 0, 1) 36 | TEST_FSGNJS(12, fsgnj.s, 0, 1, 0) 37 | TEST_FSGNJS(13, fsgnj.s, 1, 1, 1) 38 | 39 | TEST_FSGNJS(20, fsgnjn.s, 1, 0, 0) 40 | TEST_FSGNJS(21, fsgnjn.s, 0, 0, 1) 41 | TEST_FSGNJS(22, fsgnjn.s, 1, 1, 0) 42 | TEST_FSGNJS(23, fsgnjn.s, 0, 1, 1) 43 | 44 | TEST_FSGNJS(30, fsgnjx.s, 0, 0, 0) 45 | TEST_FSGNJS(31, fsgnjx.s, 1, 0, 1) 46 | TEST_FSGNJS(32, fsgnjx.s, 1, 1, 0) 47 | TEST_FSGNJS(33, fsgnjx.s, 0, 1, 1) 48 | 49 | TEST_PASSFAIL 50 | 51 | RVTEST_CODE_END 52 | 53 | .data 54 | RVTEST_DATA_BEGIN 55 | 56 | TEST_DATA 57 | 58 | RVTEST_DATA_END 59 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64uf/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # recoding.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test corner cases of John Hauser's microarchitectural recoding scheme. 8 | # There are twice as many recoded values as IEEE-754 values; some of these 9 | # extras are redundant (e.g. Inf) and others are illegal (subnormals with 10 | # too many bits set). 11 | # 12 | 13 | #include "riscv_test.h" 14 | #include "test_macros.h" 15 | 16 | RVTEST_RV64UF 17 | RVTEST_CODE_BEGIN 18 | 19 | # Make sure infinities with different mantissas compare as equal. 20 | flw f0, minf, a0 21 | flw f1, three, a0 22 | fmul.s f1, f1, f0 23 | TEST_CASE( 2, a0, 1, feq.s a0, f0, f1) 24 | TEST_CASE( 3, a0, 1, fle.s a0, f0, f1) 25 | TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) 26 | 27 | # Likewise, but for zeroes. 28 | fcvt.s.w f0, x0 29 | li a0, 1 30 | fcvt.s.w f1, a0 31 | fmul.s f1, f1, f0 32 | TEST_CASE(5, a0, 1, feq.s a0, f0, f1) 33 | TEST_CASE(6, a0, 1, fle.s a0, f0, f1) 34 | TEST_CASE(7, a0, 0, flt.s a0, f0, f1) 35 | 36 | TEST_PASSFAIL 37 | 38 | RVTEST_CODE_END 39 | 40 | .data 41 | RVTEST_DATA_BEGIN 42 | 43 | minf: .float -Inf 44 | three: .float 3.0 45 | 46 | RVTEST_DATA_END 47 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ui/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ui tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ui_sc_tests = \ 6 | add addi addiw addw \ 7 | and andi \ 8 | auipc \ 9 | beq bge bgeu blt bltu bne \ 10 | simple \ 11 | jal jalr \ 12 | lui \ 13 | or ori \ 14 | sll slli slliw sllw \ 15 | slt slti sltiu sltu \ 16 | sra srai sraiw sraw \ 17 | srl srli srliw srlw \ 18 | sub subw \ 19 | xor xori \ 20 | sw sd \ 21 | # sb sh \ 22 | # fence_i \ 23 | # lb lbu lh lhu lw lwu ld \ 24 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ui/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # auipc.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test auipc instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 10000, \ 17 | .align 3; \ 18 | lla a0, 1f + 10000; \ 19 | jal a1, 1f; \ 20 | 1: sub a0, a0, a1; \ 21 | ) 22 | 23 | TEST_CASE(3, a0, -10000, \ 24 | .align 3; \ 25 | lla a0, 1f - 10000; \ 26 | jal a1, 1f; \ 27 | 1: sub a0, a0, a1; \ 28 | ) 29 | 30 | TEST_PASSFAIL 31 | 32 | RVTEST_CODE_END 33 | 34 | .data 35 | RVTEST_DATA_BEGIN 36 | 37 | TEST_DATA 38 | 39 | RVTEST_DATA_END 40 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ui/fence_i.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fence_i.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test self-modifying code and the fence.i instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | li a3, 111 17 | lh a0, insn 18 | lh a1, insn+2 19 | 20 | # test I$ hit 21 | .align 6 22 | sh a0, 1f, t0 23 | sh a1, 1f+2, t0 24 | fence.i 25 | 26 | 1: addi a3, a3, 222 27 | TEST_CASE( 2, a3, 444, nop ) 28 | 29 | # test prefetcher hit 30 | li a4, 100 31 | 1: addi a4, a4, -1 32 | bnez a4, 1b 33 | 34 | sh a0, 1f, t0 35 | sh a1, 1f+2, t0 36 | fence.i 37 | 38 | .align 6 39 | 1: addi a3, a3, 555 40 | TEST_CASE( 3, a3, 777, nop ) 41 | 42 | TEST_PASSFAIL 43 | 44 | RVTEST_CODE_END 45 | 46 | .data 47 | RVTEST_DATA_BEGIN 48 | 49 | TEST_DATA 50 | 51 | insn: 52 | addi a3, a3, 333 53 | 54 | RVTEST_DATA_END 55 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ui/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jal.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jal instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li ra, 0 23 | 24 | jal x4, target_2 25 | linkaddr_2: 26 | nop 27 | nop 28 | 29 | j fail 30 | 31 | target_2: 32 | la x2, linkaddr_2 33 | bne x2, x4, fail 34 | 35 | #------------------------------------------------------------- 36 | # Test delay slot instructions not executed nor bypassed 37 | #------------------------------------------------------------- 38 | 39 | TEST_CASE( 3, ra, 3, \ 40 | li ra, 1; \ 41 | jal x0, 1f; \ 42 | addi ra, ra, 1; \ 43 | addi ra, ra, 1; \ 44 | addi ra, ra, 1; \ 45 | addi ra, ra, 1; \ 46 | 1: addi ra, ra, 1; \ 47 | addi ra, ra, 1; \ 48 | ) 49 | 50 | TEST_PASSFAIL 51 | 52 | RVTEST_CODE_END 53 | 54 | .data 55 | RVTEST_DATA_BEGIN 56 | 57 | TEST_DATA 58 | 59 | RVTEST_DATA_END 60 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ui/jalr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jalr.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jalr instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li t0, 0 23 | la t1, target_2 24 | 25 | jalr t0, t1, 0 26 | linkaddr_2: 27 | j fail 28 | 29 | target_2: 30 | la t1, linkaddr_2 31 | bne t0, t1, fail 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_JALR_SRC1_BYPASS( 4, 0, jalr ); 38 | TEST_JALR_SRC1_BYPASS( 5, 1, jalr ); 39 | TEST_JALR_SRC1_BYPASS( 6, 2, jalr ); 40 | 41 | #------------------------------------------------------------- 42 | # Test delay slot instructions not executed nor bypassed 43 | #------------------------------------------------------------- 44 | 45 | .option push 46 | .align 2 47 | .option norvc 48 | TEST_CASE( 7, t0, 4, \ 49 | li t0, 1; \ 50 | la t1, 1f; \ 51 | jr t1, -4; \ 52 | addi t0, t0, 1; \ 53 | addi t0, t0, 1; \ 54 | addi t0, t0, 1; \ 55 | addi t0, t0, 1; \ 56 | 1: addi t0, t0, 1; \ 57 | addi t0, t0, 1; \ 58 | ) 59 | .option pop 60 | 61 | TEST_PASSFAIL 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ui/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lui.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lui instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 ); 21 | TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1); 22 | TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20); 23 | TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20); 24 | 25 | TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); 26 | 27 | TEST_PASSFAIL 28 | 29 | RVTEST_CODE_END 30 | 31 | .data 32 | RVTEST_DATA_BEGIN 33 | 34 | TEST_DATA 35 | 36 | RVTEST_DATA_END 37 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64ui/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # simple.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This is the most basic self checking test. If your simulator does not 8 | # pass thiss then there is little chance that it will pass any of the 9 | # more complicated self checking tests. 10 | # 11 | 12 | #include "riscv_test.h" 13 | #include "test_macros.h" 14 | 15 | RVTEST_RV64U 16 | RVTEST_CODE_BEGIN 17 | 18 | RVTEST_PASS 19 | 20 | RVTEST_CODE_END 21 | 22 | .data 23 | RVTEST_DATA_BEGIN 24 | 25 | TEST_DATA 26 | 27 | RVTEST_DATA_END 28 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64um tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64um_sc_tests = \ 6 | div divu divuw divw \ 7 | mul mulh mulhsu mulhu mulw \ 8 | rem remu remuw remw \ 9 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/div.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # div.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test div instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, div, 3, 20, 6 ); 21 | TEST_RR_OP( 3, div, -3, -20, 6 ); 22 | TEST_RR_OP( 4, div, -3, 20, -6 ); 23 | TEST_RR_OP( 5, div, 3, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); 26 | TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, div, -1, -1<<63, 0 ); 29 | TEST_RR_OP( 9, div, -1, 1, 0 ); 30 | TEST_RR_OP(10, div, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/divu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divu, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 ); 22 | TEST_RR_OP( 4, divu, 0, 20, -6 ); 23 | TEST_RR_OP( 5, divu, 0, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 ); 26 | TEST_RR_OP( 7, divu, 0, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, divu, -1, -1<<63, 0 ); 29 | TEST_RR_OP( 9, divu, -1, 1, 0 ); 30 | TEST_RR_OP(10, divu, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/divuw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divuw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divuw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divuw, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); 22 | TEST_RR_OP( 4, divuw, 0, 20, -6 ); 23 | TEST_RR_OP( 5, divuw, 0, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, divuw, -1, 1, 0 ); 30 | TEST_RR_OP(10, divuw, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/divw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divw, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divw, -3, -20, 6 ); 22 | TEST_RR_OP( 4, divw, -3, 20, -6 ); 23 | TEST_RR_OP( 5, divw, 3, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, divw, -1, 1, 0 ); 30 | TEST_RR_OP(10, divw, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/rem.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # rem.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test rem instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, rem, 2, 20, 6 ); 21 | TEST_RR_OP( 3, rem, -2, -20, 6 ); 22 | TEST_RR_OP( 4, rem, 2, 20, -6 ); 23 | TEST_RR_OP( 5, rem, -2, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); 26 | TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); 29 | TEST_RR_OP( 9, rem, 1, 1, 0 ); 30 | TEST_RR_OP(10, rem, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/remu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remu, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remu, 2, -20, 6 ); 22 | TEST_RR_OP( 4, remu, 20, 20, -6 ); 23 | TEST_RR_OP( 5, remu, -20, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); 26 | TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); 29 | TEST_RR_OP( 9, remu, 1, 1, 0 ); 30 | TEST_RR_OP(10, remu, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/remuw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remuw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remuw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remuw, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remuw, 2, -20, 6 ); 22 | TEST_RR_OP( 4, remuw, 20, 20, -6 ); 23 | TEST_RR_OP( 5, remuw, -20, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remuw, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, remuw, 1, 1, 0 ); 30 | TEST_RR_OP(10, remuw, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /test/riscv-tests/isa/rv64um/remw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remw, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remw, -2, -20, 6 ); 22 | TEST_RR_OP( 4, remw, 2, 20, -6 ); 23 | TEST_RR_OP( 5, remw, -2, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remw, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, remw, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, remw, 1, 1, 0 ); 30 | TEST_RR_OP(10, remw, 0, 0, 0 ); 31 | TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 ); 32 | 33 | TEST_PASSFAIL 34 | 35 | RVTEST_CODE_END 36 | 37 | .data 38 | RVTEST_DATA_BEGIN 39 | 40 | TEST_DATA 41 | 42 | RVTEST_DATA_END 43 | -------------------------------------------------------------------------------- /test/riscv-tests/riscv-tests.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | serval/lib/unittest 5 | (prefix-in core: serval/lib/core) 6 | serval/riscv/interp 7 | serval/riscv/objdump 8 | serval/riscv/base) 9 | 10 | (define (run-test testfile) 11 | ; (define globalsfile (string->path (string-replace (path->string testfile) ".asm.rkt" ".globals.rkt"))) 12 | ; (define mapfile (string->path (string-replace (path->string testfile) ".asm.rkt" ".map.rkt"))) 13 | (define instrs (dynamic-require testfile 'instructions)) 14 | (define arch (dynamic-require testfile 'architecture)) 15 | ; (define symbols (dynamic-require mapfile 'symbols)) 16 | ; (define globals (dynamic-require globalsfile 'globals)) 17 | 18 | (define bits (case arch [(riscv:rv64) 64] [(riscv:rv32) 32])) 19 | 20 | (parameterize 21 | ([XLEN bits] 22 | [core:target-pointer-bitwidth bits]) 23 | 24 | (define cpu (init-cpu null null (lambda a (core:make-flat-memmgr)))) 25 | 26 | (define (handle-failure e) 27 | (displayln e) 28 | (define s (format "FAILURE --> Test ~e failed in ~e\n" (bitvector->integer (gpr-ref cpu 'x21)) testfile)) 29 | (assert #f s)) 30 | 31 | (with-handlers 32 | ([exn:fail? handle-failure]) 33 | (interpret-objdump-program cpu instrs)) 34 | 35 | (printf "SUCCESS --> ~e\n" testfile))) 36 | 37 | (define riscv-tests 38 | (test-suite+ 39 | "Add test" 40 | (for ([filename (current-command-line-arguments)]) 41 | (displayln filename) 42 | (test-case+ filename (run-test (build-path "../" filename)))) 43 | )) 44 | 45 | (module+ test 46 | (time (run-tests riscv-tests))) 47 | -------------------------------------------------------------------------------- /test/riscv-tests/riscv_test.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #define START_NOP \ 4 | .global _start; \ 5 | _start: \ 6 | li x1, 0; \ 7 | li x2, 0; \ 8 | li x3, 0; \ 9 | li x4, 0; \ 10 | li x5, 0; \ 11 | li x6, 0; \ 12 | li x7, 0; \ 13 | li x8, 0; \ 14 | li x9, 0; \ 15 | li x10, 0; \ 16 | li x11, 0; \ 17 | li x12, 0; \ 18 | li x13, 0; \ 19 | li x14, 0; \ 20 | li x15, 0; \ 21 | li x16, 0; \ 22 | li x17, 0; \ 23 | li x18, 0; \ 24 | li x19, 0; \ 25 | li x20, 0; \ 26 | li x21, 0; \ 27 | li x22, 0; \ 28 | li x23, 0; \ 29 | li x24, 0; \ 30 | li x25, 0; \ 31 | li x26, 0; \ 32 | li x27, 0; \ 33 | li x28, 0; \ 34 | li x29, 0; \ 35 | li x30, 0; \ 36 | li x31, 0; \ 37 | 38 | #define DROP_TEST \ 39 | .globl _start; \ 40 | _start: \ 41 | mret; \ 42 | 43 | #define RVTEST_RV32U START_NOP 44 | #define RVTEST_RV32UF DROP_TEST 45 | #define RVTEST_RV32M DROP_TEST 46 | 47 | #define RVTEST_RV64U START_NOP 48 | #define RVTEST_RV64UF DROP_TEST 49 | #define RVTEST_RV64M DROP_TEST 50 | 51 | #define RVTEST_CODE_BEGIN .text 52 | #define RVTEST_CODE_END 53 | 54 | #define RVTEST_DATA_BEGIN 55 | #define RVTEST_DATA_END 56 | 57 | #define RVTEST_FAIL unimp 58 | #define RVTEST_PASS mret 59 | 60 | #define TESTNUM x21 61 | -------------------------------------------------------------------------------- /test/riscv.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette/safe 2 | 3 | (require 4 | serval/lib/unittest 5 | serval/riscv/interp 6 | serval/riscv/base 7 | serval/riscv/interp) 8 | 9 | (define (check-jalr-clears-least-bit) 10 | (define cpu (init-cpu)) 11 | (gpr-set! cpu 'a0 (bv #xffff (XLEN))) 12 | (define i (jalr (bv 0 12) (gpr->idx 'a0) (bv 0 5))) 13 | (interpret-insn cpu i) 14 | (check-equal? (cpu-pc cpu) (bv #xfffe (XLEN)))) 15 | 16 | (define riscv-tests 17 | (test-suite+ 18 | "Tests for RISC-V behavior" 19 | (test-case+ "Check jalr clears least bit" (check-jalr-clears-least-bit)))) 20 | 21 | (module+ test 22 | (time (run-tests riscv-tests))) 23 | -------------------------------------------------------------------------------- /test/riscv/test.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require serval/riscv/base 4 | serval/riscv/interp2 5 | serval/riscv/decode) 6 | 7 | (define-symbolic rs1 rs2 rd (bitvector 5)) 8 | 9 | (displayln (decode (concat (bv 0 7) rs2 rs1 (bv 0 3) rd (bv #b0110011 7)))) -------------------------------------------------------------------------------- /test/test-flat.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require (prefix-in core: serval/lib/core)) 4 | 5 | (core:target-pointer-bitwidth 64) 6 | 7 | (define (check-read-write-bv64) 8 | 9 | (define memmgr (core:make-flat-memmgr)) 10 | (define-symbolic* addr (bitvector 64)) 11 | (define-symbolic* off (bitvector 64)) 12 | (define-symbolic* data (bitvector 64)) 13 | 14 | (core:memmgr-store! memmgr addr off data (bv 8 64)) 15 | 16 | (define readdata (core:memmgr-load memmgr addr off (bv 8 64))) 17 | 18 | (core:check-unsat? (verify (assert (bveq data readdata))))) 19 | 20 | (define flat-memory-tests 21 | (core:test-suite+ 22 | "Tests for flat memory model" 23 | (core:test-case+ "Check r/w bv64" (check-read-write-bv64)) 24 | )) 25 | 26 | (module+ test 27 | (time (core:run-tests flat-memory-tests))) -------------------------------------------------------------------------------- /test/udiv.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | uint32_t udiv(uint32_t x, uint32_t y) 4 | { 5 | if (y != 0) 6 | return x / y; 7 | return 0; 8 | } 9 | 10 | __attribute__((noinline)) 11 | static uint32_t foo(uint32_t x, uint32_t y) 12 | { 13 | return x / y; 14 | } 15 | 16 | uint32_t udiv_buggy(uint32_t x, uint32_t y) 17 | { 18 | return foo(x, y); 19 | } 20 | -------------------------------------------------------------------------------- /test/x86/adc.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "ADC" 8 | adc-r/m32-imm8 9 | adc-r/m64-imm8 10 | adc-r/m32-r32 11 | adc-r/m64-r64 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/x86/add.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "ADD" 8 | add-eax-imm32 9 | add-rax-imm32 10 | add-r/m32-imm32 11 | add-r/m64-imm32 12 | add-r/m32-imm8 13 | add-r/m64-imm8 14 | add-r/m32-r32 15 | add-r/m64-r64 16 | )) 17 | 18 | (module+ test 19 | (time (run-tests tests))) 20 | -------------------------------------------------------------------------------- /test/x86/and.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "AND" 8 | and-eax-imm32 9 | and-rax-imm32 10 | and-r/m32-imm32 11 | and-r/m64-imm32 12 | and-r/m32-imm8 13 | and-r/m64-imm8 14 | and-r/m32-r32 15 | and-r/m64-r64 16 | and-r32-r/m32 17 | and-r64-r/m64 18 | )) 19 | 20 | (module+ test 21 | (time (run-tests tests))) 22 | -------------------------------------------------------------------------------- /test/x86/bswap.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "BSWAP" 8 | bswap-r32 9 | bswap-r64 10 | )) 11 | 12 | (module+ test 13 | (time (run-tests tests))) 14 | -------------------------------------------------------------------------------- /test/x86/cmp.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "CMP" 8 | cmp-eax-imm32 9 | cmp-rax-imm32 10 | cmp-r/m32-imm32 11 | cmp-r/m64-imm32 12 | cmp-r/m32-imm8 13 | cmp-r/m64-imm8 14 | cmp-r/m32-r32 15 | cmp-r/m64-r64 16 | cmp-r32-r/m32 17 | cmp-r64-r/m64 18 | )) 19 | 20 | (module+ test 21 | (time (run-tests tests))) 22 | -------------------------------------------------------------------------------- /test/x86/div.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "DIV" 8 | div-r/m32 9 | div-r/m64 10 | )) 11 | 12 | (module+ test 13 | (time (run-tests tests))) 14 | -------------------------------------------------------------------------------- /test/x86/jcc.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "Jcc" 8 | ja-rel8 jae-rel8 9 | jb-rel8 jbe-rel8 10 | je-rel8 11 | jg-rel8 jge-rel8 12 | jl-rel8 jle-rel8 13 | jne-rel8 14 | ja-rel32 jae-rel32 15 | jb-rel32 jbe-rel32 16 | je-rel32 17 | jg-rel32 jge-rel32 18 | jl-rel32 jle-rel32 19 | jne-rel32 20 | )) 21 | 22 | (module+ test 23 | (time (run-tests tests))) 24 | -------------------------------------------------------------------------------- /test/x86/jmp.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "JMP" 8 | jmp-rel8 9 | jmp-rel32 10 | jmp-r/m64-no-rex 11 | )) 12 | 13 | (module+ test 14 | (time (run-tests tests))) 15 | -------------------------------------------------------------------------------- /test/x86/mov.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "MOV" 8 | mov-r/m32-imm32 9 | mov-r/m32-r32 10 | mov-r/m64-imm32 11 | mov-r/m64-r64 12 | mov-r8-imm8 13 | mov-r8*-imm8 14 | mov-r32-imm32 15 | mov-r32-r/m32 16 | mov-r64-imm64 17 | )) 18 | 19 | (module+ test 20 | (time (run-tests tests))) 21 | -------------------------------------------------------------------------------- /test/x86/movzx.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "MOVZX" 8 | movzx-r32-r/m8 9 | movzx-r64-r/m8 10 | movzx-r32-r/m16 11 | movzx-r64-r/m16 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/x86/mul.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "MUL" 8 | mul-r/m32 9 | mul-r/m64 10 | )) 11 | 12 | (module+ test 13 | (time (run-tests tests))) 14 | -------------------------------------------------------------------------------- /test/x86/neg.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "NEG" 8 | neg-r/m32 9 | neg-r/m64)) 10 | 11 | (module+ test 12 | (time (run-tests tests))) 13 | -------------------------------------------------------------------------------- /test/x86/or.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "OR" 8 | or-eax-imm32 9 | or-rax-imm32 10 | or-r/m32-imm32 11 | or-r/m64-imm32 12 | or-r/m32-imm8 13 | or-r/m64-imm8 14 | or-r/m32-r32 15 | or-r/m64-r64 16 | )) 17 | 18 | (module+ test 19 | (time (run-tests tests))) 20 | -------------------------------------------------------------------------------- /test/x86/rotate.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "ROL/ROR" 8 | rol-r/m16-1 rol-r/m32-1 rol-r/m64-1 9 | ror-r/m16-1 ror-r/m32-1 ror-r/m64-1 10 | rol-r/m16-cl rol-r/m32-cl rol-r/m64-cl 11 | ror-r/m16-cl ror-r/m32-cl ror-r/m64-cl 12 | rol-r/m16-imm8 rol-r/m32-imm8 rol-r/m64-imm8 13 | ror-r/m16-imm8 ror-r/m32-imm8 ror-r/m64-imm8 14 | )) 15 | 16 | (module+ test 17 | (time (run-tests tests))) 18 | -------------------------------------------------------------------------------- /test/x86/sbb.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "SBB" 8 | sbb-r/m32-imm8 9 | sbb-r/m64-imm8 10 | sbb-r/m32-r32 11 | sbb-r/m64-r64 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/x86/shift.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "SAR/SHL/SHR" 8 | sar-r/m32-1 sar-r/m64-1 9 | shl-r/m32-1 shl-r/m64-1 10 | shr-r/m32-1 shr-r/m64-1 11 | sar-r/m32-cl sar-r/m64-cl 12 | shl-r/m32-cl shl-r/m64-cl 13 | shr-r/m32-cl shr-r/m64-cl 14 | sar-r/m32-imm8 sar-r/m64-imm8 15 | shl-r/m32-imm8 shl-r/m64-imm8 16 | shr-r/m32-imm8 shr-r/m64-imm8 17 | )) 18 | 19 | (module+ test 20 | (time (run-tests tests))) 21 | -------------------------------------------------------------------------------- /test/x86/shld.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "SHLD" 8 | shld-r/m32-r32-imm8 9 | shld-r/m64-r64-imm8 10 | shld-r/m32-r32-cl 11 | shld-r/m64-r64-cl 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/x86/shrd.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "SHRD" 8 | shrd-r/m32-r32-imm8 9 | shrd-r/m64-r64-imm8 10 | shrd-r/m32-r32-cl 11 | shrd-r/m64-r64-cl 12 | )) 13 | 14 | (module+ test 15 | (time (run-tests tests))) 16 | -------------------------------------------------------------------------------- /test/x86/sub.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "SUB" 8 | sub-eax-imm32 9 | sub-rax-imm32 10 | sub-r/m32-imm32 11 | sub-r/m64-imm32 12 | sub-r/m32-imm8 13 | sub-r/m64-imm8 14 | sub-r/m32-r32 15 | sub-r/m64-r64 16 | sub-r32-r/m32 17 | sub-r64-r/m64 18 | )) 19 | 20 | (module+ test 21 | (time (run-tests tests))) 22 | -------------------------------------------------------------------------------- /test/x86/test.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "TEST" 8 | test-eax-imm32 9 | test-rax-imm32 10 | test-r/m32-imm32 11 | test-r/m64-imm32 12 | test-r/m32-r32 13 | test-r/m64-r64 14 | )) 15 | 16 | (module+ test 17 | (time (run-tests tests))) 18 | -------------------------------------------------------------------------------- /test/x86/xchg.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "XCHG" 8 | xchg-r/m32-r32 9 | xchg-r/m64-r64 10 | )) 11 | 12 | (module+ test 13 | (time (run-tests tests))) 14 | -------------------------------------------------------------------------------- /test/x86/xor.rkt: -------------------------------------------------------------------------------- 1 | #lang racket/base 2 | 3 | (require 4 | "lib.rkt") 5 | 6 | (define tests 7 | (x86-suite "XOR" 8 | xor-eax-imm32 9 | xor-rax-imm32 10 | xor-r/m32-imm32 11 | xor-r/m64-imm32 12 | xor-r/m32-imm8 13 | xor-r/m64-imm8 14 | xor-r/m32-r32 15 | xor-r/m64-r64 16 | xor-r32-r/m32 17 | xor-r64-r/m64 18 | )) 19 | 20 | (module+ test 21 | (time (run-tests tests))) 22 | --------------------------------------------------------------------------------