├── .github └── workflows │ └── build.yml ├── .gitignore ├── Codecov.png ├── LICENSE ├── Makefile ├── README.md ├── TravisCI.png ├── Whitespace.png ├── input.vc ├── sim_main.cpp ├── top.v └── verilator_56x48-min.png /.github/workflows/build.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/.github/workflows/build.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/.gitignore -------------------------------------------------------------------------------- /Codecov.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/Codecov.png -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/LICENSE -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/README.md -------------------------------------------------------------------------------- /TravisCI.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/TravisCI.png -------------------------------------------------------------------------------- /Whitespace.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/Whitespace.png -------------------------------------------------------------------------------- /input.vc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/input.vc -------------------------------------------------------------------------------- /sim_main.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/sim_main.cpp -------------------------------------------------------------------------------- /top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/top.v -------------------------------------------------------------------------------- /verilator_56x48-min.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/verilator/example-systemverilog/HEAD/verilator_56x48-min.png --------------------------------------------------------------------------------