├── .clang-format ├── .gitattributes ├── .gitignore ├── COPYING ├── Changes ├── EditFiles.pm ├── Getopt.pm ├── Language.pm ├── MANIFEST ├── MANIFEST.SKIP ├── META.yml ├── Makefile.PL ├── Netlist.pm ├── Netlist ├── Cell.pm ├── ContAssign.pm ├── Defparam.pm ├── File.pm ├── Interface.pm ├── Logger.pm ├── ModPort.pm ├── Module.pm ├── Net.pm ├── Pin.pm ├── PinSelection.pm ├── Port.pm └── Subclass.pm ├── Parser ├── .gitignore ├── Makefile.PL ├── Parser.pm ├── Parser.xs ├── SigParser.pm ├── VAst.cpp ├── VAst.h ├── VParse.cpp ├── VParse.h ├── VParseBison.y ├── VParseGrammar.h ├── VParseLex.h ├── VParseLex.l ├── VSymTable.cpp ├── VSymTable.h ├── bisonpre ├── callbackgen └── typemap ├── Preproc ├── .gitignore ├── Makefile.PL ├── Preproc.pm ├── Preproc.xs ├── VFileLine.cpp ├── VFileLine.h ├── VPreLex.h ├── VPreLex.l ├── VPreProc.cpp ├── VPreProc.h ├── flexfix ├── toolhash ├── typemap └── xsubppfix ├── README.pod ├── Std.pm ├── t ├── 00_pod.t ├── 01_manifest.t ├── 02_help.t ├── 03_spaces.t ├── 04_critic.t ├── 05_yaml.t ├── 10_keywords.t ├── 12_splitbus.t ├── 14_numbers.t ├── 16_std.t ├── 20_getopt.opt ├── 20_getopt.t ├── 30_preproc.out ├── 30_preproc.t ├── 30_preproc_nows.out ├── 30_preproc_on.out ├── 30_preproc_sub.out ├── 30_preproc_syn.out ├── 32_noinc.t ├── 32_noinc.v ├── 33_gzip.t ├── 34_parser.out ├── 34_parser.t ├── 35_sigparser.out ├── 35_sigparser.t ├── 35_sigparser_ps.out ├── 36_sigmany.t ├── 40_netlist.t ├── 41_example.out ├── 41_example.t ├── 42_dumpcheck.t ├── 42_dumpcheck_1.out ├── 42_dumpcheck_1_ps.out ├── 42_dumpcheck_1v.out ├── 42_dumpcheck_1v_ps.out ├── 42_dumpcheck_2.out ├── 42_dumpcheck_2e.out ├── 42_dumpcheck_2v.out ├── 42_dumpcheck_sv.out ├── 42_dumpcheck_v2k.out ├── 42_dumpcheck_v2kv.out ├── 43_storable.t ├── 44_create.out ├── 44_create.t ├── 46_link.t ├── 48_leak.t ├── 49_largeish.t ├── 50_vrename.out ├── 50_vrename.t ├── 51_vrename_kwd.t ├── 51_vrename_kwd.v ├── 51_vrename_kwd_chg.out ├── 51_vrename_kwd_chg2.out ├── 51_vrename_kwd_chg2.vrename ├── 51_vrename_kwd_list.out ├── 56_editfiles.t ├── 56_editfiles.v ├── 56_editfiles_a.out ├── 56_editfiles_b.out ├── 56_editfiles_edit.out ├── 58_vsplitmodule.t ├── 60_vpassert.out ├── 60_vpassert.t ├── 80_vppreproc.t ├── 80_vppreproc_cmped.out ├── 80_vppreproc_defines.out ├── 80_vppreproc_none.out ├── 80_vppreproc_rel_file.out ├── 80_vppreproc_simple.out ├── 85_vhier.t ├── 85_vhier_cells.out ├── 85_vhier_forest.out ├── 85_vhier_includes.out ├── 85_vhier_inpfiles.out ├── 85_vhier_modfiles.out ├── 85_vhier_resolvefiles.out ├── 85_vhier_skiplist.dat ├── 85_vhier_skiplist.out ├── 85_vhier_topmodule.out ├── 85_vhier_xml.out ├── 86_vhier_tick.t ├── 87_vhier_unicode.t └── test_utils.pl ├── verilog ├── example.v ├── inc1.v ├── inc2.v ├── inc_def09.v ├── inc_ifdef.v ├── inc_nonl.v ├── parser_bugs.v ├── parser_sv.v ├── parser_sv09.v ├── parser_sv17.v ├── parser_vectors.v ├── pinorder.v ├── pli.v ├── t_80_bar │ ├── bar.f │ └── bar.v ├── t_80_foo.f ├── t_80_foo.v ├── t_86_vhier_tick.v ├── t_86_vhier_tick_sub.v ├── t_preproc_inc3.vh ├── t_preproc_inc4.vh ├── test.v ├── test.vrename ├── v_comments.v ├── v_gate.v ├── v_hier_inc.vh ├── v_hier_noport.v ├── v_hier_sub.v ├── v_hier_subprim.v ├── v_hier_subsub.v ├── v_hier_top.v ├── v_hier_top2.v ├── v_recursive.v ├── v_sv_intf.v ├── v_sv_mod.v ├── v_sv_pgm.v ├── v_sv_pkg.v └── v_v2k.v ├── vhier ├── vpassert ├── vppreproc ├── vrename └── vsplitmodule /.clang-format: -------------------------------------------------------------------------------- 1 | --- 2 | Language: Cpp 3 | # BasedOnStyle: LLVM 4 | AccessModifierOffset: -4 5 | AlignAfterOpenBracket: Align 6 | AlignConsecutiveAssignments: false 7 | AlignConsecutiveDeclarations: false 8 | AlignEscapedNewlines: DontAlign 9 | AlignOperands: true 10 | AlignTrailingComments: false 11 | AllowAllParametersOfDeclarationOnNextLine: true 12 | AllowShortBlocksOnASingleLine: true 13 | AllowShortCaseLabelsOnASingleLine: true 14 | AllowShortFunctionsOnASingleLine: All 15 | AllowShortIfStatementsOnASingleLine: true 16 | AllowShortLoopsOnASingleLine: true 17 | AlwaysBreakAfterDefinitionReturnType: None 18 | AlwaysBreakAfterReturnType: None 19 | AlwaysBreakBeforeMultilineStrings: false 20 | AlwaysBreakTemplateDeclarations: false 21 | BinPackArguments: true 22 | BinPackParameters: true 23 | BraceWrapping: 24 | AfterClass: false 25 | AfterControlStatement: false 26 | AfterEnum: false 27 | AfterFunction: false 28 | AfterNamespace: false 29 | AfterObjCDeclaration: false 30 | AfterStruct: false 31 | AfterUnion: false 32 | AfterExternBlock: false 33 | BeforeCatch: false 34 | BeforeElse: false 35 | IndentBraces: false 36 | SplitEmptyFunction: true 37 | SplitEmptyRecord: true 38 | SplitEmptyNamespace: true 39 | BreakBeforeBinaryOperators: All 40 | BreakBeforeBraces: Attach 41 | BreakBeforeInheritanceComma: false 42 | BreakBeforeTernaryOperators: true 43 | BreakConstructorInitializersBeforeComma: false 44 | BreakConstructorInitializers: BeforeComma 45 | BreakAfterJavaFieldAnnotations: false 46 | BreakStringLiterals: true 47 | ColumnLimit: 99 48 | CommentPragmas: '^ IWYU pragma:' 49 | CompactNamespaces: false 50 | ConstructorInitializerAllOnOneLineOrOnePerLine: false 51 | ConstructorInitializerIndentWidth: 4 52 | ContinuationIndentWidth: 4 53 | Cpp11BracedListStyle: true 54 | DerivePointerAlignment: false 55 | DisableFormat: false 56 | ExperimentalAutoDetectBinPacking: false 57 | FixNamespaceComments: true 58 | ForEachMacros: 59 | - foreach 60 | - Q_FOREACH 61 | - BOOST_FOREACH 62 | IncludeBlocks: Preserve 63 | IncludeCategories: 64 | - Regex: '^"(llvm|llvm-c|clang|clang-c)/' 65 | Priority: 2 66 | - Regex: '^(<|"(gtest|gmock|isl|json)/)' 67 | Priority: 3 68 | - Regex: '.*' 69 | Priority: 1 70 | IncludeIsMainRegex: '(Test)?$' 71 | IndentCaseLabels: false 72 | IndentPPDirectives: None 73 | IndentWidth: 4 74 | IndentWrappedFunctionNames: false 75 | JavaScriptQuotes: Leave 76 | JavaScriptWrapImports: true 77 | KeepEmptyLinesAtTheStartOfBlocks: true 78 | MacroBlockBegin: '' 79 | MacroBlockEnd: '' 80 | MaxEmptyLinesToKeep: 1 81 | NamespaceIndentation: None 82 | ObjCBlockIndentWidth: 2 83 | ObjCSpaceAfterProperty: false 84 | ObjCSpaceBeforeProtocolList: true 85 | PenaltyBreakAssignment: 2 86 | PenaltyBreakBeforeFirstCallParameter: 19 87 | PenaltyBreakComment: 300 88 | PenaltyBreakFirstLessLess: 120 89 | PenaltyBreakString: 1000 90 | PenaltyExcessCharacter: 1000000 91 | PenaltyReturnTypeOnItsOwnLine: 60 92 | PointerAlignment: Left 93 | ReflowComments: true 94 | SortIncludes: false 95 | SortUsingDeclarations: true 96 | SpaceAfterCStyleCast: false 97 | SpaceAfterTemplateKeyword: true 98 | SpaceBeforeAssignmentOperators: true 99 | SpaceBeforeParens: ControlStatements 100 | SpaceInEmptyParentheses: false 101 | SpacesBeforeTrailingComments: 2 102 | SpacesInAngles: false 103 | SpacesInContainerLiterals: true 104 | SpacesInCStyleCastParentheses: false 105 | SpacesInParentheses: false 106 | SpacesInSquareBrackets: false 107 | Standard: Cpp03 108 | TabWidth: 8 109 | UseTab: Never 110 | ... 111 | 112 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.v linguist-language=SystemVerilog 2 | *.vh linguist-language=SystemVerilog 3 | *.sv linguist-language=SystemVerilog 4 | *.svh linguist-language=SystemVerilog 5 | nodist linguist-detectable=false 6 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | README 2 | blib 3 | Makefile 4 | pm_to_blib 5 | *.c 6 | *.bs 7 | *.old 8 | *.tmp 9 | .vpassert 10 | .vpm 11 | .git 12 | .svn 13 | simv 14 | signals.vrename 15 | test_dir 16 | MYMETA.* 17 | nodist 18 | -------------------------------------------------------------------------------- /MANIFEST: -------------------------------------------------------------------------------- 1 | .clang-format 2 | .gitignore 3 | Changes 4 | COPYING 5 | EditFiles.pm 6 | Getopt.pm 7 | Language.pm 8 | Makefile.PL 9 | MANIFEST This list of files 10 | MANIFEST.SKIP 11 | META.yml 12 | Netlist.pm 13 | Netlist/Cell.pm 14 | Netlist/ContAssign.pm 15 | Netlist/Defparam.pm 16 | Netlist/File.pm 17 | Netlist/Interface.pm 18 | Netlist/Logger.pm 19 | Netlist/ModPort.pm 20 | Netlist/Module.pm 21 | Netlist/Net.pm 22 | Netlist/Pin.pm 23 | Netlist/PinSelection.pm 24 | Netlist/Port.pm 25 | Netlist/Subclass.pm 26 | Parser/.gitignore 27 | Parser/bisonpre 28 | Parser/callbackgen 29 | Parser/gen/bisonpre-0 30 | Parser/gen/bisonpre-1 31 | Parser/gen/bisonpre-2 32 | Parser/gen/bisonpre-s 33 | Parser/gen/flex-0 34 | Parser/gen/flex-1 35 | Parser/Makefile.PL 36 | Parser/Parser.pm 37 | Parser/Parser.xs 38 | Parser/SigParser.pm 39 | Parser/typemap 40 | Parser/VAst.cpp 41 | Parser/VAst.h 42 | Parser/VParse.cpp 43 | Parser/VParse.h 44 | Parser/VParseBison.y 45 | Parser/VParseGrammar.h 46 | Parser/VParseLex.h 47 | Parser/VParseLex.l 48 | Parser/VSymTable.cpp 49 | Parser/VSymTable.h 50 | Preproc/.gitignore 51 | Preproc/flexfix 52 | Preproc/gen/flex-0 53 | Preproc/gen/flex-1 54 | Preproc/Makefile.PL 55 | Preproc/Preproc.pm 56 | Preproc/Preproc.xs 57 | Preproc/toolhash 58 | Preproc/typemap 59 | Preproc/VFileLine.cpp 60 | Preproc/VFileLine.h 61 | Preproc/VPreLex.h 62 | Preproc/VPreLex.l 63 | Preproc/VPreProc.cpp 64 | Preproc/VPreProc.h 65 | Preproc/xsubppfix 66 | README 67 | README.pod 68 | Std.pm 69 | t/00_pod.t 70 | t/01_manifest.t 71 | t/02_help.t 72 | t/03_spaces.t 73 | t/04_critic.t 74 | t/05_yaml.t 75 | t/10_keywords.t 76 | t/12_splitbus.t 77 | t/14_numbers.t 78 | t/16_std.t 79 | t/20_getopt.opt 80 | t/20_getopt.t 81 | t/30_preproc.out 82 | t/30_preproc.t 83 | t/30_preproc_nows.out 84 | t/30_preproc_on.out 85 | t/30_preproc_sub.out 86 | t/30_preproc_syn.out 87 | t/32_noinc.t 88 | t/32_noinc.v 89 | t/33_gzip.t 90 | t/34_parser.out 91 | t/34_parser.t 92 | t/35_sigparser.out 93 | t/35_sigparser.t 94 | t/35_sigparser_ps.out 95 | t/36_sigmany.t 96 | t/40_netlist.t 97 | t/41_example.out 98 | t/41_example.t 99 | t/42_dumpcheck.t 100 | t/42_dumpcheck_1.out 101 | t/42_dumpcheck_1_ps.out 102 | t/42_dumpcheck_1v.out 103 | t/42_dumpcheck_1v_ps.out 104 | t/42_dumpcheck_2.out 105 | t/42_dumpcheck_2e.out 106 | t/42_dumpcheck_2v.out 107 | t/42_dumpcheck_sv.out 108 | t/42_dumpcheck_v2k.out 109 | t/42_dumpcheck_v2kv.out 110 | t/43_storable.t 111 | t/44_create.out 112 | t/44_create.t 113 | t/46_link.t 114 | t/48_leak.t 115 | t/49_largeish.t 116 | t/50_vrename.out 117 | t/50_vrename.t 118 | t/51_vrename_kwd.t 119 | t/51_vrename_kwd.v 120 | t/51_vrename_kwd_chg.out 121 | t/51_vrename_kwd_chg2.out 122 | t/51_vrename_kwd_chg2.vrename 123 | t/51_vrename_kwd_list.out 124 | t/56_editfiles.t 125 | t/56_editfiles.v 126 | t/56_editfiles_a.out 127 | t/56_editfiles_b.out 128 | t/56_editfiles_edit.out 129 | t/58_vsplitmodule.t 130 | t/60_vpassert.out 131 | t/60_vpassert.t 132 | t/80_vppreproc.t 133 | t/80_vppreproc_cmped.out 134 | t/80_vppreproc_defines.out 135 | t/80_vppreproc_none.out 136 | t/80_vppreproc_rel_file.out 137 | t/80_vppreproc_simple.out 138 | t/85_vhier.t 139 | t/85_vhier_cells.out 140 | t/85_vhier_forest.out 141 | t/85_vhier_includes.out 142 | t/85_vhier_inpfiles.out 143 | t/85_vhier_modfiles.out 144 | t/85_vhier_resolvefiles.out 145 | t/85_vhier_skiplist.dat 146 | t/85_vhier_skiplist.out 147 | t/85_vhier_topmodule.out 148 | t/85_vhier_xml.out 149 | t/86_vhier_tick.t 150 | t/87_vhier_unicode.t 151 | t/test_utils.pl 152 | verilog/example.v 153 | verilog/inc1.v 154 | verilog/inc2.v 155 | verilog/inc_def09.v 156 | verilog/inc_ifdef.v 157 | verilog/inc_nonl.v 158 | verilog/parser_bugs.v 159 | verilog/parser_sv.v 160 | verilog/parser_sv09.v 161 | verilog/parser_sv17.v 162 | verilog/parser_vectors.v 163 | verilog/pinorder.v 164 | verilog/pli.v 165 | verilog/t_80_bar/bar.f 166 | verilog/t_80_bar/bar.v 167 | verilog/t_80_foo.f 168 | verilog/t_80_foo.v 169 | verilog/t_86_vhier_tick.v 170 | verilog/t_86_vhier_tick_sub.v 171 | verilog/t_preproc_inc3.vh 172 | verilog/t_preproc_inc4.vh 173 | verilog/test.v 174 | verilog/test.vrename 175 | verilog/v_comments.v 176 | verilog/v_gate.v 177 | verilog/v_hier_inc.vh 178 | verilog/v_hier_noport.v 179 | verilog/v_hier_sub.v 180 | verilog/v_hier_subprim.v 181 | verilog/v_hier_subsub.v 182 | verilog/v_hier_top.v 183 | verilog/v_hier_top2.v 184 | verilog/v_recursive.v 185 | verilog/v_sv_intf.v 186 | verilog/v_sv_mod.v 187 | verilog/v_sv_pgm.v 188 | verilog/v_sv_pkg.v 189 | verilog/v_v2k.v 190 | vhier 191 | vpassert 192 | vppreproc 193 | vrename 194 | vsplitmodule 195 | -------------------------------------------------------------------------------- /MANIFEST.SKIP: -------------------------------------------------------------------------------- 1 | ^CVS/ 2 | /CVS/ 3 | ^.git/ 4 | ,v$ 5 | \.(bak|old|new)/ 6 | \.(bak|old|new)$ 7 | \bMakefile$ 8 | ^INSTALL$ 9 | \.wpsin$ 10 | \.texi$ 11 | \.tar\. 12 | \.bs$ 13 | \.vpassert/.* 14 | \.o$ 15 | \.def$ 16 | \.dll$ 17 | \.exp$ 18 | \.gitattributes$ 19 | \.tmp$ 20 | \.vcs.*$ 21 | \.pre\..*$ 22 | _pretmp\..*$ 23 | VPreLex\.cpp$ 24 | simv 25 | .*\.tar\.gz 26 | \bblib\b 27 | nodist/.* 28 | pm_to_blib$ 29 | Parser/Parser.c 30 | Parser/VParseBison.*\.cpp 31 | Parser/VParseBison.*\.h 32 | Parser/VParseBison.*\.tab.c 33 | Parser/VParseBison.*\.output 34 | Parser/VParseLex.cpp 35 | Parser/VParseLex_pretmp.cpp 36 | Parser/.*_callbackgen\..* 37 | Parser/.*_cleaned\..* 38 | Preproc/Preproc.c 39 | Preproc/VPreLex_pretmp.cpp 40 | Preproc/.*_cleaned\..* 41 | signals.vrename 42 | test_dir 43 | \.svn/ 44 | ^(.*/)?MYMETA\..*$ 45 | -------------------------------------------------------------------------------- /META.yml: -------------------------------------------------------------------------------- 1 | --- #YAML:1.0 2 | name: Verilog-Perl 3 | version: 3.483 4 | version_from: Language.pm 5 | abstract: Verilog language utilities and parsing 6 | license: perl 7 | installdirs: site 8 | author: 9 | - Wilson Snyder 10 | resources: 11 | homepage: https://www.veripool.org/verilog-perl 12 | bugtracker: https://www.veripool.org/verilog-perl/issues 13 | requires: 14 | Pod::Usage: 1.34 15 | Data::Dumper: 1 16 | warnings: 1 17 | build_requires: 18 | Digest::SHA: 0 19 | Test: 1 20 | Test::More: 0 21 | Time::HiRes: 1 22 | 23 | meta-spec: 24 | url: http://module-build.sourceforge.net/META-spec-v1.4.html 25 | version: 1.4 26 | distribution_type: module 27 | generated_by: hand 28 | -------------------------------------------------------------------------------- /Netlist/ContAssign.pm: -------------------------------------------------------------------------------- 1 | # Verilog - Verilog Perl Interface 2 | # See copyright, etc in below POD section. 3 | ###################################################################### 4 | 5 | package Verilog::Netlist::ContAssign; 6 | 7 | use Verilog::Netlist; 8 | use Verilog::Netlist::Subclass; 9 | use vars qw($VERSION @ISA); 10 | use strict; 11 | @ISA = qw(Verilog::Netlist::ContAssign::Struct 12 | Verilog::Netlist::Subclass); 13 | 14 | $VERSION = '3.483'; 15 | 16 | structs('new', 17 | 'Verilog::Netlist::ContAssign::Struct' 18 | =>[name => '$', #' # Unique ID 19 | keyword => '$', #' # Keyword name 20 | filename => '$', #' # Filename this came from 21 | lineno => '$', #' # Linenumber this came from 22 | userdata => '%', # User information 23 | attributes => '%', #' # Misc attributes for systemperl or other processors 24 | # 25 | lhs => '$', #' # Left hand side of assignment 26 | rhs => '$', #' # Right hand side of assignment 27 | module => '$', #' # Module reference 28 | ]); 29 | 30 | sub delete { 31 | my $self = shift; 32 | my $h = $self->module->_statements; 33 | delete $h->{$self->name}; 34 | return undef; 35 | } 36 | 37 | ###################################################################### 38 | #### Methods 39 | 40 | sub logger { 41 | my $self = shift; 42 | return $self->netlist->logger; 43 | } 44 | sub netlist { 45 | my $self = shift; 46 | return $self->module->netlist; 47 | } 48 | 49 | sub lint {} 50 | sub link {} 51 | 52 | sub verilog_text { 53 | my $self = shift; 54 | my @out = ($self->keyword," ",$self->lhs," = ",$self->rhs,";"); 55 | return (wantarray ? @out : join('',@out)); 56 | } 57 | 58 | sub dump { 59 | my $self = shift; 60 | my $indent = shift||0; 61 | print " "x$indent,"ContAssign:",$self->keyword," lhs:",$self->lhs," rhs:",$self->rhs; 62 | print "\n"; 63 | } 64 | 65 | ###################################################################### 66 | #### Package return 67 | 1; 68 | __END__ 69 | 70 | =pod 71 | 72 | =head1 NAME 73 | 74 | Verilog::Netlist::ContAssign - ContAssign assignment 75 | 76 | =head1 SYNOPSIS 77 | 78 | use Verilog::Netlist; 79 | 80 | ... 81 | foreach my $cont ($module->statements) 82 | print $cont->name; 83 | 84 | =head1 DESCRIPTION 85 | 86 | A Verilog::Netlist::ContAssign object is created by Verilog::Netlist for 87 | every continuous assignment statement in the current module. 88 | 89 | =head1 ACCESSORS 90 | 91 | See also Verilog::Netlist::Subclass for additional accessors and methods. 92 | 93 | =over 4 94 | 95 | =item $self->keyword 96 | 97 | Keyword used to declare the assignment. Currently "assign" is the only 98 | supported value. 99 | 100 | =item $self->lhs 101 | 102 | Left hand side of the assignment. 103 | 104 | =item $self->module 105 | 106 | Pointer to the module the cell is in. 107 | 108 | =item $self->netlist 109 | 110 | Reference to the Verilog::Netlist the cell is under. 111 | 112 | =item $self->rhs 113 | 114 | Right hand side of the assignment. 115 | 116 | =back 117 | 118 | =head1 MEMBER FUNCTIONS 119 | 120 | See also Verilog::Netlist::Subclass for additional accessors and methods. 121 | 122 | =over 4 123 | 124 | =item $self->dump 125 | 126 | Prints debugging information for this cell. 127 | 128 | =back 129 | 130 | =head1 DISTRIBUTION 131 | 132 | Verilog-Perl is part of the L free Verilog EDA 133 | software tool suite. The latest version is available from CPAN and from 134 | L. 135 | 136 | Copyright 2000-2024 by Wilson Snyder. This package is free software; you 137 | can redistribute it and/or modify it under the terms of either the GNU 138 | Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 139 | 140 | =head1 AUTHORS 141 | 142 | Wilson Snyder 143 | 144 | =head1 SEE ALSO 145 | 146 | L, 147 | L 148 | L 149 | 150 | =cut 151 | -------------------------------------------------------------------------------- /Netlist/Defparam.pm: -------------------------------------------------------------------------------- 1 | # Verilog - Verilog Perl Interface 2 | # See copyright, etc in below POD section. 3 | ###################################################################### 4 | 5 | package Verilog::Netlist::Defparam; 6 | 7 | use Verilog::Netlist; 8 | use Verilog::Netlist::Subclass; 9 | use vars qw($VERSION @ISA); 10 | use strict; 11 | @ISA = qw(Verilog::Netlist::Defparam::Struct 12 | Verilog::Netlist::Subclass); 13 | 14 | $VERSION = '3.483'; 15 | 16 | structs('new', 17 | 'Verilog::Netlist::Defparam::Struct' 18 | =>[name => '$', #' # Unique ID 19 | keyword => '$', #' # Keyword name 20 | filename => '$', #' # Filename this came from 21 | lineno => '$', #' # Linenumber this came from 22 | userdata => '%', # User information 23 | attributes => '%', #' # Misc attributes for systemperl or other processors 24 | # 25 | lhs => '$', #' # Left hand side of assignment 26 | rhs => '$', #' # Right hand side of assignment 27 | module => '$', #' # Module reference 28 | ]); 29 | 30 | sub delete { 31 | my $self = shift; 32 | my $h = $self->module->_statements; 33 | delete $h->{$self->name}; 34 | return undef; 35 | } 36 | 37 | ###################################################################### 38 | #### Methods 39 | 40 | sub logger { 41 | my $self = shift; 42 | return $self->netlist->logger; 43 | } 44 | sub netlist { 45 | my $self = shift; 46 | return $self->module->netlist; 47 | } 48 | 49 | sub lint {} 50 | sub link {} 51 | 52 | sub verilog_text { 53 | my $self = shift; 54 | my @out = ($self->keyword," ",$self->lhs," = ",$self->rhs,";"); 55 | return (wantarray ? @out : join('',@out)); 56 | } 57 | 58 | sub dump { 59 | my $self = shift; 60 | my $indent = shift||0; 61 | print " "x$indent,"Defparam:",$self->keyword," lhs:",$self->lhs," rhs:",$self->rhs; 62 | print "\n"; 63 | } 64 | 65 | ###################################################################### 66 | #### Package return 67 | 1; 68 | __END__ 69 | 70 | =pod 71 | 72 | =head1 NAME 73 | 74 | Verilog::Netlist::Defparam - Defparam assignment 75 | 76 | =head1 SYNOPSIS 77 | 78 | use Verilog::Netlist; 79 | 80 | ... 81 | foreach my $cont ($module->statements) 82 | print $cont->name; 83 | 84 | =head1 DESCRIPTION 85 | 86 | A Verilog::Netlist::Defparam object is created by Verilog::Netlist for 87 | every defparam in the current module. 88 | 89 | =head1 ACCESSORS 90 | 91 | See also Verilog::Netlist::Subclass for additional accessors and methods. 92 | 93 | =over 4 94 | 95 | =item $self->keyword 96 | 97 | Keyword used to declare the assignment. Currently "defparam" is the only 98 | supported value. 99 | 100 | =item $self->lhs 101 | 102 | Left hand side of the assignment. 103 | 104 | =item $self->module 105 | 106 | Pointer to the module the cell is in. 107 | 108 | =item $self->netlist 109 | 110 | Reference to the Verilog::Netlist the cell is under. 111 | 112 | =item $self->rhs 113 | 114 | Right hand side of the assignment. 115 | 116 | =back 117 | 118 | =head1 MEMBER FUNCTIONS 119 | 120 | See also Verilog::Netlist::Subclass for additional accessors and methods. 121 | 122 | =over 4 123 | 124 | =item $self->dump 125 | 126 | Prints debugging information for this cell. 127 | 128 | =back 129 | 130 | =head1 DISTRIBUTION 131 | 132 | Verilog-Perl is part of the L free Verilog EDA 133 | software tool suite. The latest version is available from CPAN and from 134 | L. 135 | 136 | Copyright 2000-2024 by Wilson Snyder. This package is free software; you 137 | can redistribute it and/or modify it under the terms of either the GNU 138 | Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 139 | 140 | =head1 AUTHORS 141 | 142 | Wilson Snyder 143 | 144 | =head1 SEE ALSO 145 | 146 | L, 147 | L 148 | L 149 | 150 | =cut 151 | -------------------------------------------------------------------------------- /Netlist/Logger.pm: -------------------------------------------------------------------------------- 1 | # Verilog - Verilog Perl Interface 2 | # See copyright, etc in below POD section. 3 | ###################################################################### 4 | 5 | package Verilog::Netlist::Logger; 6 | require Exporter; 7 | use vars qw($VERSION); 8 | use strict; 9 | 10 | $VERSION = '3.483'; 11 | 12 | # We don't use Verilog::Netlist::Subclass, as this is called from it! 13 | 14 | ###################################################################### 15 | #### Constructors 16 | 17 | sub new { 18 | my $class = shift; 19 | my $self = { 20 | _warnings => 0, 21 | _errors => 0, 22 | _error_unlink_files => {}, 23 | @_ 24 | }; 25 | bless $self, $class; 26 | return $self; 27 | } 28 | 29 | ###################################################################### 30 | #### Accessors 31 | 32 | sub errors { 33 | my $self = shift; 34 | $self->{_errors} = shift if $#_>=0; 35 | return $self->{_errors}; 36 | } 37 | sub warnings { 38 | my $self = shift; 39 | $self->{_warnings} = shift if $#_>=0; 40 | return $self->{_warnings}; 41 | } 42 | 43 | ###################################################################### 44 | #### Error Handling 45 | 46 | sub info { 47 | my $self = shift; 48 | my $objref = shift; 49 | CORE::warn "-Info: ".$objref->fileline.": ".join('',@_); 50 | } 51 | 52 | sub warn { 53 | my $self = shift; 54 | my $objref = shift; 55 | CORE::warn "%Warning: ".$objref->fileline.": ".join('',@_); 56 | $self->warnings($self->warnings+1); 57 | } 58 | 59 | sub error { 60 | my $self = shift; 61 | my $objref = shift; 62 | CORE::warn "%Error: ".$objref->fileline.": ".join('',@_); 63 | $self->errors($self->errors+1); 64 | } 65 | 66 | sub exit_if_error { 67 | my $self = shift; 68 | my %params = @_; 69 | my $allow = $params{allow} || ""; 70 | if ($self->errors || ($self->warnings && $allow !~ /warning/)) { 71 | CORE::warn "Exiting due to errors\n"; 72 | exit(10); 73 | } 74 | return ($self->errors + $self->warnings); 75 | } 76 | 77 | sub unlink_if_error { 78 | my $self = shift; 79 | $self->{_error_unlink_files}{$_[0]} = 1; 80 | } 81 | 82 | sub error_unlink { 83 | my $self = shift; 84 | foreach my $file (keys %{$self->{_error_unlink_files}}) { 85 | unlink $file; 86 | delete $self->{_error_unlink_files}{$file}; 87 | } 88 | } 89 | 90 | sub DESTROY { 91 | my $self = shift; 92 | my $has_err = $? || $self->errors || $self->warnings; 93 | if ($has_err) { 94 | $self->error_unlink; 95 | } 96 | } 97 | 98 | ###################################################################### 99 | #### Package return 100 | 1; 101 | __END__ 102 | 103 | =pod 104 | 105 | =head1 NAME 106 | 107 | Verilog::Netlist::Logger - Error collection and reporting 108 | 109 | =head1 SYNOPSIS 110 | 111 | use Verilog::Netlist::Logger; 112 | 113 | ... 114 | 115 | my $self = Verilog::Netlist::Logger->new(); 116 | $self->info("We're here\n"); 117 | $self->warn("Things look bad\n"); 118 | $self->error("Things are even worse\n"); 119 | $self->exit_if_error(); 120 | 121 | =head1 DESCRIPTION 122 | 123 | The Verilog::Netlist::Logger is used to report all errors detected by 124 | Verilog::Netlist::* structures. By default, Verilog::Netlist creates a new 125 | Logger object, and passes it down to all contained objects. Users may 126 | create their own logger objects to catch or otherwise handle error 127 | messages. 128 | 129 | =head1 MEMBER FUNCTIONS 130 | 131 | =over 4 132 | 133 | =item $self->error(object, I) 134 | 135 | Print an error about the object in a standard format. The object must have 136 | a fileline method. 137 | 138 | =item $self->exit_if_error([allow=>'warning']) 139 | 140 | Exits the program if any errors were detected. Optionally specify 141 | allow=>'warning' to ignore warnings. 142 | 143 | =item $self->info(I) 144 | 145 | Print an informational about the object in a standard format. The object 146 | must have a fileline method. 147 | 148 | =item $self->lineno() 149 | 150 | The line number the entity was created on. 151 | 152 | =item $self->unlink_if_error(I) 153 | 154 | Requests the given file be deleted if any errors are detected when the 155 | Logger object is destroyed. Used for temporary files. 156 | 157 | =item $self->warn(I) 158 | 159 | Print a warning about the object in a standard format. The object must 160 | have a fileline method. 161 | 162 | =back 163 | 164 | =head1 DISTRIBUTION 165 | 166 | Verilog-Perl is part of the L free Verilog EDA 167 | software tool suite. The latest version is available from CPAN and from 168 | L. 169 | 170 | Copyright 2000-2024 by Wilson Snyder. This package is free software; you 171 | can redistribute it and/or modify it under the terms of either the GNU 172 | Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 173 | 174 | =head1 AUTHORS 175 | 176 | Wilson Snyder 177 | 178 | =head1 SEE ALSO 179 | 180 | L, 181 | L, 182 | L 183 | 184 | =cut 185 | -------------------------------------------------------------------------------- /Netlist/PinSelection.pm: -------------------------------------------------------------------------------- 1 | # Verilog - Verilog Perl Interface 2 | # See copyright, etc in below POD section. 3 | ###################################################################### 4 | 5 | package Verilog::Netlist::PinSelection; 6 | 7 | use vars qw($VERSION); 8 | use strict; 9 | use warnings; 10 | 11 | $VERSION = '3.427'; 12 | 13 | ###################################################################### 14 | #### Methods 15 | 16 | ## Constructor 17 | sub new { 18 | my ($class, $netname, $msb, $lsb) = @_; 19 | 20 | my $self = bless({}, $class); 21 | $self->{_netname} = $netname; 22 | $self->{_msb} = $msb; 23 | $self->{_lsb} = $lsb; 24 | return $self; 25 | } 26 | 27 | ## Standard accessors 28 | sub netname { 29 | # ($self, $new) = @_; 30 | $_[0]->{_netname} = $_[1] if (@_ == 2); 31 | return $_[0]->{_netname}; 32 | } 33 | 34 | sub lsb { 35 | # ($self, $new) = @_; 36 | $_[0]->{_lsb} = $_[1] if (@_ == 2); 37 | return $_[0]->{_lsb}; 38 | } 39 | 40 | sub msb { 41 | # ($self, $new) = @_; 42 | $_[0]->{_msb} = $_[1] if (@_ == 2); 43 | return $_[0]->{_msb}; 44 | } 45 | 46 | ## Member functions 47 | sub bracketed_msb_lsb { 48 | my $self = shift; 49 | my $out = ""; 50 | # Handle sized constant numbers (e.g., 7'b0) distinctively 51 | # but leave unsized constants (msb/lsb undefined) alone. 52 | if ($self->netname =~ /^'/) { 53 | $out .= $self->msb + 1 if defined($self->msb); 54 | $out .= $self->netname; 55 | } else { 56 | $out .= $self->netname; 57 | if (defined($self->msb)) { 58 | if ($self->msb == $self->lsb) { 59 | $out .= "[".$self->msb."]"; 60 | } else { 61 | $out .= "[".$self->msb.":".$self->lsb."]"; 62 | } 63 | } 64 | } 65 | return $out; 66 | } 67 | 68 | ###################################################################### 69 | #### Package return 70 | 1; 71 | __END__ 72 | 73 | =pod 74 | 75 | =head1 NAME 76 | 77 | Verilog::Netlist::PinSelection - Nets attached to a Verilog Cell's Pins 78 | 79 | =head1 DESCRIPTION 80 | 81 | Verilog::Netlist::PinSelection objects are used by Verilog::Netlist::Pin 82 | to define ranges of nets attached to the respective pin of a cell. 83 | 84 | =head1 ACCESSORS 85 | 86 | =over 4 87 | 88 | =item $self->netname 89 | 90 | Name of the respective net, or, if use_pinselects is disabled, the string 91 | representation of the whole pin value. In the case of a sized constant only 92 | the part following the ' is stored while the width is encoded in the msb 93 | and lsb fields. 94 | 95 | =item $self->lsb 96 | 97 | Least significant bit of the underlying net within the selection. 98 | 99 | =item $self->msb 100 | 101 | Most significant bit of the underlying net within the selection. 102 | 103 | =back 104 | 105 | =head1 MEMBER FUNCTIONS 106 | 107 | =over 4 108 | 109 | =item $self->bracketed_msb_lsb 110 | 111 | Returns the common string representation of a vectored net, e.g. netA[15:8]. 112 | 113 | =back 114 | 115 | =head1 DISTRIBUTION 116 | 117 | Verilog-Perl is part of the L free Verilog EDA 118 | software tool suite. The latest version is available from CPAN and from 119 | L. 120 | 121 | Copyright 2000-2024 by Wilson Snyder. This package is free software; you 122 | can redistribute it and/or modify it under the terms of either the GNU 123 | Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 124 | 125 | =head1 AUTHORS 126 | 127 | Stefan Tauner 128 | Wilson Snyder 129 | 130 | # =head1 SEE ALSO 131 | 132 | # L, 133 | # L 134 | # L 135 | 136 | =cut 137 | -------------------------------------------------------------------------------- /Parser/.gitignore: -------------------------------------------------------------------------------- 1 | *.bs 2 | *.c 3 | *.d 4 | *.def 5 | *.dll 6 | *.exp 7 | *.o 8 | *.old 9 | *.output 10 | *.xsc 11 | *.pre.* 12 | *_pretmp.* 13 | *_callbackgen.* 14 | *_cleaned.* 15 | Makefile 16 | VParseLex*.cpp 17 | VParseBison.c 18 | VParseBison.cpp 19 | VParseBison.h 20 | blib 21 | gen 22 | example 23 | pm_to_blib 24 | -------------------------------------------------------------------------------- /Parser/VAst.h: -------------------------------------------------------------------------------- 1 | // -*- C++ -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2009-2024 by Wilson Snyder. This program is free software; 5 | // you can redistribute it and/or modify it under the terms of either the 6 | // GNU Lesser General Public License Version 3 or the Perl Artistic License 7 | // Version 2.0. 8 | // 9 | // This program is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | //************************************************************************* 15 | /// \file 16 | /// \brief Verilog::Parse: Symbol table accessing 17 | /// 18 | /// Authors: Wilson Snyder 19 | /// 20 | /// Code available from: https://www.veripool.org/verilog-perl 21 | /// 22 | //************************************************************************* 23 | 24 | #ifndef _VAST_H_ 25 | #define _VAST_H_ 1 26 | 27 | #include 28 | #include 29 | #include 30 | using namespace std; 31 | 32 | // We don't include perl.h as it gets upset when merged with bison 33 | // code. So just grab a minimal set. 34 | struct av; 35 | struct hv; 36 | 37 | //###################################################################### 38 | // Enumeration that indicates what type of symbol is in the symbol tree. 39 | // We may later change to use a different object for each type 40 | 41 | class VAstType { 42 | public: 43 | enum en { 44 | NOT_FOUND = 0, 45 | NETLIST = 1, // Top of structure, created by Parser.pm:sub new{} 46 | AN_ERROR = 2, // Consistency error in internal tables (ERROR alone is a #define on some systems) 47 | UNKNOWN = 3, // Things that need scope, but don't know type yet 48 | // 49 | BLOCK, 50 | CHECKER, 51 | CLASS, // For yaID__CLASS 52 | CLOCKING, 53 | COVERGROUP, // For yaID__COVERGROUP 54 | ENUM, 55 | FORK, 56 | FUNCTION, 57 | INTERFACE, 58 | LET, 59 | MODPORT, 60 | MODULE, 61 | PACKAGE, // For yaID__PACKAGE 62 | PROGRAM, 63 | PROPERTY, 64 | SEQUENCE, 65 | STRUCT, 66 | TASK, 67 | TYPE, // For yaID__TYPE 68 | UNION, 69 | _MAX 70 | }; 71 | enum en m_e; 72 | inline VAstType() {}; 73 | inline VAstType(en _e) : m_e(_e) {}; 74 | explicit inline VAstType(int _e) : m_e(static_cast(_e)) {}; 75 | operator en() const { return m_e; }; 76 | const char* ascii() const { 77 | static const char* names[] = { 78 | "NOT_FOUND", "netlist", "error", "unknown", 79 | "block", "checker", "class", "clocking", "covergroup", 80 | "enum", "fork", "function", "interface", "let", 81 | "modport", "module", "package", "program", "property", 82 | "sequence", "struct", "task", "type", "union", 83 | "_MAX" 84 | }; 85 | return names[m_e]; 86 | } 87 | }; 88 | inline bool operator== (VAstType lhs, VAstType rhs) { return (lhs.m_e == rhs.m_e); } 89 | inline bool operator== (VAstType lhs, VAstType::en rhs) { return (lhs.m_e == rhs); } 90 | inline bool operator== (VAstType::en lhs, VAstType rhs) { return (lhs == rhs.m_e); } 91 | 92 | //###################################################################### 93 | // Single symbol table 94 | 95 | class VAstEnt { 96 | private: 97 | // MEMBERS 98 | // NOT ALLOWED - this class really has this==AV* 99 | 100 | // STATIC MEMBERS 101 | static int s_debug; 102 | public: 103 | static void debug(int flag) { s_debug=flag; } 104 | static int debug() { return s_debug; } 105 | 106 | private: 107 | // CREATORS 108 | VAstEnt() { assert(0); } // Not made by users, it's an AV* 109 | ~VAstEnt() { assert(0); } // Not made by users, it's an AV* 110 | 111 | av* newAVEnt(VAstType type); 112 | static void initAVEnt(struct av* avp, VAstType type, struct av* parentp); 113 | 114 | // ACCESSORS 115 | inline struct av* castAVp() { return (struct av*)(this); } 116 | inline VAstEnt* avToSymEnt(struct av* avp) { return (VAstEnt*)(avp); } 117 | 118 | /// $self->[2]: For current entry, the hash of symbols under it 119 | struct hv* subhash(); 120 | 121 | /// Insert into current table 122 | void replaceInsert(VAstEnt* newentp, const string& name); 123 | 124 | public: 125 | // ACCESSORS 126 | 127 | /// $self->[0]: For current entry, the node type 128 | VAstType type(); 129 | 130 | /// $self->[1]: For current entry, what node it is under or NULL if netlist 131 | VAstEnt* parentp(); 132 | 133 | /// type() indicates we shouldn't report this as a containing object 134 | bool typeIgnoreObjof() { VAstType t=type(); return t==VAstType::BLOCK || t==VAstType::FORK; } 135 | 136 | /// Info on current node, for debug 137 | string ascii(const string& name=""); 138 | 139 | // METHODS 140 | /// Return internal pointer for given name or null 141 | VAstEnt* findSym(const string& name); 142 | 143 | /// Find or create a symbol under current entry 144 | VAstEnt* findInsert(VAstType type, const string& name); 145 | 146 | /// Replace or create a symbol entry under current entry 147 | VAstEnt* replaceInsert(VAstType type, const string& name); 148 | 149 | /// Insert into current table from another imported package's table 150 | void import(VAstEnt* fromEntp, const string& id_or_star); 151 | 152 | protected: 153 | friend class VSymStack; 154 | void initNetlist(VFileLine* fl); 155 | }; 156 | 157 | #endif // guard 158 | -------------------------------------------------------------------------------- /Parser/VParse.cpp: -------------------------------------------------------------------------------- 1 | // -*- C++ -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | // you can redistribute it and/or modify it under the terms of either the GNU 6 | // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | // 8 | // This program is distributed in the hope that it will be useful, 9 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | // GNU General Public License for more details. 12 | // 13 | //************************************************************************* 14 | /// \file 15 | /// \brief Verilog::Parse: Internal implementation of default preprocessor 16 | /// 17 | /// Authors: Wilson Snyder 18 | /// 19 | /// Code available from: https://www.veripool.org/verilog-perl 20 | /// 21 | //************************************************************************* 22 | 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | 32 | #include "VParse.h" 33 | #include "VParseLex.h" 34 | #include "VParseGrammar.h" 35 | #include "VSymTable.h" 36 | 37 | VParseGrammar* VParseGrammar::s_grammarp = NULL; 38 | 39 | //************************************************************************* 40 | 41 | VParse::VParse(VFileLine* filelinep, av* symsp, 42 | bool sigParser, bool useUnreadbackFlag, bool useProtected, bool usePinselects) 43 | : m_syms(filelinep, symsp) 44 | { 45 | m_inFilelinep = filelinep; 46 | m_sigParser = sigParser; 47 | m_useUnreadback = useUnreadbackFlag; 48 | m_useProtected = useProtected; 49 | m_usePinselects = usePinselects; 50 | m_debug = 0; 51 | m_lexp = new VParseLex(this); 52 | m_grammarp = new VParseGrammar(this); 53 | m_eof = false; 54 | m_anonNum = 0; 55 | m_symTableNextId = NULL; 56 | m_callbackMasterEna = true; 57 | } 58 | 59 | VParse::~VParse() { 60 | if (m_lexp) { 61 | delete m_lexp; 62 | m_lexp = NULL; 63 | } 64 | if (m_grammarp) { 65 | delete m_grammarp; 66 | m_grammarp = NULL; 67 | } 68 | } 69 | 70 | void VParse::debug(int level) { 71 | m_debug = level; 72 | if (level>5) m_grammarp->debug(level); 73 | if (level>5) m_lexp->debug(level); 74 | } 75 | 76 | VFileLine* VParse::inFilelinep() const { return m_inFilelinep; } 77 | 78 | bool VParse::inCellDefine() const { return m_lexp->m_inCellDefine; } 79 | 80 | void VParse::language(const char* valuep) { m_lexp->language(valuep); } 81 | 82 | void VParse::parse(const string& text) { 83 | if (debug()>=10) { cout<<"VParse::parse: '"< max_chunk) chunk = max_chunk; 94 | m_buffers.push_back(string(text.data()+pos, chunk)); 95 | pos += chunk; 96 | } 97 | } 98 | 99 | void VParse::setEof() { 100 | m_eof = true; 101 | if (debug()) { cout<<"VParse::setEof: for "<<(void*)(this)<restart(); 103 | if (sigParser()) { 104 | // Use the bison parser 105 | m_grammarp->parse(); 106 | } else { 107 | fakeBison(); 108 | } 109 | // End of parsing callback 110 | endparseCb(inFilelinep(),""); 111 | if (debug()) { cout<<"VParse::setEof: DONE\n"; } 112 | } 113 | 114 | void VParse::fakeBison() { 115 | // Verilog::Parser and we don't care about the syntax, so just Lex. 116 | VParseBisonYYSType yylval; 117 | while (int tok = lexToBison(&yylval)) { 118 | if (tok) {} // Prevent unused on some GCCs 119 | } 120 | } 121 | 122 | int VParse::lexToBison(VParseBisonYYSType* yylvalp) { 123 | return m_lexp->lexToBison(yylvalp); 124 | } 125 | 126 | size_t VParse::inputToLex(char* buf, size_t max_size) { 127 | size_t got = 0; 128 | while (got < max_size // Haven't got enough 129 | && !m_buffers.empty()) { // And something buffered 130 | string front = m_buffers.front(); m_buffers.pop_front(); 131 | size_t len = front.length(); 132 | if (len > (max_size-got)) { // Front string too big 133 | string remainder = front.substr(max_size-got); 134 | front = front.substr(0, max_size-got); 135 | m_buffers.push_front(remainder); // Put back remainder for next time 136 | len = (max_size-got); 137 | } 138 | strncpy(buf+got, front.c_str(), len); 139 | got += len; 140 | } 141 | if (debug()>=9) { 142 | string out = string(buf,got); 143 | cout<<" inputToLex got="< 27 | #include 28 | #include 29 | #include 30 | using namespace std; 31 | #include "VFileLine.h" 32 | #include "VParse.h" 33 | #include "VAst.h" 34 | 35 | //============================================================================ 36 | // Containers of things to put out later 37 | 38 | struct VParseGPin { 39 | VFileLine* m_fl; 40 | string m_name; 41 | string m_conn; 42 | int m_number; 43 | VParseGPin(VFileLine* fl, const string& name, const string& conn, int number) 44 | : m_fl(fl), m_name(name), m_conn(conn), m_number(number) {} 45 | }; 46 | 47 | struct VParseNet { 48 | string m_name; 49 | string m_msb; 50 | string m_lsb; 51 | VParseNet(const string& net, const string& msb, const string& lsb) 52 | : m_name(net), m_msb(msb), m_lsb(lsb) {} 53 | VParseNet(const string& net) 54 | : m_name(net), m_msb(""), m_lsb("") {} 55 | }; 56 | 57 | struct VParseVar { 58 | string m_decl; 59 | string m_net; 60 | string m_io; 61 | string m_dtype; 62 | string m_range; 63 | }; 64 | 65 | //============================================================================ 66 | // We can't use bison's %union as the string type doesn't fit in a union. 67 | // It's fine to use a struct though! 68 | 69 | struct VParseBisonYYSType { 70 | string str; 71 | VFileLine* fl; 72 | VAstEnt* scp; // Symbol table scope for future lookups 73 | }; 74 | #define YYSTYPE VParseBisonYYSType 75 | 76 | //============================================================================ 77 | 78 | class VParseGrammar { 79 | static VParseGrammar* s_grammarp; ///< Current THIS, bison() isn't class based 80 | VParse* m_parsep; 81 | //int debug() { return 9; } 82 | 83 | public: // Only for VParseBison 84 | int m_pinNum; ///< Pin number being parsed 85 | 86 | VParseVar m_var; 87 | 88 | string m_cellMod; 89 | bool m_cellParam; 90 | 91 | bool m_portNextNetValid; 92 | string m_portNextNetName; 93 | string m_portNextNetMsb; 94 | string m_portNextNetLsb; 95 | 96 | bool m_withinPin; 97 | bool m_withinInst; 98 | 99 | deque m_pinStack; 100 | deque m_portStack; 101 | deque m_varStack; 102 | 103 | public: // But for internal use only 104 | static VParseGrammar* staticGrammarp() { return s_grammarp; } 105 | static VParse* staticParsep() { return staticGrammarp()->m_parsep; } 106 | 107 | static void bisonError(const char* text) { 108 | staticParsep()->error(text); 109 | } 110 | //static VFileLine* fileline() { return s_grammarp->m_fileline; } 111 | 112 | public: 113 | // CREATORS 114 | VParseGrammar(VParse* parsep) : m_parsep(parsep) { 115 | s_grammarp = this; 116 | m_pinNum = 0; 117 | m_cellParam = false; 118 | m_portNextNetValid = false; 119 | m_withinInst = false; 120 | m_withinPin = false; 121 | } 122 | ~VParseGrammar() { 123 | s_grammarp = NULL; 124 | } 125 | 126 | // ACCESSORS 127 | void debug(int level); 128 | int pinNum() const { return m_pinNum; } 129 | void pinNum(int flag) { m_pinNum = flag; } 130 | void pinNumInc() { m_pinNum++; } 131 | 132 | // METHODS 133 | int parse(); // See VParseBison.y 134 | static const char* tokenName(int token); 135 | }; 136 | 137 | #endif // Guard 138 | -------------------------------------------------------------------------------- /Parser/VParseLex.h: -------------------------------------------------------------------------------- 1 | // -*- C++ -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | // you can redistribute it and/or modify it under the terms of either the GNU 6 | // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | // 8 | // This program is distributed in the hope that it will be useful, 9 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | // GNU General Public License for more details. 12 | // 13 | //************************************************************************* 14 | /// \file 15 | /// \brief Verilog::Parse: Internal header for lex interfacing 16 | /// 17 | /// Authors: Wilson Snyder 18 | /// 19 | /// Code available from: https://www.veripool.org/verilog-perl 20 | /// 21 | /// This header provides the interface between the lex proper VParseLex.l/.cpp 22 | /// and the class implementation file VParse.cpp 23 | /// It is not intended for user applications. 24 | /// 25 | //************************************************************************* 26 | 27 | #ifndef _VPARSELEX_H_ // Guard 28 | #define _VPARSELEX_H_ 1 29 | 30 | #include "VFileLine.h" 31 | #include "VParseGrammar.h" 32 | 33 | //====================================================================== 34 | // Externs created by flex 35 | // We add a prefix so that other lexers/flexers in the same program won't collide. 36 | #ifndef yy_create_buffer 37 | # define yy_create_buffer VParseLex_create_buffer 38 | # define yy_delete_buffer VParseLex_delete_buffer 39 | # define yy_scan_buffer VParseLex_scan_buffer 40 | # define yy_scan_string VParseLex_scan_string 41 | # define yy_scan_bytes VParseLex_scan_bytes 42 | # define yy_flex_debug VParseLex_flex_debug 43 | # define yy_init_buffer VParseLex_init_buffer 44 | # define yy_flush_buffer VParseLex_flush_buffer 45 | # define yy_load_buffer_state VParseLex_load_buffer_state 46 | # define yy_switch_to_buffer VParseLex_switch_to_buffer 47 | # define yyin VParseLexin 48 | # define yyleng VParseLexleng 49 | # define yylex VParseLexlex 50 | # define yyout VParseLexout 51 | # define yyrestart VParseLexrestart 52 | # define yytext VParseLextext 53 | #endif 54 | 55 | #ifndef YY_BUFFER_STATE 56 | struct yy_buffer_state; 57 | typedef struct yy_buffer_state *YY_BUFFER_STATE; 58 | # define YY_BUF_SIZE 16384 59 | #endif 60 | 61 | extern int yylex(); 62 | extern void yyrestart(FILE*); 63 | 64 | YY_BUFFER_STATE yy_create_buffer (FILE *file, int size); 65 | YY_BUFFER_STATE yy_scan_bytes(const char *bytes, int len); 66 | void yy_switch_to_buffer(YY_BUFFER_STATE new_buffer); 67 | void yy_delete_buffer(YY_BUFFER_STATE b); 68 | 69 | class VParse; 70 | 71 | //====================================================================== 72 | /// Class entry for each lexer state 73 | 74 | class VParseLex { 75 | public: // Used only by VParseLex.cpp and VParse.cpp 76 | VParse* m_parsep; ///< Current parser 77 | bool m_inCellDefine; ///< In a `celldefine 78 | 79 | int m_prevLexToken; ///< previous parsed token (for lexer) 80 | bool m_ahead; ///< aheadToken is valid 81 | int m_aheadToken; ///< Token we read ahead 82 | VParseBisonYYSType m_aheadVal; ///< aheadToken's value 83 | 84 | int m_pvstate; ///< "pure virtual" detection 85 | 86 | // Parse state 87 | YY_BUFFER_STATE m_yyState; ///< flex input state 88 | 89 | // State to lexer 90 | static VParseLex* s_currentLexp; ///< Current lexing point 91 | static VParseBisonYYSType* s_yylvalp; 92 | int prevLexToken() { return m_prevLexToken; } // Parser -> lexer communication 93 | 94 | // CONSTRUCTORS 95 | VParseLex(VParse* parsep) { 96 | m_parsep = parsep; 97 | m_inCellDefine = false; 98 | m_prevLexToken = 0; 99 | m_ahead = false; 100 | m_pvstate = 0; 101 | 102 | m_yyState = yy_create_buffer(NULL, YY_BUF_SIZE); 103 | s_currentLexp = this; 104 | yyrestart(NULL); 105 | debug(0); 106 | } 107 | ~VParseLex() { 108 | yy_delete_buffer(m_yyState); 109 | s_currentLexp = NULL; 110 | } 111 | 112 | void restart() { yyrestart(NULL); } 113 | 114 | // Internal Utilities 115 | static bool symEscapeless(const char* textp, size_t leng) { 116 | // Are \ escapes needed to print this symbol? 117 | if (leng<1) return false; // Probably not a valid identifier, but better than a core dump... 118 | if (!isalpha(textp[0]) && textp[0] != '_') return false; 119 | const char* cp = textp; 120 | for (size_t tleng=leng; tleng; tleng--, cp++) { 121 | if (!isalnum(*cp) && *cp != '_') return false; 122 | } 123 | if (VParse::isKeyword(textp, leng)) return false; 124 | return true; 125 | } 126 | 127 | /// Called by VParse.cpp to inform lexer 128 | void unputString(const char* textp); 129 | void unputString(const char* textp, size_t length); 130 | 131 | void debug(int level); 132 | void language(const char* value); 133 | 134 | int lexToBison(VParseBisonYYSType* yylvalp); 135 | private: 136 | void unused(); 137 | int yylexReadTok(); 138 | int lexToken(VParseBisonYYSType* yylvalp); 139 | }; 140 | 141 | #endif // Guard 142 | -------------------------------------------------------------------------------- /Parser/VSymTable.h: -------------------------------------------------------------------------------- 1 | // -*- C++ -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2009-2024 by Wilson Snyder. This program is free software; 5 | // you can redistribute it and/or modify it under the terms of either the 6 | // GNU Lesser General Public License Version 3 or the Perl Artistic License 7 | // Version 2.0. 8 | // 9 | // This program is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | //************************************************************************* 15 | /// \file 16 | /// \brief Verilog::Parse: Symbol table accessing 17 | /// 18 | /// Authors: Wilson Snyder 19 | /// 20 | /// Code available from: https://www.veripool.org/verilog-perl 21 | /// 22 | //************************************************************************* 23 | 24 | #ifndef _VSYMTABLE_H_ 25 | #define _VSYMTABLE_H_ 1 26 | 27 | #include "VFileLine.h" 28 | #include "VAst.h" 29 | #include 30 | #include 31 | using namespace std; 32 | 33 | //###################################################################### 34 | // List of symbol tables 35 | 36 | class VSymStack { 37 | typedef vector SymStack; 38 | 39 | SymStack m_sympStack; // Stack of symbol tables 40 | VAstEnt* m_currentSymp; // Current symbol table 41 | 42 | public: 43 | // CONSTRUCTORS 44 | VSymStack(VFileLine* fl, struct av* symp); // Pass in top-level symbol table array 45 | ~VSymStack() {} 46 | 47 | // ACCESSORS 48 | VAstEnt* currentSymp() const { return m_currentSymp; } 49 | VAstEnt* netlistSymp() const { return m_sympStack.front(); } 50 | 51 | // METHODS 52 | /// Insert a new entry, and return the new entry 53 | VAstEnt* replaceInsert(VAstType type, const string& name) { 54 | return m_currentSymp->replaceInsert(type,name); 55 | } 56 | /// Insert an entry if it doesn't exist 57 | VAstEnt* findInsert(VAstType type, const string& name) { 58 | return m_currentSymp->findInsert(type,name); 59 | } 60 | 61 | /// Return type of current lookup 62 | VAstType curType() { return m_currentSymp->type(); } 63 | 64 | void showUpward() { 65 | cout<<"SymTable Stack:\n"; 66 | for (SymStack::reverse_iterator it=m_sympStack.rbegin(); it!=m_sympStack.rend(); ++it) { 67 | VAstEnt* symp = *it; 68 | cout<<"\t"<ascii()<parentp()) { 72 | cout<<"\t"<ascii()<findSym 78 | VAstEnt* findEntUpward(const string& name) { 79 | for (VAstEnt* symp=currentSymp(); symp; symp=symp->parentp()) { 80 | if (VAstEnt* subp = symp->findSym(name)) { 81 | return subp; 82 | } 83 | } 84 | return NULL; 85 | } 86 | VAstType findTypeUpward(const string& name) { 87 | if (VAstEnt* subp = findEntUpward(name)) { 88 | return subp->type(); 89 | } else { 90 | return VAstType::NOT_FOUND; 91 | } 92 | } 93 | 94 | /// Return what this object is a member of, ignoring blocks 95 | string objofUpward() { 96 | for (VAstEnt* symp=currentSymp(); symp; symp=symp->parentp()) { 97 | if (!symp->typeIgnoreObjof()) { 98 | return symp->type().ascii(); 99 | } 100 | } 101 | assert(0); // Should have been a NETLIST if nothing else 102 | return ""; // Asserts maybe NOPed 103 | } 104 | 105 | /// Push current scope down to a new scope 106 | void pushScope(VAstEnt* symp) { 107 | m_sympStack.push_back(symp); 108 | m_currentSymp = symp; 109 | } 110 | 111 | /// Pop current scope up to a previous scope 112 | void popScope(VFileLine* fl) { 113 | m_sympStack.pop_back(); 114 | // Must always have one remaining - it's globals. Thus this is after the pop. 115 | if (m_sympStack.empty()) { fl->error("symbol stack underflow"); return; } 116 | m_currentSymp = m_sympStack.back(); 117 | } 118 | 119 | /// Import from package::id_or_star to this 120 | void import(VFileLine* fl, const string& pkg, const string& id_or_star) { 121 | import(fl, pkg, findEntUpward(pkg), id_or_star); 122 | } 123 | void import(VFileLine* fl, const string& pkg, VAstEnt* entp, const string& id_or_star) { 124 | if (!entp) { // Internal problem, because we earlier found pkg to label it an ID__aPACKAGE 125 | fl->error("Internal: Import package not found: "+pkg); 126 | return; 127 | } 128 | m_currentSymp->import(entp, id_or_star); 129 | } 130 | 131 | static void selftest(); 132 | }; 133 | 134 | #endif // guard 135 | -------------------------------------------------------------------------------- /Parser/typemap: -------------------------------------------------------------------------------- 1 | TYPEMAP 2 | const char * T_PV 3 | VParserXs * O_CTHIS 4 | 5 | 6 | OUTPUT 7 | # The variable is stored into a pre-blessed $self->{_cthis} 8 | O_CTHIS 9 | // SELF->{_cthis} = THIS 10 | if( sv_isobject(SELF) && (SvTYPE(SvRV(SELF)) == SVt_PVHV) ) { 11 | SV **svp = hv_fetch((HV*)SvRV(SELF), \"_cthis\", 6, 1); 12 | sv_setiv(*svp, PTR2IV( $var )); 13 | XSRETURN_UNDEF; 14 | } else { 15 | warn( \"${Package}::$func_name() -- $var is not a Verilog::Parser object\" ); 16 | XSRETURN_UNDEF; 17 | } 18 | 19 | INPUT 20 | O_CTHIS 21 | $var = NULL; 22 | if( sv_isobject($arg) && (SvTYPE(SvRV( $arg )) == SVt_PVHV) ) { 23 | SV **svp = hv_fetch((HV*)SvRV(( $arg )), \"_cthis\", 6, 0); 24 | $var = NULL; 25 | if (svp) { $var = INT2PTR($type,SvIV( *svp )); } 26 | } 27 | if (!$var || !dynamic_cast($var)) { 28 | warn( \"${Package}::$func_name() -- $var is not a Verilog::Parser object\" ); 29 | XSRETURN_UNDEF; 30 | } 31 | -------------------------------------------------------------------------------- /Preproc/.gitignore: -------------------------------------------------------------------------------- 1 | blib 2 | gen 3 | Makefile 4 | pm_to_blib 5 | VPreLex*.cpp 6 | *.def 7 | *.dll 8 | *.exp 9 | *.o 10 | *.c 11 | *.bs 12 | *.xsc 13 | *.output 14 | *.old 15 | *_cleaned.* 16 | -------------------------------------------------------------------------------- /Preproc/Makefile.PL: -------------------------------------------------------------------------------- 1 | # DESCRIPTION: Perl ExtUtils: Type 'perl Makefile.PL' to create a Makefile for this package 2 | # 3 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 4 | # you can redistribute it and/or modify it under the terms of either the GNU 5 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 6 | 7 | use ExtUtils::MakeMaker; 8 | use Config; 9 | 10 | sub MY::postamble { 11 | my $out; 12 | #print Config::myconfig(); 13 | if ($Config{osname} !~ /cygwin/i && $Config{archname} !~ /cygwin/i 14 | && $Config{osname} !~ /darwin/i && $Config{archname} !~ /darwin/i) { 15 | # Cygwin: Don't change LD, it breaks 16 | # Sun: Requires g++ LD 17 | # Linux: Either way 18 | $out .= "LD = g++\n"; 19 | } 20 | # Note OPTIMIZE is passed from upper makefile, so this code needed there too. 21 | my $optimize = $Config{optimize}; $optimize =~ s/(^| )-O2( |$)/\1-O\2/g; 22 | # pass hardening flags 23 | $optimize .= " $ENV{CFLAGS} $ENV{CPPFLAGS}"; 24 | $out .= "OPTIMIZE = $optimize\n"; 25 | if ($Config{osname} =~ /cygwin/i || $Config{archname} =~ /cygwin/i) { 26 | # Cygwin ExtUtils::MakeMaker ignores our LIBS declaration and says 27 | # "No library found for -lstdc++". Force it. 28 | $out .= "LDLOADLIBS += -lstdc++\n"; 29 | # Cygwin: High optimization causes g++ "out of memory" 30 | $out .= "OPTIMIZE += -O\n"; 31 | } 32 | if ($Config{osname} =~ /darwin/i || $Config{archname} =~ /darwin/i) { 33 | # MakeMaker wants to create bundles on MacOSX rather than dylibs. We override DLEXT and LDDLFLAGS generated by MakeMaker in this case 34 | $out .= "DLEXT = dylib\n"; 35 | if ($^V eq '5.12.4') { 36 | $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.12/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); 37 | } elsif ($^V eq '5.18.2') { 38 | $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/5.18/%s/CORE -lperl -L/usr/local/lib\n",$Config{archname}); 39 | } elsif ($^V < 'v5.26.3') { 40 | $out .= sprintf("LDDLFLAGS = -dynamiclib -lstdc++ -L/System/Library/Perl/%vd/%s/CORE -lperl -lgcc_eh -L/usr/local/lib\n",$^V,$Config{archname}); 41 | } 42 | } 43 | $out .= "CCFLAGS += -Wall -Wno-unused -Wno-sign-compare -Werror\n" if $ENV{VERILATOR_AUTHOR_SITE}; 44 | #$out .= "CCFLAGS += -O0 -ggdb\n" if $ENV{VERILATOR_AUTHOR_SITE}; print "%Warning: -O0 --gdb on, also FLEX -d on"; 45 | $out .= "CCFLAGS += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; 46 | $out .= "OPTIMIZE += -Wno-unused\n" if $ENV{VERILATOR_AUTHOR_SITE}; # Makefile has another -Wall 47 | $out .= "OPTIMIZE += $ENV{VERILOGPERL_CCFLAGS}\n" if defined $ENV{VERILOGPERL_CCFLAGS}; 48 | $out .= "CCFLAGS += -I\$(PPSRC)\n"; 49 | my $cmt = $ENV{VERILOGPERL_FLEX_DEBUG} ? "" : "#"; 50 | $out .= "${cmt}CFLAGS += -DFLEX_DEBUG\n"; 51 | $out .= "${cmt}LEXFLAGS += -d\n"; 52 | $out .= ' 53 | CC = $(OBJCACHE) g++ 54 | LEX = flex 55 | YACC = bison 56 | PPSRC = ../Preproc 57 | FLEXFIX = $(PPSRC)/flexfix 58 | TOOLHASH = $(PPSRC)/toolhash 59 | XSUBPPFIX = $(PPSRC)/xsubppfix 60 | 61 | VPATH += . $(PPSRC) 62 | 63 | VPreLex.o: VPreLex.h VPreProc.h VFileLine.h 64 | VPreProc.o: VPreLex.h VPreProc.h VFileLine.h 65 | VFileLine.o: VFileLine.h 66 | 67 | VPreLex_pretmp.cpp: VPreLex.l 68 | -$(LEX) --version 69 | $(PERL) $(TOOLHASH) --verbose --in $< --out $@ --cmd $(LEX) $(LEXFLAGS) -o$@ $< 70 | 71 | VPreLex.cpp: $(FLEXFIX) VPreLex_pretmp.cpp 72 | $(PERL) $(FLEXFIX) VPreLex < VPreLex_pretmp.cpp > $@ 73 | 74 | Preproc_cleaned.cpp: Preproc.c 75 | $(PERL) $(XSUBPPFIX) < Preproc.c > Preproc_cleaned.cpp 76 | 77 | clean:: 78 | -$(RM_RF) test *.d *.o *.output 79 | -$(RM_RF) VPreLex*.cpp Preproc_cleaned.* 80 | -$(RM_RF) VPreprocLex* 81 | '; 82 | return $out; 83 | } 84 | 85 | # Grr; some flags cause warnings in g++ 86 | (my $ccflags = $Config{ccflags}) =~ s/ *-Wdeclaration-after-statement//; 87 | 88 | WriteMakefile( 89 | NAME => "Verilog::Preproc", 90 | LIBS => '-lstdc++', 91 | VERSION_FROM => 'Preproc.pm', 92 | XSOPT => '-C++', 93 | CCFLAGS => $ccflags, 94 | OBJECT => 'VFileLine.o VPreProc.o VPreLex.o', 95 | MYEXTLIB => 'Preproc_cleaned.o', 96 | ); 97 | -------------------------------------------------------------------------------- /Preproc/VFileLine.cpp: -------------------------------------------------------------------------------- 1 | // -*- C++ -*- 2 | //************************************************************************* 3 | // 4 | // Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | // you can redistribute it and/or modify it under the terms of either the GNU 6 | // Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | // 8 | // This program is distributed in the hope that it will be useful, 9 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | // GNU General Public License for more details. 12 | // 13 | //************************************************************************* 14 | /// \file 15 | /// \brief Verilog::Preproc: Error handling implementation 16 | /// 17 | /// Authors: Wilson Snyder 18 | /// 19 | /// Code available from: https://www.veripool.org/verilog-perl 20 | /// 21 | //************************************************************************* 22 | 23 | #include 24 | #include 25 | 26 | #include "VFileLine.h" 27 | 28 | int VFileLine::s_numErrors = 0; ///< Number of errors detected 29 | 30 | //============================================================================ 31 | 32 | void VFileLine::init(const string& filename, int lineno) { 33 | m_filename = filename; 34 | m_lineno = lineno; 35 | } 36 | 37 | const string VFileLine::filebasename() const { 38 | string name = filename(); 39 | string::size_type slash; 40 | if ((slash = name.rfind("/")) != string::npos) { 41 | name.erase(0,slash+1); 42 | } 43 | return name; 44 | } 45 | 46 | void VFileLine::fatal(const string& msg) { 47 | error(msg); 48 | error("Fatal Error detected"); 49 | abort(); 50 | } 51 | void VFileLine::error(const string& msg) { 52 | VFileLine::s_numErrors++; 53 | if (msg[msg.length()-1] != '\n') { 54 | fprintf(stderr, "%%Error: %s", msg.c_str()); 55 | } else { 56 | fprintf(stderr, "%%Error: %s\n", msg.c_str()); // Append newline, as user omitted it. 57 | } 58 | } 59 | 60 | const char* VFileLine::itoa(int i) { 61 | static char buf[100]; 62 | sprintf(buf,"%d",i); 63 | return buf; 64 | } 65 | 66 | string VFileLine::lineDirectiveStrg(int enterExit) const { 67 | char numbuf[20]; sprintf(numbuf, "%d", lineno()); 68 | char levelbuf[20]; sprintf(levelbuf, "%d", enterExit); 69 | return ((string)"`line "+numbuf+" \""+filename()+"\" "+levelbuf+"\n"); 70 | } 71 | 72 | VFileLine* VFileLine::lineDirective(const char* textp, int& enterExitRef) { 73 | // Handle `line directive 74 | // Skip `line 75 | while (*textp && isspace(*textp)) textp++; 76 | while (*textp && !isspace(*textp)) textp++; 77 | while (*textp && (isspace(*textp) || *textp=='"')) textp++; 78 | 79 | // Grab linenumber 80 | int lineno = this->lineno(); 81 | const char *ln = textp; 82 | while (*textp && !isspace(*textp)) textp++; 83 | if (isdigit(*ln)) { 84 | lineno = atoi(ln); 85 | } 86 | while (*textp && (isspace(*textp) || *textp=='"')) textp++; 87 | 88 | // Grab filename 89 | string filename = this->filename(); 90 | const char* fn = textp; 91 | while (*textp && !(isspace(*textp) || *textp=='"')) textp++; 92 | if (textp != fn) { 93 | string strfn = fn; 94 | strfn = strfn.substr(0, textp-fn); 95 | filename = strfn; 96 | } 97 | 98 | // Grab level 99 | while (*textp && (isspace(*textp) || *textp=='"')) textp++; 100 | if (isdigit(*textp)) enterExitRef = atoi(textp); 101 | else enterExitRef = 0; 102 | 103 | return create(filename,lineno); 104 | } 105 | 106 | //====================================================================== 107 | // Global scope 108 | 109 | ostream& operator<<(ostream& os, VFileLine* flp) { 110 | if (flp->filename()!="") { 111 | os <filename()<<":"<lineno()<<": "< 26 | #include 27 | #include 28 | using namespace std; 29 | 30 | //============================================================================ 31 | // VFileLine 32 | /// User information and error reporting functions 33 | //// 34 | /// Users can override this class to implement their own error handling 35 | 36 | class VFileLine { 37 | private: 38 | int m_lineno; ///< Line number in file 39 | string m_filename; ///< File name 40 | static int s_numErrors; ///< Number of errors detected 41 | 42 | protected: 43 | VFileLine(int called_only_for_default) {init("",0);} 44 | 45 | public: 46 | // CONSTRUCTORS 47 | /// Create a new fileline, for a new file and/or line number. 48 | /// Member functions, so that if a user provides another class, a change in the 49 | /// filename/linenumber will create a new element using the derived class. 50 | virtual VFileLine* create(const string& filename, int lineno) = 0; 51 | /// Create with same filename, new line number; just calls create(fn,ln) 52 | virtual VFileLine* create(int lineno) { return create(filename(), lineno); } 53 | virtual void init(const string& filename, int lineno); 54 | virtual ~VFileLine() {} 55 | // ACCESSORS 56 | int lineno() const { return m_lineno; } ///< Return line number 57 | void linenoIncInPlace() { m_lineno++; } ///< Increment line IN PLACE; normally use create() instead 58 | const string filename() const { return m_filename; } ///< Return filename 59 | const string filebasename() const; ///< Filename with any directory stripped 60 | string lineDirectiveStrg(int enter_exit_level) const; 61 | // METHODS 62 | virtual void fatal(const string& msg); ///< Report a fatal error at given location 63 | virtual void error(const string& msg); ///< Report a error at given location 64 | VFileLine* lineDirective(const char* textp, int& enterExitRef); 65 | // STATIC METHODS 66 | static int numErrors() { return s_numErrors; } ///< Return total errors detected 67 | 68 | // Internal methods -- special use 69 | static const char* itoa(int i); ///< Internal: Not reentrant! - for fatalSrc() only 70 | }; 71 | ostream& operator<<(ostream& os, VFileLine* fileline); 72 | 73 | /// Use this instead of fatal() to mention the source code line. 74 | #define fatalSrc(msg) fatal((string)"Internal Error: "+__FILE__+":"+VFileLine::itoa(__LINE__)+": "+(msg)) 75 | 76 | template< class T> std::string cvtToStr(const T& t) { 77 | ostringstream os; os< 27 | #include 28 | #include 29 | using namespace std; 30 | #include "VFileLine.h" 31 | 32 | /// Generic opaque pointer to VPreProcImp implementation class. 33 | struct VPreProcOpaque { 34 | virtual ~VPreProcOpaque() {} 35 | }; 36 | class VDefine; 37 | 38 | //********************************************************************** 39 | // VPreProc 40 | /// Verilog Preprocessor. 41 | //// 42 | /// This defines a preprocessor. Functions are virtual so users can override them. 43 | /// After creating, call openFile(), then getline() in a loop. The class will to the rest... 44 | 45 | class VPreProc { 46 | public: 47 | VPreProc(); 48 | void configure(VFileLine* filelinep); 49 | virtual ~VPreProc(); 50 | 51 | // STATE 52 | private: 53 | int m_keepComments; 54 | int m_keepWhitespace; 55 | bool m_lineDirectives; 56 | bool m_pedantic; 57 | bool m_synthesis; 58 | 59 | public: 60 | // CONSTANTS 61 | enum MiscConsts { 62 | DEFINE_RECURSION_LEVEL_MAX = 1000, // How many `def substitutions before an error 63 | INCLUDE_DEPTH_MAX = 500, // How many `includes deep before an error 64 | STREAM_DEPTH_LEVEL_MAX = 2000, // How many streams deep (sometimes `def deep) before an error 65 | // // Set more than DEFINE_RECURSION_LEVEL_MAX or INCLUDE_DEPTH_MAX 66 | NEWLINES_VS_TICKLINE = 20 // Use `line in place of this many newlines 67 | }; 68 | 69 | // ACCESSORS 70 | /// Insert given file into this point in input stream 71 | void openFile(string filename, VFileLine* filelinep=NULL); 72 | void debug(int level); ///< Set debugging level 73 | string getall(size_t approx_chunk); ///< Return all lines, or at least approx_chunk bytes. (Null if done.) 74 | string getline(); ///< Return next line/lines. (Null if done.) 75 | bool isEof(); ///< Return true on EOF. 76 | void insertUnreadback(string text); 77 | 78 | VFileLine* fileline(); ///< File/Line number for last getline call 79 | 80 | // The default behavior is to pass all unknown `defines right through. 81 | // This lets the user determine how to report the errors. It also nicely 82 | // allows `celldefine and such to remain in the output stream. 83 | 84 | // CONTROL METHODS 85 | // These options control how the parsing proceeds 86 | int keepComments() { return m_keepComments; } 87 | void keepComments(int flag) { m_keepComments=flag; } // Return comments, 0=no, 1=yes, 2=callback 88 | int keepWhitespace() { return m_keepWhitespace; } 89 | void keepWhitespace(int flag) { m_keepWhitespace=flag; } // Return extra whitespace 90 | bool lineDirectives() { return m_lineDirectives; } 91 | void lineDirectives(bool flag) { m_lineDirectives=flag; } // Insert `line directives 92 | bool pedantic() { return m_pedantic; } 93 | void pedantic(bool flag) { m_pedantic=flag; } // Obey standard; Don't substitute `error 94 | bool synthesis() { return m_synthesis; } 95 | void synthesis(bool flag) { m_synthesis=flag; } // Ignore translate off 96 | 97 | // CALLBACK METHODS 98 | // This probably will want to be overridden for given child users of this class. 99 | virtual void comment(string cmt) = 0; ///< Comment detected (if keepComments==2) 100 | virtual void include(string filename) = 0; ///< Request a include file be processed 101 | virtual void define(string name, string value, string params) = 0; ///< `define without any parameters 102 | virtual void undef(string name) = 0; ///< Remove a definition 103 | virtual void undefineall() = 0; ///< Remove all non-command-line definitions 104 | virtual bool defExists(string name) = 0; ///< Return true if define exists 105 | virtual string defParams(string name) = 0; ///< Return parameter list if define exists 106 | virtual string defValue(string name) = 0; ///< Return value of given define (should exist) 107 | virtual string defSubstitute(string substitute) = 0; ///< Return value to substitute for given post-parameter value 108 | 109 | // UTILITIES 110 | void error(string msg) { fileline()->error(msg); } ///< Report a error 111 | void fatal(string msg) { fileline()->fatal(msg); } ///< Report a fatal error 112 | 113 | private: 114 | VPreProcOpaque* m_opaquep; ///< Pointer to parser's implementation data. 115 | }; 116 | 117 | #endif // Guard 118 | -------------------------------------------------------------------------------- /Preproc/flexfix: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | ###################################################################### 3 | # 4 | # Copyright 2002-2024 by Wilson Snyder. This program is free software; you 5 | # can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License 7 | # Version 2.0. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | ###################################################################### 15 | 16 | # DESCRIPTION: Edits flex output to get around various broken flex issues. 17 | 18 | my $Opt_Prefix = $ARGV[0] or die "%Error: No prefix specified,"; 19 | 20 | foreach my $line () { 21 | # Fix flex 2.6.0 warning 22 | $line =~ s/ number_to_move == YY_MORE_ADJ / (int)number_to_move == (int)YY_MORE_ADJ /; 23 | # Fix flex 2.5.4 namespace omission 24 | $line =~ s/^class istream;/\#include \nusing namespace std;\n/; 25 | # Fix flex 2.5.31 redefinition 26 | $line =~ s!(\#define\s+yyFlexLexer\s+yyFlexLexer)!//flexfix: $1!g; 27 | # Fix flex 2.5.1 yytext_ptr undef 28 | $line =~ s!(\#undef\s+yytext_ptr)!//flexfix: $1!g; 29 | # Fix flex 2.5.4 and GCC 4.1.0 warn_unused_result 30 | $line =~ s!\(void\) *fwrite\((.*)\)!if (fwrite($1)) {}!g; 31 | # Fix flex 2.5.33 and GCC 4.1.2 "warning: comparison between signed and unsigned integer expressions" in YY_INPUT 32 | $line =~ s!for \( n = 0; n < max_size && !for ( n = 0; ((size_t)n < (size_t)max_size) && !g; 33 | # Fix flex 2.5.4 and GCC 4.0.2 under FLEX_DEBUG 34 | $line =~ s!--accepting rule at line %d !--accepting rule at line %ld !g; 35 | # Fix compiler warning filenames 36 | $line =~ s!(#line \d+ ".*)_pretmp!$1!; 37 | 38 | print "$line"; 39 | } 40 | -------------------------------------------------------------------------------- /Preproc/typemap: -------------------------------------------------------------------------------- 1 | TYPEMAP 2 | const char * T_PV 3 | VPreProcXs * O_CTHIS 4 | 5 | 6 | OUTPUT 7 | # The variable is stored into a pre-blessed $self->{_cthis} 8 | O_CTHIS 9 | // SELF->{_cthis} = THIS 10 | if( sv_isobject(SELF) && (SvTYPE(SvRV(SELF)) == SVt_PVHV) ) { 11 | SV **svp = hv_fetch((HV*)SvRV(SELF), \"_cthis\", 6, 1); 12 | sv_setiv(*svp, PTR2IV( $var )); 13 | XSRETURN_UNDEF; 14 | } else { 15 | warn( \"${Package}::$func_name() -- $var is not a Verilog::Preproc object\" ); 16 | XSRETURN_UNDEF; 17 | } 18 | 19 | INPUT 20 | O_CTHIS 21 | $var = NULL; 22 | if( sv_isobject($arg) && (SvTYPE(SvRV( $arg )) == SVt_PVHV) ) { 23 | SV **svp = hv_fetch((HV*)SvRV(( $arg )), \"_cthis\", 6, 0); 24 | $var = NULL; 25 | if (svp) { $var = INT2PTR($type,SvIV( *svp )); } 26 | } 27 | if (!$var || !dynamic_cast($var)) { 28 | warn( \"${Package}::$func_name() -- $var is not a Verilog::Preproc object\" ); 29 | XSRETURN_UNDEF; 30 | } 31 | -------------------------------------------------------------------------------- /Preproc/xsubppfix: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # 3 | # Copyright 2008-2024 by Wilson Snyder. This program is free software; 4 | # you can redistribute it and/or modify it under the terms of either the GNU 5 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 6 | # 7 | ###################################################################### 8 | 9 | # DESCRIPTION: Edits xsubpp output to get around various issues. 10 | 11 | foreach my $line () { 12 | # Fix xsubpp 1.9508 and GCC 4.2.1 warning 13 | # "warning: deprecated conversion from string constant to ‘char*’" 14 | $line =~ s/^(\s*)(?:const\s*|)char\*\s*file\s*=\s*__FILE__;/${1}char* file = (char*)__FILE__;/; 15 | if ($line =~ /newXSproto/) { 16 | $line =~ s/([(,]\s*)"/$1(char*)"/g; 17 | } 18 | # 19 | print "$line"; 20 | } 21 | -------------------------------------------------------------------------------- /Std.pm: -------------------------------------------------------------------------------- 1 | # See copyright, etc in below POD section. 2 | ###################################################################### 3 | 4 | package Verilog::Std; 5 | use Config; 6 | use IO::File; 7 | use File::Path; 8 | use Verilog::Language; 9 | use Carp; 10 | use strict; 11 | 12 | use vars qw($VERSION); 13 | 14 | ###################################################################### 15 | #### Configuration Section 16 | 17 | $VERSION = '3.483'; 18 | 19 | ####################################################################### 20 | # It's a PITRA to have pure datafiles get installed properly, so we have 21 | # the std text here in this package. 22 | 23 | our $_Std_Text = <}) 107 | 108 | Return the definition of the std package. Optionally pass the language 109 | standard, defaulting to what Verilog::Language::language_standard returns if 110 | unspecified. 111 | 112 | =back 113 | 114 | =head1 DISTRIBUTION 115 | 116 | Verilog-Perl is part of the L free Verilog EDA 117 | software tool suite. The latest version is available from CPAN and from 118 | L. 119 | 120 | Copyright 2009-2024 by Wilson Snyder. This package is free software; you 121 | can redistribute it and/or modify it under the terms of either the GNU 122 | Lesser General Public License Version 3 or the Perl Artistic License 123 | Version 2.0. 124 | 125 | =head1 AUTHORS 126 | 127 | Wilson Snyder 128 | 129 | =head1 SEE ALSO 130 | 131 | L 132 | 133 | =cut 134 | 135 | ###################################################################### 136 | -------------------------------------------------------------------------------- /t/00_pod.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test; 10 | 11 | eval "use Test::Pod 1.00"; 12 | if ($@) { 13 | print "1..1\n"; 14 | print "ok 1 # skip Test::Pod not installed so ignoring Pod check (harmless)"; 15 | } else { 16 | all_pod_files_ok(); 17 | } 18 | -------------------------------------------------------------------------------- /t/01_manifest.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2007-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test; 10 | 11 | BEGIN { plan tests => 1 } 12 | 13 | if (!$ENV{VERILATOR_AUTHOR_SITE}) { 14 | skip("author only test (harmless)",1); 15 | } else { 16 | eval { use ExtUtils::Manifest; }; 17 | $ExtUtils::Manifest::Quiet = 1; 18 | 19 | my ($missing, $extra) = ExtUtils::Manifest::fullcheck(); 20 | my $bad; 21 | foreach my $file (@{$missing}) { 22 | next if $file eq "README"; 23 | warn "%Warning: MANIFEST listed file not found: $file\n"; 24 | $bad = 1; 25 | } 26 | foreach my $file (@{$extra}) { 27 | warn "%Warning: MANIFEST maybe missing: $file\n"; 28 | $bad = 1; 29 | } 30 | ok (!$bad); 31 | } 32 | -------------------------------------------------------------------------------- /t/02_help.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2007-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { require "./t/test_utils.pl"; } 12 | my @execs = glob ("blib/script/[a-z]*"); 13 | plan tests => (3 * ($#execs+1)); 14 | 15 | foreach my $exe (@execs) { 16 | print "Doc test of: $exe\n"; 17 | ok (-e $exe, "exe exists: $exe"); 18 | SKIP: { 19 | skip("vsplitmodule is only example (harmless)",2) 20 | if ($exe =~ /vsplitmodule/); 21 | 22 | my $cmd = "$PERL $exe --help 2>&1"; 23 | my $help = `$cmd`; 24 | like ($help, qr/--version/, "help result for: $cmd"); 25 | 26 | $cmd = "$PERL $exe --version 2>&1"; 27 | $help = `$cmd`; 28 | like ($help, qr/Version.*[0-9]/, "version result for: $cmd"); 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /t/03_spaces.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2007-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test; 10 | 11 | BEGIN { require "./t/test_utils.pl"; } 12 | eval { use ExtUtils::Manifest; }; 13 | my $manifest = ExtUtils::Manifest::maniread(); 14 | plan tests => (1 + (keys %{$manifest})); 15 | ok(1); 16 | 17 | foreach my $filename (sort keys %{$manifest}) { 18 | if (!$ENV{VERILATOR_AUTHOR_SITE}) { 19 | skip("author only test (harmless)",1); 20 | next; 21 | } 22 | if ($filename =~ /README/) { # May not even exist 23 | skip("File doesn't need check (harmless)",1); 24 | next; 25 | } 26 | print "Space test of: $filename\n"; 27 | my $wholefile = wholefile($filename); 28 | if ($wholefile 29 | && $wholefile !~ /[ \t]+\n/ 30 | && $wholefile !~ /^[ \t]*[ ]+\t/) { 31 | ok(1); 32 | } elsif ($filename =~ m!\.out! 33 | || $filename =~ m!/gen/!) { 34 | skip("File doesn't need check (harmless)",1); 35 | } else { 36 | warn "%Error: $filename: Bad indentation\n"; 37 | ok(0); 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /t/04_critic.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test; 10 | use warnings; 11 | 12 | if (!$ENV{VERILATOR_AUTHOR_SITE} || $ENV{HARNESS_NO_CRITIC}) { 13 | plan tests => 1; 14 | skip("author only test (harmless)",1); 15 | } else { 16 | eval "use Test::Perl::Critic;"; 17 | if ($@) { 18 | plan tests => 1; 19 | skip("Test::Perl::Critic not installed so ignoring check (harmless)",1); 20 | } else { 21 | #-profile => "t/04_critic.rc" 22 | Test::Perl::Critic->import( -verbose=>9, 23 | -exclude=>['ProhibitExplicitReturnUndef', 24 | 'ProhibitNoStrict', 25 | 'ProhibitStringyEval'], 26 | ); 27 | all_critic_ok(); 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /t/05_yaml.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2010-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test; 10 | use warnings; 11 | 12 | if (!$ENV{VERILATOR_AUTHOR_SITE}) { 13 | plan tests => 1; 14 | skip("author only test (harmless)",1); 15 | } else { 16 | eval "use Test::YAML::Meta;"; 17 | if ($@) { 18 | plan tests => 1; 19 | skip("Test::YAML::Meta not installed so ignoring check (harmless)",1); 20 | } else { 21 | meta_yaml_ok(); 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /t/10_keywords.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 27 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | use Verilog::Language; 15 | ok(1); 16 | 17 | ok (Verilog::Language::is_keyword("input")); 18 | ok (!Verilog::Language::is_keyword("not_input")); 19 | ok (Verilog::Language::is_compdirect("`define")); 20 | 21 | is (Verilog::Language::language_standard(), '1800-2023'); 22 | is (Verilog::Language::language_standard('1800-2023'), '1800-2023'); 23 | is (Verilog::Language::language_standard('1800-2017'), '1800-2017'); 24 | is (Verilog::Language::language_standard('1800-2012'), '1800-2012'); 25 | is (Verilog::Language::language_standard('1800-2009'), '1800-2009'); 26 | ok (Verilog::Language::is_keyword("checker")); 27 | is (Verilog::Language::language_standard('1800-2005'), '1800-2005'); 28 | ok (!Verilog::Language::is_keyword("checker")); 29 | ok (Verilog::Language::is_keyword("do")); 30 | is (Verilog::Language::language_standard('1364-2005'), '1364-2005'); 31 | ok (Verilog::Language::is_keyword("uwire")); 32 | is (Verilog::Language::language_standard(2001), '1364-2001'); 33 | ok (!Verilog::Language::is_keyword("uwire")); 34 | ok (Verilog::Language::is_keyword("generate")); 35 | is (Verilog::Language::language_standard(1995), '1364-1995'); 36 | ok (!Verilog::Language::is_keyword("generate")); 37 | 38 | is (Verilog::Language::language_maximum(), '1800-2023', 'language_maximum'); 39 | 40 | is (Verilog::Language::strip_comments("he/**/l/**/lo"), "hello"); 41 | is (Verilog::Language::strip_comments("he//xx/*\nllo"), "he\nllo"); 42 | is (Verilog::Language::strip_comments("he/*xx//..*/llo"), "hello"); 43 | is (Verilog::Language::strip_comments("he\"//llo\""), "he\"//llo\""); 44 | 45 | ok ( Verilog::Language::is_gateprim("buf")); 46 | ok (!Verilog::Language::is_gateprim("else")); 47 | -------------------------------------------------------------------------------- /t/12_splitbus.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 5 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | use Verilog::Language; 15 | ok(1, "use"); 16 | 17 | array_ck (['none', 18 | ], 19 | Verilog::Language::split_bus 20 | ("none")); 21 | 22 | array_ck (['ff[1]', 23 | 'ff[2]', 24 | ], 25 | Verilog::Language::split_bus 26 | ("ff[1:2]")); 27 | 28 | array_ck (['ff[5]e', 29 | 'ff[3]e', 30 | 'ff[1]e', 31 | 'ff[4]e', 32 | ], 33 | Verilog::Language::split_bus 34 | ("ff[5:1:2,4]e")); 35 | 36 | array_ck (['ff[3] bar [10] end', 37 | 'ff[2] bar [9] end', 38 | 'ff[1] bar [8] end', 39 | 'ff[3] bar [7] end', 40 | 'ff[2] bar [6] end', 41 | 'ff[1] bar [5] end', 42 | 'ff[3] bar [4] end', 43 | 'ff[2] bar [3] end', 44 | ], 45 | Verilog::Language::split_bus 46 | ("ff[3:1] bar [4'ha:3] end")); 47 | 48 | sub array_ck { 49 | my $checkref = shift; 50 | my @got = @_; 51 | is_deeply(\@got, $checkref); 52 | } 53 | -------------------------------------------------------------------------------- /t/14_numbers.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 32 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | use Verilog::Language; 15 | ok(1, "use"); 16 | 17 | is (Verilog::Language::number_value("5'h13"), 19); 18 | is (Verilog::Language::number_value("5'd13"), 13); 19 | is (Verilog::Language::number_value("5'o13"), 11); 20 | is (Verilog::Language::number_value("5'B11"), 3); 21 | is (Verilog::Language::number_value("5 'B 11"), 3); 22 | is (Verilog::Language::number_value("'b10"), 2); 23 | is (Verilog::Language::number_value("2'sb10"), 2); 24 | is (Verilog::Language::number_bits("8'b10"), 8); 25 | is (Verilog::Language::number_bits("8 'b 10"), 8); 26 | is (Verilog::Language::number_signed("8 'sb 1"), 1); 27 | ok (!defined Verilog::Language::number_bits("'b10")); 28 | 29 | print " Bit::Vector\n"; 30 | eval "use Bit::Vector"; 31 | SKIP: { 32 | if ($@) { 33 | skip("Bit::Vector not installed (harmless)",5*2); 34 | } 35 | try_bitvector("5823", 32, "000016bf"); 36 | try_bitvector("80'h47cb_40d7_b50f_0147_1a85", 80, "47cb40d7b50f01471a85"); 37 | try_bitvector("83'o227525534413441101057616251", 83, "097aad721721208bf1ca9"); 38 | try_bitvector("70'b1011010111111001010111111111111001110000011000101110010100110101101101", 70, "2d7e57ff9c18b94d6d"); 39 | try_bitvector("90'd46548__4046747316__6145438700", 90, "003d9b368496d10ab0043ec"); 40 | } 41 | 42 | print " Math::BigInt\n"; 43 | eval "use Math::BigInts"; 44 | SKIP: { 45 | if ($@) { 46 | skip("Math::BigInt not installed (harmless)",5*2); 47 | } 48 | try_bigint("5823", 4, "0x16bf"); 49 | try_bigint("80'h47cb_40d7_b50f_0147_1a85", 24, "0x47cb40d7b50f01471a85"); 50 | try_bigint("83'o227525534413441101057616251", 24, "0x97aad721721208bf1ca9"); 51 | try_bigint("70'b1011010111111001010111111111111001110000011000101110010100110101101101", 21, "0x2d7e57ff9c18b94d6d"); 52 | try_bigint("90'd46548__4046747316__6145438700", 25, "0x3d9b368496d10ab0043ec"); 53 | } 54 | 55 | 56 | sub try_bitvector { 57 | my $text = shift; 58 | my $expbits = shift; 59 | my $expvalue = shift; 60 | 61 | my $got = Verilog::Language::number_bitvector($text); 62 | my $gotbits = $got->Size; 63 | my $gotvalue = lc $got->to_Hex; 64 | print " $text -> got $gotbits $gotvalue =? exp $expbits exp $expvalue\n"; 65 | is ($gotbits, $expbits, "number of bits"); 66 | is ($gotvalue, $expvalue, "value"); 67 | } 68 | 69 | sub try_bigint { 70 | my $text = shift; 71 | my $expbits = shift; 72 | my $expvalue = shift; 73 | 74 | my $got = Verilog::Language::number_bigint($text); 75 | my $gotbits = $got->length; 76 | my $gotvalue = lc $got->as_hex; 77 | print " $text -> got $gotbits $gotvalue =? exp $expbits exp $expvalue\n"; 78 | is ($gotbits, $expbits, "number of bits"); 79 | is ($gotvalue, $expvalue, "value"); 80 | } 81 | -------------------------------------------------------------------------------- /t/16_std.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2009-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 3 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | use Verilog::Std; 15 | ok(1, "use"); 16 | 17 | like (Verilog::Std::std(), qr/endpackage/); 18 | 19 | # Make sure data sticks around 20 | like (Verilog::Std::std(), qr/endpackage/); 21 | -------------------------------------------------------------------------------- /t/20_getopt.opt: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Perl ExtUtils: Option file for testing Verilog::Getopt 2 | 3 | -Dread_opt_file=1 4 | -y y_library_path 5 | -------------------------------------------------------------------------------- /t/20_getopt.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | use Cwd; 11 | 12 | BEGIN { plan tests => 15 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | use Verilog::Getopt; 16 | ok(1, "use"); 17 | 18 | $Verilog::Getopt::Debug = 1; 19 | 20 | my $opt = new Verilog::Getopt; 21 | ok(1, "new"); 22 | 23 | $ENV{DOT} = "."; 24 | is($opt->file_substitute('Fred/$DOT/$NOT_SET_IN_ENV/$DOT'), 'Fred/./$NOT_SET_IN_ENV/.'); 25 | 26 | my @param = qw ( +libext+t 27 | +incdir+t 28 | +define+foo=bar 29 | +define+foo2 30 | +define+foo3=3+foo4 31 | -v libdir 32 | -y moddir 33 | -Dbaz=bar 34 | -Iincdir2 35 | -f $DOT/t/20_getopt.opt 36 | -F $DOT/t/20_getopt.opt 37 | passthru 38 | ); 39 | 40 | my @left = $opt->parameter(@param); 41 | print join(" ",@left),"\n"; 42 | is ($#left, 0); # passthru 43 | 44 | ok ($opt->defvalue('read_opt_file')); 45 | 46 | my $fp = $opt->file_path('20_getopt.t'); 47 | print "fp $fp\n"; 48 | ok (($fp eq (Cwd::abs_path("t")."/20_getopt.t")) 49 | || ($fp eq "t/20_getopt.t")); 50 | 51 | my @out = $opt->get_parameters(); 52 | print "OUT: ",(join(" ",@out)),"\n"; 53 | is ($#out, 19); 54 | 55 | { 56 | my $opt2 = new Verilog::Getopt (); 57 | my @left2 = $opt2->parameter(@out); 58 | print "LEFT: ",join(" ",@left2),"\n"; 59 | my @out2 = $opt->get_parameters(); 60 | print "LEFT: ",join(" ",@out2),"\n"; 61 | is_deeply(\@out2, [qw(+define+baz=bar +define+foo=bar +define+foo2 62 | +define+foo3=3 +define+foo4 63 | +define+read_opt_file=1 64 | +libext+.v+t +incdir+. +incdir+t +incdir+incdir2 65 | -y . -y moddir -y y_library_path -y t/y_library_path -v libdir)]); 66 | } 67 | 68 | { 69 | my $opt2 = new Verilog::Getopt (gcc_style=>1, vcs_style=>0); 70 | my @left2 = $opt2->parameter(@param); 71 | print "LEFT: ",join(" ",@left2),"\n"; 72 | is_deeply(\@left2, [qw(+libext+t +incdir+t +define+foo=bar +define+foo2 73 | +define+foo3=3+foo4 74 | -v libdir -y moddir -y y_library_path -y y_library_path passthru)]); 75 | } 76 | 77 | { 78 | my $opt2 = new Verilog::Getopt (gcc_style=>0, vcs_style=>1); 79 | my @left2 = $opt2->parameter(@param); 80 | print "LEFT: ",join(" ",@left2),"\n"; 81 | is_deeply(\@left2, [qw(-Dbaz=bar -Iincdir2 -Dread_opt_file=1 -Dread_opt_file=1 passthru)]); 82 | } 83 | 84 | { 85 | my $opt2 = new Verilog::Getopt (gcc_style=>0, vcs_style=>1); 86 | { 87 | local $SIG{__WARN__} = sub {}, 88 | my @left2 = $opt2->parameter("+define+foo=bar", "+define+foo=baz"); 89 | } 90 | my @out2 = $opt2->get_parameters(); 91 | is_deeply($out2[0], qw(+define+foo=baz)); 92 | } 93 | 94 | $opt->map_directories(sub{s![a-z]!x!; $_}); 95 | ok(1); 96 | 97 | ok($opt->file_skip_special(".svn")); 98 | ok(!$opt->file_skip_special("svn")); 99 | ok($opt->file_skip_special("foo/bar/baz/CVS")); 100 | -------------------------------------------------------------------------------- /t/30_preproc.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 1+6*3 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | ####################################################################### 16 | package MyPreproc; 17 | use Verilog::Preproc; 18 | use base qw(Verilog::Preproc); 19 | 20 | sub comment { print $::OUTTO $_[0]->filename,":",$_[0]->lineno,": COMMENT: $_[1]\n"; 21 | $_[0]->unreadback(' /*CMT*/ '); } 22 | 23 | sub def_substitute { 24 | my ($self,$out) = @_; 25 | # Only do this for some tests, as it makes the output look strange 26 | if ($self->{_test_def_substitute} 27 | && $out !~ /^".*"$/ # And don't corrupt `include test 28 | && $out !~ /\.v/ # Nor things that look like filenames 29 | && $out !~ /NODS/){ 30 | return "DS_".$out; # Must use _ as need identifier character 31 | } else { 32 | return $out; 33 | } 34 | } 35 | 36 | package main; 37 | ####################################################################### 38 | 39 | sub prep { 40 | my $opt = new Verilog::Getopt; 41 | $opt->parameter (qw( 42 | +incdir+verilog 43 | +define+PREDEF_COMMAND_LINE 44 | )); 45 | return $opt; 46 | } 47 | 48 | use Verilog::Getopt; 49 | ok(1, "use Verilog::Getopt"); 50 | 51 | use Verilog::Preproc; 52 | ok(1, "use Verilog::Preproc"); 53 | 54 | test ('', keep_comments=>1, line_directives=>0, _no_line_numbering=>1); # Makes "diff" cleaner 55 | test ('_on', keep_comments=>1,); 56 | test ('_syn', keep_comments=>1, keep_whitespace=>1, synthesis=>1); 57 | test ('_nows', keep_comments=>0, keep_whitespace=>0, synthesis=>1); 58 | test ('_sub', keep_comments=>'sub', _test_def_substitute=>1); 59 | test_getall (); 60 | 61 | sub test { 62 | my $id = shift; 63 | my @args = @_; 64 | 65 | my $opt = prep(); 66 | my $pp = new MyPreproc (options=>$opt, @args); 67 | ok(1, "new${id}"); 68 | #$pp->debug(9); 69 | $pp->open("inc1.v"); 70 | $pp->open("inc2.v"); 71 | $pp->open("inc_ifdef.v"); 72 | $pp->open("inc_nonl.v"); 73 | $pp->open("inc_def09.v"); 74 | 75 | my $fhout = IO::File->new(">test_dir/inc${id}.out"); 76 | $::OUTTO = $fhout; 77 | while (defined(my $line = $pp->getline())) { 78 | if ($pp->{_no_line_numbering}) { 79 | print $fhout $pp->filename.": ".$line; 80 | } else { 81 | print $fhout $pp->filename.":".$pp->lineno.": ".$line; 82 | } 83 | } 84 | $fhout->close(); 85 | ok(1, "parsed${id}"); 86 | 87 | ok(files_identical("test_dir/inc${id}.out", "t/30_preproc${id}.out"), "diff${id}"); 88 | } 89 | 90 | sub test_getall { 91 | my $id = shift; 92 | my @args = @_; 93 | 94 | my $a; 95 | my $acalls = 0; 96 | { 97 | my $pp = new MyPreproc (options=>prep(), @args); 98 | $pp->open("inc1.v"); 99 | while (defined(my $line = $pp->getline)) { 100 | $a .= $line; 101 | $acalls++; 102 | } 103 | } 104 | my $b; 105 | my $bcalls = 0; 106 | { 107 | my $pp = new MyPreproc (options=>prep(), @args); 108 | $pp->open("inc1.v"); 109 | while (defined(my $all = $pp->getall)) { 110 | $b .= $all; 111 | $bcalls++; 112 | } 113 | } 114 | 115 | is($a, $b); 116 | ok($acalls > $bcalls, "getall does same callbacks"); 117 | } 118 | 119 | -------------------------------------------------------------------------------- /t/32_noinc.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 7 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | ####################################################################### 16 | 17 | use Verilog::Getopt; 18 | use Verilog::Preproc; 19 | ok(1, "use"); 20 | 21 | # Check we get error 22 | eval { 23 | check(); 24 | }; 25 | like ($@, qr/32_noinc.v:\d+: Cannot open notfound/); 26 | check(include_open_nonfatal=>1); 27 | ok (1); 28 | 29 | # Check no error 30 | 31 | sub check { 32 | my @opts = (@_); 33 | 34 | my $opt = new Verilog::Getopt; 35 | 36 | my $pp = new Verilog::Preproc (options=>$opt, 37 | @opts); 38 | ok(1, "new"); 39 | 40 | #$pp->debug(9); 41 | $pp->open("t/32_noinc.v"); 42 | ok(1, "open"); 43 | 44 | while (defined(my $line = $pp->getline())) { 45 | #print "LINE: $line"; 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /t/32_noinc.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2007-2012 by Wilson Snyder. 4 | 5 | text. 6 | 7 | `include "notfound" 8 | -------------------------------------------------------------------------------- /t/33_gzip.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 4 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | ####################################################################### 16 | 17 | use Verilog::Getopt; 18 | use Verilog::Preproc; 19 | ok(1, "use"); 20 | 21 | # Check we get error 22 | SKIP: { 23 | if (`which gzip` !~ m!^/! 24 | || `which gunzip` !~ m!^/!) { 25 | skip("no gzip installed (harmless)",3); 26 | } 27 | system("gzip t/32_noinc.v -c > test_dir/33_gzip.v.gz"); 28 | ok (-r "test_dir/33_gzip.v.gz", "gzip test creation"); 29 | 30 | my $opt = new Verilog::Getopt; 31 | my $pp = new Verilog::Preproc (options=>$opt, 32 | include_open_nonfatal=>1,); 33 | $pp->open("test_dir/33_gzip.v.gz"); 34 | ok(1, "open"); 35 | 36 | my $hit; 37 | while (defined(my $line = $pp->getline())) { 38 | #print "TEXT $line"; 39 | $hit = 1 if $line =~ /text/; 40 | } 41 | ok ($hit, "decompress found text"); 42 | } 43 | -------------------------------------------------------------------------------- /t/34_parser.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | use Data::Dumper; $Data::Dumper::Indent = 1; #Debug 11 | 12 | BEGIN { plan tests => 7 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | our %_TestCoverage; 16 | 17 | ###################################################################### 18 | 19 | package MyParser; 20 | use Verilog::Parser; 21 | use strict; 22 | use base qw(Verilog::Parser); 23 | 24 | BEGIN { 25 | # Make functions like this: 26 | # sub attribute { $_[0]->_common('attribute', @_); } 27 | foreach my $cb (Verilog::Parser::callback_names()) { 28 | my $func = ' sub __CB__ { $_[0]->_common("__CB__", @_); } '; 29 | $func =~ s/__CB__/$cb/g; 30 | eval($func); 31 | } 32 | } 33 | 34 | sub _common { 35 | my $self = shift; 36 | my $what = shift; 37 | my $call_self = shift; 38 | my @args = @_; 39 | my $urb = $self->unreadback; 40 | 41 | $_TestCoverage{$what}++; 42 | my $args=""; 43 | foreach (@args) { $args .= defined $_ ? " '$_'" : " undef"; } 44 | if ($urb && $urb ne '') { 45 | $self->{dump_fh}->printf("%s:%03d: unreadback '%s'\n", 46 | $self->filename, $self->lineno, 47 | $urb); 48 | $self->unreadback(''); 49 | } 50 | $self->{dump_fh}->printf("%s:%03d: %s%s\n", 51 | $self->filename, $self->lineno, 52 | uc $what, $args); 53 | } 54 | 55 | ###################################################################### 56 | 57 | package main; 58 | 59 | use Verilog::Parser; 60 | use Verilog::Preproc; 61 | ok(1, "use"); 62 | 63 | # Use our class and dump to a file 64 | my $dump_fh = new IO::File(">test_dir/34.dmp") or die "%Error: $! test_dir/34.dmp,"; 65 | 66 | my $p = new Verilog::Parser; 67 | ok($p, "new"); 68 | $p->selftest(); 69 | ok(1, "selftest"); 70 | 71 | $p->lineno(100); 72 | $p->filename("XXX"); 73 | is($p->lineno, 100); 74 | 75 | read_test("verilog/v_hier_subprim.v", $dump_fh); 76 | read_test("verilog/v_hier_sub.v", $dump_fh); 77 | read_test("verilog/example.v", $dump_fh); 78 | ok(1); 79 | $dump_fh->close(); 80 | 81 | # Did we read the right stuff? 82 | ok(files_identical("test_dir/34.dmp", "t/34_parser.out"), "diff"); 83 | 84 | # Did we cover everything? 85 | my $err; 86 | foreach my $cb (Verilog::Parser::callback_names()) { 87 | if (!$_TestCoverage{$cb}) { 88 | $err=1; 89 | warn "%Warning: No test coverage for callback: $cb\n"; 90 | } 91 | } 92 | ok (!$err, "coverage"); 93 | 94 | ###################################################################### 95 | 96 | sub read_test { 97 | my $filename = shift; 98 | my $dump_fh = shift; 99 | 100 | my $pp = Verilog::Preproc->new(keep_comments=>0,); 101 | 102 | my $parser = new MyParser (dump_fh => $dump_fh); 103 | 104 | # Preprocess 105 | $pp->open($filename); 106 | $parser->parse_preproc_file($pp); 107 | } 108 | -------------------------------------------------------------------------------- /t/35_sigparser.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | use Data::Dumper; $Data::Dumper::Indent = 1; 11 | 12 | BEGIN { plan tests => 6 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | our %_TestCoverage; 16 | our %_TestCallbacks; 17 | 18 | ###################################################################### 19 | 20 | package MyParser; 21 | use Verilog::SigParser; 22 | use strict; 23 | use base qw(Verilog::SigParser); 24 | 25 | BEGIN { 26 | # Make functions like this: 27 | # sub attribute { $_[0]->_common('module', @_); } 28 | foreach my $cb (Verilog::SigParser::callback_names(), 29 | 'comment') { 30 | $_TestCallbacks{$cb} = 1; 31 | my $func = ' sub __CB__ { $_[0]->_common("__CB__", @_); } '; 32 | $func =~ s/__CB__/$cb/g; 33 | eval($func); 34 | } 35 | } 36 | 37 | sub _serialize { 38 | my $in = shift; 39 | if (ref($in)) { 40 | my $dd = Data::Dumper->new([$in], [qw(in)]); 41 | $dd->Reset->Indent(0)->Terse(1)->Sortkeys(1); 42 | return $dd->Dump; 43 | } else { 44 | return $in; 45 | } 46 | } 47 | 48 | sub _common { 49 | my $self = shift; 50 | my $what = shift; 51 | my $call_self = shift; 52 | my @args = @_; 53 | 54 | $_TestCoverage{$what}++; 55 | my $args=""; 56 | foreach (@args) { 57 | if (defined $_) { 58 | $args .= " \'"._serialize($_)."\'"; 59 | } else { 60 | $args .= " undef"; 61 | } 62 | } 63 | $self->{dump_fh}->printf("%s:%03d: %s %s\n", 64 | $self->filename, $self->lineno, 65 | uc $what, 66 | $args); 67 | } 68 | 69 | sub error { 70 | my ($self,$text,$token)=@_; 71 | my $fileline = $self->filename.":".$self->lineno; 72 | warn ("%Warning: $fileline: $text\n"); 73 | } 74 | 75 | ###################################################################### 76 | 77 | package main; 78 | 79 | use Verilog::SigParser; 80 | use Verilog::Preproc; 81 | ok(1, "use"); 82 | 83 | read_tests("test_dir/35.dmp", 84 | []); 85 | ok(1, "read"); 86 | # Did we read the right stuff? 87 | ok(files_identical("test_dir/35.dmp", "t/35_sigparser.out"), "diff"); 88 | 89 | read_tests("test_dir/35_ps.dmp", 90 | [use_pinselects => 1]); 91 | ok(1, "read-pinselects"); 92 | # Did we read the right stuff? 93 | ok(files_identical("test_dir/35_ps.dmp", "t/35_sigparser_ps.out"), "diff"); 94 | 95 | # Did we cover everything? 96 | my $err; 97 | foreach my $cb (sort keys %_TestCallbacks) { 98 | if (!$_TestCoverage{$cb}) { 99 | $err=1; 100 | warn "%Warning: No test coverage for callback: $cb\n"; 101 | } 102 | } 103 | ok (!$err, "coverage"); 104 | 105 | 106 | ###################################################################### 107 | 108 | # Use our class and dump to a file 109 | sub read_tests { 110 | my $dump_filename = shift; 111 | my $option_ref = shift; 112 | 113 | my $dump_fh = new IO::File($dump_filename,"w") 114 | or die "%Error: $! $dump_filename,"; 115 | read_test($dump_fh, $option_ref, "/dev/null"); # Empty files should be ok 116 | read_test($dump_fh, $option_ref, "verilog/v_hier_subprim.v"); 117 | read_test($dump_fh, $option_ref, "verilog/v_hier_sub.v"); 118 | read_test($dump_fh, $option_ref, "verilog/parser_bugs.v"); 119 | read_test($dump_fh, $option_ref, "verilog/pinorder.v"); 120 | read_test($dump_fh, $option_ref, "verilog/parser_sv.v"); 121 | read_test($dump_fh, $option_ref, "verilog/parser_sv09.v"); 122 | read_test($dump_fh, $option_ref, "verilog/parser_sv17.v"); 123 | read_test($dump_fh, $option_ref, "verilog/parser_vectors.v"); 124 | $dump_fh->close(); 125 | } 126 | 127 | sub read_test { 128 | my $dump_fh = shift; 129 | my $option_ref = shift; 130 | my $filename = shift; 131 | 132 | my $pp = Verilog::Preproc->new(keep_comments=>1,); 133 | 134 | my $parser = new MyParser (dump_fh => $dump_fh, 135 | metacomment=>{synopsys=>1}, 136 | @$option_ref); 137 | 138 | if ($ENV{VERILOG_TEST_DEBUG}) { # For example, VERILOG_TEST_DEBUG=9 139 | $parser->debug($ENV{VERILOG_TEST_DEBUG}); 140 | } 141 | 142 | # Preprocess 143 | $pp->open($filename); 144 | $parser->parse_preproc_file($pp); 145 | 146 | print Dumper($parser->{symbol_table}) if ($parser->debug()); 147 | } 148 | -------------------------------------------------------------------------------- /t/36_sigmany.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | ###################################################################### 8 | # VERILOG_TEST_FILES="$V4/test_regress/t/t_case*.v" VERILOG_TEST_DEBUGIF=1 t/36_sigmany.t 9 | # (delete-matching-lines "^#\\|^ok \\|^1\\.\\.\\|^not ok") 10 | 11 | use strict; 12 | use Test; # Not Test::More due to skip usage 13 | use Data::Dumper; $Data::Dumper::Indent = 1; 14 | 15 | BEGIN { plan tests => 3 } 16 | BEGIN { require "./t/test_utils.pl"; } 17 | 18 | our $Any_Error; 19 | our $Got_Eof_Module; 20 | 21 | ###################################################################### 22 | 23 | package MyParser; 24 | use Verilog::SigParser; 25 | use strict; 26 | use base qw(Verilog::SigParser); 27 | 28 | sub module { 29 | my ($self,$kwd,$name)=@_; 30 | $Got_Eof_Module = 1 if $name eq '_GOT_EOF_MODULE'; 31 | } 32 | 33 | sub error { 34 | my ($self,$text,$token)=@_; 35 | my $fileline = $self->filename.":".$self->lineno; 36 | if ($text !~ /\`math/) { 37 | if (!$ENV{VERILOG_TEST_SILENT}) { 38 | warn ("%Warning: $fileline: $text\n"); 39 | $self->{_errored} = 1; 40 | $::Any_Error = 1; 41 | } else { 42 | warn ("-Silent-Warning: $fileline: $text\n"); 43 | } 44 | # Try to print source line 45 | if (my $fh=IO::File->new("<".$self->filename)) { 46 | my @lines = $fh->getlines; 47 | my $line = $lines[$self->lineno-1] || ""; 48 | $line =~ s/^\s+//; 49 | warn ("\t".$line) if $line; 50 | $fh->close(); 51 | } 52 | } 53 | } 54 | 55 | ###################################################################### 56 | 57 | package main; 58 | 59 | use Verilog::SigParser; 60 | use Verilog::Preproc; 61 | use Verilog::Getopt; 62 | ok(1); 63 | 64 | my @files; 65 | if ($ENV{VERILOG_TEST_FILES}) { 66 | ok(1); 67 | @files = split(/:/,$ENV{VERILOG_TEST_FILES}); 68 | @files = map {glob $_} @files; 69 | } 70 | else { 71 | skip("VERILOG_TEST_FILES not set (harmless)",1); 72 | # export VERILOG_TEST_FILES="$V4/test_regress/t/t_case*.v" 73 | @files = glob("verilog/*.v"); 74 | @files = grep {!m!/inc!} @files; 75 | } 76 | check_series(@files); 77 | 78 | ###################################################################### 79 | 80 | sub check_series { 81 | my @files = @_; 82 | $Any_Error = 0; 83 | foreach my $file (@files) { 84 | read_test($file); 85 | } 86 | ok(!$Any_Error); 87 | } 88 | 89 | sub read_test { 90 | my $filename = shift; 91 | my $parser = one_parse($filename, 0); 92 | if ($ENV{VERILOG_TEST_DEBUGIF} && $parser->{_errored}) { 93 | print "======== REPARSING w/debug\n"; 94 | one_parse($filename, 9); 95 | } 96 | } 97 | 98 | sub one_parse { 99 | my $filename = shift; 100 | my $debug = shift; 101 | 102 | $Got_Eof_Module = undef; 103 | 104 | print "="x70,"\n"; 105 | print "read $filename\n"; 106 | my $opt = new Verilog::Getopt; 107 | # Used to do this so we can read pre-vpassert'ed files, 108 | # but now we require a `include std_defines in all sources 109 | # even though a lint run may not indicate it's needed 110 | # (since lint runs pre-vpassert.) 111 | # $opt->define('__message_on',"1'b0"); 112 | if ($filename =~ m!(.*)/!) { 113 | # Allow includes in same dir as the test 114 | my $fdir = $1; 115 | $opt->incdir($fdir); 116 | $opt->module_dir ($fdir); 117 | } 118 | 119 | my $pp = Verilog::Preproc->new(keep_comments=>0, 120 | include_open_nonfatal=>0, 121 | options=>$opt); 122 | 123 | my $parser = new MyParser(); 124 | # Suck in std:: before enabling debug dumps 125 | $parser->std; 126 | 127 | $parser->debug($debug || $ENV{VERILOG_TEST_DEBUG}); 128 | $pp->open($filename); 129 | if ($ENV{VERILOG_TEST_KEYWORDS}) { 130 | $parser->parse("`begin_keywords \"1364-2001\" "); 131 | } 132 | $parser->reset; 133 | # Similar to $parser->parse_preproc_file($pp); 134 | # but we want to stuff a module before the EOF 135 | while (defined(my $line = $pp->getline())) { 136 | $parser->parse ($line); 137 | } 138 | $parser->parse("module _GOT_EOF_MODULE; endmodule\n"); 139 | $parser->eof; 140 | 141 | if (!$Any_Error && !$Got_Eof_Module) { 142 | warn "%Warning: $filename: Never parsed fake module at EOF\n"; 143 | $parser->{_errored} = 1; 144 | $::Any_Error = 1; 145 | } 146 | 147 | print Dumper($parser->{symbol_table}) if $parser->debug; 148 | 149 | return $parser; 150 | } 151 | -------------------------------------------------------------------------------- /t/40_netlist.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 17 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | #$Verilog::Netlist::Debug = 1; 15 | use Verilog::Netlist; 16 | ok(1, "use"); 17 | 18 | ##*** See also 41_example.t 19 | 20 | # Setup options so files can be found 21 | use Verilog::Getopt; 22 | my $opt = new Verilog::Getopt; 23 | $opt->parameter( "+incdir+verilog", 24 | "-y","verilog", 25 | ); 26 | 27 | # Prepare netlist 28 | my $nl = new Verilog::Netlist (options => $opt, 29 | keep_comments => 1, 30 | link_read_nonfatal=>1, 31 | ); 32 | foreach my $file ('verilog/v_hier_top.v', 33 | 'verilog/v_hier_top2.v', 34 | 'verilog/v_sv_mod.v' 35 | ) { 36 | $nl->read_file (filename=>$file); 37 | } 38 | # Read in any sub-modules 39 | $nl->link(); 40 | $nl->lint(); # Optional, see docs; probably not wanted 41 | $nl->exit_if_error(); 42 | 43 | print "Level tests\n"; 44 | is($nl->find_module("v_hier_top")->level, 3); 45 | is($nl->find_module("v_hier_sub")->level, 2); 46 | is($nl->find_module("v_hier_subsub")->level, 1); 47 | 48 | my @mods = map {$_->name} $nl->modules_sorted_level; 49 | is_deeply (\@mods, ['$root', 50 | 'v_hier_noport', 51 | 'v_hier_subsub', 52 | 'v_sv_pgm', 53 | 'v_hier_sub', 54 | 'v_hier_top2', 55 | 'v_recursive', 56 | 'v_hier_top', 57 | 'v_sv_mod']); 58 | 59 | # Width checks 60 | { 61 | my $mod = $nl->find_module("v_hier_top"); 62 | is (_width_of($mod,"WC_w1"), 1); 63 | is (_width_of($mod,"WC_w1b"), 1); 64 | is (_width_of($mod,"WC_w3"), 3); 65 | is (_width_of($mod,"WC_w4"), 4); 66 | is (_width_of($mod,"WC_p32"), 32); 67 | is (_width_of($mod,"WC_p1"), 1); 68 | is (_width_of($mod,"WC_p3"), 3); 69 | is (_width_of($mod,"WC_p4"), 4); 70 | is (_width_of($mod,"WC_pint"), 32); 71 | } 72 | 73 | # Port accessors 74 | { 75 | my $mod = $nl->find_module("v_hier_sub"); 76 | 77 | my @o = $mod->ports_sorted; 78 | ok ($#o == 2 && $o[0]->name eq 'avec'); 79 | 80 | @o = $mod->ports_ordered; 81 | ok ($#o == 2 && $o[0]->name eq 'clk'); 82 | } 83 | 84 | ok(1); 85 | 86 | sub _width_of { 87 | my $mod = shift; 88 | my $name = shift; 89 | if (!$mod) { 90 | warn "%Warning: No module found,"; 91 | return; 92 | } 93 | my $sig = $mod->find_net($name); 94 | if (!$sig) { 95 | warn "%Warning: No signal '$name' found,"; 96 | return; 97 | } 98 | return $sig->width; 99 | } 100 | -------------------------------------------------------------------------------- /t/41_example.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 3 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | #$Verilog::Netlist::Debug = 1; 15 | use Verilog::Netlist; 16 | ok(1, "use"); 17 | { 18 | local *STDOUT; 19 | open(STDOUT, ">", "test_dir/41_example.dmp"); 20 | 21 | print "Checking example in Netlist.pm\n"; 22 | 23 | use Verilog::Netlist; 24 | 25 | # Setup options so files can be found 26 | use Verilog::Getopt; 27 | my $opt = new Verilog::Getopt; 28 | $opt->parameter( "+incdir+verilog", 29 | "-y","verilog", 30 | ); 31 | 32 | # Prepare netlist 33 | my $nl = new Verilog::Netlist(options => $opt, 34 | link_read_nonfatal=>1, 35 | ); 36 | foreach my $file ('verilog/v_hier_top.v', 'verilog/v_hier_top2.v') { 37 | $nl->read_file(filename=>$file); 38 | } 39 | # Read in any sub-modules 40 | $nl->link(); 41 | #$nl->lint(); # Optional, see docs; probably not wanted 42 | $nl->exit_if_error(); 43 | 44 | my %recursing; # Prevent recursion; not in example 45 | foreach my $mod ($nl->top_modules_sorted) { 46 | show_hier($mod, " ", "", ""); 47 | } 48 | 49 | sub show_hier { 50 | my $mod = shift; 51 | my $indent = shift; 52 | my $hier = shift; 53 | my $cellname = shift; 54 | return if $recursing{$mod->name}++; # Not in example 55 | if (!$cellname) {$hier = $mod->name;} #top modules get the design name 56 | else {$hier .= ".$cellname";} #append the cellname 57 | printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier); 58 | foreach my $sig ($mod->ports_sorted) { 59 | printf ($indent." %sput %s\n", $sig->direction, $sig->name); 60 | } 61 | foreach my $cell ($mod->cells_sorted) { 62 | printf ($indent. " Cell %s\n", $cell->name); 63 | foreach my $pin ($cell->pins_sorted) { 64 | printf($indent." .%s(%s)\n", $pin->name, $pin->netname); 65 | } 66 | show_hier($cell->submod, $indent." ", $hier, $cell->name) if $cell->submod; 67 | } 68 | --$recursing{$mod->name}; # Not in example 69 | } 70 | 71 | print "Dump\n"; 72 | $nl->dump; 73 | } 74 | 75 | ok(files_identical("test_dir/41_example.dmp", "t/41_example.out")); 76 | 77 | ok(1, "done"); 78 | -------------------------------------------------------------------------------- /t/42_dumpcheck.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 17 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | #$Verilog::SigParser::Debug = $Verilog::Parser::Debug = 1; 15 | use Verilog::Netlist; 16 | ok(1, "use"); 17 | 18 | check ('test_dir/42.dmp', ['verilog/v_hier_top.v', 'verilog/v_hier_top2.v', 'verilog/v_comments.v'], 19 | [link_read_nonfatal=>1, keep_comments => 1,]); 20 | ok(1); 21 | ok(files_identical("test_dir/42.dmp", "t/42_dumpcheck_1.out")); 22 | ok(files_identical("test_dir/42.dmp.v", "t/42_dumpcheck_1v.out")); 23 | 24 | check ('test_dir/42_ps.dmp', ['verilog/v_hier_top.v', 'verilog/v_hier_top2.v', 'verilog/v_comments.v'], 25 | [link_read_nonfatal=>1, keep_comments => 1, use_pinselects => 1]); 26 | ok(1); 27 | ok(files_identical("test_dir/42_ps.dmp", "t/42_dumpcheck_1_ps.out")); 28 | ok(files_identical("test_dir/42_ps.dmp.v", "t/42_dumpcheck_1v_ps.out")); 29 | 30 | my $n2 = check ('test_dir/42_n2.dmp', ['verilog/pinorder.v'], 31 | [link_read_nonfatal=>1, keep_comments => 1,]); 32 | ok(1); 33 | ok(files_identical("test_dir/42_n2.dmp", "t/42_dumpcheck_2.out")); 34 | ok(files_identical("test_dir/42_n2.dmp.v", "t/42_dumpcheck_2v.out")); 35 | 36 | check ('test_dir/42_v2k.dmp', ['verilog/v_v2k.v'], 37 | [link_read_nonfatal=>1, keep_comments => 1,]); 38 | ok(1); 39 | ok(files_identical("test_dir/42_v2k.dmp", "t/42_dumpcheck_v2k.out")); 40 | ok(files_identical("test_dir/42_v2k.dmp.v", "t/42_dumpcheck_v2kv.out")); 41 | 42 | print "Edit tests\n"; 43 | $n2->find_module("pinorder4")->find_cell("foo3")->delete; 44 | $n2->find_module("pinorder4")->find_cell("foo1")->find_pin("x")->delete; 45 | $n2->find_module("pinorder4")->find_cell("foo1")->find_pin("def")->delete; 46 | $n2->find_module("pinorder4")->find_net("IPCD_const")->delete; 47 | $n2->find_module("foo2")->delete; 48 | vwrite($n2, "test_dir/42.ed.v"); 49 | ok(1); 50 | ok(files_identical("test_dir/42.ed.v", "t/42_dumpcheck_2e.out")); 51 | 52 | check ('test_dir/42_sv.dmp', ['verilog/v_sv_mod.v'], 53 | [link_read_nonfatal=>0, keep_comments => 1,]); 54 | ok(1); 55 | ok(files_identical("test_dir/42_sv.dmp", "t/42_dumpcheck_sv.out")); 56 | 57 | sub check { 58 | my $outfilename = shift; 59 | my $files = shift; 60 | my $nl_opts = shift; 61 | # Setup options so files can be found 62 | use Verilog::Getopt; 63 | my $opt = new Verilog::Getopt; 64 | $opt->parameter( "+incdir+verilog", 65 | "-y","verilog", 66 | ); 67 | my $nl = new Verilog::Netlist (options => $opt, 68 | link_read_nonfatal=>1, 69 | keep_comments => 1, 70 | @{$nl_opts}); 71 | foreach my $file (@{$files}) { 72 | $nl->read_file (filename=>$file); 73 | } 74 | # Read in any sub-modules 75 | $nl->link(); 76 | $nl->lint(); 77 | $nl->exit_if_error(); 78 | 79 | print "Dump\n"; 80 | { 81 | open (SAVEOUT, ">&STDOUT") or die "%Error: Can't dup stdout,"; 82 | if (0) { print SAVEOUT "To prevent used only once"; } 83 | open (STDOUT, ">$outfilename") or die "%Error: $! $outfilename,"; 84 | $nl->dump; 85 | 86 | print STDOUT "#### Commentary:\n"; 87 | foreach my $mod ($nl->modules_sorted) { 88 | foreach my $net ($mod->nets_sorted) { 89 | my $cmt = $net->comment||''; 90 | $cmt =~ s/\n/\\n/g; 91 | $cmt = qq{"$cmt"}; 92 | printf STDOUT "%s:%04d: %s cmt=%s\n" 93 | , $net->filename, $net->lineno, $net->name, $cmt; 94 | } 95 | } 96 | 97 | close(STDOUT); 98 | open (STDOUT, ">&SAVEOUT"); 99 | } 100 | 101 | vwrite($nl, $outfilename.".v"); 102 | return $nl; 103 | } 104 | 105 | sub vwrite { 106 | my $nl = shift; 107 | my $filename = shift; 108 | my $fh = IO::File->new($filename,"w") or die "%Error: $! writing $filename,"; 109 | print $fh $nl->verilog_text; 110 | $fh->close; 111 | } 112 | -------------------------------------------------------------------------------- /t/42_dumpcheck_1v.out: -------------------------------------------------------------------------------- 1 | root_module $root ( 2 | ); 3 | localparam GLOBAL_PARAM = 1; // Local Variables: 4 | // eval:(verilog-read-defines) 5 | // End: 6 | endroot_module 7 | 8 | module v_bug917 ( 9 | a, b, m); 10 | input a; // a-First 11 | output b; // b-Third 12 | // Third 13 | output m; // m-Second 14 | endmodule 15 | 16 | module v_bug917p ( 17 | a, b); 18 | input a; // a-First 19 | output b; // b-Secondparen 20 | // Third 21 | endmodule 22 | 23 | module v_comments ( 24 | a, b, c, d, d1, d2, d3); 25 | input a; // comment for a 26 | inout [10:0] b; 27 | output [0:10] c; // comment for c 28 | output reg d; 29 | output [32:0] d1; 30 | output [(MATH-1):0] d2; 31 | output [32-1:0] d3; 32 | var reg [11:0] e; // Comment for e 33 | endmodule 34 | 35 | module v_hier_noport ( 36 | ); 37 | parameter P; 38 | var reg internal; 39 | endmodule 40 | 41 | module v_hier_sub ( 42 | avec, clk, qvec); 43 | parameter FROM_DEFPARAM = 1; 44 | genvar K; 45 | genvar K_UNUSED; 46 | supply1 a1; // Outputs 47 | input [3:0] avec; // Comment for v_hier_sub, avec 48 | input clk; 49 | output [3:0] qvec; /* Comment for v_hier_sub, qvec */ 50 | v_hier_subsub #(.IGNORED('sh20)) subsub0 (.a(a1), .q(qvec[0])); 51 | v_hier_subsub subsub2 (.a(1'b0), .q(qvec[2])); 52 | endmodule 53 | 54 | module v_hier_subsub ( 55 | a, q); 56 | parameter IGNORED = 0; 57 | input signed a; 58 | output q; // Test protected 59 | //" 60 | endmodule 61 | 62 | module v_hier_top ( 63 | clk); 64 | localparam [0:0] WC_p1 = 0; 65 | localparam [2:0] WC_p3 = 0; 66 | localparam WC_p32 = 0; 67 | localparam [-1:2] WC_p4 = 0; 68 | localparam integer WC_pint = 0; // Assignments 69 | wire WC_w1; 70 | wire [0:0] WC_w1b; 71 | wire [2:0] WC_w3; 72 | wire [-1:2] WC_w4; 73 | wire asn_clk; 74 | input clk; /* pragma jsc_clk */ 75 | missing missing (); 76 | v_recursive #(.DEPTH(3)) recursive (); 77 | v_hier_sub sub (.avec({avec[3],avec[2:0]}), .clk(1'b0), .qvec(qvec[3:0])); 78 | defparam sub.FROM_DEFPARAM = 2; 79 | assign asn_clk = clk; 80 | endmodule 81 | 82 | module v_hier_top2 ( 83 | clk, iosig); 84 | input clk; 85 | inout [2:0] iosig; /* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/ 86 | /* synthesis aftersemi*/ 87 | // NetListName=F12_IO 88 | v_hier_noport noport (); 89 | v_hier_noport #(.P(1)) noporta [1:0] (); 90 | v_hier_noport #(.P(1)) noportp (); 91 | endmodule 92 | 93 | module v_recursive ( 94 | ); 95 | parameter DEPTH = 1; 96 | v_recursive #(.DEPTH(DEPTH-1)) recurse (); 97 | endmodule 98 | 99 | -------------------------------------------------------------------------------- /t/42_dumpcheck_1v_ps.out: -------------------------------------------------------------------------------- 1 | root_module $root ( 2 | ); 3 | localparam GLOBAL_PARAM = 1; // Local Variables: 4 | // eval:(verilog-read-defines) 5 | // End: 6 | endroot_module 7 | 8 | module v_bug917 ( 9 | a, b, m); 10 | input a; // a-First 11 | output b; // b-Third 12 | // Third 13 | output m; // m-Second 14 | endmodule 15 | 16 | module v_bug917p ( 17 | a, b); 18 | input a; // a-First 19 | output b; // b-Secondparen 20 | // Third 21 | endmodule 22 | 23 | module v_comments ( 24 | a, b, c, d, d1, d2, d3); 25 | input a; // comment for a 26 | inout [10:0] b; 27 | output [0:10] c; // comment for c 28 | output reg d; 29 | output [32:0] d1; 30 | output [(MATH-1):0] d2; 31 | output [32-1:0] d3; 32 | var reg [11:0] e; // Comment for e 33 | endmodule 34 | 35 | module v_hier_noport ( 36 | ); 37 | parameter P; 38 | var reg internal; 39 | endmodule 40 | 41 | module v_hier_sub ( 42 | avec, clk, qvec); 43 | parameter FROM_DEFPARAM = 1; 44 | genvar K; 45 | genvar K_UNUSED; 46 | supply1 a1; // Outputs 47 | input [3:0] avec; // Comment for v_hier_sub, avec 48 | input clk; 49 | output [3:0] qvec; /* Comment for v_hier_sub, qvec */ 50 | v_hier_subsub #(.IGNORED('sh20)) subsub0 (.a(a1), .q(qvec[0])); 51 | v_hier_subsub subsub2 (.a(1'b0), .q(qvec[2])); 52 | endmodule 53 | 54 | module v_hier_subsub ( 55 | a, q); 56 | parameter IGNORED = 0; 57 | input signed a; 58 | output q; // Test protected 59 | //" 60 | endmodule 61 | 62 | module v_hier_top ( 63 | clk); 64 | localparam [0:0] WC_p1 = 0; 65 | localparam [2:0] WC_p3 = 0; 66 | localparam WC_p32 = 0; 67 | localparam [-1:2] WC_p4 = 0; 68 | localparam integer WC_pint = 0; // Assignments 69 | wire WC_w1; 70 | wire [0:0] WC_w1b; 71 | wire [2:0] WC_w3; 72 | wire [-1:2] WC_w4; 73 | wire asn_clk; 74 | input clk; /* pragma jsc_clk */ 75 | missing missing (); 76 | v_recursive #(.DEPTH(3)) recursive (); 77 | v_hier_sub sub (.avec({avec[3],avec[2:0]}), .clk(1'b0), .qvec(qvec[3:0])); 78 | defparam sub.FROM_DEFPARAM = 2; 79 | assign asn_clk = clk; 80 | endmodule 81 | 82 | module v_hier_top2 ( 83 | clk, iosig); 84 | input clk; 85 | inout [2:0] iosig; /* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/ 86 | /* synthesis aftersemi*/ 87 | // NetListName=F12_IO 88 | v_hier_noport noport (); 89 | v_hier_noport #(.P(1)) noporta [1:0] (); 90 | v_hier_noport #(.P(1)) noportp (); 91 | endmodule 92 | 93 | module v_recursive ( 94 | ); 95 | parameter DEPTH = 1; 96 | v_recursive #(.DEPTH(DEPTH-1)) recurse (); 97 | endmodule 98 | 99 | -------------------------------------------------------------------------------- /t/42_dumpcheck_2.out: -------------------------------------------------------------------------------- 1 | Module:bug278 Kwd:module File:verilog/pinorder.v 2 | Port:iow Dir:inout DataT: Array: 3 | Port:iw Dir:in DataT: Array: 4 | Port:ow Dir:out DataT: Array: 5 | Net:iow DeclT:port NetT:wire DataT: Array: 6 | Net:iw O DeclT:port NetT:wire DataT: Array: 7 | Net:ow I DeclT:port NetT:wire DataT: Array: 8 | Module:foo Kwd:module File:verilog/pinorder.v 9 | Port:abcconst Dir:in DataT:[2:0] Array: 10 | Port:def Dir:in DataT:[31:0] Array: 11 | Port:noconnect Dir:in DataT:signed [3:0] Array: 12 | Port:x Dir:in DataT: Array: 13 | Port:y Dir:in DataT: Array: 14 | Net:abcconst O DeclT:port NetT: DataT:[2:0] Array: 2:0 15 | Net:def O DeclT:port NetT: DataT:[31:0] Array: 31:0 16 | Net:noconnect O DeclT:port NetT: DataT:signed [3:0] Array: 3:0 17 | Net:x O DeclT:port NetT: DataT: Array: 18 | Net:y O DeclT:port NetT: DataT: Array: 19 | Module:foo2 Kwd:module File:verilog/pinorder.v 20 | Port:x Dir:out DataT: Array: 21 | Port:y Dir:in DataT: Array: 22 | Port:z Dir:in DataT: Array: 23 | Net:x I DeclT:port NetT: DataT:reg Array: 24 | Net:y O DeclT:port NetT: DataT: Array: 25 | Net:z O DeclT:port NetT: DataT: Array: 26 | Module:pinorder4 Kwd:module File:verilog/pinorder.v 27 | Net:IPCD_const I DeclT:net NetT:wire DataT:[31:0] Array: 31:0 Value:32'h1 28 | Net:a_i I DeclT:net NetT:wire DataT:[7:0] Array: 7:0 29 | Net:b_i IO DeclT:net NetT:wire DataT: Array: 30 | Net:d_o I DeclT:net NetT:wire DataT: Array: 31 | Cell:foo1 is-a:foo 32 | Module:foo Kwd:module File:verilog/pinorder.v 33 | Pin:abcconst Net:3'h0 34 | Port:abcconst Dir:in DataT:[2:0] Array: 35 | Pin:def Net:IPCD_const 36 | Port:def Dir:in DataT:[31:0] Array: 37 | Net:IPCD_const I DeclT:net NetT:wire DataT:[31:0] Array: 31:0 Value:32'h1 38 | Pin:noconnect Net: 39 | Port:noconnect Dir:in DataT:signed [3:0] Array: 40 | Pin:x Net:a_i 41 | Port:x Dir:in DataT: Array: 42 | Net:a_i I DeclT:net NetT:wire DataT:[7:0] Array: 7:0 43 | Pin:y Net:b_i 44 | Port:y Dir:in DataT: Array: 45 | Net:b_i IO DeclT:net NetT:wire DataT: Array: 46 | Cell:foo2 is-a:foo2 47 | Module:foo2 Kwd:module File:verilog/pinorder.v 48 | Pin:x Net:b_i 49 | Port:x Dir:out DataT: Array: 50 | Net:b_i IO DeclT:net NetT:wire DataT: Array: 51 | Pin:y Net:d_o 52 | Port:y Dir:in DataT: Array: 53 | Net:d_o I DeclT:net NetT:wire DataT: Array: 54 | Pin:z Net:a_i[0] 55 | Port:z Dir:in DataT: Array: 56 | Cell:foo3 is-a:foo 57 | Module:foo Kwd:module File:verilog/pinorder.v 58 | Pin:abcconst Net:3'h0 59 | Port:abcconst Dir:in DataT:[2:0] Array: 60 | Pin:def Net:IPCD_const 61 | Port:def Dir:in DataT:[31:0] Array: 62 | Net:IPCD_const I DeclT:net NetT:wire DataT:[31:0] Array: 31:0 Value:32'h1 63 | Pin:x Net:a_i 64 | Port:x Dir:in DataT: Array: 65 | Net:a_i I DeclT:net NetT:wire DataT:[7:0] Array: 7:0 66 | Pin:y Net:b_i 67 | Port:y Dir:in DataT: Array: 68 | Net:b_i IO DeclT:net NetT:wire DataT: Array: 69 | ContAssign:assign lhs:a_i rhs:0 70 | ContAssign:assign lhs:b_i rhs:0 71 | #### Commentary: 72 | verilog/pinorder.v:0049: iow cmt="" 73 | verilog/pinorder.v:0050: iw cmt="" 74 | verilog/pinorder.v:0048: ow cmt="" 75 | verilog/pinorder.v:0041: abcconst cmt="" 76 | verilog/pinorder.v:0043: def cmt="" 77 | verilog/pinorder.v:0042: noconnect cmt="" 78 | verilog/pinorder.v:0040: x cmt="" 79 | verilog/pinorder.v:0039: y cmt="" 80 | verilog/pinorder.v:0030: x cmt="" 81 | verilog/pinorder.v:0029: y cmt="" 82 | verilog/pinorder.v:0028: z cmt="" 83 | verilog/pinorder.v:0010: IPCD_const cmt="" 84 | verilog/pinorder.v:0009: a_i cmt="" 85 | verilog/pinorder.v:0007: b_i cmt="" 86 | verilog/pinorder.v:0008: d_o cmt="" 87 | -------------------------------------------------------------------------------- /t/42_dumpcheck_2e.out: -------------------------------------------------------------------------------- 1 | module bug278 ( 2 | iow, iw, ow); 3 | inout iow; 4 | input iw; 5 | output ow; 6 | endmodule 7 | 8 | module foo ( 9 | abcconst, def, noconnect, x, y); 10 | input [2:0] abcconst; 11 | input [31:0] def; 12 | input signed [3:0] noconnect; 13 | input x; 14 | input y; 15 | endmodule 16 | 17 | module pinorder4 ( 18 | ); 19 | wire [7:0] a_i; 20 | wire b_i; 21 | wire d_o; 22 | foo foo1 (.abcconst(3'h0), .noconnect(), .y(b_i)); 23 | foo2 foo2 (.x(b_i), .y(d_o), .z(a_i[0])); 24 | assign a_i = 0; 25 | assign b_i = 0; 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /t/42_dumpcheck_2v.out: -------------------------------------------------------------------------------- 1 | module bug278 ( 2 | iow, iw, ow); 3 | inout iow; 4 | input iw; 5 | output ow; 6 | endmodule 7 | 8 | module foo ( 9 | abcconst, def, noconnect, x, y); 10 | input [2:0] abcconst; 11 | input [31:0] def; 12 | input signed [3:0] noconnect; 13 | input x; 14 | input y; 15 | endmodule 16 | 17 | module foo2 ( 18 | x, y, z); 19 | output reg x; 20 | input y; 21 | input z; 22 | endmodule 23 | 24 | module pinorder4 ( 25 | ); 26 | wire [31:0] IPCD_const = 32'h1; 27 | wire [7:0] a_i; 28 | wire b_i; 29 | wire d_o; 30 | foo foo1 (.abcconst(3'h0), .def(IPCD_const), .noconnect(), .x(a_i), .y(b_i)); 31 | foo2 foo2 (.x(b_i), .y(d_o), .z(a_i[0])); 32 | foo foo3 (.abcconst(3'h0), .def(IPCD_const), .x(a_i), .y(b_i)); 33 | assign a_i = 0; 34 | assign b_i = 0; 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /t/42_dumpcheck_sv.out: -------------------------------------------------------------------------------- 1 | Interface:sv_if_ported File:verilog/v_sv_mod.v 2 | Port:clk Dir:in DataT: Array: 3 | Net:clk O DeclT:port NetT: DataT: Array: 4 | Interface:v_sv_intf File:verilog/v_sv_intf.v 5 | Net:byte_port DeclT:var NetT: DataT:v_sv_pkg::byte_t Array: 6 | Cell:subintf is-a:v_sv_intf2 7 | Interface:v_sv_intf2 File:verilog/v_sv_intf.v 8 | Pin:* Net:* 9 | Interface:v_sv_intf2 File:verilog/v_sv_intf.v 10 | Net:byte_port DeclT:var NetT: DataT:v_sv_pkg::byte_t Array: 11 | ModPort:Master File:verilog/v_sv_intf.v 12 | Port:addr Dir:out DataT: Array: 13 | Port:data Dir:in DataT: Array: 14 | Module:v_sv_mod Kwd:module File:verilog/v_sv_mod.v 15 | Port:clk Dir:in DataT: Array: 16 | Port:intf Dir:interface DataT:v_sv_intf Array: 17 | Net:clk IO DeclT:port NetT: DataT: Array: 18 | Net:intf DeclT:port NetT: DataT:v_sv_intf Array: 19 | Cell:if_ported is-a:sv_if_ported 20 | Interface:sv_if_ported File:verilog/v_sv_mod.v 21 | Pin:clk Net:clk 22 | Port:clk Dir:in DataT: Array: 23 | Net:clk IO DeclT:port NetT: DataT: Array: 24 | Cell:intf is-a:v_sv_intf 25 | Interface:v_sv_intf File:verilog/v_sv_intf.v 26 | Cell:pgm is-a:v_sv_pgm 27 | Module:v_sv_pgm Kwd:program File:verilog/v_sv_pgm.v 28 | Module:v_sv_pgm Kwd:program File:verilog/v_sv_pgm.v 29 | #### Commentary: 30 | verilog/v_sv_mod.v:0010: clk cmt="// Import types" 31 | verilog/v_sv_mod.v:0010: intf cmt="" 32 | -------------------------------------------------------------------------------- /t/42_dumpcheck_v2k.out: -------------------------------------------------------------------------------- 1 | Module:v_v2k Kwd:module File:verilog/v_v2k.v 2 | Port:clk Dir:in DataT: Array: 3 | Port:rst Dir:in DataT: Array: 4 | Port:sig1 Dir:in DataT:[WIDTH:0] Array: 5 | Port:sig2 Dir:out DataT:reg [WIDTH:0] Array: 6 | Net:WIDTH DeclT:parameter NetT: DataT: Array: Value:16 7 | Net:clk O DeclT:port NetT: DataT: Array: 8 | Net:netmd DeclT:net NetT:wire DataT:[1:2][3:4] Array: 1:2][3:4 9 | Net:rst O DeclT:port NetT: DataT: Array: 10 | Net:sig1 O DeclT:port NetT: DataT:[WIDTH:0] Array: WIDTH:0 11 | Net:sig2 I DeclT:port NetT: DataT:reg [WIDTH:0] Array: WIDTH:0 12 | Cell:sub is-a:v_v2k_sub 13 | Module:v_v2k_sub Kwd:module File:verilog/v_v2k.v 14 | Pin:net1 Net:netmd[1] 15 | Port:net1 Dir:in DataT:[3:4] Array: 16 | Module:v_v2k_sub Kwd:module File:verilog/v_v2k.v 17 | Port:net1 Dir:in DataT:[3:4] Array: 18 | Net:net1 O DeclT:port NetT: DataT:[3:4] Array: 3:4 19 | #### Commentary: 20 | verilog/v_v2k.v:0006: WIDTH cmt="" 21 | verilog/v_v2k.v:0007: clk cmt="" 22 | verilog/v_v2k.v:0023: netmd cmt="" 23 | verilog/v_v2k.v:0008: rst cmt="" 24 | verilog/v_v2k.v:0009: sig1 cmt="" 25 | verilog/v_v2k.v:0010: sig2 cmt="" 26 | verilog/v_v2k.v:0030: net1 cmt="" 27 | -------------------------------------------------------------------------------- /t/42_dumpcheck_v2kv.out: -------------------------------------------------------------------------------- 1 | module v_v2k ( 2 | clk, rst, sig1, sig2); 3 | parameter WIDTH = 16; 4 | input clk; 5 | wire [1:2][3:4] netmd; 6 | input rst; 7 | input [WIDTH:0] sig1; 8 | output reg [WIDTH:0] sig2; 9 | v_v2k_sub sub (.net1(netmd[1])); 10 | endmodule 11 | 12 | module v_v2k_sub ( 13 | net1); 14 | input [3:4] net1; 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /t/43_storable.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | BEGIN { require "./t/test_utils.pl"; } 9 | 10 | use strict; 11 | use Test; 12 | use warnings; 13 | 14 | $SIG{__WARN__} = sub {}; 15 | 16 | eval "use Storable;"; 17 | if ($@) { 18 | plan tests => 1; 19 | skip("Storable not installed so ignoring check (harmless)",1); 20 | } else { 21 | plan tests => 4; 22 | eval "use Verilog::Netlist;"; 23 | ok(1); 24 | if (1) { 25 | my $nl = new Verilog::Netlist; 26 | $nl->read_file(filename=>"verilog/v_hier_subsub.v"); 27 | ok(1); 28 | Storable::store($nl, "test_dir/netlist.db"); 29 | ok(1); 30 | } 31 | if (1) { 32 | my $nl = retrieve("test_dir/netlist.db"); 33 | ok(1); 34 | } 35 | } 36 | -------------------------------------------------------------------------------- /t/44_create.out: -------------------------------------------------------------------------------- 1 | module a ( 2 | x, y); 3 | input [2:0] x; 4 | output [2:0] y; 5 | b i_b (.w(y[2:0]), .z(x)); 6 | endmodule 7 | 8 | -------------------------------------------------------------------------------- /t/44_create.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 3 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | #$Verilog::Netlist::Debug = 1; 15 | use Verilog::Netlist; 16 | use Verilog::Getopt; 17 | ok(1, "use"); 18 | { 19 | my $opt = new Verilog::Getopt; 20 | $opt->parameter( "+incdir+verilog", 21 | "-y","verilog", 22 | ); 23 | 24 | # Prepare netlist 25 | my $nl = new Verilog::Netlist (options => $opt, 26 | link_read_nonfatal=>1, 27 | ); 28 | 29 | my @fl = (filename=>'44_create.t', lineno=>0); 30 | 31 | my $moda = $nl->new_module (name=>'a', @fl); 32 | { 33 | my $x = $moda->new_port (name=>'x', @fl, direction=>'input', data_type=>'[2:0]',); 34 | my $y = $moda->new_port (name=>'y', @fl, direction=>'output', data_type=>'[2:0]',); 35 | my $b = $moda->new_cell (name=>'i_b', submodname=>'b', @fl); 36 | { 37 | $b->new_pin(name=>'z', portname=>'z', pinnamed=>1, netname=>'x', @fl); 38 | $b->new_pin(name=>'w', portname=>'w', pinnamed=>1, pinselects=>[{netname=>'y', msb=>2, lsb=>0}], @fl); 39 | } 40 | } 41 | 42 | $nl->link; 43 | my $fh = IO::File->new('test_dir/44_create.dmp', "w") or die "%Error: $! creating dump file,"; 44 | print $fh $nl->verilog_text; 45 | $fh->close; 46 | ok(files_identical("test_dir/44_create.dmp", "t/44_create.out")); 47 | } 48 | 49 | ok(1, "done"); 50 | -------------------------------------------------------------------------------- /t/46_link.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 2 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | #$Verilog::Netlist::Debug = 1; 15 | use Verilog::Netlist; 16 | use Verilog::Getopt; 17 | ok(1, "use"); 18 | { 19 | # Setup options so files can be found 20 | my $opt = new Verilog::Getopt; 21 | $opt->parameter( "+incdir+verilog", 22 | "-y","verilog", 23 | ); 24 | 25 | # Prepare netlist 26 | my $nl = new Verilog::Netlist (options => $opt, 27 | ); 28 | foreach my $file ('verilog/v_gate.v') { 29 | $nl->read_file (filename=>$file); 30 | } 31 | # Read in any sub-modules 32 | $nl->read_libraries(); 33 | $nl->link(); 34 | $nl->lint(); 35 | $nl->exit_if_error(); 36 | 37 | print "Dump\n"; 38 | $nl->dump; 39 | } 40 | 41 | ok(1, "done"); 42 | -------------------------------------------------------------------------------- /t/48_leak.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test; # Test::More leaks itself! 10 | use Data::Dumper; $Data::Dumper::Indent = 1; 11 | BEGIN { eval "use Devel::Leak;"; } # Optional 12 | 13 | BEGIN { plan tests => 2 } 14 | BEGIN { require "./t/test_utils.pl"; } 15 | 16 | use Verilog::SigParser; 17 | use Verilog::Preproc; 18 | use Verilog::Getopt; 19 | use Verilog::Netlist; 20 | use POSIX qw(); 21 | 22 | ###################################################################### 23 | 24 | my $mem = get_memory_usage(); 25 | my $loops = 50; # At least 10 26 | my $mem_end; my $mem_mid; 27 | my $handle; 28 | for (my $i=0; $i<$loops; $i++) { 29 | test(); 30 | my $newmem = get_memory_usage(); 31 | my $delta = $newmem - $mem; 32 | printf "$i: Memory %6.3f MB Alloced %6.3f MB\n" 33 | , $newmem/1024/1024, $delta/1024/1024 if $delta; 34 | $mem_mid = $newmem if $i==int($loops/2)-1; 35 | $mem_end = $newmem if $i==$loops-1; 36 | 37 | # The Devel checks must complete before $mem_mid is sampled, as they use memory 38 | if (0 && $Devel::Leak::VERSION) { 39 | Devel::Leak::NoteSV($handle) if $i==int($loops/2)-4; 40 | Devel::Leak::CheckSV($handle) if $i==int($loops/2)-3; 41 | #warn "EXITING" if $i==int($loops/2)-3; 42 | #POSIX::_exit(10) if $i==int($loops/2)-3; 43 | } 44 | 45 | $mem = $newmem; 46 | } 47 | ok(1); 48 | if ($mem == 0) { 49 | skip("get_memory_usage isn't supported",1); 50 | } elsif ($mem_end <= $mem_mid) { 51 | ok(1); 52 | } else { 53 | warn "%Warning: Leaked ",int(($mem_end-$mem_mid)/($loops/2))," bytes per parse\n"; 54 | if (!$ENV{VERILATOR_AUTHOR_SITE} || $ENV{HARNESS_FAST}) { 55 | # It's somewhat sensitive unless there's a lot of loops, 56 | # and lots of loops is too slow for users to deal with. 57 | skip("leaked, but author only test",1); 58 | } else { 59 | ok(0); 60 | } 61 | } 62 | 63 | ###################################################################### 64 | 65 | sub test { 66 | read_test("verilog/v_hier_sub.v"); 67 | read_test("verilog/parser_bugs.v"); 68 | read_test("verilog/pinorder.v"); 69 | read_test("verilog/parser_sv.v"); 70 | } 71 | 72 | sub read_test { 73 | my $filename = shift; 74 | 75 | my $go = Verilog::Getopt->new(); 76 | my $pp = Verilog::Preproc->new(keep_comments=>1); 77 | my $parser = Verilog::SigParser->new(); 78 | #my $parser = Verilog::Parser->new(); 79 | $pp->open($filename); 80 | ##Preproc_Only_Test: while (defined($pp->getline())) {} 81 | 82 | $parser->parse_preproc_file($pp); 83 | 84 | my $nl = Verilog::Netlist->new(); 85 | $nl->read_file(filename=>"verilog/v_hier_sub.v"); 86 | $nl->delete; 87 | #print Dumper($nl); use Devel::Peek; print "\nPEEK: \n";Dump(\$nl); 88 | } 89 | -------------------------------------------------------------------------------- /t/49_largeish.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | use Time::HiRes qw(gettimeofday tv_interval); 11 | use Data::Dumper; $Data::Dumper::Indent = 1; 12 | 13 | BEGIN { plan tests => 4 } 14 | BEGIN { require "./t/test_utils.pl"; } 15 | 16 | use Verilog::SigParser; 17 | use Verilog::Preproc; 18 | use Verilog::Getopt; 19 | use Verilog::Netlist; 20 | use POSIX qw(); 21 | 22 | ###################################################################### 23 | 24 | our $nets = 10*1000; 25 | our $Opt_Sym_Size = 30; 26 | our $Opt_Spaced_Out = 0; # Lots of stuff that preprocessor can rip out 27 | our $Opt_Dir = $ENV{HARNESS_TEST_DIR}||"test_dir"; # Move to scratch disk for very large tests 28 | 29 | prep("${Opt_Dir}/largeish_1.v",1); 30 | prep("${Opt_Dir}/largeish_2.v",1+($nets/10)); 31 | prep("${Opt_Dir}/largeish_3.v",1+$nets); 32 | 33 | per_net_test('sigparser', 100000); 34 | per_net_test('netlist', 100000); 35 | 36 | unlink(glob("${Opt_Dir}/largeish_*")); # Fat, so don't keep around 37 | 38 | ###################################################################### 39 | 40 | sub prep { 41 | my $filename = shift; 42 | my $count = shift; 43 | 44 | my $fh = IO::File->new(">$filename"); 45 | print $fh "module largeish;\n"; 46 | my $wirefmt = " wire n%0".($Opt_Sym_Size-1)."d;\n"; # Each net is constant sized 47 | for (my $i=0; $i<$count; $i++) { 48 | printf $fh $wirefmt, $i; 49 | print $fh " "x1023,"\n" if $Opt_Spaced_Out; 50 | } 51 | print $fh "endmodule\n"; 52 | 53 | printf "Wrote $filename: %6.3f MB\n", (-s $filename)/1024/1024; 54 | } 55 | 56 | sub per_net_test { 57 | my $pack = shift; 58 | my $limit = shift; 59 | 60 | my (@mem, @time, @size, @names, @secPerB); 61 | $names[1] = "${Opt_Dir}/largeish_1.v"; 62 | $names[2] = "${Opt_Dir}/largeish_2.v"; 63 | $names[3] = "${Opt_Dir}/largeish_3.v"; 64 | 65 | $mem[0] = get_memory_usage(); 66 | $time[0] = [gettimeofday]; 67 | 68 | for (my $i=1; $i<4; $i++) { 69 | read_test($pack, $names[$i]); 70 | $size[$i] = -s $names[$i]; 71 | $mem[$i] = get_memory_usage(); 72 | $time[$i] = [gettimeofday]; 73 | } 74 | 75 | for (my $i=2; $i<4; $i++) { 76 | my $deltamem = $mem[$i]-$mem[0]; 77 | my $deltatime = tv_interval($time[$i-1],$time[$i]); 78 | my $mpn = $deltamem / $size[$i]; 79 | $secPerB[$i] = $deltatime / ($size[$i]/1024/1024); 80 | printf "For $pack $names[$i]: File %1.3f MB, %1.3f s, %1.3f MB, Alloced %1.3f MB, %1.1f Alloc/FileB %1.1f s/MB\n" 81 | , $size[$i]/1024/1024, $deltatime, $mem[$i]/1024/1024, $deltamem/1024/1024, $mpn, $secPerB[$i]; 82 | } 83 | 84 | ok(1, "run complete"); 85 | 86 | my $slope = $secPerB[3] / ($secPerB[2]||1); 87 | SKIP: { 88 | if ($slope > 0.5 && $slope < 2) { 89 | ok(1, "complexity"); 90 | } else { 91 | if (!$ENV{VERILATOR_AUTHOR_SITE} || $ENV{HARNESS_FAST}) { 92 | # It's somewhat sensitive unless there's a lot of loops, 93 | # and lots of loops is too slow for users to deal with. 94 | skip("waived, author only test",1); 95 | } else { 96 | warn "%Warning: ",$slope," non O(n) based on input file size, slope=$slope\n"; 97 | ok(0, "complexity"); 98 | } 99 | } 100 | } 101 | } 102 | 103 | sub read_test { 104 | my $pack = shift; 105 | my $filename = shift; 106 | 107 | if ($pack eq 'sigparser') { 108 | my $go = Verilog::Getopt->new(); 109 | my $pp = Verilog::Preproc->new(keep_comments=>1); 110 | my $parser = Verilog::SigParser->new(); 111 | #my $parser = Verilog::Parser->new(); 112 | #$pp->debug(99); 113 | $pp->open($filename); 114 | ##Preproc_Only_Test: while (defined($pp->getline())) {} 115 | $parser->parse_preproc_file($pp); 116 | 117 | $pp->open($filename); 118 | while (defined($pp->getline())) {} 119 | 120 | } 121 | elsif ($pack eq 'netlist') { 122 | my $nl = Verilog::Netlist->new(); 123 | $nl->read_file(filename=>$filename); 124 | $nl->delete; 125 | } 126 | else { die; } 127 | } 128 | -------------------------------------------------------------------------------- /t/50_vrename.out: -------------------------------------------------------------------------------- 1 | # Generated by vrename on Thu Jul 5 09:01:51 2007 2 | # 3 | # Files read for this analysis: 4 | vfile "verilog/test.v" 5 | # 6 | # Original Signal Name Name to change to 7 | # -------------------- ----------------- 8 | # 9 | sigren "a" "a" #verilog/test.v 10 | sigren "b" "b" #verilog/test.v 11 | sigren "example" "example" #verilog/test.v 12 | sigren "result" "result" #verilog/test.v 13 | sigren "z" "z" #verilog/test.v 14 | # 15 | # Use M-x compile in emacs to automatically perform the changes: 16 | ## Local Variables: *** 17 | ## compile-command: "./vrename -change verilog/test.v " *** 18 | ## End: *** 19 | -------------------------------------------------------------------------------- /t/50_vrename.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 6 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | print "Checking vrename...\n"; 15 | { 16 | # -List 17 | my $changefile = "test_dir/signals.vrename"; 18 | unlink $changefile; 19 | my $cmd = "${PERL} ./vrename -changefile=$changefile -list -xref verilog/test.v"; 20 | run_system ($cmd); 21 | ok(1, "vrename list"); 22 | ok(files_identical($changefile, "t/50_vrename.out"), "diff"); 23 | unlink $changefile; 24 | } 25 | { 26 | # Try renaming 27 | mkdir 'test_dir/verilog', 0777; 28 | my $cmd = ("${PERL} ./vrename -change --changefile verilog/test.vrename" 29 | ." -o test_dir verilog/test.v"); 30 | run_system ($cmd); 31 | ok(1, "vrename change"); 32 | ok(-r 'test_dir/verilog/test.v', "diff"); 33 | } 34 | 35 | { 36 | # Crypt 37 | my $changefile = "test_dir/signals.vrename"; 38 | my $cmd = ("${PERL} ./vrename -changefile=$changefile -list --crypt" 39 | ." -o test_dir verilog/test.v"); 40 | run_system ($cmd); 41 | $cmd = ("${PERL} ./vrename -changefile=$changefile -change --crypt" 42 | ." -o test_dir verilog/test.v"); 43 | run_system ($cmd); 44 | ok(1, "vrename crypt"); 45 | ok(-r 'test_dir/verilog/test.v', "output exists"); 46 | } 47 | -------------------------------------------------------------------------------- /t/51_vrename_kwd.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 6 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | print "Checking vrename...\n"; 15 | my $changefile = "test_dir/51_vrename_kwd_list.vrename"; 16 | { 17 | # -List 18 | my $cmd = "${PERL} ./vrename -changefile=$changefile -list --changelang --language 1364-1995 t/51_vrename_kwd.v"; 19 | run_system ($cmd); 20 | ok(1, "vrename list"); 21 | ok(files_identical($changefile, "t/51_vrename_kwd_list.out"), "diff"); 22 | } 23 | 24 | { 25 | # Try renaming - no change 26 | mkdir 'test_dir/t', 0777; 27 | my $cmd = ("${PERL} ./vrename -change --changefile=$changefile" 28 | ." -o test_dir t/51_vrename_kwd.v"); 29 | run_system ($cmd); 30 | ok(1, "vrename change same"); 31 | ok(files_identical("test_dir/t/51_vrename_kwd.v", "t/51_vrename_kwd_chg.out"), "diff"); 32 | } 33 | 34 | { 35 | # Try renaming - with change 36 | mkdir 'test_dir/t', 0777; 37 | my $cmd = ("${PERL} ./vrename -change --changefile=t/51_vrename_kwd_chg2.vrename" 38 | ." -o test_dir t/51_vrename_kwd.v"); 39 | run_system ($cmd); 40 | ok(1, "vrename change"); 41 | ok(files_identical("test_dir/t/51_vrename_kwd.v", "t/51_vrename_kwd_chg2.out"), "diff"); 42 | } 43 | -------------------------------------------------------------------------------- /t/51_vrename_kwd.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2010-2012 by Wilson Snyder. 4 | 5 | module 51_vrename_kwd; 6 | // Keyword 7 | wire do; 8 | wire \do ; 9 | // Non escapes 10 | wire non_2non; 11 | wire non_2non_nospace 12 | ; 13 | wire non_2ext; 14 | wire non_2ext_nospace 15 | ; 16 | wire non_2esc; 17 | wire non_2esc_nospace 18 | ; 19 | // Extra unnecessary escapes 20 | // Note we cannot legally remove spaces if replacing with non-escaped name 21 | wire \ext_2non ; 22 | wire \ext_2non_nospace 23 | ; 24 | wire \ext_2ext ; 25 | wire \ext_2ext_nospace 26 | ; 27 | wire \ext_2esc ; 28 | wire \ext_2esc_nospace 29 | ; 30 | // Necessary escapes 31 | wire \esc[ape]_2non ; 32 | wire \esc[ape]_2non_nospace 33 | ; 34 | wire \esc[ape]_2ext ; 35 | wire \esc[ape]_2ext_nospace 36 | ; 37 | wire \esc[ape]_2esc ; 38 | wire \esc[ape]_2esc_nospace 39 | ; 40 | // Strings 41 | initial $display("foo"); 42 | initial $display("foo.foo"); 43 | initial $display("baz_foo"); 44 | initial $display("foo_baz"); 45 | endmodule 46 | -------------------------------------------------------------------------------- /t/51_vrename_kwd_chg.out: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2010-2012 by Wilson Snyder. 4 | 5 | module 51_vrename_kwd; 6 | // Keyword 7 | wire \do ; 8 | wire \do ; 9 | // Non escapes 10 | wire non_2non; 11 | wire non_2non_nospace 12 | ; 13 | wire non_2ext; 14 | wire non_2ext_nospace 15 | ; 16 | wire non_2esc; 17 | wire non_2esc_nospace 18 | ; 19 | // Extra unnecessary escapes 20 | // Note we cannot legally remove spaces if replacing with non-escaped name 21 | wire \ext_2non ; 22 | wire \ext_2non_nospace 23 | ; 24 | wire \ext_2ext ; 25 | wire \ext_2ext_nospace 26 | ; 27 | wire \ext_2esc ; 28 | wire \ext_2esc_nospace 29 | ; 30 | // Necessary escapes 31 | wire \esc[ape]_2non ; 32 | wire \esc[ape]_2non_nospace 33 | ; 34 | wire \esc[ape]_2ext ; 35 | wire \esc[ape]_2ext_nospace 36 | ; 37 | wire \esc[ape]_2esc ; 38 | wire \esc[ape]_2esc_nospace 39 | ; 40 | // Strings 41 | initial $display("foo"); 42 | initial $display("foo.foo"); 43 | initial $display("baz_foo"); 44 | initial $display("foo_baz"); 45 | endmodule 46 | -------------------------------------------------------------------------------- /t/51_vrename_kwd_chg2.out: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2010-2012 by Wilson Snyder. 4 | 5 | module 51_vrename_kwd; 6 | // Keyword 7 | wire do; 8 | wire \do ; 9 | // Non escapes 10 | wire chg_non_2non; 11 | wire chg_non_2non_nospace 12 | ; 13 | wire \chg_non_2ext ; 14 | wire \chg_non_2ext_nospace 15 | ; 16 | wire \chg_non[ape]_2esc ; 17 | wire \chg_non[ape]_2esc_nospace 18 | ; 19 | // Extra unnecessary escapes 20 | // Note we cannot legally remove spaces if replacing with non-escaped name 21 | wire chg_ext_2non ; 22 | wire chg_ext_2non_nospace 23 | ; 24 | wire \chg_ext_2ext ; 25 | wire \chg_ext_2ext_nospace 26 | ; 27 | wire \chg_ext[ape]_2esc ; 28 | wire \chg_ext[ape]_2esc_nospace 29 | ; 30 | // Necessary escapes 31 | wire chg_escape_2non ; 32 | wire chg_escape_2non_nospace 33 | ; 34 | wire \chg_escape_2ext ; 35 | wire \chg_escape_2ext_nospace 36 | ; 37 | wire \chg_esc[ape]_2esc ; 38 | wire \chg_esc[ape]_2esc_nospace 39 | ; 40 | // Strings 41 | initial $display("bar"); 42 | initial $display("bar.bar"); 43 | initial $display("baz_foo"); 44 | initial $display("foo_baz"); 45 | endmodule 46 | -------------------------------------------------------------------------------- /t/51_vrename_kwd_chg2.vrename: -------------------------------------------------------------------------------- 1 | # DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | # This file ONLY is placed into the Public Domain, for any use, 3 | # without warranty, 2010-2015 by Wilson Snyder. 4 | # 5 | # Original Signal Name Name to change to 6 | # -------------------- ----------------- 7 | # 8 | sigren "foo" "bar" 9 | sigren "\esc[ape]_2esc " "\chg_esc[ape]_2esc " 10 | sigren "\esc[ape]_2esc_nospace " "\chg_esc[ape]_2esc_nospace " 11 | sigren "\esc[ape]_2non " "chg_escape_2non" 12 | sigren "\esc[ape]_2non_nospace " "chg_escape_2non_nospace" 13 | sigren "\esc[ape]_2ext " "\chg_escape_2ext " 14 | sigren "\esc[ape]_2ext_nospace " "\chg_escape_2ext_nospace " 15 | sigren "non_2esc" "\chg_non[ape]_2esc " 16 | sigren "non_2esc_nospace" "\chg_non[ape]_2esc_nospace " 17 | sigren "non_2non" "chg_non_2non" 18 | sigren "non_2non_nospace" "chg_non_2non_nospace" 19 | sigren "non_2ext" "\chg_non_2ext " 20 | sigren "non_2ext_nospace" "\chg_non_2ext_nospace " 21 | sigren "ext_2esc" "\chg_ext[ape]_2esc " 22 | sigren "ext_2esc_nospace" "\chg_ext[ape]_2esc_nospace " 23 | sigren "ext_2non" "chg_ext_2non" 24 | sigren "ext_2non_nospace" "chg_ext_2non_nospace" 25 | sigren "ext_2ext" "\chg_ext_2ext " 26 | sigren "ext_2ext_nospace" "\chg_ext_2ext_nospace " 27 | -------------------------------------------------------------------------------- /t/51_vrename_kwd_list.out: -------------------------------------------------------------------------------- 1 | # Generated by vrename on Wed May 1 06:55:43 2019 2 | # 3 | # Files read for this analysis: 4 | vfile "t/51_vrename_kwd.v" 5 | # 6 | # Original Signal Name Name to change to 7 | # -------------------- ----------------- 8 | # 9 | sigren "$display" "$display" 10 | sigren "\do " "\do " 11 | sigren "\esc[ape]_2esc " "\esc[ape]_2esc " 12 | sigren "\esc[ape]_2esc_nospace " "\esc[ape]_2esc_nospace " 13 | sigren "\esc[ape]_2ext " "\esc[ape]_2ext " 14 | sigren "\esc[ape]_2ext_nospace " "\esc[ape]_2ext_nospace " 15 | sigren "\esc[ape]_2non " "\esc[ape]_2non " 16 | sigren "\esc[ape]_2non_nospace " "\esc[ape]_2non_nospace " 17 | sigren "do" "\do " 18 | sigren "ext_2esc" "ext_2esc" 19 | sigren "ext_2esc_nospace" "ext_2esc_nospace" 20 | sigren "ext_2ext" "ext_2ext" 21 | sigren "ext_2ext_nospace" "ext_2ext_nospace" 22 | sigren "ext_2non" "ext_2non" 23 | sigren "ext_2non_nospace" "ext_2non_nospace" 24 | sigren "non_2esc" "non_2esc" 25 | sigren "non_2esc_nospace" "non_2esc_nospace" 26 | sigren "non_2ext" "non_2ext" 27 | sigren "non_2ext_nospace" "non_2ext_nospace" 28 | sigren "non_2non" "non_2non" 29 | sigren "non_2non_nospace" "non_2non_nospace" 30 | sigren "vrename_kwd" "vrename_kwd" 31 | # 32 | # Use M-x compile in emacs to automatically perform the changes: 33 | ## Local Variables: *** 34 | ## compile-command: "./vrename -change t/51_vrename_kwd.v " *** 35 | ## End: *** 36 | -------------------------------------------------------------------------------- /t/56_editfiles.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2007-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | use File::Copy; 11 | 12 | BEGIN { plan tests => 9 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | BEGIN { use Verilog::EditFiles; } 16 | ok(1); 17 | 18 | { #Editing 19 | my $split = Verilog::EditFiles->new(); 20 | ok(1, "new"); 21 | 22 | my $edfile = "test_dir/56_editfiles.v"; 23 | 24 | $split->edit_file 25 | (filename => "t/56_editfiles.v", 26 | write_filename => $edfile, 27 | cb=>sub { 28 | my $wholefile = shift; 29 | $wholefile =~ s%inside_module%replaced_inside_module%mg; 30 | return $wholefile; 31 | }); 32 | ok(1, "edit_file"); 33 | ok(files_identical($edfile, "t/56_editfiles_edit.out"), "diff"); 34 | } 35 | { 36 | unlink (glob("test_dir/editout/*.v")); 37 | my $split = Verilog::EditFiles->new 38 | (program => "56_editfiles.t", 39 | outdir => "test_dir/editout", 40 | translate_synthesis => 1, 41 | lint_header => "// lint_checking HEADER\n", 42 | celldefine => 1, 43 | ); 44 | $split->read_and_split(glob("t/56_editfiles.v")); 45 | ok(1, "read_and_split"); 46 | $split->write_files(); 47 | ok(1, "write_files"); 48 | ok(files_identical("test_dir/editout/a.v", "t/56_editfiles_a.out"), "diff"); 49 | ok(files_identical("test_dir/editout/b.v", "t/56_editfiles_b.out"), "diff"); 50 | $split->write_lint(); 51 | ok(1, "write_lint"); 52 | } 53 | -------------------------------------------------------------------------------- /t/56_editfiles.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2007-2012 by Wilson Snyder. 4 | 5 | `celldefine 6 | 7 | a_front_matter; 8 | 9 | module a; 10 | wire inside_module_a; /* // double cmt */ 11 | endmodule 12 | 13 | b_front_matter; 14 | 15 | `ifdef B_HAS_X 16 | module b; 17 | `elsif 18 | module b (input x); 19 | `endif 20 | wire inside_module_b; 21 | // synopsys translate_off 22 | wire in_translate_off; 23 | // synopsys translate_on 24 | endmodule 25 | 26 | `endcelldefine 27 | -------------------------------------------------------------------------------- /t/56_editfiles_a.out: -------------------------------------------------------------------------------- 1 | // Created by 56_editfiles.t from 56_editfiles.v 2 | // Created by 56_editfiles.t from 56_editfiles.v 3 | // DESCRIPTION: Verilog::Preproc: Example source code 4 | // This file ONLY is placed into the Public Domain, for any use, 5 | // without warranty, 2007-2012 by Wilson Snyder. 6 | 7 | 8 | a_front_matter; 9 | 10 | `celldefine 11 | // lint_checking HEADER 12 | module a; 13 | wire inside_module_a; /* // double cmt */ 14 | endmodule 15 | `endcelldefine 16 | 17 | -------------------------------------------------------------------------------- /t/56_editfiles_b.out: -------------------------------------------------------------------------------- 1 | // Created by 56_editfiles.t from 56_editfiles.v 2 | 3 | b_front_matter; 4 | 5 | `celldefine 6 | // lint_checking HEADER 7 | `ifdef B_HAS_X 8 | module b; 9 | `elsif 10 | module b (input x); 11 | `endif 12 | wire inside_module_b; 13 | `ifndef SYNTHESIS 14 | wire in_translate_off; 15 | `endif //SYNTHESIS 16 | endmodule 17 | `endcelldefine 18 | 19 | -------------------------------------------------------------------------------- /t/56_editfiles_edit.out: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2007-2012 by Wilson Snyder. 4 | 5 | `celldefine 6 | 7 | a_front_matter; 8 | 9 | module a; 10 | wire replaced_inside_module_a; /* // double cmt */ 11 | endmodule 12 | 13 | b_front_matter; 14 | 15 | `ifdef B_HAS_X 16 | module b; 17 | `elsif 18 | module b (input x); 19 | `endif 20 | wire replaced_inside_module_b; 21 | // synopsys translate_off 22 | wire in_translate_off; 23 | // synopsys translate_on 24 | endmodule 25 | 26 | `endcelldefine 27 | -------------------------------------------------------------------------------- /t/58_vsplitmodule.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use strict; 9 | use Test::More; 10 | 11 | BEGIN { plan tests => 2 } 12 | BEGIN { require "./t/test_utils.pl"; } 13 | 14 | $ENV{HARNESS_ACTIVE} = 1; # vsplitmodule checks this and doesn't die 15 | 16 | print "Checking vsplitmodule...\n"; 17 | { 18 | # -List 19 | my $out = "test_dir/a.v"; 20 | unlink $out; 21 | run_system ("${PERL} ./vsplitmodule"); 22 | ok(1, "vsplitmodule"); 23 | ok(-r $out, "vsplitmodule output"); 24 | unlink $out; 25 | } 26 | -------------------------------------------------------------------------------- /t/60_vpassert.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 6 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | print "Checking vpassert...\n"; 16 | 17 | # Preprocess the files 18 | mkdir "test_dir/.vpassert", 0777; 19 | mkdir "test_dir/.vpassertcall", 0777; 20 | system ("/bin/rm -rf test_dir/verilog"); 21 | symlink ("../verilog", "test_dir/verilog"); # So `line files are found; ok if fails 22 | run_system ("${PERL} ./vpassert --minimum --nostop --date --axiom --verilator --vcs --synthcov" 23 | ." -o test_dir/.vpassert -y verilog/"); 24 | ok(1, "vpassert ran"); 25 | ok(-r 'test_dir/.vpassert/pli.v', "pli.v created"); 26 | 27 | ok(compare('lines', [glob("test_dir/.vpassert/*.v")]), "lines output"); 28 | ok(compare('diff', [glob("test_dir/.vpassert/*.v")]), "diff output"); 29 | 30 | # Preprocess with custom outputters 31 | run_system ("${PERL} ./vpassert --date --verilator --vcs" 32 | .q{ --call-error '$callError'} 33 | .q{ --call-info '$callInfo'} 34 | .q{ --call-warn '$callWarn'} 35 | ." -o test_dir/.vpassertcall -y verilog/"); 36 | ok(files_identical("test_dir/.vpassertcall/example.v", "t/60_vpassert.out"), "diff"); 37 | 38 | # Build the model 39 | unlink "simv"; 40 | chdir 'test_dir'; 41 | SKIP: { 42 | skip("author only test (harmless)",1) 43 | if (!$ENV{VERILATOR_AUTHOR_SITE}); 44 | 45 | if ($ENV{VCS_HOME} && -r "$ENV{VCS_HOME}/bin/vcs") { 46 | run_system (# We use VCS, insert your simulator here 47 | "$ENV{VCS_HOME}/bin/vcs" 48 | # check line coverage 49 | ." -cm line+assert" 50 | # vpassert optionally uses SystemVerilog coverage for $ucover_clk 51 | ." -sverilog" 52 | # vpassert uses `pli to point to the hierarchy of the pli module 53 | ." +define+pli=pli" 54 | # vpassert uses `__message_on to point to the message on variable 55 | ." +define+__message_on=pli.message_on" 56 | # vpassert --minimum uses `__message_minimum to optimize away some messages 57 | ." +define+__message_minimum=1" 58 | # Read files from .vpassert BEFORE reading from other directories 59 | ." +librescan +libext+.v -y .vpassert" 60 | # Finally, read the needed top level file 61 | ." .vpassert/example.v" 62 | ); 63 | # Execute the model (VCS is a compiled simulator) 64 | run_system ("./simv"); 65 | unlink ("./simv"); 66 | ok(1, "vcs sim"); 67 | } 68 | elsif ($ENV{NC_ROOT} && -d "$ENV{NC_ROOT}/tools") { 69 | run_system ("ncverilog" 70 | ." -q" 71 | # vpassert optionally uses SystemVerilog coverage for $ucover_clk 72 | ." +sv" 73 | # vpassert uses `pli to point to the hierarchy of the pli module 74 | ." +define+pli=pli" 75 | # vpassert uses `__message_on to point to the message on variable 76 | ." +define+__message_on=pli.message_on" 77 | # vpassert --minimum uses `__message_minimum to optimize away some messages 78 | ." +define+__message_minimum=1" 79 | # Read files from .vpassert BEFORE reading from other directories 80 | ." +librescan +libext+.v -y .vpassert" 81 | # Finally, read the needed top level file 82 | ." .vpassert/example.v" 83 | ); 84 | ok(1, "ncv sim"); 85 | } 86 | else { 87 | warn "\n"; 88 | warn "*** You do not seem to have VCS or NC-Verilog installed, not running rest of test.\n"; 89 | warn "*** (If you do not license VCS/NC-Verilog, ignore this warning).\n"; 90 | skip("No simulator found",1); 91 | } 92 | } 93 | chdir '..'; 94 | 95 | sub lines_in { 96 | my $filename = shift; 97 | my $fh = IO::File->new($filename) or die "%Error: $! $filename"; 98 | my @lines = $fh->getlines(); 99 | @lines = grep (!/\`line/, @lines); 100 | return $#lines; 101 | } 102 | 103 | sub compare { 104 | my $mode = shift; 105 | my $files = shift; 106 | my $ok = 1; 107 | file: 108 | foreach my $file (@{$files}) { 109 | $file =~ s!.*/!!; 110 | # SPECIAL FILES we processed! 111 | next if $file eq 'example.v'; 112 | next if $file eq 'pli.v'; 113 | 114 | 115 | my $fn1 = "verilog/$file"; 116 | my $fn2 = "test_dir/.vpassert/$file"; 117 | if ($mode eq 'lines') { 118 | my $orig_lines = lines_in($fn1); 119 | my $new_lines = lines_in($fn2); 120 | if ($orig_lines!=$new_lines) { $ok=0; print "%Error: "; } 121 | print "Line count: $file: $orig_lines =? $new_lines\n"; 122 | } 123 | elsif ($mode eq 'diff') { 124 | my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,"; 125 | my $f2 = IO::File->new ($fn2) or die "%Error: $! $fn2,"; 126 | my @l1 = $f1->getlines(); 127 | my @l2 = $f2->getlines(); 128 | @l1 = grep (!/`line/, @l1); 129 | @l2 = grep (!/`line/, @l2); 130 | my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl); 131 | for (my $l=0; $l<=$nl; $l++) { 132 | next if $l2[$l] =~ /vpassert/; 133 | if (($l1[$l]||"") ne ($l2[$l]||"")) { 134 | warn ("%Warning: Line ".($l+1)." mismatches; diff $fn1 $fn2\n" 135 | ."F1: ".($l1[$l]||"*EOF*\n") 136 | ."F2: ".($l2[$l]||"*EOF*\n")); 137 | $ok = 0; 138 | next file; 139 | } 140 | } 141 | } 142 | else { die; } 143 | } 144 | return $ok; 145 | } 146 | -------------------------------------------------------------------------------- /t/80_vppreproc.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 15 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | print "Checking vppreproc...\n"; 16 | 17 | vppreproc ("t/80_vppreproc_none.out", "test_dir/vppreproc_none.v", ""); 18 | vppreproc ("t/80_vppreproc_cmped.out", "test_dir/vppreproc_cmped.v", "--nocomment --pedantic"); 19 | vppreproc ("t/80_vppreproc_simple.out", "test_dir/vppreproc_simple.v", "--simple"); 20 | vppreproc ("t/80_vppreproc_defines.out", "test_dir/vppreproc_defines.v", "--dump-defines"); 21 | vppreproc ("t/80_vppreproc_rel_file.out", "test_dir/vppreproc_rel_file.v", "-f verilog/t_80_foo.f"); 22 | 23 | sub vppreproc { 24 | my $checkname = shift; 25 | my $out = shift; 26 | my $flags = shift; 27 | 28 | my $cmd = "${PERL} ./vppreproc ${flags} -y verilog inc2.v > $out"; 29 | 30 | if (0 == run_system_no_die ($cmd)) { 31 | pass("run command"); 32 | ok(-r $out, "vppreproc output from: $cmd"); 33 | ok(files_identical ($out, $checkname), "diff"); 34 | } else { 35 | fail ("run command"); 36 | fail ("no output file created"); 37 | fail ("no output file to compare"); 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /t/80_vppreproc_cmped.out: -------------------------------------------------------------------------------- 1 | `line 1 "verilog/inc2.v" 1 2 | 3 | 4 | 5 | At file "verilog/inc2.v" line 4 6 | 7 | `line 5 "verilog/inc2.v" 0 8 | `line 1 "verilog/t_preproc_inc3.vh" 1 9 | `line 2 "inc3_a_filename_from_line_directive" 0 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | At file "inc3_a_filename_from_line_directive" line 10 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | `line 19 "inc3_a_filename_from_line_directive" 2 28 | `line 5 "verilog/inc2.v" 0 29 | 30 | 31 | `line 7 "verilog/inc2.v" 2 32 | -------------------------------------------------------------------------------- /t/80_vppreproc_defines.out: -------------------------------------------------------------------------------- 1 | `define SV_COV_ASSERTION 20 2 | `define SV_COV_CHECK 3 3 | `define SV_COV_ERROR -1 4 | `define SV_COV_FSM_STATE 21 5 | `define SV_COV_HIER 11 6 | `define SV_COV_MODULE 10 7 | `define SV_COV_NOCOV 0 8 | `define SV_COV_OK 1 9 | `define SV_COV_OVERFLOW -2 10 | `define SV_COV_PARTIAL 2 11 | `define SV_COV_RESET 2 12 | `define SV_COV_START 0 13 | `define SV_COV_STATEMENT 22 14 | `define SV_COV_STOP 1 15 | `define SV_COV_TOGGLE 23 16 | `define _EMPTY 17 | `define _EXAMPLE_INC2_V_ 1 18 | -------------------------------------------------------------------------------- /t/80_vppreproc_none.out: -------------------------------------------------------------------------------- 1 | `line 1 "verilog/inc2.v" 1 2 | // DESCRIPTION: Verilog::Preproc: Example source code 3 | // This file ONLY is placed into the Public Domain, for any use, 4 | // without warranty, 2000-2012 by Wilson Snyder. 5 | At file "verilog/inc2.v" line 4 6 | 7 | `line 5 "verilog/inc2.v" 0 8 | `line 1 "verilog/t_preproc_inc3.vh" 1 9 | `line 2 "inc3_a_filename_from_line_directive" 0 10 | // DESCRIPTION: Verilog::Preproc: Example source code 11 | // This file ONLY is placed into the Public Domain, for any use, 12 | // without warranty, 2000-2012 by Wilson Snyder. 13 | 14 | 15 | 16 | 17 | // FOO 18 | At file "inc3_a_filename_from_line_directive" line 10 19 | 20 | 21 | // guard 22 | 23 | 24 | 25 | 26 | 27 | `line 19 "inc3_a_filename_from_line_directive" 2 28 | `line 5 "verilog/inc2.v" 0 29 | 30 | 31 | `line 7 "verilog/inc2.v" 2 32 | -------------------------------------------------------------------------------- /t/80_vppreproc_rel_file.out: -------------------------------------------------------------------------------- 1 | `line 1 "verilog/t_80_foo.v" 1 2 | // DESCRIPTION: Verilog::Preproc: Example source code 3 | // This file ONLY is placed into the Public Domain, for any use, 4 | // without warranty, 2012-2012 by Wilson Snyder. 5 | // 6 | // Test -F option in vppreproc. 7 | // This is the top level module. 8 | 9 | module foo(output wire y, input wire x); 10 | bar i_bar(y, x); 11 | endmodule // foo 12 | 13 | `line 12 "verilog/t_80_foo.v" 2 14 | `line 1 "verilog/t_80_bar/bar.v" 1 15 | // DESCRIPTION: Verilog::Preproc: Example source code 16 | // This file ONLY is placed into the Public Domain, for any use, 17 | // without warranty, 2012-2012 by Wilson Snyder. 18 | // 19 | // Test -F option in vppreproc. 20 | 21 | module bar(output wire y, input wire x); 22 | assign y = x; 23 | endmodule // bar 24 | 25 | `line 11 "verilog/t_80_bar/bar.v" 2 26 | `line 1 "verilog/inc2.v" 1 27 | // DESCRIPTION: Verilog::Preproc: Example source code 28 | // This file ONLY is placed into the Public Domain, for any use, 29 | // without warranty, 2000-2012 by Wilson Snyder. 30 | At file "verilog/inc2.v" line 4 31 | 32 | `line 5 "verilog/inc2.v" 0 33 | `line 1 "verilog/t_preproc_inc3.vh" 1 34 | `line 2 "inc3_a_filename_from_line_directive" 0 35 | // DESCRIPTION: Verilog::Preproc: Example source code 36 | // This file ONLY is placed into the Public Domain, for any use, 37 | // without warranty, 2000-2012 by Wilson Snyder. 38 | 39 | 40 | 41 | 42 | // FOO 43 | At file "inc3_a_filename_from_line_directive" line 10 44 | 45 | 46 | // guard 47 | 48 | 49 | 50 | 51 | 52 | `line 19 "inc3_a_filename_from_line_directive" 2 53 | `line 5 "verilog/inc2.v" 0 54 | 55 | 56 | `line 7 "verilog/inc2.v" 2 57 | -------------------------------------------------------------------------------- /t/80_vppreproc_simple.out: -------------------------------------------------------------------------------- 1 | At file "verilog/inc2.v" line 4 2 | At file "inc3_a_filename_from_line_directive" line 10 3 | -------------------------------------------------------------------------------- /t/85_vhier.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 19 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | print "Checking vhier...\n"; 16 | 17 | vhier ("t/85_vhier_cells.out", "--cells"); 18 | vhier ("t/85_vhier_includes.out", "--includes"); 19 | vhier ("t/85_vhier_inpfiles.out", "--input-files"); 20 | vhier ("t/85_vhier_resolvefiles.out","--resolve-files"); 21 | vhier ("t/85_vhier_modfiles.out", "--module-files --language 2001"); 22 | vhier ("t/85_vhier_topmodule.out", "--module-files --top-module v_hier_sub"); 23 | vhier ("t/85_vhier_forest.out", "--forest --instance"); 24 | vhier ("t/85_vhier_skiplist.out", "--forest --instance --skiplist t/85_vhier_skiplist.dat"); 25 | vhier ("t/85_vhier_xml.out", "--xml --cells --includes --input-files --module-files --missing-modules"); 26 | check_valid_xml("test_dir/vhier.out"); 27 | 28 | sub vhier { 29 | my $checkname = shift; 30 | my $flags = shift; 31 | 32 | my $out = "test_dir/vhier.out"; 33 | my $cmd = "${PERL} ./vhier ${flags} --nomissing -y verilog v_hier_top.v -o $out"; 34 | run_system ($cmd); 35 | ok(-r $out, "vhier outputted from: $cmd"); 36 | #run_system ("/bin/cp $out $checkname"); 37 | ok(files_identical ($out, $checkname), "vhier file compare"); 38 | } 39 | 40 | sub check_valid_xml { 41 | my $filename = shift; 42 | SKIP: { 43 | if ((eval("use XML::Simple; 1;")||0) == 1) { 44 | my $xs = new XML::Simple('ForceArray' => [qw(entry)],); 45 | ok ($xs->XMLin($filename), "Validate XML"); 46 | } else { 47 | skip("author only XML test (harmless)",1); 48 | } 49 | } 50 | } 51 | -------------------------------------------------------------------------------- /t/85_vhier_cells.out: -------------------------------------------------------------------------------- 1 | v_hier_top 2 | v_recursive 3 | v_hier_sub 4 | v_hier_subsub 5 | v_hier_subsub 6 | -------------------------------------------------------------------------------- /t/85_vhier_forest.out: -------------------------------------------------------------------------------- 1 | v_hier_top v_hier_top 2 | |--recursive v_recursive 3 | \--sub v_hier_sub 4 | |--subsub0 v_hier_subsub 5 | \--subsub2 v_hier_subsub 6 | -------------------------------------------------------------------------------- /t/85_vhier_includes.out: -------------------------------------------------------------------------------- 1 | verilog/v_hier_top.v 2 | v_hier_inc.vh 3 | -------------------------------------------------------------------------------- /t/85_vhier_inpfiles.out: -------------------------------------------------------------------------------- 1 | verilog/v_hier_inc.vh 2 | verilog/v_hier_sub.v 3 | verilog/v_hier_subsub.v 4 | verilog/v_hier_top.v 5 | verilog/v_recursive.v 6 | -------------------------------------------------------------------------------- /t/85_vhier_modfiles.out: -------------------------------------------------------------------------------- 1 | verilog/v_hier_top.v 2 | verilog/v_hier_sub.v 3 | verilog/v_recursive.v 4 | verilog/v_hier_subsub.v 5 | -------------------------------------------------------------------------------- /t/85_vhier_resolvefiles.out: -------------------------------------------------------------------------------- 1 | verilog/v_hier_top.v 2 | -------------------------------------------------------------------------------- /t/85_vhier_skiplist.dat: -------------------------------------------------------------------------------- 1 | v_hier_nonexistent 2 | v_hier_subsub 3 | -------------------------------------------------------------------------------- /t/85_vhier_skiplist.out: -------------------------------------------------------------------------------- 1 | v_hier_top v_hier_top 2 | |--recursive v_recursive 3 | \--sub v_hier_sub 4 | -------------------------------------------------------------------------------- /t/85_vhier_topmodule.out: -------------------------------------------------------------------------------- 1 | verilog/v_hier_sub.v 2 | verilog/v_hier_subsub.v 3 | -------------------------------------------------------------------------------- /t/85_vhier_xml.out: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | verilog/v_hier_top.v 16 | verilog/v_hier_sub.v 17 | verilog/v_recursive.v 18 | verilog/v_hier_subsub.v 19 | 20 | 21 | verilog/v_hier_inc.vh 22 | verilog/v_hier_sub.v 23 | verilog/v_hier_subsub.v 24 | verilog/v_hier_top.v 25 | verilog/v_recursive.v 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | -------------------------------------------------------------------------------- /t/86_vhier_tick.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 2 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | # bug300 16 | my $cmd = "${PERL} ./vhier --input-files -y verilog t_86_vhier_tick.v"; 17 | my $out = `$cmd`; 18 | is($?,0,$cmd); 19 | like($out, qr//, $cmd); 20 | -------------------------------------------------------------------------------- /t/87_vhier_unicode.t: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package 3 | # 4 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 5 | # you can redistribute it and/or modify it under the terms of either the GNU 6 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 7 | 8 | use IO::File; 9 | use strict; 10 | use Test::More; 11 | 12 | BEGIN { plan tests => 3 } 13 | BEGIN { require "./t/test_utils.pl"; } 14 | 15 | { 16 | my $fh = IO::File->new(">test_dir/unicode.v"); 17 | $fh->print(chr(0xEF).chr(0xBB).chr(0xBF)); # BOM 18 | $fh->print("// Bom\n"); 19 | $fh->print("module t;\n"); 20 | $fh->print(" // Chinese " 21 | .chr(0xe8).chr(0xaf).chr(0x84).chr(0xe8).chr(0xae).chr(0xba) # Comment 22 | ."\n"); 23 | $fh->print(" initial begin\n"); 24 | $fh->print(" \$write(\"Hello " 25 | .chr(0xe4).chr(0xb8).chr(0x96).chr(0xe7).chr(0x95).chr(0x8c) # World 26 | ."\\n\");\n"); 27 | $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); 28 | $fh->print(" end\n"); 29 | $fh->print("endmodule\n"); 30 | $fh->close; 31 | } 32 | ok(1); 33 | 34 | { 35 | my $out = "test_dir/unicode_vppreproc.out"; 36 | my $cmd = "${PERL} ./vppreproc -y verilog test_dir/unicode.v > $out"; 37 | run_system($cmd); 38 | ok(-r $out, "vppreproc outputted from: $cmd"); 39 | } 40 | { 41 | my $out = "test_dir/unicode_vhier.out"; 42 | my $cmd = "${PERL} ./vhier --input-files --nomissing -y verilog test_dir/unicode.v -o $out"; 43 | run_system($cmd); 44 | ok(-r $out, "vhier outputted from: $cmd"); 45 | } 46 | 47 | -------------------------------------------------------------------------------- /t/test_utils.pl: -------------------------------------------------------------------------------- 1 | # DESCRIPTION: Perl ExtUtils: Common routines required by package tests 2 | # 3 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 4 | # you can redistribute it and/or modify it under the terms of either the GNU 5 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 6 | 7 | use IO::File; 8 | use File::Copy; 9 | use strict; 10 | use vars qw($PERL); 11 | 12 | $PERL = "$^X -Iblib/arch -Iblib/lib -IPreproc/blib/arch -IPreproc/blib/lib"; 13 | 14 | mkdir 'test_dir',0777; 15 | unlink "test_dir/verilog"; # Symlink made in vpassert test will mess up others 16 | 17 | if (!$ENV{HARNESS_ACTIVE}) { 18 | use lib '.'; 19 | use lib '..'; 20 | use lib "blib/lib"; 21 | use lib "blib/arch"; 22 | use lib "Preproc/blib/lib"; 23 | use lib "Preproc/blib/arch"; 24 | } 25 | 26 | sub run_system { 27 | # Run a system command, check errors 28 | my $command = shift; 29 | print "\t$command\n"; 30 | system "$command"; 31 | my $status = $?; 32 | ($status == 0) or die "%Error: Command Failed $command, $status, stopped"; 33 | } 34 | 35 | sub run_system_no_die { 36 | # Run a system command, check errors 37 | my $command = shift; 38 | print "\t$command\n"; 39 | system "$command"; 40 | return $?; 41 | } 42 | 43 | sub wholefile { 44 | my $file = shift; 45 | my $fh = IO::File->new ($file) or die "%Error: $! $file"; 46 | my $wholefile = join('',$fh->getlines()); 47 | $fh->close(); 48 | return $wholefile; 49 | } 50 | 51 | sub files_identical { 52 | my $fn1 = shift; # got 53 | my $fn2 = shift; # expected 54 | my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,"; 55 | my $f2 = IO::File->new ($fn2) or die "%Error: $! $fn2,"; 56 | my @l1 = $f1->getlines(); 57 | my @l2 = $f2->getlines(); 58 | my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl); 59 | for (my $l=0; $l<=$nl; $l++) { 60 | $l1[$l] =~ s/\r\n/\n/g if defined $l1[$l]; # Cleanup if on Windows 61 | $l2[$l] =~ s/\r\n/\n/g if defined $l2[$l]; 62 | if (($l1[$l]||"") ne ($l2[$l]||"")) { 63 | next if ($l1[$l]||"") =~ /Generated by vrename on/; 64 | warn ("%Warning: Line ".($l+1)." mismatches; $fn1 $fn2\n" 65 | ."GOT: ".($l1[$l]||"*EOF*\n") 66 | ."EXP: ".($l2[$l]||"*EOF*\n")); 67 | if ($ENV{HARNESS_UPDATE_GOLDEN}) { # Update golden files with current 68 | warn "%Warning: HARNESS_UPDATE_GOLDEN set: cp $fn1 $fn2\n"; 69 | copy($fn1,$fn2); 70 | } else { 71 | warn "To update reference: HARNESS_UPDATE_GOLDEN=1 ".join(" ",$0,@ARGV)."\n"; 72 | } 73 | return 0; 74 | } 75 | } 76 | return 1; 77 | } 78 | 79 | sub get_memory_usage { 80 | # Return memory usage. Return 0 if the system doesn't look quite right. 81 | my $fh = IO::File->new("getline || ""; 85 | my @stats = split /\s+/, $stat; 86 | return ($stats[0]||0)*4096; # vmsize 87 | } 88 | 89 | 1; 90 | -------------------------------------------------------------------------------- /verilog/example.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Example top verilog file for vpassert program 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | `timescale 1ns/1ns 6 | 7 | module example; 8 | 9 | pli pli (); // Put on highest level of your design 10 | 11 | integer i; 12 | 13 | `define ten 10 14 | 15 | reg \escaped[10] ; 16 | 17 | initial begin 18 | $uinfo (0, "Welcome to a VPASSERTed file\n"); 19 | // 20 | $uinfo (1, "Printed only at debug level %0d\n",1); 21 | $uinfo (9, "Printed only at debug level %0d\n",9); 22 | // 23 | \escaped[10] = 1'b1; 24 | $uassert (\escaped[10] , "Escaped not 1\n"); 25 | $uassert_info (\escaped[10] , "Escaped not 1\n"); 26 | // 27 | i=0; 28 | $uassert (1==1, "Why doesn't 1==1??\n"); 29 | $uassert (10==`ten, "Why doesn't 10==10??\n"); 30 | $uassert (/*comm 31 | ent*/1==1, 32 | //comment 33 | /*com 34 | ent*/"Why doesn't 1==1??\n"/*com 35 | ent*/ 36 | ); 37 | // 38 | i=3'b100; $uassert_amone(\i [2:0], "amone ok\n"); 39 | i=3'b010; $uassert_amone(i[2:0], "amone ok\n"); 40 | i=3'b001; $uassert_amone(i[2:0], "amone ok\n"); 41 | i=3'b000; $uassert_amone(i[2:0], "amone ok\n"); 42 | //i=3'b011; $uassert_amone(i[2:0], "amone error expected\n"); 43 | //i=3'b110; $uassert_amone(i[2:0], "amone error expected\n"); 44 | // 45 | i=2'b10; $uassert_onehot(i[1:0], "onehot ok\n"); 46 | i=2'b01; $uassert_onehot(i[1:0], "onehot ok\n"); 47 | i=2'b10; $uassert_onehot(i[1],i[0], "onehot ok\n"); 48 | i=2'b10; $uassert_onehot({i[1],i[0]}, "onehot ok\n"); 49 | //i=2'b11; $uassert_onehot(i[2:0], "onehot error expected\n"); 50 | //i=2'b00; $uassert_onehot(i[2:0], "onehot error expected\n"); 51 | end 52 | 53 | // Test assertions within case statements 54 | initial begin 55 | i=3'b100; 56 | casez (i) 57 | 3'b100: ; 58 | 3'b000: $stop; 59 | 3'b010: $uerror("Why?\n"); 60 | default: $stop; 61 | endcase 62 | if ($time > 1000) $stop; 63 | end 64 | 65 | // Example of request/grant handshake 66 | reg clk; 67 | reg bus_req; // Request a transaction, single cycle pulse 68 | reg bus_ack; // Acknowledged transaction, single cycle pulse 69 | reg [31:0] bus_data; 70 | 71 | initial begin 72 | // Reset signals 73 | bus_req = 1'b0; 74 | bus_ack = 1'b0; 75 | bus_data = 1'b0; 76 | // Assert a request 77 | @ (posedge clk) ; 78 | bus_req = 1'b1; 79 | bus_data = 32'hfeed; 80 | // Wait for ack 81 | @ (posedge clk) ; 82 | bus_req = 1'b0; 83 | // Send ack 84 | @ (posedge clk) ; 85 | bus_ack = 1'b1; 86 | // Next request could be here 87 | @ (posedge clk) ; 88 | bus_ack = 1'b0; 89 | end 90 | always @ (posedge clk) begin 91 | $uassert_req_ack (bus_req, 92 | bus_ack /*COMMENT*/, 93 | bus_data); 94 | end 95 | 96 | // Overall control loop 97 | initial clk = 1'b0; 98 | initial forever begin 99 | #1; 100 | i = i + 1; 101 | clk = !clk; 102 | if (i==20) $uwarn (0, "Don't know what to do next!\n"); 103 | if (i==22) $uerror (0, "Guess I'll error out!\n"); 104 | end 105 | 106 | // Moved clock asserts 107 | always @* begin 108 | if (i==19) $uwarn_clk (clk,"Called at next edge (1 of 2)\n"); 109 | if (i==18) $ucover_clk (clk,"example_cover_label"); 110 | $ucover_foreach_clk(clk, "foreach_label", "27:3,1,0", (i[$ui])); 111 | end 112 | 113 | // Meta coverage disables 114 | initial begin 115 | // vp_coverage_off 116 | if (0) begin end // cover off'ed 117 | // vp_coverage_on 118 | end 119 | 120 | // Ifdef based disables 121 | initial begin 122 | `ifndef NEVER 123 | `ifdef SYNTHESIS 124 | if (1) begin end // cover on 125 | `elsif SYNTHESIS 126 | if (1) begin end // cover on 127 | `else 128 | if (1) begin end // cover off'ed 129 | `endif 130 | `ifndef SYNTHESIS 131 | if (1) begin end // cover off'ed 132 | `else 133 | if (1) begin end // cover on 134 | `endif 135 | `endif 136 | end 137 | 138 | endmodule 139 | -------------------------------------------------------------------------------- /verilog/inc2.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | At file `__FILE__ line `__LINE__ 5 | `include 6 | -------------------------------------------------------------------------------- /verilog/inc_def09.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Verilog Test module 2 | // 3 | // This file ONLY is placed into the Public Domain, for any use, 4 | // without warranty, 2009 by Wilson Snyder. 5 | 6 | `undefineall 7 | 8 | // Definitions as speced 9 | // Note there are trailing spaces, which spec doesn't show properly 10 | `define D(x,y) initial $display("start", x , y, "end"); 11 | '`D( "msg1" , "msg2" )' 12 | 'initial $display("start", "msg1" , "msg2" , "end");' 13 | '`D( " msg1", )' 14 | 'initial $display("start", " msg1" , , "end");' 15 | '`D(, "msg2 ")' 16 | 'initial $display("start", , "msg2 ", "end");' 17 | '`D(,)' 18 | 'initial $display("start", , , "end");' 19 | '`D( , )' 20 | 'initial $display("start", , , "end");' 21 | //`D("msg1") // ILLEGAL: only one argument 22 | //`D() // ILLEGAL: only one empty argument 23 | //`D(,,) // ILLEGAL: more actual than formal arguments 24 | 25 | // Defaults: 26 | `define MACRO1(a=5,b="B",c) $display(a,,b,,c); 27 | '`MACRO1 ( , 2, 3 )' 28 | '$display(5,,2,,3);' 29 | '`MACRO1 ( 1 , , 3 )' 30 | '$display(1 ,,"B",,3 );' 31 | '`MACRO1 ( , 2, )' 32 | '$display(5,,2,,);' 33 | //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c 34 | 35 | `define MACRO2(a=5, b, c="C") $display(a,,b,,c); 36 | '`MACRO2 (1, , 3)' 37 | '$display(5,,,,"C");' 38 | '`MACRO2 (, 2, )' 39 | '$display(5,,2,,"C");' 40 | '`MACRO2 (, 2)' 41 | '$display(5,,2,,"C");' 42 | 43 | `define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); 44 | '`MACRO3 ( 1 )' 45 | '$display(1 ,,0,,"C");' 46 | '`MACRO3 ( )' 47 | '$display(5,,0,,"C");' 48 | //`MACRO3 // ILLEGAL: parentheses required 49 | 50 | `define DTOP(a,b) a + b 51 | '`DTOP( `DTOP(b,1), `DTOP(42,a) )' 52 | 'b + 1 + 42 + a' 53 | 54 | // Local tests 55 | `define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c' 56 | `MACROQUOTE(); 57 | '"==)" "((((" () '; 58 | 59 | // Also check our line counting doesn't go bad 60 | `define MACROPAREN(a=(6), 61 | b=(eq=al), 62 | c) 'a b c' 63 | `MACROPAREN( 64 | 65 | 66 | 67 | ,, 68 | 69 | 70 | ZOT) 71 | HERE-`__LINE__ - Line71 72 | 73 | //====================================================================== 74 | -------------------------------------------------------------------------------- /verilog/inc_ifdef.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | `define EMPTY_TRUE 6 | `ifndef EMPTY_TRUE 7 | `error "Empty is still true" 8 | `endif 9 | 10 | `define A 11 | `ifdef A 12 | $display("1A"); 13 | `ifdef C 14 | $display("%Error: 2C"); 15 | `elsif A 16 | $display("2A"); 17 | `ifdef C 18 | $display("%Error: 3C"); 19 | `elsif B 20 | $display("%Error: 3B"); 21 | `else 22 | $display("3AELSE"); 23 | `endif 24 | `else 25 | $display("%Error: 2ELSE"); 26 | `endif 27 | `elsif B 28 | $display("%Error: 1B"); 29 | `ifdef A 30 | $display("%Error: noC"); 31 | `elsif A 32 | $display("%Error: noB"); 33 | `else 34 | $display("%Error: noELSE"); 35 | `endif 36 | `elsif C 37 | $display("%Error: 1C"); 38 | `else 39 | $display("%Error: 1ELSE"); 40 | `endif 41 | -------------------------------------------------------------------------------- /verilog/inc_nonl.v: -------------------------------------------------------------------------------- 1 | // The lack of a newline on the next line is intentional 2 | blah-no-newline-here> -------------------------------------------------------------------------------- /verilog/parser_sv09.v: -------------------------------------------------------------------------------- 1 | // 1800-2009 mantis1769 2 | module mantis1769 #(N=1); 3 | if (N < 1) $error("Bad N value %d", N); 4 | endmodule 5 | // 1800-2009 mantis1134 6 | module mantis1134_decoder 7 | #(BITS = 3, localparam OUT_BITS = 1 << BITS) 8 | (input [BITS-1:0] A, output reg [OUT_BITS-1:0] Y); 9 | assign Y = 1 << A; 10 | endmodule 11 | // 1800-2009 mantis907 12 | module mantis907_default_parameter 13 | #(REQUIRED); 14 | endmodule 15 | module mantis1619_default_input (input integer deflt = 10); 16 | endmodule 17 | module global_anal; // Don't be anal about "global" in old code 18 | integer global = 1; 19 | global clocking z @(posedge clk); // But still get it right 20 | endclocking 21 | endmodule 22 | module bug400; 23 | assert property 24 | ( @(posedge clk) 25 | disable iff (rst || $past (rst,1,,@(posedge clk)) || $isunknown(rst)) 26 | "assert 0"); 27 | endmodule 28 | 29 | // dobbie 30 | package pkga; 31 | endpackage 32 | package pkgb; 33 | endpackage 34 | module impbegin 35 | import pkga::*; 36 | import pkgb::*; 37 | (input foobar); 38 | endmodule 39 | 40 | 41 | // msg2546 42 | module def_cov_point; 43 | logic [7:0] data; 44 | logic [7:0] addr; 45 | covergroup c; 46 | ADDRESS : coverpoint addr { 47 | bins low[] = {[0:10]}; 48 | bins med[] = {[11:20]}; 49 | } 50 | endgroup 51 | // Can't handle this due to package parsing yaID__ETC 52 | //covergroup d; 53 | // d : coverpoint data { 54 | // bins low[] = {[0:10]}; 55 | // bins med[] = {[11:20]}; 56 | // } 57 | //endgroup 58 | endmodule 59 | -------------------------------------------------------------------------------- /verilog/parser_sv17.v: -------------------------------------------------------------------------------- 1 | // 1800-2017 2 | module sv17; 3 | integer i; 4 | initial begin 5 | for (i=0;;) break; 6 | for (;i!=0;) begin end 7 | for (;;++i) break; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilog/parser_vectors.v: -------------------------------------------------------------------------------- 1 | /* This file contains some instantiations of an unknown module that use bit vectors. */ 2 | 3 | module top(i,o); 4 | input [31:0] i; 5 | output [31:0] o; 6 | 7 | wire [3:0] somebus, someotherbus; 8 | wire somenet_1,somenet_2,somenet_3; 9 | wire [29:0] somewidebus; 10 | 11 | parameter SOMEPARAM = 10; 12 | 13 | assign somewidebus=i[31:2]; 14 | assign o[1]=somenet_1; 15 | assign o[2]=somenet_2; 16 | assign o[0]=1'b0; 17 | assign o[3]=someotherbus[2]; 18 | assign o[28:4]=25'b0; 19 | assign o[31]=~somenet_1; 20 | 21 | mod instmod_1 ( 22 | .a(somebus), 23 | .y(somenet_1) 24 | ); 25 | 26 | mod instmod_2 ( 27 | .a(somebus), 28 | .y(someotherbus[2]) 29 | ); 30 | 31 | mod instmod_3 ( 32 | .a(somewidebus[24:21]), 33 | .y(somenet_2) 34 | ); 35 | 36 | mod instmod_4 ( 37 | .a(i[31:27]), 38 | .y(o[29]) 39 | ); 40 | 41 | mod instmod_5 ( 42 | .a({somenet_1,3'b101,someotherbus[2],somewidebus[2:1]}), 43 | .y(o[30]) 44 | ); 45 | 46 | mod instmod_6 ( 47 | .a({somenet_1,3'b101,{someotherbus[2],someotherbus[2]},somewidebus[2:1]}), 48 | .y(o[30]) 49 | ); 50 | 51 | mod instmod_7 ( 52 | .a(somebus[{SOMEPARAM_3[1],SOMEPARAM_3[0]}]), 53 | .y(someotherbus[2]) 54 | ); 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /verilog/pinorder.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // 3 | // This file ONLY is placed into the Public Domain, for any use, 4 | // without warranty, 2003 by Wilson Snyder. 5 | 6 | module pinorder4(); 7 | wire b_i; 8 | wire d_o; 9 | wire [7:0] a_i; 10 | wire [31:0] IPCD_const = 32'h1; 11 | 12 | assign a_i = 0; 13 | assign b_i = 0; 14 | 15 | foo foo1( .y(b_i), .x(a_i), .abcconst(3'h0), .noconnect(), 16 | .def(IPCD_const)); 17 | foo foo3( b_i, a_i, 3'h0, , IPCD_const); 18 | foo2 foo2( b_i, a_i[0], d_o); 19 | 20 | endmodule 21 | 22 | module foo2(/*AUTOARG*/ 23 | // Outputs 24 | x, 25 | // Inputs 26 | z, y 27 | ); 28 | input z; 29 | input y; 30 | output x; 31 | reg x; 32 | always @(z or y) x = z & y; 33 | endmodule 34 | 35 | module foo (/*AUTOARG*/ 36 | // Inputs 37 | y, x, abcconst, noconnect, def 38 | ); 39 | input y; 40 | input x; 41 | input [2:0] abcconst; 42 | input signed [3:0] noconnect; 43 | input [31:0] def; 44 | endmodule 45 | 46 | module bug278 47 | ( 48 | output wire ow, 49 | inout wire iow, 50 | input wire iw); 51 | endmodule 52 | -------------------------------------------------------------------------------- /verilog/pli.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Example pli file for vpassert program 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | `timescale 1ns/1ns 6 | 7 | module pli; 8 | // A module called PLI is required, to contain the error counts 9 | // This is required with the vpassert --nostop option, which this example uses 10 | // By default (--stop), this file isn't needed at all 11 | 12 | integer errors; initial errors = 0; 13 | integer warnings; initial warnings = 0; 14 | 15 | // Normally this would be 0 at startup, then become 1 after reset deasserts 16 | // This prevents false assertion checks during reset 17 | integer message_on; initial message_on = 1; 18 | 19 | always @ (errors or warnings) begin 20 | `ifdef OPTIONAL_EXIT_ON_WARNING 21 | if (errors!=0 || warnings!=0) begin 22 | $uinfo (0, "Errors/warnings found, exiting!\n"); 23 | $finish; 24 | end 25 | `else 26 | if (errors!=0) begin 27 | $uinfo (0, "Errors found, exiting!\n"); 28 | $finish; 29 | end 30 | else if (warnings!=0) begin 31 | $uinfo (0, {"Warnings found, ","consider stopping!\n"}); 32 | end 33 | `endif 34 | end 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /verilog/t_80_bar/bar.f: -------------------------------------------------------------------------------- 1 | bar.v 2 | -------------------------------------------------------------------------------- /verilog/t_80_bar/bar.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2012-2012 by Wilson Snyder. 4 | // 5 | // Test -F option in vppreproc. 6 | 7 | module bar(output wire y, input wire x); 8 | assign y = x; 9 | endmodule // bar 10 | -------------------------------------------------------------------------------- /verilog/t_80_foo.f: -------------------------------------------------------------------------------- 1 | verilog/t_80_foo.v 2 | -F verilog/t_80_bar/bar.f 3 | -------------------------------------------------------------------------------- /verilog/t_80_foo.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2012-2012 by Wilson Snyder. 4 | // 5 | // Test -F option in vppreproc. 6 | // This is the top level module. 7 | 8 | module foo(output wire y, input wire x); 9 | bar i_bar(y, x); 10 | endmodule // foo 11 | -------------------------------------------------------------------------------- /verilog/t_86_vhier_tick.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | module t_86_vhier_tick; 6 | 7 | `define t_86_vhier_tick_sub FOOBAR_NOT_FOUND 8 | t_86_vhier_tick_sub sub (); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilog/t_86_vhier_tick_sub.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | module t_86_vhier_tick_sub; 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilog/t_preproc_inc3.vh: -------------------------------------------------------------------------------- 1 | `line 2 "inc3_a_filename_from_line_directive" 0 2 | // DESCRIPTION: Verilog::Preproc: Example source code 3 | // This file ONLY is placed into the Public Domain, for any use, 4 | // without warranty, 2000-2012 by Wilson Snyder. 5 | 6 | `ifndef _EXAMPLE_INC2_V_ 7 | `define _EXAMPLE_INC2_V_ 1 8 | `define _EMPTY 9 | // FOO 10 | At file `__FILE__ line `__LINE__ 11 | `else 12 | `error "INC2 File already included once" 13 | `endif // guard 14 | 15 | `ifdef not_defined 16 | `include "NotToBeInced.v" 17 | `endif 18 | -------------------------------------------------------------------------------- /verilog/t_preproc_inc4.vh: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog::Preproc: Example source code 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | `define T_PREPROC_INC4 6 | -------------------------------------------------------------------------------- /verilog/test.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | // ENCRYPT_ME 6 | 7 | module example (/*AUTOARG*/ 8 | // Outputs 9 | z, 10 | // Inputs 11 | a, b 12 | ); 13 | 14 | // See https://www.veripool.org 15 | // for what AUTOARG and friends can do for you! 16 | 17 | /*Comment // test*/ 18 | // 19 | 20 | input a; 21 | input b; 22 | 23 | output z; 24 | 25 | wire result = a|b; 26 | 27 | wire z = result; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /verilog/test.vrename: -------------------------------------------------------------------------------- 1 | # DESCRIPTION: vrename: For test.pl testing of vrename 2 | # 3 | # Copyright 2000-2024 by Wilson Snyder. This program is free software; 4 | # you can redistribute it and/or modify it under the terms of either the GNU 5 | # Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. 6 | ###################################################################### 7 | sigren "a" "or_term_1" 8 | sigren "b" "or_term_2" 9 | sigren "z" "ored_output" 10 | -------------------------------------------------------------------------------- /verilog/v_comments.v: -------------------------------------------------------------------------------- 1 | `define ThirtyTwo 32 2 | 3 | module v_comments ( a, // Pragma for a 4 | b, // pragma for b 5 | c, 6 | d, d1, d2, d3 ); 7 | input a; // comment for a 8 | inout [10:0] b; 9 | output [0:10] c; // comment for c 10 | output [ ((2*`ThirtyTwo) - 1) : 0 ] d; 11 | output [ `ThirtyTwo : 0 ] d1; 12 | output [ ( MATH - 1 ): 0 ] d2; 13 | output [ `ThirtyTwo - 1: 0 ] d3; 14 | 15 | reg d; 16 | reg [11:0] e; // Comment for e 17 | 18 | endmodule 19 | 20 | // 'Third' below must attach to 'b' becase there's no ) or , after b. 21 | module v_bug917 // modcmt 22 | (input wire a, // a-First 23 | output wire m // m-Second 24 | , 25 | output wire b // b-Third 26 | ); 27 | // Third 28 | endmodule 29 | 30 | module v_bug917p 31 | (input wire a, // a-First 32 | output wire b); // b-Secondparen 33 | // Third 34 | endmodule 35 | -------------------------------------------------------------------------------- /verilog/v_gate.v: -------------------------------------------------------------------------------- 1 | module buffer ( 2 | output Z, 3 | input A); 4 | buf u_buf(Z, A); 5 | endmodule 6 | 7 | module gate ( 8 | output Z, 9 | input A); 10 | buffer u_buf(Z, A); 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog/v_hier_inc.vh: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | `ifndef V_HIER_INC_VH 6 | `define V_HIER_INC_VH // Guard 7 | 8 | `define hsub v_hier_sub 9 | 10 | `endif // Guard 11 | -------------------------------------------------------------------------------- /verilog/v_hier_noport.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | module v_hier_noport; 6 | parameter P; 7 | reg internal; 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilog/v_hier_sub.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // 3 | // This file ONLY is placed into the Public Domain, for any use, 4 | // without warranty, 2000-2012 by Wilson Snyder. 5 | 6 | module v_hier_sub (/*AUTOARG*/ 7 | input clk, 8 | input [3:0] avec, // Comment for v_hier_sub, avec 9 | output [3:0] qvec /* Comment for v_hier_sub, qvec */ 10 | ); 11 | 12 | parameter FROM_DEFPARAM = 1; 13 | 14 | supply1 a1; 15 | 16 | v_hier_subsub #( 17 | .IGNORED('sh20) 18 | ) 19 | \subsub0 ( 20 | // Outputs 21 | .q (qvec[0]), 22 | // Inputs 23 | .a (a1)); // Comment for subsub cell 24 | 25 | 26 | generate 27 | genvar K, K_UNUSED; 28 | for (K=0; K<1; K=K+1) begin : genloop 29 | // By pin position, inside generate 30 | v_hier_subsub subsub2 (qvec[2], 1'b0); 31 | end 32 | endgenerate 33 | 34 | function foo; 35 | (* attribute *) 36 | /* synopsys metacommenttest */ 37 | input not_part_of_pinlist; 38 | foo = not_part_of_pinlist; 39 | endfunction 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /verilog/v_hier_subprim.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // 3 | // This file ONLY is placed into the Public Domain, for any use, 4 | // without warranty, 2000-2012 by Wilson Snyder. 5 | 6 | // surefire lint_off UDPUNS 7 | 8 | primitive v_hier_prim (/*AUTOARG*/ 9 | // Outputs 10 | q, 11 | // Inputs 12 | a 13 | ); 14 | output q; 15 | input a; 16 | 17 | table 18 | 0 : 1; 19 | 1 : 0; 20 | endtable 21 | 22 | endprimitive 23 | 24 | `celldefine 25 | module bug27070(); 26 | `define W 4 27 | parameter TAP = `W'b1001; 28 | endmodule 29 | `endcelldefine 30 | 31 | `celldefine 32 | module bug893(); 33 | reg r; 34 | initial r <=#1 '0; 35 | endmodule 36 | `endcelldefine 37 | -------------------------------------------------------------------------------- /verilog/v_hier_subsub.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | module v_hier_subsub (/*AUTOARG*/ 6 | // Outputs 7 | q, 8 | // Inputs 9 | a 10 | ); 11 | parameter IGNORED = 0; 12 | input signed a; 13 | output q; 14 | wire q = a; 15 | 16 | // Test protected 17 | `pragma protect begin_protected 18 | `pragma protect encrypt_agent = "Whatever agent" 19 | `pragma protect encrypt_agent_info = "1.2.3" 20 | `pragma protect data_method = "aes128-cbc" 21 | `pragma protect key_keyowner = "Someone" 22 | `pragma protect key_keyname = "somekey", key_method = "rsa" 23 | `pragma protect key_block encoding = (enctype = "base64") 24 | wefjosdfjklajklasjkl 25 | `pragma protect data_block encoding = (enctype = "base64", bytes = 1059) 26 | I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) 27 | #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] 28 | `pragma protect end_protected 29 | `pragma reset protect 30 | //" 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /verilog/v_hier_top.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | `include "v_hier_inc.vh" 6 | 7 | module v_hier_top (/*AUTOARG*/ 8 | // Inputs 9 | clk 10 | ); 11 | input clk; /* pragma jsc_clk */ 12 | 13 | defparam sub.FROM_DEFPARAM = 2; 14 | `hsub sub (/*AUTOINST*/ 15 | // Outputs 16 | .qvec (qvec[3:0]), 17 | // Inputs 18 | .avec ({avec[3],avec[2:0]}), 19 | .clk (1'b0)); 20 | 21 | missing missing (); 22 | 23 | v_recursive #(.DEPTH(3)) recursive (); 24 | 25 | // Width checks, bug65 26 | wire WC_w1; 27 | wire [0:0] WC_w1b; 28 | wire [2:0] WC_w3; 29 | wire [-1:2] WC_w4; 30 | localparam WC_p32=0; 31 | localparam [0:0] WC_p1=0; 32 | localparam [2:0] WC_p3=0; 33 | localparam [-1:2] WC_p4=0; 34 | localparam integer WC_pint=0; 35 | 36 | // Assignments 37 | wire asn_clk; 38 | assign asn_clk = clk; 39 | 40 | endmodule 41 | 42 | localparam GLOBAL_PARAM = 1; 43 | 44 | // Local Variables: 45 | // eval:(verilog-read-defines) 46 | // End: 47 | -------------------------------------------------------------------------------- /verilog/v_hier_top2.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2000-2012 by Wilson Snyder. 4 | 5 | module v_hier_top2 (/*AUTOARG*/ 6 | // Inputs 7 | clk 8 | ); 9 | input clk; 10 | 11 | v_hier_noport noport (); 12 | 13 | v_hier_noport #(.P(1)) noportp (); 14 | 15 | //bug1393 16 | v_hier_noport #(.P(1)) noporta[1:0] (); 17 | 18 | inout [2:0] iosig/* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/;/* synthesis aftersemi*/ // NetListName=F12_IO 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilog/v_recursive.v: -------------------------------------------------------------------------------- 1 | module v_recursive (); 2 | parameter DEPTH = 1; 3 | generate 4 | if (DEPTH > 1) begin : rec 5 | v_recursive #(.DEPTH(DEPTH-1)) recurse (); 6 | end 7 | endgenerate 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilog/v_sv_intf.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2009-2012 by Wilson Snyder. 4 | 5 | `include "v_sv_pkg.v" 6 | 7 | interface v_sv_intf; 8 | v_sv_pkg::byte_t byte_port; 9 | v_sv_intf2 subintf(.*); 10 | endinterface 11 | 12 | interface v_sv_intf2; 13 | v_sv_pkg::byte_t byte_port; 14 | modport Master(input data, output addr); 15 | endinterface 16 | -------------------------------------------------------------------------------- /verilog/v_sv_mod.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2009-2012 by Wilson Snyder. 4 | 5 | `include "v_sv_pkg" 6 | 7 | interface sv_if_ported (input clk); 8 | endinterface 9 | 10 | module v_sv_mod (v_sv_intf intf, input clk); 11 | 12 | // Import types 13 | import v_sv_pkg::*; 14 | 15 | // Internal interface (unconnected) 16 | sv_if_ported if_ported(.clk(clk)); 17 | 18 | // Grab a program 19 | v_sv_pgm pgm(); 20 | 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /verilog/v_sv_pgm.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2009-2012 by Wilson Snyder. 4 | 5 | program v_sv_pgm; 6 | int in_pgm; 7 | endprogram 8 | -------------------------------------------------------------------------------- /verilog/v_sv_pkg.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2009-2012 by Wilson Snyder. 4 | 5 | `ifndef _V_SV_PKG_ 6 | `define _V_SV_PKG_ 7 | 8 | package v_sv_pkg; 9 | typedef logic [7:0] byte_t; 10 | endpackage 11 | 12 | `endif // guard 13 | -------------------------------------------------------------------------------- /verilog/v_v2k.v: -------------------------------------------------------------------------------- 1 | // DESCRIPTION: Verilog-Perl: Example Verilog for testing package 2 | // This file ONLY is placed into the Public Domain, for any use, 3 | // without warranty, 2006-2012 by Wilson Snyder. 4 | 5 | module v_v2k 6 | #(parameter WIDTH = 16) ( 7 | input clk, 8 | input rst, 9 | input [WIDTH:0] sig1, 10 | output reg [WIDTH:0] sig2 11 | ); 12 | 13 | always @(clk) begin 14 | if (rst) begin 15 | sig2 <= #1 0; 16 | end 17 | else begin 18 | sig2 <= #1 sig1; 19 | end 20 | end 21 | 22 | // Multidim, bug1206 23 | wire [1:2] [3:4] netmd; 24 | v_v2k_sub sub (.net1 (netmd[1])); 25 | 26 | endmodule 27 | 28 | module v_v2k_sub 29 | ( 30 | input [3:4] net1 31 | ); 32 | endmodule 33 | -------------------------------------------------------------------------------- /vsplitmodule: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | # See copyright, etc in below POD section. 3 | ###################################################################### 4 | 5 | use lib 'blib/lib'; 6 | use Verilog::EditFiles; 7 | use FindBin qw($RealBin $RealScript $Script); 8 | use strict; 9 | 10 | #====================================================================== 11 | # When editing, delete this section up to the next #==== 12 | die <new 24 | (# Verilog::EditFiles will use the below program name in its comments 25 | program => $Script, 26 | 27 | # Name of the directory to write the output modules to. 28 | # I like to put all generated files under a dir named "gen" 29 | # so it is obvious the files are generated. 30 | # (But for the Verilog-Perl internal tests, this needs to be test_dir) 31 | outdir => "test_dir", #"gen", 32 | 33 | # If true, add "`celldefine" before every module statement. 34 | #celldefine => 1, 35 | 36 | # For the write_lint method, the name of the linter to use. 37 | #lint_command => 'vlint --brief', 38 | 39 | # If defined, add the provided text before every module statement. 40 | # Generally used to insert lint off pragmas. 41 | #lint_header => "// lint_checking MY_RULES OFF\n", 42 | 43 | # If defined, add the provided text before every module statement. 44 | # Generally used to insert lint off pragmas. 45 | #include_header => "`include \"my_defines.v\"\n", 46 | 47 | # If defined, add the provided text before every module statement. 48 | # Generally used to insert lint off pragmas. 49 | #timescale_header => "`include \"my_timescale.v\"\n", 50 | 51 | # If set, remove any `timescales. 52 | #timescale_removal => 1, 53 | 54 | # If 1, replace any synopsys translate on/offs with "`ifdef SYNTHESIS" and 55 | # "`endif"s. If set to a string, use that string instead of "SYNTHESIS". 56 | translate_synthesis => 'SYNTHESIS', 57 | 58 | # The suffix to add to convert a module name into a filename. Defaults to 59 | #v_suffix => '.v', 60 | 61 | # If set, show what files are being read and written 62 | verbose => 1, 63 | ); 64 | 65 | # Remove all existing files under the output. You might not want to do 66 | # this if there are files you want to keep from there 67 | unlink(glob("$split->{outdir}/*.v")); 68 | 69 | # Read specified libraries and split them 70 | $split->read_and_split(glob("t/*.v")); 71 | 72 | # And write them out 73 | $split->write_files(); 74 | 75 | # And create a lint file 76 | $split->write_lint(); 77 | 78 | # If a file needs 'manual' search and replaces, we can do that too. 79 | $split->edit_file 80 | (# The filename to be edited 81 | filename=>"$split->{outdir}/a.v", 82 | # Callback subroutine that takes file contents as a string 83 | # and returns the new file contents 84 | cb=>sub { 85 | my $wholefile = shift; 86 | # Globally search and comment out any lines with "pulldown PULLDOWN" 87 | # See "man perlre" for examples. 88 | # The %mg here means to match multiple lines (you can put 89 | # \n in the regexp), and to do it globally 90 | $wholefile =~ s%(pulldown PULLDOWN;)%//vsplitmodule: $1%mg; 91 | return $wholefile; 92 | }); 93 | --------------------------------------------------------------------------------