├── modules ├── clk │ └── vhdl │ │ ├── Manifest.py │ │ └── sys_pll.vhd ├── cordic │ └── vhdl │ │ ├── Manifest.py │ │ └── ahb3lite_cordic.vhd ├── cortex-m0 │ ├── vhdl │ │ ├── Manifest.py │ │ └── cortex_m0_wrapper.vhd │ └── verilog │ │ └── Manifest.py ├── memory │ ├── vhdl │ │ ├── Manifest.py │ │ └── rl_ram_1r1w_generic.vhd │ ├── memory_200_sim.mem │ ├── memory_1M_syn.mem │ ├── memory_busy_wait.mem │ ├── memory_interrupt_sim.mem │ ├── memory_interrupt_syn.mem │ ├── memory_dma_sim.mem │ ├── memory_dma_syn.mem │ └── memory_dummy.mem └── misc │ └── vhdl │ ├── Manifest.py │ ├── detection_fsm.vhd │ └── edge_detector.vhd ├── sim ├── kc705_dma │ └── run_dma_sim.tcl ├── kc705_blinky │ └── run_blinky_sim.tcl ├── kc705_busy_wait │ └── run_busy_wait_sim.tcl └── kc705_interrupt │ └── run_interrupt_sim.tcl ├── syn ├── kc705_dma │ └── verilog │ │ └── Manifest.py ├── kc705_blinky │ └── verilog │ │ └── Manifest.py ├── kc705_busy_wait │ └── verilog │ │ └── Manifest.py └── kc705_interruption │ └── verilog │ └── Manifest.py ├── top ├── kc705_blinky │ ├── verilog │ │ ├── Manifest.py │ │ └── cm0_blinky_top.sv │ └── cm0_blinky_top.xdc ├── kc705_busy_wait │ ├── verilog │ │ ├── Manifest.py │ │ └── cm0_busy_wait_top.sv │ └── cm0_busy_wait_top.xdc ├── kc705_interruption │ ├── verilog │ │ ├── Manifest.py │ │ └── cm0_interruption_top.sv │ └── cm0_interruption_top.xdc └── kc705_dma │ ├── verilog │ ├── Manifest.py │ └── cm0_dma_top.sv │ └── cm0_dma_top.xdc ├── .gitmodules ├── LICENSE ├── .gitignore └── README.md /modules/clk/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "sys_pll.vhd", 3 | ] 4 | 5 | -------------------------------------------------------------------------------- /modules/cordic/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "ahb3lite_cordic.vhd", 3 | ] 4 | -------------------------------------------------------------------------------- /modules/cortex-m0/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cortex_m0_wrapper.vhd", 3 | ] 4 | 5 | -------------------------------------------------------------------------------- /modules/memory/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "rl_ram_1r1w_generic.vhd", 3 | ] 4 | 5 | -------------------------------------------------------------------------------- /modules/misc/vhdl/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "detection_fsm.vhd", 3 | "edge_detector.vhd" 4 | ] 5 | 6 | -------------------------------------------------------------------------------- /modules/cortex-m0/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cortexm0ds_logic.v", 3 | "CORTEXM0INTEGRATION.v", 4 | ] 5 | 6 | -------------------------------------------------------------------------------- /sim/kc705_dma/run_dma_sim.tcl: -------------------------------------------------------------------------------- 1 | restart 2 | add_force {/cm0_dma_top/clk_200mhz} -radix hex {0 0ns} {1 2500ps} -repeat_every 5000ps 3 | add_force {/cm0_dma_top/push_button0_i} -radix hex {1 0ns} {0 10000000ps} -repeat_every 1000000000ps 4 | run 200us 5 | -------------------------------------------------------------------------------- /sim/kc705_blinky/run_blinky_sim.tcl: -------------------------------------------------------------------------------- 1 | restart 2 | add_force {/cm0_softmc_top/clk_200mhz} -radix hex {0 0ns} {1 2500ps} -repeat_every 5000ps 3 | add_force {/cm0_softmc_top/push_button0_i} -radix hex {1 0ns} {0 10000000ps} -repeat_every 1000000000ps 4 | run 400us 5 | -------------------------------------------------------------------------------- /sim/kc705_busy_wait/run_busy_wait_sim.tcl: -------------------------------------------------------------------------------- 1 | restart 2 | add_force {/cm0_busy_wait_top/clk_200mhz} -radix hex {0 0ns} {1 2500ps} -repeat_every 5000ps 3 | add_force {/cm0_busy_wait_top/push_button0_i} -radix hex {1 0ns} {0 10000000ps} -repeat_every 1000000000ps 4 | run 100us 5 | -------------------------------------------------------------------------------- /sim/kc705_interrupt/run_interrupt_sim.tcl: -------------------------------------------------------------------------------- 1 | restart 2 | add_force {/cm0_interruption_top/clk_200mhz} -radix hex {0 0ns} {1 2500ps} -repeat_every 5000ps 3 | add_force {/cm0_interruption_top/push_button0_i} -radix hex {1 0ns} {0 10000000ps} -repeat_every 1000000000ps 4 | run 100us 5 | -------------------------------------------------------------------------------- /syn/kc705_dma/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc7k325t" 5 | syn_grade = "-2" 6 | syn_package = "ffg900" 7 | syn_top = "cm0_dma_top" 8 | syn_project = "cm0_dma_top" 9 | syn_tool = "vivado" 10 | 11 | modules = { 12 | "local" : [ "../../../top/kc705_dma/verilog" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /syn/kc705_blinky/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc7k325t" 5 | syn_grade = "-2" 6 | syn_package = "ffg900" 7 | syn_top = "cm0_blinky_top" 8 | syn_project = "cm0_blinky_top" 9 | syn_tool = "vivado" 10 | 11 | modules = { 12 | "local" : [ "../../../top/kc705_blinky/verilog" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /syn/kc705_busy_wait/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc7k325t" 5 | syn_grade = "-2" 6 | syn_package = "ffg900" 7 | syn_top = "cm0_busy_wait_top" 8 | syn_project = "cm0_busy_wait_top" 9 | syn_tool = "vivado" 10 | 11 | modules = { 12 | "local" : [ "../../../top/kc705_busy_wait/verilog" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /syn/kc705_interruption/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | target = "xilinx" 2 | action = "synthesis" 3 | 4 | syn_device = "xc7k325t" 5 | syn_grade = "-2" 6 | syn_package = "ffg900" 7 | syn_top = "cm0_interruption_top" 8 | syn_project = "cm0_interruption_top" 9 | syn_tool = "vivado" 10 | 11 | modules = { 12 | "local" : [ "../../../top/kc705_interruption/verilog" ], 13 | } 14 | 15 | -------------------------------------------------------------------------------- /top/kc705_blinky/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cm0_blinky_top.sv", 3 | "../cm0_blinky_top.xdc", 4 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_master_port.sv", 5 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_slave_port.sv", 6 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect.sv", 7 | "../../../ip_cores/roa_logic/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv", 8 | "../../../ip_cores/roa_logic/ahb3lite_memory/rtl/verilog/ahb3lite_sram1rw.sv", 9 | "../../../ip_cores/roa_logic/memory/rtl/verilog/rl_ram_1r1w.sv", 10 | "../../../ip_cores/roa_logic/memory/rtl/verilog/rl_ram_1r1w_generic.sv", 11 | ] 12 | 13 | modules = { 14 | "local" : [ "../../../modules/cortex-m0/vhdl", 15 | "../../../modules/cortex-m0/verilog", 16 | "../../../modules/clk/vhdl", 17 | "../../../modules/memory/vhdl", 18 | "../../../ip_cores/general-cores", 19 | "../../../modules/misc/vhdl"], 20 | 21 | } 22 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "ip_cores/general-cores"] 2 | path = ip_cores/general-cores 3 | url = https://github.com/lnls-dig/general-cores.git 4 | [submodule "ip_cores/roa_logic/ahb3lite_interconnect"] 5 | path = ip_cores/roa_logic/ahb3lite_interconnect 6 | url = git@github.com:vfinotti/ahb3lite_interconnect.git 7 | [submodule "ip_cores/roa_logic/ahb3lite_memory"] 8 | path = ip_cores/roa_logic/ahb3lite_memory 9 | url = git@github.com:vfinotti/ahb3lite_memory.git 10 | [submodule "ip_cores/roa_logic/ahb3lite_pkg"] 11 | path = ip_cores/roa_logic/ahb3lite_pkg 12 | url = git@github.com:RoaLogic/ahb3lite_pkg.git 13 | [submodule "ip_cores/roa_logic/memory"] 14 | path = ip_cores/roa_logic/memory 15 | url = git@github.com:vfinotti/memory.git 16 | [submodule "ip_cores/vhdl-extras"] 17 | path = ip_cores/vhdl-extras 18 | url = git@github.com:vfinotti/vhdl-extras.git 19 | [submodule "ip_cores/roa_logic/ahb3lite_timer"] 20 | path = ip_cores/roa_logic/ahb3lite_timer 21 | url = https://github.com/vfinotti/ahb3lite_timer.git 22 | [submodule "ip_cores/ahb3lite_dma"] 23 | path = ip_cores/ahb3lite_dma 24 | url = git@github.com:vfinotti/ahb3lite_dma.git 25 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Vitor Finotti Ferreira 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /top/kc705_busy_wait/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cm0_busy_wait_top.sv", 3 | "../cm0_busy_wait_top.xdc", 4 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_master_port.sv", 5 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_slave_port.sv", 6 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect.sv", 7 | "../../../ip_cores/roa_logic/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv", 8 | "../../../ip_cores/roa_logic/ahb3lite_memory/rtl/verilog/ahb3lite_sram1rw.sv", 9 | "../../../ip_cores/roa_logic/memory/rtl/verilog/rl_ram_1r1w.sv", 10 | "../../../ip_cores/vhdl-extras/rtl/extras/cordic.vhdl", 11 | "../../../ip_cores/vhdl-extras/rtl/extras/pipelining.vhdl" 12 | ] 13 | 14 | modules = { 15 | "local" : [ "../../../modules/cortex-m0/vhdl", 16 | "../../../modules/cortex-m0/verilog", 17 | "../../../modules/clk/vhdl", 18 | "../../../modules/memory/vhdl", 19 | "../../../ip_cores/general-cores", 20 | "../../../modules/misc/vhdl", 21 | "../../../modules/cordic/vhdl"], 22 | 23 | } 24 | -------------------------------------------------------------------------------- /top/kc705_interruption/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cm0_interruption_top.sv", 3 | "../cm0_interruption_top.xdc", 4 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_master_port.sv", 5 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_slave_port.sv", 6 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect.sv", 7 | "../../../ip_cores/roa_logic/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv", 8 | "../../../ip_cores/roa_logic/ahb3lite_memory/rtl/verilog/ahb3lite_sram1rw.sv", 9 | "../../../ip_cores/roa_logic/memory/rtl/verilog/rl_ram_1r1w.sv", 10 | "../../../ip_cores/roa_logic/ahb3lite_timer/rtl/verilog/ahb3lite_timer.sv", 11 | "../../../ip_cores/vhdl-extras/rtl/extras/cordic.vhdl", 12 | "../../../ip_cores/vhdl-extras/rtl/extras/pipelining.vhdl" 13 | ] 14 | 15 | modules = { 16 | "local" : [ "../../../modules/cortex-m0/vhdl", 17 | "../../../modules/cortex-m0/verilog", 18 | "../../../modules/clk/vhdl", 19 | "../../../modules/memory/vhdl", 20 | "../../../ip_cores/general-cores", 21 | "../../../modules/misc/vhdl", 22 | "../../../modules/cordic/vhdl"], 23 | 24 | } 25 | -------------------------------------------------------------------------------- /top/kc705_dma/verilog/Manifest.py: -------------------------------------------------------------------------------- 1 | files = [ 2 | "cm0_dma_top.sv", 3 | "../cm0_dma_top.xdc", 4 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_master_port.sv", 5 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_slave_port.sv", 6 | "../../../ip_cores/roa_logic/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect.sv", 7 | "../../../ip_cores/roa_logic/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv", 8 | "../../../ip_cores/roa_logic/ahb3lite_memory/rtl/verilog/ahb3lite_sram1rw.sv", 9 | "../../../ip_cores/roa_logic/memory/rtl/verilog/rl_ram_1r1w.sv", 10 | "../../../ip_cores/roa_logic/ahb3lite_timer/rtl/verilog/ahb3lite_timer.sv", 11 | "../../../ip_cores/vhdl-extras/rtl/extras/cordic.vhdl", 12 | "../../../ip_cores/vhdl-extras/rtl/extras/pipelining.vhdl" 13 | ] 14 | 15 | modules = { 16 | "local" : [ "../../../modules/cortex-m0/vhdl", 17 | "../../../modules/cortex-m0/verilog", 18 | "../../../modules/clk/vhdl", 19 | "../../../modules/memory/vhdl", 20 | "../../../ip_cores/general-cores", 21 | "../../../modules/misc/vhdl", 22 | "../../../modules/cordic/vhdl", 23 | "../../../ip_cores/ahb3lite_dma"], 24 | 25 | } 26 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | ######################################################################################################### 3 | ## This is an example .gitignore file for Vivado, please treat it as an example as 4 | ## it might not be complete. In addition, XAPP 1165 should be followed. 5 | ######################################################################################################### 6 | 7 | ############# 8 | # Exclude all 9 | * 10 | !*/ 11 | !.gitignore 12 | ################ 13 | ## Source files: 14 | # Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. 15 | !*.vhd 16 | !*.v 17 | !*.sv 18 | # !*.bd 19 | # !*.edif 20 | ########### 21 | ## IP files 22 | #.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products 23 | #.xci + .dcp: implementation possible but not re-synthesis 24 | #*.xci(www.spiritconsortium.org) 25 | !*.xci 26 | #*.dcp(checkpoint files) 27 | # !*.dcp 28 | # !*.vds 29 | # !*.pb 30 | # All bd comments and layout coordinates are stored within .ui 31 | # !*.ui 32 | # !*.ooc 33 | ################### 34 | ## System Generator 35 | # !*.mdl 36 | # !*.slx 37 | # !*.bxml 38 | ############################ 39 | ## Simulation logic analyzer 40 | # !*.wcfg 41 | !*.coe 42 | ###### 43 | ## MIG 44 | # !*.prj 45 | !*.mem 46 | ################ 47 | ## Project files 48 | # XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) 49 | # Do NOT ignore *.xpr files 50 | # !*.xpr 51 | # Include *.xml files for 2013.4 or earlier version 52 | # !*.xml 53 | ################### 54 | ## Constraint files 55 | # Do NOT ignore *.xdc files 56 | !*.xdc 57 | ############# 58 | # TCL - files 59 | !*.tcl 60 | ################## 61 | ## Journal - files 62 | # !*.jou 63 | ########## 64 | ## Reports 65 | # !*.rpt 66 | !*.txt 67 | # !*.vdi 68 | ########## 69 | ## C-files 70 | !*.c 71 | !*.h 72 | !*.elf 73 | # !*.bmm 74 | # !*.xmp 75 | ########## 76 | ## Python files 77 | !*.py 78 | 79 | # ignoring files provided by ARM DesignStart program 80 | modules/cortex-m0/verilog/CORTEXM0INTEGRATION.v 81 | modules/cortex-m0/verilog/cortexm0ds_logic.v -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Cortex-M0 implementation on a Kintex-7 FPGA 2 | 3 | ## Overview 4 | Soft-microcontroller implementation of an ARM Cortex-M0 into a KC705. This project implements a design that contains the following components: 5 | 6 | - **Cortex-M0 obfuscated core**: core provided by the ARM DesignStart website 7 | - **RAM memory**: implementation of a RAM memory that accepts an initialization file 8 | - **AHB3-lite interconnection**: interconnection responsible for allowing the communication between masters and slaves in AHB3-lite protocol 9 | - **Pattern detector**: Core that implements a simple state machine that toggles its output when the pattern "f0f0f0f0" is seen on its input bus 10 | 11 | When the board is turned on, the cortex-m0 reads the RAM memory, which was synthesized with a program that counts up to a fixed number and then puts the pattern "f0f0f0f0" at the bus. This causes the pattern detector to toggle its output, which it connected to an LED. For the synthesis, the program is defined to count up to 10,000,000. For simulation purposes, a memory file with a program that counts up to 200 is available. 12 | 13 | ## Requirements 14 | The tools used in this project are listed below. However, it can be ported to different vendor/boards thanks to the flexibility provided by [hdlmake](https://www.ohwr.org/projects/hdl-make). 15 | - Vivado 16 | - KC705 Evaluation board 17 | - Hdlmake 18 | - ARM Cortex-M0 DesignStart processor, available at [ARM Design Start website](https://www.arm.com/resources/designstart) 19 | 20 | ## Instructions 21 | 22 | - Clone the repository with its submodules: 23 | ```sh 24 | $ git clone --recurse-submodules git@github.com:vfinotti/cortex-m0-soft-microcontroller.git 25 | ``` 26 | 27 | - Change the directory to the synthesis folder 28 | ```sh 29 | $ cd ./syn/kc705_blinky/verilog/ 30 | ``` 31 | - Copy the files "cortexm0ds_logic.v" and "CORTEXM0INTEGRATION.v" (obtained from the ARM DesignStart website) to *modules/cortex-m0/verilog/* 32 | 33 | - run hdlmake to generate the Makefile, and then make the project 34 | ```sh 35 | $ hdlmake 36 | $ make 37 | ``` 38 | 39 | 40 | ## References 41 | 1. : Project which inspired this work 42 | 2. : Cortex-M0 Technical Reference Manual 43 | 3. : AMBA 3 AHB-Lite Protocol Specification 44 | -------------------------------------------------------------------------------- /top/kc705_dma/cm0_dma_top.xdc: -------------------------------------------------------------------------------- 1 | #sysclk 2 | set_property PACKAGE_PIN AD11 [get_ports sys_clk_n_i] 3 | set_property IOSTANDARD LVDS [get_ports sys_clk_n_i] 4 | set_property PACKAGE_PIN AD12 [get_ports sys_clk_p_i] 5 | set_property IOSTANDARD LVDS [get_ports sys_clk_p_i] 6 | 7 | create_clock -period 5.000 -name sys_clk_p_i [get_ports sys_clk_p_i] 8 | set_clock_groups -asynchronous -group sys_clk_p_i 9 | 10 | # GPIO LEDs 11 | set_property PACKAGE_PIN AB8 [get_ports {led0}] 12 | set_property IOSTANDARD LVCMOS15 [get_ports {led0}] 13 | set_property PACKAGE_PIN AA8 [get_ports {led1}] 14 | set_property IOSTANDARD LVCMOS15 [get_ports {led1}] 15 | set_property PACKAGE_PIN AC9 [get_ports {led2}] 16 | set_property IOSTANDARD LVCMOS15 [get_ports {led2}] 17 | set_property PACKAGE_PIN AB9 [get_ports {led3}] 18 | set_property IOSTANDARD LVCMOS15 [get_ports {led3}] 19 | set_property PACKAGE_PIN AE26 [get_ports {led4}] 20 | set_property IOSTANDARD LVCMOS25 [get_ports {led4}] 21 | set_property PACKAGE_PIN G19 [get_ports {led5}] 22 | set_property IOSTANDARD LVCMOS25 [get_ports {led5}] 23 | set_property PACKAGE_PIN E18 [get_ports {led6}] 24 | set_property IOSTANDARD LVCMOS25 [get_ports {led6}] 25 | set_property PACKAGE_PIN F16 [get_ports {led7}] 26 | set_property IOSTANDARD LVCMOS25 [get_ports {led7}] 27 | 28 | # GPIO DIP SW 29 | ## SW0 30 | #set_property PACKAGE_PIN Y29 [get_ports {switches_i[0]}] 31 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[0]}] 32 | ## SW1 33 | #set_property PACKAGE_PIN W29 [get_ports {switches_i[1]}] 34 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[1]}] 35 | ## SW2 36 | #set_property PACKAGE_PIN AA28 [get_ports {switches_i[2]}] 37 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[2]}] 38 | ## SW3 39 | #set_property PACKAGE_PIN Y28 [get_ports {switches_i[3]}] 40 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[3]}] 41 | 42 | # GPIO PUSHBUTTON SW 43 | ## east 44 | set_property PACKAGE_PIN AG5 [get_ports {push_button0_i}] 45 | set_property IOSTANDARD LVCMOS15 [get_ports {push_button0_i}] 46 | ## center 47 | #set_property PACKAGE_PIN G12 [get_ports {push_buttons_i[1]}] 48 | #set_property IOSTANDARD LVCMOS25 [get_ports {push_buttons_i[1]}] 49 | ## west 50 | #set_property PACKAGE_PIN AC6 [get_ports {push_buttons_i[2]}] 51 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[2]}] 52 | ## north 53 | #set_property PACKAGE_PIN AA12 [get_ports {push_buttons_i[3]}] 54 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[3]}] 55 | ## south 56 | #set_property PACKAGE_PIN AB12 [get_ports {push_buttons_i[4]}] 57 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[4]}] 58 | -------------------------------------------------------------------------------- /top/kc705_blinky/cm0_blinky_top.xdc: -------------------------------------------------------------------------------- 1 | #sysclk 2 | set_property PACKAGE_PIN AD11 [get_ports sys_clk_n_i] 3 | set_property IOSTANDARD LVDS [get_ports sys_clk_n_i] 4 | set_property PACKAGE_PIN AD12 [get_ports sys_clk_p_i] 5 | set_property IOSTANDARD LVDS [get_ports sys_clk_p_i] 6 | 7 | create_clock -period 5.000 -name sys_clk_p_i [get_ports sys_clk_p_i] 8 | set_clock_groups -asynchronous -group sys_clk_p_i 9 | 10 | # GPIO LEDs 11 | set_property PACKAGE_PIN AB8 [get_ports {led0}] 12 | set_property IOSTANDARD LVCMOS15 [get_ports {led0}] 13 | set_property PACKAGE_PIN AA8 [get_ports {led1}] 14 | set_property IOSTANDARD LVCMOS15 [get_ports {led1}] 15 | set_property PACKAGE_PIN AC9 [get_ports {led2}] 16 | set_property IOSTANDARD LVCMOS15 [get_ports {led2}] 17 | set_property PACKAGE_PIN AB9 [get_ports {led3}] 18 | set_property IOSTANDARD LVCMOS15 [get_ports {led3}] 19 | set_property PACKAGE_PIN AE26 [get_ports {led4}] 20 | set_property IOSTANDARD LVCMOS25 [get_ports {led4}] 21 | set_property PACKAGE_PIN G19 [get_ports {led5}] 22 | set_property IOSTANDARD LVCMOS25 [get_ports {led5}] 23 | set_property PACKAGE_PIN E18 [get_ports {led6}] 24 | set_property IOSTANDARD LVCMOS25 [get_ports {led6}] 25 | set_property PACKAGE_PIN F16 [get_ports {led7}] 26 | set_property IOSTANDARD LVCMOS25 [get_ports {led7}] 27 | 28 | # GPIO DIP SW 29 | ## SW0 30 | #set_property PACKAGE_PIN Y29 [get_ports {switches_i[0]}] 31 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[0]}] 32 | ## SW1 33 | #set_property PACKAGE_PIN W29 [get_ports {switches_i[1]}] 34 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[1]}] 35 | ## SW2 36 | #set_property PACKAGE_PIN AA28 [get_ports {switches_i[2]}] 37 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[2]}] 38 | ## SW3 39 | #set_property PACKAGE_PIN Y28 [get_ports {switches_i[3]}] 40 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[3]}] 41 | 42 | # GPIO PUSHBUTTON SW 43 | ## east 44 | set_property PACKAGE_PIN AG5 [get_ports {push_button0_i}] 45 | set_property IOSTANDARD LVCMOS15 [get_ports {push_button0_i}] 46 | ## center 47 | #set_property PACKAGE_PIN G12 [get_ports {push_buttons_i[1]}] 48 | #set_property IOSTANDARD LVCMOS25 [get_ports {push_buttons_i[1]}] 49 | ## west 50 | #set_property PACKAGE_PIN AC6 [get_ports {push_buttons_i[2]}] 51 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[2]}] 52 | ## north 53 | #set_property PACKAGE_PIN AA12 [get_ports {push_buttons_i[3]}] 54 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[3]}] 55 | ## south 56 | #set_property PACKAGE_PIN AB12 [get_ports {push_buttons_i[4]}] 57 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[4]}] 58 | -------------------------------------------------------------------------------- /top/kc705_busy_wait/cm0_busy_wait_top.xdc: -------------------------------------------------------------------------------- 1 | #sysclk 2 | set_property PACKAGE_PIN AD11 [get_ports sys_clk_n_i] 3 | set_property IOSTANDARD LVDS [get_ports sys_clk_n_i] 4 | set_property PACKAGE_PIN AD12 [get_ports sys_clk_p_i] 5 | set_property IOSTANDARD LVDS [get_ports sys_clk_p_i] 6 | 7 | create_clock -period 5.000 -name sys_clk_p_i [get_ports sys_clk_p_i] 8 | set_clock_groups -asynchronous -group sys_clk_p_i 9 | 10 | # GPIO LEDs 11 | set_property PACKAGE_PIN AB8 [get_ports {led0}] 12 | set_property IOSTANDARD LVCMOS15 [get_ports {led0}] 13 | set_property PACKAGE_PIN AA8 [get_ports {led1}] 14 | set_property IOSTANDARD LVCMOS15 [get_ports {led1}] 15 | set_property PACKAGE_PIN AC9 [get_ports {led2}] 16 | set_property IOSTANDARD LVCMOS15 [get_ports {led2}] 17 | set_property PACKAGE_PIN AB9 [get_ports {led3}] 18 | set_property IOSTANDARD LVCMOS15 [get_ports {led3}] 19 | set_property PACKAGE_PIN AE26 [get_ports {led4}] 20 | set_property IOSTANDARD LVCMOS25 [get_ports {led4}] 21 | set_property PACKAGE_PIN G19 [get_ports {led5}] 22 | set_property IOSTANDARD LVCMOS25 [get_ports {led5}] 23 | set_property PACKAGE_PIN E18 [get_ports {led6}] 24 | set_property IOSTANDARD LVCMOS25 [get_ports {led6}] 25 | set_property PACKAGE_PIN F16 [get_ports {led7}] 26 | set_property IOSTANDARD LVCMOS25 [get_ports {led7}] 27 | 28 | # GPIO DIP SW 29 | ## SW0 30 | #set_property PACKAGE_PIN Y29 [get_ports {switches_i[0]}] 31 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[0]}] 32 | ## SW1 33 | #set_property PACKAGE_PIN W29 [get_ports {switches_i[1]}] 34 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[1]}] 35 | ## SW2 36 | #set_property PACKAGE_PIN AA28 [get_ports {switches_i[2]}] 37 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[2]}] 38 | ## SW3 39 | #set_property PACKAGE_PIN Y28 [get_ports {switches_i[3]}] 40 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[3]}] 41 | 42 | # GPIO PUSHBUTTON SW 43 | ## east 44 | set_property PACKAGE_PIN AG5 [get_ports {push_button0_i}] 45 | set_property IOSTANDARD LVCMOS15 [get_ports {push_button0_i}] 46 | ## center 47 | #set_property PACKAGE_PIN G12 [get_ports {push_buttons_i[1]}] 48 | #set_property IOSTANDARD LVCMOS25 [get_ports {push_buttons_i[1]}] 49 | ## west 50 | #set_property PACKAGE_PIN AC6 [get_ports {push_buttons_i[2]}] 51 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[2]}] 52 | ## north 53 | #set_property PACKAGE_PIN AA12 [get_ports {push_buttons_i[3]}] 54 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[3]}] 55 | ## south 56 | #set_property PACKAGE_PIN AB12 [get_ports {push_buttons_i[4]}] 57 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[4]}] 58 | -------------------------------------------------------------------------------- /top/kc705_interruption/cm0_interruption_top.xdc: -------------------------------------------------------------------------------- 1 | #sysclk 2 | set_property PACKAGE_PIN AD11 [get_ports sys_clk_n_i] 3 | set_property IOSTANDARD LVDS [get_ports sys_clk_n_i] 4 | set_property PACKAGE_PIN AD12 [get_ports sys_clk_p_i] 5 | set_property IOSTANDARD LVDS [get_ports sys_clk_p_i] 6 | 7 | create_clock -period 5.000 -name sys_clk_p_i [get_ports sys_clk_p_i] 8 | set_clock_groups -asynchronous -group sys_clk_p_i 9 | 10 | # GPIO LEDs 11 | set_property PACKAGE_PIN AB8 [get_ports {led0}] 12 | set_property IOSTANDARD LVCMOS15 [get_ports {led0}] 13 | set_property PACKAGE_PIN AA8 [get_ports {led1}] 14 | set_property IOSTANDARD LVCMOS15 [get_ports {led1}] 15 | set_property PACKAGE_PIN AC9 [get_ports {led2}] 16 | set_property IOSTANDARD LVCMOS15 [get_ports {led2}] 17 | set_property PACKAGE_PIN AB9 [get_ports {led3}] 18 | set_property IOSTANDARD LVCMOS15 [get_ports {led3}] 19 | set_property PACKAGE_PIN AE26 [get_ports {led4}] 20 | set_property IOSTANDARD LVCMOS25 [get_ports {led4}] 21 | set_property PACKAGE_PIN G19 [get_ports {led5}] 22 | set_property IOSTANDARD LVCMOS25 [get_ports {led5}] 23 | set_property PACKAGE_PIN E18 [get_ports {led6}] 24 | set_property IOSTANDARD LVCMOS25 [get_ports {led6}] 25 | set_property PACKAGE_PIN F16 [get_ports {led7}] 26 | set_property IOSTANDARD LVCMOS25 [get_ports {led7}] 27 | 28 | # GPIO DIP SW 29 | ## SW0 30 | #set_property PACKAGE_PIN Y29 [get_ports {switches_i[0]}] 31 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[0]}] 32 | ## SW1 33 | #set_property PACKAGE_PIN W29 [get_ports {switches_i[1]}] 34 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[1]}] 35 | ## SW2 36 | #set_property PACKAGE_PIN AA28 [get_ports {switches_i[2]}] 37 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[2]}] 38 | ## SW3 39 | #set_property PACKAGE_PIN Y28 [get_ports {switches_i[3]}] 40 | #set_property IOSTANDARD LVCMOS25 [get_ports {switches_i[3]}] 41 | 42 | # GPIO PUSHBUTTON SW 43 | ## east 44 | set_property PACKAGE_PIN AG5 [get_ports {push_button0_i}] 45 | set_property IOSTANDARD LVCMOS15 [get_ports {push_button0_i}] 46 | ## center 47 | #set_property PACKAGE_PIN G12 [get_ports {push_buttons_i[1]}] 48 | #set_property IOSTANDARD LVCMOS25 [get_ports {push_buttons_i[1]}] 49 | ## west 50 | #set_property PACKAGE_PIN AC6 [get_ports {push_buttons_i[2]}] 51 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[2]}] 52 | ## north 53 | #set_property PACKAGE_PIN AA12 [get_ports {push_buttons_i[3]}] 54 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[3]}] 55 | ## south 56 | #set_property PACKAGE_PIN AB12 [get_ports {push_buttons_i[4]}] 57 | #set_property IOSTANDARD LVCMOS15 [get_ports {push_buttons_i[4]}] 58 | -------------------------------------------------------------------------------- /modules/misc/vhdl/detection_fsm.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Vitor Finotti 3 | -- 4 | -- https://github.com/vfinotti/cortex-m0-soft-microcontroller 5 | ------------------------------------------------------------------------------- 6 | -- 7 | -- unit name: Pattern Detector 8 | -- 9 | -- description: 10 | -- 11 | -- Detects if a specific pattern is seen on the data input. If so, 12 | -- permanently asserts an output, only resetting it if the block is reset. As 13 | -- a mesure to avoid toggling when not intended (this happpens because the 14 | -- pattern appears more than once due to the pipelined nature of the 15 | -- microcontroller), the next toggle must wait at least 10 clock cycles after 16 | -- the previous. 17 | -- 18 | ------------------------------------------------------------------------------- 19 | -- Copyright (c) 2018 Vitor Finotti 20 | ------------------------------------------------------------------------------- 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | use ieee.numeric_std.all; 25 | 26 | entity detection_fsm is 27 | 28 | port ( 29 | clk_i : in std_logic; 30 | rst_i : in std_logic; 31 | data_i : in std_logic_vector(31 downto 0); 32 | detected_o : out std_logic); 33 | 34 | end entity detection_fsm; 35 | 36 | architecture rtl of detection_fsm is 37 | 38 | type state_t is (state_on, state_off); 39 | 40 | signal present_state : state_t := state_off; 41 | 42 | begin -- architecture rtl 43 | 44 | -- purpose: asserting port detected_o as '1' if pattern is detected 45 | -- type : sequential 46 | -- inputs : clk_i, rst_i, data_i 47 | -- outputs: detected_o 48 | 49 | detection : process (clk_i) 50 | variable cycles_after_toggle : integer range 0 to 10; 51 | begin 52 | if rising_edge(clk_i) then -- rising clock edge 53 | if rst_i = '1' then -- synchronous reset (active high) 54 | present_state <= state_off; 55 | cycles_after_toggle := 0; 56 | else 57 | if cycles_after_toggle < 10 then 58 | cycles_after_toggle := cycles_after_toggle + 1; 59 | end if; 60 | 61 | case present_state is 62 | 63 | when state_off => 64 | if data_i = x"f0f0f0f0" and cycles_after_toggle = 10 then 65 | present_state <= state_on; 66 | cycles_after_toggle := 0; 67 | detected_o <= '1'; 68 | else 69 | present_state <= state_off; 70 | detected_o <= '0'; 71 | end if; 72 | 73 | when state_on => 74 | if data_i = x"f0f0f0f0" and cycles_after_toggle = 10 then 75 | present_state <= state_off; 76 | cycles_after_toggle := 0; 77 | detected_o <= '0'; 78 | else 79 | present_state <= state_on; 80 | detected_o <= '1'; 81 | end if; 82 | 83 | when others => 84 | detected_o <= '0'; 85 | cycles_after_toggle := 0; 86 | present_state <= state_off; 87 | end case; 88 | end if; 89 | end if; 90 | end process detection; 91 | 92 | 93 | end architecture rtl; 94 | -------------------------------------------------------------------------------- /modules/misc/vhdl/edge_detector.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Vitor Finotti 3 | -- 4 | -- 5 | ------------------------------------------------------------------------------- 6 | -- 7 | -- unit name: Rising or falling edge detector 8 | -- 9 | -- description: 10 | -- 11 | -- 12 | -- 13 | ------------------------------------------------------------------------------- 14 | -- Copyright (c) 2019 Vitor Finotti 15 | ------------------------------------------------------------------------------- 16 | -- MIT 17 | ------------------------------------------------------------------------------- 18 | -- Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | -- this software and associated documentation files (the "Software"), to deal in 20 | -- the Software without restriction, including without limitation the rights to 21 | -- use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | -- of the Software, and to permit persons to whom the Software is furnished to do 23 | -- so, subject to the following conditions: 24 | 25 | -- The above copyright notice and this permission notice shall be included in all 26 | -- copies or substantial portions of the Software. 27 | 28 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 29 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 30 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 31 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 32 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 33 | -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 | -- SOFTWARE. 35 | ------------------------------------------------------------------------------- 36 | 37 | library ieee; 38 | use ieee.std_logic_1164.all; 39 | use ieee.numeric_std.all; 40 | 41 | entity edge_detector is 42 | 43 | generic ( 44 | g_edge_type : string := "rising"); -- rising or falling 45 | 46 | port ( 47 | clk_i : in std_logic; 48 | rst_i : in std_logic; 49 | signal_i : in std_logic; 50 | edge_detected_o : out std_logic); 51 | 52 | end entity edge_detector; 53 | 54 | architecture rtl of edge_detector is 55 | 56 | signal detection_stages : std_logic_vector(1 downto 0) := "00"; 57 | signal edge_pattern : std_logic_vector(1 downto 0); 58 | 59 | 60 | begin -- architecture rtl 61 | 62 | -- setting edge pattern to rising "01" or falling "10" 63 | edge_pattern <= "01" when g_edge_type = "rising" 64 | else "10" when g_edge_type = "falling" 65 | else "00"; 66 | 67 | pulse_detection : process (clk_i, rst_i) is 68 | begin 69 | if rst_i = '1' then 70 | detection_stages <= "00"; 71 | edge_detected_o <= '0'; 72 | elsif rising_edge(clk_i) then 73 | if detection_stages = edge_pattern then 74 | edge_detected_o <= '1'; 75 | else 76 | edge_detected_o <= '0'; 77 | end if; 78 | detection_stages(0) <= signal_i; 79 | detection_stages(1) <= detection_stages(0); 80 | end if; 81 | end process pulse_detection; 82 | 83 | end architecture rtl; 84 | -------------------------------------------------------------------------------- /modules/memory/memory_200_sim.mem: -------------------------------------------------------------------------------- 1 | 00000000000000000000100000000000 2 | 00000000000000000000000011000001 3 | 00000000000000000000000100000101 4 | 00000000000000000000000100000101 5 | 00000000000000000000000000000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000100000101 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000100000101 16 | 00000000000000000000000100000101 17 | 00000000000000000000000100000101 18 | 00000000000000000000000100000101 19 | 00000000000000000000000100000101 20 | 00000000000000000000000100000101 21 | 00000000000000000000000100000101 22 | 00000000000000000000000100000101 23 | 00000000000000000000000100000101 24 | 00000000000000000000000100000101 25 | 00000000000000000000000100000101 26 | 00000000000000000000000100000101 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | 00000000000000000000000000000000 35 | 00000000000000000000000000000000 36 | 00000000000000000000000000000000 37 | 00000000000000000000000000000000 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000000000 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | 00000000000000000000000000000000 45 | 00000000000000000000000000000000 46 | 00000000000000000000000000000000 47 | 00000000000000000000000000000000 48 | 00000000000000000000000000000000 49 | 10110000100000101011010110000000 50 | 01001011000011001010111100000000 51 | 01001011000011000110000001111011 52 | 11100000000001110110000000111011 53 | 00011101000100110110100001111010 54 | 01101000001110110110000001111011 55 | 01100000001110010001110100011001 56 | 01100000000110100110100000010010 57 | 01001011000001110110100000111010 58 | 11010011111100110100001010011010 59 | 11111000000111001111000000000000 60 | 11111000001001101111000000000000 61 | 01000110101111010100011011000000 62 | 10111101100000001011000000000010 63 | 00000000000000000000000101110100 64 | 00000000000000000000010000000000 65 | 00000000000000000000010000000100 66 | 10101111000000001011010110000000 67 | 01000110110000001110011111111110 68 | 10101111000000001011010110000000 69 | 01001010000000110100101100000010 70 | 01000110110000000110000000011010 71 | 10111101100000000100011010111101 72 | 00000000000000000000010000000000 73 | 00000000010011000100101101000000 74 | 10101111000000001011010110000000 75 | 01001010000000110100101100000010 76 | 01000110110000000110000000011010 77 | 10111101100000000100011010111101 78 | 00000000000000000000010000000000 79 | 00000000010011000100101101000000 80 | 10110000100001001011010110000000 81 | 00100011110010001010111100000000 82 | 00100011000000000110000001111011 83 | 00100011000000000110000011111011 84 | 11100000000001010110000010111011 85 | 00110011000000010110100011111011 86 | 01101000101110110110000011111011 87 | 01100000101110110011001100000001 88 | 01101000011110110110100010111010 89 | 11010011111101010100001010011010 90 | 01100000001110110100101100000010 91 | 00110011000000010110100000111011 92 | 11100111111010100110000000111011 93 | 11110000111100001111000011110000 94 | 00000000010011000100101101000000 95 | -------------------------------------------------------------------------------- /modules/memory/memory_1M_syn.mem: -------------------------------------------------------------------------------- 1 | 00000000000000000000100000000000 2 | 00000000000000000000000011000001 3 | 00000000000000000000000100000101 4 | 00000000000000000000000100000101 5 | 00000000000000000000000000000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000100000101 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000100000101 16 | 00000000000000000000000100000101 17 | 00000000000000000000000100000101 18 | 00000000000000000000000100000101 19 | 00000000000000000000000100000101 20 | 00000000000000000000000100000101 21 | 00000000000000000000000100000101 22 | 00000000000000000000000100000101 23 | 00000000000000000000000100000101 24 | 00000000000000000000000100000101 25 | 00000000000000000000000100000101 26 | 00000000000000000000000100000101 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | 00000000000000000000000000000000 35 | 00000000000000000000000000000000 36 | 00000000000000000000000000000000 37 | 00000000000000000000000000000000 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000000000 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | 00000000000000000000000000000000 45 | 00000000000000000000000000000000 46 | 00000000000000000000000000000000 47 | 00000000000000000000000000000000 48 | 00000000000000000000000000000000 49 | 10110000100000101011010110000000 50 | 01001011000011001010111100000000 51 | 01001011000011000110000001111011 52 | 11100000000001110110000000111011 53 | 00011101000100110110100001111010 54 | 01101000001110110110000001111011 55 | 01100000001110010001110100011001 56 | 01100000000110100110100000010010 57 | 01001011000001110110100000111010 58 | 11010011111100110100001010011010 59 | 11111000000111001111000000000000 60 | 11111000001001101111000000000000 61 | 01000110101111010100011011000000 62 | 10111101100000001011000000000010 63 | 00000000000000000000000101111000 64 | 00000000000000000000010000000000 65 | 00000000000000000000010000000100 66 | 10101111000000001011010110000000 67 | 01000110110000001110011111111110 68 | 10101111000000001011010110000000 69 | 01001010000000110100101100000010 70 | 01000110110000000110000000011010 71 | 10111101100000000100011010111101 72 | 00000000000000000000010000000000 73 | 00000000010011000100101101000000 74 | 10101111000000001011010110000000 75 | 01001010000000110100101100000010 76 | 01000110110000000110000000011010 77 | 10111101100000000100011010111101 78 | 00000000000000000000010000000000 79 | 00000000010011000100101101000000 80 | 10110000100001001011010110000000 81 | 01001011000010111010111100000000 82 | 00100011000000000110000001111011 83 | 00100011000000000110000011111011 84 | 11100000000001010110000010111011 85 | 00110011000000010110100011111011 86 | 01101000101110110110000011111011 87 | 01100000101110110011001100000001 88 | 01101000011110110110100010111010 89 | 11010011111101010100001010011010 90 | 01100000001110110100101100000011 91 | 00110011000000010110100000111011 92 | 11100111111010100110000000111011 93 | 00000000000011110100001001000000 94 | 11110000111100001111000011110000 95 | 00000000010011000100101101000000 96 | -------------------------------------------------------------------------------- /modules/memory/vhdl/rl_ram_1r1w_generic.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Vitor Finotti 3 | -- 4 | -- 5 | ------------------------------------------------------------------------------- 6 | -- 7 | -- unit name: RAM memory with file initialization 8 | -- 9 | -- description: 10 | -- 11 | -- 12 | -- 13 | ------------------------------------------------------------------------------- 14 | -- Copyright (c) 2019 Vitor Finotti 15 | ------------------------------------------------------------------------------- 16 | -- MIT 17 | ------------------------------------------------------------------------------- 18 | -- Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | -- this software and associated documentation files (the "Software"), to deal in 20 | -- the Software without restriction, including without limitation the rights to 21 | -- use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | -- of the Software, and to permit persons to whom the Software is furnished to do 23 | -- so, subject to the following conditions: 24 | 25 | -- The above copyright notice and this permission notice shall be included in all 26 | -- copies or substantial portions of the Software. 27 | 28 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 29 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 30 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 31 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 32 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 33 | -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 | -- SOFTWARE. 35 | ------------------------------------------------------------------------------- 36 | 37 | library ieee; 38 | use ieee.std_logic_1164.all; 39 | use ieee.numeric_std.all; 40 | use std.textio.all; 41 | 42 | entity rl_ram_1r1w_generic is 43 | 44 | generic ( 45 | ABITS : natural := 10; 46 | DBITS : natural := 32; 47 | INIT_FILE : string := ""); 48 | port ( 49 | clk_i : in std_logic; 50 | rst_ni : in std_logic; 51 | waddr_i : in std_logic_vector(ABITS-1 downto 0); 52 | din_i : in std_logic_vector(DBITS-1 downto 0); 53 | we_i : in std_logic; 54 | be_i : in std_logic_vector((DBITS+7)/8-1 downto 0); 55 | raddr_i : in std_logic_vector(DBITS-1 downto 0); 56 | dout_o : out std_logic_vector(DBITS-1 downto 0)); 57 | 58 | end entity rl_ram_1r1w_generic; 59 | 60 | architecture rtl of rl_ram_1r1w_generic is 61 | 62 | type RamType is array (0 to (2**ABITS-1)) of bit_vector(DBITS-1 downto 0); 63 | 64 | -- Function that loads RAM values from file 65 | impure function InitRamFromFile (RamFileName : in string) return RamType is 66 | file RamFile : text is in RamFileName; 67 | variable RamFileLine : line; 68 | variable RAM : RamType; 69 | begin 70 | for I in RamType'range loop 71 | readline(RamFile, RamFileLine); 72 | read(RamFileLine, RAM(I)); 73 | end loop; 74 | return RAM; 75 | end function; 76 | 77 | -- Function to evaluate if there is a init file mentioned and use 78 | -- InitRamFromFile if so 79 | impure function InitRam (RamFileName : in string) return RamType is 80 | variable RAM : RamType; 81 | begin 82 | if RamFileName /= "" then 83 | RAM := InitRamFromFile(RamFileName); 84 | else 85 | RAM := (others => (others => '0')); 86 | end if; 87 | return RAM; 88 | end function; 89 | 90 | signal RAM : RamType := InitRam(INIT_FILE); 91 | 92 | 93 | begin -- architecture rtl 94 | 95 | -- purpose: Write and read data to RAM 96 | -- type : sequential 97 | -- inputs : clk_i, rst_ni 98 | -- outputs: 99 | ram_process : process (clk_i) is 100 | begin -- process ram_process 101 | if rising_edge(clk_i) then 102 | if we_i = '1' then 103 | RAM(to_integer(unsigned(waddr_i))) <= to_bitvector(din_i); 104 | end if; 105 | end if; 106 | end process ram_process; 107 | 108 | dout_o <= to_stdlogicvector(RAM(to_integer(unsigned(waddr_i)))); 109 | 110 | 111 | end architecture rtl; 112 | -------------------------------------------------------------------------------- /modules/memory/memory_busy_wait.mem: -------------------------------------------------------------------------------- 1 | 00000000000000000000100000000000 2 | 00000000000000000000000011000001 3 | 00000000000000000000000100000101 4 | 00000000000000000000000100000101 5 | 00000000000000000000000000000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000100000101 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000100000101 16 | 00000000000000000000000100000101 17 | 00000000000000000000000100000101 18 | 00000000000000000000000100000101 19 | 00000000000000000000000100000101 20 | 00000000000000000000000100000101 21 | 00000000000000000000000100000101 22 | 00000000000000000000000100000101 23 | 00000000000000000000000100000101 24 | 00000000000000000000000100000101 25 | 00000000000000000000000100000101 26 | 00000000000000000000000100000101 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 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-------------------------------------------------------------------------------- /modules/clk/vhdl/sys_pll.vhd: -------------------------------------------------------------------------------- 1 | -- MMCM_BASE : In order to incorporate this function into the design, 2 | -- VHDL : the following instance declaration needs to be placed 3 | -- instance : in the body of the design code. The instance name 4 | -- declaration : (MMCM_BASE_inst) and/or the port declarations after the 5 | -- code : "=>" declaration maybe changed to properly reference and 6 | -- : connect this function to the design. All inputs and outputs 7 | -- : must be connected. 8 | 9 | -- Library : In addition to adding the instance declaration, a use 10 | -- declaration : statement for the UNISIM.vcomponents library needs to be 11 | -- for : added before the entity declaration. This library 12 | -- Xilinx : contains the component declarations for all Xilinx 13 | -- primitives : primitives and points to the models that will be used 14 | -- : for simulation. 15 | 16 | -- Copy the following two statements and paste them before the 17 | -- Entity declaration, unless they already exist. 18 | 19 | library UNISIM; 20 | use UNISIM.vcomponents.all; 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | 25 | entity sys_pll is 26 | generic( 27 | -- 200 MHz input clock 28 | g_clkin_period : real := 5.000; 29 | g_divclk_divide : integer := 1; 30 | g_clkbout_mult_f : integer := 5; 31 | 32 | -- Reference jitter 33 | g_ref_jitter : real := 0.010; 34 | 35 | -- 100 MHz output clock 36 | g_clk0_divide_f : integer := 10; 37 | -- 200 MHz output clock 38 | g_clk1_divide : integer := 5; 39 | g_clk2_divide : integer := 6 40 | ); 41 | port( 42 | rst_i : in std_logic := '0'; 43 | clk_i : in std_logic := '0'; 44 | clk0_o : out std_logic; 45 | clk1_o : out std_logic; 46 | clk2_o : out std_logic; 47 | locked_o : out std_logic 48 | ); 49 | end sys_pll; 50 | 51 | architecture syn of sys_pll is 52 | 53 | signal s_mmcm_fbin : std_logic; 54 | signal s_mmcm_fbout : std_logic; 55 | 56 | signal s_clk0 : std_logic; 57 | signal s_clk1 : std_logic; 58 | signal s_clk2 : std_logic; 59 | begin 60 | 61 | -- Clock PLL 62 | cmp_sys_pll : PLLE2_ADV 63 | generic map ( 64 | BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW 65 | CLKFBOUT_MULT => g_clkbout_mult_f, -- Multiply value for all CLKOUT, (2-64) 66 | CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000). 67 | -- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz). 68 | CLKIN1_PERIOD => g_clkin_period, 69 | CLKIN2_PERIOD => g_clkin_period, 70 | -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128) 71 | CLKOUT0_DIVIDE => g_clk0_divide_f, 72 | CLKOUT1_DIVIDE => g_clk1_divide, 73 | CLKOUT2_DIVIDE => g_clk2_divide, 74 | CLKOUT3_DIVIDE => 1, 75 | CLKOUT4_DIVIDE => 1, 76 | CLKOUT5_DIVIDE => 1, 77 | -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999). 78 | CLKOUT0_DUTY_CYCLE => 0.5, 79 | CLKOUT1_DUTY_CYCLE => 0.5, 80 | CLKOUT2_DUTY_CYCLE => 0.5, 81 | CLKOUT3_DUTY_CYCLE => 0.5, 82 | CLKOUT4_DUTY_CYCLE => 0.5, 83 | CLKOUT5_DUTY_CYCLE => 0.5, 84 | -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000). 85 | CLKOUT0_PHASE => 0.0, 86 | CLKOUT1_PHASE => 0.0, 87 | CLKOUT2_PHASE => 0.0, 88 | CLKOUT3_PHASE => 0.0, 89 | CLKOUT4_PHASE => 0.0, 90 | CLKOUT5_PHASE => 0.0, 91 | COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL 92 | DIVCLK_DIVIDE => g_divclk_divide, -- Master division value (1-56) 93 | -- REF_JITTER: Reference input jitter in UI (0.000-0.999). 94 | REF_JITTER1 => g_ref_jitter, 95 | REF_JITTER2 => g_ref_jitter, 96 | STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE") 97 | ) 98 | port map ( 99 | -- Clock Outputs: 1-bit (each) output: User configurable clock outputs 100 | CLKOUT0 => s_clk0, -- 1-bit output: CLKOUT0 101 | CLKOUT1 => s_clk1, -- 1-bit output: CLKOUT1 102 | CLKOUT2 => s_clk2, -- 1-bit output: CLKOUT2 103 | CLKOUT3 => open, -- 1-bit output: CLKOUT3 104 | CLKOUT4 => open, -- 1-bit output: CLKOUT4 105 | CLKOUT5 => open, -- 1-bit output: CLKOUT5 106 | -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports 107 | DO => open, -- 16-bit output: DRP data 108 | DRDY => open, -- 1-bit output: DRP ready 109 | -- Feedback Clocks: 1-bit (each) output: Clock feedback ports 110 | CLKFBOUT => s_mmcm_fbout, -- 1-bit output: Feedback clock 111 | LOCKED => locked_o, -- 1-bit output: LOCK 112 | -- Clock Inputs: 1-bit (each) input: Clock inputs 113 | CLKIN1 => clk_i, -- 1-bit input: Primary clock 114 | CLKIN2 => '0', -- 1-bit input: Secondary clock 115 | -- Control Ports: 1-bit (each) input: PLL control ports 116 | CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2 117 | PWRDWN => '0', -- 1-bit input: Power-down 118 | RST => rst_i, -- 1-bit input: Reset 119 | -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports 120 | DADDR => (others => '0'), -- 7-bit input: DRP address 121 | DCLK => '0', -- 1-bit input: DRP clock 122 | DEN => '0', -- 1-bit input: DRP enable 123 | DI => (others => '0'), -- 16-bit input: DRP data 124 | DWE => '0', -- 1-bit input: DRP write enable 125 | -- Feedback Clocks: 1-bit (each) input: Clock feedback ports 126 | CLKFBIN => s_mmcm_fbin -- 1-bit input: Feedback clock 127 | ); 128 | 129 | -- Global clock buffers for "cmp_mmcm" instance 130 | cmp_clkf_bufg : BUFG 131 | port map( 132 | O => s_mmcm_fbin, 133 | I => s_mmcm_fbout 134 | ); 135 | 136 | cmp_clkout0_buf : BUFG 137 | port map( 138 | O => clk0_o, 139 | I => s_clk0 140 | ); 141 | 142 | cmp_clkout1_buf : BUFG 143 | port map( 144 | O => clk1_o, 145 | I => s_clk1 146 | ); 147 | 148 | cmp_clkout2_buf : BUFG 149 | port map( 150 | O => clk2_o, 151 | I => s_clk2 152 | ); 153 | 154 | end syn; 155 | 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01010000000000000000000000000100 248 | 01010000000000000000000000100100 249 | 01010000000000000000000000101000 250 | 01000000000000000001000000000000 251 | 01010000000000000000000000110000 252 | 01000000000000000010000000000000 253 | 01010000000000000000000000111000 254 | 01010000000000000000000000111100 255 | 01010000000000000000000000100000 256 | 00000000000001000000000000011001 257 | 00000000010011000100101101000000 258 | -------------------------------------------------------------------------------- /modules/cordic/vhdl/ahb3lite_cordic.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Vitor Finotti 3 | -- 4 | -- 5 | ------------------------------------------------------------------------------- 6 | -- 7 | -- unit name: AHB3-Lite Cordic wrapper 8 | -- 9 | -- description: 10 | -- 11 | -- Implement a ahb3-lite compatible wrapper for the "vhdl-extra" library 12 | -- cordic module. Implementation based on the example on 13 | -- https://www.southampton.ac.uk/~bim/notes/cad/reference/ARMSoC/P3/AMBA-AHB-Lite.pdf 14 | -- 15 | ------------------------------------------------------------------------------- 16 | -- Copyright (c) 2019 Vitor Finotti 17 | ------------------------------------------------------------------------------- 18 | -- MIT 19 | ------------------------------------------------------------------------------- 20 | -- Permission is hereby granted, free of charge, to any person obtaining a copy of 21 | -- this software and associated documentation files (the "Software"), to deal in 22 | -- the Software without restriction, including without limitation the rights to 23 | -- use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 24 | -- of the Software, and to permit persons to whom the Software is furnished to do 25 | -- so, subject to the following conditions: 26 | 27 | -- The above copyright notice and this permission notice shall be included in all 28 | -- copies or substantial portions of the Software. 29 | 30 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 31 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 32 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 33 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 34 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 35 | -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 36 | -- SOFTWARE. 37 | ------------------------------------------------------------------------------- 38 | 39 | library ieee; 40 | use ieee.std_logic_1164.all; 41 | use ieee.numeric_std.all; 42 | 43 | library work; 44 | use work.cordic.all; 45 | 46 | entity ahb3lite_cordic is 47 | 48 | generic ( 49 | g_iterations : positive := 32; -- Number of iterarions for CORDIC algorithm 50 | g_reset_active_level : std_ulogic := '1'; -- Asynch. reset control level 51 | g_haddr_size : positive := 32; -- Width of operands 52 | g_hdata_size : positive := 32; 53 | g_mode : string := "rotation"); 54 | 55 | port ( 56 | hclk_i : in std_logic; 57 | hreset_n_i : in std_logic; 58 | hsel_i : in std_logic; 59 | haddr_i : in std_logic_vector(g_haddr_size-1 downto 0); 60 | hwdata_i : in std_logic_vector(g_hdata_size-1 downto 0); 61 | hrdata_o : out std_logic_vector(g_hdata_size-1 downto 0); 62 | hwrite_i : in std_logic; 63 | hsize_i : in std_logic_vector(2 downto 0); 64 | hburst_i : in std_logic_vector(2 downto 0); 65 | hprot_i : in std_logic_vector(3 downto 0); 66 | htrans_i : in std_logic_vector(1 downto 0); 67 | hreadyout_o : out std_logic; 68 | hready_i : in std_logic; 69 | hresp_o : out std_logic); 70 | 71 | -- port ( 72 | -- clk_i : in std_ulogic; 73 | -- rst_i : in std_ulogic; 74 | -- data_valid_i : in std_ulogic; 75 | -- busy_o : out std_ulogic; 76 | -- result_valid_o : out std_ulogic; -- rotation or vector mode selection 77 | -- mode_i : in cordic_mode; 78 | -- x_i : in signed(g_size-1 downto 0); 79 | -- y_i : in signed(g_size-1 downto 0); 80 | -- z_i : in signed(g_size-1 downto 0); 81 | -- x_result_o : out signed(g_size-1 downto 0); 82 | -- y_result_o : out signed(g_size-1 downto 0); 83 | -- z_result_o : out signed(g_size-1 downto 0)); 84 | 85 | end entity ahb3lite_cordic; 86 | 87 | architecture rtl of ahb3lite_cordic is 88 | 89 | signal rst : std_ulogic; 90 | 91 | -- Address phase sampling registers 92 | signal r_hsel : std_logic := '0'; 93 | signal r_haddr : std_logic_vector (g_haddr_size-1 downto 0) := (others => '0'); 94 | signal r_htrans : std_logic_vector(1 downto 0) := (others => '0'); 95 | signal r_hwrite : std_logic := '0'; 96 | signal r_hsize : std_logic_vector(2 downto 0) := (others => '0'); 97 | 98 | -- Data and control registers 99 | signal x, y, z : signed(g_hdata_size-1 downto 0) := (others => '0'); -- 1 sign bit + 1 integer bit + g_hdata_size-2 fraction bits 100 | signal x_result, y_result, z_result : signed(g_hdata_size-1 downto 0) := (others => '0'); 101 | signal control_start : std_logic_vector(g_hdata_size-1 downto 0) := (others => '0'); 102 | signal control_done : std_logic_vector(g_hdata_size-1 downto 0) := (others => '0'); 103 | -- type t_control_regs is array (7 downto 0) of std_logic_vector(g_hdata_size-1 downto 0); 104 | -- addr 0 : x input 105 | -- addr 1 : y input 106 | -- addr 2 : z input 107 | -- addr 3 : control register "start" 108 | -- addr 4 : x result 109 | -- addr 5 : y result 110 | -- addr 6 : z result 111 | -- addr 7 : control register "done" 112 | -- signal control_regs : t_control_regs; 113 | signal cordic_mode_selection : cordic_mode; 114 | 115 | signal result_valid : std_ulogic := '0'; 116 | signal busy : std_ulogic := '0'; 117 | signal data_valid : std_ulogic := '0'; 118 | signal detection_stages : std_logic_vector(1 downto 0); 119 | 120 | 121 | 122 | begin -- architecture rtl 123 | 124 | rst <= not(hreset_n_i); 125 | 126 | -- Address phase sampling 127 | address_phase : process (hclk_i, hreset_n_i) is 128 | begin 129 | if hreset_n_i = '0' then 130 | r_hsel <= '0'; 131 | r_haddr <= (others => '0'); 132 | r_htrans <= (others => '0'); 133 | r_hwrite <= '0'; 134 | r_hsize <= (others => '0'); 135 | elsif rising_edge(hclk_i) then 136 | if (hready_i = '1') then 137 | r_hsel <= hsel_i; 138 | r_haddr <= haddr_i; 139 | r_htrans <= htrans_i; 140 | r_hwrite <= hwrite_i; 141 | r_hsize <= hsize_i; 142 | end if; 143 | end if; 144 | end process address_phase; 145 | 146 | 147 | -- Data phase data transfer 148 | data_phase : process (hclk_i, hreset_n_i) is 149 | variable addr : integer range 0 to 28; -- offset in memory, considering 150 | -- each reg have 4 bytes 151 | begin 152 | -- only last 5 bits are used for addressing 153 | addr := to_integer(unsigned(r_haddr(4 downto 0))); 154 | if hreset_n_i = '0' then 155 | x <= (others => '0'); 156 | y <= (others => '0'); 157 | z <= (others => '0'); 158 | control_start <= (others => '0'); 159 | -- control_regs <= (others => (others => '0')); 160 | elsif rising_edge(hclk_i) then 161 | if ((r_hsel and r_hwrite) = '1') then 162 | case addr is 163 | when 0 => 164 | x <= signed(hwdata_i); 165 | when 4 => 166 | y <= signed(hwdata_i); 167 | when 8 => 168 | z <= signed(hwdata_i); 169 | when 12 => 170 | control_start <= hwdata_i; 171 | when others => null; 172 | end case; 173 | -- control_regs(addr) <= hwdata_i; 174 | end if; 175 | end if; 176 | end process data_phase; 177 | 178 | 179 | -- Tranfer response 180 | hreadyout_o <= '1'; 181 | hresp_o <= '0'; 182 | 183 | 184 | -- Read data 185 | -- purpose: output the register equivalent to the address on haddr 186 | -- type : combinational 187 | -- inputs : all 188 | -- outputs: 189 | process (haddr_i) is 190 | variable addr : integer range 0 to 28; -- offset in memory, considering 191 | -- each reg have 4 bytes 192 | begin -- process 193 | -- only last 5 bits are used for addressing 194 | addr := to_integer(unsigned(r_haddr(4 downto 0))); 195 | case addr is 196 | when 0 => 197 | hrdata_o <= std_logic_vector(x); 198 | when 4 => 199 | hrdata_o <= std_logic_vector(y); 200 | when 8 => 201 | hrdata_o <= std_logic_vector(z); 202 | when 12 => 203 | hrdata_o <= std_logic_vector(control_start); 204 | when 16 => 205 | hrdata_o <= std_logic_vector(x_result); 206 | when 20 => 207 | hrdata_o <= std_logic_vector(y_result); 208 | when 24 => 209 | hrdata_o <= std_logic_vector(z_result); 210 | when 28 => 211 | hrdata_o <= std_logic_vector(control_done); 212 | when others => null; 213 | end case; 214 | end process; 215 | 216 | edge_detector_1: entity work.edge_detector 217 | generic map ( 218 | g_edge_type => "rising") 219 | port map ( 220 | clk_i => hclk_i, 221 | rst_i => rst, 222 | signal_i => control_start(0), 223 | edge_detected_o => data_valid); 224 | 225 | 226 | -- Necessary due to the custom type signal "cordic_mode" created for 227 | -- setting cordic_sequential core. 228 | cordic_mode_selection <= cordic_rotate when g_mode = "rotation" else 229 | cordic_vector when g_mode = "vectoring" else 230 | cordic_rotate; 231 | 232 | 233 | -- Sequential implementation 234 | cs: entity work.cordic_sequential 235 | generic map ( 236 | SIZE => g_hdata_size, 237 | ITERATIONS => g_iterations 238 | ) 239 | port map ( 240 | Clock => hclk_i, 241 | Reset => rst, 242 | Data_valid => data_valid, 243 | Busy => busy, 244 | Result_valid => result_valid, 245 | Mode => cordic_mode_selection, 246 | X => x, 247 | Y => y, 248 | Z => z, 249 | X_result => x_result, 250 | Y_result => y_result, 251 | Z_result => z_result); 252 | 253 | control_done(0) <= result_valid and not busy; 254 | 255 | 256 | end architecture rtl; 257 | -------------------------------------------------------------------------------- /top/kc705_blinky/verilog/cm0_blinky_top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Vitor Finotti 3 | // 4 | // 5 | /////////////////////////////////////////////////////////////////////////////// 6 | // 7 | // unit name: ARM Cortex M-0 implementation on FPGA 8 | // 9 | // description: 10 | // 11 | // 12 | // 13 | /////////////////////////////////////////////////////////////////////////////// 14 | // Copyright (c) 2019 Vitor Finotti 15 | /////////////////////////////////////////////////////////////////////////////// 16 | // MIT 17 | /////////////////////////////////////////////////////////////////////////////// 18 | // Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | // this software and associated documentation files (the "Software"), to deal in 20 | // the Software without restriction, including without limitation the rights to 21 | // use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | // of the Software, and to permit persons to whom the Software is furnished to do 23 | // so, subject to the following conditions: 24 | 25 | // The above copyright notice and this permission notice shall be included in all 26 | // copies or substantial portions of the Software. 27 | 28 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 29 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 30 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 31 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 32 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 33 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 | // SOFTWARE. 35 | /////////////////////////////////////////////////////////////////////////////// 36 | 37 | 38 | module cm0_blinky_top ( 39 | output led0, 40 | output led1, 41 | output led2, 42 | output led3, 43 | output led4, 44 | output led5, 45 | output led6, 46 | output led7, 47 | input push_button0_i, 48 | input sys_clk_p_i, 49 | input sys_clk_n_i); 50 | 51 | ////////////////////////////////////////////////////////////////// 52 | // 53 | // Constants 54 | // 55 | 56 | localparam c_masters_num = 1; 57 | localparam c_slaves_num = 1; 58 | localparam c_haddr_width = 32; 59 | localparam c_hdata_width = 32; 60 | 61 | 62 | 63 | ////////////////////////////////////////////////////////////////// 64 | // 65 | // Variables 66 | // 67 | 68 | // Common signals 69 | logic clk_10mhz; 70 | logic clk_100mhz; 71 | logic clk_200mhz; 72 | logic rst_n; 73 | logic rst; 74 | logic led_value; 75 | 76 | 77 | // Master Ports; AHB masters connect to these 78 | // thus these are actually AHB Slave Interfaces 79 | logic [ 2:0] mst_priority [c_masters_num]; 80 | logic mst_hsel [c_masters_num]; 81 | logic [c_haddr_width-1:0] mst_haddr [c_masters_num]; 82 | logic [c_hdata_width-1:0] mst_hwdata [c_masters_num]; 83 | logic [c_hdata_width-1:0] mst_hrdata [c_masters_num]; 84 | logic mst_hwrite [c_masters_num]; 85 | logic [ 2:0] mst_hsize [c_masters_num]; 86 | logic [ 2:0] mst_hburst [c_masters_num]; 87 | logic [ 3:0] mst_hprot [c_masters_num]; 88 | logic [ 1:0] mst_htrans [c_masters_num]; 89 | logic mst_hmastlock [c_masters_num]; 90 | logic mst_hreadyout [c_masters_num]; 91 | logic mst_hready [c_masters_num]; 92 | logic mst_hresp [c_masters_num]; 93 | // Slave Ports; AHB Slaves connect to these 94 | // thus these are actually AHB Master Interfaces 95 | logic [c_haddr_width-1:0] slv_addr_mask [c_slaves_num]; 96 | logic [c_haddr_width-1:0] slv_addr_base [c_slaves_num]; 97 | logic slv_hsel [c_slaves_num]; 98 | logic [c_haddr_width-1:0] slv_haddr [c_slaves_num]; 99 | logic [c_hdata_width-1:0] slv_hwdata [c_slaves_num]; 100 | logic [c_hdata_width-1:0] slv_hrdata [c_slaves_num]; 101 | logic slv_hwrite [c_slaves_num]; 102 | logic [ 2:0] slv_hsize [c_slaves_num]; 103 | logic [ 2:0] slv_hburst [c_slaves_num]; 104 | logic [ 3:0] slv_hprot [c_slaves_num]; 105 | logic [ 1:0] slv_htrans [c_slaves_num]; 106 | logic slv_hmastlock [c_slaves_num]; 107 | logic slv_hreadyout [c_slaves_num]; // hreadyout to slave-decoder; generates hready to all connected slaves 108 | logic slv_hready [c_slaves_num]; // combinatorial hready from all connected slaves 109 | logic slv_hresp [c_slaves_num]; 110 | 111 | 112 | 113 | ////////////////////////////////////////////////////////////////// 114 | // 115 | // Module Body 116 | // 117 | 118 | assign mst_priority [0] = "111"; 119 | assign mst_hsel [0] = 1'b1; 120 | assign slv_addr_mask [0] = 32'hE000_0000; 121 | assign slv_addr_base [0] = 32'h0000_0000; 122 | assign slv_addr_mask [1] = 32'hE000_0000; 123 | assign slv_addr_base [1] = 32'h2000_0000; 124 | 125 | assign led3 = led_value; 126 | assign led4 = rst_n; 127 | assign led5 = 1'b1; 128 | assign led6 = 1'b0; 129 | assign led7 = 1'b1; 130 | assign rst = !rst_n; 131 | assign push_button0_n = !push_button0_i; 132 | 133 | 134 | 135 | IBUFDS #( 136 | .DIFF_TERM ( "FALSE" ), // Differential Termination 137 | .IBUF_LOW_PWR ( "TRUE" ), // Low power="TRUE", Highest perforrmance="FALSE" 138 | .IOSTANDARD ( "DEFAULT" ) ) // Specify the input I/O standard 139 | cmp_ibufds_clk_gen ( 140 | .O ( clk_200mhz ), // Buffer output 141 | .I ( sys_clk_p_i ), // Diff_p buffer input (connect directly to top-level port) 142 | .IB ( sys_clk_n_i ) ); // Diff_n buffer input (connect directly to top-level port) 143 | 144 | 145 | detection_fsm inst_detector ( 146 | .clk_i ( clk_10mhz ), 147 | .rst_i ( rst ), 148 | .data_i ( mst_hrdata [0] ), 149 | .detected_o ( led_value ) ); 150 | 151 | 152 | gc_single_reset_gen #( 153 | .g_out_reg_depth ( 5 ), // delay for 5 clk cycles 154 | .g_rst_in_num ( 1 ) ) // just 1 input 155 | gc_single_reset_gen ( 156 | .clk_i ( clk_10mhz ), 157 | .rst_signals_n_a_i ( push_button0_n ), 158 | .rst_n_o ( rst_n ) ); 159 | 160 | 161 | sys_pll #( 162 | .g_clkin_period ( 5.000 ), // 200 MHz 163 | .g_divclk_divide ( 1 ), 164 | .g_clkbout_mult_f ( 5 ), 165 | .g_clk0_divide_f ( 100 ), // 10 MHz 166 | .g_clk1_divide ( 10 ), // 100 MHz 167 | .g_clk2_divide ( 100 ) ) // 10 MHz 168 | sys_pll ( 169 | .rst_i ( 1'b0 ), 170 | .clk_i ( clk_200mhz ), 171 | .clk0_o ( clk_10mhz ), 172 | .clk1_o ( clk_100mhz ), 173 | .clk2_o ( ), 174 | .locked_o ( led0 ) ); 175 | 176 | ahb3lite_sram1rw #( 177 | .MEM_DEPTH ( 512 ), // Memory depth 178 | .HADDR_SIZE ( 32 ), 179 | .HDATA_SIZE ( 32 ), 180 | .TECHNOLOGY ( "GENERIC" ), 181 | .REGISTERED_OUTPUT ( "NO" ), 182 | .INIT_FILE ( "../../../modules/memory/memory_1M_syn.mem" ) ) 183 | rom ( 184 | .HRESETn ( rst_n ), 185 | .HCLK ( clk_10mhz ), 186 | .HSEL ( slv_hsel [0]), 187 | .HADDR ( slv_haddr [0]), 188 | .HWDATA ( slv_hwdata [0]), 189 | .HRDATA ( slv_hrdata [0]), 190 | .HWRITE ( slv_hwrite [0]), 191 | .HSIZE ( slv_hsize [0]), 192 | .HBURST ( slv_hburst [0]), 193 | .HPROT ( slv_hprot [0]), 194 | .HTRANS ( slv_htrans [0]), 195 | .HREADYOUT ( slv_hreadyout [0]), 196 | .HREADY ( slv_hready [0]), 197 | .HRESP ( slv_hresp [0]) ); 198 | 199 | // assign slv_hready [0] = rst_n; 200 | 201 | 202 | // ahb3lite_sram1rw #( 203 | // .MEM_SIZE ( 0 ), // Memory in Bytes 204 | // .MEM_DEPTH ( 512 ), // Memory depth 205 | // .HADDR_SIZE ( 32 ), 206 | // .HDATA_SIZE ( 32 ), 207 | // .TECHNOLOGY ( "GENERIC" ), 208 | // .REGISTERED_OUTPUT ( "NO" ) ) 209 | // ram ( 210 | // .HRESETn ( rst_n ), 211 | // .HCLK ( clk_10mhz ), 212 | // .HSEL ( slv_hsel [1] ), 213 | // .HADDR ( slv_haddr [1] ), 214 | // .HWDATA ( slv_hwdata [1] ), 215 | // .HRDATA ( slv_hrdata [1] ), 216 | // .HWRITE ( slv_hwrite [1] ), 217 | // .HSIZE ( slv_hsize [1] ), 218 | // .HBURST ( slv_hburst [1] ), 219 | // .HPROT ( slv_hprot [1] ), 220 | // .HTRANS ( slv_htrans [1] ), 221 | // .HREADYOUT ( slv_hreadyout [1] ), 222 | // .HREADY ( slv_hready [1] ), 223 | // .HRESP ( slv_hresp [1] ) ); 224 | 225 | 226 | ahb3lite_interconnect #( 227 | .HADDR_SIZE ( c_haddr_width ), 228 | .HDATA_SIZE ( 32 ), 229 | .MASTERS ( c_masters_num ), //number of AHB Masters 230 | .SLAVES ( c_slaves_num ) //number of AHB slaves 231 | ) 232 | interconnection ( 233 | // Common signals 234 | .HRESETn ( rst_n ), 235 | .HCLK ( clk_10mhz ), 236 | // Master Ports 237 | .mst_priority ( mst_priority ), 238 | .mst_HSEL ( mst_hsel ), 239 | .mst_HADDR ( mst_haddr ), 240 | .mst_HWDATA ( mst_hwdata ), 241 | .mst_HRDATA ( mst_hrdata ), 242 | .mst_HWRITE ( mst_hwrite ), 243 | .mst_HSIZE ( mst_hsize ), 244 | .mst_HBURST ( mst_hburst ), 245 | .mst_HPROT ( mst_hprot ), 246 | .mst_HTRANS ( mst_htrans ), 247 | .mst_HMASTLOCK ( mst_hmastlock ), 248 | .mst_HREADYOUT ( mst_hreadyout ), 249 | .mst_HREADY ( mst_hreadyout ), 250 | .mst_HRESP ( mst_hresp ), 251 | // Slave Ports 252 | .slv_addr_mask ( slv_addr_mask ), 253 | .slv_addr_base ( slv_addr_base ), 254 | .slv_HSEL ( slv_hsel ), 255 | .slv_HADDR ( slv_haddr ), 256 | .slv_HWDATA ( slv_hwdata ), 257 | .slv_HRDATA ( slv_hrdata ), 258 | .slv_HWRITE ( slv_hwrite ), 259 | .slv_HSIZE ( slv_hsize ), 260 | .slv_HBURST ( slv_hburst ), 261 | .slv_HPROT ( slv_hprot ), 262 | .slv_HTRANS ( slv_htrans ), 263 | .slv_HMASTLOCK ( slv_hmastlock ), 264 | .slv_HREADYOUT ( slv_hready ), // HREADYOUT to slave-decoder; generates HREADY to all connected slaves 265 | .slv_HREADY ( slv_hreadyout ), // combinatorial HREADY from all connected slaves 266 | .slv_HRESP ( slv_hresp ) 267 | ); 268 | 269 | 270 | cortex_m0_wrapper cortex_m0 ( 271 | // clock and resets 272 | .hclk_i ( clk_10mhz ), // clock 273 | .hreset_n_i ( rst_n ), // asynchronous reset 274 | // ahb-lite master port 275 | .haddr_o ( mst_haddr [0] ), // ahb transaction address 276 | .hburst_o ( mst_hburst [0] ), // ahb burst: tied to single 277 | .hmastlock_o ( ), // ahb locked transfer (always zero) 278 | .hprot_o ( mst_hprot [0] ), // ahb protection: priv; data or inst 279 | .hsize_o ( mst_hsize [0] ), // ahb size: byte, half-word or word 280 | .htrans_o ( mst_htrans [0] ), // ahb transfer: non-sequential only 281 | .hwdata_o ( mst_hwdata [0] ), // ahb write-data 282 | .hwrite_o ( mst_hwrite [0] ), // ahb write control 283 | .hrdata_i ( mst_hrdata [0] ), // ahb read-data 284 | .hready_i ( 1'b1 ), // mst_hready_0, // ahb stall signal 285 | .hresp_i ( 1'b0 ), // mst_hresp_0, // ahb error response 286 | // miscellaneous 287 | .nmi_i ( 1'b0 ), // non-maskable interrupt input 288 | .irq_i ( {32{1'b0}} ), // interrupt request inputs 289 | .txev_o ( ), // event output (sev executed) 290 | .rxev_i ( 1'b0 ), // event input 291 | .lockup_o ( led2 ), // core is locked-up 292 | .sysresetreq_o ( ), // system reset request 293 | // power management 294 | .sleeping_o ( led1 ) ); // core and nvic sleeping 295 | 296 | // assign mst_hready [0] = 1'b1; // Cortex M0 has no hreadyout 297 | 298 | endmodule // cm0_softmc_top 299 | -------------------------------------------------------------------------------- /top/kc705_busy_wait/verilog/cm0_busy_wait_top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Vitor Finotti 3 | // 4 | // 5 | /////////////////////////////////////////////////////////////////////////////// 6 | // 7 | // unit name: ARM Cortex M-0 implementation on FPGA 8 | // 9 | // description: 10 | // 11 | // 12 | // 13 | /////////////////////////////////////////////////////////////////////////////// 14 | // Copyright (c) 2019 Vitor Finotti 15 | /////////////////////////////////////////////////////////////////////////////// 16 | // MIT 17 | /////////////////////////////////////////////////////////////////////////////// 18 | // Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | // this software and associated documentation files (the "Software"), to deal in 20 | // the Software without restriction, including without limitation the rights to 21 | // use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | // of the Software, and to permit persons to whom the Software is furnished to do 23 | // so, subject to the following conditions: 24 | 25 | // The above copyright notice and this permission notice shall be included in all 26 | // copies or substantial portions of the Software. 27 | 28 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 29 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 30 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 31 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 32 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 33 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 | // SOFTWARE. 35 | /////////////////////////////////////////////////////////////////////////////// 36 | 37 | 38 | module cm0_busy_wait_top ( 39 | output led0, 40 | output led1, 41 | output led2, 42 | output led3, 43 | output led4, 44 | output led5, 45 | output led6, 46 | output led7, 47 | input push_button0_i, 48 | input sys_clk_p_i, 49 | input sys_clk_n_i); 50 | 51 | ////////////////////////////////////////////////////////////////// 52 | // 53 | // Constants 54 | // 55 | 56 | localparam c_masters_num = 1; 57 | localparam c_slaves_num = 5; 58 | localparam c_haddr_width = 32; 59 | localparam c_hdata_width = 32; 60 | 61 | 62 | 63 | ////////////////////////////////////////////////////////////////// 64 | // 65 | // Variables 66 | // 67 | 68 | // Common signals 69 | logic clk_10mhz; 70 | logic clk_100mhz; 71 | logic clk_200mhz; 72 | logic rst_n; 73 | logic rst; 74 | logic led_value; 75 | 76 | 77 | // Master Ports; AHB masters connect to these 78 | // thus these are actually AHB Slave Interfaces 79 | logic [ 2:0] mst_priority [c_masters_num]; 80 | logic mst_hsel [c_masters_num]; 81 | logic [c_haddr_width-1:0] mst_haddr [c_masters_num]; 82 | logic [c_hdata_width-1:0] mst_hwdata [c_masters_num]; 83 | logic [c_hdata_width-1:0] mst_hrdata [c_masters_num]; 84 | logic mst_hwrite [c_masters_num]; 85 | logic [ 2:0] mst_hsize [c_masters_num]; 86 | logic [ 2:0] mst_hburst [c_masters_num]; 87 | logic [ 3:0] mst_hprot [c_masters_num]; 88 | logic [ 1:0] mst_htrans [c_masters_num]; 89 | logic mst_hmastlock [c_masters_num]; 90 | logic mst_hreadyout [c_masters_num]; 91 | logic mst_hready [c_masters_num]; 92 | logic mst_hresp [c_masters_num]; 93 | // Slave Ports; AHB Slaves connect to these 94 | // thus these are actually AHB Master Interfaces 95 | logic [c_haddr_width-1:0] slv_addr_mask [c_slaves_num]; 96 | logic [c_haddr_width-1:0] slv_addr_base [c_slaves_num]; 97 | logic slv_hsel [c_slaves_num]; 98 | logic [c_haddr_width-1:0] slv_haddr [c_slaves_num]; 99 | logic [c_hdata_width-1:0] slv_hwdata [c_slaves_num]; 100 | logic [c_hdata_width-1:0] slv_hrdata [c_slaves_num]; 101 | logic slv_hwrite [c_slaves_num]; 102 | logic [ 2:0] slv_hsize [c_slaves_num]; 103 | logic [ 2:0] slv_hburst [c_slaves_num]; 104 | logic [ 3:0] slv_hprot [c_slaves_num]; 105 | logic [ 1:0] slv_htrans [c_slaves_num]; 106 | logic slv_hmastlock [c_slaves_num]; 107 | logic slv_hreadyout [c_slaves_num]; // hreadyout to slave-decoder; generates hready to all connected slaves 108 | logic slv_hready [c_slaves_num]; // combinatorial hready from all connected slaves 109 | logic slv_hresp [c_slaves_num]; 110 | 111 | 112 | 113 | ////////////////////////////////////////////////////////////////// 114 | // 115 | // Module Body 116 | // 117 | 118 | assign mst_priority [0] = "111"; 119 | assign mst_hsel [0] = 1'b1; 120 | assign slv_addr_mask [0] = 32'hE000_0000; 121 | assign slv_addr_base [0] = 32'h0000_0000; 122 | // assign slv_addr_mask [1] = 32'hE000_0000; 123 | // assign slv_addr_base [1] = 32'h2000_0000; 124 | assign slv_addr_mask [1] = 32'hFFFF_FFE0; 125 | assign slv_addr_base [1] = 32'h4000_0000; 126 | assign slv_addr_mask [2] = 32'hFFFF_FFE0; 127 | assign slv_addr_base [2] = 32'h4000_0100; 128 | assign slv_addr_mask [3] = 32'hFFFF_FFE0; 129 | assign slv_addr_base [3] = 32'h4000_0200; 130 | assign slv_addr_mask [4] = 32'hFFFF_FFE0; 131 | assign slv_addr_base [4] = 32'h4000_0300; 132 | 133 | assign led3 = led_value; 134 | assign led4 = rst_n; 135 | assign led5 = 1'b1; 136 | assign led6 = 1'b0; 137 | assign led7 = 1'b1; 138 | assign rst = !rst_n; 139 | assign push_button0_n = !push_button0_i; 140 | 141 | 142 | 143 | IBUFDS #( 144 | .DIFF_TERM ( "FALSE" ), // Differential Termination 145 | .IBUF_LOW_PWR ( "TRUE" ), // Low power="TRUE", Highest perforrmance="FALSE" 146 | .IOSTANDARD ( "DEFAULT" ) ) // Specify the input I/O standard 147 | cmp_ibufds_clk_gen ( 148 | .O ( clk_200mhz ), // Buffer output 149 | .I ( sys_clk_p_i ), // Diff_p buffer input (connect directly to top-level port) 150 | .IB ( sys_clk_n_i ) ); // Diff_n buffer input (connect directly to top-level port) 151 | 152 | 153 | detection_fsm inst_detector ( 154 | .clk_i ( clk_10mhz ), 155 | .rst_i ( rst ), 156 | .data_i ( mst_hrdata [0] ), 157 | .detected_o ( led_value ) ); 158 | 159 | 160 | gc_single_reset_gen #( 161 | .g_out_reg_depth ( 5 ), // delay for 5 clk cycles 162 | .g_rst_in_num ( 1 ) ) // just 1 input 163 | gc_single_reset_gen ( 164 | .clk_i ( clk_10mhz ), 165 | .rst_signals_n_a_i ( push_button0_n ), 166 | .rst_n_o ( rst_n ) ); 167 | 168 | 169 | sys_pll #( 170 | .g_clkin_period ( 5.000 ), // 200 MHz 171 | .g_divclk_divide ( 1 ), 172 | .g_clkbout_mult_f ( 5 ), 173 | .g_clk0_divide_f ( 100 ), // 10 MHz 174 | .g_clk1_divide ( 10 ), // 100 MHz 175 | .g_clk2_divide ( 100 ) ) // 10 MHz 176 | sys_pll ( 177 | .rst_i ( 1'b0 ), 178 | .clk_i ( clk_200mhz ), 179 | .clk0_o ( clk_10mhz ), 180 | .clk1_o ( clk_100mhz ), 181 | .clk2_o ( ), 182 | .locked_o ( led0 ) ); 183 | 184 | ahb3lite_sram1rw #( 185 | .MEM_DEPTH ( 512 ), // Memory depth 186 | .HADDR_SIZE ( 32 ), 187 | .HDATA_SIZE ( 32 ), 188 | .TECHNOLOGY ( "GENERIC" ), 189 | .REGISTERED_OUTPUT ( "NO" ), 190 | .INIT_FILE ( "../../../modules/memory/memory_busy_wait.mem" ) ) 191 | rom ( 192 | .HRESETn ( rst_n ), 193 | .HCLK ( clk_10mhz ), 194 | .HSEL ( slv_hsel [0]), 195 | .HADDR ( slv_haddr [0]), 196 | .HWDATA ( slv_hwdata [0]), 197 | .HRDATA ( slv_hrdata [0]), 198 | .HWRITE ( slv_hwrite [0]), 199 | .HSIZE ( slv_hsize [0]), 200 | .HBURST ( slv_hburst [0]), 201 | .HPROT ( slv_hprot [0]), 202 | .HTRANS ( slv_htrans [0]), 203 | .HREADYOUT ( slv_hreadyout [0]), 204 | .HREADY ( slv_hready [0]), 205 | .HRESP ( slv_hresp [0]) ); 206 | 207 | // assign slv_hready [0] = rst_n; 208 | 209 | 210 | // ahb3lite_sram1rw #( 211 | // .MEM_SIZE ( 0 ), // Memory in Bytes 212 | // .MEM_DEPTH ( 512 ), // Memory depth 213 | // .HADDR_SIZE ( 32 ), 214 | // .HDATA_SIZE ( 32 ), 215 | // .TECHNOLOGY ( "GENERIC" ), 216 | // .REGISTERED_OUTPUT ( "NO" ) ) 217 | // ram ( 218 | // .HRESETn ( rst_n ), 219 | // .HCLK ( clk_10mhz ), 220 | // .HSEL ( slv_hsel [1] ), 221 | // .HADDR ( slv_haddr [1] ), 222 | // .HWDATA ( slv_hwdata [1] ), 223 | // .HRDATA ( slv_hrdata [1] ), 224 | // .HWRITE ( slv_hwrite [1] ), 225 | // .HSIZE ( slv_hsize [1] ), 226 | // .HBURST ( slv_hburst [1] ), 227 | // .HPROT ( slv_hprot [1] ), 228 | // .HTRANS ( slv_htrans [1] ), 229 | // .HREADYOUT ( slv_hreadyout [1] ), 230 | // .HREADY ( slv_hready [1] ), 231 | // .HRESP ( slv_hresp [1] ) ); 232 | 233 | ahb3lite_cordic #( 234 | .g_iterations ( 32 ), 235 | .g_haddr_size ( c_haddr_width ), 236 | .g_hdata_size ( c_hdata_width ) ) 237 | cordic0 ( 238 | .hreset_n_i ( rst_n ), 239 | .hclk_i ( clk_10mhz ), 240 | .hsel_i ( slv_hsel [1]), 241 | .haddr_i ( slv_haddr [1]), 242 | .hwdata_i ( slv_hwdata [1]), 243 | .hrdata_o ( slv_hrdata [1]), 244 | .hwrite_i ( slv_hwrite [1]), 245 | .hsize_i ( slv_hsize [1]), 246 | .hburst_i ( slv_hburst [1]), 247 | .hprot_i ( slv_hprot [1]), 248 | .htrans_i ( slv_htrans [1]), 249 | .hreadyout_o ( slv_hreadyout [1]), 250 | .hready_i ( slv_hreadyout [1]), 251 | .hresp_o ( slv_hresp [1]) ); 252 | 253 | ahb3lite_cordic #( 254 | .g_iterations ( 32 ), 255 | .g_haddr_size ( c_haddr_width ), 256 | .g_hdata_size ( c_hdata_width ) ) 257 | cordic1 ( 258 | .hreset_n_i ( rst_n ), 259 | .hclk_i ( clk_10mhz ), 260 | .hsel_i ( slv_hsel [2]), 261 | .haddr_i ( slv_haddr [2]), 262 | .hwdata_i ( slv_hwdata [2]), 263 | .hrdata_o ( slv_hrdata [2]), 264 | .hwrite_i ( slv_hwrite [2]), 265 | .hsize_i ( slv_hsize [2]), 266 | .hburst_i ( slv_hburst [2]), 267 | .hprot_i ( slv_hprot [2]), 268 | .htrans_i ( slv_htrans [2]), 269 | .hreadyout_o ( slv_hreadyout [2]), 270 | .hready_i ( slv_hreadyout [2]), 271 | .hresp_o ( slv_hresp [2]) ); 272 | 273 | ahb3lite_cordic #( 274 | .g_iterations ( 32 ), 275 | .g_haddr_size ( c_haddr_width ), 276 | .g_hdata_size ( c_hdata_width ) ) 277 | cordic2 ( 278 | .hreset_n_i ( rst_n ), 279 | .hclk_i ( clk_10mhz ), 280 | .hsel_i ( slv_hsel [3]), 281 | .haddr_i ( slv_haddr [3]), 282 | .hwdata_i ( slv_hwdata [3]), 283 | .hrdata_o ( slv_hrdata [3]), 284 | .hwrite_i ( slv_hwrite [3]), 285 | .hsize_i ( slv_hsize [3]), 286 | .hburst_i ( slv_hburst [3]), 287 | .hprot_i ( slv_hprot [3]), 288 | .htrans_i ( slv_htrans [3]), 289 | .hreadyout_o ( slv_hreadyout [3]), 290 | .hready_i ( slv_hreadyout [3]), 291 | .hresp_o ( slv_hresp [3]) ); 292 | 293 | ahb3lite_cordic #( 294 | .g_iterations ( 32 ), 295 | .g_haddr_size ( c_haddr_width ), 296 | .g_hdata_size ( c_hdata_width ) ) 297 | cordic3 ( 298 | .hreset_n_i ( rst_n ), 299 | .hclk_i ( clk_10mhz ), 300 | .hsel_i ( slv_hsel [4]), 301 | .haddr_i ( slv_haddr [4]), 302 | .hwdata_i ( slv_hwdata [4]), 303 | .hrdata_o ( slv_hrdata [4]), 304 | .hwrite_i ( slv_hwrite [4]), 305 | .hsize_i ( slv_hsize [4]), 306 | .hburst_i ( slv_hburst [4]), 307 | .hprot_i ( slv_hprot [4]), 308 | .htrans_i ( slv_htrans [4]), 309 | .hreadyout_o ( slv_hreadyout [4]), 310 | .hready_i ( slv_hreadyout [4]), 311 | .hresp_o ( slv_hresp [4]) ); 312 | 313 | 314 | ahb3lite_interconnect #( 315 | .HADDR_SIZE ( c_haddr_width ), 316 | .HDATA_SIZE ( 32 ), 317 | .MASTERS ( c_masters_num ), //number of AHB Masters 318 | .SLAVES ( c_slaves_num ) //number of AHB slaves 319 | ) 320 | interconnection ( 321 | // Common signals 322 | .HRESETn ( rst_n ), 323 | .HCLK ( clk_10mhz ), 324 | // Master Ports 325 | .mst_priority ( mst_priority ), 326 | .mst_HSEL ( mst_hsel ), 327 | .mst_HADDR ( mst_haddr ), 328 | .mst_HWDATA ( mst_hwdata ), 329 | .mst_HRDATA ( mst_hrdata ), 330 | .mst_HWRITE ( mst_hwrite ), 331 | .mst_HSIZE ( mst_hsize ), 332 | .mst_HBURST ( mst_hburst ), 333 | .mst_HPROT ( mst_hprot ), 334 | .mst_HTRANS ( mst_htrans ), 335 | .mst_HMASTLOCK ( mst_hmastlock ), 336 | .mst_HREADYOUT ( mst_hreadyout ), 337 | .mst_HREADY ( mst_hreadyout ), 338 | .mst_HRESP ( mst_hresp ), 339 | // Slave Ports 340 | .slv_addr_mask ( slv_addr_mask ), 341 | .slv_addr_base ( slv_addr_base ), 342 | .slv_HSEL ( slv_hsel ), 343 | .slv_HADDR ( slv_haddr ), 344 | .slv_HWDATA ( slv_hwdata ), 345 | .slv_HRDATA ( slv_hrdata ), 346 | .slv_HWRITE ( slv_hwrite ), 347 | .slv_HSIZE ( slv_hsize ), 348 | .slv_HBURST ( slv_hburst ), 349 | .slv_HPROT ( slv_hprot ), 350 | .slv_HTRANS ( slv_htrans ), 351 | .slv_HMASTLOCK ( slv_hmastlock ), 352 | .slv_HREADYOUT ( slv_hready ), // HREADYOUT to slave-decoder; generates HREADY to all connected slaves 353 | .slv_HREADY ( slv_hreadyout ), // combinatorial HREADY from all connected slaves 354 | .slv_HRESP ( slv_hresp ) 355 | ); 356 | 357 | 358 | cortex_m0_wrapper cortex_m0 ( 359 | // clock and resets 360 | .hclk_i ( clk_10mhz ), // clock 361 | .hreset_n_i ( rst_n ), // asynchronous reset 362 | // ahb-lite master port 363 | .haddr_o ( mst_haddr [0] ), // ahb transaction address 364 | .hburst_o ( mst_hburst [0] ), // ahb burst: tied to single 365 | .hmastlock_o ( ), // ahb locked transfer (always zero) 366 | .hprot_o ( mst_hprot [0] ), // ahb protection: priv; data or inst 367 | .hsize_o ( mst_hsize [0] ), // ahb size: byte, half-word or word 368 | .htrans_o ( mst_htrans [0] ), // ahb transfer: non-sequential only 369 | .hwdata_o ( mst_hwdata [0] ), // ahb write-data 370 | .hwrite_o ( mst_hwrite [0] ), // ahb write control 371 | .hrdata_i ( mst_hrdata [0] ), // ahb read-data 372 | .hready_i ( mst_hreadyout [0] ), // mst_hready_0, // ahb stall signal 373 | .hresp_i ( 1'b0 ), // mst_hresp_0, // ahb error response 374 | // miscellaneous 375 | .nmi_i ( 1'b0 ), // non-maskable interrupt input 376 | .irq_i ( {32{1'b0}} ), // interrupt request inputs 377 | .txev_o ( ), // event output (sev executed) 378 | .rxev_i ( 1'b0 ), // event input 379 | .lockup_o ( led2 ), // core is locked-up 380 | .sysresetreq_o ( ), // system reset request 381 | // power management 382 | .sleeping_o ( led1 ) ); // core and nvic sleeping 383 | 384 | // assign mst_hready [0] = 1'b1; // Cortex M0 has no hreadyout 385 | 386 | endmodule // cm0_softmc_top 387 | -------------------------------------------------------------------------------- /top/kc705_interruption/verilog/cm0_interruption_top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Vitor Finotti 3 | // 4 | // 5 | /////////////////////////////////////////////////////////////////////////////// 6 | // 7 | // unit name: ARM Cortex M-0 implementation on FPGA 8 | // 9 | // description: 10 | // 11 | // 12 | // 13 | /////////////////////////////////////////////////////////////////////////////// 14 | // Copyright (c) 2019 Vitor Finotti 15 | /////////////////////////////////////////////////////////////////////////////// 16 | // MIT 17 | /////////////////////////////////////////////////////////////////////////////// 18 | // Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | // this software and associated documentation files (the "Software"), to deal in 20 | // the Software without restriction, including without limitation the rights to 21 | // use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | // of the Software, and to permit persons to whom the Software is furnished to do 23 | // so, subject to the following conditions: 24 | 25 | // The above copyright notice and this permission notice shall be included in all 26 | // copies or substantial portions of the Software. 27 | 28 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 29 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 30 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 31 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 32 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 33 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 | // SOFTWARE. 35 | /////////////////////////////////////////////////////////////////////////////// 36 | 37 | 38 | module cm0_interruption_top ( 39 | output led0, 40 | output led1, 41 | output led2, 42 | output led3, 43 | output led4, 44 | output led5, 45 | output led6, 46 | output led7, 47 | input push_button0_i, 48 | input sys_clk_p_i, 49 | input sys_clk_n_i); 50 | 51 | ////////////////////////////////////////////////////////////////// 52 | // 53 | // Constants 54 | // 55 | 56 | localparam c_masters_num = 1; 57 | localparam c_slaves_num = 6; 58 | localparam c_haddr_width = 32; 59 | localparam c_hdata_width = 32; 60 | 61 | 62 | 63 | ////////////////////////////////////////////////////////////////// 64 | // 65 | // Variables 66 | // 67 | 68 | // Common signals 69 | logic clk_10mhz; 70 | logic clk_100mhz; 71 | logic clk_200mhz; 72 | logic rst_n; 73 | logic rst; 74 | logic led_value; 75 | 76 | 77 | // Master Ports; AHB masters connect to these 78 | // thus these are actually AHB Slave Interfaces 79 | logic [ 2:0] mst_priority [c_masters_num]; 80 | logic mst_hsel [c_masters_num]; 81 | logic [c_haddr_width-1:0] mst_haddr [c_masters_num]; 82 | logic [c_hdata_width-1:0] mst_hwdata [c_masters_num]; 83 | logic [c_hdata_width-1:0] mst_hrdata [c_masters_num]; 84 | logic mst_hwrite [c_masters_num]; 85 | logic [ 2:0] mst_hsize [c_masters_num]; 86 | logic [ 2:0] mst_hburst [c_masters_num]; 87 | logic [ 3:0] mst_hprot [c_masters_num]; 88 | logic [ 1:0] mst_htrans [c_masters_num]; 89 | logic mst_hmastlock [c_masters_num]; 90 | logic mst_hreadyout [c_masters_num]; 91 | logic mst_hready [c_masters_num]; 92 | logic mst_hresp [c_masters_num]; 93 | // Slave Ports; AHB Slaves connect to these 94 | // thus these are actually AHB Master Interfaces 95 | logic [c_haddr_width-1:0] slv_addr_mask [c_slaves_num]; 96 | logic [c_haddr_width-1:0] slv_addr_base [c_slaves_num]; 97 | logic slv_hsel [c_slaves_num]; 98 | logic [c_haddr_width-1:0] slv_haddr [c_slaves_num]; 99 | logic [c_hdata_width-1:0] slv_hwdata [c_slaves_num]; 100 | logic [c_hdata_width-1:0] slv_hrdata [c_slaves_num]; 101 | logic slv_hwrite [c_slaves_num]; 102 | logic [ 2:0] slv_hsize [c_slaves_num]; 103 | logic [ 2:0] slv_hburst [c_slaves_num]; 104 | logic [ 3:0] slv_hprot [c_slaves_num]; 105 | logic [ 1:0] slv_htrans [c_slaves_num]; 106 | logic slv_hmastlock [c_slaves_num]; 107 | logic slv_hreadyout [c_slaves_num]; // hreadyout to slave-decoder; generates hready to all connected slaves 108 | logic slv_hready [c_slaves_num]; // combinatorial hready from all connected slaves 109 | logic slv_hresp [c_slaves_num]; 110 | 111 | // Other signals 112 | logic [ 31 : 0] irq_vector; 113 | 114 | 115 | 116 | ////////////////////////////////////////////////////////////////// 117 | // 118 | // Module Body 119 | // 120 | 121 | assign mst_priority [0] = "111"; 122 | assign mst_hsel [0] = 1'b1; 123 | assign slv_addr_mask [0] = 32'hE000_0000; 124 | assign slv_addr_base [0] = 32'h0000_0000; 125 | // assign slv_addr_mask [1] = 32'hE000_0000; 126 | // assign slv_addr_base [1] = 32'h2000_0000; 127 | assign slv_addr_mask [1] = 32'hFFFF_FFE0; 128 | assign slv_addr_base [1] = 32'h4000_0000; 129 | assign slv_addr_mask [2] = 32'hFFFF_FFE0; 130 | assign slv_addr_base [2] = 32'h4000_0100; 131 | assign slv_addr_mask [3] = 32'hFFFF_FFE0; 132 | assign slv_addr_base [3] = 32'h4000_0200; 133 | assign slv_addr_mask [4] = 32'hFFFF_FFE0; 134 | assign slv_addr_base [4] = 32'h4000_0300; 135 | assign slv_addr_mask [5] = 32'hFFFF_FFC0; 136 | assign slv_addr_base [5] = 32'h4000_0400; 137 | 138 | assign led3 = led_value; 139 | assign led4 = rst_n; 140 | assign led5 = 1'b1; 141 | assign led6 = 1'b0; 142 | assign led7 = 1'b1; 143 | assign rst = !rst_n; 144 | assign push_button0_n = !push_button0_i; 145 | 146 | assign irq_vector [31:1] = {31{1'b0}}; 147 | 148 | 149 | 150 | IBUFDS #( 151 | .DIFF_TERM ( "FALSE" ), // Differential Termination 152 | .IBUF_LOW_PWR ( "TRUE" ), // Low power="TRUE", Highest perforrmance="FALSE" 153 | .IOSTANDARD ( "DEFAULT" ) ) // Specify the input I/O standard 154 | cmp_ibufds_clk_gen ( 155 | .O ( clk_200mhz ), // Buffer output 156 | .I ( sys_clk_p_i ), // Diff_p buffer input (connect directly to top-level port) 157 | .IB ( sys_clk_n_i ) ); // Diff_n buffer input (connect directly to top-level port) 158 | 159 | 160 | detection_fsm inst_detector ( 161 | .clk_i ( clk_10mhz ), 162 | .rst_i ( rst ), 163 | .data_i ( mst_hrdata [0] ), 164 | .detected_o ( led_value ) ); 165 | 166 | 167 | gc_single_reset_gen #( 168 | .g_out_reg_depth ( 5 ), // delay for 5 clk cycles 169 | .g_rst_in_num ( 1 ) ) // just 1 input 170 | gc_single_reset_gen ( 171 | .clk_i ( clk_10mhz ), 172 | .rst_signals_n_a_i ( push_button0_n ), 173 | .rst_n_o ( rst_n ) ); 174 | 175 | 176 | sys_pll #( 177 | .g_clkin_period ( 5.000 ), // 200 MHz 178 | .g_divclk_divide ( 1 ), 179 | .g_clkbout_mult_f ( 5 ), 180 | .g_clk0_divide_f ( 100 ), // 10 MHz 181 | .g_clk1_divide ( 10 ), // 100 MHz 182 | .g_clk2_divide ( 100 ) ) // 10 MHz 183 | sys_pll ( 184 | .rst_i ( 1'b0 ), 185 | .clk_i ( clk_200mhz ), 186 | .clk0_o ( clk_10mhz ), 187 | .clk1_o ( clk_100mhz ), 188 | .clk2_o ( ), 189 | .locked_o ( led0 ) ); 190 | 191 | ahb3lite_sram1rw #( 192 | .MEM_DEPTH ( 512 ), // Memory depth 193 | .HADDR_SIZE ( 32 ), 194 | .HDATA_SIZE ( 32 ), 195 | .TECHNOLOGY ( "GENERIC" ), 196 | .REGISTERED_OUTPUT ( "NO" ), 197 | .INIT_FILE ( "../../../modules/memory/memory_interrupt_sim.mem" ) ) 198 | rom ( 199 | .HRESETn ( rst_n ), 200 | .HCLK ( clk_10mhz ), 201 | .HSEL ( slv_hsel [0]), 202 | .HADDR ( slv_haddr [0]), 203 | .HWDATA ( slv_hwdata [0]), 204 | .HRDATA ( slv_hrdata [0]), 205 | .HWRITE ( slv_hwrite [0]), 206 | .HSIZE ( slv_hsize [0]), 207 | .HBURST ( slv_hburst [0]), 208 | .HPROT ( slv_hprot [0]), 209 | .HTRANS ( slv_htrans [0]), 210 | .HREADYOUT ( slv_hreadyout [0]), 211 | .HREADY ( slv_hready [0]), 212 | .HRESP ( slv_hresp [0]) ); 213 | 214 | // assign slv_hready [0] = rst_n; 215 | 216 | 217 | // ahb3lite_sram1rw #( 218 | // .MEM_SIZE ( 0 ), // Memory in Bytes 219 | // .MEM_DEPTH ( 512 ), // Memory depth 220 | // .HADDR_SIZE ( 32 ), 221 | // .HDATA_SIZE ( 32 ), 222 | // .TECHNOLOGY ( "GENERIC" ), 223 | // .REGISTERED_OUTPUT ( "NO" ) ) 224 | // ram ( 225 | // .HRESETn ( rst_n ), 226 | // .HCLK ( clk_10mhz ), 227 | // .HSEL ( slv_hsel [1] ), 228 | // .HADDR ( slv_haddr [1] ), 229 | // .HWDATA ( slv_hwdata [1] ), 230 | // .HRDATA ( slv_hrdata [1] ), 231 | // .HWRITE ( slv_hwrite [1] ), 232 | // .HSIZE ( slv_hsize [1] ), 233 | // .HBURST ( slv_hburst [1] ), 234 | // .HPROT ( slv_hprot [1] ), 235 | // .HTRANS ( slv_htrans [1] ), 236 | // .HREADYOUT ( slv_hreadyout [1] ), 237 | // .HREADY ( slv_hready [1] ), 238 | // .HRESP ( slv_hresp [1] ) ); 239 | 240 | ahb3lite_cordic #( 241 | .g_iterations ( 32 ), 242 | .g_haddr_size ( c_haddr_width ), 243 | .g_hdata_size ( c_hdata_width ) ) 244 | cordic0 ( 245 | .hreset_n_i ( rst_n ), 246 | .hclk_i ( clk_10mhz ), 247 | .hsel_i ( slv_hsel [1]), 248 | .haddr_i ( slv_haddr [1]), 249 | .hwdata_i ( slv_hwdata [1]), 250 | .hrdata_o ( slv_hrdata [1]), 251 | .hwrite_i ( slv_hwrite [1]), 252 | .hsize_i ( slv_hsize [1]), 253 | .hburst_i ( slv_hburst [1]), 254 | .hprot_i ( slv_hprot [1]), 255 | .htrans_i ( slv_htrans [1]), 256 | .hreadyout_o ( slv_hreadyout [1]), 257 | .hready_i ( slv_hreadyout [1]), 258 | .hresp_o ( slv_hresp [1]) ); 259 | 260 | ahb3lite_cordic #( 261 | .g_iterations ( 32 ), 262 | .g_haddr_size ( c_haddr_width ), 263 | .g_hdata_size ( c_hdata_width ) ) 264 | cordic1 ( 265 | .hreset_n_i ( rst_n ), 266 | .hclk_i ( clk_10mhz ), 267 | .hsel_i ( slv_hsel [2]), 268 | .haddr_i ( slv_haddr [2]), 269 | .hwdata_i ( slv_hwdata [2]), 270 | .hrdata_o ( slv_hrdata [2]), 271 | .hwrite_i ( slv_hwrite [2]), 272 | .hsize_i ( slv_hsize [2]), 273 | .hburst_i ( slv_hburst [2]), 274 | .hprot_i ( slv_hprot [2]), 275 | .htrans_i ( slv_htrans [2]), 276 | .hreadyout_o ( slv_hreadyout [2]), 277 | .hready_i ( slv_hreadyout [2]), 278 | .hresp_o ( slv_hresp [2]) ); 279 | 280 | ahb3lite_cordic #( 281 | .g_iterations ( 32 ), 282 | .g_haddr_size ( c_haddr_width ), 283 | .g_hdata_size ( c_hdata_width ) ) 284 | cordic2 ( 285 | .hreset_n_i ( rst_n ), 286 | .hclk_i ( clk_10mhz ), 287 | .hsel_i ( slv_hsel [3]), 288 | .haddr_i ( slv_haddr [3]), 289 | .hwdata_i ( slv_hwdata [3]), 290 | .hrdata_o ( slv_hrdata [3]), 291 | .hwrite_i ( slv_hwrite [3]), 292 | .hsize_i ( slv_hsize [3]), 293 | .hburst_i ( slv_hburst [3]), 294 | .hprot_i ( slv_hprot [3]), 295 | .htrans_i ( slv_htrans [3]), 296 | .hreadyout_o ( slv_hreadyout [3]), 297 | .hready_i ( slv_hreadyout [3]), 298 | .hresp_o ( slv_hresp [3]) ); 299 | 300 | ahb3lite_cordic #( 301 | .g_iterations ( 32 ), 302 | .g_haddr_size ( c_haddr_width ), 303 | .g_hdata_size ( c_hdata_width ) ) 304 | cordic3 ( 305 | .hreset_n_i ( rst_n ), 306 | .hclk_i ( clk_10mhz ), 307 | .hsel_i ( slv_hsel [4]), 308 | .haddr_i ( slv_haddr [4]), 309 | .hwdata_i ( slv_hwdata [4]), 310 | .hrdata_o ( slv_hrdata [4]), 311 | .hwrite_i ( slv_hwrite [4]), 312 | .hsize_i ( slv_hsize [4]), 313 | .hburst_i ( slv_hburst [4]), 314 | .hprot_i ( slv_hprot [4]), 315 | .htrans_i ( slv_htrans [4]), 316 | .hreadyout_o ( slv_hreadyout [4]), 317 | .hready_i ( slv_hreadyout [4]), 318 | .hresp_o ( slv_hresp [4]) ); 319 | 320 | ahb3lite_timer #( 321 | //AHB Parameters 322 | .HADDR_SIZE ( c_haddr_width ), 323 | .HDATA_SIZE ( c_hdata_width ), 324 | //Timer Parameters 325 | .TIMERS ( 1 ) ) //Number of timers 326 | timer0 ( 327 | .HRESETn ( rst_n ), 328 | .HCLK ( clk_10mhz ), 329 | //AHB Slave Interfaces (receive data from AHB Masters) 330 | //AHB Masters connect to these ports 331 | .HSEL ( slv_hsel [5]), 332 | .HADDR ( slv_haddr [5]), 333 | .HWDATA ( slv_hwdata [5]), 334 | .HRDATA ( slv_hrdata [5]), 335 | .HWRITE ( slv_hwrite [5]), 336 | .HSIZE ( slv_hsize [5]), 337 | .HBURST ( slv_hburst [5]), 338 | .HPROT ( slv_hprot [5]), 339 | .HTRANS ( slv_htrans [5]), 340 | .HREADYOUT ( slv_hreadyout [5]), 341 | .HREADY ( slv_hreadyout [5]), 342 | .HRESP ( slv_hresp [5]), 343 | .tint ( irq_vector [0]) ); //Timer Interrupt 344 | 345 | ahb3lite_interconnect #( 346 | .HADDR_SIZE ( c_haddr_width ), 347 | .HDATA_SIZE ( 32 ), 348 | .MASTERS ( c_masters_num ), //number of AHB Masters 349 | .SLAVES ( c_slaves_num ) //number of AHB slaves 350 | ) 351 | interconnection ( 352 | // Common signals 353 | .HRESETn ( rst_n ), 354 | .HCLK ( clk_10mhz ), 355 | // Master Ports 356 | .mst_priority ( mst_priority ), 357 | .mst_HSEL ( mst_hsel ), 358 | .mst_HADDR ( mst_haddr ), 359 | .mst_HWDATA ( mst_hwdata ), 360 | .mst_HRDATA ( mst_hrdata ), 361 | .mst_HWRITE ( mst_hwrite ), 362 | .mst_HSIZE ( mst_hsize ), 363 | .mst_HBURST ( mst_hburst ), 364 | .mst_HPROT ( mst_hprot ), 365 | .mst_HTRANS ( mst_htrans ), 366 | .mst_HMASTLOCK ( mst_hmastlock ), 367 | .mst_HREADYOUT ( mst_hreadyout ), 368 | .mst_HREADY ( mst_hreadyout ), 369 | .mst_HRESP ( mst_hresp ), 370 | // Slave Ports 371 | .slv_addr_mask ( slv_addr_mask ), 372 | .slv_addr_base ( slv_addr_base ), 373 | .slv_HSEL ( slv_hsel ), 374 | .slv_HADDR ( slv_haddr ), 375 | .slv_HWDATA ( slv_hwdata ), 376 | .slv_HRDATA ( slv_hrdata ), 377 | .slv_HWRITE ( slv_hwrite ), 378 | .slv_HSIZE ( slv_hsize ), 379 | .slv_HBURST ( slv_hburst ), 380 | .slv_HPROT ( slv_hprot ), 381 | .slv_HTRANS ( slv_htrans ), 382 | .slv_HMASTLOCK ( slv_hmastlock ), 383 | .slv_HREADYOUT ( slv_hready ), // HREADYOUT to slave-decoder; generates HREADY to all connected slaves 384 | .slv_HREADY ( slv_hreadyout ), // combinatorial HREADY from all connected slaves 385 | .slv_HRESP ( slv_hresp ) 386 | ); 387 | 388 | 389 | cortex_m0_wrapper cortex_m0 ( 390 | // clock and resets 391 | .hclk_i ( clk_10mhz ), // clock 392 | .hreset_n_i ( rst_n ), // asynchronous reset 393 | // ahb-lite master port 394 | .haddr_o ( mst_haddr [0] ), // ahb transaction address 395 | .hburst_o ( mst_hburst [0] ), // ahb burst: tied to single 396 | .hmastlock_o ( ), // ahb locked transfer (always zero) 397 | .hprot_o ( mst_hprot [0] ), // ahb protection: priv; data or inst 398 | .hsize_o ( mst_hsize [0] ), // ahb size: byte, half-word or word 399 | .htrans_o ( mst_htrans [0] ), // ahb transfer: non-sequential only 400 | .hwdata_o ( mst_hwdata [0] ), // ahb write-data 401 | .hwrite_o ( mst_hwrite [0] ), // ahb write control 402 | .hrdata_i ( mst_hrdata [0] ), // ahb read-data 403 | .hready_i ( mst_hreadyout [0] ), // mst_hready_0, // ahb stall signal 404 | .hresp_i ( 1'b0 ), // mst_hresp_0, // ahb error response 405 | // miscellaneous 406 | .nmi_i ( 1'b0 ), // non-maskable interrupt input 407 | .irq_i ( irq_vector ), // interrupt request inputs 408 | .txev_o ( ), // event output (sev executed) 409 | .rxev_i ( 1'b0 ), // event input 410 | .lockup_o ( led2 ), // core is locked-up 411 | .sysresetreq_o ( ), // system reset request 412 | // power management 413 | .sleeping_o ( led1 ) ); // core and nvic sleeping 414 | 415 | // assign mst_hready [0] = 1'b1; // Cortex M0 has no hreadyout 416 | 417 | endmodule // cm0_softmc_top 418 | -------------------------------------------------------------------------------- /modules/memory/memory_dummy.mem: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 10011001100110011001100110011001 3 | 00000000000000000000000000000000 4 | 10011001100110011001100110011001 5 | 00000000000000000000000000000000 6 | 10011001100110011001100110011001 7 | 00000000000000000000000000000000 8 | 10011001100110011001100110011001 9 | 00000000000000000000000000000000 10 | 10011001100110011001100110011001 11 | 00000000000000000000000000000000 12 | 10011001100110011001100110011001 13 | 00000000000000000000000000000000 14 | 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00000000000000000000000000000000 494 | 10100101101001011010010110100101 495 | 00000000000000000000000000000000 496 | 10100101101001011010010110100101 497 | 00000000000000000000000000000000 498 | 10100101101001011010010110100101 499 | 00000000000000000000000000000000 500 | 10100101101001011010010110100101 501 | 00000000000000000000000000000000 502 | 10100101101001011010010110100101 503 | 00000000000000000000000000000000 504 | 10100101101001011010010110100101 505 | 00000000000000000000000000000000 506 | 10100101101001011010010110100101 507 | 00000000000000000000000000000000 508 | 10100101101001011010010110100101 509 | 00000000000000000000000000000000 510 | 10100101101001011010010110100101 511 | 00000000000000000000000000000000 512 | 10100101101001011010010110100101 513 | -------------------------------------------------------------------------------- /modules/cortex-m0/vhdl/cortex_m0_wrapper.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Vitor Finotti 3 | -- 4 | -- https://github.com/vfinotti/cortex-m0-soft-microcontroller 5 | ------------------------------------------------------------------------------- 6 | -- 7 | -- unit name: Cortex-M0 VHDL Wrapper 8 | -- 9 | -- description: 10 | -- 11 | -- This module was created to wrap the CORTEXM0INTEGRATION module, designed 12 | -- in Verilog, on a VHDL wrapper in order to preserve VHDL users' sanity 13 | -- while using this code on mixed language projects. This was needed due to 14 | -- many particularities of the Verilog language, like case sensitivity [1] or 15 | -- the need to use qualified expressions [2]. 16 | -- 17 | -- Please, have in mind that the Cortex-M0 files are available on ARM website 18 | -- through the DesignStart programme [3]. 19 | -- 20 | -- [1] https://stackoverflow.com/questions/38169074/case-sensitivity-while-using-verilog-module-in-vhdl 21 | -- [2] https://www.xilinx.com/support/answers/57549.html 22 | -- [3] https://www.arm.com/resources/designstart 23 | -- 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2018 Vitor Finotti 26 | ------------------------------------------------------------------------------- 27 | 28 | 29 | library ieee; 30 | use ieee.std_logic_1164.all; 31 | 32 | entity cortex_m0_wrapper is 33 | port ( 34 | -- CLOCK AND RESETS ------------------ 35 | hclk_i : in std_logic; -- Clock 36 | hreset_n_i : in std_logic; -- Asynchronous reset 37 | -- AHB-LITE MASTER PORT -------------- 38 | haddr_o : out std_logic_vector (31 downto 0); -- AHB transaction address 39 | hburst_o : out std_logic_vector (2 downto 0); -- AHB burst: tied to single 40 | hmastlock_o : out std_logic; -- AHB locked transfer (always zero) 41 | hprot_o : out std_logic_vector (3 downto 0); -- AHB protection: priv; data or inst 42 | hsize_o : out std_logic_vector (2 downto 0); -- AHB size: byte, half-word or word 43 | htrans_o : out std_logic_vector (1 downto 0); -- AHB transfer: non-sequential only 44 | hwdata_o : out std_logic_vector (31 downto 0); -- AHB write-data 45 | hwrite_o : out std_logic; -- AHB write control 46 | hrdata_i : in std_logic_vector (31 downto 0); -- AHB read-data 47 | hready_i : in std_logic; -- AHB stall signal 48 | hresp_i : in std_logic; -- ahb error response 49 | -- MISCELLANEOUS --------------------- 50 | nmi_i : in std_logic; -- Non-maskable interrupt input 51 | irq_i : in std_logic_vector (31 downto 0); -- Interrupt request inputs 52 | txev_o : out std_logic; -- Event output (SEV executed) 53 | rxev_i : in std_logic; -- Event input 54 | lockup_o : out std_logic; -- Core is locked-up 55 | sysresetreq_o : out std_logic; -- System reset request 56 | -- POWER MANAGEMENT ------------------ 57 | sleeping_o : out std_logic); -- Core and NVIC sleeping 58 | end entity cortex_m0_wrapper; 59 | 60 | architecture rtl of cortex_m0_wrapper is 61 | 62 | -- component CORTEXM0INTEGRATION 63 | -- port( 64 | -- -- CLOCK AND RESETS ------------------ 65 | -- --input wire HCLK, -- Clock 66 | -- --input wire HRESETn, -- Asynchronous reset 67 | -- HCLK : in std_logic; -- Clock 68 | -- HRESETn : in std_logic; -- Asynchronous reset 69 | -- -- AHB-LITE MASTER PORT -------------- 70 | -- --output wire [31:0] HADDR, -- AHB transaction address 71 | -- --output wire [ 2:0] HBURST, -- AHB burst: tied to single 72 | -- --output wire HMASTLOCK, -- AHB locked transfer (always zero) 73 | -- --output wire [ 3:0] HPROT, -- AHB protection: priv; data or inst 74 | -- --output wire [ 2:0] HSIZE, -- AHB size: byte, half-word or word 75 | -- --output wire [ 1:0] HTRANS, -- AHB transfer: non-sequential only 76 | -- --output wire [31:0] HWDATA, -- AHB write-data 77 | -- --output wire HWRITE, -- AHB write control 78 | -- --input wire [31:0] HRDATA, -- AHB read-data 79 | -- --input wire HREADY, -- AHB stall signal 80 | -- --input wire HRESP, -- AHB error response 81 | -- HADDR : out std_logic_vector (31 downto 0); -- AHB transaction address 82 | -- HBURST : out std_logic_vector (2 downto 0); -- AHB burst: tied to single 83 | -- HMASTLOCK : out std_logic; -- AHB locked transfer (always zero) 84 | -- HPROT : out std_logic_vector (3 downto 0); -- AHB protection: priv; data or inst 85 | -- HSIZE : out std_logic_vector (2 downto 0); -- AHB size: byte, half-word or word 86 | -- HTRANS : out std_logic_vector (1 downto 0); -- AHB transfer: non-sequential only 87 | -- HWDATA : out std_logic_vector (31 downto 0); -- AHB write-data 88 | -- HWRITE : out std_logic; -- AHB write control 89 | -- HRDATA : in std_logic_vector (31 downto 0); -- AHB read-data 90 | -- HREADY : in std_logic; -- AHB stall signal 91 | -- HRESP : in std_logic; -- AHB error response 92 | -- -- MISCELLANEOUS --------------------- 93 | -- --input wire NMI, -- Non-maskable interrupt input 94 | -- --input wire [15:0] IRQ, -- Interrupt request inputs 95 | -- --output wire TXEV, -- Event output (SEV executed) 96 | -- --input wire RXEV, -- Event input 97 | -- --output wire LOCKUP, -- Core is locked-up 98 | -- --output wire SYSRESETREQ, -- System reset request 99 | -- NMI : in std_logic; -- Non-maskable interrupt input 100 | -- IRQ : in std_logic_vector (31 downto 0); -- Interrupt request inputs 101 | -- TXEV : out std_logic; -- Event output (SEV executed) 102 | -- RXEV : in std_logic; -- Event input 103 | -- LOCKUP : out std_logic; -- Core is locked-up 104 | -- SYSRESETREQ : out std_logic; -- System reset request 105 | -- -- POWER MANAGEMENT ------------------ 106 | -- --output wire SLEEPING -- Core and NVIC sleeping 107 | -- SLEEPING : out std_logic -- Core and NVIC sleeping 108 | -- ); 109 | -- end component; 110 | 111 | signal FCLK : std_logic := '0'; 112 | signal SCLK : std_logic := '0'; 113 | signal HCLK : std_logic := '0'; 114 | signal DCLK : std_logic := '0'; 115 | signal PORESETn : std_logic := '1'; 116 | signal DBGRESETn : std_logic := '1'; 117 | signal HRESETn : std_logic := '0'; 118 | signal SWCLKTCK : std_logic := '0'; 119 | signal nTRST : std_logic := '1'; 120 | signal HADDR : std_logic_vector (31 downto 0) := (others => '0'); 121 | signal HBURST : std_logic_vector (2 downto 0) := (others => '0'); 122 | signal HMASTLOCK : std_logic := '0'; 123 | signal HPROT : std_logic_vector (3 downto 0) := (others => '0'); 124 | signal HSIZE : std_logic_vector (2 downto 0) := (others => '0'); 125 | signal HTRANS : std_logic_vector (1 downto 0) := (others => '0'); 126 | signal HWDATA : std_logic_vector (31 downto 0) := (others => '0'); 127 | signal HWRITE : std_logic := '0'; 128 | signal HRDATA : std_logic_vector (31 downto 0) := (others => '0'); 129 | signal HREADY : std_logic := '0'; 130 | signal HRESP : std_logic := '0'; 131 | signal HMASTER : std_logic := '0'; 132 | signal CODENSEQ : std_logic := '0'; 133 | signal CODEHINTDE : std_logic_vector (2 downto 0) := (others => '0'); 134 | signal SPECHTRANS : std_logic := '0'; 135 | signal SWDITMS : std_logic := '0'; 136 | signal TDI : std_logic := '0'; 137 | signal SWDO : std_logic := '0'; 138 | signal SWDOEN : std_logic := '0'; 139 | signal TDO : std_logic := '0'; 140 | signal nTDOEN : std_logic := '0'; 141 | signal DBGRESTART : std_logic := '0'; 142 | signal DBGRESTARTED : std_logic := '0'; 143 | signal EDBGRQ : std_logic := '0'; 144 | signal HALTED : std_logic := '0'; 145 | signal NMI : std_logic := '0'; 146 | signal IRQ : std_logic_vector (31 downto 0) := (others => '0'); 147 | signal TXEV : std_logic := '0'; 148 | signal RXEV : std_logic := '0'; 149 | signal LOCKUP : std_logic := '0'; 150 | signal SYSRESETREQ : std_logic := '0'; 151 | signal STCALIB : std_logic_vector (25 downto 0) := (others => '0'); 152 | signal STCLKEN : std_logic := '0'; 153 | signal IRQLATENCY : std_logic_vector (7 downto 0) := (others => '0'); 154 | signal ECOREVNUM : std_logic_vector (27 downto 0) := (others => '0'); 155 | signal GATEHCLK : std_logic := '0'; 156 | signal SLEEPING : std_logic := '0'; 157 | signal SLEEPDEEP : std_logic := '0'; 158 | signal WAKEUP : std_logic := '0'; 159 | signal WICSENSE : std_logic_vector(33 downto 0) := (others => '0'); 160 | signal SLEEPHOLDREQn : std_logic := '1'; 161 | signal SLEEPHOLDACKn : std_logic := '0'; 162 | signal WICENREQ : std_logic := '0'; 163 | signal WICENACK : std_logic := '0'; 164 | signal CDBGPWRUPREQ : std_logic := '0'; 165 | signal CDBGPWRUPACK : std_logic := '0'; 166 | signal SE : std_logic := '0'; 167 | signal RSTBYPASS : std_logic := '0'; 168 | 169 | component CORTEXM0INTEGRATION 170 | port( 171 | -- CLOCK AND RESETS ------------------ 172 | -- input wire FCLK, 173 | -- input wire SCLK, 174 | -- input wire HCLK, -- Clock 175 | -- input wire DCLK, -- Asynchronous reset 176 | -- input wire PORESETn, 177 | -- input wire DBGRESETn, 178 | -- input wire HRESETn, 179 | -- input wire SWCLKTCK, 180 | -- input wire nTRST, 181 | FCLK : in std_logic; -- Free running clock 182 | SCLK : in std_logic; -- System clock 183 | HCLK : in std_logic; -- AHB clock(from PMU) 184 | DCLK : in std_logic; -- Debug system clock (from PMU) 185 | PORESETn : in std_logic; -- Power on reset 186 | DBGRESETn : in std_logic; -- Debug reset 187 | HRESETn : in std_logic; -- AHB and System reset 188 | SWCLKTCK : in std_logic; -- 189 | nTRST : in std_logic; -- 190 | -- AHB-LITE MASTER PORT -------------- 191 | -- output wire [31:0] HADDR, -- AHB transaction address 192 | -- output wire [ 2:0] HBURST, -- AHB burst: tied to single 193 | -- output wire HMASTLOCK, -- AHB locked transfer (always zero) 194 | -- output wire [ 3:0] HPROT, -- AHB protection: priv; data or inst 195 | -- output wire [ 2:0] HSIZE, -- AHB size: byte, half-word or word 196 | -- output wire [ 1:0] HTRANS, -- AHB transfer: non-sequential only 197 | -- output wire [31:0] HWDATA, -- AHB write-data 198 | -- output wire HWRITE, -- AHB write control 199 | -- input wire [31:0] HRDATA, -- AHB read-data 200 | -- input wire HREADY, -- AHB stall signal 201 | -- input wire HRESP, -- AHB error response 202 | -- output wire HMASTER, 203 | HADDR : out std_logic_vector (31 downto 0); -- AHB transaction address 204 | HBURST : out std_logic_vector (2 downto 0); -- AHB burst: tied to single 205 | HMASTLOCK : out std_logic; -- AHB locked transfer (always zero) 206 | HPROT : out std_logic_vector (3 downto 0); -- AHB protection: priv; data or inst 207 | HSIZE : out std_logic_vector (2 downto 0); -- AHB size: byte, half-word or word 208 | HTRANS : out std_logic_vector (1 downto 0); -- AHB transfer: non-sequential only 209 | HWDATA : out std_logic_vector (31 downto 0); -- AHB write-data 210 | HWRITE : out std_logic; -- AHB write control 211 | HRDATA : in std_logic_vector (31 downto 0); -- AHB read-data 212 | HREADY : in std_logic; -- AHB stall signal 213 | HRESP : in std_logic; -- AHB error response 214 | HMASTER : out std_logic; 215 | -- CODE SEQUENTIALITY AND SPECULATION 216 | -- output wire CODENSEQ, 217 | -- output wire [ 2:0] CODEHINTDE, 218 | -- output wire SPECHTRANS, 219 | CODENSEQ : out std_logic; 220 | CODEHINTDE : out std_logic_vector (2 downto 0); 221 | SPECHTRANS : out std_logic; 222 | -- DEBUG ----------------------------- 223 | -- input wire SWDITMS, 224 | -- input wire TDI, 225 | -- output wire SWDO, 226 | -- output wire SWDOEN, 227 | -- output wire TDO, 228 | -- output wire nTDOEN, 229 | -- input wire DBGRESTART, 230 | -- output wire DBGRESTARTED, 231 | -- input wire EDBGRQ, 232 | -- output wire HALTED, 233 | SWDITMS : in std_logic; 234 | TDI : in std_logic; 235 | SWDO : out std_logic; 236 | SWDOEN : out std_logic; 237 | TDO : out std_logic; 238 | nTDOEN : out std_logic; 239 | DBGRESTART : in std_logic; 240 | DBGRESTARTED : out std_logic; 241 | EDBGRQ : in std_logic; 242 | HALTED : out std_logic; 243 | -- MISCELLANEOUS --------------------- 244 | -- input wire NMI, -- Non-maskable interrupt input 245 | -- input wire [31:0] IRQ, -- Interrupt request inputs 246 | -- output wire TXEV, -- Event output (SEV executed) 247 | -- input wire RXEV, -- Event input 248 | -- output wire LOCKUP, -- Core is locked-up 249 | -- output wire SYSRESETREQ, -- System reset request 250 | -- input wire [25 : 0] STCALIB, 251 | -- input wire STCLKEN, 252 | -- input wire [ 7:0] IRQLATENCY, 253 | -- input wire [27:0] ECOREVNUM, // [27:20] to DAP, [19:0] to core 254 | NMI : in std_logic; -- Non-maskable interrupt input 255 | IRQ : in std_logic_vector (31 downto 0); -- Interrupt request inputs 256 | TXEV : out std_logic; -- Event output (SEV executed) 257 | RXEV : in std_logic; -- Event input 258 | LOCKUP : out std_logic; -- Core is locked-up 259 | SYSRESETREQ : out std_logic; -- System reset request 260 | STCALIB : in std_logic_vector (25 downto 0); 261 | STCLKEN : in std_logic; 262 | IRQLATENCY : in std_logic_vector (7 downto 0); 263 | ECOREVNUM : in std_logic_vector (27 downto 0); -- [27 : 20] to DAP, [19 : 0] to core 264 | -- POWER MANAGEMENT ------------------ 265 | -- output wire GATEHCLK, 266 | -- output wire SLEEPING -- Core and NVIC sleeping 267 | -- output wire SLEEPDEEP, 268 | -- output wire WAKEUP, 269 | -- output wire [33:0] WICSENSE, 270 | -- input wire SLEEPHOLDREQn, 271 | -- output wire SLEEPHOLDACKn, 272 | -- input wire WICENREQ, 273 | -- output wire WICENACK, 274 | -- output wire CDBGPWRUPREQ, 275 | -- input wire CDBGPWRUPACK, 276 | GATEHCLK : out std_logic; 277 | SLEEPING : out std_logic; -- Core and NVIC sleeping 278 | SLEEPDEEP : out std_logic; 279 | WAKEUP : out std_logic; 280 | WICSENSE : out std_logic_vector(33 downto 0); 281 | SLEEPHOLDREQn : in std_logic; 282 | SLEEPHOLDACKn : out std_logic; 283 | WICENREQ : in std_logic; 284 | WICENACK : out std_logic; 285 | CDBGPWRUPREQ : out std_logic; 286 | CDBGPWRUPACK : in std_logic; 287 | -- SCAN IO --------------------------- 288 | -- input wire SE, 289 | -- input wire RSTBYPASS, 290 | SE : in std_logic; 291 | RSTBYPASS : in std_logic); 292 | end component; 293 | 294 | begin -- architecture rtl 295 | 296 | 297 | -- Processor : CORTEXM0INTEGRATION 298 | -- port map ( 299 | -- -- CLOCK AND RESETS ------------------ 300 | -- HCLK => hclk_i, -- Clock 301 | -- HRESETn => hreset_n_i, -- Asynchronous reset 302 | -- -- AHB-LITE MASTER PORT -------------- 303 | -- HADDR => haddr_o, -- AHB transaction address 304 | -- HBURST => hburst_o, -- AHB burst: tied to single 305 | -- HMASTLOCK => hmastlock_o, -- AHB locked transfer (always zero) 306 | -- HPROT => hprot_o, -- AHB protection: priv; data or inst 307 | -- HSIZE => hsize_o, -- AHB size: byte, half-word or word 308 | -- HTRANS => htrans_o, -- AHB transfer: non-sequential only 309 | -- HWDATA => hwdata_o, -- AHB write-data 310 | -- HWRITE => hwrite_o, -- AHB write control 311 | -- HRDATA => hrdata_i, -- AHB read-data 312 | -- HREADY => hready_i, -- AHB stall signal 313 | -- HRESP => hresp_i, -- AHB error response 314 | -- -- MISCELLANEOUS --------------------- 315 | -- NMI => nmi_i, -- Non-maskable interrupt input 316 | -- IRQ => irq_i, -- Interrupt request inputs 317 | -- TXEV => txev_o, -- Event output (SEV executed) 318 | -- RXEV => rxev_i, -- Event input 319 | -- LOCKUP => lockup_o, -- Core is locked-up 320 | -- SYSRESETREQ => sysresetreq_o, -- System reset request 321 | -- -- POWER MANAGEMENT ------------------ 322 | -- SLEEPING => sleeping_o); -- Core and NVIC sleeping 323 | 324 | Processor : CORTEXM0INTEGRATION 325 | port map ( 326 | -- CLOCK AND RESETS ------------------ 327 | FCLK => FCLK, 328 | SCLK => SCLK, 329 | HCLK => HCLK, 330 | DCLK => DCLK, 331 | PORESETn => PORESETn, 332 | DBGRESETn => DBGRESETn, 333 | HRESETn => HRESETn, 334 | SWCLKTCK => SWCLKTCK, 335 | nTRST => nTRST, 336 | -- AHB-LITE MASTER PORT -------------- 337 | HADDR => HADDR, 338 | HBURST => HBURST, 339 | HMASTLOCK => HMASTLOCK, 340 | HPROT => HPROT, 341 | HSIZE => HSIZE, 342 | HTRANS => HTRANS, 343 | HWDATA => HWDATA, 344 | HWRITE => HWRITE, 345 | HRDATA => HRDATA, 346 | HREADY => HREADY, 347 | HRESP => HRESP, 348 | HMASTER => HMASTER, 349 | -- CODE SEQUENTIALITY AND SPECULATION 350 | CODENSEQ => CODENSEQ, 351 | CODEHINTDE => CODEHINTDE, 352 | SPECHTRANS => SPECHTRANS, 353 | -- DEBUG ----------------------------- 354 | SWDITMS => SWDITMS, 355 | TDI => TDI, 356 | SWDO => SWDO, 357 | SWDOEN => SWDOEN, 358 | TDO => TDO, 359 | nTDOEN => nTDOEN, 360 | DBGRESTART => DBGRESTART, 361 | DBGRESTARTED => DBGRESTARTED, 362 | EDBGRQ => EDBGRQ, 363 | HALTED => HALTED, 364 | -- MISCELLANEOUS --------------------- 365 | NMI => NMI, 366 | IRQ => IRQ, 367 | TXEV => TXEV, 368 | RXEV => RXEV, 369 | LOCKUP => LOCKUP, 370 | SYSRESETREQ => SYSRESETREQ, 371 | STCALIB => STCALIB, 372 | STCLKEN => STCLKEN, 373 | IRQLATENCY => IRQLATENCY, 374 | ECOREVNUM => ECOREVNUM, 375 | -- POWER MANAGEMENT ------------------ 376 | GATEHCLK => GATEHCLK, 377 | SLEEPING => SLEEPING, 378 | SLEEPDEEP => SLEEPDEEP, 379 | WAKEUP => WAKEUP, 380 | WICSENSE => WICSENSE, 381 | SLEEPHOLDREQn => SLEEPHOLDREQn, 382 | SLEEPHOLDACKn => SLEEPHOLDACKn, 383 | WICENREQ => WICENREQ, 384 | WICENACK => WICENACK, 385 | CDBGPWRUPREQ => CDBGPWRUPREQ, 386 | CDBGPWRUPACK => CDBGPWRUPACK, 387 | -- SCAN IO --------------------------- 388 | SE => SE, 389 | RSTBYPASS => RSTBYPASS); 390 | 391 | FCLK <= hclk_i; 392 | SCLK <= hclk_i; 393 | HCLK <= hclk_i; 394 | DCLK <= hclk_i; 395 | SWCLKTCK <= hclk_i; 396 | PORESETn <= hreset_n_i; 397 | DBGRESETn <= hreset_n_i; 398 | HRESETn <= hreset_n_i; 399 | nTRST <= hreset_n_i; 400 | 401 | haddr_o <= HADDR; 402 | hburst_o <= HBURST; 403 | hmastlock_o <= HMASTLOCK; 404 | hprot_o <= HPROT; 405 | hsize_o <= HSIZE; 406 | htrans_o <= HTRANS; 407 | hwdata_o <= HWDATA; 408 | hwrite_o <= HWRITE; 409 | HRDATA <= hrdata_i; 410 | HREADY <= hready_i; 411 | HRESP <= hresp_i; 412 | 413 | NMI <= nmi_i; 414 | IRQ <= irq_i; 415 | txev_o <= TXEV; 416 | RXEV <= rxev_i; 417 | lockup_o <= LOCKUP; 418 | sysresetreq_o <= SYSRESETREQ; 419 | 420 | sleeping_o <= SLEEPING; 421 | 422 | 423 | end architecture rtl; 424 | -------------------------------------------------------------------------------- /top/kc705_dma/verilog/cm0_dma_top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Vitor Finotti 3 | // 4 | // 5 | /////////////////////////////////////////////////////////////////////////////// 6 | // 7 | // unit name: ARM Cortex M-0 implementation on FPGA 8 | // 9 | // description: 10 | // 11 | // 12 | // 13 | /////////////////////////////////////////////////////////////////////////////// 14 | // Copyright (c) 2019 Vitor Finotti 15 | /////////////////////////////////////////////////////////////////////////////// 16 | // MIT 17 | /////////////////////////////////////////////////////////////////////////////// 18 | // Permission is hereby granted, free of charge, to any person obtaining a copy of 19 | // this software and associated documentation files (the "Software"), to deal in 20 | // the Software without restriction, including without limitation the rights to 21 | // use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 22 | // of the Software, and to permit persons to whom the Software is furnished to do 23 | // so, subject to the following conditions: 24 | 25 | // The above copyright notice and this permission notice shall be included in all 26 | // copies or substantial portions of the Software. 27 | 28 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 29 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 30 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 31 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 32 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 33 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 | // SOFTWARE. 35 | /////////////////////////////////////////////////////////////////////////////// 36 | 37 | 38 | module cm0_dma_top ( 39 | output led0, 40 | output led1, 41 | output led2, 42 | output led3, 43 | output led4, 44 | output led5, 45 | output led6, 46 | output led7, 47 | input push_button0_i, 48 | input sys_clk_p_i, 49 | input sys_clk_n_i); 50 | 51 | ////////////////////////////////////////////////////////////////// 52 | // 53 | // Constants 54 | // 55 | 56 | localparam c_masters_num = 2; 57 | localparam c_slaves_num = 10; 58 | localparam c_haddr_width = 32; 59 | localparam c_hdata_width = 32; 60 | 61 | 62 | 63 | ////////////////////////////////////////////////////////////////// 64 | // 65 | // Variables 66 | // 67 | 68 | // Common signals 69 | logic clk_10mhz; 70 | logic clk_100mhz; 71 | logic clk_200mhz; 72 | logic rst_n; 73 | logic rst; 74 | logic led_value; 75 | 76 | 77 | // Master Ports; AHB masters connect to these 78 | // thus these are actually AHB Slave Interfaces 79 | logic [ 2:0] mst_priority [c_masters_num]; 80 | logic mst_hsel [c_masters_num]; 81 | logic [c_haddr_width-1:0] mst_haddr [c_masters_num]; 82 | logic [c_hdata_width-1:0] mst_hwdata [c_masters_num]; 83 | logic [c_hdata_width-1:0] mst_hrdata [c_masters_num]; 84 | logic mst_hwrite [c_masters_num]; 85 | logic [ 2:0] mst_hsize [c_masters_num]; 86 | logic [ 2:0] mst_hburst [c_masters_num]; 87 | logic [ 3:0] mst_hprot [c_masters_num]; 88 | logic [ 1:0] mst_htrans [c_masters_num]; 89 | logic mst_hmastlock [c_masters_num]; 90 | logic mst_hreadyout [c_masters_num]; 91 | logic mst_hready [c_masters_num]; 92 | logic mst_hresp [c_masters_num]; 93 | // Slave Ports; AHB Slaves connect to these 94 | // thus these are actually AHB Master Interfaces 95 | logic [c_haddr_width-1:0] slv_addr_mask [c_slaves_num]; 96 | logic [c_haddr_width-1:0] slv_addr_base [c_slaves_num]; 97 | logic slv_hsel [c_slaves_num]; 98 | logic [c_haddr_width-1:0] slv_haddr [c_slaves_num]; 99 | logic [c_hdata_width-1:0] slv_hwdata [c_slaves_num]; 100 | logic [c_hdata_width-1:0] slv_hrdata [c_slaves_num]; 101 | logic slv_hwrite [c_slaves_num]; 102 | logic [ 2:0] slv_hsize [c_slaves_num]; 103 | logic [ 2:0] slv_hburst [c_slaves_num]; 104 | logic [ 3:0] slv_hprot [c_slaves_num]; 105 | logic [ 1:0] slv_htrans [c_slaves_num]; 106 | logic slv_hmastlock [c_slaves_num]; 107 | logic slv_hreadyout [c_slaves_num]; // hreadyout to slave-decoder; generates hready to all connected slaves 108 | logic slv_hready [c_slaves_num]; // combinatorial hready from all connected slaves 109 | logic slv_hresp [c_slaves_num]; 110 | 111 | 112 | // Other signals 113 | logic [ 31 : 0] irq_vector; 114 | 115 | 116 | ////////////////////////////////////////////////////////////////// 117 | // 118 | // Module Body 119 | // 120 | 121 | assign mst_priority [0] = "111"; 122 | assign mst_priority [1] = "001"; 123 | assign slv_addr_mask [0] = 32'hE000_0000; 124 | assign slv_addr_base [0] = 32'h0000_0000; 125 | assign slv_addr_mask [1] = 32'hE000_0000; 126 | assign slv_addr_base [1] = 32'h2000_0000; 127 | assign slv_addr_mask [2] = 32'hFFFF_FFE0; 128 | assign slv_addr_base [2] = 32'h4000_0000; 129 | assign slv_addr_mask [3] = 32'hFFFF_FFE0; 130 | assign slv_addr_base [3] = 32'h4000_0100; 131 | assign slv_addr_mask [4] = 32'hFFFF_FFE0; 132 | assign slv_addr_base [4] = 32'h4000_0200; 133 | assign slv_addr_mask [5] = 32'hFFFF_FFE0; 134 | assign slv_addr_base [5] = 32'h4000_0300; 135 | assign slv_addr_mask [6] = 32'hFFFF_FFC0; 136 | assign slv_addr_base [6] = 32'h4000_0400; 137 | assign slv_addr_mask [7] = 32'hFFFF_F000; 138 | assign slv_addr_base [7] = 32'h4000_1000; 139 | assign slv_addr_mask [8] = 32'hFFFF_F000; 140 | assign slv_addr_base [8] = 32'h4000_2000; 141 | assign slv_addr_mask [9] = 32'hFFFF_F000; 142 | assign slv_addr_base [9] = 32'h5000_0000; // for a limitation on the DMA, no 143 | // other core should start with 144 | // addr "5' (check "rf_addr" on 145 | // page 31 of its datasheet 146 | 147 | assign led3 = led_value; 148 | assign led4 = rst_n; 149 | assign led5 = 1'b1; 150 | assign led6 = 1'b0; 151 | assign led7 = irqa_o; 152 | assign rst = !rst_n; 153 | assign push_button0_n = !push_button0_i; 154 | 155 | assign irq_vector [31:1] = {31{1'b0}}; 156 | 157 | 158 | IBUFDS #( 159 | .DIFF_TERM ( "FALSE" ), // Differential Termination 160 | .IBUF_LOW_PWR ( "TRUE" ), // Low power="TRUE", Highest perforrmance="FALSE" 161 | .IOSTANDARD ( "DEFAULT" ) ) // Specify the input I/O standard 162 | cmp_ibufds_clk_gen ( 163 | .O ( clk_200mhz ), // Buffer output 164 | .I ( sys_clk_p_i ), // Diff_p buffer input (connect directly to top-level port) 165 | .IB ( sys_clk_n_i ) ); // Diff_n buffer input (connect directly to top-level port) 166 | 167 | 168 | detection_fsm inst_detector ( 169 | .clk_i ( clk_10mhz ), 170 | .rst_i ( rst ), 171 | .data_i ( mst_hrdata [0] ), 172 | .detected_o ( led_value ) ); 173 | 174 | 175 | gc_single_reset_gen #( 176 | .g_out_reg_depth ( 5 ), // delay for 5 clk cycles 177 | .g_rst_in_num ( 1 ) ) // just 1 input 178 | gc_single_reset_gen ( 179 | .clk_i ( clk_10mhz ), 180 | .rst_signals_n_a_i ( push_button0_n ), 181 | .rst_n_o ( rst_n ) ); 182 | 183 | 184 | sys_pll #( 185 | .g_clkin_period ( 5.000 ), // 200 MHz 186 | .g_divclk_divide ( 1 ), 187 | .g_clkbout_mult_f ( 5 ), 188 | .g_clk0_divide_f ( 100 ), // 10 MHz 189 | .g_clk1_divide ( 10 ), // 100 MHz 190 | .g_clk2_divide ( 100 ) ) // 10 MHz 191 | sys_pll ( 192 | .rst_i ( 1'b0 ), 193 | .clk_i ( clk_200mhz ), 194 | .clk0_o ( clk_10mhz ), 195 | .clk1_o ( clk_100mhz ), 196 | .clk2_o ( ), 197 | .locked_o ( led0 ) ); 198 | 199 | ahb3lite_sram1rw #( 200 | .MEM_DEPTH ( 512 ), // Memory depth 201 | .HADDR_SIZE ( 32 ), 202 | .HDATA_SIZE ( 32 ), 203 | .TECHNOLOGY ( "GENERIC" ), 204 | .REGISTERED_OUTPUT ( "NO" ), 205 | .INIT_FILE ( "../../../modules/memory/memory_dma_sim.mem" ) ) 206 | rom ( 207 | .HRESETn ( rst_n ), 208 | .HCLK ( clk_10mhz ), 209 | .HSEL ( slv_hsel [0]), 210 | .HADDR ( slv_haddr [0]), 211 | .HWDATA ( slv_hwdata [0]), 212 | .HRDATA ( slv_hrdata [0]), 213 | .HWRITE ( slv_hwrite [0]), 214 | .HSIZE ( slv_hsize [0]), 215 | .HBURST ( slv_hburst [0]), 216 | .HPROT ( slv_hprot [0]), 217 | .HTRANS ( slv_htrans [0]), 218 | .HREADYOUT ( slv_hreadyout [0]), 219 | .HREADY ( slv_hready [0]), 220 | .HRESP ( slv_hresp [0]) ); 221 | 222 | // assign slv_hready [0] = rst_n; 223 | 224 | 225 | ahb3lite_sram1rw #( 226 | .MEM_SIZE ( 0 ), // Memory in Bytes 227 | .MEM_DEPTH ( 512 ), // Memory depth 228 | .HADDR_SIZE ( 32 ), 229 | .HDATA_SIZE ( 32 ), 230 | .TECHNOLOGY ( "GENERIC" ), 231 | .REGISTERED_OUTPUT ( "NO" ) ) 232 | ram ( 233 | .HRESETn ( rst_n ), 234 | .HCLK ( clk_10mhz ), 235 | .HSEL ( slv_hsel [1] ), 236 | .HADDR ( slv_haddr [1] ), 237 | .HWDATA ( slv_hwdata [1] ), 238 | .HRDATA ( slv_hrdata [1] ), 239 | .HWRITE ( slv_hwrite [1] ), 240 | .HSIZE ( slv_hsize [1] ), 241 | .HBURST ( slv_hburst [1] ), 242 | .HPROT ( slv_hprot [1] ), 243 | .HTRANS ( slv_htrans [1] ), 244 | .HREADYOUT ( slv_hreadyout [1] ), 245 | .HREADY ( slv_hready [1] ), 246 | .HRESP ( slv_hresp [1] ) ); 247 | 248 | ahb3lite_cordic #( 249 | .g_iterations ( 32 ), 250 | .g_haddr_size ( c_haddr_width ), 251 | .g_hdata_size ( c_hdata_width ) ) 252 | cordic0 ( 253 | .hreset_n_i ( rst_n ), 254 | .hclk_i ( clk_10mhz ), 255 | .hsel_i ( slv_hsel [2]), 256 | .haddr_i ( slv_haddr [2]), 257 | .hwdata_i ( slv_hwdata [2]), 258 | .hrdata_o ( slv_hrdata [2]), 259 | .hwrite_i ( slv_hwrite [2]), 260 | .hsize_i ( slv_hsize [2]), 261 | .hburst_i ( slv_hburst [2]), 262 | .hprot_i ( slv_hprot [2]), 263 | .htrans_i ( slv_htrans [2]), 264 | .hreadyout_o ( slv_hreadyout [2]), 265 | .hready_i ( slv_hreadyout [2]), 266 | .hresp_o ( slv_hresp [2]) ); 267 | 268 | ahb3lite_cordic #( 269 | .g_iterations ( 32 ), 270 | .g_haddr_size ( c_haddr_width ), 271 | .g_hdata_size ( c_hdata_width ) ) 272 | cordic1 ( 273 | .hreset_n_i ( rst_n ), 274 | .hclk_i ( clk_10mhz ), 275 | .hsel_i ( slv_hsel [3]), 276 | .haddr_i ( slv_haddr [3]), 277 | .hwdata_i ( slv_hwdata [3]), 278 | .hrdata_o ( slv_hrdata [3]), 279 | .hwrite_i ( slv_hwrite [3]), 280 | .hsize_i ( slv_hsize [3]), 281 | .hburst_i ( slv_hburst [3]), 282 | .hprot_i ( slv_hprot [3]), 283 | .htrans_i ( slv_htrans [3]), 284 | .hreadyout_o ( slv_hreadyout [3]), 285 | .hready_i ( slv_hreadyout [3]), 286 | .hresp_o ( slv_hresp [3]) ); 287 | 288 | ahb3lite_cordic #( 289 | .g_iterations ( 32 ), 290 | .g_haddr_size ( c_haddr_width ), 291 | .g_hdata_size ( c_hdata_width ) ) 292 | cordic2 ( 293 | .hreset_n_i ( rst_n ), 294 | .hclk_i ( clk_10mhz ), 295 | .hsel_i ( slv_hsel [4]), 296 | .haddr_i ( slv_haddr [4]), 297 | .hwdata_i ( slv_hwdata [4]), 298 | .hrdata_o ( slv_hrdata [4]), 299 | .hwrite_i ( slv_hwrite [4]), 300 | .hsize_i ( slv_hsize [4]), 301 | .hburst_i ( slv_hburst [4]), 302 | .hprot_i ( slv_hprot [4]), 303 | .htrans_i ( slv_htrans [4]), 304 | .hreadyout_o ( slv_hreadyout [4]), 305 | .hready_i ( slv_hreadyout [4]), 306 | .hresp_o ( slv_hresp [4]) ); 307 | 308 | ahb3lite_cordic #( 309 | .g_iterations ( 32 ), 310 | .g_haddr_size ( c_haddr_width ), 311 | .g_hdata_size ( c_hdata_width ) ) 312 | cordic3 ( 313 | .hreset_n_i ( rst_n ), 314 | .hclk_i ( clk_10mhz ), 315 | .hsel_i ( slv_hsel [5]), 316 | .haddr_i ( slv_haddr [5]), 317 | .hwdata_i ( slv_hwdata [5]), 318 | .hrdata_o ( slv_hrdata [5]), 319 | .hwrite_i ( slv_hwrite [5]), 320 | .hsize_i ( slv_hsize [5]), 321 | .hburst_i ( slv_hburst [5]), 322 | .hprot_i ( slv_hprot [5]), 323 | .htrans_i ( slv_htrans [5]), 324 | .hreadyout_o ( slv_hreadyout [5]), 325 | .hready_i ( slv_hreadyout [5]), 326 | .hresp_o ( slv_hresp [5]) ); 327 | 328 | ahb3lite_timer #( 329 | //AHB Parameters 330 | .HADDR_SIZE ( c_haddr_width ), 331 | .HDATA_SIZE ( c_hdata_width ), 332 | //Timer Parameters 333 | .TIMERS ( 1 ) ) //Number of timers 334 | timer0 ( 335 | .HRESETn ( rst_n ), 336 | .HCLK ( clk_10mhz ), 337 | //AHB Slave Interfaces (receive data from AHB Masters) 338 | //AHB Masters connect to these ports 339 | .HSEL ( slv_hsel [6]), 340 | .HADDR ( slv_haddr [6]), 341 | .HWDATA ( slv_hwdata [6]), 342 | .HRDATA ( slv_hrdata [6]), 343 | .HWRITE ( slv_hwrite [6]), 344 | .HSIZE ( slv_hsize [6]), 345 | .HBURST ( slv_hburst [6]), 346 | .HPROT ( slv_hprot [6]), 347 | .HTRANS ( slv_htrans [6]), 348 | .HREADYOUT ( slv_hreadyout [6]), 349 | .HREADY ( slv_hreadyout [6]), 350 | .HRESP ( slv_hresp [6]), 351 | .tint ( irq_vector [0]) ); //Timer Interrupt 352 | 353 | ahb3lite_sram1rw #( 354 | .MEM_SIZE ( 0 ), // Memory in Bytes 355 | .MEM_DEPTH ( 512 ), // Memory depth 356 | .HADDR_SIZE ( c_haddr_width ), 357 | .HDATA_SIZE ( c_hdata_width ), 358 | .TECHNOLOGY ( "GENERIC" ), 359 | .REGISTERED_OUTPUT ( "NO" ), 360 | .INIT_FILE ( "../../../modules/memory/memory_dummy.mem" ) ) 361 | generic_memory_0 ( 362 | .HRESETn ( rst_n ), 363 | .HCLK ( clk_10mhz ), 364 | .HSEL ( slv_hsel [7] ), 365 | .HADDR ( slv_haddr [7] ), 366 | .HWDATA ( slv_hwdata [7] ), 367 | .HRDATA ( slv_hrdata [7] ), 368 | .HWRITE ( slv_hwrite [7] ), 369 | .HSIZE ( slv_hsize [7] ), 370 | .HBURST ( slv_hburst [7] ), 371 | .HPROT ( slv_hprot [7] ), 372 | .HTRANS ( slv_htrans [7] ), 373 | .HREADYOUT ( slv_hreadyout [7] ), 374 | .HREADY ( slv_hready [7] ), 375 | .HRESP ( slv_hresp [7] ) ); 376 | 377 | ahb3lite_sram1rw #( 378 | .MEM_SIZE ( 0 ), // Memory in Bytes 379 | .MEM_DEPTH ( 512 ), // Memory depth 380 | .HADDR_SIZE ( c_haddr_width ), 381 | .HDATA_SIZE ( c_hdata_width ), 382 | .TECHNOLOGY ( "GENERIC" ), 383 | .REGISTERED_OUTPUT ( "NO" ) ) 384 | generic_memory_1 ( 385 | .HRESETn ( rst_n ), 386 | .HCLK ( clk_10mhz ), 387 | .HSEL ( slv_hsel [8] ), 388 | .HADDR ( slv_haddr [8] ), 389 | .HWDATA ( slv_hwdata [8] ), 390 | .HRDATA ( slv_hrdata [8] ), 391 | .HWRITE ( slv_hwrite [8] ), 392 | .HSIZE ( slv_hsize [8] ), 393 | .HBURST ( slv_hburst [8] ), 394 | .HPROT ( slv_hprot [8] ), 395 | .HTRANS ( slv_htrans [8] ), 396 | .HREADYOUT ( slv_hreadyout [8] ), 397 | .HREADY ( slv_hready [8] ), 398 | .HRESP ( slv_hresp [8] ) ); 399 | 400 | 401 | ahb3lite_dma #( 402 | // chXX_conf = { CBUF, ED, ARS, EN } 403 | .rf_addr ( 4'h5 ), // bits are compared with 31:28 of addr to access inner registers 404 | .pri_sel ( 2'h0 ), 405 | .ch_count ( 1 ), 406 | .ch0_conf ( 4'h1 ), 407 | .ch1_conf ( 4'h0 ), 408 | .ch2_conf ( 4'h0 ), 409 | .ch3_conf ( 4'h0 ), 410 | .ch4_conf ( 4'h0 ), 411 | .ch5_conf ( 4'h0 ), 412 | .ch6_conf ( 4'h0 ), 413 | .ch7_conf ( 4'h0 ), 414 | .ch8_conf ( 4'h0 ), 415 | .ch9_conf ( 4'h0 ), 416 | .ch10_conf ( 4'h0 ), 417 | .ch11_conf ( 4'h0 ), 418 | .ch12_conf ( 4'h0 ), 419 | .ch13_conf ( 4'h0 ), 420 | .ch14_conf ( 4'h0 ), 421 | .ch15_conf ( 4'h0 ), 422 | .ch16_conf ( 4'h0 ), 423 | .ch17_conf ( 4'h0 ), 424 | .ch18_conf ( 4'h0 ), 425 | .ch19_conf ( 4'h0 ), 426 | .ch20_conf ( 4'h0 ), 427 | .ch21_conf ( 4'h0 ), 428 | .ch22_conf ( 4'h0 ), 429 | .ch23_conf ( 4'h0 ), 430 | .ch24_conf ( 4'h0 ), 431 | .ch25_conf ( 4'h0 ), 432 | .ch26_conf ( 4'h0 ), 433 | .ch27_conf ( 4'h0 ), 434 | .ch28_conf ( 4'h0 ), 435 | .ch29_conf ( 4'h0 ), 436 | .ch30_conf ( 4'h0 ) ) 437 | dma0 ( 438 | // Common signals 439 | .clk_i ( clk_10mhz ), 440 | .rst_n_i ( rst_n ), 441 | // -------------------------------------- 442 | // AHB3-Lite INTERFACE 0 443 | // Slave Interface 444 | .s0HSEL ( slv_hsel [9] ), 445 | .s0HADDR ( slv_haddr [9] ), 446 | .s0HWDATA ( slv_hwdata [9] ), 447 | .s0HRDATA ( slv_hrdata [9] ), 448 | .s0HWRITE ( slv_hwrite [9] ), 449 | .s0HSIZE ( slv_hsize [9] ), 450 | .s0HBURST ( slv_hburst [9] ), 451 | .s0HPROT ( slv_hprot [9] ), 452 | .s0HTRANS ( slv_htrans [9] ), 453 | .s0HREADYOUT ( slv_hreadyout [9] ), 454 | .s0HREADY ( slv_hready [9] ), 455 | .s0HRESP ( slv_hresp [9] ), 456 | // Master Interface 457 | .m0HSEL ( mst_hsel [1] ), 458 | .m0HADDR ( mst_haddr [1] ), 459 | .m0HWDATA ( mst_hwdata [1] ), 460 | .m0HRDATA ( mst_hrdata [1] ), 461 | .m0HWRITE ( mst_hwrite [1] ), 462 | .m0HSIZE ( mst_hsize [1] ), 463 | .m0HBURST ( mst_hburst [1] ), 464 | .m0HPROT ( mst_hprot [1] ), 465 | .m0HTRANS ( mst_htrans [1] ), 466 | .m0HREADYOUT ( mst_hready [1] ), 467 | .m0HREADY ( mst_hreadyout [1] ), 468 | .m0HRESP ( mst_hresp [1] ), 469 | // -------------------------------------- 470 | // Misc Signal, 471 | .dma_req_i ( 1'b0 ), 472 | .dma_nd_i ( 1'b0 ), 473 | .dma_ack_o ( dma_ack_o ), 474 | .dma_rest_i ( 1'b0 ), 475 | .irqa_o ( irqa_o ), 476 | .irqb_o ( irqb_o ) ); 477 | 478 | 479 | ahb3lite_interconnect #( 480 | .HADDR_SIZE ( c_haddr_width ), 481 | .HDATA_SIZE ( 32 ), 482 | .MASTERS ( c_masters_num ), //number of AHB Masters 483 | .SLAVES ( c_slaves_num ) //number of AHB slaves 484 | ) 485 | interconnection ( 486 | // Common signals 487 | .HRESETn ( rst_n ), 488 | .HCLK ( clk_10mhz ), 489 | // Master Ports 490 | .mst_priority ( mst_priority ), 491 | .mst_HSEL ( mst_hsel ), 492 | .mst_HADDR ( mst_haddr ), 493 | .mst_HWDATA ( mst_hwdata ), 494 | .mst_HRDATA ( mst_hrdata ), 495 | .mst_HWRITE ( mst_hwrite ), 496 | .mst_HSIZE ( mst_hsize ), 497 | .mst_HBURST ( mst_hburst ), 498 | .mst_HPROT ( mst_hprot ), 499 | .mst_HTRANS ( mst_htrans ), 500 | .mst_HMASTLOCK ( mst_hmastlock ), 501 | .mst_HREADYOUT ( mst_hreadyout ), 502 | .mst_HREADY ( mst_hready ), 503 | .mst_HRESP ( mst_hresp ), 504 | // Slave Ports 505 | .slv_addr_mask ( slv_addr_mask ), 506 | .slv_addr_base ( slv_addr_base ), 507 | .slv_HSEL ( slv_hsel ), 508 | .slv_HADDR ( slv_haddr ), 509 | .slv_HWDATA ( slv_hwdata ), 510 | .slv_HRDATA ( slv_hrdata ), 511 | .slv_HWRITE ( slv_hwrite ), 512 | .slv_HSIZE ( slv_hsize ), 513 | .slv_HBURST ( slv_hburst ), 514 | .slv_HPROT ( slv_hprot ), 515 | .slv_HTRANS ( slv_htrans ), 516 | .slv_HMASTLOCK ( slv_hmastlock ), 517 | .slv_HREADYOUT ( slv_hready ), // HREADYOUT to slave-decoder; generates HREADY to all connected slaves 518 | .slv_HREADY ( slv_hreadyout ), // combinatorial HREADY from all connected slaves 519 | .slv_HRESP ( slv_hresp ) 520 | ); 521 | 522 | 523 | cortex_m0_wrapper cortex_m0 ( 524 | // clock and resets 525 | .hclk_i ( clk_10mhz ), // clock 526 | .hreset_n_i ( rst_n ), // asynchronous reset 527 | // ahb-lite master port 528 | .haddr_o ( mst_haddr [0] ), // ahb transaction address 529 | .hburst_o ( mst_hburst [0] ), // ahb burst: tied to single 530 | .hmastlock_o ( ), // ahb locked transfer (always zero) 531 | .hprot_o ( mst_hprot [0] ), // ahb protection: priv; data or inst 532 | .hsize_o ( mst_hsize [0] ), // ahb size: byte, half-word or word 533 | .htrans_o ( mst_htrans [0] ), // ahb transfer: non-sequential only 534 | .hwdata_o ( mst_hwdata [0] ), // ahb write-data 535 | .hwrite_o ( mst_hwrite [0] ), // ahb write control 536 | .hrdata_i ( mst_hrdata [0] ), // ahb read-data 537 | .hready_i ( mst_hreadyout [0] ), // mst_hready_0, // ahb stall signal 538 | .hresp_i ( 1'b0 ), // mst_hresp_0, // ahb error response 539 | // miscellaneous 540 | .nmi_i ( 1'b0 ), // non-maskable interrupt input 541 | .irq_i ( irq_vector ), // interrupt request inputs 542 | .txev_o ( ), // event output (sev executed) 543 | .rxev_i ( 1'b0 ), // event input 544 | .lockup_o ( led2 ), // core is locked-up 545 | .sysresetreq_o ( ), // system reset request 546 | // power management 547 | .sleeping_o ( led1 ) ); // core and nvic sleeping 548 | 549 | assign mst_hready [0] = 1'b1; // Cortex M0 has no hreadyout 550 | assign mst_hsel [0] = 1'b1; // Cortex M0 has no hsel 551 | 552 | endmodule // cm0_softmc_top 553 | --------------------------------------------------------------------------------