├── .gitignore
├── 1 - Basics
    ├── 03 - Simple Wire.v
    ├── 02 - Output Zero.v
    ├── 05 - Not Gate.v
    ├── 08 - XNOR Gate.v
    ├── 06 - And Gate.v
    ├── 01 - Getting Started.v
    ├── 07 - Nor  Gate.v
    ├── 04 - Four Wires.v
    ├── 09 - Declaring Wires.v
    └── 10 - 7458 Chip Design.v
├── 3 - Modules
    ├── 1 - Modules.v
    ├── 2 - Connect ports by position.v
    ├── 4  - Connecting Three Modules.v
    ├── 6 - Adder1.v
    ├── 3 - Connect by Name.v
    ├── 7 - adder2-design a 1-bit adder.v
    ├── 9 - Adder Subtractor.v
    ├── 8 - Carry Select Adder.v
    └── 5 - Modules and Vectors.v
├── 6 - Combinational Logic
    ├── 1- Basic Gates
    │   ├── 2 - GND.v
    │   ├── 1- Wire.v
    │   ├── 10 - Simple circuit A.v
    │   ├── 11 - Simple circuit B.v
    │   ├── 3 - NOR.v
    │   ├── 9 - Two-bit equality.v
    │   ├── 4 - Another gate.v
    │   ├── 5 - Two Gates.v
    │   ├── 7 - 7420 chip.v
    │   ├── 8 - Truth table.v
    │   ├── 13 - Ring or vibrate.v
    │   ├── 15 - 3-bit population count.v
    │   ├── 14 - Thermostat.v
    │   ├── 16 - Gates and vectors.v
    │   ├── 17 - Even longer vectors.v
    │   ├── 6 - More logic gates.v
    │   └── 12 - Combine Circuits A and B.v
    ├── 2 - Multiplexers
    │   ├── 1 - 2 to 1 Multiplexer.v
    │   ├── 2 - 2 to 1 Bus multiplexer.v
    │   ├── 4 - 256to1 4-bit multiplexer.v
    │   └── 3 - 9 to 1 Multiplexer.v
    ├── 4 - K Maps
    │   ├── 7 - K Map.v
    │   ├── 1 - Three Variable.v
    │   ├── 6 - K Map with dont care terms.v
    │   ├── 4 - Four Variable.v
    │   ├── 3 - Four Variable - SOP.v
    │   ├── 2 - Four Variable-POS.v
    │   ├── 5 - Minimum SOp & POS.v
    │   └── 8 - K Map Implemented with a Multiplexer.v
    └── 3 - Arithmatic Circuits
    │   ├── 1 - Half adder.v
    │   ├── 2 - Full Adder.v
    │   ├── 3 - 3-bit binary adder.v
    │   ├── 4 - Adder.v
    │   ├── 6 - 4-digit BDC adder.v
    │   ├── 5 - 100-bit binray Adder.v
    │   └── 7 - Signed addition overflow.v
├── 2 - Vectors
    ├── 7 - Vector Reversal.v
    ├── 9 - More Replication.v
    ├── 5 - Four Input Gate.v
    ├── 8 - Replication Operator.v
    ├── 4 - Bitwise Operators.v
    ├── 3 - Vector part select.v
    ├── 1 - Vectors.v
    ├── 2 - Vectors in more detail.v
    └── 6 - Vector Concatanation Operator.v
├── 8 - Verification
    └── 1 - Finding Bugs in  the Code
    │   ├── 2 - Nand gate fix.v
    │   ├── 1 - 2to1 Mux fix.v
    │   ├── 3 - 4 to 1 Mux fix.v
    │   ├── 4 - Adder subtractor fix.v
    │   └── 5 - Case Statement fix.v
├── 5 - More Verilog Features
    ├── 2 - reduction operators.v
    ├── 3 - reduction - even wider  gates.v
    ├── 4 - combinational for loop - vector reversal.v
    ├── 1 - Conditional Ternary Operator.v
    ├── 5 - Combinational for loop- 255 bit population count.v
    ├── 7 - Generate for loops - 100 digit BCD Adder.v
    └── 6 - Generate for loop - 100-bit Binary Adder.v
├── 7 - Sequential Logic
    ├── 1 - Latches & Flipflops
    │   ├── 2 - 8 D Flipflops.v
    │   ├── 10 - DFF+gate (XOR).v
    │   ├── 1 - D Flipflop.v
    │   ├── 9 - DFF2.v
    │   ├── 8 - DFF.v
    │   ├── 15 - Detect an edge.v
    │   ├── 16 - Detect both edges.v
    │   ├── 11 - MUX and DFF.v
    │   ├── 4 - DFF with reset value (negedge).v
    │   ├── 17 - Double edge triggered flip flop.v
    │   ├── 3 - DFF With Reset.v
    │   ├── 12 - MUX and DFF2.v
    │   ├── 5 - DFF with Asynchronus reset.v
    │   ├── 7 - D Latch.v
    │   └── 6 - DFF with byte enable.v
    └── 2 - Counters
    │   ├── 1 - Four-bit binary counter.v
    │   ├── 3 - Decade counter (1 to  10).v
    │   ├── 2 - Decade counter.v
    │   └── 4 - Slow decade counter.v
├── README.md
├── 4 - Procedures
    ├── 6 - Priority Encorder - LSB.v
    ├── 4 - If statement Latches.v
    ├── 3 - If Statement.v
    ├── 5 - Case Statement.v
    ├── 8 -Avoiding Latches - Alternative way.v
    ├── 2 - Always Block_clocked.v
    ├── 7 - Priority encorder with casez.v
    └── 1 - always_blocks_combinational.v
└── LICENSE


/.gitignore:
--------------------------------------------------------------------------------
1 | *.txt
2 | 


--------------------------------------------------------------------------------
/1 - Basics/03 - Simple Wire.v:
--------------------------------------------------------------------------------
1 | module top_module( input in, output out );
2 | 	assign out = in;
3 | endmodule
4 | 


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/3 - Modules/1 - Modules.v:
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1 | module top_module ( input a, input b, output out );
2 |     mod_a instance_1(a,b,out);
3 | endmodule
4 | 


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/6 - Combinational Logic/1- Basic Gates/2 - GND.v:
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1 | module top_module (
2 |     output out);
3 | 	assign out = 1'b0;
4 | endmodule
5 | 


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/1 - Basics/02 - Output Zero.v:
--------------------------------------------------------------------------------
1 | module top_module(output zero);// Module body starts after semicolon
2 | 	assign zero = 0;
3 | endmodule
4 | 


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/1 - Basics/05 - Not Gate.v:
--------------------------------------------------------------------------------
1 | module top_module( input in, output out );
2 |     assign out = ~in;//~ : bitwise negation operator
3 | endmodule
4 | 


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/1 - Basics/08 - XNOR Gate.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input a, 
3 |     input b, 
4 |     output out );
5 |     assign out = ~(a^b); 
6 | endmodule
7 | 


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/6 - Combinational Logic/1- Basic Gates/1- Wire.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input in,
3 |     output out);
4 | 	assign out = in;
5 |     
6 | endmodule
7 | 


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/6 - Combinational Logic/1- Basic Gates/10 - Simple circuit A.v:
--------------------------------------------------------------------------------
1 | module top_module (input x, input y, output z);
2 |     assign z = (x^y) & x;
3 | endmodule
4 | 


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/6 - Combinational Logic/1- Basic Gates/11 - Simple circuit B.v:
--------------------------------------------------------------------------------
1 | module top_module ( input x, input y, output z );
2 |     assign z= ~(x^y);
3 | endmodule
4 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/3 - NOR.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input in1,
3 |     input in2,
4 |     output out);
5 |     assign out = ~(in1|in2);
6 | endmodule
7 | 


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/6 - Combinational Logic/1- Basic Gates/9 - Two-bit equality.v:
--------------------------------------------------------------------------------
1 | module top_module ( input [1:0] A, input [1:0] B, output z ); 
2 |     assign z = (A==B);
3 | 
4 | endmodule
5 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/4 - Another gate.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input in1,
3 |     input in2,
4 |     output out);
5 | 	assign out = in1&&~in2;
6 | endmodule
7 | 


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/6 - Combinational Logic/2 - Multiplexers/1 - 2 to 1 Multiplexer.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input a, b, sel,
3 |     output out ); 
4 | 	
5 |     assign out  = sel?b:a;
6 | endmodule
7 | 


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/6 - Combinational Logic/4 - K Maps/7 - K Map.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input [4:1] x,
3 |     output f
4 | ); 
5 |     assign f = (~x[1]&x[3])|(~x[2]&~x[4])|(x[2]&x[3]&x[4]);
6 | endmodule


--------------------------------------------------------------------------------
/1 - Basics/06 - And Gate.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input a, 
3 |     input b, 
4 |     output out );
5 | 	
6 |     assign out = a & b;	// & : Bit-wise and operator
7 |     
8 | endmodule
9 | 


--------------------------------------------------------------------------------
/2 - Vectors/7 - Vector Reversal.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input [7:0] in,
3 |     output [7:0] out
4 | );
5 |     assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
6 | endmodule
7 | 


--------------------------------------------------------------------------------
/1 - Basics/01 - Getting Started.v:
--------------------------------------------------------------------------------
1 | module top_module( output one );
2 | 
3 | // Insert your code here
4 |     assign one = 1; //assign allows to drive an output continuously with a value
5 | 
6 | endmodule
7 | 


--------------------------------------------------------------------------------
/1 - Basics/07 - Nor  Gate.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input a, 
3 |     input b, 
4 |     output out );
5 |     assign out = ~(a|b); //NOR gate using bitwise OR  and NOT operators
6 | 
7 | endmodule
8 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/2 - Multiplexers/2 - 2 to 1 Bus multiplexer.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input [99:0] a, b,
3 |     input sel,
4 |     output [99:0] out );
5 | 	assign out = sel?b:a;
6 | endmodule
7 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/4 - K Maps/1 - Three Variable.v:
--------------------------------------------------------------------------------
1 | module top_module(
2 |     input a,
3 |     input b,
4 |     input c,
5 |     output out  ); 
6 |     assign out = a&(~b)&(~c) | c | b&(~c);
7 | endmodule


--------------------------------------------------------------------------------
/6 - Combinational Logic/4 - K Maps/6 - K Map with dont care terms.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input [4:1] x, 
3 |     output f );
4 | 	
5 |     assign f = (x[2]&x[4])|(x[3]&x[4])|(x[3]&~x[1]);
6 | endmodule
7 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/3 - Arithmatic Circuits/1 - Half adder.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input a, b,
3 |     output cout, sum );
4 | 	
5 |     assign sum  = a^b;
6 |     assign cout = a&b;
7 |         
8 | endmodule
9 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/3 - Arithmatic Circuits/2 - Full Adder.v:
--------------------------------------------------------------------------------
1 | module top_module( 
2 |     input a, b, cin,
3 |     output cout, sum );
4 |     
5 | 	assign cout = a&b | b&cin | a&cin;
6 | 	assign sum  = a^b^cin;
7 | endmodule


--------------------------------------------------------------------------------
/6 - Combinational Logic/4 - K Maps/4 - Four Variable.v:
--------------------------------------------------------------------------------
 1 | module top_module(
 2 |     input a,
 3 |     input b,
 4 |     input c,
 5 |     input d,
 6 |     output out  ); 
 7 | 	
 8 |     assign out = a^b^c^d;
 9 |     
10 | endmodule


--------------------------------------------------------------------------------
/1 - Basics/04 - Four Wires.v:
--------------------------------------------------------------------------------
1 | module top_module( input a,b,c,output w,x,y,z );
2 |     
3 |     assign w = a; //assign statements are executed in parallel
4 |     assign x = b;
5 |     assign y = b;
6 |     assign z = c;
7 | endmodule
8 | 


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/6 - Combinational Logic/4 - K Maps/3 - Four Variable - SOP.v:
--------------------------------------------------------------------------------
 1 | module top_module(
 2 |     input a,
 3 |     input b,
 4 |     input c,
 5 |     input d,
 6 |     output out  ); 
 7 | 	
 8 |     assign out = a|(~a&~b&c);
 9 | endmodule
10 | 


--------------------------------------------------------------------------------
/8 - Verification/1 - Finding Bugs in  the Code/2 - Nand gate fix.v:
--------------------------------------------------------------------------------
1 | module top_module (input a, input b, input c, output out);//
2 | 	wire con;
3 |     andgate inst1 ( con, a, b, c, 1'b1, 1'b1);
4 |     assign out = ~con;
5 | 
6 | endmodule
7 | 


--------------------------------------------------------------------------------
/5 - More Verilog Features/2 - reduction operators.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input [7:0] in,
3 |     output parity); 
4 |     //even parity is calculated by XOR ing all the data bits
5 |     
6 |     assign parity = ^in;
7 | 
8 | endmodule
9 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/2 - 8 D Flipflops.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input [7:0] d,
 4 |     output [7:0] q
 5 | );
 6 |     always @ (posedge clk) begin
 7 |     	q <= d;
 8 |     end
 9 | endmodule
10 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/10 - DFF+gate (XOR).v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input in, 
 4 |     output out);
 5 | 	
 6 |     always @ (posedge clk) begin
 7 |     	out <= out ^ in;
 8 |     end
 9 | endmodule
10 | 


--------------------------------------------------------------------------------
/8 - Verification/1 - Finding Bugs in  the Code/1 - 2to1 Mux fix.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input sel,
3 |     input [7:0] a,
4 |     input [7:0] b,
5 |     output [7:0] out  );
6 | 
7 |     assign out = ({8{sel}} & a) | ({8{~sel}} & b);
8 | 
9 | endmodule


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/5 - Two Gates.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input in1,
 3 |     input in2,
 4 |     input in3,
 5 |     output out);
 6 | 	
 7 |     wire wire1;
 8 |     assign wire1 = ~(in1^in2);
 9 |     assign out   = wire1^in3;
10 | endmodule
11 | 


--------------------------------------------------------------------------------
/3 - Modules/2 - Connect ports by position.v:
--------------------------------------------------------------------------------
 1 | module top_module ( 
 2 |     input a, 
 3 |     input b, 
 4 |     input c,
 5 |     input d,
 6 |     output out1,
 7 |     output out2
 8 | );
 9 |     //connect module by position
10 |     mod_a inst_1(out1,out2,a,b,c,d);
11 | 
12 | endmodule


--------------------------------------------------------------------------------
/3 - Modules/4  - Connecting Three Modules.v:
--------------------------------------------------------------------------------
1 | module top_module ( input clk, input d, output q );
2 |     wire con1,con2;
3 |     
4 |     my_dff d_flop1(.clk(clk),.d(d),.q(con1));
5 |     my_dff d_flop2(.clk(clk),.d(con1),.q(con2));
6 |     my_dff d_flop3(.clk(clk),.d(con2),.q(q));
7 | endmodule


--------------------------------------------------------------------------------
/5 - More Verilog Features/3 - reduction - even wider  gates.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [99:0] in,
 3 |     output out_and,
 4 |     output out_or,
 5 |     output out_xor 
 6 | );
 7 | 	assign out_and = &in;
 8 |     assign out_or  = |in;
 9 |     assign out_xor = ^in;
10 | endmodule


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/1 - D Flipflop.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,    // Clocks are used in sequential circuits
 3 |     input d,
 4 |     output reg q );//
 5 | 
 6 |     always @ (posedge clk) begin
 7 |     	q <= d;
 8 |     
 9 |     end
10 | 
11 | endmodule
12 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/9 - DFF2.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input d, 
 4 |     input r,   // synchronous reset
 5 |     output q);
 6 |     always @ (posedge clk) begin
 7 |         if (r) q <= 1'b0;
 8 |         else   q <= d;
 9 |     end
10 | endmodule


--------------------------------------------------------------------------------
/3 - Modules/6 - Adder1.v:
--------------------------------------------------------------------------------
 1 | module top_module(
 2 |     input [31:0] a,
 3 |     input [31:0] b,
 4 |     output [31:0] sum
 5 | );
 6 |     wire con1, con2;
 7 |     add16 adder_1(a[15:0], b[15:0], 0, sum[15:0], con1);
 8 |     add16 adder_2(a[31:16], b[31:16], con1, sum[31:16], con2);
 9 | 
10 | endmodule


--------------------------------------------------------------------------------
/6 - Combinational Logic/4 - K Maps/2 - Four Variable-POS.v:
--------------------------------------------------------------------------------
 1 | //Here product of sum is used.
 2 | 
 3 | module top_module(
 4 |     input a,
 5 |     input b,
 6 |     input c,
 7 |     input d,
 8 |     output out  ); 
 9 | 	
10 |     assign out = (c|!d|!b) & (!a|!b|c) & (a|b|!c|!d) & (!a|!c|d);
11 | endmodule
12 | 


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/6 - Combinational Logic/4 - K Maps/5 - Minimum SOp & POS.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input a,
 3 |     input b,
 4 |     input c,
 5 |     input d,
 6 |     output out_sop,
 7 |     output out_pos
 8 | ); 
 9 |     assign out_sop = (c&d)|(~a&~b&c);
10 |     assign out_pos = c&(~b|~c|d)&(~a|~c|d);
11 | endmodule
12 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # HDL-Bits-Solutions
2 | This is a repository containing solutions to  the  problem statements given in HDL Bits website. It has 180 problems covering various aspects of Digital designing such as Flipflops, Latches, Combinational circuits, FSMs etc. 
3 | 
4 | Link : https://hdlbits.01xz.net/wiki/Main_Page
5 | 


--------------------------------------------------------------------------------
/2 - Vectors/9 - More Replication.v:
--------------------------------------------------------------------------------
1 | module top_module (
2 |     input a, b, c, d, e,
3 |     output [24:0] out );//
4 | 
5 |     // The output is XNOR of two vectors created by 
6 |     // concatenating and replicating the five inputs.
7 |     assign out = ~{ {5{a}},{5{b}},{5{c}},{5{d}},{5{e}}} ^ { {5{a,b,c,d,e}}};
8 | endmodule


--------------------------------------------------------------------------------
/3 - Modules/3 - Connect by Name.v:
--------------------------------------------------------------------------------
 1 | module top_module ( 
 2 |     input a, 
 3 |     input b, 
 4 |     input c,
 5 |     input d,
 6 |     output out1,
 7 |     output out2
 8 | );
 9 |     //connect ports by name
10 |     mod_a inst_1(.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2));
11 | 
12 | endmodule
13 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/7 - 7420 chip.v:
--------------------------------------------------------------------------------
 1 | module top_module ( 
 2 |     input p1a, p1b, p1c, p1d,
 3 |     output p1y,
 4 |     input p2a, p2b, p2c, p2d,
 5 |     output p2y );
 6 | 	
 7 |     assign p1y = ~(p1a && p1b && p1c && p1d);
 8 |     assign p2y = ~(p2a && p2b && p2c && p2d);
 9 | 
10 | endmodule
11 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/8 - Truth table.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input x3,
 3 |     input x2,
 4 |     input x1,  // three inputs
 5 |     output f   // one output
 6 | );
 7 | 	//here sum of products is used
 8 |     assign f = (~x3&x2&~x1) | (~x3&x2&x1) | (x3&~x2&x1) | (x3&x2&x1);
 9 | endmodule
10 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/2 - Counters/1 - Four-bit binary counter.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input reset,      // Synchronous active-high reset
 4 |     output [3:0] q);
 5 | 
 6 |     always @ (posedge clk) begin
 7 |         if (reset) q <= 4'd0;
 8 |         else q <= q+4'd1;
 9 |     end
10 | endmodule


--------------------------------------------------------------------------------
/5 - More Verilog Features/4 - combinational for loop - vector reversal.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [99:0] in,
 3 |     output [99:0] out
 4 | );
 5 |     integer i;
 6 |     always @ (in) begin 
 7 |         for (i=0;i<100; i=i+1) begin
 8 |             out[99-i] = in[i];
 9 |         end        
10 |     end
11 | endmodule


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/8 - DFF.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input d, 
 4 |     input ar,   // asynchronous reset
 5 |     output q);
 6 |     
 7 |     always @ (posedge clk, posedge ar) begin
 8 |         if (ar) q<=1'b0;
 9 |         else q<=d;
10 |         
11 |     end
12 | endmodule
13 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/13 - Ring or vibrate.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input ring,
 3 |     input vibrate_mode,
 4 |     output ringer,       // Make sound
 5 |     output motor         // Vibrate
 6 | );
 7 |     assign motor  = vibrate_mode && ring;
 8 |     assign ringer = (~vibrate_mode) && ring;
 9 | endmodule
10 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/4 - K Maps/8 - K Map Implemented with a Multiplexer.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input a,
 3 |     input b,
 4 |     input c,
 5 |     input d,
 6 |     output out_sop,
 7 |     output out_pos
 8 | ); 
 9 |     assign out_sop = (c&d)|(~a&~b&c);
10 |     assign out_pos = c&(~b|~c|d)&(~a|~c|d);
11 | endmodule
12 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/2 - Counters/3 - Decade counter (1 to  10).v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input reset,
 4 |     output [3:0] q);
 5 | 
 6 |     always @ (posedge clk) begin
 7 |         if (reset) q <= 4'd1;
 8 |         else if (q == 4'd10) q<= 4'd1;
 9 |         else q <= q+4'd1;
10 |     end
11 |     
12 | endmodule
13 | 


--------------------------------------------------------------------------------
/2 - Vectors/5 - Four Input Gate.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [3:0] in,
 3 |     output out_and,
 4 |     output out_or,
 5 |     output out_xor
 6 | );
 7 |     
 8 |     assign out_and = in[3] && in[2] && in[1] && in[0];
 9 |     assign out_or = in[3] || in[2] || in[1] || in[0];
10 |     assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
11 | 
12 | endmodule


--------------------------------------------------------------------------------
/7 - Sequential Logic/2 - Counters/2 - Decade counter.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input reset,        // Synchronous active-high reset
 4 |     output [3:0] q);
 5 |     
 6 |     always @ (posedge clk) begin
 7 |         if (reset) q <= 4'd0;
 8 |         else if (q == 4'd9) q<= 4'd0;
 9 |         else q <= q+4'd1;
10 |     end
11 | endmodule


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/15 - Detect an edge.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input [7:0] in,
 4 |     output [7:0] pedge
 5 | );
 6 |     reg [7:0]intermediate;
 7 |     
 8 |     always @ (posedge clk) begin
 9 |         intermediate <= in;
10 |         pedge        <= (~intermediate) & in;
11 |     end
12 | 
13 | endmodule
14 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/16 - Detect both edges.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input [7:0] in,
 4 |     output [7:0] anyedge
 5 | );
 6 |   	reg [7:0]intermediate;
 7 |     
 8 |     always @ (posedge clk) begin
 9 |         intermediate   <= in;
10 |         anyedge        <= intermediate ^ in;
11 |     end
12 | endmodule
13 | 


--------------------------------------------------------------------------------
/2 - Vectors/8 - Replication Operator.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input [7:0] in,
 3 |     output [31:0] out );//
 4 | 	// The replication operator allows repeating a vector and concatenating them together:
 5 | 	//{num{vector}}
 6 |     
 7 |     //this is sign-extending a smaller number to a larger one
 8 |     assign out = { {24{in[7]}} , in[7:0] };
 9 | 
10 | endmodule


--------------------------------------------------------------------------------
/5 - More Verilog Features/1 - Conditional Ternary Operator.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input [7:0] a, b, c, d,
 3 |     output [7:0] min);
 4 |     
 5 |     wire [7:0] int1, int2;
 6 |     
 7 |     //condition ? if_true : if_false
 8 |     assign int1 = (a<b)? a:b; 
 9 |     assign int2 = (int1<c)? int1:c;
10 |     assign min  = (int2<d)? int2:d;
11 | endmodule
12 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/15 - 3-bit population count.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [2:0] in,
 3 |     output [1:0] out );
 4 |     integer i,count;
 5 | 	always @ * begin
 6 |         count = 0;
 7 |         for (i=0; i<3;i=i+1) begin
 8 |             if (in[i]==1'b1) count=count+1;
 9 |         end
10 |         out = count;
11 |     end
12 | endmodule


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/11 - MUX and DFF.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 | 	input clk,
 3 | 	input L,
 4 | 	input r_in,
 5 | 	input q_in,
 6 | 	output reg Q);
 7 |     
 8 |     always @ (posedge clk) begin
 9 |         case (L)
10 |             1'b0 : Q <= q_in;
11 |             1'b1 : Q <= r_in;
12 |         endcase    
13 |     end
14 | 
15 | endmodule
16 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/4 - DFF with reset value (negedge).v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input reset,
 4 |     input [7:0] d,
 5 |     output [7:0] q
 6 | );
 7 |     always @ (negedge clk) begin
 8 |         //this is an active high  synchronous reset
 9 |         if (reset==1'b1) q<=8'h34;
10 |         else q <= d;
11 |     end
12 | endmodule


--------------------------------------------------------------------------------
/1 - Basics/09 - Declaring Wires.v:
--------------------------------------------------------------------------------
 1 | `default_nettype none
 2 | module top_module(
 3 |     input a,
 4 |     input b,
 5 |     input c,
 6 |     input d,
 7 |     output out,
 8 |     output out_n   ); 
 9 | 	
10 |     wire int1,int2;
11 |     
12 |     assign int1 = a&b;
13 |     assign int2 = c&d;
14 |     assign out = int1|int2;
15 |     assign out_n = ~out;
16 |     
17 | endmodule
18 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/17 - Double edge triggered flip flop.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input d,
 4 |     output q
 5 | );
 6 |     reg q1,q2;
 7 |     always @ (posedge clk) begin
 8 |     	q1 <= q2^d; 
 9 |     end
10 |     
11 |     always @ (negedge clk) begin
12 |     	q2 <= q1^d; 
13 |     end
14 |     
15 |     assign q = q1^q2; 
16 | endmodule


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/3 - DFF With Reset.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input reset,            // Synchronous reset
 4 |     input [7:0] d,
 5 |     output [7:0] q
 6 | );
 7 | 	always @ (posedge clk) begin
 8 |         //this is an active high  synchronous reset
 9 |         if (reset) q<=8'b0;
10 |         else q <= d;
11 |     end
12 | endmodule


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/14 - Thermostat.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input too_cold,
 3 |     input too_hot,
 4 |     input mode,
 5 |     input fan_on,
 6 |     output heater,
 7 |     output aircon,
 8 |     output fan
 9 | ); 
10 | 	assign heater = mode && too_cold;
11 |     assign aircon = (~mode) && too_hot;
12 |     assign fan    = aircon || heater || fan_on;
13 | endmodule


--------------------------------------------------------------------------------
/2 - Vectors/4 - Bitwise Operators.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [2:0] a,
 3 |     input [2:0] b,
 4 |     output [2:0] out_or_bitwise,
 5 |     output out_or_logical,
 6 |     output [5:0] out_not
 7 | );
 8 |     
 9 |     assign out_or_bitwise = a|b;
10 |     assign out_or_logical = a||b;
11 |     assign out_not[5:3]   = ~b; //this is bitwise not
12 |     assign out_not[2:0]   = ~a;
13 | 
14 | endmodule
15 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/2 - Counters/4 - Slow decade counter.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input slowena,
 4 |     input reset,
 5 |     output [3:0] q);
 6 | 
 7 |     always @ (posedge clk) begin
 8 |         if (reset) q <= 4'd0;
 9 |         else if (slowena) begin
10 |         	if (q == 4'd9) q<= 4'd0;
11 |         	else q <= q+4'd1;
12 |         end
13 |     end
14 |     
15 | endmodule
16 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/12 - MUX and DFF2.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input w, R, E, L,
 4 |     output Q
 5 | );
 6 |     wire [1:0] con;
 7 |     assign con = {E,L};
 8 | 	always @ (posedge clk) begin
 9 |         case (con)
10 |             2'b00 : Q <= Q;
11 |             2'b01 : Q <= R;
12 | 			2'b10 : Q <= w;
13 |             2'b11 : Q <= R;        
14 |         endcase    
15 |     end
16 | 
17 | endmodule


--------------------------------------------------------------------------------
/4 - Procedures/6 - Priority Encorder - LSB.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input [3:0] in,
 3 |     output reg [1:0] pos  );
 4 |     always @(*) begin
 5 |         if (in[0]==1'b1)
 6 |             pos = 0;
 7 |         else if (in[1]==1'b1)
 8 |             pos = 1;
 9 |         else if (in[2]==1'b1)
10 |             pos = 2;
11 |         else if (in[3]==1'b1)
12 |             pos = 3;
13 |         else
14 |             pos = 0;
15 |     end
16 | endmodule
17 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/2 - Multiplexers/4 - 256to1 4-bit multiplexer.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [1023:0] in,
 3 |     input [7:0] sel,
 4 |     output [3:0] out );
 5 | 	
 6 |     integer range;
 7 |     wire [7:0]con1; 
 8 |     
 9 |     always @ (*) begin
10 |         range = sel;
11 |     	//max_lim = sel;
12 |         //min_lim = ;
13 |         //con1 = sel+sel+sel+sel; 
14 |         out  = in[sel*4 +:4]; //vector[LSB+:width]
15 |         
16 |     end
17 | endmodule


--------------------------------------------------------------------------------
/3 - Modules/7 - adder2-design a 1-bit adder.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input [31:0] a,
 3 |     input [31:0] b,
 4 |     output [31:0] sum
 5 | );//
 6 | 	wire con1, con2;
 7 |     add16 adder_1(a[15:0], b[15:0], 0, sum[15:0], con1);
 8 |     add16 adder_2(a[31:16], b[31:16], con1, sum[31:16], con2);
 9 | endmodule
10 | 
11 | module add1 ( input a, input b, input cin,   output sum, output cout );
12 |     assign sum  = a^b^cin;
13 |     assign cout = (a&b)|(a&cin)|(b&cin);
14 | endmodule


--------------------------------------------------------------------------------
/8 - Verification/1 - Finding Bugs in  the Code/3 - 4 to 1 Mux fix.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input [1:0] sel,
 3 |     input [7:0] a,
 4 |     input [7:0] b,
 5 |     input [7:0] c,
 6 |     input [7:0] d,
 7 |     output [7:0] out  ); 
 8 | 
 9 |     wire [7:0] mux_con_0, mux_con_1;
10 |     mux2 mux_inst_0 ( sel[0],    a,    b, mux_con_0 );
11 |     mux2 mux_inst_1 ( sel[0],    c,    d, mux_con_1 );
12 |     mux2 mux_inst_2 ( sel[1], mux_con_0, mux_con_1,  out );
13 | 
14 | endmodule


--------------------------------------------------------------------------------
/4 - Procedures/4 - If statement Latches.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input      cpu_overheated,
 3 |     output reg shut_off_computer,
 4 |     input      arrived,
 5 |     input      gas_tank_empty,
 6 |     output reg keep_driving  ); //
 7 | 
 8 |     always @(*) begin
 9 |         if (cpu_overheated)
10 |            shut_off_computer = 1;
11 |     end
12 | 
13 |     always @(*) begin
14 |         if (~arrived)
15 |            keep_driving = ~gas_tank_empty;
16 |     end
17 | 
18 | endmodule
19 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/5 - DFF with Asynchronus reset.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     //clocking signal cannot  be referenced anywhere in the always block 
 3 |     input clk,
 4 |     input areset,   // active high asynchronous reset
 5 |     input [7:0] d,
 6 |     output [7:0] q
 7 | );
 8 |     always @ (posedge clk or posedge areset ) begin
 9 |         //this is an active high  asynchronous reset
10 |         if (areset==1'b1) q<= 1'b0;
11 |         else q <= d;
12 |     end
13 | endmodule


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/16 - Gates and vectors.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [3:0] in,
 3 |     output [2:0] out_both,
 4 |     output [3:1] out_any,
 5 |     output [3:0] out_different );
 6 | 	
 7 |     assign out_both      = in[2:0] & in[3:1];//here bits of input vector is shifted right 
 8 |     									//and bitwise and is performed to obtain the required output
 9 |     assign out_any       = in[3:1] | in[2:0];
10 |     assign out_different = in ^ {in[0],in[3:1]};
11 |     
12 | endmodule
13 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/17 - Even longer vectors.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [99:0] in,
 3 |     output [98:0] out_both,
 4 |     output [99:1] out_any,
 5 |     output [99:0] out_different );
 6 | 	
 7 |     assign out_both      = in[98:0] & in[99:1];//here bits of input vector is shifted right 
 8 |     									//and bitwise and is performed to obtain the required output
 9 |     assign out_any       = in[99:1] | in[98:0];
10 |     assign out_different = in ^ {in[0],in[99:1]};
11 |  
12 | endmodule
13 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/3 - Arithmatic Circuits/3 - 3-bit binary adder.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [2:0] a, b,
 3 |     input cin,
 4 |     output [2:0] cout,
 5 |     output [2:0] sum );
 6 | 
 7 |     FA FA1(a[0],b[0],cin,cout[0],sum[0]);
 8 |     FA FA2(a[1],b[1],cout[0],cout[1],sum[1]);
 9 |     FA FA3(a[2],b[2],cout[1],cout[2],sum[2]);
10 |     
11 | endmodule
12 | 
13 | module FA( 
14 |     input a, b, cin,
15 |     output cout, sum );
16 |     
17 | 	assign cout = a&b | b&cin | a&cin;
18 | 	assign sum  = a^b^cin;
19 | endmodule


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/6 - More logic gates.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input a, b,
 3 |     output out_and,
 4 |     output out_or,
 5 |     output out_xor,
 6 |     output out_nand,
 7 |     output out_nor,
 8 |     output out_xnor,
 9 |     output out_anotb
10 | );
11 | 	assign out_and   = a && b;
12 |     assign out_or    = a || b;
13 |     assign out_xor   = a ^ b;
14 |     assign out_nand  = ~(a&&b);
15 |     assign out_nor   = ~(a||b);
16 |     assign out_xnor  = ~(a^b);
17 |     assign out_anotb =  a&&~b;
18 | endmodule
19 | 


--------------------------------------------------------------------------------
/2 - Vectors/3 - Vector part select.v:
--------------------------------------------------------------------------------
 1 | //byte reversing
 2 | //This operation is often used when the endianness of a piece of data needs to be swapped, 
 3 | //for example between little-endian x86 systems and the big-endian formats used in many Internet protocols.
 4 | `default_nettype none
 5 | 
 6 | module top_module( 
 7 |     input [31:0] in,
 8 |     output [31:0] out );//
 9 | 
10 |     assign out[7:0] = in[31:24];
11 |     assign out[15:8] = in[23:16];
12 |     assign out[23:16] = in[15:8];
13 |     assign out[31:24] = in[7:0];
14 | endmodule
15 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/1- Basic Gates/12 - Combine Circuits A and B.v:
--------------------------------------------------------------------------------
 1 | module top_module (input x, input y, output z);
 2 |     wire z1, z2, z3, z4,z5,z6;
 3 |     
 4 |     A IA1(x,y,z1);
 5 |     B IB1(x,y,z2);
 6 |     A IA2(x,y,z3);
 7 |     B IB2(x,y,z4);
 8 |     
 9 |     assign z5 = z1||z2;
10 |     assign z6 = z3&&z4;
11 |     assign  z = z5^z6;
12 | endmodule
13 | 
14 | module B( input x, input y, output z );
15 |     assign z= ~(x^y);
16 | endmodule
17 | 
18 | module A(input x, input y, output z);
19 |     assign z = (x^y) & x;
20 | endmodule
21 | 
22 | 


--------------------------------------------------------------------------------
/5 - More Verilog Features/5 - Combinational for loop- 255 bit population count.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [254:0] in,
 3 |     output [7:0] out );
 4 |     
 5 | 	//A "population count" circuit counts the number of '1's in an input vector.
 6 | 
 7 |     integer i;
 8 |     reg [7:0] counter;
 9 |     always @ (in) begin
10 |         counter = 0;
11 |         for (i=0; i<255; i=i+1) begin
12 |             if (in[i]==1'b1) 
13 |                 counter = counter+1'b1;
14 |         end
15 |        	
16 |         out = counter;
17 |     end
18 | 
19 | endmodule


--------------------------------------------------------------------------------
/4 - Procedures/3 - If Statement.v:
--------------------------------------------------------------------------------
 1 | // synthesis verilog_input_version verilog_2001
 2 | module top_module(
 3 |     input a,
 4 |     input b,
 5 |     input sel_b1,
 6 |     input sel_b2,
 7 |     output wire out_assign,
 8 |     output reg out_always   ); 
 9 | 	
10 |     assign out_assign= (sel_b1==1'b1 && sel_b2==1'b1)? b:a;
11 |     
12 |     always @(*)begin
13 |         if (sel_b1==1'b1 && sel_b2==1'b1) begin
14 |     		out_always  = b;
15 |         end
16 |         else begin
17 |             out_always = a;
18 |         end
19 |     end
20 |     
21 | endmodule
22 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/3 - Arithmatic Circuits/4 - Adder.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input [3:0] x,
 3 |     input [3:0] y, 
 4 |     output [4:0] sum);
 5 |     wire [3:0]cout;
 6 |     
 7 |     FA FA1(x[0],y[0],0,cout[0],sum[0]);
 8 |     FA FA2(x[1],y[1],cout[0],cout[1],sum[1]);
 9 |     FA FA3(x[2],y[2],cout[1],cout[2],sum[2]);
10 |     FA FA4(x[3],y[3],cout[2],sum[4],sum[3]);
11 | endmodule
12 | 
13 | module FA( 
14 |     input a, b, cin,
15 |     output cout, sum );
16 |     
17 | 	assign cout = a&b | b&cin | a&cin;
18 | 	assign sum  = a^b^cin;
19 | endmodule
20 | 


--------------------------------------------------------------------------------
/8 - Verification/1 - Finding Bugs in  the Code/4 - Adder subtractor fix.v:
--------------------------------------------------------------------------------
 1 | // synthesis verilog_input_version verilog_2001
 2 | module top_module ( 
 3 |     input do_sub,
 4 |     input [7:0] a,
 5 |     input [7:0] b,
 6 |     output reg [7:0] out,
 7 |     output reg result_is_zero
 8 | );//
 9 | 
10 |     always @(*) begin
11 |         case (do_sub)
12 |           0: out = a+b;
13 |           1: out = a-b;
14 |         endcase
15 | 
16 |         if (out==8'd0)
17 |             result_is_zero = 1'd1;
18 |         else result_is_zero = 1'd0;
19 |     end
20 | 
21 | endmodule


--------------------------------------------------------------------------------
/3 - Modules/9 - Adder Subtractor.v:
--------------------------------------------------------------------------------
 1 | module top_module(
 2 |     input [31:0] a,
 3 |     input [31:0] b,
 4 |     input sub,
 5 |     output [31:0] result
 6 | );
 7 | 	//An XOR gate can also be viewed as a programmable inverter, where one input controls whether
 8 |     //the other should be inverted. 
 9 |     
10 |     wire wire1;
11 |     wire [31:0]b_xor;
12 |     
13 |     assign b_xor = {32{sub}}^b; 
14 |     add16 adder1(a[15:0], b_xor[15:0], sub, result[15:0], wire1);
15 |     add16 adder2(a[31:16], b_xor[31:16], wire1, result[31:16]);
16 |     
17 |     
18 | endmodule


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/7 - D Latch.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input d, 
 3 |     input ena,
 4 |     output q);
 5 | 	
 6 |     //Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
 7 | 	//However, they are still sequential elements, so should use non-blocking assignments.
 8 | 	//A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.
 9 | 
10 |     always @ (*) begin
11 |         if (ena) q<=d;
12 |     end
13 | 
14 | endmodule


--------------------------------------------------------------------------------
/5 - More Verilog Features/7 - Generate for loops - 100 digit BCD Adder.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [399:0] a, b,
 3 |     input cin,
 4 |     output cout,
 5 |     output [399:0] sum );
 6 | 	
 7 |     wire[99:0] cout_wires;
 8 |     genvar i;
 9 |     
10 |     generate
11 |         bcd_fadd(a[3:0], b[3:0], cin, cout_wires[0],sum[3:0]);
12 |         for (i=4; i<400; i=i+4) begin: bcd_adder_instances
13 |             bcd_fadd bcd_adder(a[i+3:i], b[i+3:i], cout_wires[i/4-1],cout_wires[i/4],sum[i+3:i]);
14 |         end
15 |     endgenerate
16 |     
17 |     assign cout = cout_wires[99];
18 | endmodule
19 | 


--------------------------------------------------------------------------------
/1 - Basics/10 - 7458 Chip Design.v:
--------------------------------------------------------------------------------
 1 | module top_module ( 
 2 |     //designing a  7458  chip
 3 |     input p1a, p1b, p1c, p1d, p1e, p1f,
 4 |     output p1y,
 5 |     input p2a, p2b, p2c, p2d,
 6 |     output p2y );
 7 | 	
 8 |     wire and3_wire_a, and3_wire_b, and2_wire_c, and2_wire_d;
 9 |     
10 |     assign and3_wire_a = p1a && p1b && p1c;
11 |     assign and3_wire_b = p1d && p1e && p1f;
12 |     assign and2_wire_c = p2a && p2b;
13 |     assign and2_wire_d = p2c && p2d;
14 |     
15 |     assign p1y = and3_wire_a || and3_wire_b;
16 |     assign p2y = and2_wire_c || and2_wire_d;
17 |     
18 | 
19 | endmodule
20 | 


--------------------------------------------------------------------------------
/3 - Modules/8 - Carry Select Adder.v:
--------------------------------------------------------------------------------
 1 | module top_module(
 2 |     input [31:0] a,
 3 |     input [31:0] b,
 4 |     output reg [31:0] sum
 5 | );
 6 |     wire [15:0] cout,con2;
 7 |     wire [15:0]alt_sum1, alt_sum2;
 8 |     add16 adder1(a[15:0], b[15:0], 0, sum[15:0], cout);
 9 |     add16 adder_sel1(a[31:16], b[31:16], 0, alt_sum1, con2);
10 |     add16 adder_sel2(a[31:16], b[31:16], 1, alt_sum2, con2);
11 |     
12 |     always @(cout, alt_sum1, alt_sum2) begin
13 |         case(cout)
14 |             0 : sum[31:16] = alt_sum1;
15 |             1 : sum[31:16] = alt_sum2;
16 |         endcase
17 |     end
18 | 
19 | endmodule
20 | 


--------------------------------------------------------------------------------
/7 - Sequential Logic/1 - Latches & Flipflops/6 - DFF with byte enable.v:
--------------------------------------------------------------------------------
 1 | module top_module (
 2 |     input clk,
 3 |     input resetn,
 4 |     input [1:0] byteena,
 5 |     input [15:0] d,
 6 |     output [15:0] q
 7 | );
 8 | 	always @ (posedge clk) begin
 9 |         //this is an active high  synchronous reset
10 |         if (resetn==1'b0) q<= 1'b0;
11 |         else begin
12 |             case(byteena)
13 | 				2'b00: q       <= q;
14 |                 2'b01: q[7:0]  <= d[7:0];
15 |                 2'b10: q[15:8] <= d[15:8];
16 |                 2'b11: q       <= d;
17 |             endcase
18 |         end
19 |     end	
20 | endmodule
21 | 


--------------------------------------------------------------------------------
/6 - Combinational Logic/2 - Multiplexers/3 - 9 to 1 Multiplexer.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [15:0] a, b, c, d, e, f, g, h, i,
 3 |     input [3:0] sel,
 4 |     output [15:0] out );
 5 |   
 6 |     always @ * begin
 7 |   
 8 |         case (sel)
 9 |             4'b0000 : out = a;
10 |             4'b0001 : out = b;
11 |             4'b0010 : out = c;
12 |             4'b0011 : out = d;
13 |             4'b0100 : out = e;
14 |             4'b0101 : out = f;
15 |             4'b0110 : out = g;
16 |             4'b0111 : out = h;
17 |             4'b1000 : out = i;
18 |             default : out = {16{1'b1}};
19 |         endcase
20 |     end
21 | 
22 | endmodule


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/2 - Vectors/1 - Vectors.v:
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 1 | module top_module ( 
 2 |     input wire [2:0] vec,
 3 |     output wire [2:0] outv,
 4 |     output wire o2,
 5 |     output wire o1,
 6 |     output wire o0  ); // Module body starts after module declaration
 7 | 	
 8 |     //Notice that the declaration of a vector places the dimensions before the name of the vector, which is unusual 
 9 |     //compared to C syntax. However, the part select has the dimensions after the vector name as you would expect.
10 |     
11 |     //declaring something "input" or "output" automatically declares it  as a wire
12 |     
13 |     assign outv = vec;
14 |     assign   o0 = vec[0];
15 |     assign   o1 = vec[1];
16 |     assign   o2 = vec[2];
17 |     
18 | endmodule
19 | 


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/4 - Procedures/5 - Case Statement.v:
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 1 | // synthesis verilog_input_version verilog_2001
 2 | module top_module ( 
 3 |     input [2:0] sel, 
 4 |     input [3:0] data0,
 5 |     input [3:0] data1,
 6 |     input [3:0] data2,
 7 |     input [3:0] data3,
 8 |     input [3:0] data4,
 9 |     input [3:0] data5,
10 |     output reg [3:0] out   );//
11 | 
12 |     always@(*) begin  // This is a combinational circuit
13 |         case(sel)
14 |             3'b000: out = data0;
15 |             3'b001: out = data1;
16 |             3'b010: out = data2;
17 |             3'b011: out = data3;
18 |             3'b100: out = data4;
19 |             3'b101: out = data5;
20 |             default: out = 4'b0000;
21 |         endcase
22 |     end
23 | 
24 | endmodule
25 | 


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/2 - Vectors/2 - Vectors in more detail.v:
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 1 | `default_nettype none     // Disable implicit nets. Reduces some types of bugs.
 2 | // Implicit nets are always one-bit wires and causes bugs if you had intended to use a vector. 
 3 | //Disabling creation of implicit nets can be done using the `default_nettype none directive.
 4 | 
 5 | module top_module( 
 6 |     input wire [15:0] in,
 7 |     output wire [7:0] out_hi,
 8 |     output wire [7:0] out_lo );
 9 |     //The unpacked dimensions are declared after the name. They are generally used to declare memory arrays. 
10 | 	//reg [7:0] mem [255:0];   // 256 unpacked elements, each of which is a 8-bit packed vector of reg.
11 |     
12 |     assign out_hi = in[15:8];
13 |     assign out_lo = in[7:0];
14 | endmodule
15 | 


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/6 - Combinational Logic/3 - Arithmatic Circuits/6 - 4-digit BDC adder.v:
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 1 | module top_module( 
 2 |     input [15:0] a, b,
 3 |     input cin,
 4 |     output cout,
 5 |     output [15:0] sum );
 6 |     wire [2:0]con1;
 7 |     
 8 |     //in BCD addition, if sum of digit BCD numbers is greater than 9 then we should further add 6 to the result to obtain the correct solution
 9 |     //ex : 5+3 = 8  = 0000 1000 obtained by 0101+0011      
10 |     //     8+9 = 17 = 0001 0111 obtained by 1000+1001+0110
11 |  
12 |     bcd_fadd B_add1(a[3:0],b[3:0],cin,con1[0],sum[3:0]);
13 |     bcd_fadd B_add2(a[7:4],b[7:4],con1[0],con1[1],sum[7:4]);
14 |     bcd_fadd B_add3(a[11:8],b[11:8],con1[1],con1[2],sum[11:8]);
15 |     bcd_fadd B_add4(a[15:12],b[15:12],con1[2],cout,sum[15:12]);
16 | 
17 | endmodule
18 | 


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/2 - Vectors/6 - Vector Concatanation Operator.v:
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 1 | module top_module (
 2 |     input [4:0] a, b, c, d, e, f,
 3 |     output [7:0] w, x, y, z );//
 4 | 	//Concatenation needs to know the width of every component (or how would you know the length of the result?). 
 5 |     //Thus, {1, 2, 3} is illegal and results in the error message: unsized constants are not allowed in concatenations.
 6 | 	//The concatenation operator can be used on both the left and right sides of assignments.
 7 |     
 8 |     wire [31:0] concat_reg; //raise an error when work with reg. Reason unknown???
 9 |     assign concat_reg = {a[4:0], b[4:0], c[4:0], d[4:0], e[4:0], f[4:0], 2'b11};
10 |     assign w = concat_reg[31:24];
11 |     assign x = concat_reg[23:16];
12 |     assign y = concat_reg[15:8];
13 |     assign z = concat_reg[7:0];
14 | 
15 | endmodule
16 | 


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/3 - Modules/5 - Modules and Vectors.v:
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 1 | module top_module ( 
 2 |     input clk, 
 3 |     input [7:0] d, 
 4 |     input [1:0] sel, 
 5 |     output reg [7:0] q 
 6 | );
 7 |     wire [7:0]con1,con2,con3;
 8 |     
 9 |     my_dff8 d_flop1(.clk(clk), .d(d), .q(con1));
10 |     my_dff8 d_flop2(.clk(clk), .d(con1), .q(con2) );
11 |     my_dff8 d_flop3(.clk(clk), .d(con2), .q(con3));
12 |     
13 |     always @ (*) begin
14 |         case(sel)
15 |             0 : q = d ;
16 |             1 : q = con1;
17 |             2 : q = con2;
18 |             3 : q = con3;
19 |         endcase
20 |         
21 |         /*if(sel==2'b00)
22 |             q=d;
23 |         else if( sel == 2'b01)
24 |       		q = con1;
25 |         else if( sel == 2'b10)
26 |       		q = con2;
27 |         else if( sel == 2'b11)
28 |       		q = con3;
29 |  		*/
30 |  	end
31 |     
32 | endmodule


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/4 - Procedures/8 -Avoiding Latches - Alternative way.v:
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 1 | module top_module (
 2 |     input [15:0] scancode,
 3 |     output reg left,
 4 |     output reg down,
 5 |     output reg right,
 6 |     output reg up  ); 
 7 | 	
 8 |     always @ (scancode) begin
 9 |         up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
10 |         case (scancode)
11 |             16'he06b:begin
12 |                 up = 1'b0; down = 1'b0; left = 1'b1; right = 1'b0;
13 |             end
14 |             16'he072:begin
15 |                 up = 1'b0; down = 1'b1; left = 1'b0; right = 1'b0;
16 |             end
17 |             16'he074:begin
18 |                 up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b1;
19 |             end
20 |             16'he075:begin
21 |                 up = 1'b1; down = 1'b0; left = 1'b0; right = 1'b0;
22 |             end
23 |                 
24 |         endcase
25 |     end
26 | endmodule
27 | 


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/4 - Procedures/2 - Always Block_clocked.v:
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 1 | // synthesis verilog_input_version verilog_2001
 2 | module top_module(
 3 |     input clk,
 4 |     input a,
 5 |     input b,
 6 |     output wire out_assign,
 7 |     output reg out_always_comb,
 8 |     output reg out_always_ff   );
 9 | 
10 |     //There are three types of assignments in Verilog:
11 | 		//Continuous assignments (assign x = y;). Can only be used when not inside a procedure ("always block").
12 | 		//Procedural blocking assignment: (x = y;). Can only be used inside a procedure.
13 | 		//Procedural non-blocking assignment: (x <= y;). Can only be used inside a procedure.
14 | 
15 |     //In a combinational always block, use blocking assignments. In a clocked always block, use non-blocking assignments.
16 | 
17 |     assign out_assign = a^b;
18 |     
19 |     always @ (*) begin 
20 |         out_always_comb = a^b;
21 |     end
22 |     
23 |     always @ (posedge clk) begin
24 |         out_always_ff <= a^b;
25 |     end
26 |     
27 | endmodul


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/5 - More Verilog Features/6 - Generate for loop - 100-bit Binary Adder.v:
--------------------------------------------------------------------------------
 1 | module one_bit_FA(
 2 |     input a,b,
 3 |     input cin,
 4 |     output cout,sum);
 5 | 	
 6 |     assign sum  = a^b^cin;
 7 |     assign cout = (a&b)|(b&cin)|(cin&a);
 8 | endmodule
 9 | 
10 | module top_module( 
11 |     input [99:0] a, b,
12 |     input cin,
13 |     output [99:0] cout,
14 |     output [99:0] sum );
15 | 
16 |     genvar i;
17 |     
18 |     one_bit_FA FA1(a[0],b[0],cin,cout[0],sum[0]);
19 |     
20 |     //this is a generte block
21 |     //The loop generate construct provides an easy and concise method to create multiple instances 
22 |     //of module items such as module instances, assign statements, assertions, interface instances 
23 |     //In essence generate block is a special type of for loop with the loop index variable of datatype genvar.
24 |     generate
25 |         for (i=1; i<100; i=i+1) begin : Full_adder_block
26 |         one_bit_FA FA(a[i],b[i],cout[i-1],cout[i],sum[i]);
27 |     end
28 |     endgenerate
29 | endmodule


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/4 - Procedures/7 - Priority encorder with casez.v:
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 1 | module top_module (
 2 |     input [7:0] in,
 3 |     output reg [2:0] pos  );
 4 |     
 5 |     // casez treats bits that have the value z as don't-care in the comparison.
 6 |     
 7 |     //Notice how there are certain inputs (e.g., 4'b1111) that will match more than one case item. 
 8 |     //The first match is chosen (so 4'b1111 matches the first item, out = 0, but not any of the later ones).
 9 | 	
10 |     //There is also a similar casex that treats both x and z as don't-care. I don't see much purpose to using it over casez.
11 | 	//The digit ? is a synonym for z. so 2'bz0 is the same as 2'b?0
12 |     
13 |     always @(*) begin
14 |        	casez (in[7:0])
15 |             8'bzzzzzzz1: pos = 0;
16 |             8'bzzzzzz1z: pos = 1;
17 |             8'bzzzzz1zz: pos = 2;
18 |             8'bzzzz1zzz: pos = 3;
19 |             8'bzzz1zzzz: pos = 4;
20 |             8'bzz1zzzzz: pos = 5;
21 |             8'bz1zzzzzz: pos = 6;
22 |             8'b1zzzzzzz: pos = 7;
23 |             default: 	 pos = 0;
24 |     	endcase
25 | 	end
26 | endmodule
27 | 


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/6 - Combinational Logic/3 - Arithmatic Circuits/5 - 100-bit binray Adder.v:
--------------------------------------------------------------------------------
 1 | module top_module( 
 2 |     input [99:0] a, b,
 3 |     input cin,
 4 |     output cout,
 5 |     output [99:0] sum );
 6 | 
 7 |     genvar i;
 8 |     wire [98:0]con_vect;
 9 |     one_bit_FA FA1(a[0],b[0],cin,con_vect[0],sum[0]);
10 |     one_bit_FA FA2(a[99],b[99],con_vect[98],cout,sum[99]);
11 |     
12 |     //this is a generte block
13 |     //The loop generate construct provides an easy and concise method to create multiple instances 
14 |     //of module items such as module instances, assign statements, assertions, interface instances 
15 |     //In essence generate block is a special type of for loop with the loop index variable of datatype genvar.
16 |     generate
17 |         for (i=1; i<99; i=i+1) begin : Full_adder_block
18 |             one_bit_FA FA(a[i],b[i],con_vect[i-1],con_vect[i],sum[i]);
19 |     end
20 |     
21 |       
22 |     endgenerate
23 |     
24 | endmodule
25 | 
26 | module one_bit_FA(
27 |     input a,b,
28 |     input cin,
29 |     output cout,sum);
30 | 	
31 |     assign sum  = a^b^cin;
32 |     assign cout = (a&b)|(b&cin)|(cin&a);
33 | endmodule


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/4 - Procedures/1 - always_blocks_combinational.v:
--------------------------------------------------------------------------------
 1 | // synthesis verilog_input_version verilog_2001
 2 | module top_module(
 3 |     input a, 
 4 |     input b,
 5 |     output wire out_assign,
 6 |     output reg out_alwaysblock
 7 | );
 8 |     //For synthesizing hardware, two types of always blocks are relevant:
 9 |     //	Combinational: always @(*)
10 |     //	Clocked: always @(posedge clk)
11 |     //Combinational always blocks are equivalent to assign statements,
12 | 
13 |     // If you explicitly specify the sensitivity list and miss a signal, the synthesized hardware will still behave as though (*) was specified, 
14 |     //but the simulation will not and not match the hardware's behaviour.
15 |     //why is above??
16 | 	
17 |     //A note on wire vs. reg: The left-hand-side of an assign statement must be a net type (e.g., wire), 
18 |     //while the left-hand-side of a procedural assignment (in an always block) must be a variable type (e.g., reg). These types (wire vs. reg) have nothing to do with what hardware is synthesized,
19 |     
20 |     assign out_assign = a&&b;
21 |     
22 |     always @(*) begin
23 |     	out_alwaysblock = a&&b;
24 |     end
25 |     
26 | endmodule


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/6 - Combinational Logic/3 - Arithmatic Circuits/7 - Signed addition overflow.v:
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 1 | module top_module (
 2 |     input [7:0] a,
 3 |     input [7:0] b,
 4 |     output [7:0] s,
 5 |     output overflow
 6 | ); //
 7 |  	//2's complement for a binary number is found by inverting the numbers and adding 1
 8 |     //	i.e: 2'scomplement of 0011 is : 1100+0001 =  1101
 9 |     //
10 |     //Also remember that MSB of the 2's complement number represents  the sign. i.e if MSB is one then the number is -ve
11 |     //	i.e: 1101 = -8+4+0+1=-3
12 |     //
13 |     //If 2= 0010 then -2= 1101+1 = 1110
14 |     //Also 2+(-2) = 1111 (This property holds for all the numbers)
15 |     //
16 |     //While adding two 2's complement numbers, overflow can be detected two ways:
17 |     //	1. If carryout and crry-on to  MSB are different then overflow occured
18 |     //  2. If both numbers are +ve and result is-ve or vise versa, overflow occurs
19 |     
20 |     assign s = a+b;
21 |     assign overflow = a[7]&&b[7]&&(~s[7]) || (~a[7])&&(~b[7])&&(s[7]); 
22 | 
23 | endmodule
24 | 
25 | 
26 | 
27 | module top_m( 
28 |     input a, b, cin,
29 |     output cout, sum );
30 |     
31 | 	assign cout = a&b | b&cin | a&cin;
32 | 	assign sum  = a^b^cin;
33 | endmodule


--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
 1 | This is free and unencumbered software released into the public domain.
 2 | 
 3 | Anyone is free to copy, modify, publish, use, compile, sell, or
 4 | distribute this software, either in source code form or as a compiled
 5 | binary, for any purpose, commercial or non-commercial, and by any
 6 | means.
 7 | 
 8 | In jurisdictions that recognize copyright laws, the author or authors
 9 | of this software dedicate any and all copyright interest in the
10 | software to the public domain. We make this dedication for the benefit
11 | of the public at large and to the detriment of our heirs and
12 | successors. We intend this dedication to be an overt act of
13 | relinquishment in perpetuity of all present and future rights to this
14 | software under copyright law.
15 | 
16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 | IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 | OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 | ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 | OTHER DEALINGS IN THE SOFTWARE.
23 | 
24 | For more information, please refer to <http://unlicense.org>
25 | 


--------------------------------------------------------------------------------
/8 - Verification/1 - Finding Bugs in  the Code/5 - Case Statement fix.v:
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 1 | module top_module (
 2 |     input [7:0] code,
 3 |     output reg [3:0] out,
 4 |     output reg valid );//
 5 | 
 6 |     always @(*) begin
 7 |         case (code)
 8 |             8'h45:begin 
 9 |                 out   = 0;
10 |                 valid = 1;
11 |             end
12 |             8'h16: begin
13 |                 out = 1;
14 |                 valid = 1;
15 |             end
16 |             8'h1e: begin
17 |                 out = 2;
18 |                 valid = 1;
19 |             end
20 |             8'h26: begin
21 |                 out = 3;
22 |                 valid = 1;
23 |             end
24 |             8'h25: begin
25 |                 out = 4;
26 |               	valid = 1;
27 |             end
28 |             8'h2e: begin
29 |                 out = 5;
30 |                 valid = 1;
31 |             end
32 |             8'h36: begin
33 |                 out = 6;
34 |                 valid = 1;
35 |             end
36 |             8'h3d: begin
37 |                 out = 7;
38 |                 valid = 1;
39 |             end
40 |             8'h3e: begin
41 |                 out = 8;
42 |                 valid = 1; 
43 |             end
44 |             8'h46: begin 
45 |                 out = 9;
46 |                 valid = 1;
47 |             end
48 |             default: begin
49 |                 valid = 0;
50 |             	out   = 0;
51 |             end
52 |         endcase
53 |     end
54 | 
55 | endmodule


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