├── README.md └── aes_hw ├── aes_0 ├── README.md ├── SBOX.hex ├── addroundkey.v ├── aes.v ├── aes_slave_intf.v ├── keyexpand.v ├── mixcolumns.v ├── sbox.v ├── shiftrows.v └── subbytes.v ├── aes_1 ├── README.md ├── SBOX.hex ├── aes.v ├── aes_slave_intf.v ├── mixcolumns.v ├── sbox.v ├── shiftrows.v └── test1.v ├── aes_10 ├── README.md ├── SBOX.hex ├── addroundkey.v ├── aes.v ├── aes_slave_intf.v ├── keyexpand.v ├── mixcolumns.v ├── sbox.v ├── shiftrows.v ├── subbytes.v ├── synch_fifo.v └── test1.v ├── aes_11 ├── README.md ├── SBOX.hex ├── addroundkey.v ├── aes.v ├── aes_slave_intf.v ├── keyexpand.v ├── mixcolumns.v ├── sbox.v ├── shiftrows.v ├── subbytes.v ├── synch_fifo.v ├── synch_reg.v ├── test.v └── test1.v ├── aes_12 ├── README ├── T0.hex ├── aes.v ├── aes_slave_intf.v ├── shiftrows.v ├── synch_fifo.v ├── synch_reg.v ├── t0.v ├── test.v └── test1.v ├── aes_2 ├── README.md ├── aes.v ├── aes_slave_intf.v ├── mixcolumns.v ├── sample.c ├── sbox.v ├── shiftrows.v └── test2.v ├── aes_3 ├── README.md ├── aes.v ├── aes_slave_intf.v ├── mixcolumns.v ├── sbox.v ├── shiftrows.v └── test1.v ├── aes_4 ├── README.md ├── T0.hex ├── T1.hex ├── T2.hex ├── T3.hex ├── aes.v ├── aes_slave_intf.v ├── shiftrows.v ├── t0.v ├── t1.v ├── t2.v ├── t3.v └── test1.v ├── aes_5 ├── README.md ├── T0.hex ├── aes.v ├── aes_slave_intf.v ├── shiftrows.v ├── t0.v └── test1.v ├── aes_6 ├── README.md ├── T0.hex ├── aes.v ├── aes_slave_intf.v ├── shiftrows.v ├── t0.v └── test1.v ├── aes_7 ├── README.md ├── SBOX.hex ├── aes.v ├── aes_slave_intf.v ├── mixcolumns.v ├── sbox.v ├── shiftrows.v ├── synch_fifo.v ├── test.v └── test1.v ├── aes_8 ├── README.md ├── T0.hex ├── aes.v ├── aes_slave_intf.v ├── shiftrows.v ├── synch_fifo.v ├── t0.v ├── test.v └── test1.v ├── aes_9 ├── README.md ├── SBOX.hex ├── addroundkey.v ├── aes.v ├── aes_slave_intf.v ├── keyexpand.v ├── mixcolumns.v ├── sbox.v ├── shiftrows.v ├── subbytes.v ├── synch_fifo.v └── test1.v └── bin ├── README.md ├── aes.h ├── bmp_cs50.h ├── cpu.h ├── dma.h ├── hello_world.c ├── tv.bmp ├── tv.zip ├── vga_display.c └── vga_display.h /README.md: -------------------------------------------------------------------------------- 1 | # AES128 2 | Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board. 3 | -------------------------------------------------------------------------------- /aes_hw/aes_0/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_0/SBOX.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_0/addroundkey.v: -------------------------------------------------------------------------------- 1 | module addroundkey ( 2 | input [127:0] istate, 3 | input [127:0] key, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | assign ostate = istate ^ key; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /aes_hw/aes_0/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | 7 | input [127:0] i_text, 8 | input [127:0] key, 9 | input [3:0] round, 10 | 11 | output reg [127:0] o_text, 12 | output reg [127:0] Rkey, 13 | 14 | output done 15 | ); 16 | 17 | wire [127:0] okey; 18 | 19 | wire [127:0] subbytes_text; 20 | wire [127:0] roundkey_text; 21 | wire [127:0] shiftrows_text; 22 | wire [127:0] mixcolumns_text; 23 | 24 | 25 | //Sub bytes computation for Encryption 26 | subbytes U1 (.istate(i_text), .ostate(subbytes_text)); 27 | 28 | //Shift Rows for Encryption 29 | shiftrows U2 (.istate(subbytes_text), .ostate(shiftrows_text)); 30 | 31 | //Mix Columns for Encryption 32 | mixcolumns U3 (.istate(shiftrows_text), .bypass(round==4'h9), .ostate(mixcolumns_text)); 33 | 34 | //Key Expansion for Encryption 35 | keyexpand U4 (.ikey(key), .round(round), .okey(okey)); 36 | 37 | //Add Roundkey for Encryption 38 | addroundkey U5 (.istate(mixcolumns_text), .key(okey), .ostate(roundkey_text)); 39 | 40 | always @(posedge clock) begin 41 | if(!resetn) begin 42 | o_text <= 128'h0; 43 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 44 | end 45 | else if(enable & (round == 4'h9)) begin 46 | o_text <= roundkey_text; 47 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 48 | end 49 | else if(enable) begin 50 | o_text <= roundkey_text; 51 | Rkey <= okey; 52 | end 53 | end 54 | 55 | assign done = 1'b1; 56 | 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /aes_hw/aes_0/aes_slave_intf.v: -------------------------------------------------------------------------------- 1 | module aes_slave_intf ( 2 | input clock, 3 | input resetn, 4 | 5 | input chipselect, 6 | input [3:0] address, 7 | 8 | input read, 9 | output reg [31:0] readdata, 10 | 11 | input write, 12 | input [31:0] writedata, 13 | 14 | output waitrequest 15 | ); 16 | 17 | reg [127:0] plain_text; 18 | reg [127:0] cipher_text; 19 | 20 | 21 | wire plain_text_write; 22 | reg plain_text_complete; 23 | 24 | reg [1:0] icounter; 25 | 26 | reg [4:0] ecounter; 27 | reg [4:0] ecounter_next; 28 | 29 | reg enable; 30 | reg [127:0] i_text; 31 | wire [3:0] round; 32 | wire [127:0] o_text; 33 | wire [127:0] Rkey; 34 | 35 | wire done; 36 | 37 | wire cipher_text_read; 38 | reg [1:0] ocounter; 39 | reg cipher_available; 40 | wire cipher_status_read; 41 | 42 | 43 | 44 | assign plain_text_write = chipselect & write & (address == 4'h0); 45 | 46 | 47 | always @(posedge clock) begin 48 | if(!resetn) begin 49 | icounter <= 2'h0; 50 | end 51 | else if(plain_text_write) begin 52 | icounter <= icounter + 2'h1; 53 | end 54 | end 55 | 56 | 57 | always @(posedge clock) begin 58 | if(!resetn) begin 59 | plain_text <= 128'h0; 60 | plain_text_complete <= 1'b0; 61 | end 62 | else if((icounter == 2'h0) & plain_text_write) begin // & ~waitrequest 63 | plain_text <= {96'h0, writedata}; 64 | plain_text_complete <= 1'b0; 65 | end 66 | else if((icounter == 2'h1) & plain_text_write) begin // & ~waitrequest 67 | plain_text <= {plain_text[95:0], writedata}; 68 | end 69 | else if((icounter == 2'h2) & plain_text_write) begin // & ~waitrequest 70 | plain_text <= {plain_text[95:0], writedata}; 71 | end 72 | else if((icounter == 2'h3) & plain_text_write) begin // & ~waitrequest 73 | plain_text <= {plain_text[95:0], writedata}; 74 | plain_text_complete <= 1'b1; 75 | end 76 | else begin 77 | plain_text_complete <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | 83 | 84 | 85 | 86 | always @(posedge clock) begin 87 | if(!resetn) begin 88 | ecounter <= 5'h0; 89 | end 90 | else begin 91 | ecounter <= ecounter_next; 92 | end 93 | end 94 | 95 | //Multiple rounds - 10 for 128bit encryption. 96 | always @(ecounter or plain_text_complete or o_text or plain_text or Rkey or done) begin 97 | 98 | if( (ecounter == 5'h0) ) begin 99 | cipher_text = o_text; 100 | if(plain_text_complete) begin 101 | enable = 1'b1; 102 | i_text = plain_text ^ Rkey; 103 | ecounter_next = 5'h1; 104 | end 105 | else begin 106 | enable = 1'b0; 107 | i_text = 128'h0; 108 | ecounter_next = ecounter; 109 | end 110 | end 111 | else if( (ecounter == 5'h13) ) begin 112 | enable = 1'b0; 113 | if(done) begin 114 | ecounter_next = 5'h0; 115 | end 116 | end 117 | else if( (ecounter[0]) ) begin 118 | enable = 1'b0; 119 | if(done) begin 120 | ecounter_next = ecounter + 5'h1; 121 | end 122 | end 123 | else if( (!ecounter[0]) )begin 124 | enable = 1'b1; 125 | i_text = o_text; 126 | ecounter_next = ecounter + 5'h1; 127 | end 128 | 129 | end 130 | 131 | 132 | assign round = ecounter[4:1]; 133 | 134 | //Compute AES cipher for one round. 135 | aes aes0 ( 136 | .clock(clock), 137 | .resetn(resetn), 138 | 139 | .enable(enable), 140 | 141 | .i_text(i_text), 142 | .key(Rkey), 143 | .round(round), 144 | 145 | .o_text(o_text), 146 | .Rkey(Rkey), 147 | 148 | .done(done) 149 | ); 150 | 151 | 152 | 153 | always @(posedge clock) begin 154 | if(!resetn) begin 155 | cipher_available <= 1'b0; 156 | end 157 | else if((ecounter == 5'h13) & done) begin 158 | cipher_available <= 1'b1; 159 | end 160 | else if((ecounter == 5'h0) & plain_text_complete) begin 161 | cipher_available <= 1'b0; 162 | end 163 | end 164 | 165 | 166 | assign cipher_text_read = chipselect & read & (address == 4'h4); 167 | assign cipher_status_read = chipselect & read & (address == 4'h8); 168 | 169 | always @(posedge clock) begin 170 | if(!resetn) begin 171 | ocounter <= 2'h0; 172 | end 173 | else if(cipher_text_read & (~waitrequest)) begin 174 | ocounter <= ocounter + 2'h1; 175 | end 176 | end 177 | 178 | 179 | //Reading Out Cipher 180 | always @(ocounter or cipher_text_read or cipher_status_read or cipher_text or cipher_available) begin 181 | readdata = 32'h0; 182 | 183 | if(cipher_text_read) begin 184 | case(ocounter) 185 | 2'h0 : begin readdata = cipher_text[127:96]; end 186 | 2'h1 : begin readdata = cipher_text[95:64]; end 187 | 2'h2 : begin readdata = cipher_text[63:32]; end 188 | 2'h3 : begin readdata = cipher_text[31:0]; end 189 | endcase 190 | end 191 | 192 | else if(cipher_status_read) begin 193 | readdata = {31'h0, cipher_available}; 194 | end 195 | 196 | end 197 | 198 | assign waitrequest = cipher_text_read & (~cipher_available); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /aes_hw/aes_0/keyexpand.v: -------------------------------------------------------------------------------- 1 | module keyexpand ( 2 | 3 | input [127:0] ikey, 4 | input [3:0] round, 5 | 6 | output [127:0] okey 7 | ); 8 | 9 | reg [7:0] Rcon[0:9]; //Round Constant 10 | 11 | wire [7:0] o13; 12 | wire [7:0] o14; 13 | wire [7:0] o15; 14 | wire [7:0] o12; 15 | 16 | 17 | genvar i; 18 | 19 | 20 | initial begin 21 | Rcon[0] = 8'h01; 22 | Rcon[1] = 8'h02; 23 | Rcon[2] = 8'h04; 24 | Rcon[3] = 8'h08; 25 | Rcon[4] = 8'h10; 26 | Rcon[5] = 8'h20; 27 | Rcon[6] = 8'h40; 28 | Rcon[7] = 8'h80; 29 | Rcon[8] = 8'h1b; 30 | Rcon[9] = 8'h36; 31 | end 32 | 33 | 34 | assign okey[8*0+7 : 8*0] = o13 ^ ikey[8*0+7 : 8*0] ^ Rcon[round]; 35 | assign okey[8*1+7 : 8*1] = o14 ^ ikey[8*1+7 : 8*1]; 36 | assign okey[8*2+7 : 8*2] = o15 ^ ikey[8*2+7 : 8*2]; 37 | assign okey[8*3+7 : 8*3] = o12 ^ ikey[8*3+7 : 8*3]; 38 | 39 | 40 | sbox sbox0(.index(ikey[8*13+7 : 8*13]), 41 | 42 | .o(o13) 43 | ); 44 | 45 | sbox sbox1(.index(ikey[8*14+7 : 8*14]), 46 | 47 | .o(o14) 48 | ); 49 | 50 | sbox sbox2(.index(ikey[8*15+7 : 8*15]), 51 | 52 | .o(o15) 53 | ); 54 | 55 | sbox sbox3(.index(ikey[8*12+7 : 8*12]), 56 | 57 | .o(o12) 58 | ); 59 | 60 | 61 | //Key Expansion for Encryption 62 | generate 63 | for(i = 4; i < 16; i = i+1) begin : key_expand 64 | assign okey[8*i+7 : 8*i] = ikey[8*i+7 : 8*i] ^ okey[8*(i-4)+7 : 8*(i-4)]; 65 | end 66 | endgenerate 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /aes_hw/aes_0/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input [127:0] istate, 3 | input bypass, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | wire [127:0] buf1; 9 | wire [127:0] buf3; 10 | wire [127:0] buf4; 11 | 12 | genvar i; 13 | 14 | generate 15 | for(i = 0; i < 16; i= i+4) begin : mix_columns0 16 | 17 | assign buf1[ 8*i+31 : 8*i ] = { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] } ^ { istate[ 8*i+15 : 8*i ], istate[ 8*i+31 : 8*i+16 ] } ^ { istate[ 8*i+23 : 8*i ], istate[ 8*i+31 : 8*i+24 ] }; 18 | 19 | assign buf3[ 8*i+31 : 8*i] = istate[ 8*i+31 : 8*i ] ^ { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] }; 20 | 21 | //Galois Multiplication 22 | assign buf4[ 8*(i)+7 : 8*(i) ] = buf3[ 8*(i)+7 ] ? ( { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 }; 23 | assign buf4[ 8*(i+1)+7 : 8*(i+1) ] = buf3[ 8*(i+1)+7 ] ? ( { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 }; 24 | assign buf4[ 8*(i+2)+7 : 8*(i+2) ] = buf3[ 8*(i+2)+7 ] ? ( { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 }; 25 | assign buf4[ 8*(i+3)+7 : 8*(i+3) ] = buf3[ 8*(i+3)+7 ] ? ( { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 }; 26 | 27 | //bypass option for last round of encryption 28 | assign ostate[ 8*i+31 : 8*i ] = bypass ? istate[ 8*i+31 : 8*i ] : buf1[ 8*i+31 : 8*i ] ^ buf4[ 8*i+31 : 8*i ]; 29 | 30 | end 31 | endgenerate 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /aes_hw/aes_0/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input [7:0] index, 3 | 4 | output [7:0] o 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("SBOX.hex", mem); 11 | end 12 | 13 | assign o = mem[ index ]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_0/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_0/subbytes.v: -------------------------------------------------------------------------------- 1 | module subbytes ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | //Sub bytes computation for Encryption 10 | generate 11 | for(i = 0; i < 16; i = i+1) begin : sub_bytes 12 | 13 | sbox inst(.index(istate[8*i+7 : 8*i]), 14 | 15 | .o(ostate[8*i+7 : 8*i]) 16 | ); 17 | end 18 | endgenerate 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /aes_hw/aes_1/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_1/SBOX.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_1/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | input [127:0] i_text, 7 | input [127:0] key, 8 | input [3:0] round, 9 | 10 | output reg [127:0] o_text, 11 | output reg [127:0] Rkey, 12 | output done 13 | ); 14 | 15 | reg [7:0] index; 16 | wire [7:0] byteout; 17 | 18 | reg [4:0] bytecounter; 19 | reg [4:0] bytecounter_next; 20 | reg [127:0] tstate; 21 | 22 | reg [127:0] subbytes_text; 23 | wire [127:0] roundkey_text; 24 | wire [127:0] shiftrows_text; 25 | wire [127:0] mixcolumns_text; 26 | 27 | wire [127:0] okey; 28 | reg [31:0] tkey; 29 | 30 | reg [7:0] Rcon[0:9]; //Round Constant 31 | 32 | initial begin 33 | Rcon[0] = 8'h01; 34 | Rcon[1] = 8'h02; 35 | Rcon[2] = 8'h04; 36 | Rcon[3] = 8'h08; 37 | Rcon[4] = 8'h10; 38 | Rcon[5] = 8'h20; 39 | Rcon[6] = 8'h40; 40 | Rcon[7] = 8'h80; 41 | Rcon[8] = 8'h1b; 42 | Rcon[9] = 8'h36; 43 | end 44 | 45 | always @(posedge clock) begin 46 | if(!resetn) begin 47 | bytecounter <= 5'h0; 48 | end 49 | else begin 50 | bytecounter <= bytecounter_next; 51 | end 52 | end 53 | 54 | 55 | always @(bytecounter or enable or i_text or byteout or key or round) begin 56 | 57 | if((bytecounter == 5'h0)) begin 58 | if(enable) begin 59 | index = i_text[127:120]; 60 | tstate[127:120] = byteout; 61 | end 62 | else begin 63 | tstate = 128'h0; 64 | tkey = 32'h0; 65 | end 66 | end 67 | else if((bytecounter == 5'h1)) begin 68 | index = i_text[119:112]; 69 | tstate[119:112] = byteout; 70 | end 71 | else if((bytecounter == 5'h2)) begin 72 | index = i_text[111:104]; 73 | tstate[111:104] = byteout; 74 | end 75 | else if((bytecounter == 5'h3)) begin 76 | index = i_text[103:96]; 77 | tstate[103:96] = byteout; 78 | end 79 | else if((bytecounter == 5'h4)) begin 80 | index = i_text[95:88]; 81 | tstate[95:88] = byteout; 82 | end 83 | else if((bytecounter == 5'h5)) begin 84 | index = i_text[87:80]; 85 | tstate[87:80] = byteout; 86 | end 87 | else if((bytecounter == 5'h6)) begin 88 | index = i_text[79:72]; 89 | tstate[79:72] = byteout; 90 | end 91 | else if((bytecounter == 5'h7)) begin 92 | index = i_text[71:64]; 93 | tstate[71:64] = byteout; 94 | end 95 | else if((bytecounter == 5'h8)) begin 96 | index = i_text[63:56]; 97 | tstate[63:56] = byteout; 98 | end 99 | else if((bytecounter == 5'h9)) begin 100 | index = i_text[55:48]; 101 | tstate[55:48] = byteout; 102 | end 103 | else if((bytecounter == 5'hA)) begin 104 | index = i_text[47:40]; 105 | tstate[47:40] = byteout; 106 | end 107 | else if((bytecounter == 5'hB)) begin 108 | index = i_text[39:32]; 109 | tstate[39:32] = byteout; 110 | end 111 | else if((bytecounter == 5'hC)) begin 112 | index = i_text[31:24]; 113 | tstate[31:24] = byteout; 114 | end 115 | else if((bytecounter == 5'hD)) begin 116 | index = i_text[23:16]; 117 | tstate[23:16] = byteout; 118 | end 119 | else if((bytecounter == 5'hE)) begin 120 | index = i_text[15:8]; 121 | tstate[15:8] = byteout; 122 | end 123 | else if((bytecounter == 5'hF)) begin 124 | index = i_text[7:0]; 125 | tstate[7:0] = byteout; 126 | end 127 | else if((bytecounter == 5'h10)) begin 128 | index = key[111 : 104]; //8*13+7 : 8*13 129 | tkey[7 : 0] = byteout ^ key[7 : 0] ^ Rcon[round]; 130 | end 131 | else if((bytecounter == 5'h11)) begin 132 | index = key[119 : 112]; //8*14+7 : 8*14 133 | tkey[15 : 8] = byteout ^ key[15 : 8]; 134 | end 135 | else if((bytecounter == 5'h12)) begin 136 | index = key[127 : 120]; //8*15+7 : 8*15 137 | tkey[23 : 16] = byteout ^ key[23 : 16]; 138 | end 139 | else if((bytecounter == 5'h13)) begin 140 | index = key[103 : 96]; //8*12+7 : 8*12 141 | tkey[31 : 24] = byteout ^ key[31 : 24]; 142 | end 143 | 144 | 145 | if((bytecounter == 5'h13)) begin 146 | bytecounter_next = 5'h0; 147 | end 148 | else if( ((bytecounter == 5'h0) & enable) || (|(bytecounter)) ) begin 149 | bytecounter_next = bytecounter + 5'h1; 150 | end 151 | else begin 152 | bytecounter_next = bytecounter; 153 | end 154 | 155 | end 156 | 157 | //SBOX lookup 158 | sbox inst(.index(index), 159 | 160 | .o(byteout) 161 | ); 162 | 163 | 164 | always @(posedge clock) begin 165 | if(!resetn) begin 166 | subbytes_text <= 128'h0; 167 | end 168 | else if(bytecounter == 5'hF) begin 169 | subbytes_text <= tstate; 170 | end 171 | end 172 | 173 | 174 | //Shift Rows for Encryption 175 | shiftrows U2 (.istate(subbytes_text), .ostate(shiftrows_text)); 176 | 177 | //Mix Columns for Encryption 178 | mixcolumns U3 (.istate(shiftrows_text), .bypass(round==4'h9), .ostate(mixcolumns_text)); 179 | 180 | //Key Expansion for Encryption 181 | assign okey[31:0] = tkey[31:0]; 182 | assign okey[127:32] = key[127:32] ^ okey[95:0]; 183 | 184 | //Add Roundkey for Encryption 185 | assign roundkey_text = mixcolumns_text ^ okey; 186 | 187 | 188 | assign done = (bytecounter == 5'h13) ? 1'b1 : 1'b0; 189 | 190 | always @(posedge clock) begin 191 | if(!resetn) begin 192 | o_text <= 128'h0; 193 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 194 | end 195 | else if(done & (round == 4'h9)) begin 196 | o_text <= roundkey_text; 197 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 198 | end 199 | else if(done) begin 200 | o_text <= roundkey_text; 201 | Rkey <= okey; 202 | end 203 | end 204 | 205 | 206 | endmodule 207 | -------------------------------------------------------------------------------- /aes_hw/aes_1/aes_slave_intf.v: -------------------------------------------------------------------------------- 1 | module aes_slave_intf ( 2 | input clock, 3 | input resetn, 4 | 5 | input chipselect, 6 | input [3:0] address, 7 | 8 | input read, 9 | output reg [31:0] readdata, 10 | 11 | input write, 12 | input [31:0] writedata, 13 | 14 | output waitrequest 15 | ); 16 | 17 | reg [127:0] plain_text; 18 | reg [127:0] cipher_text; 19 | 20 | 21 | wire plain_text_write; 22 | reg plain_text_complete; 23 | 24 | reg [1:0] icounter; 25 | 26 | reg [4:0] ecounter; 27 | reg [4:0] ecounter_next; 28 | 29 | reg enable; 30 | reg [127:0] i_text; 31 | wire [3:0] round; 32 | wire [127:0] o_text; 33 | wire [127:0] Rkey; 34 | 35 | wire done; 36 | 37 | wire cipher_text_read; 38 | reg [1:0] ocounter; 39 | reg cipher_available; 40 | wire cipher_status_read; 41 | 42 | 43 | 44 | assign plain_text_write = chipselect & write & (address == 4'h0); 45 | 46 | 47 | always @(posedge clock) begin 48 | if(!resetn) begin 49 | icounter <= 2'h0; 50 | end 51 | else if(plain_text_write) begin 52 | icounter <= icounter + 2'h1; 53 | end 54 | end 55 | 56 | 57 | always @(posedge clock) begin 58 | if(!resetn) begin 59 | plain_text <= 128'h0; 60 | plain_text_complete <= 1'b0; 61 | end 62 | else if((icounter == 2'h0) & plain_text_write) begin // & ~waitrequest 63 | plain_text <= {96'h0, writedata}; 64 | plain_text_complete <= 1'b0; 65 | end 66 | else if((icounter == 2'h1) & plain_text_write) begin // & ~waitrequest 67 | plain_text <= {plain_text[95:0], writedata}; 68 | end 69 | else if((icounter == 2'h2) & plain_text_write) begin // & ~waitrequest 70 | plain_text <= {plain_text[95:0], writedata}; 71 | end 72 | else if((icounter == 2'h3) & plain_text_write) begin // & ~waitrequest 73 | plain_text <= {plain_text[95:0], writedata}; 74 | plain_text_complete <= 1'b1; 75 | end 76 | else begin 77 | plain_text_complete <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | 83 | 84 | 85 | 86 | always @(posedge clock) begin 87 | if(!resetn) begin 88 | ecounter <= 5'h0; 89 | end 90 | else begin 91 | ecounter <= ecounter_next; 92 | end 93 | end 94 | 95 | //Multiple rounds - 10 for 128bit encryption. 96 | always @(ecounter or plain_text_complete or o_text or plain_text or Rkey or done) begin 97 | 98 | if( (ecounter == 5'h0) ) begin 99 | cipher_text = o_text; 100 | if(plain_text_complete) begin 101 | enable = 1'b1; 102 | i_text = plain_text ^ Rkey; 103 | ecounter_next = 5'h1; 104 | end 105 | else begin 106 | enable = 1'b0; 107 | i_text = 128'h0; 108 | ecounter_next = ecounter; 109 | end 110 | end 111 | else if( (ecounter == 5'h13) ) begin 112 | enable = 1'b0; 113 | if(done) begin 114 | ecounter_next = 5'h0; 115 | end 116 | end 117 | else if( (ecounter[0]) ) begin 118 | enable = 1'b0; 119 | if(done) begin 120 | ecounter_next = ecounter + 5'h1; 121 | end 122 | end 123 | else if( (!ecounter[0]) )begin 124 | enable = 1'b1; 125 | i_text = o_text; 126 | ecounter_next = ecounter + 5'h1; 127 | end 128 | 129 | end 130 | 131 | 132 | assign round = ecounter[4:1]; 133 | 134 | //Compute AES cipher for one round. 135 | aes aes0 ( 136 | .clock(clock), 137 | .resetn(resetn), 138 | 139 | .enable(enable), 140 | 141 | .i_text(i_text), 142 | .key(Rkey), 143 | .round(round), 144 | 145 | .o_text(o_text), 146 | .Rkey(Rkey), 147 | 148 | .done(done) 149 | ); 150 | 151 | 152 | 153 | always @(posedge clock) begin 154 | if(!resetn) begin 155 | cipher_available <= 1'b0; 156 | end 157 | else if((ecounter == 5'h13) & done) begin 158 | cipher_available <= 1'b1; 159 | end 160 | else if((ecounter == 5'h0) & plain_text_complete) begin 161 | cipher_available <= 1'b0; 162 | end 163 | end 164 | 165 | 166 | assign cipher_text_read = chipselect & read & (address == 4'h4); 167 | assign cipher_status_read = chipselect & read & (address == 4'h8); 168 | 169 | always @(posedge clock) begin 170 | if(!resetn) begin 171 | ocounter <= 2'h0; 172 | end 173 | else if(cipher_text_read & (~waitrequest)) begin 174 | ocounter <= ocounter + 2'h1; 175 | end 176 | end 177 | 178 | 179 | //Reading Out Cipher 180 | always @(ocounter or cipher_text_read or cipher_status_read or cipher_text or cipher_available) begin 181 | readdata = 32'h0; 182 | 183 | if(cipher_text_read) begin 184 | case(ocounter) 185 | 2'h0 : begin readdata = cipher_text[127:96]; end 186 | 2'h1 : begin readdata = cipher_text[95:64]; end 187 | 2'h2 : begin readdata = cipher_text[63:32]; end 188 | 2'h3 : begin readdata = cipher_text[31:0]; end 189 | endcase 190 | end 191 | 192 | else if(cipher_status_read) begin 193 | readdata = {31'h0, cipher_available}; 194 | end 195 | 196 | end 197 | 198 | assign waitrequest = cipher_text_read & (~cipher_available); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /aes_hw/aes_1/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input [127:0] istate, 3 | input bypass, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | wire [127:0] buf1; 9 | wire [127:0] buf3; 10 | wire [127:0] buf4; 11 | 12 | genvar i; 13 | 14 | generate 15 | for(i = 0; i < 16; i= i+4) begin : mix_columns0 16 | 17 | assign buf1[ 8*i+31 : 8*i ] = { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] } ^ { istate[ 8*i+15 : 8*i ], istate[ 8*i+31 : 8*i+16 ] } ^ { istate[ 8*i+23 : 8*i ], istate[ 8*i+31 : 8*i+24 ] }; 18 | 19 | assign buf3[ 8*i+31 : 8*i] = istate[ 8*i+31 : 8*i ] ^ { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] }; 20 | 21 | //Galois Multiplication 22 | assign buf4[ 8*(i)+7 : 8*(i) ] = buf3[ 8*(i)+7 ] ? ( { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 }; 23 | assign buf4[ 8*(i+1)+7 : 8*(i+1) ] = buf3[ 8*(i+1)+7 ] ? ( { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 }; 24 | assign buf4[ 8*(i+2)+7 : 8*(i+2) ] = buf3[ 8*(i+2)+7 ] ? ( { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 }; 25 | assign buf4[ 8*(i+3)+7 : 8*(i+3) ] = buf3[ 8*(i+3)+7 ] ? ( { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 }; 26 | 27 | //bypass option for last round of encryption 28 | assign ostate[ 8*i+31 : 8*i ] = bypass ? istate[ 8*i+31 : 8*i ] : buf1[ 8*i+31 : 8*i ] ^ buf4[ 8*i+31 : 8*i ]; 29 | 30 | end 31 | endgenerate 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /aes_hw/aes_1/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input [7:0] index, 3 | 4 | output [7:0] o 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("SBOX.hex", mem); 11 | end 12 | 13 | assign o = mem[ index ]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_1/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_1/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #160; 38 | //enable = 1'b0; 39 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 40 | //enable = 1'b1; 41 | #9000; 42 | $finish; 43 | end 44 | 45 | 46 | always @(posedge clk) begin 47 | if(!resetn) begin 48 | ecounter <= 4'h0; 49 | end 50 | else begin 51 | ecounter <= ecounter_next; 52 | end 53 | end 54 | 55 | //Multiple rounds - 10 for 128bit encryption. 56 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 57 | ecounter_next = ecounter; //Keep the same state. 58 | enable = 1'b0; 59 | round = 4'h0; 60 | i_text = 128'h0; 61 | 62 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 63 | if(plain_text_complete) begin 64 | if(done) begin 65 | ecounter_next = 4'h1; 66 | end 67 | enable = 1'b1; 68 | round = 4'h0; 69 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 70 | end 71 | end 72 | else begin 73 | if(done) begin 74 | ecounter_next = ecounter + 4'h1; 75 | end 76 | enable = 1'b1; 77 | round = ecounter; 78 | i_text = o_text; 79 | end 80 | end 81 | 82 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /aes_hw/aes_10/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_10/SBOX.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_10/addroundkey.v: -------------------------------------------------------------------------------- 1 | module addroundkey ( 2 | input [127:0] istate, 3 | input [127:0] key, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | assign ostate = istate ^ key; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /aes_hw/aes_10/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | 7 | input [127:0] i_text, 8 | input [127:0] key, 9 | input [3:0] round, 10 | 11 | output reg [127:0] o_text, 12 | output reg [127:0] Rkey, 13 | 14 | output done 15 | ); 16 | 17 | wire [127:0] okey; 18 | 19 | wire [127:0] subbytes_text; 20 | wire [127:0] roundkey_text; 21 | wire [127:0] shiftrows_text; 22 | wire [127:0] mixcolumns_text; 23 | 24 | 25 | //Sub bytes computation for Encryption 26 | subbytes U1 (.istate(i_text), .ostate(subbytes_text)); 27 | 28 | //Shift Rows for Encryption 29 | shiftrows U2 (.istate(subbytes_text), .ostate(shiftrows_text)); 30 | 31 | //Mix Columns for Encryption 32 | mixcolumns U3 (.istate(shiftrows_text), .bypass(round==4'h9), .ostate(mixcolumns_text)); 33 | 34 | //Key Expansion for Encryption 35 | keyexpand U4 (.ikey(key), .round(round), .okey(okey)); 36 | 37 | //Add Roundkey for Encryption 38 | addroundkey U5 (.istate(mixcolumns_text), .key(okey), .ostate(roundkey_text)); 39 | 40 | always @(posedge clock) begin 41 | if(!resetn) begin 42 | o_text <= 128'h0; 43 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 44 | end 45 | else if(enable & (round == 4'h9)) begin 46 | o_text <= roundkey_text; 47 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 48 | end 49 | else if(enable) begin 50 | o_text <= roundkey_text; 51 | Rkey <= okey; 52 | end 53 | end 54 | 55 | assign done = 1'b1; 56 | 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /aes_hw/aes_10/keyexpand.v: -------------------------------------------------------------------------------- 1 | module keyexpand ( 2 | 3 | input [127:0] ikey, 4 | input [3:0] round, 5 | 6 | output [127:0] okey 7 | ); 8 | 9 | reg [7:0] Rcon[0:9]; //Round Constant 10 | 11 | wire [7:0] o13; 12 | wire [7:0] o14; 13 | wire [7:0] o15; 14 | wire [7:0] o12; 15 | 16 | 17 | genvar i; 18 | 19 | 20 | initial begin 21 | Rcon[0] = 8'h01; 22 | Rcon[1] = 8'h02; 23 | Rcon[2] = 8'h04; 24 | Rcon[3] = 8'h08; 25 | Rcon[4] = 8'h10; 26 | Rcon[5] = 8'h20; 27 | Rcon[6] = 8'h40; 28 | Rcon[7] = 8'h80; 29 | Rcon[8] = 8'h1b; 30 | Rcon[9] = 8'h36; 31 | end 32 | 33 | 34 | assign okey[8*0+7 : 8*0] = o13 ^ ikey[8*0+7 : 8*0] ^ Rcon[round]; 35 | assign okey[8*1+7 : 8*1] = o14 ^ ikey[8*1+7 : 8*1]; 36 | assign okey[8*2+7 : 8*2] = o15 ^ ikey[8*2+7 : 8*2]; 37 | assign okey[8*3+7 : 8*3] = o12 ^ ikey[8*3+7 : 8*3]; 38 | 39 | 40 | sbox sbox0(.index(ikey[8*13+7 : 8*13]), 41 | 42 | .o(o13) 43 | ); 44 | 45 | sbox sbox1(.index(ikey[8*14+7 : 8*14]), 46 | 47 | .o(o14) 48 | ); 49 | 50 | sbox sbox2(.index(ikey[8*15+7 : 8*15]), 51 | 52 | .o(o15) 53 | ); 54 | 55 | sbox sbox3(.index(ikey[8*12+7 : 8*12]), 56 | 57 | .o(o12) 58 | ); 59 | 60 | 61 | //Key Expansion for Encryption 62 | generate 63 | for(i = 4; i < 16; i = i+1) begin : key_expand 64 | assign okey[8*i+7 : 8*i] = ikey[8*i+7 : 8*i] ^ okey[8*(i-4)+7 : 8*(i-4)]; 65 | end 66 | endgenerate 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /aes_hw/aes_10/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input [127:0] istate, 3 | input bypass, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | wire [127:0] buf1; 9 | wire [127:0] buf3; 10 | wire [127:0] buf4; 11 | 12 | genvar i; 13 | 14 | generate 15 | for(i = 0; i < 16; i= i+4) begin : mix_columns0 16 | 17 | assign buf1[ 8*i+31 : 8*i ] = { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] } ^ { istate[ 8*i+15 : 8*i ], istate[ 8*i+31 : 8*i+16 ] } ^ { istate[ 8*i+23 : 8*i ], istate[ 8*i+31 : 8*i+24 ] }; 18 | 19 | assign buf3[ 8*i+31 : 8*i] = istate[ 8*i+31 : 8*i ] ^ { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] }; 20 | 21 | //Galois Multiplication 22 | assign buf4[ 8*(i)+7 : 8*(i) ] = buf3[ 8*(i)+7 ] ? ( { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 }; 23 | assign buf4[ 8*(i+1)+7 : 8*(i+1) ] = buf3[ 8*(i+1)+7 ] ? ( { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 }; 24 | assign buf4[ 8*(i+2)+7 : 8*(i+2) ] = buf3[ 8*(i+2)+7 ] ? ( { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 }; 25 | assign buf4[ 8*(i+3)+7 : 8*(i+3) ] = buf3[ 8*(i+3)+7 ] ? ( { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 }; 26 | 27 | //bypass option for last round of encryption 28 | assign ostate[ 8*i+31 : 8*i ] = bypass ? istate[ 8*i+31 : 8*i ] : buf1[ 8*i+31 : 8*i ] ^ buf4[ 8*i+31 : 8*i ]; 29 | 30 | end 31 | endgenerate 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /aes_hw/aes_10/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input [7:0] index, 3 | 4 | output [7:0] o 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("SBOX.hex", mem); 11 | end 12 | 13 | assign o = mem[ index ]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_10/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_10/subbytes.v: -------------------------------------------------------------------------------- 1 | module subbytes ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | //Sub bytes computation for Encryption 10 | generate 11 | for(i = 0; i < 16; i = i+1) begin : sub_bytes 12 | 13 | sbox inst(.index(istate[8*i+7 : 8*i]), 14 | 15 | .o(ostate[8*i+7 : 8*i]) 16 | ); 17 | end 18 | endgenerate 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /aes_hw/aes_10/synch_fifo.v: -------------------------------------------------------------------------------- 1 | module synch_fifo #(parameter wbits = 128, abits = 2) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output full, 11 | output empty 12 | ); 13 | 14 | reg [abits:0] wptr; 15 | reg [abits:0] rptr; 16 | 17 | reg [wbits-1:0] fifofile [0 : 2**abits-1]; 18 | 19 | reg [wbits-1:0] fout; 20 | 21 | assign full = (wptr[abits-1:0] == rptr[abits-1:0]) & (wptr[abits] != rptr[abits]); 22 | assign empty = (wptr == rptr); 23 | 24 | always @(posedge clock) begin 25 | if(!resetn) begin 26 | wptr <= 'h0; 27 | rptr <= 'h0; 28 | end 29 | else begin 30 | if(wen & ~full) begin 31 | fifofile[wptr[abits-1:0]] <= wdata; 32 | wptr <= wptr + 'h1; 33 | end 34 | if(ren & ~empty) begin 35 | rptr <= rptr + 'h1; 36 | end 37 | end 38 | end 39 | 40 | assign rdata = fifofile[rptr[abits-1:0]]; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /aes_hw/aes_10/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #90; 38 | plain_text_complete = 1'b0; 39 | //enable = 1'b0; 40 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 41 | //enable = 1'b1; 42 | #100; 43 | $finish; 44 | end 45 | 46 | 47 | always @(posedge clk) begin 48 | if(!resetn) begin 49 | ecounter <= 4'h0; 50 | end 51 | else begin 52 | ecounter <= ecounter_next; 53 | end 54 | end 55 | 56 | //Multiple rounds - 10 for 128bit encryption. 57 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 58 | ecounter_next = ecounter; //Keep the same state. 59 | enable = 1'b0; 60 | round = 4'h0; 61 | i_text = 128'h0; 62 | 63 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 64 | if(plain_text_complete) begin 65 | if(done) begin 66 | ecounter_next = 4'h1; 67 | end 68 | enable = 1'b1; 69 | round = 4'h0; 70 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 71 | end 72 | end 73 | else begin 74 | if(done) begin 75 | ecounter_next = ecounter + 4'h1; 76 | end 77 | enable = 1'b1; 78 | round = ecounter; 79 | i_text = o_text; 80 | end 81 | end 82 | 83 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 84 | 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /aes_hw/aes_11/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_11/SBOX.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_11/addroundkey.v: -------------------------------------------------------------------------------- 1 | module addroundkey ( 2 | input [127:0] istate, 3 | input [127:0] key, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | assign ostate = istate ^ key; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /aes_hw/aes_11/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | 7 | input [127:0] i_text, 8 | input [127:0] key, 9 | input [3:0] round, 10 | 11 | output reg [127:0] o_text, 12 | output reg [127:0] Rkey, 13 | 14 | output reg done 15 | ); 16 | 17 | wire [127:0] okey; 18 | 19 | wire [127:0] subbytes_text; 20 | wire [127:0] roundkey_text; 21 | wire [127:0] shiftrows_text; 22 | wire [127:0] mixcolumns_text; 23 | 24 | 25 | //Sub bytes computation for Encryption 26 | subbytes U1 (.istate(i_text), .ostate(subbytes_text)); 27 | 28 | //Shift Rows for Encryption 29 | shiftrows U2 (.istate(subbytes_text), .ostate(shiftrows_text)); 30 | 31 | //Mix Columns for Encryption 32 | mixcolumns U3 (.istate(shiftrows_text), .bypass(round==4'h9), .ostate(mixcolumns_text)); 33 | 34 | //Key Expansion for Encryption 35 | keyexpand U4 (.ikey(key), .round(round), .okey(okey)); 36 | 37 | //Add Roundkey for Encryption 38 | addroundkey U5 (.istate(mixcolumns_text), .key(okey), .ostate(roundkey_text)); 39 | 40 | always @(posedge clock) begin 41 | if(!resetn) begin 42 | o_text <= 128'h0; 43 | end 44 | else if(enable) begin 45 | o_text <= roundkey_text; 46 | end 47 | end 48 | 49 | always @(posedge clock) begin 50 | if(!resetn) begin 51 | Rkey <= 128'h0; 52 | done <= 1'b0; 53 | end 54 | else if(enable) begin 55 | Rkey <= okey; 56 | done <= 1'b1; 57 | end 58 | else begin 59 | //Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 60 | done <= 1'b0; 61 | end 62 | end 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /aes_hw/aes_11/keyexpand.v: -------------------------------------------------------------------------------- 1 | module keyexpand ( 2 | 3 | input [127:0] ikey, 4 | input [3:0] round, 5 | 6 | output [127:0] okey 7 | ); 8 | 9 | reg [7:0] Rcon[0:9]; //Round Constant 10 | 11 | wire [7:0] o13; 12 | wire [7:0] o14; 13 | wire [7:0] o15; 14 | wire [7:0] o12; 15 | 16 | 17 | genvar i; 18 | 19 | 20 | initial begin 21 | Rcon[0] = 8'h01; 22 | Rcon[1] = 8'h02; 23 | Rcon[2] = 8'h04; 24 | Rcon[3] = 8'h08; 25 | Rcon[4] = 8'h10; 26 | Rcon[5] = 8'h20; 27 | Rcon[6] = 8'h40; 28 | Rcon[7] = 8'h80; 29 | Rcon[8] = 8'h1b; 30 | Rcon[9] = 8'h36; 31 | end 32 | 33 | 34 | assign okey[8*0+7 : 8*0] = o13 ^ ikey[8*0+7 : 8*0] ^ Rcon[round]; 35 | assign okey[8*1+7 : 8*1] = o14 ^ ikey[8*1+7 : 8*1]; 36 | assign okey[8*2+7 : 8*2] = o15 ^ ikey[8*2+7 : 8*2]; 37 | assign okey[8*3+7 : 8*3] = o12 ^ ikey[8*3+7 : 8*3]; 38 | 39 | 40 | sbox sbox0(.index(ikey[8*13+7 : 8*13]), 41 | 42 | .o(o13) 43 | ); 44 | 45 | sbox sbox1(.index(ikey[8*14+7 : 8*14]), 46 | 47 | .o(o14) 48 | ); 49 | 50 | sbox sbox2(.index(ikey[8*15+7 : 8*15]), 51 | 52 | .o(o15) 53 | ); 54 | 55 | sbox sbox3(.index(ikey[8*12+7 : 8*12]), 56 | 57 | .o(o12) 58 | ); 59 | 60 | 61 | //Key Expansion for Encryption 62 | generate 63 | for(i = 4; i < 16; i = i+1) begin : key_expand 64 | assign okey[8*i+7 : 8*i] = ikey[8*i+7 : 8*i] ^ okey[8*(i-4)+7 : 8*(i-4)]; 65 | end 66 | endgenerate 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /aes_hw/aes_11/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input [127:0] istate, 3 | input bypass, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | wire [127:0] buf1; 9 | wire [127:0] buf3; 10 | wire [127:0] buf4; 11 | 12 | genvar i; 13 | 14 | generate 15 | for(i = 0; i < 16; i= i+4) begin : mix_columns0 16 | 17 | assign buf1[ 8*i+31 : 8*i ] = { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] } ^ { istate[ 8*i+15 : 8*i ], istate[ 8*i+31 : 8*i+16 ] } ^ { istate[ 8*i+23 : 8*i ], istate[ 8*i+31 : 8*i+24 ] }; 18 | 19 | assign buf3[ 8*i+31 : 8*i] = istate[ 8*i+31 : 8*i ] ^ { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] }; 20 | 21 | //Galois Multiplication 22 | assign buf4[ 8*(i)+7 : 8*(i) ] = buf3[ 8*(i)+7 ] ? ( { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 }; 23 | assign buf4[ 8*(i+1)+7 : 8*(i+1) ] = buf3[ 8*(i+1)+7 ] ? ( { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 }; 24 | assign buf4[ 8*(i+2)+7 : 8*(i+2) ] = buf3[ 8*(i+2)+7 ] ? ( { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 }; 25 | assign buf4[ 8*(i+3)+7 : 8*(i+3) ] = buf3[ 8*(i+3)+7 ] ? ( { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 }; 26 | 27 | //bypass option for last round of encryption 28 | assign ostate[ 8*i+31 : 8*i ] = bypass ? istate[ 8*i+31 : 8*i ] : buf1[ 8*i+31 : 8*i ] ^ buf4[ 8*i+31 : 8*i ]; 29 | 30 | end 31 | endgenerate 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /aes_hw/aes_11/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input [7:0] index, 3 | 4 | output [7:0] o 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("SBOX.hex", mem); 11 | end 12 | 13 | assign o = mem[ index ]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_11/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_11/subbytes.v: -------------------------------------------------------------------------------- 1 | module subbytes ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | //Sub bytes computation for Encryption 10 | generate 11 | for(i = 0; i < 16; i = i+1) begin : sub_bytes 12 | 13 | sbox inst(.index(istate[8*i+7 : 8*i]), 14 | 15 | .o(ostate[8*i+7 : 8*i]) 16 | ); 17 | end 18 | endgenerate 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /aes_hw/aes_11/synch_fifo.v: -------------------------------------------------------------------------------- 1 | module synch_fifo #(parameter wbits = 128, abits = 2) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output full, 11 | output empty 12 | ); 13 | 14 | reg [abits:0] wptr; 15 | reg [abits:0] rptr; 16 | 17 | reg [wbits-1:0] fifofile [0 : 2**abits-1]; 18 | 19 | reg [wbits-1:0] fout; 20 | 21 | assign full = (wptr[abits-1:0] == rptr[abits-1:0]) & (wptr[abits] != rptr[abits]); 22 | assign empty = (wptr == rptr); 23 | 24 | always @(posedge clock) begin 25 | if(!resetn) begin 26 | wptr <= 'h0; 27 | rptr <= 'h0; 28 | end 29 | else begin 30 | if(wen & ~full) begin 31 | fifofile[wptr[abits-1:0]] <= wdata; 32 | wptr <= wptr + 'h1; 33 | end 34 | if(ren & ~empty) begin 35 | rptr <= rptr + 'h1; 36 | end 37 | end 38 | end 39 | 40 | assign rdata = fifofile[rptr[abits-1:0]]; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /aes_hw/aes_11/synch_reg.v: -------------------------------------------------------------------------------- 1 | module synch_reg #(parameter wbits = 128) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output reg full, 11 | output empty 12 | ); 13 | 14 | reg [wbits-1:0] mem; 15 | 16 | always @(posedge clock) begin 17 | if(!resetn) begin 18 | full <= 1'b0; 19 | mem <= 128'h0; 20 | end 21 | else if(wen & (~full)) begin 22 | full <= 1'b1; 23 | mem <= wdata; 24 | end 25 | else if(ren & full) begin 26 | full <= 1'b0; 27 | end 28 | end 29 | 30 | assign empty = ~full; 31 | 32 | assign rdata = mem; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /aes_hw/aes_11/test.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg cs = 1'b0; 7 | reg [3:0] a; 8 | reg [31:0] d; 9 | reg wen; 10 | reg ren; 11 | wire halt; 12 | wire [31:0] out; 13 | 14 | reg [31:0] d1; 15 | reg [31:0] d2; 16 | reg [31:0] d3; 17 | reg [31:0] d4; 18 | 19 | 20 | initial begin 21 | clk = 1'b0; 22 | forever #5 clk = ~clk; 23 | end 24 | 25 | initial begin 26 | #10; 27 | resetn = 1'b1; 28 | #10; 29 | resetn = 1'b0; 30 | #200; 31 | resetn = 1'b1; 32 | cs = 1'b0; 33 | wen = 1'b0; 34 | a = 4'h0; 35 | d = 32'h0; 36 | repeat(30)@(posedge clk); 37 | //ptwrite(128'h11111111111111111111111111111111); 38 | //ptwrite(128'h22222222222222222222222222222222); 39 | //ptwrite(128'h33333333333333333333333333333333); 40 | //ptwrite(128'h44444444444444444444444444444444); 41 | //ptwrite(128'h55555555555555555555555555555555); 42 | //ptwrite(128'h66666666666666666666666666666666); 43 | //ptwrite(128'h77777777777777777777777777777777); 44 | //ptwrite(128'h88888888888888888888888888888888); 45 | ptwrite(128'hffeeddccbbaa99887766554433221100); 46 | ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 47 | ptwrite(128'hffeeddccbbaa99887766554433221100); 48 | ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 49 | ptwrite(128'hffeeddccbbaa99887766554433221100); 50 | ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 51 | ptwrite(128'hffeeddccbbaa99887766554433221100); 52 | ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 53 | repeat(50)@(posedge clk); 54 | ptread; 55 | repeat(30)@(posedge clk); 56 | ptread; 57 | ptread; 58 | ptread; 59 | ptread; 60 | ptread; 61 | ptread; 62 | 63 | repeat(300)@(posedge clk); 64 | $finish; 65 | end 66 | 67 | 68 | task ptwrite; 69 | input [127:0] ptext; 70 | begin 71 | //repeat(1)@(posedge clk); 72 | wr(4'h0, ptext[127:96]); 73 | //repeat(1)@(posedge clk); 74 | wr(4'h0, ptext[95:64]); 75 | //repeat(1)@(posedge clk); 76 | wr(4'h0, ptext[63:32]); 77 | //repeat(1)@(posedge clk); 78 | wr(4'h0, ptext[31:0]); 79 | //repeat(10)@(posedge clk); 80 | end 81 | endtask 82 | 83 | task ptread; 84 | begin 85 | rd(4'h4); 86 | d1 = out; 87 | rd(4'h4); 88 | d2 = out; 89 | rd(4'h4); 90 | d3 = out; 91 | rd(4'h4); 92 | d4 = out; 93 | 94 | $display("%h %h %h %h", d1, d2, d3, d4); 95 | end 96 | endtask 97 | 98 | 99 | task wr; 100 | input [3:0] addr; 101 | input [31:0] data; 102 | begin 103 | cs = 1'b1; 104 | wen = 1'b1; 105 | a = addr; 106 | d = data; 107 | @(posedge clk); 108 | cs = 1'b0; 109 | wen = 1'b0; 110 | end 111 | endtask 112 | 113 | task rd; 114 | input [3:0] addr; 115 | begin 116 | cs = 1'b1; 117 | ren = 1'b1; 118 | a = addr; 119 | @(posedge clk); 120 | cs = 1'b0; 121 | ren = 1'b0; 122 | end 123 | endtask 124 | 125 | aes_slave_intf a0 (.clock(clk), .resetn(resetn), .chipselect(cs), .address(a), .writedata(d), .readdata(out), .write(wen), .chipselect1(cs), .address1(a), .read(ren), .waitrequest(halt)); 126 | 127 | wire [31:0] cipher; 128 | assign cipher = ren ? out : 32'hz; 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /aes_hw/aes_11/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable0; 7 | reg [127:0] i_text0; 8 | wire [127:0] o_text0; 9 | wire [127:0] Rkey0; 10 | reg [127:0] key0; 11 | wire done0; 12 | 13 | reg enable1; 14 | reg [127:0] i_text1; 15 | wire [127:0] o_text1; 16 | wire [127:0] Rkey1; 17 | reg [127:0] key1; 18 | wire done1; 19 | 20 | reg enable2; 21 | reg [127:0] i_text2; 22 | wire [127:0] o_text2; 23 | wire [127:0] Rkey2; 24 | reg [127:0] key2; 25 | wire done2; 26 | 27 | 28 | wire [127:0] cipher_text; 29 | 30 | reg [127:0] plain_text; 31 | reg plain_text_complete; 32 | 33 | reg [4:0] ecounter; 34 | reg [4:0] ecounter_next; 35 | 36 | wire [3:0] round; 37 | 38 | 39 | 40 | initial begin 41 | //$readmemh("SBOX.hex", mem); 42 | clk = 1'b0; 43 | forever #5 clk = ~clk; 44 | end 45 | 46 | initial begin 47 | resetn = 1'b0; 48 | #100; 49 | @(posedge clk); 50 | resetn = 1'b1; 51 | #50; 52 | @(posedge clk); 53 | plain_text = 128'hffeeddccbbaa99887766554433221100; 54 | plain_text_complete = 1'b1; 55 | @(posedge clk); 56 | plain_text_complete = 1'b1; 57 | plain_text = 128'hf47237c18b4c5a4059d1c3ab48966732; 58 | @(posedge clk); 59 | plain_text_complete = 1'b0; 60 | #100; 61 | $finish; 62 | end 63 | 64 | 65 | 66 | always @(posedge clk) begin 67 | if(!resetn) begin 68 | i_text0 <= 128'h0; 69 | key0 <= Rkey0; 70 | end 71 | else if(plain_text_complete) begin 72 | i_text0 <= plain_text ^ 128'h0f0e0d0c0b0a09080706050403020100; 73 | key0 <= 128'h0f0e0d0c0b0a09080706050403020100; 74 | end 75 | end 76 | 77 | always @(posedge clk) begin 78 | if(!resetn) begin 79 | enable0 <= 1'b0; 80 | end 81 | else if(plain_text_complete) begin 82 | enable0 <= 1'b1; 83 | end 84 | else begin 85 | enable0 <= 1'b0; 86 | end 87 | end 88 | 89 | 90 | 91 | always @(posedge clk) begin 92 | if(!resetn) begin 93 | i_text1 <= 128'h0; 94 | key1 <= Rkey1; 95 | end 96 | else if(done0) begin 97 | i_text1 <= o_text0; 98 | key1 <= Rkey0; 99 | end 100 | end 101 | 102 | always @(posedge clk) begin 103 | if(!resetn) begin 104 | enable1 <= 1'b0; 105 | end 106 | else if(done0) begin 107 | enable1 <= 1'b1; 108 | end 109 | else begin 110 | enable1 <= 1'b0; 111 | end 112 | end 113 | 114 | 115 | 116 | always @(posedge clk) begin 117 | if(!resetn) begin 118 | i_text2 <= 128'h0; 119 | key2 <= Rkey2; 120 | end 121 | else if(done1) begin 122 | i_text2 <= o_text1; 123 | key2 <= Rkey1; 124 | end 125 | end 126 | 127 | always @(posedge clk) begin 128 | if(!resetn) begin 129 | enable2 <= 1'b0; 130 | end 131 | else if(done1) begin 132 | enable2 <= 1'b1; 133 | end 134 | else begin 135 | enable2 <= 1'b0; 136 | end 137 | end 138 | 139 | 140 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable0), .i_text(i_text0), .key(key0), .round(4'h0), .o_text(o_text0), .Rkey(Rkey0), .done(done0)); 141 | aes s1 (.clock(clk), .resetn(resetn), .enable(enable1), .i_text(i_text1), .key(key1), .round(4'h1), .o_text(o_text1), .Rkey(Rkey1), .done(done1)); 142 | aes s2 (.clock(clk), .resetn(resetn), .enable(enable2), .i_text(i_text2), .key(key2), .round(4'h2), .o_text(o_text2), .Rkey(Rkey2), .done(done2)); 143 | 144 | 145 | assign cipher_text = o_text2; 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /aes_hw/aes_12/README: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_12/T0.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_12/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_12/synch_fifo.v: -------------------------------------------------------------------------------- 1 | module synch_fifo #(parameter wbits = 128, abits = 2) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output full, 11 | output empty 12 | ); 13 | 14 | reg [abits:0] wptr; 15 | reg [abits:0] rptr; 16 | 17 | reg [wbits-1:0] fifofile [0 : 2**abits-1]; 18 | 19 | reg [wbits-1:0] fout; 20 | 21 | assign full = (wptr[abits-1:0] == rptr[abits-1:0]) & (wptr[abits] != rptr[abits]); 22 | assign empty = (wptr == rptr); 23 | 24 | always @(posedge clock) begin 25 | if(!resetn) begin 26 | wptr <= 'h0; 27 | rptr <= 'h0; 28 | end 29 | else begin 30 | if(wen & ~full) begin 31 | fifofile[wptr[abits-1:0]] <= wdata; 32 | wptr <= wptr + 'h1; 33 | end 34 | if(ren & ~empty) begin 35 | rptr <= rptr + 'h1; 36 | end 37 | end 38 | end 39 | 40 | assign rdata = fifofile[rptr[abits-1:0]]; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /aes_hw/aes_12/synch_reg.v: -------------------------------------------------------------------------------- 1 | module synch_reg #(parameter wbits = 128) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output reg full, 11 | output empty 12 | ); 13 | 14 | reg [wbits-1:0] mem; 15 | 16 | always @(posedge clock) begin 17 | if(!resetn) begin 18 | full <= 1'b0; 19 | mem <= 128'h0; 20 | end 21 | else if(wen & (~full)) begin 22 | full <= 1'b1; 23 | mem <= wdata; 24 | end 25 | else if(ren & full) begin 26 | full <= 1'b0; 27 | end 28 | end 29 | 30 | assign empty = ~full; 31 | 32 | assign rdata = mem; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /aes_hw/aes_12/t0.v: -------------------------------------------------------------------------------- 1 | module tbox0 ( 2 | input [7:0] index, 3 | 4 | output [31:0] tbox 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | wire [7:0] sbox; 10 | wire [7:0] galois; 11 | 12 | initial begin 13 | $readmemh("T0.hex", mem); 14 | end 15 | 16 | assign sbox = mem[index]; 17 | assign galois = {sbox[6:0], 1'b0} ^ (sbox[7] ? 8'h1b : 8'h00); 18 | 19 | assign tbox = {galois ^ sbox, sbox, sbox, galois}; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /aes_hw/aes_12/test.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg cs = 1'b0; 7 | reg [3:0] a; 8 | reg [31:0] d; 9 | reg wen; 10 | reg ren; 11 | wire halt; 12 | wire [31:0] out; 13 | 14 | reg [31:0] d1; 15 | reg [31:0] d2; 16 | reg [31:0] d3; 17 | reg [31:0] d4; 18 | 19 | 20 | initial begin 21 | clk = 1'b0; 22 | forever #5 clk = ~clk; 23 | end 24 | 25 | initial begin 26 | #10; 27 | resetn = 1'b1; 28 | #10; 29 | resetn = 1'b0; 30 | #200; 31 | resetn = 1'b1; 32 | cs = 1'b0; 33 | wen = 1'b0; 34 | a = 4'h0; 35 | d = 32'h0; 36 | repeat(30)@(posedge clk); 37 | //ptwrite(128'h11111111111111111111111111111111); 38 | //ptwrite(128'h22222222222222222222222222222222); 39 | //ptwrite(128'h33333333333333333333333333333333); 40 | //ptwrite(128'h44444444444444444444444444444444); 41 | //ptwrite(128'h55555555555555555555555555555555); 42 | //ptwrite(128'h66666666666666666666666666666666); 43 | //ptwrite(128'h77777777777777777777777777777777); 44 | //ptwrite(128'h88888888888888888888888888888888); 45 | ptwrite(128'hffeeddccbbaa99887766554433221100); 46 | //repeat(100)@(posedge clk); 47 | ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 48 | //repeat(100)@(posedge clk); 49 | ptwrite(128'hffeeddccbbaa99887766554433221100); 50 | ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 51 | //ptwrite(128'hffeeddccbbaa99887766554433221100); 52 | //ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 53 | //ptwrite(128'hffeeddccbbaa99887766554433221100); 54 | //ptwrite(128'hf47237c18b4c5a4059d1c3ab48966732); 55 | repeat(100)@(posedge clk); 56 | ptread; 57 | ptread; 58 | 59 | repeat(300)@(posedge clk); 60 | $finish; 61 | end 62 | 63 | 64 | task ptwrite; 65 | input [127:0] ptext; 66 | begin 67 | //repeat(1)@(posedge clk); 68 | wr(4'h0, ptext[127:96]); 69 | //repeat(1)@(posedge clk); 70 | wr(4'h0, ptext[95:64]); 71 | //repeat(1)@(posedge clk); 72 | wr(4'h0, ptext[63:32]); 73 | //repeat(1)@(posedge clk); 74 | wr(4'h0, ptext[31:0]); 75 | //repeat(10)@(posedge clk); 76 | end 77 | endtask 78 | 79 | task ptread; 80 | begin 81 | rd(4'h4); 82 | d1 = out; 83 | rd(4'h4); 84 | d2 = out; 85 | rd(4'h4); 86 | d3 = out; 87 | rd(4'h4); 88 | d4 = out; 89 | 90 | $display("%h %h %h %h", d1, d2, d3, d4); 91 | end 92 | endtask 93 | 94 | 95 | task wr; 96 | input [3:0] addr; 97 | input [31:0] data; 98 | begin 99 | cs = 1'b1; 100 | wen = 1'b1; 101 | a = addr; 102 | d = data; 103 | @(posedge clk); 104 | cs = 1'b0; 105 | wen = 1'b0; 106 | end 107 | endtask 108 | 109 | task rd; 110 | input [3:0] addr; 111 | begin 112 | cs = 1'b1; 113 | ren = 1'b1; 114 | a = addr; 115 | @(posedge clk); 116 | cs = 1'b0; 117 | ren = 1'b0; 118 | end 119 | endtask 120 | 121 | aes_slave_intf a0 (.clock(clk), .resetn(resetn), .chipselect(cs), .address(a), .writedata(d), .readdata(out), .write(wen), .chipselect1(cs), .address1(a), .read(ren), .waitrequest(halt)); 122 | 123 | wire [31:0] cipher; 124 | assign cipher = ren ? out : 32'hz; 125 | 126 | endmodule 127 | -------------------------------------------------------------------------------- /aes_hw/aes_12/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable0; 7 | reg [127:0] i_text0; 8 | wire [127:0] o_text0; 9 | wire [127:0] Rkey0; 10 | reg [127:0] key0; 11 | wire done0; 12 | 13 | reg enable1; 14 | reg [127:0] i_text1; 15 | wire [127:0] o_text1; 16 | wire [127:0] Rkey1; 17 | reg [127:0] key1; 18 | wire done1; 19 | 20 | reg enable2; 21 | reg [127:0] i_text2; 22 | wire [127:0] o_text2; 23 | wire [127:0] Rkey2; 24 | reg [127:0] key2; 25 | wire done2; 26 | 27 | 28 | wire [127:0] cipher_text; 29 | 30 | reg [127:0] plain_text; 31 | reg plain_text_complete; 32 | 33 | reg [4:0] ecounter; 34 | reg [4:0] ecounter_next; 35 | 36 | wire [3:0] round; 37 | 38 | 39 | 40 | initial begin 41 | //$readmemh("SBOX.hex", mem); 42 | clk = 1'b0; 43 | forever #5 clk = ~clk; 44 | end 45 | 46 | initial begin 47 | resetn = 1'b0; 48 | #100; 49 | @(posedge clk); 50 | resetn = 1'b1; 51 | #50; 52 | @(posedge clk); 53 | plain_text = 128'hffeeddccbbaa99887766554433221100; 54 | plain_text_complete = 1'b1; 55 | @(posedge clk); 56 | plain_text_complete = 1'b1; 57 | plain_text = 128'hf47237c18b4c5a4059d1c3ab48966732; 58 | @(posedge clk); 59 | plain_text_complete = 1'b0; 60 | #100; 61 | $finish; 62 | end 63 | 64 | 65 | 66 | always @(posedge clk) begin 67 | if(!resetn) begin 68 | i_text0 <= 128'h0; 69 | key0 <= Rkey0; 70 | end 71 | else if(plain_text_complete) begin 72 | i_text0 <= plain_text ^ 128'h0f0e0d0c0b0a09080706050403020100; 73 | key0 <= 128'h0f0e0d0c0b0a09080706050403020100; 74 | end 75 | end 76 | 77 | always @(posedge clk) begin 78 | if(!resetn) begin 79 | enable0 <= 1'b0; 80 | end 81 | else if(plain_text_complete) begin 82 | enable0 <= 1'b1; 83 | end 84 | else begin 85 | enable0 <= 1'b0; 86 | end 87 | end 88 | 89 | 90 | 91 | always @(posedge clk) begin 92 | if(!resetn) begin 93 | i_text1 <= 128'h0; 94 | key1 <= Rkey1; 95 | end 96 | else if(done0) begin 97 | i_text1 <= o_text0; 98 | key1 <= Rkey0; 99 | end 100 | end 101 | 102 | always @(posedge clk) begin 103 | if(!resetn) begin 104 | enable1 <= 1'b0; 105 | end 106 | else if(done0) begin 107 | enable1 <= 1'b1; 108 | end 109 | else begin 110 | enable1 <= 1'b0; 111 | end 112 | end 113 | 114 | 115 | 116 | always @(posedge clk) begin 117 | if(!resetn) begin 118 | i_text2 <= 128'h0; 119 | key2 <= Rkey2; 120 | end 121 | else if(done1) begin 122 | i_text2 <= o_text1; 123 | key2 <= Rkey1; 124 | end 125 | end 126 | 127 | always @(posedge clk) begin 128 | if(!resetn) begin 129 | enable2 <= 1'b0; 130 | end 131 | else if(done1) begin 132 | enable2 <= 1'b1; 133 | end 134 | else begin 135 | enable2 <= 1'b0; 136 | end 137 | end 138 | 139 | 140 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable0), .i_text(i_text0), .key(key0), .round(4'h0), .o_text(o_text0), .Rkey(Rkey0), .done(done0)); 141 | aes s1 (.clock(clk), .resetn(resetn), .enable(enable1), .i_text(i_text1), .key(key1), .round(4'h1), .o_text(o_text1), .Rkey(Rkey1), .done(done1)); 142 | aes s2 (.clock(clk), .resetn(resetn), .enable(enable2), .i_text(i_text2), .key(key2), .round(4'h2), .o_text(o_text2), .Rkey(Rkey2), .done(done2)); 143 | 144 | 145 | assign cipher_text = o_text2; 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /aes_hw/aes_2/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_2/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | input [127:0] i_text, 7 | input [127:0] key, 8 | input [3:0] round, 9 | 10 | output reg [127:0] o_text, 11 | output reg [127:0] Rkey, 12 | output done 13 | ); 14 | 15 | reg [127:0] subbytes_text; 16 | wire [127:0] roundkey_text; 17 | wire [127:0] shiftrows_text; 18 | wire [127:0] mixcolumns_text; 19 | 20 | wire [127:0] okey; 21 | reg [31:0] tkey; 22 | 23 | reg [7:0] Rcon[0:9]; //Round Constant 24 | 25 | initial begin 26 | Rcon[0] = 8'h01; 27 | Rcon[1] = 8'h02; 28 | Rcon[2] = 8'h04; 29 | Rcon[3] = 8'h08; 30 | Rcon[4] = 8'h10; 31 | Rcon[5] = 8'h20; 32 | Rcon[6] = 8'h40; 33 | Rcon[7] = 8'h80; 34 | Rcon[8] = 8'h1b; 35 | Rcon[9] = 8'h36; 36 | end 37 | 38 | reg [1:0] scounter; 39 | reg [1:0] scounter_next; 40 | 41 | reg sbox_en; 42 | reg [159:0] sbox_in; 43 | wire [159:0] sbox_out; 44 | wire sbox_done; 45 | 46 | always @(posedge clock) begin 47 | if(!resetn) begin 48 | scounter <= 2'h0; 49 | end 50 | else begin 51 | scounter <= scounter_next; 52 | end 53 | end 54 | 55 | always @(scounter or enable or i_text or key or round or sbox_out or sbox_done) begin 56 | 57 | if((scounter == 2'h0)) begin 58 | if(enable) begin 59 | sbox_en = 1'b1; 60 | sbox_in = { i_text, key[103:96], key[127:104] }; 61 | scounter_next = scounter + 2'h1; 62 | end 63 | else begin 64 | sbox_en = 1'b0; 65 | sbox_in = 160'h0; 66 | scounter_next = 2'h0; 67 | tkey = 32'h0; 68 | end 69 | end 70 | else if((scounter == 2'h1)) begin 71 | if(sbox_done) begin 72 | scounter_next = scounter + 2'h1; 73 | tkey[7 : 0] = sbox_out[7:0] ^ key[7 : 0] ^ Rcon[round]; 74 | tkey[15 : 8] = sbox_out[15:8] ^ key[15 : 8]; 75 | tkey[23 : 16] = sbox_out[23:16] ^ key[23 : 16]; 76 | tkey[31 : 24] = sbox_out[31:24] ^ key[31 : 24]; 77 | end 78 | end 79 | else if((scounter == 2'h2)) begin 80 | sbox_en = 1'b0; 81 | scounter_next = 2'h0; 82 | end 83 | end 84 | 85 | 86 | //SBOX lookup 87 | sbox inst ( .clk(clock), 88 | .resetn(resetn), 89 | 90 | .enable(sbox_en), 91 | .index(sbox_in), 92 | 93 | .sbout(sbox_out), 94 | .done(sbox_done) 95 | ); 96 | 97 | 98 | always @(posedge clock) begin 99 | if(!resetn) begin 100 | subbytes_text <= 128'h0; 101 | end 102 | else if((scounter == 5'h1) & sbox_done) begin 103 | subbytes_text <= sbox_out[159:32]; 104 | end 105 | end 106 | 107 | 108 | 109 | 110 | //Shift Rows for Encryption 111 | shiftrows U2 (.istate(subbytes_text), .ostate(shiftrows_text)); 112 | 113 | //Mix Columns for Encryption 114 | mixcolumns U3 (.istate(shiftrows_text), .bypass(round==4'h9), .ostate(mixcolumns_text)); 115 | 116 | //Key Expansion for Encryption 117 | assign okey[31:0] = tkey[31:0]; 118 | assign okey[127:32] = key[127:32] ^ okey[95:0]; 119 | 120 | //Add Roundkey for Encryption 121 | assign roundkey_text = mixcolumns_text ^ okey; 122 | 123 | 124 | assign done = (scounter == 5'h2); 125 | 126 | always @(posedge clock) begin 127 | if(!resetn) begin 128 | o_text <= 128'h0; 129 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 130 | end 131 | else if(done & (round == 4'h9)) begin 132 | o_text <= roundkey_text; 133 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 134 | end 135 | else if(done) begin 136 | o_text <= roundkey_text; 137 | Rkey <= okey; 138 | end 139 | end 140 | 141 | 142 | endmodule 143 | -------------------------------------------------------------------------------- /aes_hw/aes_2/aes_slave_intf.v: -------------------------------------------------------------------------------- 1 | module aes_slave_intf ( 2 | input clock, 3 | input resetn, 4 | 5 | input chipselect, 6 | input [3:0] address, 7 | 8 | input read, 9 | output reg [31:0] readdata, 10 | 11 | input write, 12 | input [31:0] writedata, 13 | 14 | output waitrequest 15 | ); 16 | 17 | reg [127:0] plain_text; 18 | reg [127:0] cipher_text; 19 | 20 | 21 | wire plain_text_write; 22 | reg plain_text_complete; 23 | 24 | reg [1:0] icounter; 25 | 26 | reg [4:0] ecounter; 27 | reg [4:0] ecounter_next; 28 | 29 | reg enable; 30 | reg [127:0] i_text; 31 | wire [3:0] round; 32 | wire [127:0] o_text; 33 | wire [127:0] Rkey; 34 | 35 | wire done; 36 | 37 | wire cipher_text_read; 38 | reg [1:0] ocounter; 39 | reg cipher_available; 40 | wire cipher_status_read; 41 | 42 | 43 | 44 | assign plain_text_write = chipselect & write & (address == 4'h0); 45 | 46 | 47 | always @(posedge clock) begin 48 | if(!resetn) begin 49 | icounter <= 2'h0; 50 | end 51 | else if(plain_text_write) begin 52 | icounter <= icounter + 2'h1; 53 | end 54 | end 55 | 56 | 57 | always @(posedge clock) begin 58 | if(!resetn) begin 59 | plain_text <= 128'h0; 60 | plain_text_complete <= 1'b0; 61 | end 62 | else if((icounter == 2'h0) & plain_text_write) begin // & ~waitrequest 63 | plain_text <= {96'h0, writedata}; 64 | plain_text_complete <= 1'b0; 65 | end 66 | else if((icounter == 2'h1) & plain_text_write) begin // & ~waitrequest 67 | plain_text <= {plain_text[95:0], writedata}; 68 | end 69 | else if((icounter == 2'h2) & plain_text_write) begin // & ~waitrequest 70 | plain_text <= {plain_text[95:0], writedata}; 71 | end 72 | else if((icounter == 2'h3) & plain_text_write) begin // & ~waitrequest 73 | plain_text <= {plain_text[95:0], writedata}; 74 | plain_text_complete <= 1'b1; 75 | end 76 | else begin 77 | plain_text_complete <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | 83 | 84 | 85 | 86 | always @(posedge clock) begin 87 | if(!resetn) begin 88 | ecounter <= 5'h0; 89 | end 90 | else begin 91 | ecounter <= ecounter_next; 92 | end 93 | end 94 | 95 | //Multiple rounds - 10 for 128bit encryption. 96 | always @(ecounter or plain_text_complete or o_text or plain_text or Rkey or done) begin 97 | 98 | if( (ecounter == 5'h0) ) begin 99 | cipher_text = o_text; 100 | if(plain_text_complete) begin 101 | enable = 1'b1; 102 | i_text = plain_text ^ Rkey; 103 | ecounter_next = 5'h1; 104 | end 105 | else begin 106 | enable = 1'b0; 107 | i_text = 128'h0; 108 | ecounter_next = ecounter; 109 | end 110 | end 111 | else if( (ecounter == 5'h13) ) begin 112 | enable = 1'b0; 113 | if(done) begin 114 | ecounter_next = 5'h0; 115 | end 116 | end 117 | else if( (ecounter[0]) ) begin 118 | enable = 1'b0; 119 | if(done) begin 120 | ecounter_next = ecounter + 5'h1; 121 | end 122 | end 123 | else if( (!ecounter[0]) )begin 124 | enable = 1'b1; 125 | i_text = o_text; 126 | ecounter_next = ecounter + 5'h1; 127 | end 128 | 129 | end 130 | 131 | 132 | assign round = ecounter[4:1]; 133 | 134 | //Compute AES cipher for one round. 135 | aes aes0 ( 136 | .clock(clock), 137 | .resetn(resetn), 138 | 139 | .enable(enable), 140 | 141 | .i_text(i_text), 142 | .key(Rkey), 143 | .round(round), 144 | 145 | .o_text(o_text), 146 | .Rkey(Rkey), 147 | 148 | .done(done) 149 | ); 150 | 151 | 152 | 153 | always @(posedge clock) begin 154 | if(!resetn) begin 155 | cipher_available <= 1'b0; 156 | end 157 | else if((ecounter == 5'h13) & done) begin 158 | cipher_available <= 1'b1; 159 | end 160 | else if((ecounter == 5'h0) & plain_text_complete) begin 161 | cipher_available <= 1'b0; 162 | end 163 | end 164 | 165 | 166 | assign cipher_text_read = chipselect & read & (address == 4'h4); 167 | assign cipher_status_read = chipselect & read & (address == 4'h8); 168 | 169 | always @(posedge clock) begin 170 | if(!resetn) begin 171 | ocounter <= 2'h0; 172 | end 173 | else if(cipher_text_read & (~waitrequest)) begin 174 | ocounter <= ocounter + 2'h1; 175 | end 176 | end 177 | 178 | 179 | //Reading Out Cipher 180 | always @(ocounter or cipher_text_read or cipher_status_read or cipher_text or cipher_available) begin 181 | readdata = 32'h0; 182 | 183 | if(cipher_text_read) begin 184 | case(ocounter) 185 | 2'h0 : begin readdata = cipher_text[127:96]; end 186 | 2'h1 : begin readdata = cipher_text[95:64]; end 187 | 2'h2 : begin readdata = cipher_text[63:32]; end 188 | 2'h3 : begin readdata = cipher_text[31:0]; end 189 | endcase 190 | end 191 | 192 | else if(cipher_status_read) begin 193 | readdata = {31'h0, cipher_available}; 194 | end 195 | 196 | end 197 | 198 | assign waitrequest = cipher_text_read & (~cipher_available); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /aes_hw/aes_2/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input [127:0] istate, 3 | input bypass, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | wire [127:0] buf1; 9 | wire [127:0] buf3; 10 | wire [127:0] buf4; 11 | 12 | genvar i; 13 | 14 | generate 15 | for(i = 0; i < 16; i= i+4) begin : mix_columns0 16 | 17 | assign buf1[ 8*i+31 : 8*i ] = { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] } ^ { istate[ 8*i+15 : 8*i ], istate[ 8*i+31 : 8*i+16 ] } ^ { istate[ 8*i+23 : 8*i ], istate[ 8*i+31 : 8*i+24 ] }; 18 | 19 | assign buf3[ 8*i+31 : 8*i] = istate[ 8*i+31 : 8*i ] ^ { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] }; 20 | 21 | //Galois Multiplication 22 | assign buf4[ 8*(i)+7 : 8*(i) ] = buf3[ 8*(i)+7 ] ? ( { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 }; 23 | assign buf4[ 8*(i+1)+7 : 8*(i+1) ] = buf3[ 8*(i+1)+7 ] ? ( { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 }; 24 | assign buf4[ 8*(i+2)+7 : 8*(i+2) ] = buf3[ 8*(i+2)+7 ] ? ( { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 }; 25 | assign buf4[ 8*(i+3)+7 : 8*(i+3) ] = buf3[ 8*(i+3)+7 ] ? ( { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 }; 26 | 27 | //bypass option for last round of encryption 28 | assign ostate[ 8*i+31 : 8*i ] = bypass ? istate[ 8*i+31 : 8*i ] : buf1[ 8*i+31 : 8*i ] ^ buf4[ 8*i+31 : 8*i ]; 29 | 30 | end 31 | endgenerate 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /aes_hw/aes_2/sample.c: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_2/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input clk, 3 | input resetn, 4 | 5 | input [159:0] index, 6 | input enable, 7 | 8 | output reg [159:0] sbout, 9 | output done 10 | ); 11 | 12 | reg [7:0] p; 13 | wire [7:0] p_next; 14 | 15 | reg [7:0] q; 16 | wire [7:0] q_next; 17 | 18 | wire [7:0] aff; 19 | 20 | reg [19:0] complete; 21 | 22 | genvar i; 23 | 24 | 25 | always @(posedge clk) begin 26 | if(!resetn) begin 27 | p <= 8'h1; 28 | q <= 8'h1; 29 | end 30 | else if(!enable) begin 31 | p <= 8'h1; 32 | q <= 8'h1; 33 | end 34 | else begin 35 | p <= p_next; 36 | q <= q_next; 37 | end 38 | end 39 | 40 | /* Multiply by 03 in Galois Field GF(256) 41 | * p = p ^ (p<<1) ^ (p & 0x80 ? 0x1b : 0x00); 42 | * */ 43 | assign p_next = {p[7]^p[6], p[6]^p[5], p[5]^p[4], p[4]^p[3]^p[7], p[3]^p[2]^p[7], p[2]^p[1], p[1]^p[0]^p[7], p[0]^p[7]}; 44 | 45 | /* Inverse of p in Galois Field GF(256) 46 | * q ^= q<<1; 47 | * q ^= q<<2; 48 | * q ^= q<<4; 49 | * q ^= q & 0x80 ? 0x09 : 0x00; 50 | * */ 51 | assign q_next[0] = q[0] ^ q_next[7]; 52 | assign q_next[1] = q[1] ^ q[0]; 53 | assign q_next[2] = q[2] ^ q_next[1]; 54 | assign q_next[3] = q[7] ^ q[6] ^ q[5] ^ q[4]; 55 | assign q_next[4] = q[4] ^ q[3] ^ q_next[2]; 56 | assign q_next[5] = q[5] ^ q_next[4]; 57 | assign q_next[6] = q[6] ^ q_next[5]; 58 | assign q_next[7] = q[7] ^ q_next[6]; 59 | 60 | 61 | /* Compute Affine Transformation 62 | * b'(i) = b(i) ^ b(i+4 % 8) ^ b(i+5 % 8) ^ b(i+6 % 8) ^ b(i+7 % 8) ^ c(i); 63 | * c = 0x63; 64 | */ 65 | assign aff[0] = ~(q[0] ^ q_next[3]); //q[0] ^ q[4] ^ q[5] ^ q[6] ^ q[7] ^ 1'b1; 66 | assign aff[1] = ~(q_next[1] ^ q_next[3] ^ q[4]); //q[1] ^ q[5] ^ q[6] ^ q[7] ^ q[0] ^ 1'b1; 67 | assign aff[2] = q_next[2] ^ q[6] ^ q[7]; //q[2] ^ q[6] ^ q[7] ^ q[0] ^ q[1] ^ 1'b0; 68 | assign aff[3] = q_next[4] ^ q[4] ^ q[7]; //q[3] ^ q[7] ^ q[0] ^ q[1] ^ q[2] ^ 1'b0; 69 | assign aff[4] = q_next[4]; //q[4] ^ q[0] ^ q[1] ^ q[2] ^ q[3] ^ 1'b0; 70 | assign aff[5] = ~(q_next[5] ^ q[0]); //q[5] ^ q[1] ^ q[2] ^ q[3] ^ q[4] ^ 1'b1; 71 | assign aff[6] = ~(q_next[6] ^ q_next[1]); //q[6] ^ q[2] ^ q[3] ^ q[4] ^ q[5] ^ 1'b1; 72 | assign aff[7] = q_next[7] ^ q_next[2]; //q[7] ^ q[3] ^ q[4] ^ q[5] ^ q[6] ^ 1'b0; 73 | 74 | 75 | generate 76 | for(i = 0; i < 20; i = i+1) begin : sbox_sample 77 | always @(enable or aff or index or p) begin 78 | if(enable) begin 79 | if(index[8*i+7:8*i] == 8'h0) begin 80 | complete[i] = 1'b1; 81 | end 82 | else if(index[8*i+7:8*i] == p) begin 83 | sbout[8*i+7:8*i] = aff; 84 | complete[i] = 1'b1; 85 | end 86 | end 87 | else begin 88 | sbout[8*i+7:8*i] = 8'h63; 89 | complete[i] = 1'b0; 90 | end 91 | end 92 | end 93 | 94 | endgenerate 95 | 96 | 97 | assign done = &(complete[19:0]); 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /aes_hw/aes_2/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_2/test2.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg clk; 4 | reg resetn; 5 | 6 | 7 | reg [159:0] ptext; 8 | wire [127:0] stext; 9 | wire [159:0] dout; 10 | 11 | wire sdone; 12 | wire mdone; 13 | wire [31:0] mout; 14 | reg men; 15 | reg [127:0] s; 16 | 17 | wire done; 18 | reg enable; 19 | 20 | initial begin 21 | clk = 1'b0; 22 | forever #5 clk = ~clk; 23 | end 24 | 25 | initial begin 26 | resetn = 1'b0; 27 | enable = 1'b0; 28 | #100; 29 | resetn = 1'b1; 30 | #50; 31 | ptext = 128'hffeeddccbbaa99887766554433221100 ^ 128'h0f0e0d0c0b0a09080706050403020100; 32 | enable = 1'b1; 33 | #2560; 34 | enable = 1'b0; 35 | #100; 36 | men = 1'b1; 37 | #400; 38 | men = 1'b0; 39 | #100; 40 | $finish; 41 | end 42 | 43 | 44 | sbox s0 (.clk(clk), .resetn(resetn), .enable(enable), .index(ptext), .sbout(dout), .done(sdone)); 45 | //Shift Rows for Encryption 46 | shiftrows U2 (.istate(dout[127:0]), .ostate(stext)); 47 | 48 | always @(posedge clk) begin 49 | if(!resetn) begin 50 | s <= 128'h0; 51 | end 52 | else if(sdone) begin 53 | s <= stext; 54 | end 55 | end 56 | 57 | //Mix Columns for Encryption 58 | mixcolumns U3 (.clock(clk), .resetn(resetn), .enable(men), .istate(s), .ostate(mout), .done(mdone)); 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /aes_hw/aes_3/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_3/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | input [127:0] i_text, 7 | input [127:0] key, 8 | input [3:0] round, 9 | 10 | output reg [127:0] o_text, 11 | output reg [127:0] Rkey, 12 | output reg done 13 | ); 14 | 15 | reg [127:0] subbytes_text; 16 | wire [127:0] roundkey_text; 17 | wire [127:0] shiftrows_text; 18 | reg [127:0] mixcolumns_text; 19 | 20 | wire [127:0] okey; 21 | reg [31:0] tkey; 22 | 23 | reg [7:0] Rcon[0:9]; //Round Constant 24 | 25 | initial begin 26 | Rcon[0] = 8'h01; 27 | Rcon[1] = 8'h02; 28 | Rcon[2] = 8'h04; 29 | Rcon[3] = 8'h08; 30 | Rcon[4] = 8'h10; 31 | Rcon[5] = 8'h20; 32 | Rcon[6] = 8'h40; 33 | Rcon[7] = 8'h80; 34 | Rcon[8] = 8'h1b; 35 | Rcon[9] = 8'h36; 36 | end 37 | 38 | reg [3:0] scounter; 39 | reg [3:0] scounter_next; 40 | 41 | reg sbox_en; 42 | reg [159:0] sbox_in; 43 | wire [159:0] sbox_out; 44 | wire sbox_done; 45 | 46 | reg mix_en; 47 | reg [31:0] mix_in; 48 | wire [31:0] mix_out; 49 | wire mix_done; 50 | 51 | always @(posedge clock) begin 52 | if(!resetn) begin 53 | scounter <= 4'h0; 54 | end 55 | else begin 56 | scounter <= scounter_next; 57 | end 58 | end 59 | 60 | always @(scounter or enable or i_text or key or round or sbox_out or sbox_done or shiftrows_text or mix_out or mix_done) begin 61 | 62 | done = 1'b0; 63 | 64 | if((scounter == 4'h0)) begin 65 | if(enable) begin 66 | sbox_en = 1'b1; 67 | sbox_in = { i_text, key[103:96], key[127:104] }; 68 | scounter_next = scounter + 4'h1; 69 | mix_en = 1'b0; 70 | mix_in = 32'h0; 71 | end 72 | else begin 73 | sbox_en = 1'b0; 74 | sbox_in = 160'h0; 75 | scounter_next = 4'h0; 76 | tkey = 32'h0; 77 | mix_en = 1'b0; 78 | mix_in = 32'h0; 79 | mixcolumns_text = 128'h0; 80 | end 81 | end 82 | else if((scounter == 4'h1)) begin 83 | if(sbox_done) begin 84 | scounter_next = scounter + 4'h1; 85 | tkey[7 : 0] = sbox_out[7:0] ^ key[7 : 0] ^ Rcon[round]; 86 | tkey[15 : 8] = sbox_out[15:8] ^ key[15 : 8]; 87 | tkey[23 : 16] = sbox_out[23:16] ^ key[23 : 16]; 88 | tkey[31 : 24] = sbox_out[31:24] ^ key[31 : 24]; 89 | end 90 | end 91 | else if((scounter == 4'h2)) begin 92 | sbox_en = 1'b0; 93 | if(round == 4'h9) begin 94 | mix_en = 1'b0; 95 | mixcolumns_text = shiftrows_text; 96 | scounter_next = 4'h0; 97 | done = 1'b1; 98 | end 99 | else begin 100 | mix_en = 1'b1; 101 | mix_in = shiftrows_text[31:0]; 102 | scounter_next = scounter + 4'h1; 103 | end 104 | end 105 | else if((scounter == 4'h3)) begin 106 | if(mix_done) begin 107 | mixcolumns_text[31:0] = mix_out; 108 | scounter_next = scounter + 4'h1; 109 | end 110 | end 111 | else if((scounter == 4'h4)) begin 112 | sbox_en = 1'b0; 113 | mix_en = 1'b1; 114 | mix_in = shiftrows_text[63:32]; 115 | scounter_next = scounter + 4'h1; 116 | end 117 | else if((scounter == 4'h5)) begin 118 | if(mix_done) begin 119 | mixcolumns_text[63:32] = mix_out; 120 | scounter_next = scounter + 4'h1; 121 | end 122 | end 123 | else if((scounter == 4'h6)) begin 124 | sbox_en = 1'b0; 125 | mix_en = 1'b1; 126 | mix_in = shiftrows_text[95:64]; 127 | scounter_next = scounter + 4'h1; 128 | end 129 | else if((scounter == 4'h7)) begin 130 | if(mix_done) begin 131 | mixcolumns_text[95:64] = mix_out; 132 | scounter_next = scounter + 4'h1; 133 | end 134 | end 135 | else if((scounter == 4'h8)) begin 136 | sbox_en = 1'b0; 137 | mix_en = 1'b1; 138 | mix_in = shiftrows_text[127:96]; 139 | scounter_next = scounter + 4'h1; 140 | end 141 | else if((scounter == 4'h9)) begin 142 | if(mix_done) begin 143 | mixcolumns_text[127:96] = mix_out; 144 | scounter_next = 4'h0; 145 | done = 1'b1; 146 | end 147 | end 148 | end 149 | 150 | 151 | //SBOX lookup 152 | sbox inst ( .clk(clock), 153 | .resetn(resetn), 154 | 155 | .enable(sbox_en), 156 | .index(sbox_in), 157 | 158 | .sbout(sbox_out), 159 | .done(sbox_done) 160 | ); 161 | 162 | 163 | always @(posedge clock) begin 164 | if(!resetn) begin 165 | subbytes_text <= 128'h0; 166 | end 167 | else if((scounter == 5'h1) & sbox_done) begin 168 | subbytes_text <= sbox_out[159:32]; 169 | end 170 | end 171 | 172 | 173 | //Shift Rows for Encryption 174 | shiftrows U2 (.istate(subbytes_text), .ostate(shiftrows_text)); 175 | 176 | //Mix Columns for Encryption 177 | mixcolumns U3 (.clock(clock), .resetn(resetn), .enable(mix_en), .istate(mix_in), .ostate(mix_out), .done(mix_done)); 178 | 179 | //Key Expansion for Encryption 180 | assign okey[31:0] = tkey[31:0]; 181 | assign okey[127:32] = key[127:32] ^ okey[95:0]; 182 | 183 | //Add Roundkey for Encryption 184 | assign roundkey_text = mixcolumns_text ^ okey; 185 | 186 | 187 | always @(posedge clock) begin 188 | if(!resetn) begin 189 | o_text <= 128'h0; 190 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 191 | end 192 | else if(done & (round == 4'h9)) begin 193 | o_text <= roundkey_text; 194 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 195 | end 196 | else if(done) begin 197 | o_text <= roundkey_text; 198 | Rkey <= okey; 199 | end 200 | end 201 | 202 | 203 | endmodule 204 | -------------------------------------------------------------------------------- /aes_hw/aes_3/aes_slave_intf.v: -------------------------------------------------------------------------------- 1 | module aes_slave_intf ( 2 | input clock, 3 | input resetn, 4 | 5 | input chipselect, 6 | input [3:0] address, 7 | 8 | input read, 9 | output reg [31:0] readdata, 10 | 11 | input write, 12 | input [31:0] writedata, 13 | 14 | output waitrequest 15 | ); 16 | 17 | reg [127:0] plain_text; 18 | reg [127:0] cipher_text; 19 | 20 | 21 | wire plain_text_write; 22 | reg plain_text_complete; 23 | 24 | reg [1:0] icounter; 25 | 26 | reg [4:0] ecounter; 27 | reg [4:0] ecounter_next; 28 | 29 | reg enable; 30 | reg [127:0] i_text; 31 | wire [3:0] round; 32 | wire [127:0] o_text; 33 | wire [127:0] Rkey; 34 | 35 | wire done; 36 | 37 | wire cipher_text_read; 38 | reg [1:0] ocounter; 39 | reg cipher_available; 40 | wire cipher_status_read; 41 | 42 | 43 | 44 | assign plain_text_write = chipselect & write & (address == 4'h0); 45 | 46 | 47 | always @(posedge clock) begin 48 | if(!resetn) begin 49 | icounter <= 2'h0; 50 | end 51 | else if(plain_text_write) begin 52 | icounter <= icounter + 2'h1; 53 | end 54 | end 55 | 56 | 57 | always @(posedge clock) begin 58 | if(!resetn) begin 59 | plain_text <= 128'h0; 60 | plain_text_complete <= 1'b0; 61 | end 62 | else if((icounter == 2'h0) & plain_text_write) begin // & ~waitrequest 63 | plain_text <= {96'h0, writedata}; 64 | plain_text_complete <= 1'b0; 65 | end 66 | else if((icounter == 2'h1) & plain_text_write) begin // & ~waitrequest 67 | plain_text <= {plain_text[95:0], writedata}; 68 | end 69 | else if((icounter == 2'h2) & plain_text_write) begin // & ~waitrequest 70 | plain_text <= {plain_text[95:0], writedata}; 71 | end 72 | else if((icounter == 2'h3) & plain_text_write) begin // & ~waitrequest 73 | plain_text <= {plain_text[95:0], writedata}; 74 | plain_text_complete <= 1'b1; 75 | end 76 | else begin 77 | plain_text_complete <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | 83 | 84 | 85 | 86 | always @(posedge clock) begin 87 | if(!resetn) begin 88 | ecounter <= 5'h0; 89 | end 90 | else begin 91 | ecounter <= ecounter_next; 92 | end 93 | end 94 | 95 | //Multiple rounds - 10 for 128bit encryption. 96 | always @(ecounter or plain_text_complete or o_text or plain_text or Rkey or done) begin 97 | 98 | if( (ecounter == 5'h0) ) begin 99 | cipher_text = o_text; 100 | if(plain_text_complete) begin 101 | enable = 1'b1; 102 | i_text = plain_text ^ Rkey; 103 | ecounter_next = 5'h1; 104 | end 105 | else begin 106 | enable = 1'b0; 107 | i_text = 128'h0; 108 | ecounter_next = ecounter; 109 | end 110 | end 111 | else if( (ecounter == 5'h13) ) begin 112 | enable = 1'b0; 113 | if(done) begin 114 | ecounter_next = 5'h0; 115 | end 116 | end 117 | else if( (ecounter[0]) ) begin 118 | enable = 1'b0; 119 | if(done) begin 120 | ecounter_next = ecounter + 5'h1; 121 | end 122 | end 123 | else if( (!ecounter[0]) )begin 124 | enable = 1'b1; 125 | i_text = o_text; 126 | ecounter_next = ecounter + 5'h1; 127 | end 128 | 129 | end 130 | 131 | 132 | assign round = ecounter[4:1]; 133 | 134 | //Compute AES cipher for one round. 135 | aes aes0 ( 136 | .clock(clock), 137 | .resetn(resetn), 138 | 139 | .enable(enable), 140 | 141 | .i_text(i_text), 142 | .key(Rkey), 143 | .round(round), 144 | 145 | .o_text(o_text), 146 | .Rkey(Rkey), 147 | 148 | .done(done) 149 | ); 150 | 151 | 152 | 153 | always @(posedge clock) begin 154 | if(!resetn) begin 155 | cipher_available <= 1'b0; 156 | end 157 | else if((ecounter == 5'h13) & done) begin 158 | cipher_available <= 1'b1; 159 | end 160 | else if((ecounter == 5'h0) & plain_text_complete) begin 161 | cipher_available <= 1'b0; 162 | end 163 | end 164 | 165 | 166 | assign cipher_text_read = chipselect & read & (address == 4'h4); 167 | assign cipher_status_read = chipselect & read & (address == 4'h8); 168 | 169 | always @(posedge clock) begin 170 | if(!resetn) begin 171 | ocounter <= 2'h0; 172 | end 173 | else if(cipher_text_read & (~waitrequest)) begin 174 | ocounter <= ocounter + 2'h1; 175 | end 176 | end 177 | 178 | 179 | //Reading Out Cipher 180 | always @(ocounter or cipher_text_read or cipher_status_read or cipher_text or cipher_available) begin 181 | readdata = 32'h0; 182 | 183 | if(cipher_text_read) begin 184 | case(ocounter) 185 | 2'h0 : begin readdata = cipher_text[127:96]; end 186 | 2'h1 : begin readdata = cipher_text[95:64]; end 187 | 2'h2 : begin readdata = cipher_text[63:32]; end 188 | 2'h3 : begin readdata = cipher_text[31:0]; end 189 | endcase 190 | end 191 | 192 | else if(cipher_status_read) begin 193 | readdata = {31'h0, cipher_available}; 194 | end 195 | 196 | end 197 | 198 | assign waitrequest = cipher_text_read & (~cipher_available); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /aes_hw/aes_3/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | input [31:0] istate, 7 | 8 | output reg [31:0] ostate, 9 | output reg done 10 | ); 11 | 12 | reg [3:0] counter; 13 | reg [3:0] counter_next; 14 | 15 | reg [31:0] tstate; 16 | reg [7:0] i1_1; 17 | reg [7:0] i1_2; 18 | reg [7:0] i2_1; 19 | reg [7:0] i2_2; 20 | wire [7:0] o1; 21 | wire [7:0] o2; 22 | 23 | always @(posedge clock) begin 24 | if(!resetn) begin 25 | counter <= 4'h0; 26 | ostate <= 32'h0; 27 | end 28 | else if(enable) begin 29 | counter <= counter_next; 30 | ostate <= tstate; 31 | end 32 | end 33 | 34 | 35 | always @(counter or enable or istate or ostate or o1 or o2) begin 36 | 37 | if(enable) begin 38 | counter_next = counter + 4'h1; 39 | end 40 | else begin 41 | tstate = 32'h0; 42 | counter_next = 4'h0; 43 | end 44 | 45 | if((counter == 4'h0)) begin 46 | i1_1 = istate[15:8]; 47 | i1_2 = istate[7:0]; 48 | tstate[7:0] = o1; 49 | 50 | i2_1 = istate[31:24]; 51 | i2_2 = istate[23:16]; 52 | tstate[23:16] = o2; 53 | done = 1'b0; 54 | end 55 | else if((counter == 4'h1)) begin 56 | i1_1 = ostate[23:16]; 57 | i1_2 = ostate[7:0]; 58 | tstate[7:0] = o1; //a0 = a 59 | 60 | i2_1 = o1; 61 | i2_2 = istate[15:8]; 62 | tstate[15:8] = o2; //a1 = a + a1 63 | end 64 | else if((counter == 4'h2)) begin 65 | i1_1 = ostate[7:0]; 66 | i1_2 = istate[23:16]; 67 | tstate[23:16] = o1; //a2 = a + a2 68 | 69 | i2_1 = ostate[7:0]; 70 | i2_2 = istate[31:24]; 71 | tstate[31:24] = o2; //a3 = a + a3 72 | end 73 | else if((counter == 4'h3)) begin 74 | i1_1 = ostate[7:0]; 75 | i1_2 = istate[7:0]; 76 | tstate[7:0] = o1; //a0 = a + a0 77 | 78 | i2_1 = {istate[6:0], 1'b0}; 79 | i2_2 = {3'b000, istate[7], istate[7], 1'b0, istate[7], istate[7]}; 80 | end 81 | else if((counter == 4'h4)) begin 82 | i1_1 = ostate[7:0]; 83 | i1_2 = o2; 84 | tstate[7:0] = o1; //a0 = a + a0 + 2a0 85 | end 86 | else if((counter == 4'h5)) begin 87 | i1_1 = ostate[31:24]; 88 | i1_2 = o2; 89 | tstate[31:24] = o1; //a3 = a + a3 + 2a0 90 | end 91 | else if((counter == 4'h6)) begin 92 | i1_1 = {istate[14:8], 1'b0}; 93 | i1_2 = {3'b000, istate[15], istate[15], 1'b0, istate[15], istate[15]}; 94 | 95 | i2_1 = ostate[7:0]; 96 | i2_2 = o1; 97 | tstate[7:0] = o2; // a0 = a + a0 + 2a1 + 2a0 98 | end 99 | else if((counter == 4'h7)) begin 100 | i2_1 = ostate[15:8]; 101 | i2_2 = o1; 102 | tstate[15:8] = o2; //a1 = a + a1 + 2a1 103 | end 104 | else if((counter == 4'h8)) begin 105 | i1_1 = {istate[22:16], 1'b0}; 106 | i1_2 = {3'b000, istate[23], istate[23], 1'b0, istate[23], istate[23]}; 107 | 108 | i2_1 = ostate[23:16]; 109 | i2_2 = o1; 110 | tstate[23:16] = o2; //a2 = a + a2 + 2a2 111 | end 112 | else if((counter == 4'h9)) begin 113 | i2_1 = ostate[15:8]; 114 | i2_2 = o1; 115 | tstate[15:8] = o2; //a1 = a + a1 + 2a1 + 2a2 116 | end 117 | else if((counter == 4'hA)) begin 118 | i1_1 = {istate[30:24], 1'b0}; 119 | i1_2 = {3'b000, istate[31], istate[31], 1'b0, istate[31], istate[31]}; 120 | 121 | i2_1 = ostate[31:24]; 122 | i2_2 = o1; 123 | tstate[31:24] = o2; //a3 = a + a3 + 2a0 + 2a3 124 | end 125 | else if((counter == 4'hB)) begin 126 | i2_1 = ostate[23:16]; 127 | i2_2 = o1; 128 | tstate[23:16] = o2; //a2 = a + a2 + 2a2 + 2a3 129 | end 130 | else begin 131 | done = 1'b1; 132 | counter_next = 4'h0; 133 | end 134 | end 135 | 136 | 137 | cxor x1 (.i1(i1_1), .i2(i1_2), .o(o1)); 138 | cxor x2 (.i1(i2_1), .i2(i2_2), .o(o2)); 139 | 140 | endmodule 141 | 142 | 143 | 144 | 145 | module cxor ( 146 | input [7:0] i1, 147 | input [7:0] i2, 148 | 149 | output [7:0] o 150 | ); 151 | 152 | assign o = i1 ^ i2; 153 | 154 | endmodule 155 | -------------------------------------------------------------------------------- /aes_hw/aes_3/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input clk, 3 | input resetn, 4 | 5 | input [159:0] index, 6 | input enable, 7 | 8 | output reg [159:0] sbout, 9 | output done 10 | ); 11 | 12 | reg [7:0] p; 13 | wire [7:0] p_next; 14 | 15 | reg [7:0] q; 16 | wire [7:0] q_next; 17 | 18 | wire [7:0] aff; 19 | 20 | reg [19:0] complete; 21 | 22 | genvar i; 23 | 24 | 25 | always @(posedge clk) begin 26 | if(!resetn) begin 27 | p <= 8'h1; 28 | q <= 8'h1; 29 | end 30 | else if(!enable) begin 31 | p <= 8'h1; 32 | q <= 8'h1; 33 | end 34 | else begin 35 | p <= p_next; 36 | q <= q_next; 37 | end 38 | end 39 | 40 | /* Multiply by 03 in Galois Field GF(256) 41 | * p = p ^ (p<<1) ^ (p & 0x80 ? 0x1b : 0x00); 42 | * */ 43 | assign p_next = {p[7]^p[6], p[6]^p[5], p[5]^p[4], p[4]^p[3]^p[7], p[3]^p[2]^p[7], p[2]^p[1], p[1]^p[0]^p[7], p[0]^p[7]}; 44 | 45 | /* Inverse of p in Galois Field GF(256) 46 | * q ^= q<<1; 47 | * q ^= q<<2; 48 | * q ^= q<<4; 49 | * q ^= q & 0x80 ? 0x09 : 0x00; 50 | * */ 51 | assign q_next[0] = q[0] ^ q_next[7]; 52 | assign q_next[1] = q[1] ^ q[0]; 53 | assign q_next[2] = q[2] ^ q_next[1]; 54 | assign q_next[3] = q[7] ^ q[6] ^ q[5] ^ q[4]; 55 | assign q_next[4] = q[4] ^ q[3] ^ q_next[2]; 56 | assign q_next[5] = q[5] ^ q_next[4]; 57 | assign q_next[6] = q[6] ^ q_next[5]; 58 | assign q_next[7] = q[7] ^ q_next[6]; 59 | 60 | 61 | /* Compute Affine Transformation 62 | * b'(i) = b(i) ^ b(i+4 % 8) ^ b(i+5 % 8) ^ b(i+6 % 8) ^ b(i+7 % 8) ^ c(i); 63 | * c = 0x63; 64 | */ 65 | assign aff[0] = ~(q[0] ^ q_next[3]); //q[0] ^ q[4] ^ q[5] ^ q[6] ^ q[7] ^ 1'b1; 66 | assign aff[1] = ~(q_next[1] ^ q_next[3] ^ q[4]); //q[1] ^ q[5] ^ q[6] ^ q[7] ^ q[0] ^ 1'b1; 67 | assign aff[2] = q_next[2] ^ q[6] ^ q[7]; //q[2] ^ q[6] ^ q[7] ^ q[0] ^ q[1] ^ 1'b0; 68 | assign aff[3] = q_next[4] ^ q[4] ^ q[7]; //q[3] ^ q[7] ^ q[0] ^ q[1] ^ q[2] ^ 1'b0; 69 | assign aff[4] = q_next[4]; //q[4] ^ q[0] ^ q[1] ^ q[2] ^ q[3] ^ 1'b0; 70 | assign aff[5] = ~(q_next[5] ^ q[0]); //q[5] ^ q[1] ^ q[2] ^ q[3] ^ q[4] ^ 1'b1; 71 | assign aff[6] = ~(q_next[6] ^ q_next[1]); //q[6] ^ q[2] ^ q[3] ^ q[4] ^ q[5] ^ 1'b1; 72 | assign aff[7] = q_next[7] ^ q_next[2]; //q[7] ^ q[3] ^ q[4] ^ q[5] ^ q[6] ^ 1'b0; 73 | 74 | 75 | generate 76 | for(i = 0; i < 20; i = i+1) begin : sbox_sample 77 | always @(enable or aff or index or p) begin 78 | if(enable) begin 79 | if(index[8*i+7:8*i] == 8'h0) begin 80 | complete[i] = 1'b1; 81 | end 82 | else if(index[8*i+7:8*i] == p) begin 83 | sbout[8*i+7:8*i] = aff; 84 | complete[i] = 1'b1; 85 | end 86 | end 87 | else begin 88 | sbout[8*i+7:8*i] = 8'h63; 89 | complete[i] = 1'b0; 90 | end 91 | end 92 | end 93 | 94 | endgenerate 95 | 96 | 97 | assign done = &(complete[19:0]); 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /aes_hw/aes_3/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_3/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #160; 38 | //enable = 1'b0; 39 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 40 | //enable = 1'b1; 41 | #9000; 42 | $finish; 43 | end 44 | 45 | 46 | always @(posedge clk) begin 47 | if(!resetn) begin 48 | ecounter <= 4'h0; 49 | end 50 | else begin 51 | ecounter <= ecounter_next; 52 | end 53 | end 54 | 55 | //Multiple rounds - 10 for 128bit encryption. 56 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 57 | ecounter_next = ecounter; //Keep the same state. 58 | enable = 1'b0; 59 | round = 4'h0; 60 | i_text = 128'h0; 61 | 62 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 63 | if(plain_text_complete) begin 64 | if(done) begin 65 | ecounter_next = 4'h1; 66 | end 67 | enable = 1'b1; 68 | round = 4'h0; 69 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 70 | end 71 | end 72 | else begin 73 | if(done) begin 74 | ecounter_next = ecounter + 4'h1; 75 | end 76 | enable = 1'b1; 77 | round = ecounter; 78 | i_text = o_text; 79 | end 80 | end 81 | 82 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /aes_hw/aes_4/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_4/T0.hex: -------------------------------------------------------------------------------- 1 | a56363c6 2 | 847c7cf8 3 | 997777ee 4 | 8d7b7bf6 5 | 0df2f2ff 6 | bd6b6bd6 7 | b16f6fde 8 | 54c5c591 9 | 50303060 10 | 03010102 11 | a96767ce 12 | 7d2b2b56 13 | 19fefee7 14 | 62d7d7b5 15 | e6abab4d 16 | 9a7676ec 17 | 45caca8f 18 | 9d82821f 19 | 40c9c989 20 | 877d7dfa 21 | 15fafaef 22 | eb5959b2 23 | c947478e 24 | 0bf0f0fb 25 | ecadad41 26 | 67d4d4b3 27 | fda2a25f 28 | eaafaf45 29 | bf9c9c23 30 | f7a4a453 31 | 967272e4 32 | 5bc0c09b 33 | c2b7b775 34 | 1cfdfde1 35 | ae93933d 36 | 6a26264c 37 | 5a36366c 38 | 413f3f7e 39 | 02f7f7f5 40 | 4fcccc83 41 | 5c343468 42 | f4a5a551 43 | 34e5e5d1 44 | 08f1f1f9 45 | 937171e2 46 | 73d8d8ab 47 | 53313162 48 | 3f15152a 49 | 0c040408 50 | 52c7c795 51 | 65232346 52 | 5ec3c39d 53 | 28181830 54 | a1969637 55 | 0f05050a 56 | b59a9a2f 57 | 0907070e 58 | 36121224 59 | 9b80801b 60 | 3de2e2df 61 | 26ebebcd 62 | 6927274e 63 | cdb2b27f 64 | 9f7575ea 65 | 1b090912 66 | 9e83831d 67 | 742c2c58 68 | 2e1a1a34 69 | 2d1b1b36 70 | b26e6edc 71 | ee5a5ab4 72 | fba0a05b 73 | f65252a4 74 | 4d3b3b76 75 | 61d6d6b7 76 | ceb3b37d 77 | 7b292952 78 | 3ee3e3dd 79 | 712f2f5e 80 | 97848413 81 | f55353a6 82 | 68d1d1b9 83 | 00000000 84 | 2cededc1 85 | 60202040 86 | 1ffcfce3 87 | c8b1b179 88 | ed5b5bb6 89 | be6a6ad4 90 | 46cbcb8d 91 | d9bebe67 92 | 4b393972 93 | de4a4a94 94 | d44c4c98 95 | e85858b0 96 | 4acfcf85 97 | 6bd0d0bb 98 | 2aefefc5 99 | e5aaaa4f 100 | 16fbfbed 101 | c5434386 102 | d74d4d9a 103 | 55333366 104 | 94858511 105 | cf45458a 106 | 10f9f9e9 107 | 06020204 108 | 817f7ffe 109 | f05050a0 110 | 443c3c78 111 | ba9f9f25 112 | e3a8a84b 113 | f35151a2 114 | fea3a35d 115 | c0404080 116 | 8a8f8f05 117 | ad92923f 118 | bc9d9d21 119 | 48383870 120 | 04f5f5f1 121 | dfbcbc63 122 | c1b6b677 123 | 75dadaaf 124 | 63212142 125 | 30101020 126 | 1affffe5 127 | 0ef3f3fd 128 | 6dd2d2bf 129 | 4ccdcd81 130 | 140c0c18 131 | 35131326 132 | 2fececc3 133 | e15f5fbe 134 | a2979735 135 | cc444488 136 | 3917172e 137 | 57c4c493 138 | f2a7a755 139 | 827e7efc 140 | 473d3d7a 141 | ac6464c8 142 | e75d5dba 143 | 2b191932 144 | 957373e6 145 | a06060c0 146 | 98818119 147 | d14f4f9e 148 | 7fdcdca3 149 | 66222244 150 | 7e2a2a54 151 | ab90903b 152 | 8388880b 153 | ca46468c 154 | 29eeeec7 155 | d3b8b86b 156 | 3c141428 157 | 79dedea7 158 | e25e5ebc 159 | 1d0b0b16 160 | 76dbdbad 161 | 3be0e0db 162 | 56323264 163 | 4e3a3a74 164 | 1e0a0a14 165 | db494992 166 | 0a06060c 167 | 6c242448 168 | e45c5cb8 169 | 5dc2c29f 170 | 6ed3d3bd 171 | efacac43 172 | a66262c4 173 | a8919139 174 | a4959531 175 | 37e4e4d3 176 | 8b7979f2 177 | 32e7e7d5 178 | 43c8c88b 179 | 5937376e 180 | b76d6dda 181 | 8c8d8d01 182 | 64d5d5b1 183 | d24e4e9c 184 | e0a9a949 185 | b46c6cd8 186 | fa5656ac 187 | 07f4f4f3 188 | 25eaeacf 189 | af6565ca 190 | 8e7a7af4 191 | e9aeae47 192 | 18080810 193 | d5baba6f 194 | 887878f0 195 | 6f25254a 196 | 722e2e5c 197 | 241c1c38 198 | f1a6a657 199 | c7b4b473 200 | 51c6c697 201 | 23e8e8cb 202 | 7cdddda1 203 | 9c7474e8 204 | 211f1f3e 205 | dd4b4b96 206 | dcbdbd61 207 | 868b8b0d 208 | 858a8a0f 209 | 907070e0 210 | 423e3e7c 211 | c4b5b571 212 | aa6666cc 213 | d8484890 214 | 05030306 215 | 01f6f6f7 216 | 120e0e1c 217 | a36161c2 218 | 5f35356a 219 | f95757ae 220 | d0b9b969 221 | 91868617 222 | 58c1c199 223 | 271d1d3a 224 | b99e9e27 225 | 38e1e1d9 226 | 13f8f8eb 227 | b398982b 228 | 33111122 229 | bb6969d2 230 | 70d9d9a9 231 | 898e8e07 232 | a7949433 233 | b69b9b2d 234 | 221e1e3c 235 | 92878715 236 | 20e9e9c9 237 | 49cece87 238 | ff5555aa 239 | 78282850 240 | 7adfdfa5 241 | 8f8c8c03 242 | f8a1a159 243 | 80898909 244 | 170d0d1a 245 | dabfbf65 246 | 31e6e6d7 247 | c6424284 248 | b86868d0 249 | c3414182 250 | b0999929 251 | 772d2d5a 252 | 110f0f1e 253 | cbb0b07b 254 | fc5454a8 255 | d6bbbb6d 256 | 3a16162c 257 | -------------------------------------------------------------------------------- /aes_hw/aes_4/T1.hex: -------------------------------------------------------------------------------- 1 | 6363c6a5 2 | 7c7cf884 3 | 7777ee99 4 | 7b7bf68d 5 | f2f2ff0d 6 | 6b6bd6bd 7 | 6f6fdeb1 8 | c5c59154 9 | 30306050 10 | 01010203 11 | 6767cea9 12 | 2b2b567d 13 | fefee719 14 | d7d7b562 15 | abab4de6 16 | 7676ec9a 17 | caca8f45 18 | 82821f9d 19 | c9c98940 20 | 7d7dfa87 21 | fafaef15 22 | 5959b2eb 23 | 47478ec9 24 | f0f0fb0b 25 | adad41ec 26 | d4d4b367 27 | a2a25ffd 28 | afaf45ea 29 | 9c9c23bf 30 | a4a453f7 31 | 7272e496 32 | c0c09b5b 33 | b7b775c2 34 | fdfde11c 35 | 93933dae 36 | 26264c6a 37 | 36366c5a 38 | 3f3f7e41 39 | f7f7f502 40 | cccc834f 41 | 3434685c 42 | a5a551f4 43 | e5e5d134 44 | f1f1f908 45 | 7171e293 46 | d8d8ab73 47 | 31316253 48 | 15152a3f 49 | 0404080c 50 | c7c79552 51 | 23234665 52 | c3c39d5e 53 | 18183028 54 | 969637a1 55 | 05050a0f 56 | 9a9a2fb5 57 | 07070e09 58 | 12122436 59 | 80801b9b 60 | e2e2df3d 61 | ebebcd26 62 | 27274e69 63 | b2b27fcd 64 | 7575ea9f 65 | 0909121b 66 | 83831d9e 67 | 2c2c5874 68 | 1a1a342e 69 | 1b1b362d 70 | 6e6edcb2 71 | 5a5ab4ee 72 | a0a05bfb 73 | 5252a4f6 74 | 3b3b764d 75 | d6d6b761 76 | b3b37dce 77 | 2929527b 78 | e3e3dd3e 79 | 2f2f5e71 80 | 84841397 81 | 5353a6f5 82 | d1d1b968 83 | 00000000 84 | ededc12c 85 | 20204060 86 | fcfce31f 87 | b1b179c8 88 | 5b5bb6ed 89 | 6a6ad4be 90 | cbcb8d46 91 | bebe67d9 92 | 3939724b 93 | 4a4a94de 94 | 4c4c98d4 95 | 5858b0e8 96 | cfcf854a 97 | d0d0bb6b 98 | efefc52a 99 | aaaa4fe5 100 | fbfbed16 101 | 434386c5 102 | 4d4d9ad7 103 | 33336655 104 | 85851194 105 | 45458acf 106 | f9f9e910 107 | 02020406 108 | 7f7ffe81 109 | 5050a0f0 110 | 3c3c7844 111 | 9f9f25ba 112 | a8a84be3 113 | 5151a2f3 114 | a3a35dfe 115 | 404080c0 116 | 8f8f058a 117 | 92923fad 118 | 9d9d21bc 119 | 38387048 120 | f5f5f104 121 | bcbc63df 122 | b6b677c1 123 | dadaaf75 124 | 21214263 125 | 10102030 126 | ffffe51a 127 | f3f3fd0e 128 | d2d2bf6d 129 | cdcd814c 130 | 0c0c1814 131 | 13132635 132 | ececc32f 133 | 5f5fbee1 134 | 979735a2 135 | 444488cc 136 | 17172e39 137 | c4c49357 138 | a7a755f2 139 | 7e7efc82 140 | 3d3d7a47 141 | 6464c8ac 142 | 5d5dbae7 143 | 1919322b 144 | 7373e695 145 | 6060c0a0 146 | 81811998 147 | 4f4f9ed1 148 | dcdca37f 149 | 22224466 150 | 2a2a547e 151 | 90903bab 152 | 88880b83 153 | 46468cca 154 | eeeec729 155 | b8b86bd3 156 | 1414283c 157 | dedea779 158 | 5e5ebce2 159 | 0b0b161d 160 | dbdbad76 161 | e0e0db3b 162 | 32326456 163 | 3a3a744e 164 | 0a0a141e 165 | 494992db 166 | 06060c0a 167 | 2424486c 168 | 5c5cb8e4 169 | c2c29f5d 170 | d3d3bd6e 171 | acac43ef 172 | 6262c4a6 173 | 919139a8 174 | 959531a4 175 | e4e4d337 176 | 7979f28b 177 | e7e7d532 178 | c8c88b43 179 | 37376e59 180 | 6d6ddab7 181 | 8d8d018c 182 | d5d5b164 183 | 4e4e9cd2 184 | a9a949e0 185 | 6c6cd8b4 186 | 5656acfa 187 | f4f4f307 188 | eaeacf25 189 | 6565caaf 190 | 7a7af48e 191 | aeae47e9 192 | 08081018 193 | baba6fd5 194 | 7878f088 195 | 25254a6f 196 | 2e2e5c72 197 | 1c1c3824 198 | a6a657f1 199 | b4b473c7 200 | c6c69751 201 | e8e8cb23 202 | dddda17c 203 | 7474e89c 204 | 1f1f3e21 205 | 4b4b96dd 206 | bdbd61dc 207 | 8b8b0d86 208 | 8a8a0f85 209 | 7070e090 210 | 3e3e7c42 211 | b5b571c4 212 | 6666ccaa 213 | 484890d8 214 | 03030605 215 | f6f6f701 216 | 0e0e1c12 217 | 6161c2a3 218 | 35356a5f 219 | 5757aef9 220 | b9b969d0 221 | 86861791 222 | c1c19958 223 | 1d1d3a27 224 | 9e9e27b9 225 | e1e1d938 226 | f8f8eb13 227 | 98982bb3 228 | 11112233 229 | 6969d2bb 230 | d9d9a970 231 | 8e8e0789 232 | 949433a7 233 | 9b9b2db6 234 | 1e1e3c22 235 | 87871592 236 | e9e9c920 237 | cece8749 238 | 5555aaff 239 | 28285078 240 | dfdfa57a 241 | 8c8c038f 242 | a1a159f8 243 | 89890980 244 | 0d0d1a17 245 | bfbf65da 246 | e6e6d731 247 | 424284c6 248 | 6868d0b8 249 | 414182c3 250 | 999929b0 251 | 2d2d5a77 252 | 0f0f1e11 253 | b0b07bcb 254 | 5454a8fc 255 | bbbb6dd6 256 | 16162c3a 257 | -------------------------------------------------------------------------------- /aes_hw/aes_4/T2.hex: -------------------------------------------------------------------------------- 1 | 63c6a563 2 | 7cf8847c 3 | 77ee9977 4 | 7bf68d7b 5 | f2ff0df2 6 | 6bd6bd6b 7 | 6fdeb16f 8 | c59154c5 9 | 30605030 10 | 01020301 11 | 67cea967 12 | 2b567d2b 13 | fee719fe 14 | d7b562d7 15 | ab4de6ab 16 | 76ec9a76 17 | ca8f45ca 18 | 821f9d82 19 | c98940c9 20 | 7dfa877d 21 | faef15fa 22 | 59b2eb59 23 | 478ec947 24 | f0fb0bf0 25 | ad41ecad 26 | d4b367d4 27 | a25ffda2 28 | af45eaaf 29 | 9c23bf9c 30 | a453f7a4 31 | 72e49672 32 | c09b5bc0 33 | b775c2b7 34 | fde11cfd 35 | 933dae93 36 | 264c6a26 37 | 366c5a36 38 | 3f7e413f 39 | f7f502f7 40 | cc834fcc 41 | 34685c34 42 | a551f4a5 43 | e5d134e5 44 | f1f908f1 45 | 71e29371 46 | d8ab73d8 47 | 31625331 48 | 152a3f15 49 | 04080c04 50 | c79552c7 51 | 23466523 52 | c39d5ec3 53 | 18302818 54 | 9637a196 55 | 050a0f05 56 | 9a2fb59a 57 | 070e0907 58 | 12243612 59 | 801b9b80 60 | e2df3de2 61 | ebcd26eb 62 | 274e6927 63 | b27fcdb2 64 | 75ea9f75 65 | 09121b09 66 | 831d9e83 67 | 2c58742c 68 | 1a342e1a 69 | 1b362d1b 70 | 6edcb26e 71 | 5ab4ee5a 72 | a05bfba0 73 | 52a4f652 74 | 3b764d3b 75 | d6b761d6 76 | b37dceb3 77 | 29527b29 78 | e3dd3ee3 79 | 2f5e712f 80 | 84139784 81 | 53a6f553 82 | d1b968d1 83 | 00000000 84 | edc12ced 85 | 20406020 86 | fce31ffc 87 | b179c8b1 88 | 5bb6ed5b 89 | 6ad4be6a 90 | cb8d46cb 91 | be67d9be 92 | 39724b39 93 | 4a94de4a 94 | 4c98d44c 95 | 58b0e858 96 | cf854acf 97 | d0bb6bd0 98 | efc52aef 99 | aa4fe5aa 100 | fbed16fb 101 | 4386c543 102 | 4d9ad74d 103 | 33665533 104 | 85119485 105 | 458acf45 106 | f9e910f9 107 | 02040602 108 | 7ffe817f 109 | 50a0f050 110 | 3c78443c 111 | 9f25ba9f 112 | a84be3a8 113 | 51a2f351 114 | a35dfea3 115 | 4080c040 116 | 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183 | 4e9cd24e 184 | a949e0a9 185 | 6cd8b46c 186 | 56acfa56 187 | f4f307f4 188 | eacf25ea 189 | 65caaf65 190 | 7af48e7a 191 | ae47e9ae 192 | 08101808 193 | ba6fd5ba 194 | 78f08878 195 | 254a6f25 196 | 2e5c722e 197 | 1c38241c 198 | a657f1a6 199 | b473c7b4 200 | c69751c6 201 | e8cb23e8 202 | dda17cdd 203 | 74e89c74 204 | 1f3e211f 205 | 4b96dd4b 206 | bd61dcbd 207 | 8b0d868b 208 | 8a0f858a 209 | 70e09070 210 | 3e7c423e 211 | b571c4b5 212 | 66ccaa66 213 | 4890d848 214 | 03060503 215 | f6f701f6 216 | 0e1c120e 217 | 61c2a361 218 | 356a5f35 219 | 57aef957 220 | b969d0b9 221 | 86179186 222 | c19958c1 223 | 1d3a271d 224 | 9e27b99e 225 | e1d938e1 226 | f8eb13f8 227 | 982bb398 228 | 11223311 229 | 69d2bb69 230 | d9a970d9 231 | 8e07898e 232 | 9433a794 233 | 9b2db69b 234 | 1e3c221e 235 | 87159287 236 | e9c920e9 237 | ce8749ce 238 | 55aaff55 239 | 28507828 240 | dfa57adf 241 | 8c038f8c 242 | a159f8a1 243 | 89098089 244 | 0d1a170d 245 | bf65dabf 246 | e6d731e6 247 | 4284c642 248 | 68d0b868 249 | 4182c341 250 | 9929b099 251 | 2d5a772d 252 | 0f1e110f 253 | b07bcbb0 254 | 54a8fc54 255 | bb6dd6bb 256 | 162c3a16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_4/T3.hex: -------------------------------------------------------------------------------- 1 | c6a56363 2 | f8847c7c 3 | ee997777 4 | f68d7b7b 5 | ff0df2f2 6 | d6bd6b6b 7 | deb16f6f 8 | 9154c5c5 9 | 60503030 10 | 02030101 11 | cea96767 12 | 567d2b2b 13 | e719fefe 14 | b562d7d7 15 | 4de6abab 16 | ec9a7676 17 | 8f45caca 18 | 1f9d8282 19 | 8940c9c9 20 | fa877d7d 21 | ef15fafa 22 | b2eb5959 23 | 8ec94747 24 | fb0bf0f0 25 | 41ecadad 26 | b367d4d4 27 | 5ffda2a2 28 | 45eaafaf 29 | 23bf9c9c 30 | 53f7a4a4 31 | e4967272 32 | 9b5bc0c0 33 | 75c2b7b7 34 | e11cfdfd 35 | 3dae9393 36 | 4c6a2626 37 | 6c5a3636 38 | 7e413f3f 39 | f502f7f7 40 | 834fcccc 41 | 685c3434 42 | 51f4a5a5 43 | d134e5e5 44 | f908f1f1 45 | e2937171 46 | ab73d8d8 47 | 62533131 48 | 2a3f1515 49 | 080c0404 50 | 9552c7c7 51 | 46652323 52 | 9d5ec3c3 53 | 30281818 54 | 37a19696 55 | 0a0f0505 56 | 2fb59a9a 57 | 0e090707 58 | 24361212 59 | 1b9b8080 60 | df3de2e2 61 | cd26ebeb 62 | 4e692727 63 | 7fcdb2b2 64 | ea9f7575 65 | 121b0909 66 | 1d9e8383 67 | 58742c2c 68 | 342e1a1a 69 | 362d1b1b 70 | dcb26e6e 71 | b4ee5a5a 72 | 5bfba0a0 73 | a4f65252 74 | 764d3b3b 75 | b761d6d6 76 | 7dceb3b3 77 | 527b2929 78 | dd3ee3e3 79 | 5e712f2f 80 | 13978484 81 | a6f55353 82 | b968d1d1 83 | 00000000 84 | c12ceded 85 | 40602020 86 | e31ffcfc 87 | 79c8b1b1 88 | b6ed5b5b 89 | d4be6a6a 90 | 8d46cbcb 91 | 67d9bebe 92 | 724b3939 93 | 94de4a4a 94 | 98d44c4c 95 | b0e85858 96 | 854acfcf 97 | bb6bd0d0 98 | c52aefef 99 | 4fe5aaaa 100 | ed16fbfb 101 | 86c54343 102 | 9ad74d4d 103 | 66553333 104 | 11948585 105 | 8acf4545 106 | e910f9f9 107 | 04060202 108 | fe817f7f 109 | a0f05050 110 | 78443c3c 111 | 25ba9f9f 112 | 4be3a8a8 113 | a2f35151 114 | 5dfea3a3 115 | 80c04040 116 | 058a8f8f 117 | 3fad9292 118 | 21bc9d9d 119 | 70483838 120 | f104f5f5 121 | 63dfbcbc 122 | 77c1b6b6 123 | af75dada 124 | 42632121 125 | 20301010 126 | e51affff 127 | fd0ef3f3 128 | bf6dd2d2 129 | 814ccdcd 130 | 18140c0c 131 | 26351313 132 | c32fecec 133 | bee15f5f 134 | 35a29797 135 | 88cc4444 136 | 2e391717 137 | 9357c4c4 138 | 55f2a7a7 139 | fc827e7e 140 | 7a473d3d 141 | c8ac6464 142 | bae75d5d 143 | 322b1919 144 | e6957373 145 | c0a06060 146 | 19988181 147 | 9ed14f4f 148 | a37fdcdc 149 | 44662222 150 | 547e2a2a 151 | 3bab9090 152 | 0b838888 153 | 8cca4646 154 | c729eeee 155 | 6bd3b8b8 156 | 283c1414 157 | a779dede 158 | bce25e5e 159 | 161d0b0b 160 | ad76dbdb 161 | db3be0e0 162 | 64563232 163 | 744e3a3a 164 | 141e0a0a 165 | 92db4949 166 | 0c0a0606 167 | 486c2424 168 | b8e45c5c 169 | 9f5dc2c2 170 | bd6ed3d3 171 | 43efacac 172 | c4a66262 173 | 39a89191 174 | 31a49595 175 | d337e4e4 176 | f28b7979 177 | d532e7e7 178 | 8b43c8c8 179 | 6e593737 180 | dab76d6d 181 | 018c8d8d 182 | b164d5d5 183 | 9cd24e4e 184 | 49e0a9a9 185 | d8b46c6c 186 | acfa5656 187 | f307f4f4 188 | cf25eaea 189 | caaf6565 190 | f48e7a7a 191 | 47e9aeae 192 | 10180808 193 | 6fd5baba 194 | f0887878 195 | 4a6f2525 196 | 5c722e2e 197 | 38241c1c 198 | 57f1a6a6 199 | 73c7b4b4 200 | 9751c6c6 201 | cb23e8e8 202 | a17cdddd 203 | e89c7474 204 | 3e211f1f 205 | 96dd4b4b 206 | 61dcbdbd 207 | 0d868b8b 208 | 0f858a8a 209 | e0907070 210 | 7c423e3e 211 | 71c4b5b5 212 | ccaa6666 213 | 90d84848 214 | 06050303 215 | f701f6f6 216 | 1c120e0e 217 | c2a36161 218 | 6a5f3535 219 | aef95757 220 | 69d0b9b9 221 | 17918686 222 | 9958c1c1 223 | 3a271d1d 224 | 27b99e9e 225 | d938e1e1 226 | eb13f8f8 227 | 2bb39898 228 | 22331111 229 | d2bb6969 230 | a970d9d9 231 | 07898e8e 232 | 33a79494 233 | 2db69b9b 234 | 3c221e1e 235 | 15928787 236 | c920e9e9 237 | 8749cece 238 | aaff5555 239 | 50782828 240 | a57adfdf 241 | 038f8c8c 242 | 59f8a1a1 243 | 09808989 244 | 1a170d0d 245 | 65dabfbf 246 | d731e6e6 247 | 84c64242 248 | d0b86868 249 | 82c34141 250 | 29b09999 251 | 5a772d2d 252 | 1e110f0f 253 | 7bcbb0b0 254 | a8fc5454 255 | 6dd6bbbb 256 | 2c3a1616 257 | -------------------------------------------------------------------------------- /aes_hw/aes_4/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | input [127:0] i_text, 7 | input [127:0] key, 8 | input [3:0] round, 9 | 10 | output reg [127:0] o_text, 11 | output reg [127:0] Rkey, 12 | output done 13 | ); 14 | 15 | wire [127:0] roundkey_text; 16 | wire [127:0] shiftrows_text; 17 | reg [127:0] mixcolumns_text; 18 | 19 | wire [127:0] okey; 20 | reg [31:0] tkey; 21 | 22 | reg [7:0] Rcon[0:9]; //Round Constant 23 | 24 | reg [2:0] counter; 25 | reg [2:0] counter_next; 26 | 27 | reg [7:0] t0_in; 28 | reg [7:0] t1_in; 29 | reg [7:0] t2_in; 30 | reg [7:0] t3_in; 31 | 32 | wire [31:0] t0_out; 33 | wire [31:0] t1_out; 34 | wire [31:0] t2_out; 35 | wire [31:0] t3_out; 36 | 37 | 38 | initial begin 39 | Rcon[0] = 8'h01; 40 | Rcon[1] = 8'h02; 41 | Rcon[2] = 8'h04; 42 | Rcon[3] = 8'h08; 43 | Rcon[4] = 8'h10; 44 | Rcon[5] = 8'h20; 45 | Rcon[6] = 8'h40; 46 | Rcon[7] = 8'h80; 47 | Rcon[8] = 8'h1b; 48 | Rcon[9] = 8'h36; 49 | end 50 | 51 | 52 | 53 | always @(posedge clock) begin 54 | if(!resetn) begin 55 | counter <= 3'h0; 56 | end 57 | else begin 58 | counter <= counter_next; 59 | end 60 | end 61 | 62 | 63 | 64 | 65 | //Shift Rows for Encryption 66 | shiftrows U2 (.istate(i_text), .ostate(shiftrows_text)); 67 | 68 | 69 | //TBOX (SBOX) lookup for Encryption 70 | always @(counter or enable or shiftrows_text or key or round or t0_out or t1_out or t2_out or t3_out) begin 71 | 72 | if((counter == 3'h0)) begin 73 | if(enable) begin 74 | t0_in = shiftrows_text[7:0]; 75 | t1_in = shiftrows_text[15:8]; 76 | t2_in = shiftrows_text[23:16]; 77 | t3_in = shiftrows_text[31:24]; 78 | if(round == 4'h9) begin 79 | mixcolumns_text[31:0] = {t3_out[7:0], t2_out[7:0], t1_out[23:16], t0_out[23:16]}; 80 | end 81 | else begin 82 | mixcolumns_text[31:0] = t0_out ^ t1_out ^ t2_out ^ t3_out; 83 | end 84 | counter_next = counter + 3'h1; 85 | end 86 | else begin 87 | t0_in = 32'h0; 88 | t1_in = 32'h0; 89 | t2_in = 32'h0; 90 | t3_in = 32'h0; 91 | mixcolumns_text = 128'h0; 92 | tkey = 32'h0; 93 | counter_next = 3'h0; 94 | end 95 | end 96 | else if((counter == 3'h1)) begin 97 | t0_in = shiftrows_text[39:32]; 98 | t1_in = shiftrows_text[47:40]; 99 | t2_in = shiftrows_text[55:48]; 100 | t3_in = shiftrows_text[63:56]; 101 | if(round == 4'h9) begin 102 | mixcolumns_text[63:32] = {t3_out[7:0], t2_out[7:0], t1_out[23:16], t0_out[23:16]}; 103 | end 104 | else begin 105 | mixcolumns_text[63:32] = t0_out ^ t1_out ^ t2_out ^ t3_out; 106 | end 107 | counter_next = counter + 3'h1; 108 | end 109 | else if((counter == 3'h2)) begin 110 | t0_in = shiftrows_text[71:64]; 111 | t1_in = shiftrows_text[79:72]; 112 | t2_in = shiftrows_text[87:80]; 113 | t3_in = shiftrows_text[95:88]; 114 | if(round == 4'h9) begin 115 | mixcolumns_text[95:64] = {t3_out[7:0], t2_out[7:0], t1_out[23:16], t0_out[23:16]}; 116 | end 117 | else begin 118 | mixcolumns_text[95:64] = t0_out ^ t1_out ^ t2_out ^ t3_out; 119 | end 120 | counter_next = counter + 3'h1; 121 | end 122 | else if((counter == 3'h3)) begin 123 | t0_in = shiftrows_text[103:96]; 124 | t1_in = shiftrows_text[111:104]; 125 | t2_in = shiftrows_text[119:112]; 126 | t3_in = shiftrows_text[127:120]; 127 | if(round == 4'h9) begin 128 | mixcolumns_text[127:96] = {t3_out[7:0], t2_out[7:0], t1_out[23:16], t0_out[23:16]}; 129 | end 130 | else begin 131 | mixcolumns_text[127:96] = t0_out ^ t1_out ^ t2_out ^ t3_out; 132 | end 133 | counter_next = counter + 3'h1; 134 | end 135 | else if((counter == 3'h4)) begin 136 | t0_in = key[111 : 104]; //8*13+7 : 8*13 137 | t1_in = key[119 : 112]; //8*14+7 : 8*14 138 | t2_in = key[127 : 120]; //8*15+7 : 8*15 139 | t3_in = key[103 : 96]; //8*12+7 : 8*12 140 | 141 | 142 | tkey[7 : 0] = t0_out[23:16] ^ key[7 : 0] ^ Rcon[round]; 143 | tkey[15 : 8] = t1_out[23:16] ^ key[15 : 8]; 144 | tkey[23 : 16] = t2_out[7:0] ^ key[23 : 16]; 145 | tkey[31 : 24] = t3_out[7:0] ^ key[31 : 24]; 146 | counter_next = 3'h0; 147 | end 148 | end 149 | 150 | 151 | //Key Expansion for Encryption 152 | assign okey[31:0] = tkey[31:0]; 153 | assign okey[127:32] = key[127:32] ^ okey[95:0]; 154 | 155 | //Add Roundkey for Encryption 156 | assign roundkey_text = mixcolumns_text ^ okey; 157 | 158 | //TBOX (SBOX) lookup 159 | tbox0 T0 (.index(t0_in), .tbox(t0_out)); 160 | tbox1 T1 (.index(t1_in), .tbox(t1_out)); 161 | tbox2 T2 (.index(t2_in), .tbox(t2_out)); 162 | tbox3 T3 (.index(t3_in), .tbox(t3_out)); 163 | 164 | assign done = (counter == 3'h4) ? 1'b1 : 1'b0; 165 | 166 | always @(posedge clock) begin 167 | if(!resetn) begin 168 | o_text <= 128'h0; 169 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 170 | end 171 | else if(done & (round == 4'h9)) begin 172 | o_text <= roundkey_text; 173 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 174 | end 175 | else if(done) begin 176 | o_text <= roundkey_text; 177 | Rkey <= okey; 178 | end 179 | end 180 | 181 | 182 | endmodule 183 | -------------------------------------------------------------------------------- /aes_hw/aes_4/aes_slave_intf.v: -------------------------------------------------------------------------------- 1 | module aes_slave_intf ( 2 | input clock, 3 | input resetn, 4 | 5 | input chipselect, 6 | input [3:0] address, 7 | 8 | input read, 9 | output reg [31:0] readdata, 10 | 11 | input write, 12 | input [31:0] writedata, 13 | 14 | output waitrequest 15 | ); 16 | 17 | reg [127:0] plain_text; 18 | reg [127:0] cipher_text; 19 | 20 | 21 | wire plain_text_write; 22 | reg plain_text_complete; 23 | 24 | reg [1:0] icounter; 25 | 26 | reg [4:0] ecounter; 27 | reg [4:0] ecounter_next; 28 | 29 | reg enable; 30 | reg [127:0] i_text; 31 | wire [3:0] round; 32 | wire [127:0] o_text; 33 | wire [127:0] Rkey; 34 | 35 | wire done; 36 | 37 | wire cipher_text_read; 38 | reg [1:0] ocounter; 39 | reg cipher_available; 40 | wire cipher_status_read; 41 | 42 | 43 | 44 | assign plain_text_write = chipselect & write & (address == 4'h0); 45 | 46 | 47 | always @(posedge clock) begin 48 | if(!resetn) begin 49 | icounter <= 2'h0; 50 | end 51 | else if(plain_text_write) begin 52 | icounter <= icounter + 2'h1; 53 | end 54 | end 55 | 56 | 57 | always @(posedge clock) begin 58 | if(!resetn) begin 59 | plain_text <= 128'h0; 60 | plain_text_complete <= 1'b0; 61 | end 62 | else if((icounter == 2'h0) & plain_text_write) begin // & ~waitrequest 63 | plain_text <= {96'h0, writedata}; 64 | plain_text_complete <= 1'b0; 65 | end 66 | else if((icounter == 2'h1) & plain_text_write) begin // & ~waitrequest 67 | plain_text <= {plain_text[95:0], writedata}; 68 | end 69 | else if((icounter == 2'h2) & plain_text_write) begin // & ~waitrequest 70 | plain_text <= {plain_text[95:0], writedata}; 71 | end 72 | else if((icounter == 2'h3) & plain_text_write) begin // & ~waitrequest 73 | plain_text <= {plain_text[95:0], writedata}; 74 | plain_text_complete <= 1'b1; 75 | end 76 | else begin 77 | plain_text_complete <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | 83 | 84 | 85 | 86 | always @(posedge clock) begin 87 | if(!resetn) begin 88 | ecounter <= 5'h0; 89 | end 90 | else begin 91 | ecounter <= ecounter_next; 92 | end 93 | end 94 | 95 | //Multiple rounds - 10 for 128bit encryption. 96 | always @(ecounter or plain_text_complete or o_text or plain_text or Rkey or done) begin 97 | 98 | if( (ecounter == 5'h0) ) begin 99 | cipher_text = o_text; 100 | if(plain_text_complete) begin 101 | enable = 1'b1; 102 | i_text = plain_text ^ Rkey; 103 | ecounter_next = 5'h1; 104 | end 105 | else begin 106 | enable = 1'b0; 107 | i_text = 128'h0; 108 | ecounter_next = ecounter; 109 | end 110 | end 111 | else if( (ecounter == 5'h13) ) begin 112 | enable = 1'b0; 113 | if(done) begin 114 | ecounter_next = 5'h0; 115 | end 116 | end 117 | else if( (ecounter[0]) ) begin 118 | enable = 1'b0; 119 | if(done) begin 120 | ecounter_next = ecounter + 5'h1; 121 | end 122 | end 123 | else if( (!ecounter[0]) )begin 124 | enable = 1'b1; 125 | i_text = o_text; 126 | ecounter_next = ecounter + 5'h1; 127 | end 128 | 129 | end 130 | 131 | 132 | assign round = ecounter[4:1]; 133 | 134 | //Compute AES cipher for one round. 135 | aes aes0 ( 136 | .clock(clock), 137 | .resetn(resetn), 138 | 139 | .enable(enable), 140 | 141 | .i_text(i_text), 142 | .key(Rkey), 143 | .round(round), 144 | 145 | .o_text(o_text), 146 | .Rkey(Rkey), 147 | 148 | .done(done) 149 | ); 150 | 151 | 152 | 153 | always @(posedge clock) begin 154 | if(!resetn) begin 155 | cipher_available <= 1'b0; 156 | end 157 | else if((ecounter == 5'h13) & done) begin 158 | cipher_available <= 1'b1; 159 | end 160 | else if((ecounter == 5'h0) & plain_text_complete) begin 161 | cipher_available <= 1'b0; 162 | end 163 | end 164 | 165 | 166 | assign cipher_text_read = chipselect & read & (address == 4'h4); 167 | assign cipher_status_read = chipselect & read & (address == 4'h8); 168 | 169 | always @(posedge clock) begin 170 | if(!resetn) begin 171 | ocounter <= 2'h0; 172 | end 173 | else if(cipher_text_read & (~waitrequest)) begin 174 | ocounter <= ocounter + 2'h1; 175 | end 176 | end 177 | 178 | 179 | //Reading Out Cipher 180 | always @(ocounter or cipher_text_read or cipher_status_read or cipher_text or cipher_available) begin 181 | readdata = 32'h0; 182 | 183 | if(cipher_text_read) begin 184 | case(ocounter) 185 | 2'h0 : begin readdata = cipher_text[127:96]; end 186 | 2'h1 : begin readdata = cipher_text[95:64]; end 187 | 2'h2 : begin readdata = cipher_text[63:32]; end 188 | 2'h3 : begin readdata = cipher_text[31:0]; end 189 | endcase 190 | end 191 | 192 | else if(cipher_status_read) begin 193 | readdata = {31'h0, cipher_available}; 194 | end 195 | 196 | end 197 | 198 | assign waitrequest = cipher_text_read & (~cipher_available); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /aes_hw/aes_4/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_4/t0.v: -------------------------------------------------------------------------------- 1 | module tbox0 ( 2 | input [7:0] index, 3 | 4 | output [31:0] tbox 5 | ); 6 | 7 | reg [31:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("T0.hex", mem); 11 | end 12 | 13 | assign tbox = mem[index]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_4/t1.v: -------------------------------------------------------------------------------- 1 | module tbox1 ( 2 | input [7:0] index, 3 | 4 | output [31:0] tbox 5 | ); 6 | 7 | reg [31:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("T1.hex", mem); 11 | end 12 | 13 | assign tbox = mem[index]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_4/t2.v: -------------------------------------------------------------------------------- 1 | module tbox2 ( 2 | input [7:0] index, 3 | 4 | output [31:0] tbox 5 | ); 6 | 7 | reg [31:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("T2.hex", mem); 11 | end 12 | 13 | assign tbox = mem[index]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_4/t3.v: -------------------------------------------------------------------------------- 1 | module tbox3 ( 2 | input [7:0] index, 3 | 4 | output [31:0] tbox 5 | ); 6 | 7 | reg [31:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("T3.hex", mem); 11 | end 12 | 13 | assign tbox = mem[index]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_4/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #160; 38 | //enable = 1'b0; 39 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 40 | //enable = 1'b1; 41 | #9000; 42 | $finish; 43 | end 44 | 45 | 46 | always @(posedge clk) begin 47 | if(!resetn) begin 48 | ecounter <= 4'h0; 49 | end 50 | else begin 51 | ecounter <= ecounter_next; 52 | end 53 | end 54 | 55 | //Multiple rounds - 10 for 128bit encryption. 56 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 57 | ecounter_next = ecounter; //Keep the same state. 58 | enable = 1'b0; 59 | round = 4'h0; 60 | i_text = 128'h0; 61 | 62 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 63 | if(plain_text_complete) begin 64 | if(done) begin 65 | ecounter_next = 4'h1; 66 | end 67 | enable = 1'b1; 68 | round = 4'h0; 69 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 70 | end 71 | end 72 | else begin 73 | if(done) begin 74 | ecounter_next = ecounter + 4'h1; 75 | end 76 | enable = 1'b1; 77 | round = ecounter; 78 | i_text = o_text; 79 | end 80 | end 81 | 82 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /aes_hw/aes_5/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_5/T0.hex: -------------------------------------------------------------------------------- 1 | c663 2 | f87c 3 | ee77 4 | f67b 5 | fff2 6 | d66b 7 | de6f 8 | 91c5 9 | 6030 10 | 0201 11 | ce67 12 | 562b 13 | e7fe 14 | b5d7 15 | 4dab 16 | ec76 17 | 8fca 18 | 1f82 19 | 89c9 20 | fa7d 21 | effa 22 | b259 23 | 8e47 24 | fbf0 25 | 41ad 26 | b3d4 27 | 5fa2 28 | 45af 29 | 239c 30 | 53a4 31 | e472 32 | 9bc0 33 | 75b7 34 | e1fd 35 | 3d93 36 | 4c26 37 | 6c36 38 | 7e3f 39 | f5f7 40 | 83cc 41 | 6834 42 | 51a5 43 | d1e5 44 | f9f1 45 | e271 46 | abd8 47 | 6231 48 | 2a15 49 | 0804 50 | 95c7 51 | 4623 52 | 9dc3 53 | 3018 54 | 3796 55 | 0a05 56 | 2f9a 57 | 0e07 58 | 2412 59 | 1b80 60 | dfe2 61 | cdeb 62 | 4e27 63 | 7fb2 64 | ea75 65 | 1209 66 | 1d83 67 | 582c 68 | 341a 69 | 361b 70 | dc6e 71 | b45a 72 | 5ba0 73 | a452 74 | 763b 75 | b7d6 76 | 7db3 77 | 5229 78 | dde3 79 | 5e2f 80 | 1384 81 | a653 82 | b9d1 83 | 0000 84 | c1ed 85 | 4020 86 | e3fc 87 | 79b1 88 | b65b 89 | d46a 90 | 8dcb 91 | 67be 92 | 7239 93 | 944a 94 | 984c 95 | b058 96 | 85cf 97 | bbd0 98 | c5ef 99 | 4faa 100 | edfb 101 | 8643 102 | 9a4d 103 | 6633 104 | 1185 105 | 8a45 106 | e9f9 107 | 0402 108 | fe7f 109 | a050 110 | 783c 111 | 259f 112 | 4ba8 113 | a251 114 | 5da3 115 | 8040 116 | 058f 117 | 3f92 118 | 219d 119 | 7038 120 | f1f5 121 | 63bc 122 | 77b6 123 | afda 124 | 4221 125 | 2010 126 | e5ff 127 | fdf3 128 | bfd2 129 | 81cd 130 | 180c 131 | 2613 132 | c3ec 133 | be5f 134 | 3597 135 | 8844 136 | 2e17 137 | 93c4 138 | 55a7 139 | fc7e 140 | 7a3d 141 | c864 142 | ba5d 143 | 3219 144 | e673 145 | c060 146 | 1981 147 | 9e4f 148 | a3dc 149 | 4422 150 | 542a 151 | 3b90 152 | 0b88 153 | 8c46 154 | c7ee 155 | 6bb8 156 | 2814 157 | a7de 158 | bc5e 159 | 160b 160 | addb 161 | dbe0 162 | 6432 163 | 743a 164 | 140a 165 | 9249 166 | 0c06 167 | 4824 168 | b85c 169 | 9fc2 170 | bdd3 171 | 43ac 172 | c462 173 | 3991 174 | 3195 175 | d3e4 176 | f279 177 | d5e7 178 | 8bc8 179 | 6e37 180 | da6d 181 | 018d 182 | b1d5 183 | 9c4e 184 | 49a9 185 | d86c 186 | ac56 187 | f3f4 188 | cfea 189 | ca65 190 | f47a 191 | 47ae 192 | 1008 193 | 6fba 194 | f078 195 | 4a25 196 | 5c2e 197 | 381c 198 | 57a6 199 | 73b4 200 | 97c6 201 | cbe8 202 | a1dd 203 | e874 204 | 3e1f 205 | 964b 206 | 61bd 207 | 0d8b 208 | 0f8a 209 | e070 210 | 7c3e 211 | 71b5 212 | cc66 213 | 9048 214 | 0603 215 | f7f6 216 | 1c0e 217 | c261 218 | 6a35 219 | ae57 220 | 69b9 221 | 1786 222 | 99c1 223 | 3a1d 224 | 279e 225 | d9e1 226 | ebf8 227 | 2b98 228 | 2211 229 | d269 230 | a9d9 231 | 078e 232 | 3394 233 | 2d9b 234 | 3c1e 235 | 1587 236 | c9e9 237 | 87ce 238 | aa55 239 | 5028 240 | a5df 241 | 038c 242 | 59a1 243 | 0989 244 | 1a0d 245 | 65bf 246 | d7e6 247 | 8442 248 | d068 249 | 8241 250 | 2999 251 | 5a2d 252 | 1e0f 253 | 7bb0 254 | a854 255 | 6dbb 256 | 2c16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_5/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | input [127:0] i_text, 7 | input [127:0] key, 8 | input [3:0] round, 9 | 10 | output reg [127:0] o_text, 11 | output reg [127:0] Rkey, 12 | output done 13 | ); 14 | 15 | wire [127:0] roundkey_text; 16 | wire [127:0] shiftrows_text; 17 | reg [127:0] mixcolumns_text; 18 | 19 | wire [127:0] okey; 20 | reg [31:0] tkey; 21 | 22 | reg [7:0] Rcon[0:9]; //Round Constant 23 | 24 | reg [2:0] counter; 25 | reg [2:0] counter_next; 26 | 27 | reg [7:0] t0_in; 28 | reg [7:0] t1_in; 29 | reg [7:0] t2_in; 30 | reg [7:0] t3_in; 31 | 32 | wire [23:0] t0_out; 33 | wire [23:0] t1_out; 34 | wire [23:0] t2_out; 35 | wire [23:0] t3_out; 36 | 37 | 38 | initial begin 39 | Rcon[0] = 8'h01; 40 | Rcon[1] = 8'h02; 41 | Rcon[2] = 8'h04; 42 | Rcon[3] = 8'h08; 43 | Rcon[4] = 8'h10; 44 | Rcon[5] = 8'h20; 45 | Rcon[6] = 8'h40; 46 | Rcon[7] = 8'h80; 47 | Rcon[8] = 8'h1b; 48 | Rcon[9] = 8'h36; 49 | end 50 | 51 | 52 | 53 | always @(posedge clock) begin 54 | if(!resetn) begin 55 | counter <= 3'h0; 56 | end 57 | else begin 58 | counter <= counter_next; 59 | end 60 | end 61 | 62 | 63 | 64 | 65 | //Shift Rows for Encryption 66 | shiftrows U2 (.istate(i_text), .ostate(shiftrows_text)); 67 | 68 | 69 | //TBOX (SBOX) lookup for Encryption 70 | always @(counter or enable or shiftrows_text or key or round or t0_out or t1_out or t2_out or t3_out) begin 71 | 72 | if((counter == 3'h0)) begin 73 | if(enable) begin 74 | t0_in = shiftrows_text[7:0]; 75 | t1_in = shiftrows_text[15:8]; 76 | t2_in = shiftrows_text[23:16]; 77 | t3_in = shiftrows_text[31:24]; 78 | if(round == 4'h9) begin 79 | mixcolumns_text[31:0] = {t3_out[7:0], t2_out[7:0], t1_out[7:0], t0_out[7:0]}; 80 | end 81 | else begin 82 | mixcolumns_text[31:0] = {t0_out[23:16] ^ t1_out[7:0] ^ t2_out[7:0] ^ t3_out[15:8], 83 | t0_out[7:0] ^ t1_out[7:0] ^ t2_out[15:8] ^ t3_out[23:16], 84 | t0_out[7:0] ^ t1_out[15:8] ^ t2_out[23:16] ^ t3_out[7:0], 85 | t0_out[15:8] ^ t1_out[23:16] ^ t2_out[7:0] ^ t3_out[7:0]}; 86 | end 87 | counter_next = counter + 3'h1; 88 | end 89 | else begin 90 | t0_in = 32'h0; 91 | t1_in = 32'h0; 92 | t2_in = 32'h0; 93 | t3_in = 32'h0; 94 | mixcolumns_text = 128'h0; 95 | tkey = 32'h0; 96 | counter_next = 3'h0; 97 | end 98 | end 99 | else if((counter == 3'h1)) begin 100 | t0_in = shiftrows_text[39:32]; 101 | t1_in = shiftrows_text[47:40]; 102 | t2_in = shiftrows_text[55:48]; 103 | t3_in = shiftrows_text[63:56]; 104 | if(round == 4'h9) begin 105 | mixcolumns_text[63:32] = {t3_out[7:0], t2_out[7:0], t1_out[7:0], t0_out[7:0]}; 106 | end 107 | else begin 108 | mixcolumns_text[63:32] = {t0_out[23:16] ^ t1_out[7:0] ^ t2_out[7:0] ^ t3_out[15:8], 109 | t0_out[7:0] ^ t1_out[7:0] ^ t2_out[15:8] ^ t3_out[23:16], 110 | t0_out[7:0] ^ t1_out[15:8] ^ t2_out[23:16] ^ t3_out[7:0], 111 | t0_out[15:8] ^ t1_out[23:16] ^ t2_out[7:0] ^ t3_out[7:0]}; 112 | end 113 | counter_next = counter + 3'h1; 114 | end 115 | else if((counter == 3'h2)) begin 116 | t0_in = shiftrows_text[71:64]; 117 | t1_in = shiftrows_text[79:72]; 118 | t2_in = shiftrows_text[87:80]; 119 | t3_in = shiftrows_text[95:88]; 120 | if(round == 4'h9) begin 121 | mixcolumns_text[95:64] = {t3_out[7:0], t2_out[7:0], t1_out[7:0], t0_out[7:0]}; 122 | end 123 | else begin 124 | mixcolumns_text[95:64] = {t0_out[23:16] ^ t1_out[7:0] ^ t2_out[7:0] ^ t3_out[15:8], 125 | t0_out[7:0] ^ t1_out[7:0] ^ t2_out[15:8] ^ t3_out[23:16], 126 | t0_out[7:0] ^ t1_out[15:8] ^ t2_out[23:16] ^ t3_out[7:0], 127 | t0_out[15:8] ^ t1_out[23:16] ^ t2_out[7:0] ^ t3_out[7:0]}; 128 | end 129 | counter_next = counter + 3'h1; 130 | end 131 | else if((counter == 3'h3)) begin 132 | t0_in = shiftrows_text[103:96]; 133 | t1_in = shiftrows_text[111:104]; 134 | t2_in = shiftrows_text[119:112]; 135 | t3_in = shiftrows_text[127:120]; 136 | if(round == 4'h9) begin 137 | mixcolumns_text[127:96] = {t3_out[7:0], t2_out[7:0], t1_out[7:0], t0_out[7:0]}; 138 | end 139 | else begin 140 | mixcolumns_text[127:96] = {t0_out[23:16] ^ t1_out[7:0] ^ t2_out[7:0] ^ t3_out[15:8], 141 | t0_out[7:0] ^ t1_out[7:0] ^ t2_out[15:8] ^ t3_out[23:16], 142 | t0_out[7:0] ^ t1_out[15:8] ^ t2_out[23:16] ^ t3_out[7:0], 143 | t0_out[15:8] ^ t1_out[23:16] ^ t2_out[7:0] ^ t3_out[7:0]}; 144 | end 145 | counter_next = counter + 3'h1; 146 | end 147 | else if((counter == 3'h4)) begin 148 | t0_in = key[111 : 104]; //8*13+7 : 8*13 149 | t1_in = key[119 : 112]; //8*14+7 : 8*14 150 | t2_in = key[127 : 120]; //8*15+7 : 8*15 151 | t3_in = key[103 : 96]; //8*12+7 : 8*12 152 | 153 | 154 | tkey[7 : 0] = t0_out[7:0] ^ key[7 : 0] ^ Rcon[round]; 155 | tkey[15 : 8] = t1_out[7:0] ^ key[15 : 8]; 156 | tkey[23 : 16] = t2_out[7:0] ^ key[23 : 16]; 157 | tkey[31 : 24] = t3_out[7:0] ^ key[31 : 24]; 158 | counter_next = 3'h0; 159 | end 160 | end 161 | 162 | 163 | //Key Expansion for Encryption 164 | assign okey[31:0] = tkey[31:0]; 165 | assign okey[127:32] = key[127:32] ^ okey[95:0]; 166 | 167 | //Add Roundkey for Encryption 168 | assign roundkey_text = mixcolumns_text ^ okey; 169 | 170 | //TBOX (SBOX) lookup 171 | tbox0 T0 (.index(t0_in), .tbox(t0_out)); 172 | tbox0 T1 (.index(t1_in), .tbox(t1_out)); 173 | tbox0 T2 (.index(t2_in), .tbox(t2_out)); 174 | tbox0 T3 (.index(t3_in), .tbox(t3_out)); 175 | 176 | assign done = (counter == 3'h4) ? 1'b1 : 1'b0; 177 | 178 | always @(posedge clock) begin 179 | if(!resetn) begin 180 | o_text <= 128'h0; 181 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 182 | end 183 | else if(done & (round == 4'h9)) begin 184 | o_text <= roundkey_text; 185 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 186 | end 187 | else if(done) begin 188 | o_text <= roundkey_text; 189 | Rkey <= okey; 190 | end 191 | end 192 | 193 | 194 | endmodule 195 | -------------------------------------------------------------------------------- /aes_hw/aes_5/aes_slave_intf.v: -------------------------------------------------------------------------------- 1 | module aes_slave_intf ( 2 | input clock, 3 | input resetn, 4 | 5 | input chipselect, 6 | input [3:0] address, 7 | 8 | input read, 9 | output reg [31:0] readdata, 10 | 11 | input write, 12 | input [31:0] writedata, 13 | 14 | output waitrequest 15 | ); 16 | 17 | reg [127:0] plain_text; 18 | reg [127:0] cipher_text; 19 | 20 | 21 | wire plain_text_write; 22 | reg plain_text_complete; 23 | 24 | reg [1:0] icounter; 25 | 26 | reg [4:0] ecounter; 27 | reg [4:0] ecounter_next; 28 | 29 | reg enable; 30 | reg [127:0] i_text; 31 | wire [3:0] round; 32 | wire [127:0] o_text; 33 | wire [127:0] Rkey; 34 | 35 | wire done; 36 | 37 | wire cipher_text_read; 38 | reg [1:0] ocounter; 39 | reg cipher_available; 40 | wire cipher_status_read; 41 | 42 | 43 | 44 | assign plain_text_write = chipselect & write & (address == 4'h0); 45 | 46 | 47 | always @(posedge clock) begin 48 | if(!resetn) begin 49 | icounter <= 2'h0; 50 | end 51 | else if(plain_text_write) begin 52 | icounter <= icounter + 2'h1; 53 | end 54 | end 55 | 56 | 57 | always @(posedge clock) begin 58 | if(!resetn) begin 59 | plain_text <= 128'h0; 60 | plain_text_complete <= 1'b0; 61 | end 62 | else if((icounter == 2'h0) & plain_text_write) begin // & ~waitrequest 63 | plain_text <= {96'h0, writedata}; 64 | plain_text_complete <= 1'b0; 65 | end 66 | else if((icounter == 2'h1) & plain_text_write) begin // & ~waitrequest 67 | plain_text <= {plain_text[95:0], writedata}; 68 | end 69 | else if((icounter == 2'h2) & plain_text_write) begin // & ~waitrequest 70 | plain_text <= {plain_text[95:0], writedata}; 71 | end 72 | else if((icounter == 2'h3) & plain_text_write) begin // & ~waitrequest 73 | plain_text <= {plain_text[95:0], writedata}; 74 | plain_text_complete <= 1'b1; 75 | end 76 | else begin 77 | plain_text_complete <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | 83 | 84 | 85 | 86 | always @(posedge clock) begin 87 | if(!resetn) begin 88 | ecounter <= 5'h0; 89 | end 90 | else begin 91 | ecounter <= ecounter_next; 92 | end 93 | end 94 | 95 | //Multiple rounds - 10 for 128bit encryption. 96 | always @(ecounter or plain_text_complete or o_text or plain_text or Rkey or done) begin 97 | 98 | if( (ecounter == 5'h0) ) begin 99 | cipher_text = o_text; 100 | if(plain_text_complete) begin 101 | enable = 1'b1; 102 | i_text = plain_text ^ Rkey; 103 | ecounter_next = 5'h1; 104 | end 105 | else begin 106 | enable = 1'b0; 107 | i_text = 128'h0; 108 | ecounter_next = ecounter; 109 | end 110 | end 111 | else if( (ecounter == 5'h13) ) begin 112 | enable = 1'b0; 113 | if(done) begin 114 | ecounter_next = 5'h0; 115 | end 116 | end 117 | else if( (ecounter[0]) ) begin 118 | enable = 1'b0; 119 | if(done) begin 120 | ecounter_next = ecounter + 5'h1; 121 | end 122 | end 123 | else if( (!ecounter[0]) )begin 124 | enable = 1'b1; 125 | i_text = o_text; 126 | ecounter_next = ecounter + 5'h1; 127 | end 128 | 129 | end 130 | 131 | 132 | assign round = ecounter[4:1]; 133 | 134 | //Compute AES cipher for one round. 135 | aes aes0 ( 136 | .clock(clock), 137 | .resetn(resetn), 138 | 139 | .enable(enable), 140 | 141 | .i_text(i_text), 142 | .key(Rkey), 143 | .round(round), 144 | 145 | .o_text(o_text), 146 | .Rkey(Rkey), 147 | 148 | .done(done) 149 | ); 150 | 151 | 152 | 153 | always @(posedge clock) begin 154 | if(!resetn) begin 155 | cipher_available <= 1'b0; 156 | end 157 | else if((ecounter == 5'h13) & done) begin 158 | cipher_available <= 1'b1; 159 | end 160 | else if((ecounter == 5'h0) & plain_text_complete) begin 161 | cipher_available <= 1'b0; 162 | end 163 | end 164 | 165 | 166 | assign cipher_text_read = chipselect & read & (address == 4'h4); 167 | assign cipher_status_read = chipselect & read & (address == 4'h8); 168 | 169 | always @(posedge clock) begin 170 | if(!resetn) begin 171 | ocounter <= 2'h0; 172 | end 173 | else if(cipher_text_read & (~waitrequest)) begin 174 | ocounter <= ocounter + 2'h1; 175 | end 176 | end 177 | 178 | 179 | //Reading Out Cipher 180 | always @(ocounter or cipher_text_read or cipher_status_read or cipher_text or cipher_available) begin 181 | readdata = 32'h0; 182 | 183 | if(cipher_text_read) begin 184 | case(ocounter) 185 | 2'h0 : begin readdata = cipher_text[127:96]; end 186 | 2'h1 : begin readdata = cipher_text[95:64]; end 187 | 2'h2 : begin readdata = cipher_text[63:32]; end 188 | 2'h3 : begin readdata = cipher_text[31:0]; end 189 | endcase 190 | end 191 | 192 | else if(cipher_status_read) begin 193 | readdata = {31'h0, cipher_available}; 194 | end 195 | 196 | end 197 | 198 | assign waitrequest = cipher_text_read & (~cipher_available); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /aes_hw/aes_5/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_5/t0.v: -------------------------------------------------------------------------------- 1 | module tbox0 ( 2 | input [7:0] index, 3 | 4 | output [23:0] tbox 5 | ); 6 | 7 | reg [15:0] mem[0:255]; 8 | 9 | wire [15:0] temp; 10 | 11 | initial begin 12 | $readmemh("T0.hex", mem); 13 | end 14 | 15 | assign temp = mem[index]; 16 | 17 | assign tbox = {temp[15:8] ^ temp[7:0], temp}; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /aes_hw/aes_5/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #160; 38 | //enable = 1'b0; 39 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 40 | //enable = 1'b1; 41 | #9000; 42 | $finish; 43 | end 44 | 45 | 46 | always @(posedge clk) begin 47 | if(!resetn) begin 48 | ecounter <= 4'h0; 49 | end 50 | else begin 51 | ecounter <= ecounter_next; 52 | end 53 | end 54 | 55 | //Multiple rounds - 10 for 128bit encryption. 56 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 57 | ecounter_next = ecounter; //Keep the same state. 58 | enable = 1'b0; 59 | round = 4'h0; 60 | i_text = 128'h0; 61 | 62 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 63 | if(plain_text_complete) begin 64 | if(done) begin 65 | ecounter_next = 4'h1; 66 | end 67 | enable = 1'b1; 68 | round = 4'h0; 69 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 70 | end 71 | end 72 | else begin 73 | if(done) begin 74 | ecounter_next = ecounter + 4'h1; 75 | end 76 | enable = 1'b1; 77 | round = ecounter; 78 | i_text = o_text; 79 | end 80 | end 81 | 82 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /aes_hw/aes_6/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_6/T0.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_6/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | input [127:0] i_text, 7 | input [127:0] key, 8 | input [3:0] round, 9 | 10 | output reg [127:0] o_text, 11 | output reg [127:0] Rkey, 12 | output done 13 | ); 14 | 15 | wire [127:0] roundkey_text; 16 | wire [127:0] shiftrows_text; 17 | reg [127:0] mixcolumns_text; 18 | 19 | wire [127:0] okey; 20 | reg [31:0] tkey; 21 | 22 | reg [7:0] Rcon[0:9]; //Round Constant 23 | 24 | reg [4:0] counter; 25 | reg [4:0] counter_next; 26 | 27 | reg [7:0] t3_in; 28 | 29 | reg [31:0] t0_out; 30 | reg [31:0] t1_out; 31 | reg [31:0] t2_out; 32 | wire [31:0] t3_out; 33 | 34 | wire [31:0] m_text; 35 | 36 | genvar i; 37 | 38 | initial begin 39 | Rcon[0] = 8'h01; 40 | Rcon[1] = 8'h02; 41 | Rcon[2] = 8'h04; 42 | Rcon[3] = 8'h08; 43 | Rcon[4] = 8'h10; 44 | Rcon[5] = 8'h20; 45 | Rcon[6] = 8'h40; 46 | Rcon[7] = 8'h80; 47 | Rcon[8] = 8'h1b; 48 | Rcon[9] = 8'h36; 49 | end 50 | 51 | 52 | 53 | always @(posedge clock) begin 54 | if(!resetn) begin 55 | counter <= 5'h0; 56 | end 57 | else begin 58 | counter <= counter_next; 59 | end 60 | end 61 | 62 | 63 | 64 | 65 | //Shift Rows for Encryption 66 | shiftrows U2 (.istate(i_text), .ostate(shiftrows_text)); 67 | 68 | 69 | //TBOX (SBOX) lookup for Encryption 70 | always @(counter or enable or shiftrows_text or key or round or t3_out or m_text) begin 71 | 72 | if(~enable & (counter == 5'h0)) begin 73 | counter_next = 5'h0; 74 | end 75 | else if(enable & (counter == 5'h0)) begin 76 | counter_next = counter + 5'h1; 77 | end 78 | else if((counter != 5'h13)) begin 79 | counter_next = counter + 5'h1; 80 | end 81 | else begin 82 | counter_next = 5'h0; 83 | end 84 | 85 | 86 | case(counter) 87 | 88 | 5'h0 : begin t3_in = enable ? shiftrows_text[7:0] : 32'h0; end 89 | 5'h1 : begin t3_in = shiftrows_text[15:8 ]; end 90 | 5'h2 : begin t3_in = shiftrows_text[23:16]; end 91 | 5'h3 : begin t3_in = shiftrows_text[31:24]; end 92 | 93 | 5'h4 : begin t3_in = shiftrows_text[39:32]; end 94 | 5'h5 : begin t3_in = shiftrows_text[47:40]; end 95 | 5'h6 : begin t3_in = shiftrows_text[55:48]; end 96 | 5'h7 : begin t3_in = shiftrows_text[63:56]; end 97 | 98 | 5'h8 : begin t3_in = shiftrows_text[71:64]; end 99 | 5'h9 : begin t3_in = shiftrows_text[79:72]; end 100 | 5'hA : begin t3_in = shiftrows_text[87:80]; end 101 | 5'hB : begin t3_in = shiftrows_text[95:88]; end 102 | 103 | 5'hC : begin t3_in = shiftrows_text[103:96 ]; end 104 | 5'hD : begin t3_in = shiftrows_text[111:104]; end 105 | 5'hE : begin t3_in = shiftrows_text[119:112]; end 106 | 5'hF : begin t3_in = shiftrows_text[127:120]; end 107 | 108 | 5'h10 : begin t3_in = key[111 : 104]; end //8*13+7 : 8*13 109 | 5'h11 : begin t3_in = key[119 : 112]; end //8*14+7 : 8*14 110 | 5'h12 : begin t3_in = key[127 : 120]; end //8*15+7 : 8*15 111 | 5'h13 : begin t3_in = key[103 : 96 ]; end //8*12+7 : 8*12 112 | 113 | endcase 114 | 115 | 116 | case(counter) 117 | 118 | 5'h0 : begin t0_out = enable ? t3_out : 32'h0; 119 | t1_out = 32'h0; 120 | t2_out = 32'h0; 121 | mixcolumns_text = 128'h0; 122 | tkey = 32'h0; 123 | end 124 | 5'h1 : begin t1_out = t3_out; end 125 | 5'h2 : begin t2_out = t3_out; end 126 | 5'h3 : begin mixcolumns_text[31:0] = m_text; end 127 | 128 | 5'h4 : begin t0_out = t3_out; end 129 | 5'h5 : begin t1_out = t3_out; end 130 | 5'h6 : begin t2_out = t3_out; end 131 | 5'h7 : begin mixcolumns_text[63:32] = m_text; end 132 | 133 | 5'h8 : begin t0_out = t3_out; end 134 | 5'h9 : begin t1_out = t3_out; end 135 | 5'hA : begin t2_out = t3_out; end 136 | 5'hB : begin mixcolumns_text[95:64] = m_text; end 137 | 138 | 5'hC : begin t0_out = t3_out; end 139 | 5'hD : begin t1_out = t3_out; end 140 | 5'hE : begin t2_out = t3_out; end 141 | 5'hF : begin mixcolumns_text[127:96] = m_text; end 142 | 143 | 5'h10 : begin tkey[7 : 0] = t3_out[15:8] ^ key[7 : 0] ^ Rcon[round]; end //8*13+7 : 8*13 144 | 5'h11 : begin tkey[15 : 8] = t3_out[15:8] ^ key[15 : 8]; end //8*14+7 : 8*14 145 | 5'h12 : begin tkey[23 : 16] = t3_out[15:8] ^ key[23 : 16]; end //8*15+7 : 8*15 146 | 5'h13 : begin tkey[31 : 24] = t3_out[15:8] ^ key[31 : 24]; end //8*12+7 : 8*12 147 | 148 | endcase 149 | 150 | end 151 | 152 | 153 | 154 | assign m_text = (round == 4'h9) ? {t3_out[15:8], t2_out[15:8], t1_out[15:8], t0_out[15:8]} : t0_out ^ {t1_out[23:0], t1_out[31:24]} ^ {t2_out[15:0], t2_out[31:16]} ^ {t3_out[7:0], t3_out[31:8]}; 155 | 156 | 157 | //Key Expansion for Encryption 158 | assign okey[31:0] = tkey[31:0]; 159 | assign okey[127:32] = key[127:32] ^ okey[95:0]; 160 | 161 | //Add Roundkey for Encryption 162 | assign roundkey_text = mixcolumns_text ^ okey; 163 | 164 | //TBOX (SBOX) lookup 165 | tbox0 T3 (.index(t3_in), .tbox(t3_out)); 166 | 167 | 168 | 169 | assign done = (counter == 5'h13) ? 1'b1 : 1'b0; 170 | 171 | always @(posedge clock) begin 172 | if(!resetn) begin 173 | o_text <= 128'h0; 174 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 175 | end 176 | else if(done & (round == 4'h9)) begin 177 | o_text <= roundkey_text; 178 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 179 | end 180 | else if(done) begin 181 | o_text <= roundkey_text; 182 | Rkey <= okey; 183 | end 184 | end 185 | 186 | 187 | endmodule 188 | -------------------------------------------------------------------------------- /aes_hw/aes_6/aes_slave_intf.v: -------------------------------------------------------------------------------- 1 | module aes_slave_intf ( 2 | input clock, 3 | input resetn, 4 | 5 | input chipselect, 6 | input [3:0] address, 7 | 8 | input read, 9 | output reg [31:0] readdata, 10 | 11 | input write, 12 | input [31:0] writedata, 13 | 14 | output waitrequest 15 | ); 16 | 17 | reg [127:0] plain_text; 18 | reg [127:0] cipher_text; 19 | 20 | 21 | wire plain_text_write; 22 | reg plain_text_complete; 23 | 24 | reg [1:0] icounter; 25 | 26 | reg [4:0] ecounter; 27 | reg [4:0] ecounter_next; 28 | 29 | reg enable; 30 | reg [127:0] i_text; 31 | wire [3:0] round; 32 | wire [127:0] o_text; 33 | wire [127:0] Rkey; 34 | 35 | wire done; 36 | 37 | wire cipher_text_read; 38 | reg [1:0] ocounter; 39 | reg cipher_available; 40 | wire cipher_status_read; 41 | 42 | 43 | 44 | assign plain_text_write = chipselect & write & (address == 4'h0); 45 | 46 | 47 | always @(posedge clock) begin 48 | if(!resetn) begin 49 | icounter <= 2'h0; 50 | end 51 | else if(plain_text_write) begin 52 | icounter <= icounter + 2'h1; 53 | end 54 | end 55 | 56 | 57 | always @(posedge clock) begin 58 | if(!resetn) begin 59 | plain_text <= 128'h0; 60 | plain_text_complete <= 1'b0; 61 | end 62 | else if((icounter == 2'h0) & plain_text_write) begin // & ~waitrequest 63 | plain_text <= {96'h0, writedata}; 64 | plain_text_complete <= 1'b0; 65 | end 66 | else if((icounter == 2'h1) & plain_text_write) begin // & ~waitrequest 67 | plain_text <= {plain_text[95:0], writedata}; 68 | end 69 | else if((icounter == 2'h2) & plain_text_write) begin // & ~waitrequest 70 | plain_text <= {plain_text[95:0], writedata}; 71 | end 72 | else if((icounter == 2'h3) & plain_text_write) begin // & ~waitrequest 73 | plain_text <= {plain_text[95:0], writedata}; 74 | plain_text_complete <= 1'b1; 75 | end 76 | else begin 77 | plain_text_complete <= 1'b0; 78 | end 79 | end 80 | 81 | 82 | 83 | 84 | 85 | 86 | always @(posedge clock) begin 87 | if(!resetn) begin 88 | ecounter <= 5'h0; 89 | end 90 | else begin 91 | ecounter <= ecounter_next; 92 | end 93 | end 94 | 95 | //Multiple rounds - 10 for 128bit encryption. 96 | always @(ecounter or plain_text_complete or o_text or plain_text or Rkey or done) begin 97 | 98 | if( (ecounter == 5'h0) ) begin 99 | cipher_text = o_text; 100 | if(plain_text_complete) begin 101 | enable = 1'b1; 102 | i_text = plain_text ^ Rkey; 103 | ecounter_next = 5'h1; 104 | end 105 | else begin 106 | enable = 1'b0; 107 | i_text = 128'h0; 108 | ecounter_next = ecounter; 109 | end 110 | end 111 | else if( (ecounter == 5'h13) ) begin 112 | enable = 1'b0; 113 | if(done) begin 114 | ecounter_next = 5'h0; 115 | end 116 | end 117 | else if( (ecounter[0]) ) begin 118 | enable = 1'b0; 119 | if(done) begin 120 | ecounter_next = ecounter + 5'h1; 121 | end 122 | end 123 | else if( (!ecounter[0]) )begin 124 | enable = 1'b1; 125 | i_text = o_text; 126 | ecounter_next = ecounter + 5'h1; 127 | end 128 | 129 | end 130 | 131 | 132 | assign round = ecounter[4:1]; 133 | 134 | //Compute AES cipher for one round. 135 | aes aes0 ( 136 | .clock(clock), 137 | .resetn(resetn), 138 | 139 | .enable(enable), 140 | 141 | .i_text(i_text), 142 | .key(Rkey), 143 | .round(round), 144 | 145 | .o_text(o_text), 146 | .Rkey(Rkey), 147 | 148 | .done(done) 149 | ); 150 | 151 | 152 | 153 | always @(posedge clock) begin 154 | if(!resetn) begin 155 | cipher_available <= 1'b0; 156 | end 157 | else if((ecounter == 5'h13) & done) begin 158 | cipher_available <= 1'b1; 159 | end 160 | else if((ecounter == 5'h0) & plain_text_complete) begin 161 | cipher_available <= 1'b0; 162 | end 163 | end 164 | 165 | 166 | assign cipher_text_read = chipselect & read & (address == 4'h4); 167 | assign cipher_status_read = chipselect & read & (address == 4'h8); 168 | 169 | always @(posedge clock) begin 170 | if(!resetn) begin 171 | ocounter <= 2'h0; 172 | end 173 | else if(cipher_text_read & (~waitrequest)) begin 174 | ocounter <= ocounter + 2'h1; 175 | end 176 | end 177 | 178 | 179 | //Reading Out Cipher 180 | always @(ocounter or cipher_text_read or cipher_status_read or cipher_text or cipher_available) begin 181 | readdata = 32'h0; 182 | 183 | if(cipher_text_read) begin 184 | case(ocounter) 185 | 2'h0 : begin readdata = cipher_text[127:96]; end 186 | 2'h1 : begin readdata = cipher_text[95:64]; end 187 | 2'h2 : begin readdata = cipher_text[63:32]; end 188 | 2'h3 : begin readdata = cipher_text[31:0]; end 189 | endcase 190 | end 191 | 192 | else if(cipher_status_read) begin 193 | readdata = {31'h0, cipher_available}; 194 | end 195 | 196 | end 197 | 198 | assign waitrequest = cipher_text_read & (~cipher_available); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /aes_hw/aes_6/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_6/t0.v: -------------------------------------------------------------------------------- 1 | module tbox0 ( 2 | input [7:0] index, 3 | 4 | output [31:0] tbox 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | wire [7:0] sbox; 10 | wire [7:0] galois; 11 | 12 | initial begin 13 | $readmemh("T0.hex", mem); 14 | end 15 | 16 | assign sbox = mem[index]; 17 | assign galois = {sbox[6:0], 1'b0} ^ (sbox[7] ? 8'h1b : 8'h00); 18 | 19 | assign tbox = {galois ^ sbox, sbox, sbox, galois}; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /aes_hw/aes_6/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #160; 38 | //enable = 1'b0; 39 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 40 | //enable = 1'b1; 41 | #9000; 42 | $finish; 43 | end 44 | 45 | 46 | always @(posedge clk) begin 47 | if(!resetn) begin 48 | ecounter <= 4'h0; 49 | end 50 | else begin 51 | ecounter <= ecounter_next; 52 | end 53 | end 54 | 55 | //Multiple rounds - 10 for 128bit encryption. 56 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 57 | ecounter_next = ecounter; //Keep the same state. 58 | enable = 1'b0; 59 | round = 4'h0; 60 | i_text = 128'h0; 61 | 62 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 63 | if(plain_text_complete) begin 64 | if(done) begin 65 | ecounter_next = 4'h1; 66 | end 67 | enable = 1'b1; 68 | round = 4'h0; 69 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 70 | end 71 | end 72 | else begin 73 | if(done) begin 74 | ecounter_next = ecounter + 4'h1; 75 | end 76 | enable = 1'b1; 77 | round = ecounter; 78 | i_text = o_text; 79 | end 80 | end 81 | 82 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /aes_hw/aes_7/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_7/SBOX.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_7/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input [127:0] istate, 3 | input bypass, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | wire [127:0] buf1; 9 | wire [127:0] buf3; 10 | wire [127:0] buf4; 11 | 12 | genvar i; 13 | 14 | generate 15 | for(i = 0; i < 16; i= i+4) begin : mix_columns0 16 | 17 | assign buf1[ 8*i+31 : 8*i ] = { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] } ^ { istate[ 8*i+15 : 8*i ], istate[ 8*i+31 : 8*i+16 ] } ^ { istate[ 8*i+23 : 8*i ], istate[ 8*i+31 : 8*i+24 ] }; 18 | 19 | assign buf3[ 8*i+31 : 8*i] = istate[ 8*i+31 : 8*i ] ^ { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] }; 20 | 21 | //Galois Multiplication 22 | assign buf4[ 8*(i)+7 : 8*(i) ] = buf3[ 8*(i)+7 ] ? ( { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 }; 23 | assign buf4[ 8*(i+1)+7 : 8*(i+1) ] = buf3[ 8*(i+1)+7 ] ? ( { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 }; 24 | assign buf4[ 8*(i+2)+7 : 8*(i+2) ] = buf3[ 8*(i+2)+7 ] ? ( { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 }; 25 | assign buf4[ 8*(i+3)+7 : 8*(i+3) ] = buf3[ 8*(i+3)+7 ] ? ( { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 }; 26 | 27 | //bypass option for last round of encryption 28 | assign ostate[ 8*i+31 : 8*i ] = bypass ? istate[ 8*i+31 : 8*i ] : buf1[ 8*i+31 : 8*i ] ^ buf4[ 8*i+31 : 8*i ]; 29 | 30 | end 31 | endgenerate 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /aes_hw/aes_7/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input [7:0] index, 3 | 4 | output [7:0] o 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("SBOX.hex", mem); 11 | end 12 | 13 | assign o = mem[ index ]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_7/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_7/synch_fifo.v: -------------------------------------------------------------------------------- 1 | module synch_fifo #(parameter wbits = 128, abits = 2) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output full, 11 | output empty 12 | ); 13 | 14 | reg [abits:0] wptr; 15 | reg [abits:0] rptr; 16 | 17 | reg [wbits-1:0] fifofile [0 : 2**abits-1]; 18 | 19 | reg [wbits-1:0] fout; 20 | 21 | assign full = (wptr[abits-1:0] == rptr[abits-1:0]) & (wptr[abits] != rptr[abits]); 22 | assign empty = (wptr == rptr); 23 | 24 | always @(posedge clock) begin 25 | if(!resetn) begin 26 | wptr <= 'h0; 27 | rptr <= 'h0; 28 | end 29 | else begin 30 | if(wen & ~full) begin 31 | fifofile[wptr[abits-1:0]] <= wdata; 32 | wptr <= wptr + 'h1; 33 | end 34 | if(ren & ~empty) begin 35 | rptr <= rptr + 'h1; 36 | end 37 | end 38 | end 39 | 40 | assign rdata = fifofile[rptr[abits-1:0]]; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /aes_hw/aes_7/test.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg cs = 1'b0; 7 | reg [3:0] a; 8 | reg [31:0] d; 9 | reg wen; 10 | reg ren; 11 | wire halt; 12 | wire [31:0] out; 13 | 14 | initial begin 15 | clk = 1'b0; 16 | forever #5 clk = ~clk; 17 | end 18 | 19 | initial begin 20 | resetn = 1'b0; 21 | #200; 22 | resetn = 1'b1; 23 | repeat(10)@(posedge clk); 24 | wr(4'h0, 32'h0); 25 | repeat(10)@(posedge clk); 26 | wr(4'h0, 32'h1); 27 | repeat(10)@(posedge clk); 28 | wr(4'h0, 32'h2); 29 | repeat(10)@(posedge clk); 30 | wr(4'h0, 32'h3); 31 | repeat(10)@(posedge clk); 32 | wr(4'h0, 32'h4); 33 | repeat(10)@(posedge clk); 34 | wr(4'h0, 32'h5); 35 | repeat(10)@(posedge clk); 36 | wr(4'h0, 32'h6); 37 | repeat(10)@(posedge clk); 38 | wr(4'h0, 32'h7); 39 | repeat(10)@(posedge clk); 40 | wr(4'h0, 32'h8); 41 | repeat(10)@(posedge clk); 42 | wr(4'h0, 32'h9); 43 | repeat(10)@(posedge clk); 44 | wr(4'h0, 32'hA); 45 | repeat(10)@(posedge clk); 46 | wr(4'h0, 32'hB); 47 | repeat(10)@(posedge clk); 48 | wr(4'h0, 32'hC); 49 | repeat(10)@(posedge clk); 50 | wr(4'h0, 32'hD); 51 | repeat(10)@(posedge clk); 52 | wr(4'h0, 32'hE); 53 | repeat(10)@(posedge clk); 54 | wr(4'h0, 32'hF); 55 | repeat(10)@(posedge clk); 56 | rd(4'h4); 57 | repeat(10)@(posedge clk); 58 | rd(4'h5); 59 | repeat(10)@(posedge clk); 60 | rd(4'h6); 61 | repeat(10)@(posedge clk); 62 | rd(4'h7); 63 | repeat(10)@(posedge clk); 64 | rd(4'h4); 65 | repeat(10)@(posedge clk); 66 | rd(4'h5); 67 | repeat(10)@(posedge clk); 68 | rd(4'h6); 69 | repeat(10)@(posedge clk); 70 | rd(4'h7); 71 | repeat(10)@(posedge clk); 72 | rd(4'h4); 73 | repeat(10)@(posedge clk); 74 | rd(4'h5); 75 | repeat(10)@(posedge clk); 76 | rd(4'h6); 77 | repeat(10)@(posedge clk); 78 | rd(4'h7); 79 | repeat(10)@(posedge clk); 80 | rd(4'h4); 81 | repeat(10)@(posedge clk); 82 | rd(4'h5); 83 | repeat(10)@(posedge clk); 84 | rd(4'h6); 85 | repeat(10)@(posedge clk); 86 | rd(4'h7); 87 | repeat(10)@(posedge clk); 88 | $finish; 89 | end 90 | 91 | task wr; 92 | input [3:0] addr; 93 | input [31:0] data; 94 | begin 95 | cs = 1'b1; 96 | wen = 1'b1; 97 | a = addr; 98 | d = data; 99 | @(posedge clk); 100 | cs = 1'b0; 101 | wen = 1'b0; 102 | end 103 | endtask 104 | 105 | task rd; 106 | input [3:0] addr; 107 | begin 108 | cs = 1'b1; 109 | ren = 1'b1; 110 | a = addr; 111 | @(posedge clk); 112 | cs = 1'b0; 113 | ren = 1'b0; 114 | end 115 | endtask 116 | 117 | aes_slave_intf a0 (.clock(clk), .resetn(resetn), .chipselect(cs), .address(a), .writedata(d), .readdata(out), .write(wen), .read(ren), .waitrequest(halt)); 118 | 119 | endmodule 120 | -------------------------------------------------------------------------------- /aes_hw/aes_7/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #160; 38 | //enable = 1'b0; 39 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 40 | //enable = 1'b1; 41 | #9000; 42 | $finish; 43 | end 44 | 45 | 46 | always @(posedge clk) begin 47 | if(!resetn) begin 48 | ecounter <= 4'h0; 49 | end 50 | else begin 51 | ecounter <= ecounter_next; 52 | end 53 | end 54 | 55 | //Multiple rounds - 10 for 128bit encryption. 56 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 57 | ecounter_next = ecounter; //Keep the same state. 58 | enable = 1'b0; 59 | round = 4'h0; 60 | i_text = 128'h0; 61 | 62 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 63 | if(plain_text_complete) begin 64 | if(done) begin 65 | ecounter_next = 4'h1; 66 | end 67 | enable = 1'b1; 68 | round = 4'h0; 69 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 70 | end 71 | end 72 | else begin 73 | if(done) begin 74 | ecounter_next = ecounter + 4'h1; 75 | end 76 | enable = 1'b1; 77 | round = ecounter; 78 | i_text = o_text; 79 | end 80 | end 81 | 82 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /aes_hw/aes_8/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_8/T0.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_8/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_8/synch_fifo.v: -------------------------------------------------------------------------------- 1 | module synch_fifo #(parameter wbits = 128, abits = 2) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output full, 11 | output empty 12 | ); 13 | 14 | reg [abits:0] wptr; 15 | reg [abits:0] rptr; 16 | 17 | reg [wbits-1:0] fifofile [0 : 2**abits-1]; 18 | 19 | reg [wbits-1:0] fout; 20 | 21 | assign full = (wptr[abits-1:0] == rptr[abits-1:0]) & (wptr[abits] != rptr[abits]); 22 | assign empty = (wptr == rptr); 23 | 24 | always @(posedge clock) begin 25 | if(!resetn) begin 26 | wptr <= 'h0; 27 | rptr <= 'h0; 28 | end 29 | else begin 30 | if(wen & ~full) begin 31 | fifofile[wptr[abits-1:0]] <= wdata; 32 | wptr <= wptr + 'h1; 33 | end 34 | if(ren & ~empty) begin 35 | rptr <= rptr + 'h1; 36 | end 37 | end 38 | end 39 | 40 | assign rdata = fifofile[rptr[abits-1:0]]; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /aes_hw/aes_8/t0.v: -------------------------------------------------------------------------------- 1 | module tbox0 ( 2 | input [7:0] index, 3 | 4 | output [31:0] tbox 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | wire [7:0] sbox; 10 | wire [7:0] galois; 11 | 12 | initial begin 13 | $readmemh("T0.hex", mem); 14 | end 15 | 16 | assign sbox = mem[index]; 17 | assign galois = {sbox[6:0], 1'b0} ^ (sbox[7] ? 8'h1b : 8'h00); 18 | 19 | assign tbox = {galois ^ sbox, sbox, sbox, galois}; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /aes_hw/aes_8/test.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg cs = 1'b0; 7 | reg [3:0] a; 8 | reg [31:0] d; 9 | reg wen; 10 | reg ren; 11 | wire halt; 12 | wire [31:0] out; 13 | 14 | initial begin 15 | clk = 1'b0; 16 | forever #5 clk = ~clk; 17 | end 18 | 19 | initial begin 20 | resetn = 1'b0; 21 | #200; 22 | resetn = 1'b1; 23 | repeat(10)@(posedge clk); 24 | wr(4'h0, 32'h0); 25 | repeat(10)@(posedge clk); 26 | wr(4'h0, 32'h1); 27 | repeat(10)@(posedge clk); 28 | wr(4'h0, 32'h2); 29 | repeat(10)@(posedge clk); 30 | wr(4'h0, 32'h3); 31 | repeat(10)@(posedge clk); 32 | wr(4'h0, 32'h4); 33 | repeat(10)@(posedge clk); 34 | wr(4'h0, 32'h5); 35 | repeat(10)@(posedge clk); 36 | wr(4'h0, 32'h6); 37 | repeat(10)@(posedge clk); 38 | wr(4'h0, 32'h7); 39 | repeat(10)@(posedge clk); 40 | wr(4'h0, 32'h8); 41 | repeat(10)@(posedge clk); 42 | wr(4'h0, 32'h9); 43 | repeat(10)@(posedge clk); 44 | wr(4'h0, 32'hA); 45 | repeat(10)@(posedge clk); 46 | wr(4'h0, 32'hB); 47 | repeat(10)@(posedge clk); 48 | wr(4'h0, 32'hC); 49 | repeat(10)@(posedge clk); 50 | wr(4'h0, 32'hD); 51 | repeat(10)@(posedge clk); 52 | wr(4'h0, 32'hE); 53 | repeat(10)@(posedge clk); 54 | wr(4'h0, 32'hF); 55 | repeat(10)@(posedge clk); 56 | rd(4'h4); 57 | repeat(10)@(posedge clk); 58 | rd(4'h5); 59 | repeat(10)@(posedge clk); 60 | rd(4'h6); 61 | repeat(10)@(posedge clk); 62 | rd(4'h7); 63 | repeat(10)@(posedge clk); 64 | rd(4'h4); 65 | repeat(10)@(posedge clk); 66 | rd(4'h5); 67 | repeat(10)@(posedge clk); 68 | rd(4'h6); 69 | repeat(10)@(posedge clk); 70 | rd(4'h7); 71 | repeat(10)@(posedge clk); 72 | rd(4'h4); 73 | repeat(10)@(posedge clk); 74 | rd(4'h5); 75 | repeat(10)@(posedge clk); 76 | rd(4'h6); 77 | repeat(10)@(posedge clk); 78 | rd(4'h7); 79 | repeat(10)@(posedge clk); 80 | rd(4'h4); 81 | repeat(10)@(posedge clk); 82 | rd(4'h5); 83 | repeat(10)@(posedge clk); 84 | rd(4'h6); 85 | repeat(10)@(posedge clk); 86 | rd(4'h7); 87 | repeat(10)@(posedge clk); 88 | $finish; 89 | end 90 | 91 | task wr; 92 | input [3:0] addr; 93 | input [31:0] data; 94 | begin 95 | cs = 1'b1; 96 | wen = 1'b1; 97 | a = addr; 98 | d = data; 99 | @(posedge clk); 100 | cs = 1'b0; 101 | wen = 1'b0; 102 | end 103 | endtask 104 | 105 | task rd; 106 | input [3:0] addr; 107 | begin 108 | cs = 1'b1; 109 | ren = 1'b1; 110 | a = addr; 111 | @(posedge clk); 112 | cs = 1'b0; 113 | ren = 1'b0; 114 | end 115 | endtask 116 | 117 | aes_slave_intf a0 (.clock(clk), .resetn(resetn), .chipselect(cs), .address(a), .writedata(d), .readdata(out), .write(wen), .read(ren), .waitrequest(halt)); 118 | 119 | endmodule 120 | -------------------------------------------------------------------------------- /aes_hw/aes_8/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #160; 38 | //enable = 1'b0; 39 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 40 | //enable = 1'b1; 41 | #9000; 42 | $finish; 43 | end 44 | 45 | 46 | always @(posedge clk) begin 47 | if(!resetn) begin 48 | ecounter <= 4'h0; 49 | end 50 | else begin 51 | ecounter <= ecounter_next; 52 | end 53 | end 54 | 55 | //Multiple rounds - 10 for 128bit encryption. 56 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 57 | ecounter_next = ecounter; //Keep the same state. 58 | enable = 1'b0; 59 | round = 4'h0; 60 | i_text = 128'h0; 61 | 62 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 63 | if(plain_text_complete) begin 64 | if(done) begin 65 | ecounter_next = 4'h1; 66 | end 67 | enable = 1'b1; 68 | round = 4'h0; 69 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 70 | end 71 | end 72 | else begin 73 | if(done) begin 74 | ecounter_next = ecounter + 4'h1; 75 | end 76 | enable = 1'b1; 77 | round = ecounter; 78 | i_text = o_text; 79 | end 80 | end 81 | 82 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /aes_hw/aes_9/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/aes_9/SBOX.hex: -------------------------------------------------------------------------------- 1 | 63 2 | 7c 3 | 77 4 | 7b 5 | f2 6 | 6b 7 | 6f 8 | c5 9 | 30 10 | 01 11 | 67 12 | 2b 13 | fe 14 | d7 15 | ab 16 | 76 17 | ca 18 | 82 19 | c9 20 | 7d 21 | fa 22 | 59 23 | 47 24 | f0 25 | ad 26 | d4 27 | a2 28 | af 29 | 9c 30 | a4 31 | 72 32 | c0 33 | b7 34 | fd 35 | 93 36 | 26 37 | 36 38 | 3f 39 | f7 40 | cc 41 | 34 42 | a5 43 | e5 44 | f1 45 | 71 46 | d8 47 | 31 48 | 15 49 | 04 50 | c7 51 | 23 52 | c3 53 | 18 54 | 96 55 | 05 56 | 9a 57 | 07 58 | 12 59 | 80 60 | e2 61 | eb 62 | 27 63 | b2 64 | 75 65 | 09 66 | 83 67 | 2c 68 | 1a 69 | 1b 70 | 6e 71 | 5a 72 | a0 73 | 52 74 | 3b 75 | d6 76 | b3 77 | 29 78 | e3 79 | 2f 80 | 84 81 | 53 82 | d1 83 | 00 84 | ed 85 | 20 86 | fc 87 | b1 88 | 5b 89 | 6a 90 | cb 91 | be 92 | 39 93 | 4a 94 | 4c 95 | 58 96 | cf 97 | d0 98 | ef 99 | aa 100 | fb 101 | 43 102 | 4d 103 | 33 104 | 85 105 | 45 106 | f9 107 | 02 108 | 7f 109 | 50 110 | 3c 111 | 9f 112 | a8 113 | 51 114 | a3 115 | 40 116 | 8f 117 | 92 118 | 9d 119 | 38 120 | f5 121 | bc 122 | b6 123 | da 124 | 21 125 | 10 126 | ff 127 | f3 128 | d2 129 | cd 130 | 0c 131 | 13 132 | ec 133 | 5f 134 | 97 135 | 44 136 | 17 137 | c4 138 | a7 139 | 7e 140 | 3d 141 | 64 142 | 5d 143 | 19 144 | 73 145 | 60 146 | 81 147 | 4f 148 | dc 149 | 22 150 | 2a 151 | 90 152 | 88 153 | 46 154 | ee 155 | b8 156 | 14 157 | de 158 | 5e 159 | 0b 160 | db 161 | e0 162 | 32 163 | 3a 164 | 0a 165 | 49 166 | 06 167 | 24 168 | 5c 169 | c2 170 | d3 171 | ac 172 | 62 173 | 91 174 | 95 175 | e4 176 | 79 177 | e7 178 | c8 179 | 37 180 | 6d 181 | 8d 182 | d5 183 | 4e 184 | a9 185 | 6c 186 | 56 187 | f4 188 | ea 189 | 65 190 | 7a 191 | ae 192 | 08 193 | ba 194 | 78 195 | 25 196 | 2e 197 | 1c 198 | a6 199 | b4 200 | c6 201 | e8 202 | dd 203 | 74 204 | 1f 205 | 4b 206 | bd 207 | 8b 208 | 8a 209 | 70 210 | 3e 211 | b5 212 | 66 213 | 48 214 | 03 215 | f6 216 | 0e 217 | 61 218 | 35 219 | 57 220 | b9 221 | 86 222 | c1 223 | 1d 224 | 9e 225 | e1 226 | f8 227 | 98 228 | 11 229 | 69 230 | d9 231 | 8e 232 | 94 233 | 9b 234 | 1e 235 | 87 236 | e9 237 | ce 238 | 55 239 | 28 240 | df 241 | 8c 242 | a1 243 | 89 244 | 0d 245 | bf 246 | e6 247 | 42 248 | 68 249 | 41 250 | 99 251 | 2d 252 | 0f 253 | b0 254 | 54 255 | bb 256 | 16 257 | -------------------------------------------------------------------------------- /aes_hw/aes_9/addroundkey.v: -------------------------------------------------------------------------------- 1 | module addroundkey ( 2 | input [127:0] istate, 3 | input [127:0] key, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | assign ostate = istate ^ key; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /aes_hw/aes_9/aes.v: -------------------------------------------------------------------------------- 1 | module aes ( 2 | input clock, 3 | input resetn, 4 | 5 | input enable, 6 | 7 | input [127:0] i_text, 8 | input [127:0] key, 9 | input [3:0] round, 10 | 11 | output reg [127:0] o_text, 12 | output reg [127:0] Rkey, 13 | 14 | output done 15 | ); 16 | 17 | wire [127:0] okey; 18 | 19 | wire [127:0] subbytes_text; 20 | wire [127:0] roundkey_text; 21 | wire [127:0] shiftrows_text; 22 | wire [127:0] mixcolumns_text; 23 | 24 | 25 | //Sub bytes computation for Encryption 26 | subbytes U1 (.istate(i_text), .ostate(subbytes_text)); 27 | 28 | //Shift Rows for Encryption 29 | shiftrows U2 (.istate(subbytes_text), .ostate(shiftrows_text)); 30 | 31 | //Mix Columns for Encryption 32 | mixcolumns U3 (.istate(shiftrows_text), .bypass(round==4'h9), .ostate(mixcolumns_text)); 33 | 34 | //Key Expansion for Encryption 35 | keyexpand U4 (.ikey(key), .round(round), .okey(okey)); 36 | 37 | //Add Roundkey for Encryption 38 | addroundkey U5 (.istate(mixcolumns_text), .key(okey), .ostate(roundkey_text)); 39 | 40 | always @(posedge clock) begin 41 | if(!resetn) begin 42 | o_text <= 128'h0; 43 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 44 | end 45 | else if(enable & (round == 4'h9)) begin 46 | o_text <= roundkey_text; 47 | Rkey <= 128'h0f0e0d0c0b0a09080706050403020100; 48 | end 49 | else if(enable) begin 50 | o_text <= roundkey_text; 51 | Rkey <= okey; 52 | end 53 | end 54 | 55 | assign done = 1'b1; 56 | 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /aes_hw/aes_9/keyexpand.v: -------------------------------------------------------------------------------- 1 | module keyexpand ( 2 | 3 | input [127:0] ikey, 4 | input [3:0] round, 5 | 6 | output [127:0] okey 7 | ); 8 | 9 | reg [7:0] Rcon[0:9]; //Round Constant 10 | 11 | wire [7:0] o13; 12 | wire [7:0] o14; 13 | wire [7:0] o15; 14 | wire [7:0] o12; 15 | 16 | 17 | genvar i; 18 | 19 | 20 | initial begin 21 | Rcon[0] = 8'h01; 22 | Rcon[1] = 8'h02; 23 | Rcon[2] = 8'h04; 24 | Rcon[3] = 8'h08; 25 | Rcon[4] = 8'h10; 26 | Rcon[5] = 8'h20; 27 | Rcon[6] = 8'h40; 28 | Rcon[7] = 8'h80; 29 | Rcon[8] = 8'h1b; 30 | Rcon[9] = 8'h36; 31 | end 32 | 33 | 34 | assign okey[8*0+7 : 8*0] = o13 ^ ikey[8*0+7 : 8*0] ^ Rcon[round]; 35 | assign okey[8*1+7 : 8*1] = o14 ^ ikey[8*1+7 : 8*1]; 36 | assign okey[8*2+7 : 8*2] = o15 ^ ikey[8*2+7 : 8*2]; 37 | assign okey[8*3+7 : 8*3] = o12 ^ ikey[8*3+7 : 8*3]; 38 | 39 | 40 | sbox sbox0(.index(ikey[8*13+7 : 8*13]), 41 | 42 | .o(o13) 43 | ); 44 | 45 | sbox sbox1(.index(ikey[8*14+7 : 8*14]), 46 | 47 | .o(o14) 48 | ); 49 | 50 | sbox sbox2(.index(ikey[8*15+7 : 8*15]), 51 | 52 | .o(o15) 53 | ); 54 | 55 | sbox sbox3(.index(ikey[8*12+7 : 8*12]), 56 | 57 | .o(o12) 58 | ); 59 | 60 | 61 | //Key Expansion for Encryption 62 | generate 63 | for(i = 4; i < 16; i = i+1) begin : key_expand 64 | assign okey[8*i+7 : 8*i] = ikey[8*i+7 : 8*i] ^ okey[8*(i-4)+7 : 8*(i-4)]; 65 | end 66 | endgenerate 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /aes_hw/aes_9/mixcolumns.v: -------------------------------------------------------------------------------- 1 | module mixcolumns ( 2 | input [127:0] istate, 3 | input bypass, 4 | 5 | output [127:0] ostate 6 | ); 7 | 8 | wire [127:0] buf1; 9 | wire [127:0] buf3; 10 | wire [127:0] buf4; 11 | 12 | genvar i; 13 | 14 | generate 15 | for(i = 0; i < 16; i= i+4) begin : mix_columns0 16 | 17 | assign buf1[ 8*i+31 : 8*i ] = { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] } ^ { istate[ 8*i+15 : 8*i ], istate[ 8*i+31 : 8*i+16 ] } ^ { istate[ 8*i+23 : 8*i ], istate[ 8*i+31 : 8*i+24 ] }; 18 | 19 | assign buf3[ 8*i+31 : 8*i] = istate[ 8*i+31 : 8*i ] ^ { istate[ 8*i+7 : 8*i ], istate[ 8*i+31 : 8*i+8 ] }; 20 | 21 | //Galois Multiplication 22 | assign buf4[ 8*(i)+7 : 8*(i) ] = buf3[ 8*(i)+7 ] ? ( { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i)+6 : 8*(i) ], 1'b0 }; 23 | assign buf4[ 8*(i+1)+7 : 8*(i+1) ] = buf3[ 8*(i+1)+7 ] ? ( { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+1)+6 : 8*(i+1) ], 1'b0 }; 24 | assign buf4[ 8*(i+2)+7 : 8*(i+2) ] = buf3[ 8*(i+2)+7 ] ? ( { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+2)+6 : 8*(i+2) ], 1'b0 }; 25 | assign buf4[ 8*(i+3)+7 : 8*(i+3) ] = buf3[ 8*(i+3)+7 ] ? ( { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 } ^ 8'h1b ) : { buf3[ 8*(i+3)+6 : 8*(i+3) ], 1'b0 }; 26 | 27 | //bypass option for last round of encryption 28 | assign ostate[ 8*i+31 : 8*i ] = bypass ? istate[ 8*i+31 : 8*i ] : buf1[ 8*i+31 : 8*i ] ^ buf4[ 8*i+31 : 8*i ]; 29 | 30 | end 31 | endgenerate 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /aes_hw/aes_9/sbox.v: -------------------------------------------------------------------------------- 1 | module sbox ( 2 | input [7:0] index, 3 | 4 | output [7:0] o 5 | ); 6 | 7 | reg [7:0] mem[0:255]; 8 | 9 | initial begin 10 | $readmemh("SBOX.hex", mem); 11 | end 12 | 13 | assign o = mem[ index ]; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /aes_hw/aes_9/shiftrows.v: -------------------------------------------------------------------------------- 1 | module shiftrows ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | // state[0] = state[0] 10 | // state[4] = state[4] 11 | // state[8] = state[8] 12 | // state[12] = state[12] 13 | generate 14 | for(i = 0; i < 16; i = i+4) begin : shift0 15 | assign ostate[8*i+7 : 8*i] = istate[8*i+7 : 8*i]; 16 | end 17 | endgenerate 18 | 19 | 20 | // state[1] = state[5] 21 | // state[5] = state[9] 22 | // state[9] = state[13] 23 | // state[13] = state[1] 24 | generate 25 | for(i = 1; i < 13; i = i+4) begin : shift1 26 | assign ostate[8*i+7 : 8*i] = istate[8*(i+4)+7 : 8*(i+4)]; 27 | end 28 | endgenerate 29 | 30 | assign ostate[8*13+7 : 8*13] = istate[8*1+7 : 8*1]; 31 | 32 | 33 | // state[2] = state[10] 34 | // state[6] = state[14] 35 | // state[10] = state[2] 36 | // state[14] = state[6] 37 | generate 38 | for(i = 2; i < 7; i = i+4) begin : shift2 39 | assign ostate[8*i+7 : 8*i] = istate[8*(i+8)+7 : 8*(i+8)]; 40 | end 41 | endgenerate 42 | 43 | generate 44 | for(i = 10; i < 16; i = i+4) begin : shift3 45 | assign ostate[8*i+7 : 8*i] = istate[8*(i-8)+7 : 8*(i-8)]; 46 | end 47 | endgenerate 48 | 49 | 50 | // state[7] = state[3] 51 | // state[11] = state[7] 52 | // state[15] = state[11] 53 | // state[3] = state[15] 54 | generate 55 | for(i = 7; i < 16; i = i+4) begin : shift4 56 | assign ostate[8*i+7 : 8*i] = istate[8*(i-4)+7 : 8*(i-4)]; 57 | end 58 | endgenerate 59 | 60 | assign ostate[8*3+7 : 8*3] = istate[8*15+7 : 8*15]; 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /aes_hw/aes_9/subbytes.v: -------------------------------------------------------------------------------- 1 | module subbytes ( 2 | input [127:0] istate, 3 | 4 | output [127:0] ostate 5 | ); 6 | 7 | genvar i; 8 | 9 | //Sub bytes computation for Encryption 10 | generate 11 | for(i = 0; i < 16; i = i+1) begin : sub_bytes 12 | 13 | sbox inst(.index(istate[8*i+7 : 8*i]), 14 | 15 | .o(ostate[8*i+7 : 8*i]) 16 | ); 17 | end 18 | endgenerate 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /aes_hw/aes_9/synch_fifo.v: -------------------------------------------------------------------------------- 1 | module synch_fifo #(parameter wbits = 128, abits = 2) ( 2 | input clock, 3 | input resetn, 4 | 5 | input wen, 6 | input ren, 7 | input [wbits-1:0] wdata, 8 | output [wbits-1:0] rdata, 9 | 10 | output full, 11 | output empty 12 | ); 13 | 14 | reg [abits:0] wptr; 15 | reg [abits:0] rptr; 16 | 17 | reg [wbits-1:0] fifofile [0 : 2**abits-1]; 18 | 19 | reg [wbits-1:0] fout; 20 | 21 | assign full = (wptr[abits-1:0] == rptr[abits-1:0]) & (wptr[abits] != rptr[abits]); 22 | assign empty = (wptr == rptr); 23 | 24 | always @(posedge clock) begin 25 | if(!resetn) begin 26 | wptr <= 'h0; 27 | rptr <= 'h0; 28 | end 29 | else begin 30 | if(wen & ~full) begin 31 | fifofile[wptr[abits-1:0]] <= wdata; 32 | wptr <= wptr + 'h1; 33 | end 34 | if(ren & ~empty) begin 35 | rptr <= rptr + 'h1; 36 | end 37 | end 38 | end 39 | 40 | assign rdata = fifofile[rptr[abits-1:0]]; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /aes_hw/aes_9/test1.v: -------------------------------------------------------------------------------- 1 | module tb; 2 | 3 | reg resetn; 4 | reg clk; 5 | 6 | reg enable; 7 | 8 | reg [127:0] i_text; 9 | wire [127:0] o_text; 10 | wire [127:0] Rkey; 11 | 12 | reg [127:0] plain_text; 13 | reg plain_text_complete; 14 | 15 | reg [3:0] ecounter; 16 | reg [3:0] ecounter_next; 17 | 18 | reg [3:0] round; 19 | 20 | wire done; 21 | 22 | 23 | initial begin 24 | //$readmemh("SBOX.hex", mem); 25 | clk = 1'b0; 26 | forever #5 clk = ~clk; 27 | end 28 | 29 | initial begin 30 | resetn = 1'b0; 31 | #100; 32 | resetn = 1'b1; 33 | #50; 34 | plain_text = 128'hffeeddccbbaa99887766554433221100; 35 | plain_text_complete = 1'b1; 36 | //enable = 1'b1; 37 | #90; 38 | plain_text_complete = 1'b0; 39 | //enable = 1'b0; 40 | //itext = 128'hf47237c18b4c5a4059d1c3ab48966732; 41 | //enable = 1'b1; 42 | #100; 43 | $finish; 44 | end 45 | 46 | 47 | always @(posedge clk) begin 48 | if(!resetn) begin 49 | ecounter <= 4'h0; 50 | end 51 | else begin 52 | ecounter <= ecounter_next; 53 | end 54 | end 55 | 56 | //Multiple rounds - 10 for 128bit encryption. 57 | always @(ecounter or plain_text_complete or plain_text or o_text or Rkey or done) begin 58 | ecounter_next = ecounter; //Keep the same state. 59 | enable = 1'b0; 60 | round = 4'h0; 61 | i_text = 128'h0; 62 | 63 | if( (ecounter == 4'h0) || (ecounter == 4'hA)) begin 64 | if(plain_text_complete) begin 65 | if(done) begin 66 | ecounter_next = 4'h1; 67 | end 68 | enable = 1'b1; 69 | round = 4'h0; 70 | i_text = plain_text ^ Rkey; //First Addroundkey for Encryption. //XOR Initialization Vector here.. 71 | end 72 | end 73 | else begin 74 | if(done) begin 75 | ecounter_next = ecounter + 4'h1; 76 | end 77 | enable = 1'b1; 78 | round = ecounter; 79 | i_text = o_text; 80 | end 81 | end 82 | 83 | aes s0 (.clock(clk), .resetn(resetn), .enable(enable), .i_text(i_text), .key(Rkey), .round(round), .o_text(o_text), .Rkey(Rkey), .done(done)); 84 | 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /aes_hw/bin/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /aes_hw/bin/bmp_cs50.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************** 2 | * bmp.h 3 | * 4 | * Computer Science 50 5 | * Problem Set 5 6 | * 7 | * BMP-related data types based on Microsoft's own. 8 | ***************************************************************************/ 9 | 10 | #include 11 | 12 | 13 | /* 14 | * Common Data Types 15 | * 16 | * The data types in this section are essentially aliases for C/C++ 17 | * primitive data types. 18 | * 19 | * Adapted from http://msdn.microsoft.com/en-us/library/cc230309(PROT.10).aspx. 20 | * See http://en.wikipedia.org/wiki/Stdint.h for more on stdint.h. 21 | */ 22 | 23 | typedef uint8_t BYTE; 24 | typedef uint32_t DWORD; 25 | typedef int32_t LONG; 26 | typedef uint16_t WORD; 27 | 28 | 29 | /* 30 | * BITMAPFILEHEADER 31 | * 32 | * The BITMAPFILEHEADER structure contains information about the type, size, 33 | * and layout of a file that contains a DIB [device-independent bitmap]. 34 | * 35 | * Adapted from http://msdn.microsoft.com/en-us/library/dd183374(VS.85).aspx. 36 | */ 37 | 38 | typedef struct 39 | { 40 | WORD bfType; 41 | DWORD bfSize; 42 | WORD bfReserved1; 43 | WORD bfReserved2; 44 | DWORD bfOffBits; 45 | } __attribute__((__packed__)) 46 | BITMAPFILEHEADER; 47 | 48 | 49 | /* 50 | * BITMAPINFOHEADER 51 | * 52 | * The BITMAPINFOHEADER structure contains information about the 53 | * dimensions and color format of a DIB [device-independent bitmap]. 54 | * 55 | * Adapted from http://msdn.microsoft.com/en-us/library/dd183376(VS.85).aspx. 56 | */ 57 | 58 | typedef struct 59 | { 60 | DWORD biSize; 61 | LONG biWidth; 62 | LONG biHeight; 63 | WORD biPlanes; 64 | WORD biBitCount; 65 | DWORD biCompression; 66 | DWORD biSizeImage; 67 | LONG biXPelsPerMeter; 68 | LONG biYPelsPerMeter; 69 | DWORD biClrUsed; 70 | DWORD biClrImportant; 71 | } __attribute__((__packed__)) 72 | BITMAPINFOHEADER; 73 | 74 | 75 | /* 76 | * RGBTRIPLE 77 | * 78 | * This structure describes a color consisting of relative intensities of 79 | * red, green, and blue. 80 | * 81 | * Adapted from http://msdn.microsoft.com/en-us/library/aa922590.aspx. 82 | */ 83 | 84 | typedef struct 85 | { 86 | BYTE rgbtBlue; 87 | BYTE rgbtGreen; 88 | BYTE rgbtRed; 89 | } __attribute__((__packed__)) 90 | RGBTRIPLE; 91 | -------------------------------------------------------------------------------- /aes_hw/bin/cpu.h: -------------------------------------------------------------------------------- 1 | /* 2 | * cpu.h 3 | * 4 | * Created on: Dec 8, 2017 5 | * Author: 695r24 6 | */ 7 | 8 | #ifndef CPU_H_ 9 | #define CPU_H_ 10 | 11 | #define PERF_CNTR_BASE alt_get_performance_counter_base() 12 | 13 | static unsigned int* aes_control = AES_SLAVE_INTERFACE_11_0_AVALON_SLAVE_WR_BASE; 14 | static unsigned int* aes_status = AES_SLAVE_INTERFACE_11_0_AVALON_SLAVE_RD_BASE + 16; 15 | 16 | void cpu_encrypt(unsigned int* ptext, unsigned int* ctext) 17 | { 18 | int i; 19 | unsigned int data1; 20 | unsigned int data2; 21 | unsigned int data3; 22 | unsigned int data4; 23 | 24 | //printf("Entering CPU Encryption! \n\n"); 25 | 26 | //Performance Counter 27 | PERF_BEGIN(PERF_CNTR_BASE, 1); 28 | 29 | *(aes_control) = *(ptext); 30 | *(aes_control) = *(ptext+1); 31 | *(aes_control) = *(ptext+2); 32 | *(aes_control) = *(ptext+3); 33 | 34 | *(ctext) = *(aes_status); 35 | *(ctext+1) = *(aes_status); 36 | *(ctext+2) = *(aes_status); 37 | *(ctext+3) = *(aes_status); 38 | 39 | //Performance Counter 40 | PERF_END(PERF_CNTR_BASE, 1); 41 | 42 | data1 = *(ctext); 43 | data2 = *(ctext+1); 44 | data3 = *(ctext+2); 45 | data4 = *(ctext+3); 46 | //printf("0x%08x%08x%08x%08x \n", data1, data2, data3, data4); 47 | 48 | //printf("\nExiting CPU Encryption! \n\n"); 49 | } 50 | 51 | 52 | #endif /* CPU_H_ */ 53 | -------------------------------------------------------------------------------- /aes_hw/bin/dma.h: -------------------------------------------------------------------------------- 1 | /* 2 | * dma.h 3 | * 4 | * Created on: Dec 6, 2017 5 | * Author: 695r24 6 | */ 7 | 8 | #ifndef DMA_H_ 9 | #define DMA_H_ 10 | 11 | #include "io.h" 12 | 13 | #define PERF_CNTR_BASE alt_get_performance_counter_base() 14 | #define DMA_WR_BASE DMA_0_BASE 15 | #define DMA_RD_BASE DMA_1_BASE 16 | 17 | 18 | //static unsigned int* aes_control = AES_SLAVE_INTERFACE_11_0_AVALON_SLAVE_WR_BASE; 19 | //static unsigned int* aes_status = AES_SLAVE_INTERFACE_11_0_AVALON_SLAVE_RD_BASE + 16; 20 | 21 | extern unsigned int* aes_control; 22 | extern unsigned int* aes_status; 23 | 24 | void dma_encrypt(unsigned int* ptext, unsigned int* ctext, unsigned int size) 25 | { 26 | int i; 27 | unsigned int data1; 28 | unsigned int data2; 29 | unsigned int data3; 30 | unsigned int data4; 31 | 32 | //printf("Entering DMA Encryption! \n\n"); 33 | 34 | //Performance Counter 35 | PERF_BEGIN(PERF_CNTR_BASE, 1); 36 | 37 | IOWR(DMA_WR_BASE, 6, 1<<12); 38 | IOWR(DMA_WR_BASE, 6, 1<<12); 39 | IOWR(DMA_WR_BASE, 1, ptext); 40 | IOWR(DMA_WR_BASE, 2, aes_control); 41 | IOWR(DMA_WR_BASE, 3, size); 42 | 43 | IOWR(DMA_RD_BASE, 6, 1<<12); 44 | IOWR(DMA_RD_BASE, 6, 1<<12); 45 | IOWR(DMA_RD_BASE, 1, aes_status); 46 | IOWR(DMA_RD_BASE, 2, ctext); 47 | IOWR(DMA_RD_BASE, 3, size); 48 | 49 | IOWR(DMA_WR_BASE, 6, 1<<9 | 1<< 7 | 1<<3 | 1<<2); 50 | IOWR(DMA_RD_BASE, 6, 1<<8 | 1<< 7 | 1<<3 | 1<<2); 51 | while((IORD(DMA_WR_BASE, 0) & 0x1) == 0); 52 | IOWR(DMA_WR_BASE, 0, 0); 53 | 54 | while((IORD(DMA_RD_BASE, 0) & 0x1) == 0); 55 | IOWR(DMA_RD_BASE, 0, 0); 56 | 57 | //Performance Counter 58 | PERF_END(PERF_CNTR_BASE, 1); 59 | 60 | /*for(i = 0; i < 16; i = i+4) 61 | { 62 | data1 = ctext[i]; 63 | data2 = ctext[i+1]; 64 | data3 = ctext[i+2]; 65 | data4 = ctext[i+3]; 66 | //printf("0x%08x%08x%08x%08x \n", data1, data2, data3, data4); 67 | }*/ 68 | 69 | //printf("\nExiting DMA Encryption! \n"); 70 | } 71 | 72 | 73 | #endif /* DMA_H_ */ 74 | -------------------------------------------------------------------------------- /aes_hw/bin/tv.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/vignesh-raghavan/AES128/22cf74e9512cbbcb0126fa5c36e94e907a3b0d06/aes_hw/bin/tv.bmp -------------------------------------------------------------------------------- /aes_hw/bin/tv.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/vignesh-raghavan/AES128/22cf74e9512cbbcb0126fa5c36e94e907a3b0d06/aes_hw/bin/tv.zip -------------------------------------------------------------------------------- /aes_hw/bin/vga_display.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include "bmp_cs50.h" 5 | #include "altera_up_avalon_video_pixel_buffer_dma.h" 6 | #include 7 | #include "aes.h" 8 | #include "vga_display.h" 9 | #include "cpu.h" 10 | #include "dma.h" 11 | 12 | //#define PERF_CNTR_BASE alt_get_performance_counter_base() 13 | 14 | 15 | //Expected Output 16 | //5ac5b47080b7cdd830047b6ad8e0c469 17 | //26c3f4415c36600bc6e67b10df5047fa 18 | 19 | unsigned int ewords[256]; 20 | 21 | unsigned int words[256] = { 22 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 23 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 24 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 25 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 26 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 27 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 28 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 29 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 30 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 31 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 32 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 33 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 34 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 35 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 36 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 37 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 38 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 39 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 40 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 41 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 42 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 43 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 44 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 45 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 46 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 47 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 48 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 49 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 50 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 51 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 52 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 53 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 54 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 55 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 56 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 57 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 58 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 59 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 60 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 61 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 62 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 63 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 64 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 65 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 66 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 67 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 68 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 69 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 70 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 71 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 72 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 73 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 74 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 75 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 76 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 77 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 78 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 79 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 80 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 81 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 82 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 83 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732, 84 | 0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100, 85 | 0xf47237c1, 0x8b4c5a40, 0x59d1c3ab, 0x48966732 86 | }; 87 | 88 | const char* s[3] = {"AES_SW", "AES_CPU", "AES_DMA"}; 89 | 90 | int main() 91 | { 92 | int i; 93 | 94 | //Performance Counter 95 | PERF_RESET(PERF_CNTR_BASE); 96 | PERF_START_MEASURING(PERF_CNTR_BASE); 97 | 98 | printf("Hello from Nios II!\n"); 99 | 100 | alt_up_pixel_buffer_dma_dev *pb = alt_up_pixel_buffer_dma_open_dev("/dev/video_pixel_buffer_dma_0"); 101 | 102 | FILE *inptr = fopen("/mnt/rozipfs/tv.bmp", "r"); 103 | 104 | if(inptr == NULL) 105 | printf("Image not found \n"); 106 | 107 | BITMAPFILEHEADER bf; 108 | fread(&bf, sizeof(BITMAPFILEHEADER), 1, inptr); 109 | //printf("headerfile_size = %d\n", sizeof(BITMAPFILEHEADER)); 110 | 111 | BITMAPINFOHEADER bi; 112 | fread(&bi, sizeof(BITMAPINFOHEADER), 1, inptr); 113 | //printf("headerinfo_size = %d\n", sizeof(BITMAPFILEHEADER)); 114 | 115 | int32_t biHeight; 116 | 117 | int k; 118 | unsigned int p; 119 | int j; 120 | int padding = (4 - (bi.biWidth * sizeof(RGBTRIPLE)) % 4) % 4; 121 | int pixel_size = ( abs(bi.biHeight)*bi.biWidth )/2 ;//144 122 | unsigned int pixel[pixel_size]; 123 | 124 | unsigned int *pixel1; // = (unsigned int*) 0x10800000; 125 | 126 | k = 0; 127 | p = 0; 128 | //printf("%d\n", pixel_size); 129 | printf("width = %d height = %d\n", bi.biWidth, bi.biHeight); 130 | for (i = 0, biHeight = abs(bi.biHeight); i < biHeight; i++) 131 | { 132 | j = 0; 133 | for (j = 0; j < bi.biWidth; j=j+2) 134 | { 135 | RGBTRIPLE triple; 136 | fread(&triple, sizeof(RGBTRIPLE), 1, inptr); 137 | 138 | p = (unsigned int) (triple.rgbtRed & (0xF8))<<8; // red 139 | p = p | ((triple.rgbtGreen & (0xFC)) << 3); // green 140 | p = p | ((triple.rgbtBlue & (0xF8)) >> 3); // blue 141 | 142 | p = p << 16; 143 | 144 | fread(&triple, sizeof(RGBTRIPLE), 1, inptr); 145 | 146 | p = p | (triple.rgbtRed & (0xF8))<<8; // red 147 | p = p | ((triple.rgbtGreen & (0xFC)) << 3); // green 148 | p = p | ((triple.rgbtBlue & (0xF8)) >> 3); // blue 149 | 150 | pixel[k] = p; 151 | k++; 152 | //printf("%0x\n", p); 153 | } 154 | //printf("\n\n"); 155 | fseek(inptr, padding, SEEK_CUR); 156 | } 157 | i = pixel_size - 1; 158 | j = 0; 159 | for(i = pixel_size-1; i>=0; i--) 160 | { 161 | pixel1[j] = pixel[i]; 162 | j++; 163 | } 164 | 165 | pixel_vga_display(pb, pixel1, bi.biWidth, biHeight); 166 | 167 | printf("Hello Encryption\n"); 168 | 169 | unsigned int *pwords = pixel1; //words; 170 | unsigned int *cwords = (unsigned int*) 0x10800000; 171 | 172 | unsigned int mode = 3; 173 | //unsigned int pixel_size = 256; 174 | 175 | if(mode == 1) 176 | { 177 | for(i = 0; i < pixel_size; i = i+4) 178 | { 179 | sw_encrypt(pwords+i, cwords+i); 180 | // printf("0x%08x%08x%08x%08x \n", pwords[i], pwords[i+1], pwords[i+2], pwords[i+3]); 181 | // printf("0x%08x%08x%08x%08x \n", cwords[i], cwords[i+1], cwords[i+2], cwords[i+3]); 182 | } 183 | } 184 | 185 | else if(mode == 2) 186 | { 187 | for(i = 0; i < pixel_size; i = i+4) 188 | { 189 | cpu_encrypt(pwords+i, cwords+i); 190 | // printf("0x%08x%08x%08x%08x \n", pwords[i], pwords[i+1], pwords[i+2], pwords[i+3]); 191 | // printf("0x%08x%08x%08x%08x \n", cwords[i], cwords[i+1], cwords[i+2], cwords[i+3]); 192 | } 193 | } 194 | 195 | else if(mode == 3) dma_encrypt(pwords, cwords, 4*pixel_size); 196 | 197 | printf("End Encryption\n"); 198 | 199 | //Performance Counter 200 | PERF_STOP_MEASURING(PERF_CNTR_BASE); 201 | perf_print_formatted_report(PERF_CNTR_BASE, 50000000, 1, s[mode-1]); 202 | 203 | return 0; 204 | } 205 | -------------------------------------------------------------------------------- /aes_hw/bin/vga_display.h: -------------------------------------------------------------------------------- 1 | /* 2 | * vga_display.h 3 | * 4 | * Created on: Dec 8, 2017 5 | * Author: 695r24 6 | */ 7 | 8 | #ifndef VGA_DISPLAY_H_ 9 | #define VGA_DISPLAY_H_ 10 | 11 | void pixel_vga_display(alt_up_pixel_buffer_dma_dev *pixel_buffer, unsigned int *pixel, int32_t imsize_x, int32_t imsize_y) 12 | { 13 | register unsigned int addr; 14 | register unsigned int limit_x; 15 | register unsigned int limit_y; 16 | 17 | addr = pixel_buffer->buffer_start_address; 18 | limit_x = pixel_buffer->x_resolution; 19 | limit_x = limit_x << 1;//since i am converting the 32 bit to 16 bit pixel 20 | limit_y = pixel_buffer->y_resolution; 21 | 22 | register int x = 0; 23 | register int y = 0; 24 | register int i = 0; 25 | 26 | for (y = 0; y < limit_y; y++) 27 | { 28 | for (x = 0; x < limit_x; x = x+2) 29 | { 30 | if(x < imsize_x && y < imsize_y) 31 | { 32 | IOWR_16DIRECT(addr, x << 1, (pixel[i]>>16)); 33 | IOWR_16DIRECT(addr, (x+1) << 1, (pixel[i] & 0xFFFF)); 34 | i++; 35 | } 36 | else 37 | { 38 | IOWR_16DIRECT(addr, x<<1, 0xF81F); 39 | IOWR_16DIRECT(addr, (x+1)<<1, 0xF81F); 40 | } 41 | } 42 | addr = addr + limit_x; 43 | } 44 | } 45 | 46 | 47 | 48 | #endif /* VGA_DISPLAY_H_ */ 49 | --------------------------------------------------------------------------------