├── MyCodes └── axi_ip │ ├── rtl │ └── pcores │ │ ├── axi_lite_master_v1_00_a │ │ ├── data │ │ │ ├── axi_lite_master_v2_1_0.mpd │ │ │ ├── axi_lite_master_v2_1_0.mui │ │ │ └── axi_lite_master_v2_1_0.pao │ │ └── hdl │ │ │ ├── verilog │ │ │ ├── axi_lite_master.v │ │ │ └── axi_lite_master_template.v │ │ │ └── vhdl │ │ │ └── axi_lite_master.vhd │ │ ├── axi_lite_slave_v1_00_a │ │ ├── data │ │ │ ├── axi_lite_slave_v2_1_0.mpd │ │ │ ├── axi_lite_slave_v2_1_0.mui │ │ │ └── axi_lite_slave_v2_1_0.pao │ │ └── hdl │ │ │ ├── verilog │ │ │ └── axi_lite_slave.v │ │ │ └── vhdl │ │ │ └── axi_lite_slave.vhd │ │ ├── axi_master_v1_00_a │ │ ├── data │ │ │ ├── axi_master_v2_1_0.mpd │ │ │ ├── axi_master_v2_1_0.mui │ │ │ └── axi_master_v2_1_0.pao │ │ └── hdl │ │ │ ├── verilog │ │ │ └── axi_master.v │ │ │ └── vhdl │ │ │ └── axi_master.vhd │ │ ├── axi_slave_v1_00_a │ │ ├── data │ │ │ ├── axi_slave_v2_1_0.mpd │ │ │ ├── axi_slave_v2_1_0.mui │ │ │ └── axi_slave_v2_1_0.pao │ │ └── hdl │ │ │ ├── verilog │ │ │ └── axi_slave.v │ │ │ └── vhdl │ │ │ └── axi_slave.vhd │ │ └── axi_stream_v1_00_a │ │ ├── data │ │ ├── axi_stream_v2_1_0.mpd │ │ ├── axi_stream_v2_1_0.mui │ │ └── axi_stream_v2_1_0.pao │ │ └── hdl │ │ └── vhdl │ │ └── axi_stream.vhd │ ├── run │ ├── compile_verilog.sh │ ├── filelist.v │ ├── run.sh │ └── transcript │ └── verification │ └── tb_axi_lite.v └── README.md /MyCodes/axi_ip/rtl/pcores/axi_lite_master_v1_00_a/data/axi_lite_master_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | #-- DISCLAIMER OF LIABILITY 2 | #-- 3 | #-- This file contains proprietary and confidential information of 4 | #-- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | #-- from Xilinx, and may be used, copied and/or disclosed only 6 | #-- pursuant to the terms of a valid license agreement with Xilinx. 7 | #-- 8 | #-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | #-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | #-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | #-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | #-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | #-- does not warrant that functions included in the Materials will 14 | #-- meet the requirements of Licensee, or that the operation of the 15 | #-- Materials will be uninterrupted or error-free, or that defects 16 | #-- in the Materials will be corrected. Furthermore, Xilinx does 17 | #-- not warrant or make any representations regarding use, or the 18 | #-- results of the use, of the Materials in terms of correctness, 19 | #-- accuracy, reliability or otherwise. 20 | #-- 21 | #-- Xilinx products are not designed or intended to be fail-safe, 22 | #-- or for use in any application requiring fail-safe performance, 23 | #-- such as life-support or safety devices or systems, Class III 24 | #-- medical devices, nuclear facilities, applications related to 25 | #-- the deployment of airbags, or any other applications that could 26 | #-- lead to death, personal injury or severe property or 27 | #-- environmental damage (individually and collectively, "critical 28 | #-- applications"). Customer assumes the sole risk and liability 29 | #-- of any use of Xilinx products in critical applications, 30 | #-- subject only to applicable laws and regulations governing 31 | #-- limitations on product liability. 32 | #-- 33 | #-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 34 | #-- 35 | #-- This disclaimer and copyright notice must be retained as part 36 | #-- of this file at all times. 37 | #-- 38 | ################################################################### 39 | ## 40 | ## Name : axi_lite_master 41 | ## Desc : Microprocessor Peripheral Description 42 | ## : Automatically generated by PsfUtility 43 | ## 44 | ################################################################### 45 | 46 | BEGIN axi_lite_master 47 | 48 | ## Peripheral Options 49 | OPTION IPTYPE = PERIPHERAL 50 | OPTION IMP_NETLIST = TRUE 51 | OPTION STYLE = HDL 52 | OPTION DESC = AXI Lite Master 53 | OPTION LONG_DESC = AXI4-Lite Master 54 | OPTION HDL = MIXED 55 | OPTION RUN_NGCBUILD = FALSE 56 | 57 | ## Bus Interfaces 58 | BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER 59 | 60 | ## Generics for VHDL or Parameters for Verilog 61 | PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI 62 | PARAMETER C_M_AXI_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI 63 | PARAMETER C_M_AXI_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = M_AXI 64 | PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_AXI 65 | PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_AXI 66 | 67 | ## Ports 68 | PORT M_AXI_ACLK = "", BUS = M_AXI, DIR = I, SIGIS = CLK 69 | PORT M_AXI_ARESETN = ARESETN, BUS = M_AXI, DIR = I, SIGIS = RST 70 | PORT M_AXI_AWADDR = AWADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0] 71 | PORT M_AXI_AWPROT = AWPROT, BUS = M_AXI, DIR = O, VEC = [2:0] 72 | PORT M_AXI_AWVALID = AWVALID, BUS = M_AXI, DIR = O 73 | PORT M_AXI_AWREADY = AWREADY, BUS = M_AXI, DIR = I 74 | PORT M_AXI_WDATA = WDATA, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0] 75 | PORT M_AXI_WSTRB = WSTRB, BUS = M_AXI, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8) -1):0] 76 | PORT M_AXI_WVALID = WVALID, BUS = M_AXI, DIR = O 77 | PORT M_AXI_WREADY = WREADY, BUS = M_AXI, DIR = I 78 | PORT M_AXI_BRESP = BRESP, BUS = M_AXI, DIR = I, VEC = [1:0] 79 | PORT M_AXI_BVALID = BVALID, BUS = M_AXI, DIR = I 80 | PORT M_AXI_BREADY = BREADY, BUS = M_AXI, DIR = O 81 | PORT M_AXI_ARADDR = ARADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0 82 | PORT M_AXI_ARPROT = ARPROT, BUS = M_AXI, DIR = O, VEC = [2:0] 83 | PORT M_AXI_ARVALID = ARVALID, BUS = M_AXI, DIR = O 84 | PORT M_AXI_ARREADY = ARREADY, BUS = M_AXI, DIR = I 85 | PORT M_AXI_RDATA = RDATA, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0] 86 | PORT M_AXI_RRESP = RRESP, BUS = M_AXI, DIR = I, VEC = [1:0] 87 | PORT M_AXI_RVALID = RVALID, BUS = M_AXI, DIR = I 88 | PORT M_AXI_RREADY = RREADY, BUS = M_AXI, DIR = O 89 | 90 | #Example Ports 91 | PORT DONE_SUCCESS = "", DIR = O 92 | 93 | END 94 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_master_v1_00_a/data/axi_lite_master_v2_1_0.mui: -------------------------------------------------------------------------------- 1 | 2 | 3 | 45 | 46 | 48 | 49 | 51 | C_M_AXI_ADDR_WIDTH 52 | 53 | 54 | 55 | '> 56 | 58 | C_M_AXI_DATA_WIDTH 59 | 60 | 61 | 62 | '> 63 | 65 | C_M_AXI_PROTOCOL 66 | 67 | 68 | 69 | '> 70 | 72 | C_M_AXI_SUPPORTS_READ 73 | 74 | 75 | 76 | '> 77 | 79 | C_M_AXI_SUPPORTS_WRITE 80 | 81 | 82 | 83 | '> 84 | 85 | 86 | ]> 87 | 88 | 89 | 90 | User 91 | 92 | Common 93 | &C_M_AXI_PROTOCOL; 94 | 95 | 96 | 97 | System 98 | 99 | AXI 100 | &C_M_AXI_ADDR_WIDTH; 101 | &C_M_AXI_DATA_WIDTH; 102 | &C_M_AXI_SUPPORTS_READ; 103 | &C_M_AXI_SUPPORTS_WRITE; 104 | 105 | 106 | 107 | 108 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_master_v1_00_a/data/axi_lite_master_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ## -- DISCLAIMER OF LIABILITY 2 | ## -- 3 | ## -- This file contains proprietary and confidential information of 4 | ## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | ## -- from Xilinx, and may be used, copied and/or disclosed only 6 | ## -- pursuant to the terms of a valid license agreement with Xilinx. 7 | ## -- 8 | ## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | ## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | ## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | ## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | ## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | ## -- does not warrant that functions included in the Materials will 14 | ## -- meet the requirements of Licensee, or that the operation of the 15 | ## -- Materials will be uninterrupted or error-free, or that defects 16 | ## -- in the Materials will be corrected. Furthermore, Xilinx does 17 | ## -- not warrant or make any representations regarding use, or the 18 | ## -- results of the use, of the Materials in terms of correctness, 19 | ## -- accuracy, reliability or otherwise. 20 | ## -- 21 | ## -- Xilinx products are not designed or intended to be fail-safe, 22 | ## -- or for use in any application requiring fail-safe performance, 23 | ## -- such as life-support or safety devices or systems, Class III 24 | ## -- medical devices, nuclear facilities, applications related to 25 | ## -- the deployment of airbags, or any other applications that could 26 | ## -- lead to death, personal injury or severe property or 27 | ## -- environmental damage (individually and collectively, "critical 28 | ## -- applications"). Customer assumes the sole risk and liability 29 | ## -- of any use of Xilinx products in critical applications, 30 | ## -- subject only to applicable laws and regulations governing 31 | ## -- limitations on product liability. 32 | ## -- 33 | ## -- Copyright 2009 Xilinx, Inc. 34 | ## -- All rights reserved. 35 | ## -- 36 | ## -- This disclaimer and copyright notice must be retained as part 37 | ## -- of this file at all times. 38 | ## 39 | ############################################################################### 40 | ## 41 | ## axi_master_v1_00_a.pao 42 | ## 43 | ## Peripheral Analyze Order File 44 | ## 45 | ## 46 | ############################################################################### 47 | 48 | 49 | #lib axi_lite_master_v1_00_a axi_lite_master.vhd vhdl 50 | lib axi_lite_master_v1_00_a axi_lite_master.v verilog 51 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_master_v1_00_a/hdl/verilog/axi_lite_master.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // AXI4-Lite Master 4 | // 5 | //////////////////////////////////////////////////////////////////////////// 6 | // 7 | // Structure: 8 | // axi_lite_master 9 | // 10 | // Last Update: 11 | // 7/8/2010 12 | //////////////////////////////////////////////////////////////////////////// 13 | /* 14 | AXI4-Lite Master Example 15 | 16 | The purpose of this design is to provide a simple AXI4-Lite example. 17 | 18 | The distinguishing characteristics of AXI4-Lite are the single-beat transfers, 19 | limited data width, and limited other transaction qualifiers. These make it 20 | best suited for low-throughput control functions. 21 | 22 | The example user application will perform a set of writes from a lookup 23 | table. This may be useful for initial register configurations, such as 24 | setting the AXI_VDMA register settings. After completing all the writes, 25 | the example design will perform reads and attempt to verify the values. 26 | 27 | If the reads match the write values and no error responses were captured, 28 | the DONE_SUCCESS output will be asserted. 29 | 30 | To modify this example for other applications, edit/remove the logic 31 | associated with the 'Example' section comments. Generally, this example 32 | works by the user providing a 'push_write' or 'pop_read' command to initiate 33 | a command and data transfer. 34 | 35 | The latest version of this file can be found in Xilinx Answer 37425 36 | http://www.xilinx.com/support/answers/37425.htm 37 | */ 38 | `timescale 1ns/1ps 39 | 40 | module axi_lite_master # 41 | ( 42 | parameter integer C_M_AXI_ADDR_WIDTH = 32, 43 | parameter integer C_M_AXI_DATA_WIDTH = 32, 44 | parameter C_NUM_COMMANDS = 16, 45 | parameter READ_WRITE_ADDR = 32'h88000000 46 | ) 47 | ( 48 | // System Signals 49 | input wire M_AXI_ACLK, 50 | input wire M_AXI_ARESETN, 51 | 52 | // Master Interface Write Address 53 | output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, 54 | output wire [3-1:0] M_AXI_AWPROT, 55 | output wire M_AXI_AWVALID, 56 | input wire M_AXI_AWREADY, 57 | 58 | // Master Interface Write Data 59 | output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, 60 | output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, 61 | output wire M_AXI_WVALID, 62 | input wire M_AXI_WREADY, 63 | 64 | // Master Interface Write Response 65 | input wire [2-1:0] M_AXI_BRESP, 66 | input wire M_AXI_BVALID, 67 | output wire M_AXI_BREADY, 68 | 69 | // Master Interface Read Address 70 | output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, 71 | output wire [3-1:0] M_AXI_ARPROT, 72 | output wire M_AXI_ARVALID, 73 | input wire M_AXI_ARREADY, 74 | 75 | // Master Interface Read Data 76 | input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, 77 | input wire [2-1:0] M_AXI_RRESP, 78 | input wire M_AXI_RVALID, 79 | output wire M_AXI_RREADY, 80 | 81 | //Example Output 82 | output wire DONE_SUCCESS, 83 | input wire start_input_gpio, 84 | 85 | //Test Ports 86 | output wire test_awvalid, 87 | output wire [31:0] test_awaddr, 88 | output wire [31:0] test_wdata, 89 | output wire test_wvalid, 90 | output wire test_bready, 91 | output wire test_bvalid, 92 | output wire test_rready, 93 | output wire [31:0] test_araddr, 94 | output wire test_arvalid, 95 | output wire [31:0] test_rdata, 96 | output wire test_rvalid 97 | ); 98 | 99 | // AXI4 signals 100 | reg awvalid; 101 | reg wvalid; 102 | reg push_write; 103 | reg pop_read; 104 | reg arvalid; 105 | reg rready; 106 | reg bready; 107 | reg [31:0] awaddr; 108 | reg [31:0] wdata; 109 | reg [31:0] araddr; 110 | wire write_resp_error; 111 | wire read_resp_error; 112 | 113 | wire [31:0] rdata; 114 | 115 | 116 | 117 | //Example-specific design signals 118 | reg writes_done; 119 | reg reads_done; 120 | reg error_reg; 121 | reg [31:0] write_index; 122 | reg [31:0] read_index; 123 | reg [31:0] check_rdata; 124 | reg done_success_int; 125 | wire read_mismatch; 126 | wire last_write; 127 | wire last_read; 128 | 129 | ///////////////// 130 | //I/O Connections 131 | ///////////////// 132 | //TEST Port 133 | assign test_awvalid = awvalid; 134 | assign test_awaddr = awaddr ; 135 | assign test_wdata = wdata; 136 | assign test_wvalid = wvalid; 137 | assign test_bready = bready; 138 | assign test_bvalid = M_AXI_BVALID; 139 | assign test_rready = rready; 140 | assign test_araddr = araddr ; 141 | assign test_arvalid = arvalid ; 142 | assign test_rdata = M_AXI_RDATA; 143 | assign test_rvalid = M_AXI_RVALID; 144 | 145 | //////////////////// 146 | //Write Address (AW) 147 | //////////////////// 148 | assign M_AXI_AWADDR = awaddr; 149 | 150 | assign M_AXI_WDATA = wdata; 151 | assign M_AXI_AWPROT = 3'h0; 152 | assign M_AXI_AWVALID = awvalid; 153 | 154 | /////////////// 155 | //Write Data(W) 156 | /////////////// 157 | assign M_AXI_WVALID = wvalid; 158 | 159 | //Set all byte strobes in this example 160 | assign M_AXI_WSTRB = -1; 161 | 162 | //////////////////// 163 | //Write Response (B) 164 | //////////////////// 165 | assign M_AXI_BREADY = bready; 166 | 167 | /////////////////// 168 | //Read Address (AR) 169 | /////////////////// 170 | assign M_AXI_ARADDR = araddr; 171 | assign M_AXI_ARVALID = arvalid; 172 | assign M_AXI_ARPROT = 3'b0; 173 | 174 | //////////////////////////// 175 | //Read and Read Response (R) 176 | //////////////////////////// 177 | assign M_AXI_RREADY = rready; 178 | 179 | //////////////////// 180 | //Example design I/O 181 | //////////////////// 182 | assign DONE_SUCCESS = done_success_int; 183 | 184 | assign reset_start = M_AXI_ARESETN && start_input_gpio ; 185 | 186 | /////////////////////// 187 | //Write Address Channel 188 | /////////////////////// 189 | /* 190 | The purpose of the write address channel is to request the address and 191 | command information for the entire transaction. It is a single beat 192 | of information. 193 | 194 | Note for this example the awvalid/wvalid are asserted at the same 195 | time, and then each is deasserted independent from each other. 196 | This is a lower-performance, but simplier control scheme. 197 | 198 | AXI VALID signals must be held active until accepted by the partner. 199 | 200 | A data transfer is accepted by the slave when a master has 201 | VALID data and the slave acknoledges it is also READY. While the master 202 | is allowed to generated multiple, back-to-back requests by not 203 | deasserting VALID, this design will add an extra rest cycle for 204 | simplicity. 205 | 206 | Since only one outstanding transaction is issued by the user design, 207 | there will not be a collision between a new request and an accepted 208 | request on the same clock cycle. Otherwise, an additional clause is 209 | necessary. 210 | */ 211 | always @(posedge M_AXI_ACLK) 212 | begin 213 | 214 | //Only VALID signals must be deasserted during reset per AXI spec 215 | //Consider inverting then registering active-low reset for higher fmax 216 | 217 | if (reset_start == 0) 218 | awvalid <= 1'b0; 219 | 220 | //Address accepted by interconnect/slave 221 | else if (M_AXI_AWREADY && awvalid) 222 | awvalid <= 1'b0; 223 | 224 | //Signal a new address/data command is available by user logic 225 | else if (push_write) 226 | awvalid <= 1'b1; 227 | else 228 | awvalid <= awvalid; 229 | end 230 | 231 | //////////////////// 232 | //Write Data Channel 233 | //////////////////// 234 | /* 235 | The write data channel is for transfering the actual data. 236 | 237 | The data generation is specific to the example design, and 238 | so only the WVALID/WREADY handshake is shown here 239 | */ 240 | always @(posedge M_AXI_ACLK) 241 | begin 242 | 243 | if ( reset_start == 0) 244 | wvalid <= 1'b0; 245 | 246 | //Data accepted by interconnect/slave 247 | else if (M_AXI_WREADY && wvalid) 248 | wvalid <= 1'b0; 249 | 250 | //Signal a new address/data command is available by user logic 251 | else if (push_write) 252 | wvalid <= 1'b1; 253 | else 254 | wvalid <= awvalid; 255 | end 256 | 257 | //////////////////////////// 258 | //Write Response (B) Channel 259 | //////////////////////////// 260 | /* 261 | The write response channel provides feedback that the write has committed 262 | to memory. BREADY will occur after both the data and the write address 263 | has arrived and been accepted by the slave, and can guarantee that no 264 | other accesses launched afterwards will be able to be reordered before it. 265 | 266 | The BRESP bit [1] is used indicate any errors from the interconnect or 267 | slave for the entire write burst. This example will capture the error. 268 | 269 | While not necessary per spec, it is advisable to reset READY signals in 270 | case of differing reset latencies between master/slave. 271 | */ 272 | 273 | //Always accept write responses 274 | always @(posedge M_AXI_ACLK) 275 | begin 276 | 277 | if (reset_start == 0) 278 | bready <= 1'b0; 279 | else 280 | bready <= 1'b1; 281 | end 282 | 283 | //Flag write errors 284 | assign write_resp_error = bready & M_AXI_BVALID & M_AXI_BRESP[1]; 285 | 286 | ////////////////////// 287 | //Read Address Channel 288 | ////////////////////// 289 | always @(posedge M_AXI_ACLK) 290 | begin 291 | 292 | if (reset_start == 0) 293 | arvalid <= 1'b0; 294 | else if (M_AXI_ARREADY && arvalid) 295 | arvalid <= 1'b0; 296 | else if (pop_read) 297 | arvalid <= 1'b1; 298 | else 299 | arvalid <= arvalid; 300 | end 301 | 302 | ////////////////////////////////// 303 | //Read Data (and Response) Channel 304 | ////////////////////////////////// 305 | /* 306 | The Read Data channel returns the results of the read request 307 | 308 | In this example the data checker is always able to accept 309 | more data, so no need to throttle the RREADY signal. 310 | 311 | While not necessary per spec, it is advisable to reset READY signals in 312 | case of differing reset latencies between master/slave. 313 | */ 314 | always @(posedge M_AXI_ACLK) 315 | begin 316 | 317 | if (reset_start == 0) 318 | rready <= 1'b0; 319 | else 320 | rready <= 1'b1; 321 | end 322 | 323 | //Flag write errors 324 | assign read_resp_error = rready & M_AXI_RVALID & M_AXI_RRESP[1]; 325 | 326 | //////////// 327 | //User Logic 328 | //////////// 329 | /////////////////////// 330 | //Address/Data Stimulus 331 | /////////////////////// 332 | /* 333 | Address/data pairs for this example. The read and write values should 334 | match. 335 | 336 | Modify these as desired for different address patterns. 337 | */ 338 | 339 | //Number of address/data pairs specificed below 340 | //parameter C_NUM_COMMANDS = 3; 341 | //Write Addresses 342 | always @(write_index) 343 | begin 344 | awaddr <= READ_WRITE_ADDR+ ((write_index-1)*4) ; 345 | //case (write_index) 346 | // 1: awaddr <= 32'h00000000; 347 | // 2: awaddr <= 32'h00000004; 348 | // 3: awaddr <= 32'h00000008; 349 | // default: awaddr <= 32'h00000000; 350 | //endcase 351 | end 352 | 353 | //Read Addresses 354 | always @(read_index) 355 | begin 356 | araddr <= READ_WRITE_ADDR + ((read_index-1)*4) ; 357 | // case (read_index) 358 | // 1: araddr <= 32'h00000000; 359 | // 2: araddr <= 32'h00000004; 360 | // 3: araddr <= 32'h00000008; 361 | // default: araddr <= 32'h00000000; 362 | // endcase 363 | end 364 | 365 | //Write data 366 | always @(write_index) 367 | begin 368 | wdata <= write_index ; 369 | //case (write_index) 370 | //1: wdata <= 32'h11111111; 371 | //2: wdata <= 32'h22222222; 372 | //3: wdata <= 32'h33333333; 373 | //default: wdata <= 32'h00000000; 374 | //endcase 375 | end 376 | 377 | //Expected read data 378 | always @(read_index) 379 | begin 380 | check_rdata <= read_index ; 381 | //case (read_index) 382 | // 1: check_rdata <= 32'h11111111; 383 | // 2: check_rdata <= 32'h22222222; 384 | // 3: check_rdata <= 32'h33333333; 385 | // default: check_rdata <= 32'h00000000; 386 | //endcase 387 | end 388 | 389 | /////////////////////// 390 | //Main write controller 391 | /////////////////////// 392 | /* 393 | By only issuing one request at a time, the control logic is 394 | simplified. 395 | 396 | Request a new write if: 397 | -A command was not just submitted 398 | -AW and W channels are both idle 399 | -A new request was not requested last cycle 400 | */ 401 | always @(posedge M_AXI_ACLK) 402 | begin 403 | 404 | if (reset_start == 0) 405 | begin 406 | push_write <= 1'b0; 407 | write_index <= 0; 408 | end 409 | 410 | //Request new write and increment write commmand counter 411 | else if (~awvalid && ~wvalid && ~last_write && ~push_write) 412 | begin 413 | push_write <= 1'b1; 414 | write_index <= write_index + 1; 415 | end 416 | else 417 | begin 418 | push_write <= 1'b0; //Negate to generate a pulse 419 | write_index <= write_index; 420 | end 421 | end 422 | 423 | //Terminal write count 424 | assign last_write = (write_index == C_NUM_COMMANDS); 425 | /* 426 | Check for last write completion. 427 | 428 | This logic is to qualify the last write count with the final write 429 | response. This demonstrates how to confirm that a write has been 430 | committed. 431 | */ 432 | always @(posedge M_AXI_ACLK) 433 | begin 434 | 435 | if (reset_start == 0) 436 | writes_done <= 1'b0; 437 | 438 | //The last write should be associated with a valid response 439 | else if (last_write && M_AXI_BVALID) 440 | writes_done <= 1'b1; 441 | else 442 | writes_done <= writes_done; 443 | end 444 | 445 | ////////////// 446 | //Read example 447 | ////////////// 448 | 449 | //Terminal Read Count 450 | assign last_read = (read_index == C_NUM_COMMANDS); 451 | 452 | ////////////////////// 453 | //Main read controller 454 | ////////////////////// 455 | /* 456 | Request a new read if: 457 | -A command was not just submitted 458 | -AR channel is idle 459 | -A new request was not requested last cycle 460 | */ 461 | always @(posedge M_AXI_ACLK) 462 | begin 463 | 464 | //Need to wait for last write to be committed 465 | if (reset_start == 0 || writes_done == 0) 466 | begin 467 | pop_read <= 1'b0; 468 | read_index <= 0; 469 | end 470 | 471 | //Request new read and increment read commmand counter 472 | else if (~arvalid && ~last_read && ~pop_read) 473 | begin 474 | pop_read <= 1'b1; 475 | read_index <= read_index + 1; 476 | end 477 | else 478 | begin 479 | pop_read <= 1'b0; 480 | read_index <= read_index; 481 | end 482 | end 483 | 484 | /* 485 | Check for last read completion. 486 | 487 | This logic is to qualify the last read count with the final read 488 | response/data. 489 | */ 490 | always @(posedge M_AXI_ACLK) 491 | begin 492 | 493 | if (reset_start == 0) 494 | reads_done <= 1'b0; 495 | 496 | //The last read should be associated with a read valid response 497 | else if (last_read && M_AXI_RVALID) 498 | reads_done <= 1'b1; 499 | else 500 | reads_done <= reads_done; 501 | end 502 | 503 | /////////////////////////////// 504 | //Example design error register 505 | /////////////////////////////// 506 | 507 | //Data Comparison 508 | assign read_mismatch = ((M_AXI_RVALID && rready) && (M_AXI_RDATA != check_rdata)); 509 | 510 | // Register and hold any data mismatches, or read/write interface errors 511 | always @(posedge M_AXI_ACLK) 512 | begin 513 | 514 | if (reset_start == 0) 515 | error_reg <= 1'b0; 516 | 517 | //Capture any error types 518 | else if (read_mismatch || write_resp_error || read_resp_error) 519 | error_reg <= 1'b1; 520 | else 521 | error_reg <= error_reg; 522 | end 523 | 524 | ///////////////////////////////////////// 525 | //DONE_SUCCESS output example calculation 526 | ///////////////////////////////////////// 527 | always @(posedge M_AXI_ACLK) 528 | begin 529 | 530 | if (reset_start == 0 ) 531 | done_success_int <= 1'b0; 532 | 533 | //Are both writes and read done without error? 534 | else if (writes_done && reads_done && ~error_reg) 535 | done_success_int <= 1'b1; 536 | else 537 | done_success_int <= done_success_int; 538 | end 539 | 540 | endmodule 541 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_master_v1_00_a/hdl/verilog/axi_lite_master_template.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // AXI4/Lite Master 4 | // 5 | //////////////////////////////////////////////////////////////////////////// 6 | // 7 | // Structure: 8 | // axi_lite_master 9 | // 10 | //////////////////////////////////////////////////////////////////////////// 11 | 12 | `timescale 1ns/1ps 13 | 14 | module axi_lite_master # 15 | ( 16 | parameter integer C_M_AXI_ADDR_WIDTH = 32, 17 | parameter integer C_M_AXI_DATA_WIDTH = 32 18 | ) 19 | ( 20 | // System Signals 21 | input wire M_AXI_ACLK, 22 | input wire M_AXI_ARESETN, 23 | 24 | // Master Interface Write Address 25 | output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, 26 | output wire [3-1:0] M_AXI_AWPROT, 27 | output wire M_AXI_AWVALID, 28 | input wire M_AXI_AWREADY, 29 | 30 | // Master Interface Write Data 31 | output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, 32 | output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, 33 | output wire M_AXI_WVALID, 34 | input wire M_AXI_WREADY, 35 | 36 | // Master Interface Write Response 37 | input wire [2-1:0] M_AXI_BRESP, 38 | input wire M_AXI_BVALID, 39 | output wire M_AXI_BREADY, 40 | 41 | // Master Interface Read Address 42 | output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, 43 | output wire [3-1:0] M_AXI_ARPROT, 44 | output wire M_AXI_ARVALID, 45 | input wire M_AXI_ARREADY, 46 | 47 | // Master Interface Read Data 48 | input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, 49 | input wire [2-1:0] M_AXI_RRESP, 50 | input wire M_AXI_RVALID, 51 | output wire M_AXI_RREADY 52 | ); 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_master_v1_00_a/hdl/vhdl/axi_lite_master.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- AXI4-Lite Master 4 | -- 5 | -- VHDL-Standard: VHDL'93 6 | ---------------------------------------------------------------------------- 7 | -- 8 | -- Structure: 9 | -- axi_lite_master 10 | -- 11 | ---------------------------------------------------------------------------- 12 | 13 | library ieee; 14 | use ieee.std_logic_1164.all; 15 | use ieee.numeric_std.all; 16 | use ieee.std_logic_misc.all; 17 | 18 | --library unisim; 19 | --use unisim.vcomponents.all; 20 | 21 | entity axi_lite_master is 22 | generic( 23 | C_M_AXI_ADDR_WIDTH : integer := 32; 24 | C_M_AXI_DATA_WIDTH : integer := 32 25 | ); 26 | port( 27 | -- System Signals 28 | M_AXI_ACLK : in std_logic; 29 | M_AXI_ARESETN : in std_logic; 30 | 31 | -- Master Interface Write Address 32 | M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); 33 | M_AXI_AWPROT : out std_logic_vector(3-1 downto 0); 34 | M_AXI_AWVALID : out std_logic; 35 | M_AXI_AWREADY : in std_logic; 36 | 37 | -- Master Interface Write Data 38 | M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); 39 | M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0); 40 | M_AXI_WVALID : out std_logic; 41 | M_AXI_WREADY : in std_logic; 42 | 43 | -- Master Interface Write Response 44 | M_AXI_BRESP : in std_logic_vector(2-1 downto 0); 45 | M_AXI_BVALID : in std_logic; 46 | M_AXI_BREADY : out std_logic; 47 | 48 | -- Master Interface Read Address 49 | 50 | M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); 51 | M_AXI_ARPROT : out std_logic_vector(3-1 downto 0); 52 | M_AXI_ARVALID : out std_logic; 53 | M_AXI_ARREADY : in std_logic; 54 | 55 | -- Master Interface Read Data 56 | M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); 57 | M_AXI_RRESP : in std_logic_vector(2-1 downto 0); 58 | M_AXI_RVALID : in std_logic; 59 | M_AXI_RREADY : out std_logic 60 | 61 | ); 62 | 63 | end axi_lite_master; 64 | 65 | ------------------------------------------------------------------------------- 66 | -- Architecture 67 | ------------------------------------------------------------------------------- 68 | architecture implementation of axi_lite_master is 69 | begin 70 | end implementation; 71 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_slave_v1_00_a/data/axi_lite_slave_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | #-- DISCLAIMER OF LIABILITY 2 | #-- 3 | #-- This file contains proprietary and confidential information of 4 | #-- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | #-- from Xilinx, and may be used, copied and/or disclosed only 6 | #-- pursuant to the terms of a valid license agreement with Xilinx. 7 | #-- 8 | #-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | #-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | #-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | #-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | #-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | #-- does not warrant that functions included in the Materials will 14 | #-- meet the requirements of Licensee, or that the operation of the 15 | #-- Materials will be uninterrupted or error-free, or that defects 16 | #-- in the Materials will be corrected. Furthermore, Xilinx does 17 | #-- not warrant or make any representations regarding use, or the 18 | #-- results of the use, of the Materials in terms of correctness, 19 | #-- accuracy, reliability or otherwise. 20 | #-- 21 | #-- Xilinx products are not designed or intended to be fail-safe, 22 | #-- or for use in any application requiring fail-safe performance, 23 | #-- such as life-support or safety devices or systems, Class III 24 | #-- medical devices, nuclear facilities, applications related to 25 | #-- the deployment of airbags, or any other applications that could 26 | #-- lead to death, personal injury or severe property or 27 | #-- environmental damage (individually and collectively, "critical 28 | #-- applications"). Customer assumes the sole risk and liability 29 | #-- of any use of Xilinx products in critical applications, 30 | #-- subject only to applicable laws and regulations governing 31 | #-- limitations on product liability. 32 | #-- 33 | #-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 34 | #-- 35 | #-- This disclaimer and copyright notice must be retained as part 36 | #-- of this file at all times. 37 | #-- 38 | ################################################################### 39 | ## 40 | ## Name : axi_slave 41 | ## Desc : Microprocessor Peripheral Description 42 | ## : Automatically generated by PsfUtility 43 | ## 44 | ################################################################### 45 | 46 | BEGIN axi_lite_slave 47 | 48 | ## Peripheral Options 49 | OPTION IPTYPE = PERIPHERAL 50 | OPTION IMP_NETLIST = TRUE 51 | OPTION STYLE = HDL 52 | OPTION DESC = AXI Lite Slave 53 | OPTION LONG_DESC = AXI4-Lite Slave 54 | OPTION HDL = MIXED 55 | OPTION RUN_NGCBUILD = FALSE 56 | 57 | ## Bus Interfaces 58 | BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE 59 | 60 | ## Generics for VHDL or Parameters for Verilog 61 | PARAMETER C_S_AXI_BASE_ADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_HIGH_ADDR, MIN_SIZE = 0x10000 62 | PARAMETER C_S_AXI_HIGH_ADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_BASE_ADDR, 63 | PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI 64 | PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI 65 | PARAMETER C_S_AXI_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = S_AXI 66 | PARAMETER C_S_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI 67 | PARAMETER C_S_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI 68 | #PARAMETER C_S_AXI_NUM_ADDR_RANGES = 1, BUS = S_AXI, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4) 69 | #PARAMETER C_S_AXI_RNG00_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG00_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000 70 | #PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG00_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL 71 | #PARAMETER C_S_AXI_RNG01_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG01_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000 72 | #PARAMETER C_S_AXI_RNG01_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG01_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL 73 | #PARAMETER C_S_AXI_RNG02_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG02_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000 74 | #PARAMETER C_S_AXI_RNG02_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG02_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL 75 | #PARAMETER C_S_AXI_RNG03_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG03_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000 76 | #PARAMETER C_S_AXI_RNG03_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG03_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL 77 | 78 | ## Ports 79 | PORT ACLK = "", BUS = S_AXI, DIR = I, SIGIS = CLK 80 | PORT ARESETN = ARESETN, BUS = S_AXI, DIR = I, SIGIS = RST 81 | PORT S_AXI_AWADDR = AWADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0] 82 | PORT S_AXI_AWPROT = AWPROT, BUS = S_AXI, DIR = I, VEC = [2:0] 83 | PORT S_AXI_AWVALID = AWVALID, BUS = S_AXI, DIR = I 84 | PORT S_AXI_AWREADY = AWREADY, BUS = S_AXI, DIR = O 85 | PORT S_AXI_WDATA = WDATA, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0] 86 | PORT S_AXI_WSTRB = WSTRB, BUS = S_AXI, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8) -1):0] 87 | PORT S_AXI_WVALID = WVALID, BUS = S_AXI, DIR = I 88 | PORT S_AXI_WREADY = WREADY, BUS = S_AXI, DIR = O 89 | PORT S_AXI_BRESP = BRESP, BUS = S_AXI, DIR = O, VEC = [1:0] 90 | PORT S_AXI_BVALID = BVALID, BUS = S_AXI, DIR = O 91 | PORT S_AXI_BREADY = BREADY, BUS = S_AXI, DIR = I 92 | PORT S_AXI_ARADDR = ARADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0 93 | PORT S_AXI_ARPROT = ARPROT, BUS = S_AXI, DIR = I, VEC = [2:0] 94 | PORT S_AXI_ARVALID = ARVALID, BUS = S_AXI, DIR = I 95 | PORT S_AXI_ARREADY = ARREADY, BUS = S_AXI, DIR = O 96 | PORT S_AXI_RDATA = RDATA, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0] 97 | PORT S_AXI_RRESP = RRESP, BUS = S_AXI, DIR = O, VEC = [1:0] 98 | PORT S_AXI_RVALID = RVALID, BUS = S_AXI, DIR = O 99 | PORT S_AXI_RREADY = RREADY, BUS = S_AXI, DIR = I 100 | 101 | END 102 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_slave_v1_00_a/data/axi_lite_slave_v2_1_0.mui: -------------------------------------------------------------------------------- 1 | 2 | 3 | 42 | 43 | 46 | C_S_AXI_ADDR_WIDTH 47 | 48 | 49 | 50 | '> 51 | 53 | C_S_AXI_DATA_WIDTH 54 | 55 | 56 | 57 | '> 58 | 60 | C_S_AXI_PROTOCOL 61 | 62 | 63 | 64 | '> 65 | 66 | 68 | C_S_AXI_SUPPORTS_READ 69 | 70 | 71 | 72 | '> 73 | 75 | C_S_AXI_SUPPORTS_WRITE 76 | 77 | 78 | 79 | '> 80 | 82 | C_S_AXI_NUM_ADDR_RANGES 83 | 84 | 85 | 86 | '> 87 | 89 | C_S_AXI_RNG00_BASEADDR 90 | 91 | 92 | 93 | '> 94 | 96 | C_S_AXI_RNG00_HIGHADDR 97 | 98 | 99 | 100 | '> 101 | 103 | C_S_AXI_RNG01_BASEADDR 104 | 105 | 106 | 107 | '> 108 | 110 | C_S_AXI_RNG01_HIGHADDR 111 | 112 | 113 | 114 | '> 115 | 117 | C_S_AXI_RNG02_BASEADDR 118 | 119 | 120 | 121 | '> 122 | 124 | C_S_AXI_RNG02_HIGHADDR 125 | 126 | 127 | 128 | '> 129 | 131 | C_S_AXI_RNG03_BASEADDR 132 | 133 | 134 | 135 | '> 136 | 138 | C_S_AXI_RNG03_HIGHADDR 139 | 140 | 141 | 142 | '> 143 | ]> 144 | 145 | 146 | 147 | User 148 | 149 | Common 150 | &C_USE_ADVANCED_PORTS; 151 | 152 | 153 | 154 | System 155 | 156 | Addresses 157 | &C_S_AXI_NUM_ADDR_RANGES; 158 | &C_S_AXI_RNG00_BASEADDR; 159 | &C_S_AXI_RNG00_HIGHADDR; 160 | &C_S_AXI_RNG01_BASEADDR; 161 | &C_S_AXI_RNG01_HIGHADDR; 162 | &C_S_AXI_RNG02_BASEADDR; 163 | &C_S_AXI_RNG02_HIGHADDR; 164 | &C_S_AXI_RNG03_BASEADDR; 165 | &C_S_AXI_RNG03_HIGHADDR; 166 | 167 | 168 | S_AXI 169 | &C_S_AXI_PROTOCOL; 170 | &C_S_AXI_ADDR_WIDTH; 171 | &C_S_AXI_DATA_WIDTH; 172 | &C_S_AXI_SUPPORTS_READ; 173 | &C_S_AXI_SUPPORTS_WRITE; 174 | 175 | 176 | 177 | 178 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_slave_v1_00_a/data/axi_lite_slave_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ## -- DISCLAIMER OF LIABILITY 2 | ## -- 3 | ## -- This file contains proprietary and confidential information of 4 | ## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | ## -- from Xilinx, and may be used, copied and/or disclosed only 6 | ## -- pursuant to the terms of a valid license agreement with Xilinx. 7 | ## -- 8 | ## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | ## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | ## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | ## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | ## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | ## -- does not warrant that functions included in the Materials will 14 | ## -- meet the requirements of Licensee, or that the operation of the 15 | ## -- Materials will be uninterrupted or error-free, or that defects 16 | ## -- in the Materials will be corrected. Furthermore, Xilinx does 17 | ## -- not warrant or make any representations regarding use, or the 18 | ## -- results of the use, of the Materials in terms of correctness, 19 | ## -- accuracy, reliability or otherwise. 20 | ## -- 21 | ## -- Xilinx products are not designed or intended to be fail-safe, 22 | ## -- or for use in any application requiring fail-safe performance, 23 | ## -- such as life-support or safety devices or systems, Class III 24 | ## -- medical devices, nuclear facilities, applications related to 25 | ## -- the deployment of airbags, or any other applications that could 26 | ## -- lead to death, personal injury or severe property or 27 | ## -- environmental damage (individually and collectively, "critical 28 | ## -- applications"). Customer assumes the sole risk and liability 29 | ## -- of any use of Xilinx products in critical applications, 30 | ## -- subject only to applicable laws and regulations governing 31 | ## -- limitations on product liability. 32 | ## -- 33 | ## -- Copyright 2009 Xilinx, Inc. 34 | ## -- All rights reserved. 35 | ## -- 36 | ## -- This disclaimer and copyright notice must be retained as part 37 | ## -- of this file at all times. 38 | ## 39 | ############################################################################### 40 | ## 41 | ## axi_lite_slave_v2_1_0.pao 42 | ## 43 | ## Peripheral Analyze Order File 44 | ## 45 | ## 46 | ############################################################################### 47 | 48 | 49 | lib axi_lite_slave_v1_00_a axi_lite_slave.v verilog 50 | #lib axi_lite_slave_v1_00_a axi_lite_slave.vhd vhdl 51 | 52 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_slave_v1_00_a/hdl/verilog/axi_lite_slave.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. 3 | //-- 4 | //-- This file contains confidential and proprietary information 5 | //-- of Xilinx, Inc. and is protected under U.S. and 6 | //-- international copyright and other intellectual property 7 | //-- laws. 8 | //-- 9 | //-- DISCLAIMER 10 | //-- This disclaimer is not a license and does not grant any 11 | //-- rights to the materials distributed herewith. Except as 12 | //-- otherwise provided in a valid license issued to you by 13 | //-- Xilinx, and to the maximum extent permitted by applicable 14 | //-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | //-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | //-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | //-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | //-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | //-- (2) Xilinx shall not be liable (whether in contract or tort, 20 | //-- including negligence, or under any other theory of 21 | //-- liability) for any loss or damage of any kind or nature 22 | //-- related to, arising under or in connection with these 23 | //-- materials, including for any direct, or any indirect, 24 | //-- special, incidental, or consequential loss or damage 25 | //-- (including loss of data, profits, goodwill, or any type of 26 | //-- loss or damage suffered as a result of any action brought 27 | //-- by a third party) even if such damage or loss was 28 | //-- reasonably foreseeable or Xilinx had been advised of the 29 | //-- possibility of the same. 30 | //-- 31 | //-- CRITICAL APPLICATIONS 32 | //-- Xilinx products are not designed or intended to be fail- 33 | //-- safe, or for use in any application requiring fail-safe 34 | //-- performance, such as life-support or safety devices or 35 | //-- systems, Class III medical devices, nuclear facilities, 36 | //-- applications related to the deployment of airbags, or any 37 | //-- other applications that could lead to death, personal 38 | //-- injury, or severe property or environmental damage 39 | //-- (individually and collectively, "Critical 40 | //-- Applications"). Customer assumes the sole risk and 41 | //-- liability of any use of Xilinx products in Critical 42 | //-- Applications, subject only to applicable laws and 43 | //-- regulations governing limitations on product liability. 44 | //-- 45 | //-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | //-- PART OF THIS FILE AT ALL TIMES. 47 | //----------------------------------------------------------------------------- 48 | // 49 | // AXI Lite Slave 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // axi_lite_slave 56 | // 57 | //-------------------------------------------------------------------------- 58 | 59 | `timescale 1ns/1ps 60 | 61 | module axi_lite_slave # 62 | ( 63 | parameter integer C_S_AXI_BASE_ADDR = 32'h0000_0000, 64 | parameter integer C_S_AXI_HIGH_ADDR = 32'h0000_FFFF, 65 | parameter integer C_S_AXI_ADDR_WIDTH = 32, 66 | parameter integer C_S_AXI_DATA_WIDTH = 32 67 | ) 68 | ( 69 | // System Signals 70 | input wire ACLK, 71 | input wire ARESETN, 72 | 73 | // Slave Interface Write Address Ports 74 | input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, 75 | input wire [3-1:0] S_AXI_AWPROT, 76 | input wire S_AXI_AWVALID, 77 | output wire S_AXI_AWREADY, 78 | 79 | // Slave Interface Write Data Ports 80 | input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, 81 | input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, 82 | input wire S_AXI_WVALID, 83 | output wire S_AXI_WREADY, 84 | 85 | // Slave Interface Write Response Ports 86 | output wire [2-1:0] S_AXI_BRESP, 87 | output wire S_AXI_BVALID, 88 | input wire S_AXI_BREADY, 89 | 90 | // Slave Interface Read Address Ports 91 | input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, 92 | input wire [3-1:0] S_AXI_ARPROT, 93 | input wire S_AXI_ARVALID, 94 | output wire S_AXI_ARREADY, 95 | 96 | // Slave Interface Read Data Ports 97 | output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, 98 | output wire [2-1:0] S_AXI_RRESP, 99 | output wire S_AXI_RVALID, 100 | input wire S_AXI_RREADY 101 | 102 | ); 103 | 104 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg0; 105 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg1; 106 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg2; 107 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg3; 108 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg0_addr = C_S_AXI_BASE_ADDR; 109 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg1_addr = C_S_AXI_BASE_ADDR + 4; 110 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg2_addr = C_S_AXI_BASE_ADDR + 8; 111 | reg [C_S_AXI_DATA_WIDTH-1 : 0] slv_reg3_addr = C_S_AXI_BASE_ADDR + 12; 112 | reg [31:0] read_address ; 113 | reg arready ; 114 | reg [1:0] rresp; 115 | reg rvalid; 116 | reg [31:0] rdata; 117 | 118 | //reg [31:0] write_address = S_AXI_AWADDR ; 119 | reg awready ; 120 | reg [1:0] bresp; 121 | //reg wvalid; 122 | //reg [31:0] wdata = S_AXI_WDATA;; 123 | reg wready; 124 | reg bvalid; 125 | //reg arvalid; 126 | assign S_AXI_AWREADY = awready ; 127 | assign S_AXI_ARREADY = arready ; 128 | assign S_AXI_RRESP = rresp; 129 | assign S_AXI_RVALID = rvalid; 130 | assign S_AXI_RDATA = rdata; 131 | assign S_AXI_WREADY = wready; 132 | assign S_AXI_BVALID = bvalid; 133 | //assign S_AXI_ARVALID = arvalid; 134 | 135 | assign S_AXI_BRESP = bresp; 136 | //assign S_AXI_WVALID = wvalid; 137 | 138 | //Write Address channel 139 | always @ (posedge ACLK) 140 | begin 141 | 142 | if (ARESETN == 1'b0) 143 | begin 144 | awready <= 1'b1; 145 | //write_address <= write_address; 146 | end 147 | else if(S_AXI_AWVALID==1'b1) 148 | begin 149 | if(( C_S_AXI_BASE_ADDR > S_AXI_AWADDR > C_S_AXI_HIGH_ADDR )) 150 | begin 151 | awready <= 1'b0; 152 | //write_address <= S_AXI_AWADDR; 153 | end 154 | else 155 | begin 156 | awready <= 1'b1; 157 | //write_address <= write_address; 158 | end 159 | 160 | end 161 | end 162 | //Write Data Channel 163 | always @ (posedge ACLK) 164 | begin 165 | 166 | if (ARESETN == 1'b0) 167 | begin 168 | wready <= 1'b0; 169 | bresp <= 2'b00; //OKAY 170 | bvalid <= 1'b0; 171 | end 172 | else if(S_AXI_WVALID==1'b1 && S_AXI_BREADY == 1'b1) 173 | begin 174 | if(( C_S_AXI_BASE_ADDR > S_AXI_AWADDR > C_S_AXI_HIGH_ADDR )) 175 | begin 176 | case ( S_AXI_AWADDR) 177 | slv_reg0_addr: 178 | slv_reg0 <= S_AXI_WDATA; 179 | slv_reg1_addr: 180 | slv_reg1 <= S_AXI_WDATA; 181 | slv_reg2_addr: 182 | slv_reg2 <= S_AXI_WDATA; 183 | slv_reg3_addr: 184 | slv_reg3 <= S_AXI_WDATA; 185 | default 186 | begin 187 | bresp <= 2'b11; //SLAVE ERROR(SLVERR) 188 | end 189 | endcase 190 | wready <= 1'b1; 191 | bresp <= 2'b00; //OKAY 192 | bvalid <= 1'b1; 193 | end 194 | else 195 | begin 196 | wready <= 1'b0; 197 | bresp <= 2'b00; //OKAY 198 | bvalid <= 1'b0; 199 | end 200 | end 201 | else 202 | begin 203 | wready <= 1'b0; 204 | bresp <= 2'b00; //OKAY 205 | bvalid <= 1'b0; 206 | end 207 | end 208 | //Read Address Channel 209 | always @ (posedge ACLK) 210 | begin 211 | if(S_AXI_ARVALID== 1'b1) 212 | begin 213 | read_address <= S_AXI_ARADDR; 214 | arready <= 1'b0 ; 215 | end 216 | else 217 | begin 218 | read_address <= read_address ; 219 | arready <= 1'b1 ; 220 | end 221 | 222 | end 223 | //Read Data Channel 224 | always @ (posedge ACLK) 225 | begin 226 | if(S_AXI_RREADY == 1'b1 && S_AXI_ARPROT==3'b000) 227 | begin 228 | if(( C_S_AXI_BASE_ADDR > read_address > C_S_AXI_HIGH_ADDR )) 229 | begin 230 | rvalid <= 1'b1; 231 | rresp <= 2'b00; //OKAY 232 | end 233 | else 234 | begin 235 | rvalid <= 1'b0; 236 | rresp <= 2'b00; //OKAY 237 | end 238 | 239 | case (read_address) 240 | slv_reg0_addr: 241 | rdata <= slv_reg0; 242 | slv_reg1_addr: 243 | rdata <= slv_reg1; 244 | slv_reg2_addr: 245 | rdata <= slv_reg2; 246 | slv_reg3_addr: 247 | rdata <= slv_reg3; 248 | default 249 | begin 250 | rdata <= 32'hAAAA_BBBB; 251 | end 252 | endcase 253 | end 254 | else 255 | begin 256 | rvalid <= 1'b0; 257 | rresp <= 2'b00; //OKAY 258 | end 259 | end 260 | 261 | endmodule 262 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_lite_slave_v1_00_a/hdl/vhdl/axi_lite_slave.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------- 2 | -- 3 | -- AXI Lite Slave 4 | -- 5 | ----------------------------------------------------------------------------- 6 | 7 | library ieee; 8 | use ieee.std_logic_1164.all; 9 | use ieee.numeric_std.all; 10 | use ieee.std_logic_misc.all; 11 | 12 | --library unisim; 13 | --use unisim.vcomponents.all; 14 | 15 | entity axi_lite_slave is 16 | generic ( 17 | C_S_AXI_ADDR_WIDTH : integer := 32; 18 | C_S_AXI_DATA_WIDTH : integer := 32 19 | ); 20 | port( 21 | -- System Signals 22 | ACLK : in std_logic; 23 | ARESETN : in std_logic; 24 | 25 | -- Slave Interface Write Address Ports 26 | S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 27 | S_AXI_AWPROT : in std_logic_vector(3-1 downto 0); 28 | S_AXI_AWVALID : in std_logic; 29 | S_AXI_AWREADY : out std_logic; 30 | 31 | -- Slave Interface Write Data Ports 32 | S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 33 | S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); 34 | S_AXI_WVALID : in std_logic; 35 | S_AXI_WREADY : out std_logic; 36 | 37 | -- Slave Interface Write Response Ports 38 | S_AXI_BRESP : out std_logic_vector(2-1 downto 0); 39 | S_AXI_BVALID : out std_logic; 40 | S_AXI_BREADY : in std_logic; 41 | 42 | -- Slave Interface Read Address Ports 43 | S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 44 | S_AXI_ARPROT : in std_logic_vector(3-1 downto 0); 45 | S_AXI_ARVALID : in std_logic; 46 | S_AXI_ARREADY : out std_logic; 47 | 48 | -- Slave Interface Read Data Ports 49 | S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 50 | S_AXI_RRESP : out std_logic_vector(2-1 downto 0); 51 | S_AXI_RVALID : out std_logic; 52 | S_AXI_RREADY : in std_logic 53 | ); 54 | 55 | end axi_lite_slave; 56 | 57 | architecture implementation of axi_lite_slave is 58 | begin 59 | 60 | end implementation; 61 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_master_v1_00_a/data/axi_master_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | #-- DISCLAIMER OF LIABILITY 2 | #-- 3 | #-- This file contains proprietary and confidential information of 4 | #-- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | #-- from Xilinx, and may be used, copied and/or disclosed only 6 | #-- pursuant to the terms of a valid license agreement with Xilinx. 7 | #-- 8 | #-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | #-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | #-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | #-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | #-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | #-- does not warrant that functions included in the Materials will 14 | #-- meet the requirements of Licensee, or that the operation of the 15 | #-- Materials will be uninterrupted or error-free, or that defects 16 | #-- in the Materials will be corrected. Furthermore, Xilinx does 17 | #-- not warrant or make any representations regarding use, or the 18 | #-- results of the use, of the Materials in terms of correctness, 19 | #-- accuracy, reliability or otherwise. 20 | #-- 21 | #-- Xilinx products are not designed or intended to be fail-safe, 22 | #-- or for use in any application requiring fail-safe performance, 23 | #-- such as life-support or safety devices or systems, Class III 24 | #-- medical devices, nuclear facilities, applications related to 25 | #-- the deployment of airbags, or any other applications that could 26 | #-- lead to death, personal injury or severe property or 27 | #-- environmental damage (individually and collectively, "critical 28 | #-- applications"). Customer assumes the sole risk and liability 29 | #-- of any use of Xilinx products in critical applications, 30 | #-- subject only to applicable laws and regulations governing 31 | #-- limitations on product liability. 32 | #-- 33 | #-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 34 | #-- 35 | #-- This disclaimer and copyright notice must be retained as part 36 | #-- of this file at all times. 37 | #-- 38 | ################################################################### 39 | ## 40 | ## Name : axi_master 41 | ## Desc : Microprocessor Peripheral Description 42 | ## : Automatically generated by PsfUtility 43 | ## 44 | ################################################################### 45 | 46 | BEGIN axi_master 47 | 48 | ## Peripheral Options 49 | OPTION IPTYPE = PERIPHERAL 50 | OPTION IMP_NETLIST = TRUE 51 | OPTION STYLE = HDL 52 | OPTION DESC = AXI Master 53 | OPTION LONG_DESC = An AXI Master memory test example 54 | OPTION HDL = MIXED 55 | OPTION RUN_NGCBUILD = FALSE 56 | 57 | ## Bus Interfaces 58 | BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER 59 | 60 | ## Generics for VHDL or Parameters for Verilog 61 | PARAMETER C_M_AXI_SUPPORTS_THREADS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI 62 | PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, RANGE = (1:16), BUS = M_AXI 63 | PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI 64 | PARAMETER C_M_AXI_DATA_WIDTH = 32, DT = integer, RANGE = (32, 64, 128, 256), BUS = M_AXI 65 | PARAMETER C_M_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, VALUES = (AXI4 = AXI4, AXI4Lite = AXI4Lite), BUS = M_AXI 66 | # Max number of write commands able to be issued without responses 67 | # In this example, issued writes + unread writes will throttle write address channel 68 | PARAMETER C_INTERCONNECT_M_AXI_WRITE_ISSUING = 8, DT = INTEGER, BUS = M_AXI 69 | #Read Issuing in this example HDL will go as high as write issuing parameter 70 | PARAMETER C_INTERCONNECT_M_AXI_READ_ISSUING = 8, DT = INTEGER, BUS = M_AXI, TYPE = NON_HDL 71 | PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL 72 | PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL 73 | PARAMETER C_M_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI 74 | PARAMETER C_M_AXI_AWUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI 75 | PARAMETER C_M_AXI_ARUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI 76 | PARAMETER C_M_AXI_WUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI 77 | PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI 78 | PARAMETER C_M_AXI_BUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI 79 | PARAMETER C_M_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI 80 | 81 | # Example Parameters 82 | # Base address of targeted slave 83 | PARAMETER C_M_AXI_TARGET = 0x00000000, DT = std_logic_vector(31 downto 0) 84 | # Burst length for transactions, in C_M_AXI_DATA_WIDTHs 85 | PARAMETER C_M_AXI_BURST_LEN = 16, DT = integer 86 | # Number of address bits to test before wrapping 87 | PARAMETER C_OFFSET_WIDTH = 9, DT = integer 88 | 89 | ## Ports 90 | PORT ACLK = "", BUS = M_AXI, DIR = I, SIGIS = CLK 91 | PORT ARESETN = ARESETN, BUS = M_AXI, DIR = I, SIGIS = RST 92 | PORT M_AXI_AWID = AWID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0] 93 | PORT M_AXI_AWADDR = AWADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0] 94 | PORT M_AXI_AWLEN = AWLEN, BUS = M_AXI, DIR = O, VEC = [7:0] 95 | PORT M_AXI_AWSIZE = AWSIZE, BUS = M_AXI, DIR = O, VEC = [2:0] 96 | PORT M_AXI_AWBURST = AWBURST, BUS = M_AXI, DIR = O, VEC = [1:0] 97 | PORT M_AXI_AWLOCK = AWLOCK, BUS = M_AXI, DIR = O #, VEC = [1:0] 98 | PORT M_AXI_AWCACHE = AWCACHE, BUS = M_AXI, DIR = O, VEC = [3:0] 99 | PORT M_AXI_AWPROT = AWPROT, BUS = M_AXI, DIR = O, VEC = [2:0] 100 | PORT M_AXI_AWQOS = AWQOS, BUS = M_AXI, DIR = O, VEC = [3:0] 101 | PORT M_AXI_AWUSER = AWUSER, BUS = M_AXI, DIR = O, VEC = [C_M_AXI_AWUSER_WIDTH-1:0] 102 | PORT M_AXI_AWVALID = AWVALID, BUS = M_AXI, DIR = O 103 | PORT M_AXI_AWREADY = AWREADY, BUS = M_AXI, DIR = I 104 | PORT M_AXI_WDATA = WDATA, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0] 105 | PORT M_AXI_WSTRB = WSTRB, BUS = M_AXI, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8) -1):0] 106 | PORT M_AXI_WLAST = WLAST, BUS = M_AXI, DIR = O 107 | PORT M_AXI_WUSER = WUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_WUSER_WIDTH-1):0] 108 | PORT M_AXI_WVALID = WVALID, BUS = M_AXI, DIR = O 109 | PORT M_AXI_WREADY = WREADY, BUS = M_AXI, DIR = I 110 | PORT M_AXI_BID = BID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0] 111 | PORT M_AXI_BRESP = BRESP, BUS = M_AXI, DIR = I, VEC = [1:0] 112 | PORT M_AXI_BUSER = BUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_BUSER_WIDTH-1):0] 113 | PORT M_AXI_BVALID = BVALID, BUS = M_AXI, DIR = I 114 | PORT M_AXI_BREADY = BREADY, BUS = M_AXI, DIR = O 115 | PORT M_AXI_ARID = ARID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0] 116 | PORT M_AXI_ARADDR = ARADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0] 117 | PORT M_AXI_ARLEN = ARLEN, BUS = M_AXI, DIR = O, VEC = [7:0] 118 | PORT M_AXI_ARSIZE = ARSIZE, BUS = M_AXI, DIR = O, VEC = [2:0] 119 | PORT M_AXI_ARBURST = ARBURST, BUS = M_AXI, DIR = O, VEC = [1:0] 120 | PORT M_AXI_ARLOCK = ARLOCK, BUS = M_AXI, DIR = O, VEC = [1:0] 121 | PORT M_AXI_ARCACHE = ARCACHE, BUS = M_AXI, DIR = O, VEC = [3:0] 122 | PORT M_AXI_ARPROT = ARPROT, BUS = M_AXI, DIR = O, VEC = [2:0] 123 | PORT M_AXI_ARQOS = ARQOS, BUS = M_AXI, DIR = O, VEC = [3:0] 124 | PORT M_AXI_ARUSER = ARUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ARUSER_WIDTH-1):0] 125 | PORT M_AXI_ARVALID = ARVALID, BUS = M_AXI, DIR = O 126 | PORT M_AXI_ARREADY = ARREADY, BUS = M_AXI, DIR = I 127 | PORT M_AXI_RID = RID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0] 128 | PORT M_AXI_RDATA = RDATA, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0] 129 | PORT M_AXI_RRESP = RRESP, BUS = M_AXI, DIR = I, VEC = [1:0] 130 | PORT M_AXI_RLAST = RLAST, BUS = M_AXI, DIR = I 131 | PORT M_AXI_RUSER = RUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_RUSER_WIDTH-1):0] 132 | PORT M_AXI_RVALID = RVALID, BUS = M_AXI, DIR = I 133 | PORT M_AXI_RREADY = RREADY, BUS = M_AXI, DIR = O 134 | 135 | #Example IO port 136 | PORT ERROR = "", DIR = O 137 | 138 | END 139 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_master_v1_00_a/data/axi_master_v2_1_0.mui: -------------------------------------------------------------------------------- 1 | 2 | 3 | 45 | 46 | 48 | 50 | C_M_AXI_SUPPORTS_THREADS 51 | 52 | 53 | 54 | '> 55 | 57 | C_M_AXI_THREAD_ID_WIDTH 58 | 59 | 60 | 61 | '> 62 | 64 | C_M_AXI_ADDR_WIDTH 65 | 66 | 67 | 68 | '> 69 | 71 | C_M_AXI_DATA_WIDTH 72 | 73 | 74 | 75 | '> 76 | 78 | C_M_AXI_PROTOCOL 79 | 80 | 81 | 82 | '> 83 | 85 | C_USE_ADVANCED_PORTS 86 | 87 | 88 | 89 | '> 90 | 92 | C_M_AXI_SUPPORTS_READ 93 | 94 | 95 | 96 | '> 97 | 99 | C_M_AXI_SUPPORTS_WRITE 100 | 101 | 102 | 103 | '> 104 | 106 | C_M_AXI_SUPPORTS_USER_SIGNALS 107 | 108 | 109 | 110 | '> 111 | 113 | C_M_AXI_AWUSER_WIDTH 114 | 115 | 116 | 117 | '> 118 | 120 | C_M_AXI_ARUSER_WIDTH 121 | 122 | 123 | 124 | '> 125 | 127 | C_M_AXI_WUSER_WIDTH 128 | 129 | 130 | 131 | '> 132 | 134 | C_M_AXI_RUSER_WIDTH 135 | 136 | 137 | 138 | '> 139 | 141 | C_M_AXI_BUSER_WIDTH 142 | 143 | 144 | 145 | '> 146 | 148 | C_M_AXI_SUPPORTS_NARROW_BURST 149 | 150 | 151 | 152 | '> 153 | 155 | C_M_AXI_TARGET 156 | 157 | 158 | 159 | '> 160 | 162 | C_M_AXI_BURST_LEN 163 | 164 | 165 | 166 | '> 167 | 169 | C_MAX_UNREAD_WRITES 170 | 171 | 172 | 173 | '> 174 | 176 | C_OFFSET_WIDTH 177 | 178 | 179 | 180 | '> 181 | 182 | ]> 183 | 184 | 185 | 186 | User 187 | 188 | Common 189 | &C_M_AXI_TARGET; 190 | &C_M_AXI_BURST_LEN; 191 | &C_MAX_UNREAD_WRITES; 192 | &C_OFFSET_WIDTH; 193 | &C_M_AXI_PROTOCOL; 194 | 195 | 196 | 197 | System 198 | 199 | AXI 200 | &C_M_AXI_ADDR_WIDTH; 201 | &C_M_AXI_DATA_WIDTH; 202 | &C_M_AXI_SUPPORTS_READ; 203 | &C_M_AXI_SUPPORTS_WRITE; 204 | &C_M_AXI_SUPPORTS_THREADS; 205 | &C_M_AXI_THREAD_ID_WIDTH; 206 | &C_M_AXI_SUPPORTS_NARROW_BURST; 207 | &C_M_AXI_SUPPORTS_USER_SIGNALS; 208 | &C_M_AXI_AWUSER_WIDTH; 209 | &C_M_AXI_ARUSER_WIDTH; 210 | &C_M_AXI_WUSER_WIDTH; 211 | &C_M_AXI_RUSER_WIDTH; 212 | &C_M_AXI_BUSER_WIDTH; 213 | 214 | 215 | 216 | 217 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_master_v1_00_a/data/axi_master_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ## -- DISCLAIMER OF LIABILITY 2 | ## -- 3 | ## -- This file contains proprietary and confidential information of 4 | ## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | ## -- from Xilinx, and may be used, copied and/or disclosed only 6 | ## -- pursuant to the terms of a valid license agreement with Xilinx. 7 | ## -- 8 | ## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | ## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | ## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | ## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | ## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | ## -- does not warrant that functions included in the Materials will 14 | ## -- meet the requirements of Licensee, or that the operation of the 15 | ## -- Materials will be uninterrupted or error-free, or that defects 16 | ## -- in the Materials will be corrected. Furthermore, Xilinx does 17 | ## -- not warrant or make any representations regarding use, or the 18 | ## -- results of the use, of the Materials in terms of correctness, 19 | ## -- accuracy, reliability or otherwise. 20 | ## -- 21 | ## -- Xilinx products are not designed or intended to be fail-safe, 22 | ## -- or for use in any application requiring fail-safe performance, 23 | ## -- such as life-support or safety devices or systems, Class III 24 | ## -- medical devices, nuclear facilities, applications related to 25 | ## -- the deployment of airbags, or any other applications that could 26 | ## -- lead to death, personal injury or severe property or 27 | ## -- environmental damage (individually and collectively, "critical 28 | ## -- applications"). Customer assumes the sole risk and liability 29 | ## -- of any use of Xilinx products in critical applications, 30 | ## -- subject only to applicable laws and regulations governing 31 | ## -- limitations on product liability. 32 | ## -- 33 | ## -- Copyright 2009 Xilinx, Inc. 34 | ## -- All rights reserved. 35 | ## -- 36 | ## -- This disclaimer and copyright notice must be retained as part 37 | ## -- of this file at all times. 38 | ## 39 | ############################################################################### 40 | ## 41 | ## axi_master_v1_00_a.pao 42 | ## 43 | ## Peripheral Analyze Order File 44 | ## 45 | ## 46 | ############################################################################### 47 | 48 | 49 | lib axi_master_v1_00_a axi_master.v verilog 50 | 51 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_master_v1_00_a/hdl/verilog/axi_master.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // AXI Master 4 | // 5 | // Verilog-standard: Verilog 2001 6 | //-------------------------------------------------------------------------- 7 | // 8 | // Structure: 9 | // axi_master 10 | // 11 | // Last Update: 12 | // 8/24/2011 13 | // 14 | //-------------------------------------------------------------------------- 15 | /* 16 | AXI4 Master Example 17 | 18 | The purpose of this design is to provide a high-throughput AXI4 example 19 | and AXI4 throughput demonstration. 20 | 21 | The example user application performs a simple memory 22 | test through continuous burst writes to memory, followed by burst 23 | reads. The simple data pattern is checked and any data comparison or 24 | interface errors are latched with the example ERROR output. 25 | 26 | To modify this example for other applications, edit/remove the logic 27 | associated with the 'Example' section comments. For clarity, most 28 | transfer qualifiers are left as constants, but can be easily added 29 | to their associated channels. 30 | 31 | The latest version of this file can be found in Xilinx Answer 37425 32 | http://www.xilinx.com/support/answers/37425.htm 33 | */ 34 | 35 | `timescale 1ns/1ps 36 | 37 | //Simple Log2 calculation function 38 | `define C_LOG_2(n) (\ 39 | (n) <= (1<<0) ? 0 : (n) <= (1<<1) ? 1 :\ 40 | (n) <= (1<<2) ? 2 : (n) <= (1<<3) ? 3 :\ 41 | (n) <= (1<<4) ? 4 : (n) <= (1<<5) ? 5 :\ 42 | (n) <= (1<<6) ? 6 : (n) <= (1<<7) ? 7 :\ 43 | (n) <= (1<<8) ? 8 : (n) <= (1<<9) ? 9 :\ 44 | (n) <= (1<<10) ? 10 : (n) <= (1<<11) ? 11 :\ 45 | (n) <= (1<<12) ? 12 : (n) <= (1<<13) ? 13 :\ 46 | (n) <= (1<<14) ? 14 : (n) <= (1<<15) ? 15 :\ 47 | (n) <= (1<<16) ? 16 : (n) <= (1<<17) ? 17 :\ 48 | (n) <= (1<<18) ? 18 : (n) <= (1<<19) ? 19 :\ 49 | (n) <= (1<<20) ? 20 : (n) <= (1<<21) ? 21 :\ 50 | (n) <= (1<<22) ? 22 : (n) <= (1<<23) ? 23 :\ 51 | (n) <= (1<<24) ? 24 : (n) <= (1<<25) ? 25 :\ 52 | (n) <= (1<<26) ? 26 : (n) <= (1<<27) ? 27 :\ 53 | (n) <= (1<<28) ? 28 : (n) <= (1<<29) ? 29 :\ 54 | (n) <= (1<<30) ? 30 : (n) <= (1<<31) ? 31 : 32) 55 | 56 | module axi_master # 57 | ( 58 | parameter integer C_M_AXI_THREAD_ID_WIDTH = 1, 59 | parameter integer C_M_AXI_ADDR_WIDTH = 32, 60 | parameter integer C_M_AXI_DATA_WIDTH = 32, 61 | parameter integer C_M_AXI_AWUSER_WIDTH = 1, 62 | parameter integer C_M_AXI_ARUSER_WIDTH = 1, 63 | parameter integer C_M_AXI_WUSER_WIDTH = 1, 64 | parameter integer C_M_AXI_RUSER_WIDTH = 1, 65 | parameter integer C_M_AXI_BUSER_WIDTH = 1, 66 | 67 | /* Disabling these parameters will remove any throttling. 68 | The resulting ERROR flag will not be useful */ 69 | parameter integer C_M_AXI_SUPPORTS_WRITE = 1, 70 | parameter integer C_M_AXI_SUPPORTS_READ = 1, 71 | 72 | /* Max count of written but not yet read bursts. 73 | If the interconnect/slave is able to accept enough 74 | addresses and the read channels are stalled, the 75 | master will issue this many commands ahead of 76 | write responses */ 77 | parameter integer C_INTERCONNECT_M_AXI_WRITE_ISSUING = 8, 78 | 79 | //////////////////////////// 80 | // Example design parameters 81 | //////////////////////////// 82 | 83 | // Base address of targeted slave 84 | parameter C_M_AXI_TARGET = 'h00000000, 85 | 86 | // Number of address bits to test before wrapping 87 | parameter integer C_OFFSET_WIDTH = 9, 88 | 89 | /* Burst length for transactions, in C_M_AXI_DATA_WIDTHs. 90 | Non-2^n lengths will eventually cause bursts across 4K 91 | address boundaries.*/ 92 | parameter integer C_M_AXI_BURST_LEN = 16 93 | ) 94 | ( 95 | // System Signals 96 | input wire ACLK, 97 | input wire ARESETN, 98 | 99 | // Master Interface Write Address 100 | output wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_AWID, 101 | output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, 102 | output wire [8-1:0] M_AXI_AWLEN, 103 | output wire [3-1:0] M_AXI_AWSIZE, 104 | output wire [2-1:0] M_AXI_AWBURST, 105 | output wire M_AXI_AWLOCK, 106 | output wire [4-1:0] M_AXI_AWCACHE, 107 | output wire [3-1:0] M_AXI_AWPROT, 108 | // AXI3 output wire [4-1:0] M_AXI_AWREGION, 109 | output wire [4-1:0] M_AXI_AWQOS, 110 | output wire [C_M_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, 111 | output wire M_AXI_AWVALID, 112 | input wire M_AXI_AWREADY, 113 | 114 | // Master Interface Write Data 115 | // AXI3 output wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_WID, 116 | output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, 117 | output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, 118 | output wire M_AXI_WLAST, 119 | output wire [C_M_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, 120 | output wire M_AXI_WVALID, 121 | input wire M_AXI_WREADY, 122 | 123 | // Master Interface Write Response 124 | input wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_BID, 125 | input wire [2-1:0] M_AXI_BRESP, 126 | input wire [C_M_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, 127 | input wire M_AXI_BVALID, 128 | output wire M_AXI_BREADY, 129 | 130 | // Master Interface Read Address 131 | output wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_ARID, 132 | output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, 133 | output wire [8-1:0] M_AXI_ARLEN, 134 | output wire [3-1:0] M_AXI_ARSIZE, 135 | output wire [2-1:0] M_AXI_ARBURST, 136 | output wire [2-1:0] M_AXI_ARLOCK, 137 | output wire [4-1:0] M_AXI_ARCACHE, 138 | output wire [3-1:0] M_AXI_ARPROT, 139 | // AXI3 output wire [4-1:0] M_AXI_ARREGION, 140 | output wire [4-1:0] M_AXI_ARQOS, 141 | output wire [C_M_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, 142 | output wire M_AXI_ARVALID, 143 | input wire M_AXI_ARREADY, 144 | 145 | // Master Interface Read Data 146 | input wire [C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI_RID, 147 | input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, 148 | input wire [2-1:0] M_AXI_RRESP, 149 | input wire M_AXI_RLAST, 150 | input wire [C_M_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, 151 | input wire M_AXI_RVALID, 152 | output wire M_AXI_RREADY, 153 | 154 | // Example Design 155 | input wire start_i, 156 | output wire ERROR, 157 | //Output test ports --Write 158 | output wire [C_M_AXI_ADDR_WIDTH-1:0] test_AWADDR, 159 | output wire test_AWVALID, 160 | output wire test_AWREADY, 161 | output wire [C_M_AXI_DATA_WIDTH-1:0] test_WDATA, 162 | output wire test_WLAST, 163 | output wire test_WVALID, 164 | output wire test_WREADY, 165 | output wire [2-1:0] test_BRESP, 166 | output wire test_BVALID, 167 | output wire test_BREADY, 168 | //Read 169 | output wire [C_M_AXI_ADDR_WIDTH-1:0] test_ARADDR, 170 | output wire test_ARVALID, 171 | output wire test_ARREADY, 172 | output wire [C_M_AXI_DATA_WIDTH-1:0] test_RDATA, 173 | output wire test_RLAST, 174 | output wire test_RVALID, 175 | output wire test_RREADY 176 | ); 177 | 178 | 179 | // A fancy terminal counter, using extra bits to reduce decode logic 180 | localparam integer C_WLEN_COUNT_WIDTH = `C_LOG_2(C_M_AXI_BURST_LEN-2)+2; 181 | reg [C_WLEN_COUNT_WIDTH-1:0] wlen_count; 182 | 183 | // Local address counters 184 | reg [C_OFFSET_WIDTH-1:0] araddr_offset = 'b0; 185 | reg [C_OFFSET_WIDTH-1:0] awaddr_offset = 'b0; 186 | 187 | // Example throttling counters 188 | reg [`C_LOG_2(C_INTERCONNECT_M_AXI_WRITE_ISSUING)-1:0] unread_writes; 189 | reg [`C_LOG_2(C_INTERCONNECT_M_AXI_WRITE_ISSUING)-1:0] aw_issue_count; 190 | reg [`C_LOG_2(C_INTERCONNECT_M_AXI_WRITE_ISSUING)-1:0] w_issue_count; 191 | 192 | // Throttling flags 193 | reg aw_throttle; 194 | reg w_throttle; 195 | reg ar_throttle; 196 | 197 | // Example user application signals 198 | reg read_mismatch; 199 | reg error_reg; 200 | reg [C_M_AXI_DATA_WIDTH-1:0] data_gen; 201 | 202 | // Interface response error flags 203 | wire write_resp_error; 204 | wire read_resp_error; 205 | 206 | // AXI4 temp signals 207 | reg awvalid; 208 | reg [C_M_AXI_DATA_WIDTH-1:0] wdata; 209 | wire wlast; 210 | reg wvalid; 211 | reg bready; 212 | reg arvalid; 213 | reg rready; 214 | 215 | wire wnext; 216 | 217 | ///////////////// 218 | //I/O Connections 219 | ///////////////// 220 | assign test_AWADDR = M_AXI_AWADDR ; 221 | assign test_AWVALID = M_AXI_AWVALID ; 222 | assign test_AWREADY = M_AXI_AWREADY ; 223 | assign test_WDATA = M_AXI_WDATA ; 224 | assign test_WLAST = M_AXI_WLAST ; 225 | assign test_WVALID = M_AXI_WVALID ; 226 | assign test_WREADY = M_AXI_WREADY ; 227 | assign test_BRESP = M_AXI_BRESP ; 228 | assign test_BVALID = M_AXI_BVALID ; 229 | assign test_BREADY = M_AXI_BREADY ; 230 | //Read 231 | assign test_ARADDR = M_AXI_ARADDR ; 232 | assign test_ARVALID = M_AXI_ARVALID ; 233 | assign test_ARREADY = M_AXI_ARREADY ; 234 | assign test_RDATA = M_AXI_RDATA ; 235 | assign test_RLAST = M_AXI_RLAST ; 236 | assign test_RVALID = M_AXI_RVALID ; 237 | assign test_RREADY = M_AXI_RREADY ; 238 | 239 | 240 | //////////////////// 241 | //Write Address (AW) 242 | //////////////////// 243 | 244 | // Single threaded 245 | assign M_AXI_AWID = 'b0; 246 | 247 | // The AXI address is a concatenation of the target base address + active offset range 248 | assign M_AXI_AWADDR = {C_M_AXI_TARGET[C_M_AXI_ADDR_WIDTH-1:C_OFFSET_WIDTH],awaddr_offset}; 249 | 250 | //Burst LENgth is number of transaction beats, minus 1 251 | assign M_AXI_AWLEN = C_M_AXI_BURST_LEN - 1; 252 | 253 | // Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used 254 | assign M_AXI_AWSIZE = `C_LOG_2(C_M_AXI_DATA_WIDTH/8); 255 | 256 | // INCR burst type is usually used, except for keyhole bursts 257 | assign M_AXI_AWBURST = 2'b01; 258 | assign M_AXI_AWLOCK = 1'b0; 259 | 260 | // Not Allocated, Modifiable, not Bufferable 261 | // Not Bufferable since this example is meant to test memory, not intermediate cache 262 | assign M_AXI_AWCACHE = 4'b0010; 263 | assign M_AXI_AWPROT = 3'h0; 264 | assign M_AXI_AWQOS = 4'h0; 265 | assign M_AXI_AWUSER = 'b0; 266 | assign M_AXI_AWVALID = awvalid; 267 | 268 | /////////////// 269 | //Write Data(W) 270 | /////////////// 271 | assign M_AXI_WDATA = wdata; 272 | 273 | //All bursts are complete and aligned in this example 274 | assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}}; 275 | assign M_AXI_WLAST = wlast; 276 | assign M_AXI_WUSER = 'b0; 277 | assign M_AXI_WVALID = wvalid; 278 | 279 | //////////////////// 280 | //Write Response (B) 281 | //////////////////// 282 | assign M_AXI_BREADY = bready; 283 | 284 | /////////////////// 285 | //Read Address (AR) 286 | /////////////////// 287 | assign M_AXI_ARID = 'b0; 288 | assign M_AXI_ARADDR = {C_M_AXI_TARGET[C_M_AXI_ADDR_WIDTH-1:C_OFFSET_WIDTH],araddr_offset}; 289 | 290 | //Burst LENgth is number of transaction beats, minus 1 291 | assign M_AXI_ARLEN = C_M_AXI_BURST_LEN - 1; 292 | 293 | // Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used 294 | assign M_AXI_ARSIZE = `C_LOG_2(C_M_AXI_DATA_WIDTH/8); 295 | 296 | // INCR burst type is usually used, except for keyhole bursts 297 | assign M_AXI_ARBURST = 2'b01; 298 | assign M_AXI_ARLOCK = 1'b0; 299 | // Not Allocated, Modifiable, not Bufferable 300 | // Not Bufferable since this example is meant to test memory, not intermediate cache 301 | assign M_AXI_ARCACHE = 4'b0010; 302 | assign M_AXI_ARPROT = 3'h0; 303 | assign M_AXI_ARQOS = 4'h0; 304 | assign M_AXI_ARUSER = 'b0; 305 | assign M_AXI_ARVALID = arvalid; 306 | 307 | //////////////////////////// 308 | //Read and Read Response (R) 309 | //////////////////////////// 310 | assign M_AXI_RREADY = rready; 311 | 312 | //////////////////// 313 | //Example design I/O 314 | //////////////////// 315 | assign ERROR = error_reg; 316 | 317 | // Userlogic based start 318 | assign reset_start = ARESETN && start_i ; 319 | //////////////////////////////////////////////// 320 | //Reset logic, workaround for AXI_BRAM CR#582705 321 | //////////////////////////////////////////////// 322 | reg aresetn_r = 1'b0; 323 | reg aresetn_rr = 1'b0; 324 | reg aresetn_rrr = 1'b0; 325 | 326 | always @(posedge ACLK) 327 | begin 328 | aresetn_r <= reset_start; 329 | aresetn_rr <= aresetn_r; 330 | aresetn_rrr <= aresetn_rr; 331 | end 332 | 333 | /////////////////////// 334 | //Write Address Channel 335 | /////////////////////// 336 | /* 337 | The purpose of the write address channel is to request the address and 338 | command information for the entire transaction. It is a single beat 339 | of data for each burst. 340 | 341 | The AXI4 Write address channel in this example will continue to initiate 342 | write commands as fast as it is allowed by the slave/interconnect. 343 | 344 | The address will be incremented on each accepted address transaction, 345 | until wrapping on the C_OFFSET_WIDTH boundary with awaddr_offset. 346 | */ 347 | always @(posedge ACLK) 348 | begin 349 | 350 | /* Delay write address channel by a few cycles for CR#582705 351 | Only necessary when point2point to AXI_BRAM slave */ 352 | if (aresetn_rrr == 0 ) 353 | //if (ARESETN == 0) 354 | awvalid <= 1'b0; 355 | 356 | // If previously not valid and no throttling, start next transaction 357 | else if (C_M_AXI_SUPPORTS_WRITE && awvalid==0 && aw_throttle == 0) 358 | awvalid <= 1'b1; 359 | 360 | /* Once asserted, VALIDs cannot be deasserted, so AWVALID 361 | must wait until transaction is accepted before throttling */ 362 | else if (M_AXI_AWREADY && awvalid && aw_throttle) 363 | awvalid <= 1'b0; 364 | else 365 | awvalid <= awvalid; 366 | end 367 | 368 | 369 | // Next address after AWREADY indicates previous address acceptance 370 | always @(posedge ACLK) 371 | begin 372 | if (reset_start == 0) 373 | awaddr_offset <= 'b0; 374 | else if (M_AXI_AWREADY && awvalid) 375 | awaddr_offset <= awaddr_offset + C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8; 376 | else 377 | awaddr_offset <= awaddr_offset; 378 | end 379 | 380 | //////////////////// 381 | //Write Data Channel 382 | //////////////////// 383 | /* 384 | The write data will continually try to push write data across the interface. 385 | 386 | The amount of data accepted will depend on the AXI slave and the AXI 387 | Interconnect settings, such as if there are FIFOs enabled in interconnect. 388 | 389 | Note that there is no explicit timing relationship to the write address channel. 390 | The write channel has its own throttling flag, separate from the AW channel. 391 | 392 | Synchronization between the channels must be determined by the user. 393 | 394 | The simpliest but lowest performance would be to only issue one address write 395 | and write data burst at a time. 396 | 397 | In this example they are kept in sync by using the same address increment 398 | and burst sizes. Then the AW and W channels have their transactions measured 399 | with threshold counters as part of the user logic, to make sure neither 400 | channel gets too far ahead of each other. 401 | */ 402 | 403 | // Forward movement occurs when the channel is valid and ready 404 | assign wnext = M_AXI_WREADY & wvalid; 405 | 406 | // WVALID logic, similar to the AWVALID always block above 407 | always @(posedge ACLK) 408 | begin 409 | if (aresetn_rrr == 0 ) 410 | //if (ARESETN == 0) 411 | wvalid <= 1'b0; 412 | 413 | // If previously not valid and not throttling, start next transaction 414 | else if (C_M_AXI_SUPPORTS_WRITE && wvalid==0 && w_throttle == 0) 415 | wvalid <= 1'b1; 416 | 417 | /* If WREADY and too many writes, throttle WVALID 418 | Once asserted, VALIDs cannot be deasserted, so WVALID 419 | must wait until burst is complete with WLAST */ 420 | else if (wnext && wlast && w_throttle) 421 | wvalid <= 1'b0; 422 | else 423 | wvalid <= wvalid; 424 | end 425 | 426 | //WLAST generation on the MSB of a counter underflow 427 | assign wlast = wlen_count[C_WLEN_COUNT_WIDTH-1]; 428 | 429 | /* Burst length counter. Uses extra counter register bit to indicate terminal 430 | count to reduce decode logic */ 431 | always @(posedge ACLK) 432 | begin 433 | if (reset_start == 0 || (wnext && wlen_count[C_WLEN_COUNT_WIDTH-1])) 434 | wlen_count <= C_M_AXI_BURST_LEN - 2; 435 | else if (wnext) 436 | wlen_count <= wlen_count - 1; 437 | else 438 | wlen_count <= wlen_count; 439 | end 440 | 441 | /* Write Data Generator 442 | Data pattern is only a simple incrementing count from 0 for each burst */ 443 | always @(posedge ACLK) 444 | begin 445 | if (reset_start == 0) 446 | wdata <= 'b0; 447 | else if (wnext && wlast) 448 | wdata <= 'b0; 449 | else if (wnext) 450 | wdata <= wdata + 1; 451 | else 452 | wdata <= wdata; 453 | end 454 | 455 | //////////////////////////// 456 | //Write Response (B) Channel 457 | //////////////////////////// 458 | /* 459 | The write response channel provides feedback that the write has committed 460 | to memory. BREADY will occur when all of the data and the write address 461 | has arrived and been accepted by the slave. 462 | 463 | The write issuance (number of outstanding write addresses) is started by 464 | the Address Write transfer, and is completed by a BREADY/BRESP. 465 | 466 | While negating BREADY will eventually throttle the AWREADY signal, 467 | it is best not to throttle the whole data channel this way. 468 | 469 | The BRESP bit [1] is used indicate any errors from the interconnect or 470 | slave for the entire write burst. This example will capture the error 471 | into the ERROR output. 472 | */ 473 | 474 | //Always accept write responses 475 | always @(posedge ACLK) 476 | begin 477 | if (reset_start == 0) 478 | bready <= 1'b0; 479 | else 480 | bready <= C_M_AXI_SUPPORTS_WRITE; 481 | end 482 | 483 | //Flag any write response errors 484 | assign write_resp_error = bready & M_AXI_BVALID & M_AXI_BRESP[1]; 485 | 486 | ////////////////////// 487 | //Read Address Channel 488 | ////////////////////// 489 | /* 490 | The Read Address Channel (AW) provides a similar function to the 491 | Write Address channel- to provide the tranfer qualifiers for the 492 | burst. 493 | 494 | In this example, the read address increments in the same 495 | manner as the write address channel. 496 | */ 497 | always @(posedge ACLK) 498 | begin 499 | if (reset_start == 0) 500 | begin 501 | arvalid <= 1'b0; 502 | araddr_offset <= 'b0; 503 | end 504 | else if (arvalid && M_AXI_ARREADY) 505 | begin 506 | arvalid <= 1'b0; 507 | araddr_offset <= araddr_offset + C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8; 508 | end 509 | else if (C_M_AXI_SUPPORTS_READ && ar_throttle == 0) 510 | begin 511 | arvalid <= 1'b1; 512 | araddr_offset <= araddr_offset; 513 | end 514 | else 515 | begin 516 | arvalid <= arvalid; 517 | araddr_offset <= araddr_offset; 518 | end 519 | end 520 | 521 | ////////////////////////////////// 522 | //Read Data (and Response) Channel 523 | ////////////////////////////////// 524 | /* 525 | The Read Data channel returns the results of the read request 526 | 527 | In this example the data checker is always able to accept 528 | more data, so no need to throttle the RREADY signal 529 | */ 530 | always @(posedge ACLK) 531 | begin 532 | if (reset_start == 0) 533 | rready <= 1'b0; 534 | else 535 | rready <= C_M_AXI_SUPPORTS_READ; 536 | end 537 | 538 | //Check received read data against data generator 539 | always @(posedge ACLK) 540 | begin 541 | if (reset_start == 0) 542 | read_mismatch <= 1'b0; 543 | 544 | //Only check data when RVALID is active 545 | else if ((M_AXI_RVALID && rready) && (M_AXI_RDATA != data_gen)) 546 | read_mismatch <= 1'b1; 547 | else 548 | read_mismatch <= 1'b0; 549 | end 550 | assign read_resp_error = rready & M_AXI_RVALID & M_AXI_RRESP[1]; 551 | 552 | 553 | ////////////////////////////////////////// 554 | //Example design read check data generator 555 | ////////////////////////////////////////// 556 | 557 | //Generate expected read data to check against actual read data 558 | always @(posedge ACLK) 559 | begin 560 | if (reset_start == 0) 561 | data_gen <= 'b0; 562 | 563 | //On a handshaked cycle, reset if last transfer, otherwise increment 564 | else if (M_AXI_RVALID && rready) 565 | begin 566 | if (M_AXI_RLAST) 567 | data_gen <= 'b0; 568 | else 569 | data_gen <= data_gen + 1; 570 | end 571 | else 572 | data_gen <= data_gen; 573 | end 574 | 575 | /////////////////////////////// 576 | //Example design error register 577 | /////////////////////////////// 578 | 579 | // Register and hold any data mismatches, or read/write interface errors 580 | always @(posedge ACLK) 581 | begin 582 | if (reset_start == 0) 583 | error_reg <= 1'b0; 584 | else if (read_mismatch || write_resp_error || read_resp_error) 585 | error_reg <= 1'b1; 586 | else 587 | error_reg <= error_reg; 588 | end 589 | 590 | /////////////////////////// 591 | //Example design throttling 592 | /////////////////////////// 593 | /* 594 | For maximum port throughput, this user example code will try to allow 595 | each channel to run as independently and as quickly as possible. 596 | 597 | However, there are times when the flow of data needs to be throtted by 598 | the user application. This example application requires that data is 599 | not read before it is written and that the write channels do not 600 | advance beyond an arbitrary threshold (say to prevent an 601 | overrun of the current read address by the write address). 602 | 603 | From AXI4 Specification, 13.13.1: "If a master requires ordering between 604 | read and write transactions, it must ensure that a response is received 605 | for the previous transaction before issuing the next transaction." 606 | 607 | This example accomplishes this user application throttling through: 608 | -Reads wait for writes to fully complete 609 | -Address writes wait when not read + issued transaction counts pass 610 | a parameterized threshold 611 | -Writes wait when a not read + active data burst count pass 612 | a parameterized threshold 613 | */ 614 | 615 | // Up/down counter of accepted, but not completed, write address commands 616 | always @(posedge ACLK) 617 | begin 618 | if (reset_start == 0) 619 | aw_issue_count <= 'b0; 620 | else if (bready && M_AXI_BVALID && M_AXI_AWVALID && M_AXI_AWREADY) 621 | aw_issue_count <= aw_issue_count; 622 | else if (bready && M_AXI_BVALID) 623 | aw_issue_count <= aw_issue_count - 1; 624 | else if (M_AXI_AWVALID && M_AXI_AWREADY) 625 | aw_issue_count <= aw_issue_count + 1; 626 | else 627 | aw_issue_count <= aw_issue_count; 628 | end 629 | 630 | // Up/down counter of bursts of data written, but not completed with BREADY 631 | always @(posedge ACLK) 632 | begin 633 | if (reset_start == 0) 634 | w_issue_count <= 'b0; 635 | else if (bready && M_AXI_BVALID && (M_AXI_WLAST & M_AXI_WVALID && M_AXI_WREADY)) 636 | w_issue_count <= w_issue_count; 637 | else if (bready && M_AXI_BVALID) 638 | w_issue_count <= w_issue_count - 1; 639 | else if (M_AXI_WLAST & M_AXI_WVALID && M_AXI_WREADY) 640 | w_issue_count <= w_issue_count + 1; 641 | else 642 | w_issue_count <= w_issue_count; 643 | end 644 | 645 | // Up/down counter of writes that have been completed, but not yet read 646 | always @(posedge ACLK) 647 | begin 648 | if (reset_start == 0) 649 | unread_writes <= 'b0; 650 | else if (bready && M_AXI_BVALID && M_AXI_ARVALID && M_AXI_ARREADY) 651 | unread_writes <= unread_writes; 652 | else if (bready && M_AXI_BVALID) 653 | unread_writes <= unread_writes + 1; 654 | else if (M_AXI_ARVALID && M_AXI_ARREADY) 655 | unread_writes <= unread_writes - 1; 656 | else 657 | unread_writes <= unread_writes; 658 | end 659 | 660 | /*If there are fully completed writes, allow reads to start 661 | If the write logic is removed, never throttle reads */ 662 | always @(unread_writes) 663 | begin 664 | if (unread_writes > 0 || C_M_AXI_SUPPORTS_WRITE == 0) 665 | ar_throttle = 1'b0; 666 | else 667 | ar_throttle = 1'b1; 668 | end 669 | 670 | /* If reads supported and the number of completed but not read bursts + 671 | issued but not yet completed write addresses is equal or greater than a threshold, 672 | throttle the address write channel. */ 673 | always @(aw_issue_count,unread_writes) 674 | begin 675 | if (C_M_AXI_SUPPORTS_READ && (aw_issue_count + unread_writes >= C_INTERCONNECT_M_AXI_WRITE_ISSUING)) 676 | aw_throttle = 1'b1; 677 | else 678 | aw_throttle = 1'b0; 679 | end 680 | 681 | /* If the number of completed but not read bursts + issued but not 682 | yet completed write addresses is equal or greater than a threshold, 683 | throttle the address write channel. */ 684 | always @(w_issue_count,unread_writes) 685 | begin 686 | if (C_M_AXI_SUPPORTS_READ && (w_issue_count + unread_writes >= C_INTERCONNECT_M_AXI_WRITE_ISSUING)) 687 | w_throttle = 1'b1; 688 | else 689 | w_throttle = 1'b0; 690 | end 691 | 692 | endmodule -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_master_v1_00_a/hdl/vhdl/axi_master.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- AXI Master 4 | -- 5 | -- VHDL-Standard: VHDL'93 6 | ---------------------------------------------------------------------------- 7 | -- 8 | -- Structure: 9 | -- axi_master 10 | -- 11 | ---------------------------------------------------------------------------- 12 | 13 | library ieee; 14 | use ieee.std_logic_1164.all; 15 | use ieee.numeric_std.all; 16 | use ieee.std_logic_misc.all; 17 | 18 | --library unisim; 19 | --use unisim.vcomponents.all; 20 | 21 | entity axi_master is 22 | generic( 23 | C_M_AXI_THREAD_ID_WIDTH : integer := 1; 24 | C_M_AXI_ADDR_WIDTH : integer := 32; 25 | C_M_AXI_DATA_WIDTH : integer := 32; 26 | C_M_AXI_AWUSER_WIDTH : integer := 1; 27 | C_M_AXI_ARUSER_WIDTH : integer := 1; 28 | C_M_AXI_WUSER_WIDTH : integer := 1; 29 | C_M_AXI_RUSER_WIDTH : integer := 1; 30 | C_M_AXI_BUSER_WIDTH : integer := 1 31 | ); 32 | port( 33 | -- System Signals 34 | ACLK : in std_logic; 35 | ARESETN : in std_logic; 36 | 37 | -- Master Interface Write Address 38 | M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0); 39 | M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); 40 | M_AXI_AWLEN : out std_logic_vector(8-1 downto 0); 41 | M_AXI_AWSIZE : out std_logic_vector(3-1 downto 0); 42 | M_AXI_AWBURST : out std_logic_vector(2-1 downto 0); 43 | M_AXI_AWLOCK : out std_logic; 44 | M_AXI_AWCACHE : out std_logic_vector(4-1 downto 0); 45 | M_AXI_AWPROT : out std_logic_vector(3-1 downto 0); 46 | -- AXI3 M_AXI_AWREGION:out std_logic_vector(4-1 downto 0); 47 | M_AXI_AWQOS : out std_logic_vector(4-1 downto 0); 48 | M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0); 49 | M_AXI_AWVALID : out std_logic; 50 | M_AXI_AWREADY : in std_logic; 51 | 52 | -- Master Interface Write Data 53 | -- AXI3 M_AXI_WID(C_M_AXI_THREAD_ID_WIDTH-1 downto 0); 54 | M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); 55 | M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0); 56 | M_AXI_WLAST : out std_logic; 57 | M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0); 58 | M_AXI_WVALID : out std_logic; 59 | M_AXI_WREADY : in std_logic; 60 | 61 | -- Master Interface Write Response 62 | M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0); 63 | M_AXI_BRESP : in std_logic_vector(2-1 downto 0); 64 | M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0); 65 | M_AXI_BVALID : in std_logic; 66 | M_AXI_BREADY : out std_logic; 67 | 68 | -- Master Interface Read Address 69 | M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0); 70 | M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); 71 | M_AXI_ARLEN : out std_logic_vector(8-1 downto 0); 72 | M_AXI_ARSIZE : out std_logic_vector(3-1 downto 0); 73 | M_AXI_ARBURST : out std_logic_vector(2-1 downto 0); 74 | M_AXI_ARLOCK : out std_logic_vector(2-1 downto 0); 75 | M_AXI_ARCACHE : out std_logic_vector(4-1 downto 0); 76 | M_AXI_ARPROT : out std_logic_vector(3-1 downto 0); 77 | -- AXI3 M_AXI_ARREGION:out std_logic_vector(4-1 downto 0); 78 | M_AXI_ARQOS : out std_logic_vector(4-1 downto 0); 79 | M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0); 80 | M_AXI_ARVALID : out std_logic; 81 | M_AXI_ARREADY : in std_logic; 82 | 83 | -- Master Interface Read Data 84 | M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0); 85 | M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); 86 | M_AXI_RRESP : in std_logic_vector(2-1 downto 0); 87 | M_AXI_RLAST : in std_logic; 88 | M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0); 89 | M_AXI_RVALID : in std_logic; 90 | M_AXI_RREADY : out std_logic; 91 | 92 | -- Example Design only 93 | error : out std_logic 94 | ); 95 | 96 | end axi_master; 97 | 98 | ------------------------------------------------------------------------------- 99 | -- Architecture 100 | ------------------------------------------------------------------------------- 101 | architecture implementation of axi_master is 102 | begin 103 | end implementation; 104 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_slave_v1_00_a/data/axi_slave_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | #-- DISCLAIMER OF LIABILITY 2 | #-- 3 | #-- This file contains proprietary and confidential information of 4 | #-- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | #-- from Xilinx, and may be used, copied and/or disclosed only 6 | #-- pursuant to the terms of a valid license agreement with Xilinx. 7 | #-- 8 | #-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | #-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | #-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | #-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | #-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | #-- does not warrant that functions included in the Materials will 14 | #-- meet the requirements of Licensee, or that the operation of the 15 | #-- Materials will be uninterrupted or error-free, or that defects 16 | #-- in the Materials will be corrected. Furthermore, Xilinx does 17 | #-- not warrant or make any representations regarding use, or the 18 | #-- results of the use, of the Materials in terms of correctness, 19 | #-- accuracy, reliability or otherwise. 20 | #-- 21 | #-- Xilinx products are not designed or intended to be fail-safe, 22 | #-- or for use in any application requiring fail-safe performance, 23 | #-- such as life-support or safety devices or systems, Class III 24 | #-- medical devices, nuclear facilities, applications related to 25 | #-- the deployment of airbags, or any other applications that could 26 | #-- lead to death, personal injury or severe property or 27 | #-- environmental damage (individually and collectively, "critical 28 | #-- applications"). Customer assumes the sole risk and liability 29 | #-- of any use of Xilinx products in critical applications, 30 | #-- subject only to applicable laws and regulations governing 31 | #-- limitations on product liability. 32 | #-- 33 | #-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 34 | #-- 35 | #-- This disclaimer and copyright notice must be retained as part 36 | #-- of this file at all times. 37 | #-- 38 | ################################################################### 39 | ## 40 | ## Name : axi_slave 41 | ## Desc : Microprocessor Peripheral Description 42 | ## : Automatically generated by PsfUtility 43 | ## 44 | ################################################################### 45 | 46 | BEGIN axi_slave 47 | 48 | ## Peripheral Options 49 | OPTION IPTYPE = PERIPHERAL 50 | OPTION IMP_NETLIST = TRUE 51 | OPTION STYLE = HDL 52 | OPTION DESC = AXI Slave 53 | OPTION LONG_DESC = AXI Slave 54 | OPTION HDL = MIXED 55 | OPTION RUN_NGCBUILD = FALSE 56 | 57 | ## Bus Interfaces 58 | BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE 59 | 60 | ## Generics for VHDL or Parameters for Verilog 61 | PARAMETER C_S_AXI_ID_WIDTH = 1, DT = integer, BUS = S_AXI 62 | PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI 63 | PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = integer, RANGE = (32, 64, 128, 256), BUS = S_AXI 64 | PARAMETER C_S_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, VALUES = (AXI4 = AXI4, AXI4Lite = AXI4Lite, AXI3 = AXI3), BUS = S_AXI 65 | PARAMETER C_S_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI 66 | PARAMETER C_S_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI 67 | PARAMETER C_S_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = S_AXI 68 | PARAMETER C_S_AXI_AWUSER_WIDTH = 1, DT = integer, ISVALID = (C_S_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = S_AXI 69 | PARAMETER C_S_AXI_ARUSER_WIDTH = 1, DT = integer, ISVALID = (C_S_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = S_AXI 70 | PARAMETER C_S_AXI_WUSER_WIDTH = 1, DT = integer, ISVALID = (C_S_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = S_AXI 71 | PARAMETER C_S_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_S_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = S_AXI 72 | PARAMETER C_S_AXI_BUSER_WIDTH = 1, DT = integer, ISVALID = (C_S_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = S_AXI 73 | PARAMETER C_S_AXI_NUM_ADDR_RANGES = 1, BUS = S_AXI, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4) 74 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG00_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000 75 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG00_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL 76 | PARAMETER C_S_AXI_RNG01_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG01_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000 77 | PARAMETER C_S_AXI_RNG01_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG01_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL 78 | PARAMETER C_S_AXI_RNG02_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG02_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000 79 | PARAMETER C_S_AXI_RNG02_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG02_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL 80 | PARAMETER C_S_AXI_RNG03_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG03_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000 81 | PARAMETER C_S_AXI_RNG03_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG03_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL 82 | 83 | ## Ports 84 | PORT ACLK = "", BUS = S_AXI, DIR = I, SIGIS = CLK 85 | PORT ARESETN = ARESETN, BUS = S_AXI, DIR = I, SIGIS = RST 86 | PORT S_AXI_AWID = AWID, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ID_WIDTH-1):0] 87 | PORT S_AXI_AWADDR = AWADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0] 88 | PORT S_AXI_AWLEN = AWLEN, BUS = S_AXI, DIR = I, VEC = [7:0] 89 | PORT S_AXI_AWSIZE = AWSIZE, BUS = S_AXI, DIR = I, VEC = [2:0] 90 | PORT S_AXI_AWBURST = AWBURST, BUS = S_AXI, DIR = I, VEC = [1:0] 91 | PORT S_AXI_AWLOCK = AWLOCK, BUS = S_AXI, DIR = I, VEC = [1:0] 92 | PORT S_AXI_AWCACHE = AWCACHE, BUS = S_AXI, DIR = I, VEC = [3:0] 93 | PORT S_AXI_AWPROT = AWPROT, BUS = S_AXI, DIR = I, VEC = [2:0] 94 | PORT S_AXI_AWREGION = AWREGION, BUS = S_AXI, DIR = I, VEC = [3:0] 95 | PORT S_AXI_AWQOS = AWQOS, BUS = S_AXI, DIR = I, VEC = [3:0] 96 | PORT S_AXI_AWUSER = AWUSER, BUS = S_AXI, DIR = I, VEC = [C_S_AXI_AWUSER_WIDTH-1:0] 97 | PORT S_AXI_AWVALID = AWVALID, BUS = S_AXI, DIR = I 98 | PORT S_AXI_AWREADY = AWREADY, BUS = S_AXI, DIR = O 99 | PORT S_AXI_WID = WID, BUS = S_AXI, DIR = I, VEC = [C_S_AXI_ID_WIDTH-1:0] 100 | PORT S_AXI_WDATA = WDATA, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0] 101 | PORT S_AXI_WSTRB = WSTRB, BUS = S_AXI, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8) -1):0] 102 | PORT S_AXI_WLAST = WLAST, BUS = S_AXI, DIR = I 103 | PORT S_AXI_WUSER = WUSER, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_WUSER_WIDTH-1):0] 104 | PORT S_AXI_WVALID = WVALID, BUS = S_AXI, DIR = I 105 | PORT S_AXI_WREADY = WREADY, BUS = S_AXI, DIR = O 106 | PORT S_AXI_BID = BID, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_ID_WIDTH-1):0] 107 | PORT S_AXI_BRESP = BRESP, BUS = S_AXI, DIR = O, VEC = [1:0] 108 | PORT S_AXI_BUSER = BUSER, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_BUSER_WIDTH-1):0] 109 | PORT S_AXI_BVALID = BVALID, BUS = S_AXI, DIR = O 110 | PORT S_AXI_BREADY = BREADY, BUS = S_AXI, DIR = I 111 | PORT S_AXI_ARID = ARID, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ID_WIDTH-1):0 112 | PORT S_AXI_ARADDR = ARADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0 113 | PORT S_AXI_ARLEN = ARLEN, BUS = S_AXI, DIR = I, VEC = [7:0] 114 | PORT S_AXI_ARSIZE = ARSIZE, BUS = S_AXI, DIR = I, VEC = [2:0] 115 | PORT S_AXI_ARBURST = ARBURST, BUS = S_AXI, DIR = I, VEC = [1:0] 116 | PORT S_AXI_ARLOCK = ARLOCK, BUS = S_AXI, DIR = I, VEC = [1:0] 117 | PORT S_AXI_ARCACHE = ARCACHE, BUS = S_AXI, DIR = I, VEC = [3:0] 118 | PORT S_AXI_ARPROT = ARPROT, BUS = S_AXI, DIR = I, VEC = [2:0] 119 | PORT S_AXI_ARREGION = ARREGION, BUS = S_AXI, DIR = I, VEC = [3:0] 120 | PORT S_AXI_ARQOS = ARQOS, BUS = S_AXI, DIR = I, VEC = [3:0] 121 | PORT S_AXI_ARUSER = ARUSER, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ARUSER_WIDTH-1):0] 122 | PORT S_AXI_ARVALID = ARVALID, BUS = S_AXI, DIR = I 123 | PORT S_AXI_ARREADY = ARREADY, BUS = S_AXI, DIR = O 124 | PORT S_AXI_RID = RID, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_ID_WIDTH-1):0 125 | PORT S_AXI_RDATA = RDATA, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0] 126 | PORT S_AXI_RRESP = RRESP, BUS = S_AXI, DIR = O, VEC = [1:0] 127 | PORT S_AXI_RLAST = RLAST, BUS = S_AXI, DIR = O 128 | PORT S_AXI_RUSER = RUSER, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_RUSER_WIDTH-1):0] 129 | PORT S_AXI_RVALID = RVALID, BUS = S_AXI, DIR = O 130 | PORT S_AXI_RREADY = RREADY, BUS = S_AXI, DIR = I 131 | 132 | END 133 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_slave_v1_00_a/data/axi_slave_v2_1_0.mui: -------------------------------------------------------------------------------- 1 | 2 | 3 | 42 | 43 | 46 | C_S_AXI_ID_WIDTH 47 | 48 | 49 | 50 | '> 51 | 53 | C_S_AXI_ADDR_WIDTH 54 | 55 | 56 | 57 | '> 58 | 60 | C_S_AXI_DATA_WIDTH 61 | 62 | 63 | 64 | '> 65 | 67 | C_S_AXI_PROTOCOL 68 | 69 | 70 | 71 | '> 72 | 73 | 75 | C_S_AXI_SUPPORTS_READ 76 | 77 | 78 | 79 | '> 80 | 82 | C_S_AXI_SUPPORTS_WRITE 83 | 84 | 85 | 86 | '> 87 | 89 | C_S_AXI_SUPPORTS_USER_SIGNALS 90 | 91 | 92 | 93 | '> 94 | 96 | C_S_AXI_AWUSER_WIDTH 97 | 98 | 99 | 100 | '> 101 | 103 | C_S_AXI_ARUSER_WIDTH 104 | 105 | 106 | 107 | '> 108 | 110 | C_S_AXI_WUSER_WIDTH 111 | 112 | 113 | 114 | '> 115 | 117 | C_S_AXI_RUSER_WIDTH 118 | 119 | 120 | 121 | '> 122 | 124 | C_S_AXI_BUSER_WIDTH 125 | 126 | 127 | 128 | '> 129 | 131 | C_S_AXI_NUM_ADDR_RANGES 132 | 133 | 134 | 135 | '> 136 | 138 | C_S_AXI_RNG00_BASEADDR 139 | 140 | 141 | 142 | '> 143 | 145 | C_S_AXI_RNG00_HIGHADDR 146 | 147 | 148 | 149 | '> 150 | 152 | C_S_AXI_RNG01_BASEADDR 153 | 154 | 155 | 156 | '> 157 | 159 | C_S_AXI_RNG01_HIGHADDR 160 | 161 | 162 | 163 | '> 164 | 166 | C_S_AXI_RNG02_BASEADDR 167 | 168 | 169 | 170 | '> 171 | 173 | C_S_AXI_RNG02_HIGHADDR 174 | 175 | 176 | 177 | '> 178 | 180 | C_S_AXI_RNG03_BASEADDR 181 | 182 | 183 | 184 | '> 185 | 187 | C_S_AXI_RNG03_HIGHADDR 188 | 189 | 190 | 191 | '> 192 | ]> 193 | 194 | 195 | 196 | User 197 | 198 | Common 199 | &C_USE_ADVANCED_PORTS; 200 | 201 | 202 | 203 | System 204 | 205 | Addresses 206 | &C_S_AXI_NUM_ADDR_RANGES; 207 | &C_S_AXI_RNG00_BASEADDR; 208 | &C_S_AXI_RNG00_HIGHADDR; 209 | &C_S_AXI_RNG01_BASEADDR; 210 | &C_S_AXI_RNG01_HIGHADDR; 211 | &C_S_AXI_RNG02_BASEADDR; 212 | &C_S_AXI_RNG02_HIGHADDR; 213 | &C_S_AXI_RNG03_BASEADDR; 214 | &C_S_AXI_RNG03_HIGHADDR; 215 | 216 | 217 | S_AXI 218 | &C_S_AXI_PROTOCOL; 219 | &C_S_AXI_ID_WIDTH; 220 | &C_S_AXI_ADDR_WIDTH; 221 | &C_S_AXI_DATA_WIDTH; 222 | &C_S_AXI_SUPPORTS_READ; 223 | &C_S_AXI_SUPPORTS_WRITE; 224 | &C_S_AXI_SUPPORTS_USER_SIGNALS; 225 | &C_S_AXI_AWUSER_WIDTH; 226 | &C_S_AXI_ARUSER_WIDTH; 227 | &C_S_AXI_WUSER_WIDTH; 228 | &C_S_AXI_RUSER_WIDTH; 229 | &C_S_AXI_BUSER_WIDTH; 230 | 231 | 232 | 233 | 234 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_slave_v1_00_a/data/axi_slave_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ## -- DISCLAIMER OF LIABILITY 2 | ## -- 3 | ## -- This file contains proprietary and confidential information of 4 | ## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | ## -- from Xilinx, and may be used, copied and/or disclosed only 6 | ## -- pursuant to the terms of a valid license agreement with Xilinx. 7 | ## -- 8 | ## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | ## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | ## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | ## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | ## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | ## -- does not warrant that functions included in the Materials will 14 | ## -- meet the requirements of Licensee, or that the operation of the 15 | ## -- Materials will be uninterrupted or error-free, or that defects 16 | ## -- in the Materials will be corrected. Furthermore, Xilinx does 17 | ## -- not warrant or make any representations regarding use, or the 18 | ## -- results of the use, of the Materials in terms of correctness, 19 | ## -- accuracy, reliability or otherwise. 20 | ## -- 21 | ## -- Xilinx products are not designed or intended to be fail-safe, 22 | ## -- or for use in any application requiring fail-safe performance, 23 | ## -- such as life-support or safety devices or systems, Class III 24 | ## -- medical devices, nuclear facilities, applications related to 25 | ## -- the deployment of airbags, or any other applications that could 26 | ## -- lead to death, personal injury or severe property or 27 | ## -- environmental damage (individually and collectively, "critical 28 | ## -- applications"). Customer assumes the sole risk and liability 29 | ## -- of any use of Xilinx products in critical applications, 30 | ## -- subject only to applicable laws and regulations governing 31 | ## -- limitations on product liability. 32 | ## -- 33 | ## -- Copyright 2009 Xilinx, Inc. 34 | ## -- All rights reserved. 35 | ## -- 36 | ## -- This disclaimer and copyright notice must be retained as part 37 | ## -- of this file at all times. 38 | ## 39 | ############################################################################### 40 | ## 41 | ## axi_slave_v2_1_0.pao 42 | ## 43 | ## Peripheral Analyze Order File 44 | ## 45 | ## 46 | ############################################################################### 47 | 48 | 49 | #lib axi_slave_v1_00_a axi_slave.v verilog 50 | lib axi_slave_v1_00_a axi_slave.vhd vhdl 51 | 52 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_slave_v1_00_a/hdl/verilog/axi_slave.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. 3 | //-- 4 | //-- This file contains confidential and proprietary information 5 | //-- of Xilinx, Inc. and is protected under U.S. and 6 | //-- international copyright and other intellectual property 7 | //-- laws. 8 | //-- 9 | //-- DISCLAIMER 10 | //-- This disclaimer is not a license and does not grant any 11 | //-- rights to the materials distributed herewith. Except as 12 | //-- otherwise provided in a valid license issued to you by 13 | //-- Xilinx, and to the maximum extent permitted by applicable 14 | //-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | //-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | //-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | //-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | //-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | //-- (2) Xilinx shall not be liable (whether in contract or tort, 20 | //-- including negligence, or under any other theory of 21 | //-- liability) for any loss or damage of any kind or nature 22 | //-- related to, arising under or in connection with these 23 | //-- materials, including for any direct, or any indirect, 24 | //-- special, incidental, or consequential loss or damage 25 | //-- (including loss of data, profits, goodwill, or any type of 26 | //-- loss or damage suffered as a result of any action brought 27 | //-- by a third party) even if such damage or loss was 28 | //-- reasonably foreseeable or Xilinx had been advised of the 29 | //-- possibility of the same. 30 | //-- 31 | //-- CRITICAL APPLICATIONS 32 | //-- Xilinx products are not designed or intended to be fail- 33 | //-- safe, or for use in any application requiring fail-safe 34 | //-- performance, such as life-support or safety devices or 35 | //-- systems, Class III medical devices, nuclear facilities, 36 | //-- applications related to the deployment of airbags, or any 37 | //-- other applications that could lead to death, personal 38 | //-- injury, or severe property or environmental damage 39 | //-- (individually and collectively, "Critical 40 | //-- Applications"). Customer assumes the sole risk and 41 | //-- liability of any use of Xilinx products in Critical 42 | //-- Applications, subject only to applicable laws and 43 | //-- regulations governing limitations on product liability. 44 | //-- 45 | //-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | //-- PART OF THIS FILE AT ALL TIMES. 47 | //----------------------------------------------------------------------------- 48 | // 49 | // AXI Slave 50 | // 51 | // Verilog-standard: Verilog 2001 52 | //-------------------------------------------------------------------------- 53 | // 54 | // Structure: 55 | // axi_slave 56 | // 57 | //-------------------------------------------------------------------------- 58 | 59 | `timescale 1ns/1ps 60 | 61 | module axi_slave # 62 | ( 63 | parameter integer C_S_AXI_ID_WIDTH = 1, 64 | parameter integer C_S_AXI_ADDR_WIDTH = 32, 65 | parameter integer C_S_AXI_DATA_WIDTH = 32, 66 | parameter integer C_S_AXI_AWUSER_WIDTH = 1, 67 | parameter integer C_S_AXI_ARUSER_WIDTH = 1, 68 | parameter integer C_S_AXI_WUSER_WIDTH = 1, 69 | parameter integer C_S_AXI_RUSER_WIDTH = 1, 70 | parameter integer C_S_AXI_BUSER_WIDTH = 1 71 | ) 72 | ( 73 | // System Signals 74 | input wire ACLK, 75 | input wire ARESETN, 76 | 77 | // Slave Interface Write Address Ports 78 | input wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_AWID, 79 | input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, 80 | input wire [8-1:0] S_AXI_AWLEN, 81 | input wire [3-1:0] S_AXI_AWSIZE, 82 | input wire [2-1:0] S_AXI_AWBURST, 83 | input wire [2-1:0] S_AXI_AWLOCK, 84 | input wire [4-1:0] S_AXI_AWCACHE, 85 | input wire [3-1:0] S_AXI_AWPROT, 86 | input wire [4-1:0] S_AXI_AWREGION, 87 | input wire [4-1:0] S_AXI_AWQOS, 88 | input wire [C_S_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, 89 | input wire S_AXI_AWVALID, 90 | output wire S_AXI_AWREADY, 91 | 92 | // Slave Interface Write Data Ports 93 | input wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_WID, 94 | input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, 95 | input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, 96 | input wire S_AXI_WLAST, 97 | input wire [C_S_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, 98 | input wire S_AXI_WVALID, 99 | output wire S_AXI_WREADY, 100 | 101 | // Slave Interface Write Response Ports 102 | output wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_BID, 103 | output wire [2-1:0] S_AXI_BRESP, 104 | output wire [C_S_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, 105 | output wire S_AXI_BVALID, 106 | input wire S_AXI_BREADY, 107 | 108 | // Slave Interface Read Address Ports 109 | input wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_ARID, 110 | input wire [C_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, 111 | input wire [8-1:0] S_AXI_ARLEN, 112 | input wire [3-1:0] S_AXI_ARSIZE, 113 | input wire [2-1:0] S_AXI_ARBURST, 114 | input wire [2-1:0] S_AXI_ARLOCK, 115 | input wire [4-1:0] S_AXI_ARCACHE, 116 | input wire [3-1:0] S_AXI_ARPROT, 117 | input wire [4-1:0] S_AXI_ARREGION, 118 | input wire [4-1:0] S_AXI_ARQOS, 119 | input wire [C_S_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, 120 | input wire S_AXI_ARVALID, 121 | output wire S_AXI_ARREADY, 122 | 123 | // Slave Interface Read Data Ports 124 | output wire [C_S_AXI_ID_WIDTH-1:0] S_AXI_RID, 125 | output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, 126 | output wire [2-1:0] S_AXI_RRESP, 127 | output wire S_AXI_RLAST, 128 | output wire [C_S_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, 129 | output wire S_AXI_RVALID, 130 | input wire S_AXI_RREADY 131 | 132 | ); 133 | 134 | endmodule 135 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_slave_v1_00_a/hdl/vhdl/axi_slave.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------- 2 | -- 3 | -- AXI Slave 4 | -- 5 | ----------------------------------------------------------------------------- 6 | 7 | library ieee; 8 | use ieee.std_logic_1164.all; 9 | use ieee.numeric_std.all; 10 | use ieee.std_logic_misc.all; 11 | 12 | --library unisim; 13 | --use unisim.vcomponents.all; 14 | 15 | entity axi_slave is 16 | generic ( 17 | C_S_AXI_ID_WIDTH : integer := 1; 18 | C_S_AXI_ADDR_WIDTH : integer := 32; 19 | C_S_AXI_DATA_WIDTH : integer := 32; 20 | C_S_AXI_AWUSER_WIDTH : integer := 1; 21 | C_S_AXI_ARUSER_WIDTH : integer := 1; 22 | C_S_AXI_WUSER_WIDTH : integer := 1; 23 | C_S_AXI_RUSER_WIDTH : integer := 1; 24 | C_S_AXI_BUSER_WIDTH : integer := 1 25 | ); 26 | port( 27 | -- System Signals 28 | ACLK : in std_logic; 29 | ARESETN : in std_logic; 30 | 31 | -- Slave Interface Write Address Ports 32 | S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); 33 | S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 34 | S_AXI_AWLEN : in std_logic_vector(8-1 downto 0); 35 | S_AXI_AWSIZE : in std_logic_vector(3-1 downto 0); 36 | S_AXI_AWBURST : in std_logic_vector(2-1 downto 0); 37 | S_AXI_AWLOCK : in std_logic_vector(2-1 downto 0); 38 | S_AXI_AWCACHE : in std_logic_vector(4-1 downto 0); 39 | S_AXI_AWPROT : in std_logic_vector(3-1 downto 0); 40 | S_AXI_AWREGION : in std_logic_vector(4-1 downto 0); 41 | S_AXI_AWQOS : in std_logic_vector(4-1 downto 0); 42 | S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0); 43 | S_AXI_AWVALID : in std_logic; 44 | S_AXI_AWREADY : out std_logic; 45 | 46 | -- Slave Interface Write Data Ports 47 | S_AXI_WID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); 48 | S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 49 | S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); 50 | S_AXI_WLAST : in std_logic; 51 | S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0); 52 | S_AXI_WVALID : in std_logic; 53 | S_AXI_WREADY : out std_logic; 54 | 55 | -- Slave Interface Write Response Ports 56 | S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); 57 | S_AXI_BRESP : out std_logic_vector(2-1 downto 0); 58 | S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0); 59 | S_AXI_BVALID : out std_logic; 60 | S_AXI_BREADY : in std_logic; 61 | 62 | -- Slave Interface Read Address Ports 63 | S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); 64 | S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); 65 | S_AXI_ARLEN : in std_logic_vector(8-1 downto 0); 66 | S_AXI_ARSIZE : in std_logic_vector(3-1 downto 0); 67 | S_AXI_ARBURST : in std_logic_vector(2-1 downto 0); 68 | S_AXI_ARLOCK : in std_logic_vector(2-1 downto 0); 69 | S_AXI_ARCACHE : in std_logic_vector(4-1 downto 0); 70 | S_AXI_ARPROT : in std_logic_vector(3-1 downto 0); 71 | S_AXI_ARREGION : in std_logic_vector(4-1 downto 0); 72 | S_AXI_ARQOS : in std_logic_vector(4-1 downto 0); 73 | S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0); 74 | S_AXI_ARVALID : in std_logic; 75 | S_AXI_ARREADY : out std_logic; 76 | 77 | -- Slave Interface Read Data Ports 78 | S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); 79 | S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); 80 | S_AXI_RRESP : out std_logic_vector(2-1 downto 0); 81 | S_AXI_RLAST : out std_logic; 82 | S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0); 83 | S_AXI_RVALID : out std_logic; 84 | S_AXI_RREADY : in std_logic 85 | ); 86 | 87 | end axi_slave; 88 | 89 | architecture implementation of axi_slave is 90 | begin 91 | 92 | end implementation; 93 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_stream_v1_00_a/data/axi_stream_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | #-- DISCLAIMER OF LIABILITY 2 | #-- 3 | #-- This file contains proprietary and confidential information of 4 | #-- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | #-- from Xilinx, and may be used, copied and/or disclosed only 6 | #-- pursuant to the terms of a valid license agreement with Xilinx. 7 | #-- 8 | #-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | #-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | #-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | #-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | #-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | #-- does not warrant that functions included in the Materials will 14 | #-- meet the requirements of Licensee, or that the operation of the 15 | #-- Materials will be uninterrupted or error-free, or that defects 16 | #-- in the Materials will be corrected. Furthermore, Xilinx does 17 | #-- not warrant or make any representations regarding use, or the 18 | #-- results of the use, of the Materials in terms of correctness, 19 | #-- accuracy, reliability or otherwise. 20 | #-- 21 | #-- Xilinx products are not designed or intended to be fail-safe, 22 | #-- or for use in any application requiring fail-safe performance, 23 | #-- such as life-support or safety devices or systems, Class III 24 | #-- medical devices, nuclear facilities, applications related to 25 | #-- the deployment of airbags, or any other applications that could 26 | #-- lead to death, personal injury or severe property or 27 | #-- environmental damage (individually and collectively, "critical 28 | #-- applications"). Customer assumes the sole risk and liability 29 | #-- of any use of Xilinx products in critical applications, 30 | #-- subject only to applicable laws and regulations governing 31 | #-- limitations on product liability. 32 | #-- 33 | #-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 34 | #-- 35 | #-- This disclaimer and copyright notice must be retained as part 36 | #-- of this file at all times. 37 | #-- 38 | ################################################################### 39 | ## 40 | ## Name : axi_stream 41 | ## Desc : Microprocessor Peripheral Description 42 | ## : Automatically generated by PsfUtility 43 | ## 44 | ################################################################### 45 | 46 | BEGIN axi_stream 47 | 48 | ## Peripheral Options 49 | OPTION IPTYPE = PERIPHERAL 50 | OPTION IMP_NETLIST = TRUE 51 | OPTION HDL = VHDL 52 | OPTION USAGE_LEVEL = BASE_USER 53 | OPTION RUN_NGCBUILD = TRUE 54 | OPTION STYLE = HDL 55 | OPTION DESC = AXI Stream 56 | OPTION LONG_DESC = AXI4-Stream 57 | 58 | ## Bus Interfaces 59 | BUS_INTERFACE BUS = M_AXIS, BUS_STD = AXIS, BUS_TYPE = INITIATOR 60 | BUS_INTERFACE BUS = S_AXIS, BUS_STD = AXIS, BUS_TYPE = TARGET 61 | 62 | ## Generics for VHDL or Parameters for Verilog 63 | PARAMETER C_M_AXIS_DATA_WIDTH = 32, DT = INTEGER, RANGE = (32,64,128,256), BUS = M_AXIS 64 | PARAMETER C_S_AXIS_DATA_WIDTH = 32, DT = INTEGER, RANGE = (32,64,128,256), BUS = S_AXIS 65 | 66 | 67 | ## Ports 68 | PORT axi_aclk = "", DIR = I, SIGIS = CLK, BUS = M_AXIS:S_AXIS 69 | PORT axi_resetn = ARESETN, DIR = I, SIGIS = RST, BUS = M_AXIS:S_AXIS 70 | 71 | #PORT m_axis_aresetn = ARESETN, DIR = O, BUS = M_AXIS 72 | PORT m_axis_tdata = TDATA, DIR = O, VEC = [C_M_AXIS_DATA_WIDTH-1:0], BUS = M_AXIS, ENDIAN = LITTLE 73 | PORT m_axis_tstrb = TSTRB, DIR = O, VEC = [(C_M_AXIS_DATA_WIDTH/8)-1:0], BUS = M_AXIS, ENDIAN = LITTLE 74 | PORT m_axis_tvalid = TVALID, DIR = O, BUS = M_AXIS 75 | PORT m_axis_tready = TREADY, DIR = I, BUS = M_AXIS 76 | PORT m_axis_tlast = TLAST, DIR = O, BUS = M_AXIS 77 | 78 | #PORT s_axis_aresetn = ARESETN, DIR = I, BUS = S_AXIS 79 | PORT s_axis_tdata = TDATA, DIR = I, VEC = [C_S_AXIS_DATA_WIDTH-1:0], BUS = S_AXIS, ENDIAN = LITTLE 80 | PORT s_axis_tstrb = TSTRB, DIR = I, VEC = [(C_S_AXIS_DATA_WIDTH/8)-1:0], BUS = S_AXIS, ENDIAN = LITTLE 81 | PORT s_axis_tvalid = TVALID, DIR = I, BUS = S_AXIS 82 | PORT s_axis_tready = TREADY, DIR = O, BUS = S_AXIS 83 | PORT s_axis_tlast = TLAST, DIR = I, BUS = S_AXIS 84 | 85 | END 86 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_stream_v1_00_a/data/axi_stream_v2_1_0.mui: -------------------------------------------------------------------------------- 1 | 2 | 3 | 60 | 64 | C_M_AXIS_DATA_WIDTH 65 | 66 | Master Stream Data Width must be equal to 67 | MM2S Memory Map Data Width 68 | 69 | '> 70 | 71 | 73 | C_S_AXIS_DATA_WIDTH 74 | 75 | Slave Stream Data Width must be equal to 76 | S2MM Memory Map Data Width 77 | 78 | '> 79 | ]> 80 | 81 | 82 | 83 | System 84 | 85 | AXI 86 | &C_M_AXIS_DATA_WIDTH; 87 | &C_S_AXIS_DATA_WIDTH; 88 | 89 | 90 | 91 | 92 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_stream_v1_00_a/data/axi_stream_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ## -- DISCLAIMER OF LIABILITY 2 | ## -- 3 | ## -- This file contains proprietary and confidential information of 4 | ## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license 5 | ## -- from Xilinx, and may be used, copied and/or disclosed only 6 | ## -- pursuant to the terms of a valid license agreement with Xilinx. 7 | ## -- 8 | ## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 9 | ## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 10 | ## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT 11 | ## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, 12 | ## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx 13 | ## -- does not warrant that functions included in the Materials will 14 | ## -- meet the requirements of Licensee, or that the operation of the 15 | ## -- Materials will be uninterrupted or error-free, or that defects 16 | ## -- in the Materials will be corrected. Furthermore, Xilinx does 17 | ## -- not warrant or make any representations regarding use, or the 18 | ## -- results of the use, of the Materials in terms of correctness, 19 | ## -- accuracy, reliability or otherwise. 20 | ## -- 21 | ## -- Xilinx products are not designed or intended to be fail-safe, 22 | ## -- or for use in any application requiring fail-safe performance, 23 | ## -- such as life-support or safety devices or systems, Class III 24 | ## -- medical devices, nuclear facilities, applications related to 25 | ## -- the deployment of airbags, or any other applications that could 26 | ## -- lead to death, personal injury or severe property or 27 | ## -- environmental damage (individually and collectively, "critical 28 | ## -- applications"). Customer assumes the sole risk and liability 29 | ## -- of any use of Xilinx products in critical applications, 30 | ## -- subject only to applicable laws and regulations governing 31 | ## -- limitations on product liability. 32 | ## -- 33 | ## -- Copyright 2010 Xilinx, Inc. 34 | ## -- All rights reserved. 35 | ## -- 36 | ## -- This disclaimer and copyright notice must be retained as part 37 | ## -- of this file at all times. 38 | ## 39 | ############################################################################### 40 | ## 41 | ## axi_stream_v2_1_0.pao 42 | ## 43 | ## Peripheral Analyze Order File 44 | ## 45 | ## Generated by Xilinx IP Engineering 46 | ## 47 | ############################################################################### 48 | ## Helper Libraries 49 | 50 | 51 | ############################################################################### 52 | ## AXI Stream Core 53 | lib axi_stream_v1_00_a axi_stream.vhd vhdl 54 | 55 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/rtl/pcores/axi_stream_v1_00_a/hdl/vhdl/axi_stream.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- axi_stream 3 | ------------------------------------------------------------------------------- 4 | -- 5 | -- ************************************************************************* 6 | -- 7 | -- (c) Copyright 2010 Xilinx, Inc. All rights reserved. 8 | -- 9 | -- This file contains confidential and proprietary information 10 | -- of Xilinx, Inc. and is protected under U.S. and 11 | -- international copyright and other intellectual property 12 | -- laws. 13 | -- 14 | -- DISCLAIMER 15 | -- This disclaimer is not a license and does not grant any 16 | -- rights to the materials distributed herewith. Except as 17 | -- otherwise provided in a valid license issued to you by 18 | -- Xilinx, and to the maximum extent permitted by applicable 19 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 20 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 21 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 22 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 23 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 24 | -- (2) Xilinx shall not be liable (whether in contract or tort, 25 | -- including negligence, or under any other theory of 26 | -- liability) for any loss or damage of any kind or nature 27 | -- related to, arising under or in connection with these 28 | -- materials, including for any direct, or any indirect, 29 | -- special, incidental, or consequential loss or damage 30 | -- (including loss of data, profits, goodwill, or any type of 31 | -- loss or damage suffered as a result of any action brought 32 | -- by a third party) even if such damage or loss was 33 | -- reasonably foreseeable or Xilinx had been advised of the 34 | -- possibility of the same. 35 | -- 36 | -- CRITICAL APPLICATIONS 37 | -- Xilinx products are not designed or intended to be fail- 38 | -- safe, or for use in any application requiring fail-safe 39 | -- performance, such as life-support or safety devices or 40 | -- systems, Class III medical devices, nuclear facilities, 41 | -- applications related to the deployment of airbags, or any 42 | -- other applications that could lead to death, personal 43 | -- injury, or severe property or environmental damage 44 | -- (individually and collectively, "Critical 45 | -- Applications"). Customer assumes the sole risk and 46 | -- liability of any use of Xilinx products in Critical 47 | -- Applications, subject only to applicable laws and 48 | -- regulations governing limitations on product liability. 49 | -- 50 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 51 | -- PART OF THIS FILE AT ALL TIMES. 52 | -- 53 | -- ************************************************************************* 54 | -- 55 | ------------------------------------------------------------------------------- 56 | -- Filename: axi_stream.vhd 57 | -- Description: An AXI Stream interface example 58 | -- 59 | -- VHDL-Standard: VHDL'93 60 | ------------------------------------------------------------------------------- 61 | -- Structure: 62 | -- axi_stream.vhd 63 | -- 64 | ------------------------------------------------------------------------------- 65 | 66 | library ieee; 67 | use ieee.std_logic_1164.all; 68 | use ieee.numeric_std.all; 69 | use ieee.std_logic_misc.all; 70 | 71 | --library unisim; 72 | --use unisim.vcomponents.all; 73 | 74 | ------------------------------------------------------------------------------- 75 | entity axi_stream is 76 | generic( 77 | 78 | -- Master AXI Stream Data Width 79 | C_M_AXIS_DATA_WIDTH : integer range 32 to 256 := 32; 80 | 81 | -- Slave AXI Stream Data Width 82 | C_S_AXIS_DATA_WIDTH : integer range 32 to 256 := 32 83 | 84 | ); 85 | port ( 86 | 87 | -- Global Ports 88 | axi_aclk : in std_logic; 89 | axi_resetn : in std_logic; 90 | 91 | -- Master Stream Ports 92 | -- m_axis_aresetn : out std_logic; 93 | m_axis_tdata : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0); 94 | m_axis_tstrb : out std_logic_vector((C_M_AXIS_DATA_WIDTH/8)-1 downto 0); 95 | m_axis_tvalid : out std_logic; 96 | m_axis_tready : in std_logic; 97 | m_axis_tlast : out std_logic; 98 | 99 | -- Slave Stream Ports 100 | -- s_axis_aresetn : in std_logic; 101 | s_axis_tdata : in std_logic_vector(C_S_AXIS_DATA_WIDTH-1 downto 0); 102 | s_axis_tstrb : in std_logic_vector((C_S_AXIS_DATA_WIDTH/8)-1 downto 0); 103 | s_axis_tvalid : in std_logic; 104 | s_axis_tready : out std_logic; 105 | s_axis_tlast : in std_logic 106 | 107 | ); 108 | 109 | end axi_stream; 110 | 111 | ------------------------------------------------------------------------------- 112 | -- Architecture 113 | ------------------------------------------------------------------------------- 114 | architecture implementation of axi_stream is 115 | begin 116 | end implementation; 117 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/run/compile_verilog.sh: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlog -f filelist.v -------------------------------------------------------------------------------- /MyCodes/axi_ip/run/filelist.v: -------------------------------------------------------------------------------- 1 | ../rtl/axi_lite_master_v1_00_a/hdl/verilog/axi_lite_master.v 2 | ../rtl/axi_lite_slave_v1_00_a/hdl/verilog/axi_lite_slave.v 3 | ../verification/tb_axi_lite.v -------------------------------------------------------------------------------- /MyCodes/axi_ip/run/run.sh: -------------------------------------------------------------------------------- 1 | vsim -c tb_axi_lite 2 | vsim -view wave 3 | vsim -add wave /* -r 4 | vsim run -all -------------------------------------------------------------------------------- /MyCodes/axi_ip/run/transcript: -------------------------------------------------------------------------------- 1 | # ** Error: (vish-3296) Unknown option '-all'. 2 | # Use the -help option for complete vsim usage. 3 | -------------------------------------------------------------------------------- /MyCodes/axi_ip/verification/tb_axi_lite.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module tb_axi_lite (); 4 | 5 | 6 | reg M_AXI_ACLK ; 7 | reg M_AXI_ARESETN ; 8 | 9 | 10 | wire [31:0] M_AXI_AWADDR ; 11 | wire [2:0] M_AXI_AWPROT ; 12 | wire M_AXI_AWVALID ; 13 | wire M_AXI_AWREADY ; 14 | 15 | // Master Interface Write Data 16 | wire [31:0] M_AXI_WDATA ; 17 | wire [3:0] M_AXI_WSTRB ; 18 | wire M_AXI_WVALID ; 19 | wire M_AXI_WREADY ; 20 | 21 | // Master Interface Write Response 22 | wire [1:0] M_AXI_BRESP ; 23 | wire M_AXI_BVALID ; 24 | wire M_AXI_BREADY ; 25 | 26 | // Master Interface Read Address 27 | wire [31:0] M_AXI_ARADDR ; 28 | wire [2:0] M_AXI_ARPROT ; 29 | wire M_AXI_ARVALID ; 30 | wire M_AXI_ARREADY ; 31 | 32 | // Master Interface Read Data 33 | wire [31:0] M_AXI_RDATA ; 34 | wire [1:0] M_AXI_RRESP ; 35 | wire M_AXI_RVALID ; 36 | wire M_AXI_RREADY ; 37 | 38 | reg start_input_gpio ; 39 | 40 | 41 | 42 | axi_lite_master # 43 | ( 44 | .C_M_AXI_ADDR_WIDTH (32), 45 | .C_M_AXI_DATA_WIDTH (32), 46 | .C_NUM_COMMANDS (16), 47 | .READ_WRITE_ADDR (32'h88000000) 48 | ) 49 | MASTER 50 | ( 51 | // System Signals 52 | .M_AXI_ACLK (M_AXI_ACLK), 53 | .M_AXI_ARESETN (M_AXI_ARESETN), 54 | 55 | // Master Interface Write Address 56 | .M_AXI_AWADDR (M_AXI_AWADDR), 57 | .M_AXI_AWPROT (M_AXI_AWPROT), 58 | .M_AXI_AWVALID (M_AXI_AWVALID), 59 | .M_AXI_AWREADY (M_AXI_AWREADY), 60 | 61 | // Master Interface Write Data 62 | .M_AXI_WDATA (M_AXI_WDATA), 63 | .M_AXI_WSTRB (M_AXI_WSTRB), 64 | .M_AXI_WVALID (M_AXI_WVALID), 65 | .M_AXI_WREADY (M_AXI_WREADY), 66 | 67 | // Master Interface Write Response 68 | .M_AXI_BRESP (M_AXI_BRESP), 69 | .M_AXI_BVALID (M_AXI_BVALID), 70 | .M_AXI_BREADY (M_AXI_BREADY), 71 | 72 | // Master Interface Read Address 73 | .M_AXI_ARADDR (M_AXI_ARADDR), 74 | .M_AXI_ARPROT (M_AXI_ARPROT), 75 | .M_AXI_ARVALID (M_AXI_ARVALID), 76 | .M_AXI_ARREADY (M_AXI_ARREADY), 77 | 78 | // Master Interface Read Data 79 | .M_AXI_RDATA (M_AXI_RDATA), 80 | .M_AXI_RRESP (M_AXI_RRESP), 81 | .M_AXI_RVALID (M_AXI_RVALID), 82 | .M_AXI_RREADY (M_AXI_RREADY), 83 | 84 | //Example Output 85 | .DONE_SUCCESS (), 86 | .start_input_gpio (start_input_gpio), 87 | 88 | //Test Ports 89 | .test_awvalid (), 90 | .test_awaddr (), 91 | .test_wdata (), 92 | .test_wvalid (), 93 | .test_bready (), 94 | .test_bvalid (), 95 | .test_rready (), 96 | .test_araddr (), 97 | .test_arvalid (), 98 | .test_rdata (), 99 | .test_rvalid () 100 | ); 101 | 102 | axi_lite_final # 103 | ( 104 | .C_BASEADDR (32'h88000000), 105 | .C_HIGHADDR (32'h880001FF), 106 | .C_S_AXI_MIN_SIZE (32'h000001ff), 107 | .C_S_AXI_ADDR_WIDTH (32), 108 | .C_S_AXI_DATA_WIDTH (32), 109 | .C_NUM_REG (4) 110 | ) 111 | SLAVE 112 | ( 113 | // System Signals 114 | .ACLK (M_AXI_ACLK), 115 | .ARESETN (M_AXI_ARESETN), 116 | // Slave Interface Write Address Ports 117 | .S_AXI_AWADDR (M_AXI_AWADDR), 118 | .S_AXI_AWPROT (M_AXI_AWPROT), 119 | .S_AXI_AWVALID (M_AXI_AWVALID), 120 | .S_AXI_AWREADY (M_AXI_AWREADY), 121 | 122 | // Slave Interface Write Data Ports 123 | .S_AXI_WDATA (M_AXI_WDATA), 124 | .S_AXI_WSTRB (M_AXI_WSTRB), 125 | .S_AXI_WVALID (M_AXI_WVALID), 126 | .S_AXI_WREADY (M_AXI_WREADY), 127 | 128 | // Slave Interface Write Response Ports 129 | .S_AXI_BRESP (M_AXI_BRESP), 130 | .S_AXI_BVALID (M_AXI_BVALID), 131 | .S_AXI_BREADY (M_AXI_BREADY), 132 | 133 | // Slave Interface Read Address Ports 134 | .S_AXI_ARADDR (M_AXI_ARADDR), 135 | .S_AXI_ARPROT (M_AXI_ARPROT), 136 | .S_AXI_ARVALID (M_AXI_ARVALID), 137 | .S_AXI_ARREADY (M_AXI_ARREADY), 138 | 139 | // Slave Interface Read Data Ports 140 | .S_AXI_RDATA (M_AXI_RDATA), 141 | .S_AXI_RRESP (M_AXI_RRESP), 142 | .S_AXI_RVALID (M_AXI_RVALID), 143 | .S_AXI_RREADY (M_AXI_RREADY) 144 | ); 145 | 146 | 147 | initial 148 | begin 149 | M_AXI_ACLK = 1'b0 ; 150 | M_AXI_ARESETN = 1'b0 ; 151 | start_input_gpio = 1'b0; 152 | #500 M_AXI_ARESETN = 1'b1 ; 153 | start_input_gpio = 1'b1 ; 154 | #30000 $stop; 155 | end 156 | 157 | always #50 M_AXI_ACLK = ~ M_AXI_ACLK ; 158 | 159 | endmodule 160 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | OpenProjects 2 | ============ 3 | Work repository --------------------------------------------------------------------------------