├── ARM9
    └── uart_top.v
├── DDCA
    ├── MIPS
    │   ├── mips.sv
    │   └── mips.vhd
    └── Mont_VHDL.vhd
├── EE287
    └── FIFO
    │   ├── fifo_Mar10v3_worked.v
    │   ├── fifo_Mar6v2_unworked.v
    │   ├── ftb.v
    │   ├── mem1k.v
    │   ├── runfifo.pl
    │   └── topfifo.v
├── Labs
    ├── Lab01
    │   ├── circ.v
    │   ├── hwres2.txt
    │   ├── run2.pl
    │   └── synres.txt
    └── Lab02_03
    │   ├── fpmul111.v
    │   ├── fpmul200.v
    │   ├── hwres2.txt
    │   ├── run2.pl
    │   └── synres.txt
├── README.md
├── ciletti
    └── Advanced Digital Design with the Verilog HDL源码
    │   ├── Chapter 10
    │       ├── ADDVB_Models_10.doc
    │       ├── Dividers
    │       │   ├── Divider_RR_STG.v
    │       │   ├── Divider_STG_0.v
    │       │   ├── Divider_STG_0_sub.v
    │       │   ├── Divider_STG_1.v
    │       │   ├── _vti_cnf
    │       │   │   ├── Divider_RR_STG.v
    │       │   │   ├── Divider_STG_0.v
    │       │   │   ├── Divider_STG_0_sub.v
    │       │   │   ├── Divider_STG_1.v
    │       │   │   └── t_Divider_RR_STG.v
    │       │   └── t_Divider_RR_STG.v
    │       ├── Multipliers
    │       │   ├── Multiplier_ASM_0.v
    │       │   ├── Multiplier_ASM_1.v
    │       │   ├── Multiplier_Booth_STG_0.v
    │       │   ├── Multiplier_Implicit_1.v
    │       │   ├── Multiplier_Implicit_2.v
    │       │   ├── Multiplier_RR_ASM.v
    │       │   ├── Multiplier_STG_0.v
    │       │   ├── Multiplier_STG_1.v
    │       │   ├── Radix_4__STG_0.v
    │       │   └── _vti_cnf
    │       │   │   ├── Multiplier_ASM_0.v
    │       │   │   ├── Multiplier_ASM_1.v
    │       │   │   ├── Multiplier_Booth_STG_0.v
    │       │   │   ├── Multiplier_Implicit_1.v
    │       │   │   ├── Multiplier_Implicit_2.v
    │       │   │   ├── Multiplier_RR_ASM.v
    │       │   │   ├── Multiplier_STG_0.v
    │       │   │   ├── Multiplier_STG_1.v
    │       │   │   └── Radix_4__STG_0.v
    │       └── _vti_cnf
    │       │   └── ADDVB_Models_10.doc
    │   ├── Chapter 11
    │       ├── ADDVB_Models_11.doc
    │       ├── BIST
    │       │   ├── ASIC_with_BIST.v
    │       │   ├── _vti_cnf
    │       │   │   ├── ASIC_with_BIST.v
    │       │   │   └── t_ASIC_with_BIST.v
    │       │   └── t_ASIC_with_BIST.v
    │       ├── JTAG
    │       │   ├── ASIC_with_TAP.v
    │       │   ├── BR_Cell.v
    │       │   ├── BSC_Cell.v
    │       │   ├── Boundary_Scan_Register.v
    │       │   ├── IR_Cell.v
    │       │   ├── Instruction_Decoder.v
    │       │   ├── Instruction_Register.v
    │       │   ├── TAP_FSM.v
    │       │   ├── TDI_Generator.v
    │       │   ├── TDO_Monitor.v
    │       │   ├── _vti_cnf
    │       │   │   ├── ASIC_with_TAP.v
    │       │   │   ├── BR_Cell.v
    │       │   │   ├── BSC_Cell.v
    │       │   │   ├── Boundary_Scan_Register.v
    │       │   │   ├── IR_Cell.v
    │       │   │   ├── Instruction_Decoder.v
    │       │   │   ├── Instruction_Register.v
    │       │   │   ├── TAP_FSM.v
    │       │   │   ├── TDI_Generator.v
    │       │   │   ├── TDO_Monitor.v
    │       │   │   ├── t_ASIC_with_TAP.v
    │       │   │   ├── t_Boundary_Scan_Register.v
    │       │   │   ├── t_Instruction_Register.v
    │       │   │   └── tap_controller.v
    │       │   ├── t_ASIC_with_TAP.v
    │       │   ├── t_Boundary_Scan_Register.v
    │       │   ├── t_Instruction_Register.v
    │       │   └── tap_controller.v
    │       ├── Latch_Races.v
    │       └── _vti_cnf
    │       │   ├── ADDVB_Models_11.doc
    │       │   └── Latch_Races.v
    │   ├── Chapter 4
    │       ├── ADDVB_Models_4.doc
    │       ├── AOI_UDP.v
    │       ├── AOI_str.v
    │       ├── Add_rca_4.v
    │       ├── Mux_2_32_CA.v
    │       ├── Mux_4_32_CA.v
    │       ├── Mux_4_32_CA_if.v
    │       ├── Mux_4_32_case.v
    │       ├── _vti_cnf
    │       │   ├── ADDVB_Models_4.doc
    │       │   ├── AOI_UDP.v
    │       │   ├── AOI_str.v
    │       │   ├── Add_rca_4.v
    │       │   ├── Mux_2_32_CA.v
    │       │   ├── Mux_4_32_CA.v
    │       │   ├── Mux_4_32_CA_if.v
    │       │   ├── Mux_4_32_case.v
    │       │   ├── compare_2_str.v
    │       │   ├── compare_4_str.v
    │       │   ├── t_Add_full_ASIC.v
    │       │   ├── t_Add_full_unit_delay.v
    │       │   ├── t_Add_half.v
    │       │   ├── t_Add_rca_4_Unit_Delay.v
    │       │   └── test_hiZ.v
    │       ├── compare_2_str.v
    │       ├── compare_4_str.v
    │       ├── t_Add_full_ASIC.v
    │       ├── t_Add_full_unit_delay.v
    │       ├── t_Add_half.v
    │       ├── t_Add_rca_4_Unit_Delay.v
    │       └── test_hiZ.v
    │   ├── Chapter 5
    │       ├── ADDVB_Models_5.doc
    │       ├── AOI_5_CA0.v
    │       ├── AOI_5_CA1.v
    │       ├── AOI_5_CA2.v
    │       ├── AOI_5_CA3.v
    │       ├── Auto_LFSR_ALGO.v
    │       ├── Auto_LFSR_Param.v
    │       ├── Auto_LFSR_RTL.v
    │       ├── Hex_Keypad_Grayhill_072.v
    │       ├── Latch_CA.v
    │       ├── Latch_Rbar_CA.v
    │       ├── Majority.v
    │       ├── Majority_4b.v
    │       ├── Mux_4_32_CA.v
    │       ├── Mux_4_32_case.v
    │       ├── Mux_4_32_if.v
    │       ├── Par_load_reg4.v
    │       ├── Register_File.v
    │       ├── Row_Signal.v
    │       ├── Seven_Seg_Display.v
    │       ├── Shift_reg4.v
    │       ├── Synchronizer.v
    │       ├── Universal_Shift_Reg.v
    │       ├── Universal_Shift_Register.v
    │       ├── Up_Down_Implicit1.v
    │       ├── _vti_cnf
    │       │   ├── ADDVB_Models_5.doc
    │       │   ├── AOI_5_CA0.v
    │       │   ├── AOI_5_CA1.v
    │       │   ├── AOI_5_CA2.v
    │       │   ├── AOI_5_CA3.v
    │       │   ├── Auto_LFSR_ALGO.v
    │       │   ├── Auto_LFSR_Param.v
    │       │   ├── Auto_LFSR_RTL.v
    │       │   ├── Hex_Keypad_Grayhill_072.v
    │       │   ├── Latch_CA.v
    │       │   ├── Latch_Rbar_CA.v
    │       │   ├── Majority.v
    │       │   ├── Majority_4b.v
    │       │   ├── Mux_4_32_CA.v
    │       │   ├── Mux_4_32_case.v
    │       │   ├── Mux_4_32_if.v
    │       │   ├── Par_load_reg4.v
    │       │   ├── Register_File.v
    │       │   ├── Row_Signal.v
    │       │   ├── Seven_Seg_Display.v
    │       │   ├── Shift_reg4.v
    │       │   ├── Synchronizer.v
    │       │   ├── Universal_Shift_Reg.v
    │       │   ├── Universal_Shift_Register.v
    │       │   ├── Up_Down_Implicit1.v
    │       │   ├── add_4cycle.v
    │       │   ├── adder_task.v
    │       │   ├── arithmetic_unit.v
    │       │   ├── asynch_df_behav.v
    │       │   ├── barrel_shifter.v
    │       │   ├── comparator.v
    │       │   ├── compare_2_CA0.v
    │       │   ├── compare_2_CA1.txt
    │       │   ├── compare_2_CA1.v
    │       │   ├── compare_2_ROM.v
    │       │   ├── compare_2_RTL.v
    │       │   ├── compare_2_algo.v
    │       │   ├── compare_32_CA.v
    │       │   ├── decoder.v
    │       │   ├── df_behav.v
    │       │   ├── encoder.v
    │       │   ├── find_first_one.v
    │       │   ├── pipe_2stage.v
    │       │   ├── priority.v
    │       │   ├── ring_counter.v
    │       │   ├── shift_reg_PA.v
    │       │   ├── shiftreg_PA.v
    │       │   ├── shiftreg_PA_rev.v
    │       │   ├── shiftreg_nb.v
    │       │   ├── synchro_2.v
    │       │   ├── t_AOI_5_CA1.v
    │       │   ├── t_AOI_5_CA2.v
    │       │   ├── t_Bin_Cnt_Part_RTL.v
    │       │   ├── t_Hex_Keypad_Grayhill_072.v
    │       │   ├── t_Latch_CA.v
    │       │   ├── t_Latch_Rbar_CA.v
    │       │   ├── tr_latch.v
    │       │   ├── up_down_counter.v
    │       │   └── word_aligner.v
    │       ├── add_4cycle.v
    │       ├── adder_task.v
    │       ├── arithmetic_unit.v
    │       ├── asynch_df_behav.v
    │       ├── barrel_shifter.v
    │       ├── comparator.v
    │       ├── compare_2_CA0.v
    │       ├── compare_2_CA1.txt
    │       ├── compare_2_CA1.v
    │       ├── compare_2_ROM.v
    │       ├── compare_2_RTL.v
    │       ├── compare_2_algo.v
    │       ├── compare_32_CA.v
    │       ├── decoder.v
    │       ├── df_behav.v
    │       ├── encoder.v
    │       ├── find_first_one.v
    │       ├── pipe_2stage.v
    │       ├── priority.v
    │       ├── ring_counter.v
    │       ├── shift_reg_PA.v
    │       ├── shiftreg_PA.v
    │       ├── shiftreg_PA_rev.v
    │       ├── shiftreg_nb.v
    │       ├── synchro_2.v
    │       ├── t_AOI_5_CA1.v
    │       ├── t_AOI_5_CA2.v
    │       ├── t_Bin_Cnt_Part_RTL.v
    │       ├── t_Hex_Keypad_Grayhill_072.v
    │       ├── t_Latch_CA.v
    │       ├── t_Latch_Rbar_CA.v
    │       ├── tr_latch.v
    │       ├── up_down_counter.v
    │       └── word_aligner.v
    │   ├── Chapter 6
    │       ├── ADDVB_Models_6.doc
    │       ├── Add_Accum_1.v
    │       ├── Add_Accum_2.v
    │       ├── Add_Accum_both.v
    │       ├── BCD_to_Excess_3a.v
    │       ├── BCD_to_Excess_3b.v
    │       ├── BCD_to_Excess_3b_Post.v
    │       ├── BCD_to_Excess_3c.v
    │       ├── BCD_to_Excess_3c_Post.v
    │       ├── Bi_dir_bus.v
    │       ├── D_reg4_a.v
    │       ├── Latched_Seven_Seg_Display.v
    │       ├── NRZI.v
    │       ├── NRZ_2_Manchester_Mealy.v
    │       ├── NRZ_2_Manchester_Mealy_Post.v
    │       ├── NRZ_2_Manchester_Moore.v
    │       ├── NRZ_2_Manchester_Moore_Post.v
    │       ├── Seq_Rec_3_1s.v
    │       ├── Seq_Rec_3_1s_Mealy.v
    │       ├── Seq_Rec_3_1s_Moore.v
    │       ├── Seq_Rec_3_1s_Shft_Reg.v
    │       ├── Seq_Rec_Moore_imp.v
    │       ├── Test_Seq_Rec_Moore_imp.v
    │       ├── Test_count_ones_IMP.v
    │       ├── Test_count_ones_SD.v
    │       ├── Test_count_ones_SD_0.v
    │       ├── Test_count_ones_SM.v
    │       ├── Test_count_ones_a.v
    │       ├── Test_count_ones_b.v
    │       ├── Test_count_ones_c.v
    │       ├── Test_count_ones_d.v
    │       ├── Uni_dir_bus.v.doc
    │       ├── _vti_cnf
    │       │   ├── ADDVB_Models_6.doc
    │       │   ├── Add_Accum_1.v
    │       │   ├── Add_Accum_2.v
    │       │   ├── Add_Accum_both.v
    │       │   ├── BCD_to_Excess_3a.v
    │       │   ├── BCD_to_Excess_3b.v
    │       │   ├── BCD_to_Excess_3b_Post.v
    │       │   ├── BCD_to_Excess_3c.v
    │       │   ├── BCD_to_Excess_3c_Post.v
    │       │   ├── Bi_dir_bus.v
    │       │   ├── D_reg4_a.v
    │       │   ├── Latched_Seven_Seg_Display.v
    │       │   ├── NRZI.v
    │       │   ├── NRZ_2_Manchester_Mealy.v
    │       │   ├── NRZ_2_Manchester_Mealy_Post.v
    │       │   ├── NRZ_2_Manchester_Moore.v
    │       │   ├── NRZ_2_Manchester_Moore_Post.v
    │       │   ├── Seq_Rec_3_1s.v
    │       │   ├── Seq_Rec_3_1s_Mealy.v
    │       │   ├── Seq_Rec_3_1s_Moore.v
    │       │   ├── Seq_Rec_3_1s_Shft_Reg.v
    │       │   ├── Seq_Rec_Moore_imp.v
    │       │   ├── Test_Seq_Rec_Moore_imp.v
    │       │   ├── Test_count_ones_IMP.v
    │       │   ├── Test_count_ones_SD.v
    │       │   ├── Test_count_ones_SM.v
    │       │   ├── Test_count_ones_a.v
    │       │   ├── Test_count_ones_b.v
    │       │   ├── Test_count_ones_c.v
    │       │   ├── Test_count_ones_d.v
    │       │   ├── Uni_dir_bus.v.doc
    │       │   ├── alu_with_z1.v
    │       │   ├── badd_4.v
    │       │   ├── boole_opt.v
    │       │   ├── count_ones_IMP.v
    │       │   ├── count_ones_SD.v
    │       │   ├── count_ones_SM.v
    │       │   ├── count_ones_a.v
    │       │   ├── count_ones_b.v
    │       │   ├── count_ones_b0.v
    │       │   ├── count_ones_b1.v
    │       │   ├── count_ones_b2.v
    │       │   ├── count_ones_c.v
    │       │   ├── count_ones_d.v
    │       │   ├── expression_sub.v
    │       │   ├── expression_sub_nb.v
    │       │   ├── for_and_loop_comb.v
    │       │   ├── latch_if1.v
    │       │   ├── latch_if2.v
    │       │   ├── multiple_reg_assign.v
    │       │   ├── mux_4pri.v
    │       │   ├── mux_latch.v
    │       │   ├── mux_logic.v
    │       │   ├── mux_reg.v
    │       │   ├── operator_group.v
    │       │   ├── or4_behav.v
    │       │   ├── or4_behav_latch.v
    │       │   ├── or_nand.v
    │       │   ├── res_share.v
    │       │   ├── ripple_counter.v
    │       │   ├── shifter_1.v
    │       │   ├── shifter_2.v
    │       │   ├── swap_synch.v
    │       │   ├── t_BCD_Excess_3.v
    │       │   └── test_NRZ_2_Manchester_Moore.v
    │       ├── alu_with_z1.v
    │       ├── badd_4.v
    │       ├── boole_opt.v
    │       ├── count_ones_IMP.v
    │       ├── count_ones_SD.v
    │       ├── count_ones_SD_0.v
    │       ├── count_ones_SM.v
    │       ├── count_ones_a.v
    │       ├── count_ones_b.v
    │       ├── count_ones_b0.v
    │       ├── count_ones_b1.v
    │       ├── count_ones_b2.v
    │       ├── count_ones_c.v
    │       ├── count_ones_d.v
    │       ├── expression_sub.v
    │       ├── expression_sub_nb.v
    │       ├── for_and_loop_comb.v
    │       ├── latch_if1.v
    │       ├── latch_if2.v
    │       ├── multiple_reg_assign.v
    │       ├── mux_4pri.v
    │       ├── mux_latch.v
    │       ├── mux_logic.v
    │       ├── mux_reg.v
    │       ├── operator_group.v
    │       ├── or4_behav.v
    │       ├── or4_behav_latch.v
    │       ├── or_nand.v
    │       ├── res_share.v
    │       ├── ripple_counter.v
    │       ├── shifter_1.v
    │       ├── shifter_2.v
    │       ├── swap_synch.v
    │       ├── t_BCD_Excess_3.v
    │       └── test_NRZ_2_Manchester_Moore.v
    │   ├── Chapter 7
    │       ├── ADDVB_Models_7.doc
    │       ├── ADDVB_Models_7.v.txt
    │       ├── Bin_Cnt_Part_RTL.v
    │       ├── Bin_Cnt_Part_RTL_by_3.v
    │       ├── Clock_Unit.v
    │       ├── Gap_Finder.doc
    │       ├── Gap_Finder.v
    │       ├── RISC_SPM.v
    │       ├── UART_xmtr_Arch.v
    │       ├── _vti_cnf
    │       │   ├── ADDVB_Models_7.doc
    │       │   ├── Bin_Cnt_Part_RTL.v
    │       │   ├── Bin_Cnt_Part_RTL_by_3.v
    │       │   ├── RISC_SPM.v
    │       │   ├── UART_xmtr_Arch.v
    │       │   ├── t_Bin_Cnt_Part_RTL_by_3.v
    │       │   ├── test_RISC_SPM.v
    │       │   ├── uart8_rcvr.v
    │       │   └── uart8_rcvr_partition.v
    │       ├── t_Bin_Cnt_Part_RTL_by_3.v
    │       ├── test_RISC_SPM.v
    │       ├── uart8_rcvr.v
    │       └── uart8_rcvr_partition.v
    │   ├── Chapter 8
    │       ├── ADDVB_Models_8.doc
    │       ├── BCD_to_Excess_3_ROM.v
    │       ├── Counter8_prog.v
    │       ├── FIFO.v
    │       ├── PLA_array.v
    │       ├── PLA_plane.v
    │       ├── RAM_2048_8.v
    │       ├── RAM_static.v
    │       ├── RAM_static_BD.v
    │       ├── Row_Signal.v
    │       ├── SRAM_with_Con.v
    │       ├── _vti_cnf
    │       │   ├── ADDVB_Models_8.doc
    │       │   ├── BCD_to_Excess_3_ROM.v
    │       │   ├── Counter8_prog.v
    │       │   ├── FIFO.v
    │       │   ├── PLA_array.v
    │       │   ├── PLA_plane.v
    │       │   ├── RAM_2048_8.v
    │       │   ├── RAM_static.v
    │       │   ├── RAM_static_BD.v
    │       │   ├── Row_Signal.v
    │       │   ├── SRAM_with_Con.v
    │       │   ├── t_keypad_FIFO.v
    │       │   └── top_keypad_FIFO.v
    │       ├── t_keypad_FIFO.v
    │       └── top_keypad_FIFO.v
    │   ├── Chapter 9
    │       ├── ADDVB_Models_9.doc
    │       ├── Bubble Sorter
    │       │   ├── Bubble_sort.v
    │       │   ├── _vti_cnf
    │       │   │   └── Bubble_sort.v
    │       │   └── t_Bubble_Sort.v
    │       ├── DSP
    │       │   ├── FIR_Gaussian.v
    │       │   ├── IIR_Filter.v
    │       │   ├── Integrator_Seq.v
    │       │   ├── _vti_cnf
    │       │   │   ├── FIR_Gaussian.v
    │       │   │   ├── IIR_Filter.v
    │       │   │   ├── Integrator_Seq.v
    │       │   │   ├── decimator_1.v
    │       │   │   ├── decimator_2.v
    │       │   │   ├── decimator_3.v
    │       │   │   ├── integrator_par.v
    │       │   │   ├── t_Integrator_Seq.v
    │       │   │   ├── t_decimator_1.v
    │       │   │   ├── t_decimator_2.v
    │       │   │   ├── t_decimator_3.v
    │       │   │   ├── t_integrator_par.v
    │       │   │   ├── test_FIR_Gaussian.v
    │       │   │   └── test_IIR.v
    │       │   ├── decimator_1.v
    │       │   ├── decimator_2.v
    │       │   ├── decimator_3.v
    │       │   ├── integrator_par.v
    │       │   ├── t_Integrator_Seq.v
    │       │   ├── t_decimator_1.v
    │       │   ├── t_decimator_2.v
    │       │   ├── t_decimator_3.v
    │       │   ├── t_integrator_par.v
    │       │   ├── test_FIR_Gaussian.v
    │       │   └── test_IIR.v
    │       ├── Pipeline and FIFO
    │       │   ├── Circular_Buffer_1.v
    │       │   ├── Circular_Buffer_2.v
    │       │   ├── FIFO_Buffer.v
    │       │   ├── Ser_Par_Conv_32.v
    │       │   ├── Ser_Par_Conv_8.v
    │       │   ├── _vti_cnf
    │       │   │   ├── Circular_Buffer_1.v
    │       │   │   ├── Circular_Buffer_2.v
    │       │   │   ├── FIFO_Buffer.v
    │       │   │   ├── Ser_Par_Conv_32.v
    │       │   │   ├── Ser_Par_Conv_8.v
    │       │   │   ├── t_Circular_Buffers.v
    │       │   │   ├── t_FIFO_Buffer.v
    │       │   │   ├── t_FIFO_Clock_Domain_Synch.v
    │       │   │   ├── t_Ser_Par_Conv_32.v
    │       │   │   ├── t_Ser_Par_Conv_8.v
    │       │   │   ├── t_write_synch.v
    │       │   │   └── write_synch.v
    │       │   ├── t_Circular_Buffers.v
    │       │   ├── t_FIFO_Buffer.v
    │       │   ├── t_FIFO_Clock_Domain_Synch.v
    │       │   ├── t_Ser_Par_Conv_32.v
    │       │   ├── t_Ser_Par_Conv_8.v
    │       │   ├── t_write_synch.v
    │       │   └── write_synch.v
    │       ├── Pixel Converter
    │       │   ├── Image_Converter_0.v
    │       │   ├── Image_Converter_1.v
    │       │   ├── Image_Converter_Baseline.v
    │       │   ├── Image_converter_2.v
    │       │   ├── _vti_cnf
    │       │   │   ├── Image_Converter_0.v
    │       │   │   ├── Image_Converter_1.v
    │       │   │   ├── Image_Converter_Baseline.v
    │       │   │   ├── Image_converter_2.v
    │       │   │   ├── t_Image_Converter_0.v
    │       │   │   ├── t_Image_Converter_1.v
    │       │   │   ├── t_Image_Converter_2.v
    │       │   │   └── t_Image_Converter_Baseline.v
    │       │   ├── t_Image_Converter_0.v
    │       │   ├── t_Image_Converter_1.v
    │       │   ├── t_Image_Converter_2.v
    │       │   └── t_Image_Converter_Baseline.v
    │       ├── _vti_cnf
    │       │   └── ADDVB_Models_9.doc
    │       └── add_16_pipe.v
    │   ├── Clock generator
    │       ├── Clock_Prog.v
    │       ├── Clock_Unit.v
    │       ├── clock.v
    │       ├── clock_1_2.v
    │       └── clock_gen.v
    │   ├── FAQs.doc
    │   ├── Models and Testbenches 11_10_2004
    │       ├── Chapter 10
    │       │   ├── ADDVB_Models_10.doc
    │       │   ├── Dividers
    │       │   │   ├── Divider_RR_STG.v
    │       │   │   ├── Divider_STG_0.v
    │       │   │   ├── Divider_STG_0_sub.v
    │       │   │   ├── Divider_STG_1.v
    │       │   │   ├── _vti_cnf
    │       │   │   │   ├── Divider_RR_STG.v
    │       │   │   │   ├── Divider_STG_0.v
    │       │   │   │   ├── Divider_STG_0_sub.v
    │       │   │   │   ├── Divider_STG_1.v
    │       │   │   │   └── t_Divider_RR_STG.v
    │       │   │   └── t_Divider_RR_STG.v
    │       │   ├── Multipliers
    │       │   │   ├── Multiplier_ASM_0.v
    │       │   │   ├── Multiplier_ASM_1.v
    │       │   │   ├── Multiplier_Booth_STG_0.v
    │       │   │   ├── Multiplier_Implicit_1.v
    │       │   │   ├── Multiplier_Implicit_2.v
    │       │   │   ├── Multiplier_RR_ASM.v
    │       │   │   ├── Multiplier_STG_0.v
    │       │   │   ├── Multiplier_STG_1.v
    │       │   │   ├── Radix_4__STG_0.v
    │       │   │   └── _vti_cnf
    │       │   │   │   ├── Multiplier_ASM_0.v
    │       │   │   │   ├── Multiplier_ASM_1.v
    │       │   │   │   ├── Multiplier_Booth_STG_0.v
    │       │   │   │   ├── Multiplier_Implicit_1.v
    │       │   │   │   ├── Multiplier_Implicit_2.v
    │       │   │   │   ├── Multiplier_RR_ASM.v
    │       │   │   │   ├── Multiplier_STG_0.v
    │       │   │   │   ├── Multiplier_STG_1.v
    │       │   │   │   └── Radix_4__STG_0.v
    │       │   └── _vti_cnf
    │       │   │   └── ADDVB_Models_10.doc
    │       ├── Chapter 11
    │       │   ├── ADDVB_Models_11.doc
    │       │   ├── BIST
    │       │   │   ├── ASIC_with_BIST.v
    │       │   │   ├── _vti_cnf
    │       │   │   │   ├── ASIC_with_BIST.v
    │       │   │   │   └── t_ASIC_with_BIST.v
    │       │   │   └── t_ASIC_with_BIST.v
    │       │   ├── JTAG
    │       │   │   ├── ASIC_with_TAP.v
    │       │   │   ├── BR_Cell.v
    │       │   │   ├── BSC_Cell.v
    │       │   │   ├── Boundary_Scan_Register.v
    │       │   │   ├── IR_Cell.v
    │       │   │   ├── Instruction_Decoder.v
    │       │   │   ├── Instruction_Register.v
    │       │   │   ├── TAP_FSM.v
    │       │   │   ├── TDI_Generator.v
    │       │   │   ├── TDO_Monitor.v
    │       │   │   ├── _vti_cnf
    │       │   │   │   ├── ASIC_with_TAP.v
    │       │   │   │   ├── BR_Cell.v
    │       │   │   │   ├── BSC_Cell.v
    │       │   │   │   ├── Boundary_Scan_Register.v
    │       │   │   │   ├── IR_Cell.v
    │       │   │   │   ├── Instruction_Decoder.v
    │       │   │   │   ├── Instruction_Register.v
    │       │   │   │   ├── TAP_FSM.v
    │       │   │   │   ├── TDI_Generator.v
    │       │   │   │   ├── TDO_Monitor.v
    │       │   │   │   ├── t_ASIC_with_TAP.v
    │       │   │   │   ├── t_Boundary_Scan_Register.v
    │       │   │   │   ├── t_Instruction_Register.v
    │       │   │   │   └── tap_controller.v
    │       │   │   ├── t_ASIC_with_TAP.v
    │       │   │   ├── t_Boundary_Scan_Register.v
    │       │   │   ├── t_Instruction_Register.v
    │       │   │   └── tap_controller.v
    │       │   ├── Latch_Races.v
    │       │   └── _vti_cnf
    │       │   │   ├── ADDVB_Models_11.doc
    │       │   │   └── Latch_Races.v
    │       ├── Chapter 4
    │       │   ├── ADDVB_Models_4.doc
    │       │   ├── AOI_UDP.v
    │       │   ├── AOI_str.v
    │       │   ├── Add_rca_4.v
    │       │   ├── Mux_2_32_CA.v
    │       │   ├── Mux_4_32_CA.v
    │       │   ├── Mux_4_32_CA_if.v
    │       │   ├── Mux_4_32_case.v
    │       │   ├── _vti_cnf
    │       │   │   ├── ADDVB_Models_4.doc
    │       │   │   ├── AOI_UDP.v
    │       │   │   ├── AOI_str.v
    │       │   │   ├── Add_rca_4.v
    │       │   │   ├── Mux_2_32_CA.v
    │       │   │   ├── Mux_4_32_CA.v
    │       │   │   ├── Mux_4_32_CA_if.v
    │       │   │   ├── Mux_4_32_case.v
    │       │   │   ├── compare_2_str.v
    │       │   │   ├── compare_4_str.v
    │       │   │   ├── t_Add_full_ASIC.v
    │       │   │   ├── t_Add_full_unit_delay.v
    │       │   │   ├── t_Add_half.v
    │       │   │   ├── t_Add_rca_4_Unit_Delay.v
    │       │   │   └── test_hiZ.v
    │       │   ├── compare_2_str.v
    │       │   ├── compare_4_str.v
    │       │   ├── t_Add_full_ASIC.v
    │       │   ├── t_Add_full_unit_delay.v
    │       │   ├── t_Add_half.v
    │       │   ├── t_Add_rca_4_Unit_Delay.v
    │       │   └── test_hiZ.v
    │       ├── Chapter 5
    │       │   ├── ADDVB_Models_5.doc
    │       │   ├── AOI_5_CA0.v
    │       │   ├── AOI_5_CA1.v
    │       │   ├── AOI_5_CA2.v
    │       │   ├── AOI_5_CA3.v
    │       │   ├── Auto_LFSR_ALGO.v
    │       │   ├── Auto_LFSR_Param.v
    │       │   ├── Auto_LFSR_RTL.v
    │       │   ├── Hex_Keypad_Grayhill_072.v
    │       │   ├── Latch_CA.v
    │       │   ├── Latch_Rbar_CA.v
    │       │   ├── Majority.v
    │       │   ├── Majority_4b.v
    │       │   ├── Mux_4_32_CA.v
    │       │   ├── Mux_4_32_case.v
    │       │   ├── Mux_4_32_if.v
    │       │   ├── Par_load_reg4.v
    │       │   ├── Register_File.v
    │       │   ├── Row_Signal.v
    │       │   ├── Seven_Seg_Display.v
    │       │   ├── Shift_reg4.v
    │       │   ├── Synchronizer.v
    │       │   ├── Universal_Shift_Reg.v
    │       │   ├── Universal_Shift_Register.v
    │       │   ├── Up_Down_Implicit1.v
    │       │   ├── _vti_cnf
    │       │   │   ├── ADDVB_Models_5.doc
    │       │   │   ├── AOI_5_CA0.v
    │       │   │   ├── AOI_5_CA1.v
    │       │   │   ├── AOI_5_CA2.v
    │       │   │   ├── AOI_5_CA3.v
    │       │   │   ├── Auto_LFSR_ALGO.v
    │       │   │   ├── Auto_LFSR_Param.v
    │       │   │   ├── Auto_LFSR_RTL.v
    │       │   │   ├── Hex_Keypad_Grayhill_072.v
    │       │   │   ├── Latch_CA.v
    │       │   │   ├── Latch_Rbar_CA.v
    │       │   │   ├── Majority.v
    │       │   │   ├── Majority_4b.v
    │       │   │   ├── Mux_4_32_CA.v
    │       │   │   ├── Mux_4_32_case.v
    │       │   │   ├── Mux_4_32_if.v
    │       │   │   ├── Par_load_reg4.v
    │       │   │   ├── Register_File.v
    │       │   │   ├── Row_Signal.v
    │       │   │   ├── Seven_Seg_Display.v
    │       │   │   ├── Shift_reg4.v
    │       │   │   ├── Synchronizer.v
    │       │   │   ├── Universal_Shift_Reg.v
    │       │   │   ├── Universal_Shift_Register.v
    │       │   │   ├── Up_Down_Implicit1.v
    │       │   │   ├── add_4cycle.v
    │       │   │   ├── adder_task.v
    │       │   │   ├── arithmetic_unit.v
    │       │   │   ├── asynch_df_behav.v
    │       │   │   ├── barrel_shifter.v
    │       │   │   ├── comparator.v
    │       │   │   ├── compare_2_CA0.v
    │       │   │   ├── compare_2_CA1.txt
    │       │   │   ├── compare_2_CA1.v
    │       │   │   ├── compare_2_ROM.v
    │       │   │   ├── compare_2_RTL.v
    │       │   │   ├── compare_2_algo.v
    │       │   │   ├── compare_32_CA.v
    │       │   │   ├── decoder.v
    │       │   │   ├── df_behav.v
    │       │   │   ├── encoder.v
    │       │   │   ├── find_first_one.v
    │       │   │   ├── pipe_2stage.v
    │       │   │   ├── priority.v
    │       │   │   ├── ring_counter.v
    │       │   │   ├── shift_reg_PA.v
    │       │   │   ├── shiftreg_PA.v
    │       │   │   ├── shiftreg_PA_rev.v
    │       │   │   ├── shiftreg_nb.v
    │       │   │   ├── synchro_2.v
    │       │   │   ├── t_AOI_5_CA1.v
    │       │   │   ├── t_AOI_5_CA2.v
    │       │   │   ├── t_Bin_Cnt_Part_RTL.v
    │       │   │   ├── t_Hex_Keypad_Grayhill_072.v
    │       │   │   ├── t_Latch_CA.v
    │       │   │   ├── t_Latch_Rbar_CA.v
    │       │   │   ├── tr_latch.v
    │       │   │   ├── up_down_counter.v
    │       │   │   └── word_aligner.v
    │       │   ├── add_4cycle.v
    │       │   ├── adder_task.v
    │       │   ├── arithmetic_unit.v
    │       │   ├── asynch_df_behav.v
    │       │   ├── barrel_shifter.v
    │       │   ├── comparator.v
    │       │   ├── compare_2_CA0.v
    │       │   ├── compare_2_CA1.txt
    │       │   ├── compare_2_CA1.v
    │       │   ├── compare_2_ROM.v
    │       │   ├── compare_2_RTL.v
    │       │   ├── compare_2_algo.v
    │       │   ├── compare_32_CA.v
    │       │   ├── decoder.v
    │       │   ├── df_behav.v
    │       │   ├── encoder.v
    │       │   ├── find_first_one.v
    │       │   ├── pipe_2stage.v
    │       │   ├── priority.v
    │       │   ├── ring_counter.v
    │       │   ├── shift_reg_PA.v
    │       │   ├── shiftreg_PA.v
    │       │   ├── shiftreg_PA_rev.v
    │       │   ├── shiftreg_nb.v
    │       │   ├── synchro_2.v
    │       │   ├── t_AOI_5_CA1.v
    │       │   ├── t_AOI_5_CA2.v
    │       │   ├── t_Bin_Cnt_Part_RTL.v
    │       │   ├── t_Hex_Keypad_Grayhill_072.v
    │       │   ├── t_Latch_CA.v
    │       │   ├── t_Latch_Rbar_CA.v
    │       │   ├── tr_latch.v
    │       │   ├── up_down_counter.v
    │       │   └── word_aligner.v
    │       ├── Chapter 6
    │       │   ├── ADDVB_Models_6.doc
    │       │   ├── Add_Accum_1.v
    │       │   ├── Add_Accum_2.v
    │       │   ├── Add_Accum_both.v
    │       │   ├── BCD_to_Excess_3a.v
    │       │   ├── BCD_to_Excess_3b.v
    │       │   ├── BCD_to_Excess_3b_Post.v
    │       │   ├── BCD_to_Excess_3c.v
    │       │   ├── BCD_to_Excess_3c_Post.v
    │       │   ├── Bi_dir_bus.v
    │       │   ├── D_reg4_a.v
    │       │   ├── Latched_Seven_Seg_Display.v
    │       │   ├── NRZI.v
    │       │   ├── NRZ_2_Manchester_Mealy.v
    │       │   ├── NRZ_2_Manchester_Mealy_Post.v
    │       │   ├── NRZ_2_Manchester_Moore.v
    │       │   ├── NRZ_2_Manchester_Moore_Post.v
    │       │   ├── Seq_Rec_3_1s.v
    │       │   ├── Seq_Rec_3_1s_Mealy.v
    │       │   ├── Seq_Rec_3_1s_Moore.v
    │       │   ├── Seq_Rec_3_1s_Shft_Reg.v
    │       │   ├── Seq_Rec_Moore_imp.v
    │       │   ├── Test_Seq_Rec_Moore_imp.v
    │       │   ├── Test_count_ones_IMP.v
    │       │   ├── Test_count_ones_SD.v
    │       │   ├── Test_count_ones_SD_0.v
    │       │   ├── Test_count_ones_SM.v
    │       │   ├── Test_count_ones_a.v
    │       │   ├── Test_count_ones_b.v
    │       │   ├── Test_count_ones_c.v
    │       │   ├── Test_count_ones_d.v
    │       │   ├── Uni_dir_bus.v.doc
    │       │   ├── _vti_cnf
    │       │   │   ├── ADDVB_Models_6.doc
    │       │   │   ├── Add_Accum_1.v
    │       │   │   ├── Add_Accum_2.v
    │       │   │   ├── Add_Accum_both.v
    │       │   │   ├── BCD_to_Excess_3a.v
    │       │   │   ├── BCD_to_Excess_3b.v
    │       │   │   ├── BCD_to_Excess_3b_Post.v
    │       │   │   ├── BCD_to_Excess_3c.v
    │       │   │   ├── BCD_to_Excess_3c_Post.v
    │       │   │   ├── Bi_dir_bus.v
    │       │   │   ├── D_reg4_a.v
    │       │   │   ├── Latched_Seven_Seg_Display.v
    │       │   │   ├── NRZI.v
    │       │   │   ├── NRZ_2_Manchester_Mealy.v
    │       │   │   ├── NRZ_2_Manchester_Mealy_Post.v
    │       │   │   ├── NRZ_2_Manchester_Moore.v
    │       │   │   ├── NRZ_2_Manchester_Moore_Post.v
    │       │   │   ├── Seq_Rec_3_1s.v
    │       │   │   ├── Seq_Rec_3_1s_Mealy.v
    │       │   │   ├── Seq_Rec_3_1s_Moore.v
    │       │   │   ├── Seq_Rec_3_1s_Shft_Reg.v
    │       │   │   ├── Seq_Rec_Moore_imp.v
    │       │   │   ├── Test_Seq_Rec_Moore_imp.v
    │       │   │   ├── Test_count_ones_IMP.v
    │       │   │   ├── Test_count_ones_SD.v
    │       │   │   ├── Test_count_ones_SM.v
    │       │   │   ├── Test_count_ones_a.v
    │       │   │   ├── Test_count_ones_b.v
    │       │   │   ├── Test_count_ones_c.v
    │       │   │   ├── Test_count_ones_d.v
    │       │   │   ├── Uni_dir_bus.v.doc
    │       │   │   ├── alu_with_z1.v
    │       │   │   ├── badd_4.v
    │       │   │   ├── boole_opt.v
    │       │   │   ├── count_ones_IMP.v
    │       │   │   ├── count_ones_SD.v
    │       │   │   ├── count_ones_SM.v
    │       │   │   ├── count_ones_a.v
    │       │   │   ├── count_ones_b.v
    │       │   │   ├── count_ones_b0.v
    │       │   │   ├── count_ones_b1.v
    │       │   │   ├── count_ones_b2.v
    │       │   │   ├── count_ones_c.v
    │       │   │   ├── count_ones_d.v
    │       │   │   ├── expression_sub.v
    │       │   │   ├── expression_sub_nb.v
    │       │   │   ├── for_and_loop_comb.v
    │       │   │   ├── latch_if1.v
    │       │   │   ├── latch_if2.v
    │       │   │   ├── multiple_reg_assign.v
    │       │   │   ├── mux_4pri.v
    │       │   │   ├── mux_latch.v
    │       │   │   ├── mux_logic.v
    │       │   │   ├── mux_reg.v
    │       │   │   ├── operator_group.v
    │       │   │   ├── or4_behav.v
    │       │   │   ├── or4_behav_latch.v
    │       │   │   ├── or_nand.v
    │       │   │   ├── res_share.v
    │       │   │   ├── ripple_counter.v
    │       │   │   ├── shifter_1.v
    │       │   │   ├── shifter_2.v
    │       │   │   ├── swap_synch.v
    │       │   │   ├── t_BCD_Excess_3.v
    │       │   │   └── test_NRZ_2_Manchester_Moore.v
    │       │   ├── alu_with_z1.v
    │       │   ├── badd_4.v
    │       │   ├── boole_opt.v
    │       │   ├── count_ones_IMP.v
    │       │   ├── count_ones_SD.v
    │       │   ├── count_ones_SD_0.v
    │       │   ├── count_ones_SM.v
    │       │   ├── count_ones_a.v
    │       │   ├── count_ones_b.v
    │       │   ├── count_ones_b0.v
    │       │   ├── count_ones_b1.v
    │       │   ├── count_ones_b2.v
    │       │   ├── count_ones_c.v
    │       │   ├── count_ones_d.v
    │       │   ├── expression_sub.v
    │       │   ├── expression_sub_nb.v
    │       │   ├── for_and_loop_comb.v
    │       │   ├── latch_if1.v
    │       │   ├── latch_if2.v
    │       │   ├── multiple_reg_assign.v
    │       │   ├── mux_4pri.v
    │       │   ├── mux_latch.v
    │       │   ├── mux_logic.v
    │       │   ├── mux_reg.v
    │       │   ├── operator_group.v
    │       │   ├── or4_behav.v
    │       │   ├── or4_behav_latch.v
    │       │   ├── or_nand.v
    │       │   ├── res_share.v
    │       │   ├── ripple_counter.v
    │       │   ├── shifter_1.v
    │       │   ├── shifter_2.v
    │       │   ├── swap_synch.v
    │       │   ├── t_BCD_Excess_3.v
    │       │   └── test_NRZ_2_Manchester_Moore.v
    │       ├── Chapter 7
    │       │   ├── ADDVB_Models_7.doc
    │       │   ├── ADDVB_Models_7.v.txt
    │       │   ├── Bin_Cnt_Part_RTL.v
    │       │   ├── Bin_Cnt_Part_RTL_by_3.v
    │       │   ├── Clock_Unit.v
    │       │   ├── Gap_Finder.doc
    │       │   ├── Gap_Finder.v
    │       │   ├── RISC_SPM.v
    │       │   ├── UART_xmtr_Arch.v
    │       │   ├── _vti_cnf
    │       │   │   ├── ADDVB_Models_7.doc
    │       │   │   ├── Bin_Cnt_Part_RTL.v
    │       │   │   ├── Bin_Cnt_Part_RTL_by_3.v
    │       │   │   ├── RISC_SPM.v
    │       │   │   ├── UART_xmtr_Arch.v
    │       │   │   ├── t_Bin_Cnt_Part_RTL_by_3.v
    │       │   │   ├── test_RISC_SPM.v
    │       │   │   ├── uart8_rcvr.v
    │       │   │   └── uart8_rcvr_partition.v
    │       │   ├── t_Bin_Cnt_Part_RTL_by_3.v
    │       │   ├── test_RISC_SPM.v
    │       │   ├── uart8_rcvr.v
    │       │   └── uart8_rcvr_partition.v
    │       ├── Chapter 8
    │       │   ├── ADDVB_Models_8.doc
    │       │   ├── BCD_to_Excess_3_ROM.v
    │       │   ├── Counter8_prog.v
    │       │   ├── FIFO.v
    │       │   ├── PLA_array.v
    │       │   ├── PLA_plane.v
    │       │   ├── RAM_2048_8.v
    │       │   ├── RAM_static.v
    │       │   ├── RAM_static_BD.v
    │       │   ├── Row_Signal.v
    │       │   ├── SRAM_with_Con.v
    │       │   ├── _vti_cnf
    │       │   │   ├── ADDVB_Models_8.doc
    │       │   │   ├── BCD_to_Excess_3_ROM.v
    │       │   │   ├── Counter8_prog.v
    │       │   │   ├── FIFO.v
    │       │   │   ├── PLA_array.v
    │       │   │   ├── PLA_plane.v
    │       │   │   ├── RAM_2048_8.v
    │       │   │   ├── RAM_static.v
    │       │   │   ├── RAM_static_BD.v
    │       │   │   ├── Row_Signal.v
    │       │   │   ├── SRAM_with_Con.v
    │       │   │   ├── t_keypad_FIFO.v
    │       │   │   └── top_keypad_FIFO.v
    │       │   ├── t_keypad_FIFO.v
    │       │   └── top_keypad_FIFO.v
    │       ├── Chapter 9
    │       │   ├── ADDVB_Models_9.doc
    │       │   ├── Bubble Sorter
    │       │   │   ├── Bubble_sort.v
    │       │   │   └── _vti_cnf
    │       │   │   │   └── Bubble_sort.v
    │       │   ├── DSP
    │       │   │   ├── FIR_Gaussian.v
    │       │   │   ├── IIR_Filter.v
    │       │   │   ├── Integrator_Seq.v
    │       │   │   ├── _vti_cnf
    │       │   │   │   ├── FIR_Gaussian.v
    │       │   │   │   ├── IIR_Filter.v
    │       │   │   │   ├── Integrator_Seq.v
    │       │   │   │   ├── decimator_1.v
    │       │   │   │   ├── decimator_2.v
    │       │   │   │   ├── decimator_3.v
    │       │   │   │   ├── integrator_par.v
    │       │   │   │   ├── t_Integrator_Seq.v
    │       │   │   │   ├── t_decimator_1.v
    │       │   │   │   ├── t_decimator_2.v
    │       │   │   │   ├── t_decimator_3.v
    │       │   │   │   ├── t_integrator_par.v
    │       │   │   │   ├── test_FIR_Gaussian.v
    │       │   │   │   └── test_IIR.v
    │       │   │   ├── decimator_1.v
    │       │   │   ├── decimator_2.v
    │       │   │   ├── decimator_3.v
    │       │   │   ├── integrator_par.v
    │       │   │   ├── t_Integrator_Seq.v
    │       │   │   ├── t_decimator_1.v
    │       │   │   ├── t_decimator_2.v
    │       │   │   ├── t_decimator_3.v
    │       │   │   ├── t_integrator_par.v
    │       │   │   ├── test_FIR_Gaussian.v
    │       │   │   └── test_IIR.v
    │       │   ├── Pipeline and FIFO
    │       │   │   ├── Circular_Buffer_1.v
    │       │   │   ├── Circular_Buffer_2.v
    │       │   │   ├── FIFO_Buffer.v
    │       │   │   ├── Ser_Par_Conv_32.v
    │       │   │   ├── Ser_Par_Conv_8.v
    │       │   │   ├── _vti_cnf
    │       │   │   │   ├── Circular_Buffer_1.v
    │       │   │   │   ├── Circular_Buffer_2.v
    │       │   │   │   ├── FIFO_Buffer.v
    │       │   │   │   ├── Ser_Par_Conv_32.v
    │       │   │   │   ├── Ser_Par_Conv_8.v
    │       │   │   │   ├── t_Circular_Buffers.v
    │       │   │   │   ├── t_FIFO_Buffer.v
    │       │   │   │   ├── t_FIFO_Clock_Domain_Synch.v
    │       │   │   │   ├── t_Ser_Par_Conv_32.v
    │       │   │   │   ├── t_Ser_Par_Conv_8.v
    │       │   │   │   ├── t_write_synch.v
    │       │   │   │   └── write_synch.v
    │       │   │   ├── t_Circular_Buffers.v
    │       │   │   ├── t_FIFO_Buffer.v
    │       │   │   ├── t_FIFO_Clock_Domain_Synch.v
    │       │   │   ├── t_Ser_Par_Conv_32.v
    │       │   │   ├── t_Ser_Par_Conv_8.v
    │       │   │   ├── t_write_synch.v
    │       │   │   └── write_synch.v
    │       │   ├── Pixel Converter
    │       │   │   ├── Image_Converter_0.v
    │       │   │   ├── Image_Converter_1.v
    │       │   │   ├── Image_Converter_Baseline.v
    │       │   │   ├── Image_converter_2.v
    │       │   │   ├── _vti_cnf
    │       │   │   │   ├── Image_Converter_0.v
    │       │   │   │   ├── Image_Converter_1.v
    │       │   │   │   ├── Image_Converter_Baseline.v
    │       │   │   │   ├── Image_converter_2.v
    │       │   │   │   ├── t_Image_Converter_0.v
    │       │   │   │   ├── t_Image_Converter_1.v
    │       │   │   │   ├── t_Image_Converter_2.v
    │       │   │   │   └── t_Image_Converter_Baseline.v
    │       │   │   ├── t_Image_Converter_0.v
    │       │   │   ├── t_Image_Converter_1.v
    │       │   │   ├── t_Image_Converter_2.v
    │       │   │   └── t_Image_Converter_Baseline.v
    │       │   └── _vti_cnf
    │       │   │   └── ADDVB_Models_9.doc
    │       ├── Clock generator
    │       │   ├── Clock_Prog.v
    │       │   ├── Clock_Unit.v
    │       │   ├── clock.v
    │       │   ├── clock_1_2.v
    │       │   └── clock_gen.v
    │       └── README.txt
    │   └── README.txt
├── hmc-mips-7-3-15
    ├── debug.fdo
    ├── doc
    │   ├── Test_Plan.doc
    │   ├── decodestage.vsd
    │   ├── executestage.vsd
    │   ├── fetchstage.vsd
    │   ├── memorystage.vsd
    │   ├── mipsblock.vsd
    │   └── originalblock.vsd
    ├── fpga.fdo
    ├── multdiv.fdo
    ├── src
    │   ├── README.txt
    │   ├── components.v
    │   ├── imem.v
    │   ├── mem.v
    │   ├── memtests.v
    │   ├── mipspipelined.v
    │   ├── multdiv.v
    │   └── top.v
    ├── testing
    │   ├── Makefile
    │   ├── adelaide
    │   │   ├── Cache-for_testing.jelib
    │   │   ├── Cache.jelib
    │   │   ├── DecoderBench.java
    │   │   ├── muddlib07.jelib
    │   │   ├── test_adrtagdatalogic.cmd
    │   │   ├── test_byteenlog.cmd
    │   │   ├── test_dataout_read.cmd
    │   │   ├── test_dataout_write.cmd
    │   │   ├── test_decoder64.cmd
    │   │   ├── test_decoder64_1.cmd
    │   │   ├── test_mux2_1x_32.cmd
    │   │   ├── test_mux2_4.cmd
    │   │   ├── test_mux2_c_1x.cmd
    │   │   ├── test_mux2_dp_1x.cmd
    │   │   ├── test_mux2_zip.cmd
    │   │   └── test_srambit.cmd
    │   ├── fpga.v
    │   ├── fpgabench.v
    │   ├── mipstest.v
    │   ├── moduletests
    │   │   ├── md_rand_001.tv
    │   │   ├── mdvectorgen.py
    │   │   ├── multdiv.tv
    │   │   └── multdivtest.v
    │   ├── test_000.asm
    │   ├── test_000.dat
    │   ├── test_001.asm
    │   ├── test_001.dat
    │   ├── test_002.asm
    │   ├── test_002.dat
    │   ├── test_003.asm
    │   ├── test_003.dat
    │   ├── test_004.asm
    │   ├── test_004.dat
    │   ├── test_005.asm
    │   ├── test_005.dat
    │   ├── test_006.asm
    │   ├── test_006.dat
    │   ├── test_007.asm
    │   ├── test_007.dat
    │   ├── test_008.asm
    │   ├── test_008.dat
    │   ├── test_009.asm
    │   ├── test_009.dat
    │   ├── test_010.asm
    │   ├── test_010.dat
    │   ├── test_011.asm
    │   ├── test_011.dat
    │   ├── test_012.asm
    │   ├── test_012.c
    │   ├── test_012.dat
    │   ├── test_013.asm
    │   ├── test_013.dat
    │   ├── test_014.asm
    │   ├── test_014.dat
    │   ├── test_015.asm
    │   ├── test_015.dat
    │   ├── test_016.c
    │   ├── test_016.dat
    │   ├── test_017.c
    │   ├── test_017.dat
    │   ├── test_018.asm
    │   ├── test_018.dat
    │   ├── test_019.asm
    │   ├── test_019.dat
    │   ├── test_020.asm
    │   ├── test_020.dat
    │   ├── test_021.asm
    │   ├── test_021.dat
    │   ├── test_022.asm
    │   ├── test_022.dat
    │   ├── test_023.asm
    │   ├── test_023.dat
    │   ├── test_024.asm
    │   ├── test_024.dat
    │   ├── test_025.asm
    │   ├── test_025.dat
    │   ├── test_026.asm
    │   ├── test_026.c
    │   ├── test_026.dat
    │   └── test_fp_001.c
    ├── wave_alu.do
    └── wave_multdiv.do
├── learnVerilog_2013
    ├── Cilietti
    │   ├── Clock_Unit.v
    │   ├── RISC_SPM.v
    │   ├── RISC_SPM_20130220155415.jpg
    │   └── test_RISC_SPM.v
    └── Verilog HDL
    │   ├── component.v
    │   ├── stimulus.v
    │   └── success_Feb212013.png
├── mips2k
    └── MIPS2K.v
├── verilog 100 examples
    ├── ADC_16bit.v
    ├── ALL.V
    ├── COMPARE.V
    ├── DECODER1.V
    ├── FIFO_2.V
    ├── MUL16.V
    ├── MUX8X8.V
    ├── PLI.TAR
    ├── PLI
    │   ├── Makefile
    │   ├── README
    │   ├── mypli.c
    │   ├── mypli.h
    │   ├── mypli.tab
    │   ├── mypli.v
    │   ├── pliread.c
    │   ├── pliread.dat
    │   ├── pliread.h
    │   ├── pliread.tab
    │   └── pliread.v
    ├── RISC8.ZIP
    ├── RISC8
    │   ├── BASIC.HEX
    │   ├── COPYING
    │   ├── DDS.HEX
    │   ├── alu.v
    │   ├── basic.asm
    │   ├── basic.rom
    │   ├── cpu.v
    │   ├── dds.asm
    │   ├── dds.rom
    │   ├── dram.v
    │   ├── exp.v
    │   ├── hex2v.c
    │   ├── idec.v
    │   ├── pram.v
    │   ├── regs.v
    │   ├── risc8.gif
    │   ├── risc8doc.html
    │   ├── runit
    │   ├── sindata.c
    │   ├── sindata.hex
    │   └── test.v
    ├── SHIFTER.V
    ├── SYNTHPIC.ZIP
    ├── SYNTHPIC
    │   ├── HEX2VHDL.CPP
    │   ├── HEX2VHDL.EXE
    │   ├── PICALU.VHD
    │   ├── PICCPU.VHD
    │   ├── PICREGS.VHD
    │   ├── PICROM.VHD
    │   ├── PICTEST.CMD
    │   ├── PICTEST.VHD
    │   ├── README.TXT
    │   ├── SYNTHPIC.TXT
    │   ├── TEST1.ASM
    │   ├── TEST2.ASM
    │   ├── TEST3.ASM
    │   ├── TEST4.ASM
    │   ├── TEST5.ASM
    │   └── TEST6.ASM
    ├── TEST.V
    ├── adder_8bit.v
    ├── adder_8bit_2.v
    ├── binarytogray.v
    ├── cla_8bits.v
    ├── dds.v
    ├── decoder3x8.v
    ├── div16.v
    ├── encoder8x3.v
    ├── encoder8x3_2.v
    ├── fifo.v
    ├── fifo_16x16.v
    ├── framer.v
    ├── frequency5x2.v
    ├── full_adder_1.v
    ├── full_adder_2.v
    ├── gencrc.v.txt
    ├── half_adder_1.v
    ├── half_adder_2.v
    ├── half_adder_3.v
    ├── lead_8bits_adder.v
    ├── lead_8bits_adder2.v
    ├── mult16.v
    ├── mult_piped_8x8.v
    ├── mult_select.v
    ├── multi_select_1.v
    ├── myrand.c
    ├── nco.v
    ├── onehot.v
    ├── pic.v
    ├── sequence_dectect.v
    ├── string.v
    ├── test_cla_8bits.v
    ├── testing.v.txt
    └── wpulse.v.txt
└── verilog_tutorial
    ├── cnt_tb.v
    ├── count.pdf
    └── first_counter.v


/README.md:
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1 | This is the GitHub for the EE 287 ASIC design class.
2 | Learn the ARM9 Core/ MiniMIPS/ CompArch/ DDCA/ Xilinx/ Synopsys as soon as possible!


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 10/ADDVB_Models_10.doc:
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https://raw.githubusercontent.com/vlsi1217/ASIC/26565ac05915dd3acf139bc8b92408bfdf4bdd70/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 10/ADDVB_Models_10.doc


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 11/JTAG/BR_Cell.v:
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 1 | module  Bypass_Register(scan_out, scan_in, shiftDR, clockDR);
 2 |   output 	scan_out;
 3 |   input 		scan_in, shiftDR, clockDR;
 4 |   reg 		scan_out;
 5 | 
 6 |   always @ (posedge clockDR) scan_out <= scan_in & shiftDR;
 7 | 
 8 | endmodule 
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 11/JTAG/_vti_cnf/BR_Cell.v:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 11/_vti_cnf/Latch_Races.v:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 4/ADDVB_Models_4.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 4/AOI_str.v:
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 1 | module AOI_str (y, x_in1, x_in2, x_in3, x_in4, x_in5);
 2 |   output 	y;
 3 |   input	x_in1, x_in2, x_in3, x_in4, x_in5;
 4 |   
 5 |   wire	y1, y2;		// Internal wires
 6 | 
 7 |   nor 	(y_out, y1, y2);
 8 |   and 	(y1, x_in1, x_in2);
 9 |   and 	(y2, x_in3, x_in4, x_in5);
10 | endmodule
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 4/Mux_2_32_CA.v:
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 1 | module Mux_2_32_CA (mux_out, data_1, data_0, select);
 2 | 	  parameter	word_size = 32;
 3 | 	  output 	[word_size -1: 0] mux_out;
 4 |  	  input 	[word_size -1: 0] data_1, data_0;
 5 | 	  input 			 	select;
 6 | 	   
 7 | 	  assign mux_out = enable ? data_1 : data_0;
 8 | endmodule
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 4/_vti_cnf/AOI_UDP.v:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/ADDVB_Models_5.doc:
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https://raw.githubusercontent.com/vlsi1217/ASIC/26565ac05915dd3acf139bc8b92408bfdf4bdd70/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/ADDVB_Models_5.doc


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/AOI_5_CA0.v:
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 1 | module AOI_5 _CA0 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5);
 2 |   // md ciletti
 3 |   input 	x_in1, x_in2, x_in3, x_in4, x_in5;
 4 |   output	y_out;
 5 | 
 6 |   assign y_out = ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5));
 7 | 	 
 8 | endmodule
 9 | 
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/AOI_5_CA1.v:
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 1 | module AOI_5 _CA1 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
 2 |   // md ciletti
 3 |   input 		x_in1, x_in2, x_in3, x_in4, x_in5, enable;
 4 |   output	y_out;
 5 | 
 6 |   assign y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)) : 1'bz;
 7 | 	 
 8 | endmodule
 9 | 
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/AOI_5_CA2.v:
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 1 | module AOI_5 _CA2 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
 2 |   // md ciletti
 3 |   input 	x_in1, x_in2, x_in3, x_in4, x_in5, enable;
 4 |   output	y_out;
 5 | 
 6 |   wire y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)): 1'bz;
 7 | 	 
 8 | endmodule
 9 | 
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/AOI_5_CA3.v:
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 1 | module AOI_5 _CA2 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
 2 |   // md ciletti
 3 |   input 	x_in1, x_in2, x_in3, x_in4, x_in5;
 4 |   output	y_out;
 5 |   wire #1 y1 = x_in1 & x_in2;
 6 |   wire #1 y2 = x_in3 & x_in4;
 7 |   wire #1 y_out = ~(y1 | y2); 
 8 | endmodule
 9 | 
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/Latch_CA.v:
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1 | module Latch_CA (q_out, data_in, enable);
2 |   output 		q_out;
3 |   input 		data_in, enable;
4 | 
5 |   assign q_out = enable ? data_in : q_out;
6 | endmodule
7 | 
8 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/Latch_Rbar_CA.v:
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1 | module Latch_Rbar_CA (q_out, data_in, enable, reset);
2 |   output 		q_out;
3 |   input 		data_in, enable, reset;
4 | 
5 |   assign q_out = !reset ? 0 : enable ? data_in : q_out;
6 | endmodule
7 | 
8 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/Majority_4b.v:
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 1 | module Majority_4b (Y, A, B, C, D);
 2 |   input 	A, B, C, D;
 3 |   output	Y;
 4 |   reg 	Y;
 5 |   always @ (A or B or C or D) begin
 6 |     case ({A, B,C, D})
 7 |       7, 11, 13, 14, 15:	Y = 1;
 8 |       default		Y = 0;
 9 |     endcase
10 |   end
11 | endmodule
12 | 
13 | 
14 | 
15 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/compare_2_CA1.txt:
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 1 | module compare_2_CA1  (A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0);
 2 |   input 		A1, A0, B1, B0;
 3 |   output 		A_lt_B, A_gt_B, A_eq_B;
 4 | 
 5 |   assign 	A_lt_B = ({A1,A0} < {B1,B0});
 6 |   assign 	A_gt_B = ({A1,A0} > {B1,B0});
 7 |   assign 	A_eq_B = ({A1,A0} == {B1,B0});
 8 | endmodule
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/compare_2_CA1.v:
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 1 | module compare_2_CA1 (A_lt_B, A_gt_B, A_eq_B, A, B);
 2 |   input	[1: 0] 	A, B;
 3 |   output 		A_lt_B, A_gt_B, A_eq_B;
 4 | 
 5 |   assign 	A_lt_B = (A < B);
 6 |   assign 	A_gt_B = (A > B);
 7 |   assign 	A_eq_B = (A == B);
 8 | endmodule
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/compare_32_CA.v:
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 1 | module compare_32_CA (A_gt_B, A_lt_B, A_eq_B, A, B);
 2 |   parameter 	word_size = 32;
 3 |   input 		[word_size-1: 0] 	A, B;
 4 |   output 		A_gt_B, A_lt_B, A_eq_B;
 5 | 
 6 |   assign 	A_gt_B = (A > B),		// Note: list of multiple assignments
 7 | 	  		A_lt_B = (A < B),
 8 | 	  		A_eq_B = (A == B);
 9 | endmodule
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/t_AOI_5_CA1.v:
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 1 | module AOI_5_CA1 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
 2 |   input 		x_in1, x_in2, x_in3, x_in4, x_in5, enable;
 3 |   output	y_out;
 4 | 
 5 |   assign y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)) : 1'bz;
 6 | 	 
 7 | endmodule
 8 | 
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/t_AOI_5_CA2.v:
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1 | module AOI_5_CA2 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
2 |   input 		x_in1, x_in2, x_in3, x_in4, x_in5, enable;
3 |   output	y_out;
4 | 
5 |   wire y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)) : 1'bz;
6 | 	 
7 | endmodule
8 | 
9 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 5/tr_latch.v:
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 1 | module tr_latch (q_out, enable, data);
 2 |   output q_out;
 3 |   input enable, data;
 4 |   reg q_out;
 5 | 
 6 |   always @  (enable or data)
 7 |     begin 
 8 |       if (enable) q_out = data;	 
 9 |     end
10 | endmodule
11 | 
12 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 6/badd_4.v:
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 1 | module badd_4 (Sum, C_out, A, B, C_in);
 2 |   output 	[3: 0] 	Sum;
 3 |   output 		C_out;
 4 |   input 	[3: 0] 	A, B;
 5 |   input 		C_in;
 6 | 
 7 |   assign {C_out, Sum} = A + B + C_in;
 8 | endmodule
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 6/latch_if2.v:
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 1 | module latch_if2 (data_out, data_in, latch_enable);
 2 |   output	[3: 0] 	data_out; 
 3 |   input 	[3: 0] 	data_in;
 4 |   input 		latch_enable;
 5 |   reg 	[3: 0] 	data_out;
 6 |  
 7 |   always @  (latch_enable or data_in)
 8 |     if (latch_enable) data_out = data_in;	// Incompletely specified	
 9 | endmodule
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 6/mux_logic.v:
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1 | module mux_logic (y, select, sig_G, sig_max, sig_a, sig_b);
2 |   output 		y;
3 |   input   		select, sig_G, sig_max, sig_a, sig_b;
4 | 
5 |   assign y = (select == 1) || (sig_G ==1) || (sig_max == 0) ? sig_a : sig_b; 
6 | 		 
7 | endmodule
8 | 
9 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 6/operator_group.v:
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 1 | module operator_group (sum1, sum2, a, b, c, d);
 2 |   output 	[4: 0]	sum1, sum2;
 3 |   input 	[3: 0] 	a, b, c, d;
 4 |   
 5 | 
 6 |   assign sum1 = a + b + c + d;
 7 |   assign sum2 = (a + b) + (c + d);
 8 | 
 9 | endmodule
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 6/or_nand.v:
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1 | module or_nand (y, enable, x1, x2, x3, x4);
2 |   output y;
3 |   input 	enable, x1, x2, x3, x4;
4 | 
5 |   assign y = ~(enable & (x1 | x2) & (x3 | x4));
6 | endmodule
7 | 
8 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 6/res_share.v:
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1 | module res_share (y_out, sel, data_a, data_b, accum);
2 |   output 		[4: 0]	y_out;
3 |   input		[3: 0]	data_a, data_b, accum;
4 |   input			sel;
5 | 
6 |   assign y_out = data_a + (sel ? accum : data_b);
7 | endmodule
8 | 
9 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 7/ADDVB_Models_7.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 7/Clock_Unit.v:
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 1 | module Clock_Unit (clock);
 2 | output clock;
 3 |  reg clock;
 4 | parameter delay = 0;
 5 | parameter half_cycle = 10;
 6 | initial begin
 7 | #delay clock = 0;
 8 | forever #half_cycle clock = ~clock;
 9 | end
10 | endmodule
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Chapter 7/Gap_Finder.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Clock generator/Clock_Unit.v:
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 1 | module Clock_Unit (clock);
 2 | output clock;
 3 |  reg clock;
 4 | parameter delay = 0;
 5 | parameter half_cycle = 10;
 6 | initial begin
 7 | #delay clock = 0;
 8 | forever #half_cycle clock = ~clock;
 9 | end
10 | endmodule
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Clock generator/clock.v:
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 1 | module clock_gen (clock);
 2 |   parameter Half_cycle = 50;
 3 |   output clock;
 4 |   reg clock;
 5 | 
 6 |   initial
 7 |     clock = 0;
 8 | 
 9 |   always
10 |     begin
11 |       # Half_cycle clock = ~ clock;
12 |     end
13 | endmodule
14 | 
15 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Clock generator/clock_gen.v:
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 1 | module Clock_Gen (clock);
 2 | output clock;
 3 |  reg clock;
 4 | parameter delay = 0;
 5 | parameter half_cycle = 5;
 6 | initial begin
 7 | #delay clock = 0;
 8 | forever #half_cycle clock = ~clock;
 9 | end
10 | endmodule
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/FAQs.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 11/ADDVB_Models_11.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 11/JTAG/BR_Cell.v:
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 1 | module  Bypass_Register(scan_out, scan_in, shiftDR, clockDR);
 2 |   output 	scan_out;
 3 |   input 		scan_in, shiftDR, clockDR;
 4 |   reg 		scan_out;
 5 | 
 6 |   always @ (posedge clockDR) scan_out <= scan_in & shiftDR;
 7 | 
 8 | endmodule 
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 4/ADDVB_Models_4.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 4/AOI_str.v:
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 1 | module AOI_str (y, x_in1, x_in2, x_in3, x_in4, x_in5);
 2 |   output 	y;
 3 |   input	x_in1, x_in2, x_in3, x_in4, x_in5;
 4 |   
 5 |   wire	y1, y2;		// Internal wires
 6 | 
 7 |   nor 	(y_out, y1, y2);
 8 |   and 	(y1, x_in1, x_in2);
 9 |   and 	(y2, x_in3, x_in4, x_in5);
10 | endmodule
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 4/Mux_2_32_CA.v:
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 1 | module Mux_2_32_CA (mux_out, data_1, data_0, select);
 2 | 	  parameter	word_size = 32;
 3 | 	  output 	[word_size -1: 0] mux_out;
 4 |  	  input 	[word_size -1: 0] data_1, data_0;
 5 | 	  input 			 	select;
 6 | 	   
 7 | 	  assign mux_out = enable ? data_1 : data_0;
 8 | endmodule
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 4/_vti_cnf/AOI_UDP.v:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/AOI_5_CA0.v:
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 1 | module AOI_5 _CA0 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5);
 2 |   // md ciletti
 3 |   input 	x_in1, x_in2, x_in3, x_in4, x_in5;
 4 |   output	y_out;
 5 | 
 6 |   assign y_out = ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5));
 7 | 	 
 8 | endmodule
 9 | 
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/AOI_5_CA2.v:
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 1 | module AOI_5 _CA2 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
 2 |   // md ciletti
 3 |   input 	x_in1, x_in2, x_in3, x_in4, x_in5, enable;
 4 |   output	y_out;
 5 | 
 6 |   wire y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)): 1'bz;
 7 | 	 
 8 | endmodule
 9 | 
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/Latch_CA.v:
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1 | module Latch_CA (q_out, data_in, enable);
2 |   output 		q_out;
3 |   input 		data_in, enable;
4 | 
5 |   assign q_out = enable ? data_in : q_out;
6 | endmodule
7 | 
8 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/Latch_Rbar_CA.v:
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1 | module Latch_Rbar_CA (q_out, data_in, enable, reset);
2 |   output 		q_out;
3 |   input 		data_in, enable, reset;
4 | 
5 |   assign q_out = !reset ? 0 : enable ? data_in : q_out;
6 | endmodule
7 | 
8 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/Majority_4b.v:
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 1 | module Majority_4b (Y, A, B, C, D);
 2 |   input 	A, B, C, D;
 3 |   output	Y;
 4 |   reg 	Y;
 5 |   always @ (A or B or C or D) begin
 6 |     case ({A, B,C, D})
 7 |       7, 11, 13, 14, 15:	Y = 1;
 8 |       default		Y = 0;
 9 |     endcase
10 |   end
11 | endmodule
12 | 
13 | 
14 | 
15 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/compare_2_CA1.v:
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 1 | module compare_2_CA1 (A_lt_B, A_gt_B, A_eq_B, A, B);
 2 |   input	[1: 0] 	A, B;
 3 |   output 		A_lt_B, A_gt_B, A_eq_B;
 4 | 
 5 |   assign 	A_lt_B = (A < B);
 6 |   assign 	A_gt_B = (A > B);
 7 |   assign 	A_eq_B = (A == B);
 8 | endmodule
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/t_AOI_5_CA1.v:
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 1 | module AOI_5_CA1 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
 2 |   input 		x_in1, x_in2, x_in3, x_in4, x_in5, enable;
 3 |   output	y_out;
 4 | 
 5 |   assign y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)) : 1'bz;
 6 | 	 
 7 | endmodule
 8 | 
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/t_AOI_5_CA2.v:
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1 | module AOI_5_CA2 (y_out, x_in1, x_in2, x_in3, x_in4, x_in5, enable);
2 |   input 		x_in1, x_in2, x_in3, x_in4, x_in5, enable;
3 |   output	y_out;
4 | 
5 |   wire y_out = enable ? ~((x_in1 & x_in2) | (x_in3 & x_in4 & x_in5)) : 1'bz;
6 | 	 
7 | endmodule
8 | 
9 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 5/tr_latch.v:
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 1 | module tr_latch (q_out, enable, data);
 2 |   output q_out;
 3 |   input enable, data;
 4 |   reg q_out;
 5 | 
 6 |   always @  (enable or data)
 7 |     begin 
 8 |       if (enable) q_out = data;	 
 9 |     end
10 | endmodule
11 | 
12 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 6/badd_4.v:
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 1 | module badd_4 (Sum, C_out, A, B, C_in);
 2 |   output 	[3: 0] 	Sum;
 3 |   output 		C_out;
 4 |   input 	[3: 0] 	A, B;
 5 |   input 		C_in;
 6 | 
 7 |   assign {C_out, Sum} = A + B + C_in;
 8 | endmodule
 9 | 
10 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 6/mux_logic.v:
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1 | module mux_logic (y, select, sig_G, sig_max, sig_a, sig_b);
2 |   output 		y;
3 |   input   		select, sig_G, sig_max, sig_a, sig_b;
4 | 
5 |   assign y = (select == 1) || (sig_G ==1) || (sig_max == 0) ? sig_a : sig_b; 
6 | 		 
7 | endmodule
8 | 
9 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 6/operator_group.v:
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 1 | module operator_group (sum1, sum2, a, b, c, d);
 2 |   output 	[4: 0]	sum1, sum2;
 3 |   input 	[3: 0] 	a, b, c, d;
 4 |   
 5 | 
 6 |   assign sum1 = a + b + c + d;
 7 |   assign sum2 = (a + b) + (c + d);
 8 | 
 9 | endmodule
10 | 
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 6/or_nand.v:
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1 | module or_nand (y, enable, x1, x2, x3, x4);
2 |   output y;
3 |   input 	enable, x1, x2, x3, x4;
4 | 
5 |   assign y = ~(enable & (x1 | x2) & (x3 | x4));
6 | endmodule
7 | 
8 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 6/res_share.v:
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1 | module res_share (y_out, sel, data_a, data_b, accum);
2 |   output 		[4: 0]	y_out;
3 |   input		[3: 0]	data_a, data_b, accum;
4 |   input			sel;
5 | 
6 |   assign y_out = data_a + (sel ? accum : data_b);
7 | endmodule
8 | 
9 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 7/ADDVB_Models_7.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 7/Clock_Unit.v:
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 1 | module Clock_Unit (clock);
 2 | output clock;
 3 |  reg clock;
 4 | parameter delay = 0;
 5 | parameter half_cycle = 10;
 6 | initial begin
 7 | #delay clock = 0;
 8 | forever #half_cycle clock = ~clock;
 9 | end
10 | endmodule
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Chapter 7/Gap_Finder.doc:
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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Clock generator/Clock_Unit.v:
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 1 | module Clock_Unit (clock);
 2 | output clock;
 3 |  reg clock;
 4 | parameter delay = 0;
 5 | parameter half_cycle = 10;
 6 | initial begin
 7 | #delay clock = 0;
 8 | forever #half_cycle clock = ~clock;
 9 | end
10 | endmodule
11 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Clock generator/clock.v:
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 1 | module clock_gen (clock);
 2 |   parameter Half_cycle = 50;
 3 |   output clock;
 4 |   reg clock;
 5 | 
 6 |   initial
 7 |     clock = 0;
 8 | 
 9 |   always
10 |     begin
11 |       # Half_cycle clock = ~ clock;
12 |     end
13 | endmodule
14 | 
15 | 


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/ciletti/Advanced Digital Design with the Verilog HDL源码/Models and Testbenches 11_10_2004/Clock generator/clock_gen.v:
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 1 | module Clock_Gen (clock);
 2 | output clock;
 3 |  reg clock;
 4 | parameter delay = 0;
 5 | parameter half_cycle = 5;
 6 | initial begin
 7 | #delay clock = 0;
 8 | forever #half_cycle clock = ~clock;
 9 | end
10 | endmodule
11 | 


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/hmc-mips-7-3-15/doc/Test_Plan.doc:
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/hmc-mips-7-3-15/testing/adelaide/test_mux2_zip.cmd:
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 1 | |test_mux2_zip.cmd
 2 | 
 3 | print s=0, expect s_out=0, sb_out=1
 4 | l s
 5 | s 1
 6 | assert s_out  0
 7 | assert sb_out 1
 8 | 
 9 | print s=1, expect s_out=1, sb_out=0
10 | h s
11 | s 1
12 | assert s_out  1
13 | assert sb_out 0
14 | 


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/hmc-mips-7-3-15/testing/test_000.dat:
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 1 | 20020000
 2 | 20030001
 3 | 20050015
 4 | 00432020
 5 | 00601020
 6 | 00801820
 7 | 10850003
 8 | 00000000
 9 | 1000fffa
10 | 00000000
11 | ac440007
12 | 1000ffff
13 | 00000000
14 | 


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/hmc-mips-7-3-15/testing/test_001.dat:
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 1 | 20020005
 2 | 2003000c
 3 | 2067fff7
 4 | 00e22025
 5 | 00642824
 6 | 00a42820
 7 | 10a7000d
 8 | 00000000
 9 | 0064202a
10 | 10800002
11 | 00000000
12 | 20050000
13 | 00e2202a
14 | 00853820
15 | 00e23822
16 | ac6701f4
17 | 8c020200
18 | 10000002
19 | 00000000
20 | 20020001
21 | ac020204
22 | 1000ffff
23 | 00000000
24 | 


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/hmc-mips-7-3-15/testing/test_002.dat:
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 1 | 2402fff6
 2 | 2403000a
 3 | 00431021
 4 | 24440064
 5 | 2445ff9c
 6 | 2843ffff
 7 | 00431021
 8 | 2c437fff
 9 | 3c0470f0
10 | 3484f000
11 | 3884fff0
12 | 2c82ffff
13 | 00431021
14 | ac820000
15 | 1000ffff
16 | 00000000
17 | 


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/hmc-mips-7-3-15/testing/test_003.dat:
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 1 | 2402fff6
 2 | 2403000a
 3 | 00632823
 4 | 14a00013
 5 | 00431021
 6 | 24040064
 7 | 24440064
 8 | 2445ff9c
 9 | 0045182a
10 | 00431024
11 | 34057fff
12 | 30a57fff
13 | 0045182b
14 | 3c0470f0
15 | 3405f000
16 | 00852025
17 | 3405fff0
18 | 3884fff0
19 | 2005ffff
20 | 0085102b
21 | 00431021
22 | 00822027
23 | ac820003
24 | 1000ffff
25 | 00000000
26 | 


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/hmc-mips-7-3-15/testing/test_004.dat:
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 1 | 2402007f
 2 | 00021942
 3 | 00621004
 4 | 00022580
 5 | 00042583
 6 | 3c058000
 7 | 00852026
 8 | 34050005
 9 | 00a42007
10 | 00642004
11 | 00031842
12 | 00642006
13 | ac820000
14 | 1000ffff
15 | 00000000
16 | 


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/hmc-mips-7-3-15/testing/test_006.dat:
--------------------------------------------------------------------------------
 1 | 2003ffff
 2 | 40836000
 3 | 00000000
 4 | 00000000
 5 | 00000000
 6 | 40046000
 7 | ac80ffff
 8 | 1000ffff
 9 | 00000000
10 | 


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/hmc-mips-7-3-15/testing/test_007.dat:
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 1 | 2003ffff
 2 | 20040010
 3 | ac830000
 4 | a0800001
 5 | 20065555
 6 | 00063200
 7 | a4860002
 8 | 8c850000
 9 | 00000000
10 | ac850004
11 | 1000ffff
12 | 


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/hmc-mips-7-3-15/testing/test_023.dat:
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 1 | 24080200
 2 | 3c09bfc0
 3 | 35290200
 4 | 3c0adead
 5 | 340bbee0
 6 | ad0a0000
 7 | a1200000
 8 | ad2b0000
 9 | 8d0a0000
10 | 8d2b0000
11 | 014b5025
12 | a1000000
13 | 240b000f
14 | ad2b0000
15 | 8d0c0000
16 | 014c5025
17 | ac0a0000
18 | 1000ffff
19 | 00000000
20 | 00000000
21 | 


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/hmc-mips-7-3-15/testing/test_025.dat:
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 1 | 24080200
 2 | 3c0adead
 3 | 24090400
 4 | 340bbeef
 5 | ad0a0000
 6 | ad2b0000
 7 | 00000000
 8 | 00000000
 9 | 00000000
10 | 8d2a0000
11 | 8d0b0000
12 | 014b5025
13 | ac0a0000
14 | 1000ffff
15 | 00000000
16 | 00000000
17 | 


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/learnVerilog_2013/Cilietti/Clock_Unit.v:
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 1 | module Clock_Unit (clock);
 2 | output clock;
 3 |  reg clock;
 4 | parameter delay = 0;
 5 | parameter half_cycle = 10;
 6 | initial begin
 7 | #delay clock = 0;
 8 | forever #half_cycle clock = ~clock;
 9 | end
10 | endmodule
11 | 


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/learnVerilog_2013/Cilietti/RISC_SPM_20130220155415.jpg:
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/learnVerilog_2013/Verilog HDL/success_Feb212013.png:
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/verilog 100 examples/COMPARE.V:
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1 | module compare(a,b,equal);
2 | 
3 | parameter size=1;
4 | input [size-1:0]a,b;
5 | output equal;
6 | 
7 | assign  equal=(a==b)?1:0;
8 | endmodule
9 | 


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/verilog 100 examples/DECODER1.V:
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1 | module decoder(out,in);
2 | output    [7:0] out;
3 | input     [2:0]  in;
4 | assign  out=1'b1<<in;
5 | endmodule


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/verilog 100 examples/PLI/Makefile:
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 1 | it: vcspliread
 2 | 
 3 | vcsmypli: mypli.c mypli.v
 4 | 	vcs -R mypli.v -P mypli.tab mypli.c
 5 | 
 6 | vcspliread: pliread.c pliread.v
 7 | 	vcs -R pliread.v -P pliread.tab pliread.c
 8 | 
 9 | clean:
10 | 	rm -r -f simv.daidir simv
11 | 


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/verilog 100 examples/PLI/README:
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1 | These files show basics of doing some PLI calls.  These two examples
2 | are completely independent.  The PLI is very extensive, but these
3 | examples show that you can do a lot with just a little.  Makefiles
4 | will run either simulation.  This is all VCS.
5 | 
6 | 


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/verilog 100 examples/PLI/mypli.h:
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1 | #ifndef _MYPLI_H_
2 | #define _MYPLI_H_
3 | int	mypli_reset_call	(void);
4 | int	mypli_cycle_call	(void);
5 | int	mypli_getcount_call	(void);
6 | int	mypli_setmodulo_call	(void);
7 | #endif
8 | 


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/verilog 100 examples/PLI/mypli.tab:
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1 | $mypli_reset call=mypli_reset_call acc+=rw:*
2 | $mypli_cycle call=mypli_cycle_call acc+=rw:*
3 | $mypli_getcount call=mypli_getcount_call acc+=rw:*
4 | $mypli_setmodulo call=mypli_setmodulo_call acc+=rw:*
5 | 


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/verilog 100 examples/PLI/pliread.dat:
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1 | 13A5CFF2
2 | 55566df2
3 | 13
4 | 777
5 | 


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/verilog 100 examples/PLI/pliread.h:
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1 | #ifndef _PLIREAD_H_
2 | #define _PLIREAD_H_
3 | int     pliopen_call        (void);
4 | int     pliread_call        (void);
5 | int     pliclose_call     (void);
6 | #endif
7 | 


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/verilog 100 examples/PLI/pliread.tab:
--------------------------------------------------------------------------------
1 | $pliopen  call=pliopen_call  acc+=rw:*
2 | $pliread  call=pliread_call  acc+=rw:*
3 | $pliclose call=pliclose_call acc+=rw:*
4 | 


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/verilog 100 examples/RISC8.ZIP:
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/verilog 100 examples/RISC8/risc8.gif:
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/verilog 100 examples/RISC8/risc8doc.html:
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/verilog 100 examples/RISC8/runit:
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1 | verilog test.v cpu.v alu.v regs.v idec.v exp.v dram.v pram.v
2 | 
3 | 
4 | 


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/verilog 100 examples/SYNTHPIC.ZIP:
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/verilog 100 examples/SYNTHPIC/HEX2VHDL.EXE:
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/verilog 100 examples/adder_8bit.v:
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 1 | module adder_8bit_1(a,b,cin,out,carry);
 2 | input     [7:0]  a,   b;
 3 | input            cin;
 4 | output    [7:0]  out;
 5 | output           carry;
 6 | reg        [7:0]  out;
 7 | reg               carry;    
 8 | always@(a or b or cin)
 9 |  {carry,out}=a+b+cin;
10 | 
11 | endmodule
12 | 


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/verilog 100 examples/encoder8x3.v:
--------------------------------------------------------------------------------
 1 | module encoder8x3(in,out);
 2 | input  [7:0] in;
 3 | output [2:0] out;
 4 | reg    [2:0] out;
 5 | reg    [2:0] i;
 6 | always @(in)
 7 | begin
 8 |   for(i=0;i<8;i=i+1)
 9 |    if(in[i])
10 |      out=i;
11 | end
12 | 
13 | endmodule
14 |      
15 |  
16 | 


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/verilog 100 examples/full_adder_2.v:
--------------------------------------------------------------------------------
 1 | `include "half_adder_1.v"
 2 | module full_adder(a,b,cin,out,carry);
 3 | input a,b,cin;
 4 | output carry,out;
 5 | 
 6 | half_adder m1 (a,b,out1,carry1);
 7 | half_adder m2 (cin,out1,out,carry2);
 8 | or         m3 (carry,carry1,carry2);
 9 | 
10 | endmodule
11 | 


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/verilog 100 examples/half_adder_1.v:
--------------------------------------------------------------------------------
1 | module half_adder(a,b,out,carry);
2 | input a,b;
3 | output out,carry;
4 | assign {carry,out}=a+b;
5 | endmodule


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/verilog 100 examples/half_adder_2.v:
--------------------------------------------------------------------------------
1 | module half_adder(a,b,out,carry);
2 | input a,b;
3 | output out,carry;
4 | assign out=a^b;
5 | assign carry=a&b;
6 | endmodule
7 | 


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/verilog 100 examples/half_adder_3.v:
--------------------------------------------------------------------------------
1 | module half_adder(a,b,out,carry);
2 | input a,b;
3 | output out,carry;
4 | xor n1(out,a,b);
5 | and n2(carry,a,b);
6 | endmodule


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/verilog 100 examples/multi_select_1.v:
--------------------------------------------------------------------------------
 1 | module mult_select(a,b,select,out);
 2 | parameter size=8;
 3 | input    [size-1:0]a,b;
 4 | input              select;
 5 | output   [size-1:0]out;
 6 | reg      [size-1:0]out;
 7 | always@(a or b or select)
 8 |   begin
 9 |        if(select)
10 |              out=a;
11 |         else 
12 |              out=b;
13 |    end
14 |    
15 | endmodule


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