├── Digital Event Detector ├── Event Detector - Verilog HDL Design, Simulation & Synthesis.pdf ├── HDL │ ├── README │ ├── event_detector_async.v │ ├── event_detector_async_TB.v │ ├── event_detector_sync.v │ └── event_detector_sync_TB.v └── README ├── Event Detector - Verilog HDL Design, Simulation & Synthesis.pdf ├── Fixed Priority Arbiter - Verilog HDL Design, Simulation & Synthesis.pdf ├── Fixed Priority Arbiter ├── Fixed Priority Arbiter - Verilog Design, Simulation & Synthesis.pdf ├── HDL │ ├── Fixed_Priority_Arbiter.v │ ├── Fixed_Priority_Arbiter_TB.v │ └── README └── README ├── README.md ├── Round Robin Arbiter (Fixed Time Slices) - Verilog HDL Design, Simulation & Synthesis.pdf ├── Round Robin Arbiter (Variable Time Slices) - Verilog HDL Design, Simulation & Synthesis.pdf └── UART Tx & Rx Controller Design ├── HDL ├── README ├── UART_TB.v ├── baudRateGenerator.v ├── defines.v ├── uart_controller.v ├── uart_rx_controller.v └── uart_tx_controller.v ├── README └── UART Tx & Rx Controller Design & Simulation.pdf /Digital Event Detector/Event Detector - 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