├── CPU 16- Bit using Verilog ├── ALU.v ├── ALU.v.bak ├── ArithUnit.v ├── ArithUnit.v.bak ├── Basics.v ├── Basics.v.bak ├── CPU.v ├── CPU.v.bak ├── Controller.v ├── Controller.v.bak ├── Counter.v ├── Counter.v.bak ├── DataMemory.v ├── DataMemory.v.bak ├── Encoder16-4.v ├── Encoder16-4.v.bak ├── InstMemory.v ├── InstMemory.v.bak ├── InstReg.v ├── InstReg.v.bak ├── LogicUnit.v ├── LogicUnit.v.bak ├── Mux.v ├── Mux.v.bak ├── MuxB.v ├── MuxB.v.bak ├── PC.v ├── PC.v.bak ├── RegA.v ├── RegA.v.bak ├── RegB.v ├── RegB.v.bak ├── RegC.v ├── RegC.v.bak ├── Untitled.png ├── Verilog.cr.mti ├── Verilog.mpf ├── vsim.wlf └── work │ ├── _info │ ├── _lib.qdb │ ├── _lib1_14.qdb │ ├── _lib1_14.qpg │ ├── _lib1_14.qtl │ ├── _lib1_16.qdb │ ├── _lib1_16.qpg │ ├── _lib1_16.qtl │ ├── _lib1_19.qdb │ ├── _lib1_19.qpg │ ├── _lib1_19.qtl │ ├── _lib1_6.qdb │ ├── _lib1_6.qpg │ ├── _lib1_6.qtl │ └── _vmake └── README.md /CPU 16- Bit using Verilog/ALU.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | // This describes the ALU of the design //// 3 | //////////////////////////////////////////////////////////////////// 4 | 5 | module ALU( a, b, opcode, mode, outALU, za, zb, eq, gt, lt); 6 | input [15:0] a; 7 | input [15:0] b; 8 | input [2:0] opcode; 9 | input mode; 10 | output [31:0] outALU; 11 | output za, zb, eq, gt, lt; 12 | 13 | reg [31:0] outALU; 14 | reg za, zb, eq, gt, lt; 15 | 16 | wire [31:0] outau; 17 | wire [31:0] outlu; 18 | wire tza, tzb, teq, tgt, tlt; 19 | 20 | // Instantiation of the modules 21 | 22 | arith a1 (.a(a), .b(b), .opcode(opcode), .outau(outau)); 23 | logic l1 (.a(a), .b(b), .opcode(opcode), .outlu(outlu), .za(tza), .zb(tzb), .eq(teq), .gt(tgt), .lt(tlt)); 24 | 25 | // At every change of a, b, mode and opcode, we need to select the output. 26 | 27 | always@(a,b,mode,opcode) 28 | begin 29 | if(mode == 0) begin 30 | outALU = outau; 31 | end 32 | else if (mode == 1) begin 33 | outALU = outlu; 34 | end 35 | else begin 36 | outALU = 32'h00000000; 37 | end 38 | 39 | za = tza; 40 | zb = tzb; 41 | eq = teq; 42 | gt = tgt; 43 | lt = tlt; 44 | end 45 | 46 | endmodule 47 | //////////////////////////////////////////////////////////////////////// 48 | // Testbench for the ALU design /////// 49 | /////////////////////////////////////////////////////////////////////// 50 | 51 | module tb_ALU(); 52 | reg [15:0] a; 53 | reg [15:0] b; 54 | reg [2:0] opcode; 55 | reg mode; 56 | wire [31:0] outALU; 57 | wire za, zb, eq, gt, lt; 58 | 59 | 60 | // Instantiation of ALU 61 | 62 | ALU d1 (.a(a), .b(b), .opcode(opcode), .mode(mode), .outALU(outALU), .za(za), .zb(zb), .eq(eq), .gt(gt), .lt(lt)); 63 | 64 | // Initialization 65 | initial 66 | begin 67 | a <= 16'h0000; 68 | b <= 16'h0000; 69 | opcode <= 000; 70 | mode <= 0; 71 | end 72 | 73 | initial 74 | begin 75 | 76 | #10 mode = 0; // Mode 0 test the Arithmetic Unit 77 | #5 a = 16'h0001; 78 | #5 b = 16'h0010; 79 | 80 | # 5 opcode = 3'b001; 81 | # 5 opcode = 3'b010; 82 | # 5 opcode = 3'b011; 83 | # 5 opcode = 3'b100; 84 | # 5 opcode = 3'b101; 85 | # 5 opcode = 3'b110; 86 | # 5 opcode = 3'b111; 87 | 88 | #5 a = 16'h0100; 89 | #5 b = 16'h0110; 90 | # 5 opcode = 3'b001; 91 | # 5 opcode = 3'b010; 92 | # 5 opcode = 3'b011; 93 | # 5 opcode = 3'b100; 94 | # 5 opcode = 3'b101; 95 | # 5 opcode = 3'b110; 96 | # 5 opcode = 3'b111; 97 | 98 | #10 mode = 1; // Mode 1 test for logic unit 99 | a = 16'h0003; 100 | b = 16'h000F; 101 | 102 | // Various opcodes to see the output 103 | # 5 opcode = 3'b001; 104 | # 5 opcode = 3'b010; 105 | # 5 opcode = 3'b011; 106 | # 5 opcode = 3'b100; 107 | # 5 opcode = 3'b101; 108 | # 5 opcode = 3'b110; 109 | # 5 opcode = 3'b111; 110 | 111 | // When A=B test all the conditions 112 | #10 a = 16'h00E9; 113 | b = 16'h00E9; 114 | # 5 opcode = 3'b001; 115 | # 5 opcode = 3'b010; 116 | # 5 opcode = 3'b011; 117 | # 5 opcode = 3'b100; 118 | # 5 opcode = 3'b101; 119 | # 5 opcode = 3'b110; 120 | # 5 opcode = 3'b111; 121 | 122 | // Test ZA 123 | #10 a <= 16'h0000; 124 | 125 | // Test ZB 126 | #10 b <= 16'h0000; 127 | end 128 | endmodule 129 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/ALU.v.bak: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | // This describes the ALU of the design //// 3 | //////////////////////////////////////////////////////////////////// 4 | 5 | module ALU( a, b, opcode, mode, outALU, za, zb, eq, gt, lt); 6 | input [15:0] a; 7 | input [15:0] b; 8 | input [2:0] opcode; 9 | input mode; 10 | output [31:0] outALU; 11 | output za, zb, eq, gt, lt; 12 | 13 | reg [31:0] outALU; 14 | reg za, zb, eq, gt, lt; 15 | 16 | wire [31:0] outau; 17 | wire [31:0] outlu; 18 | wire tza, tzb, teq, tgt, tlt; 19 | 20 | // Instantiation of the modules 21 | 22 | arith a1 (.a(a), .b(b), .opcode(opcode), .outau(outau)); 23 | logic l1 (.a(a), .b(b), .opcode(opcode), .outlu(outlu), .za(tza), .zb(tzb), .eq(teq), .gt(tgt), .lt(tlt)); 24 | 25 | // At every change of a, b, mode and opcode, we need to select the output. 26 | 27 | always@(a,b,mode,opcode) 28 | begin 29 | if(mode == 0) begin 30 | outALU = outau; 31 | end 32 | else if (mode == 1) begin 33 | outALU = outlu; 34 | za = tza; 35 | zb = tzb; 36 | eq = teq; 37 | gt = tgt; 38 | lt = tlt; 39 | end 40 | else begin 41 | outALU = 32'h00000000; 42 | za = 0; 43 | zb = 0; 44 | eq = 0; 45 | gt = 0; 46 | lt = 0; 47 | end 48 | end 49 | 50 | endmodule 51 | //////////////////////////////////////////////////////////////////////// 52 | // Testbench for the ALU design /////// 53 | /////////////////////////////////////////////////////////////////////// 54 | 55 | module tb_ALU(); 56 | reg [15:0] a; 57 | reg [15:0] b; 58 | reg [2:0] opcode; 59 | reg mode; 60 | wire [31:0] outALU; 61 | wire za, zb, eq, gt, lt; 62 | 63 | 64 | // Instantiation of ALU 65 | 66 | ALU d1 (.a(a), .b(b), .opcode(opcode), .mode(mode), .outALU(outALU), .za(za), .zb(zb), .eq(eq), .gt(gt), .lt(lt)); 67 | 68 | // Initialization 69 | initial 70 | begin 71 | a <= 16'h0000; 72 | b <= 16'h0000; 73 | opcode <= 000; 74 | mode <= 0; 75 | end 76 | 77 | initial 78 | begin 79 | 80 | #10 mode = 0; // Mode 0 test the Arithmetic Unit 81 | #5 a = 16'h0001; 82 | #5 b = 16'h0010; 83 | 84 | # 5 opcode = 3'b001; 85 | # 5 opcode = 3'b010; 86 | # 5 opcode = 3'b011; 87 | # 5 opcode = 3'b100; 88 | # 5 opcode = 3'b101; 89 | # 5 opcode = 3'b110; 90 | # 5 opcode = 3'b111; 91 | 92 | #5 a = 16'h0100; 93 | #5 b = 16'h0110; 94 | # 5 opcode = 3'b001; 95 | # 5 opcode = 3'b010; 96 | # 5 opcode = 3'b011; 97 | # 5 opcode = 3'b100; 98 | # 5 opcode = 3'b101; 99 | # 5 opcode = 3'b110; 100 | # 5 opcode = 3'b111; 101 | 102 | #10 mode = 1; // Mode 1 test for logic unit 103 | a = 16'h0003; 104 | b = 16'h000F; 105 | 106 | // Various opcodes to see the output 107 | # 5 opcode = 3'b001; 108 | # 5 opcode = 3'b010; 109 | # 5 opcode = 3'b011; 110 | # 5 opcode = 3'b100; 111 | # 5 opcode = 3'b101; 112 | # 5 opcode = 3'b110; 113 | # 5 opcode = 3'b111; 114 | 115 | // When A=B test all the conditions 116 | #10 a = 16'h00E9; 117 | b = 16'h00E9; 118 | # 5 opcode = 3'b001; 119 | # 5 opcode = 3'b010; 120 | # 5 opcode = 3'b011; 121 | # 5 opcode = 3'b100; 122 | # 5 opcode = 3'b101; 123 | # 5 opcode = 3'b110; 124 | # 5 opcode = 3'b111; 125 | 126 | // Test ZA 127 | #10 a <= 16'h0000; 128 | 129 | // Test ZB 130 | #10 b <= 16'h0000; 131 | end 132 | endmodule 133 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/ArithUnit.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | //// This module describes a Arithmatic unit of ALU. ///// 3 | /// This will have two inputs of 16 bits each. ///// 4 | /// It has to provide either Arithmatic operation //// 5 | //////////////////////////////////////////////////////////////////////////// 6 | module arith(a,b,opcode,outau); 7 | input [15:0] a; 8 | input [15:0] b; 9 | input [2:0] opcode; 10 | output [31:0] outau; 11 | reg [31:0] outau; 12 | 13 | always@(a,b,opcode) 14 | begin 15 | case(opcode) 16 | 3'b000: outau = {16'h0000, a+b}; 17 | 3'b001: outau = a * b; 18 | 3'b010: if (a > b) begin 19 | outau = a - b; 20 | end 21 | else begin 22 | outau = b - a; 23 | end 24 | 3'b011: if (a > b) begin 25 | outau = a / b; 26 | end 27 | else begin 28 | outau = b /a; 29 | end 30 | default outau = 32'h00000000; 31 | endcase 32 | end 33 | endmodule 34 | 35 | //////////////////////////////////////////////////////////////// 36 | /////// Test bench for the Arithmetic unit /////// 37 | ////////////////////////////////////////////////////////////// 38 | module tb_arith(); 39 | reg [15:0] a; 40 | reg [15:0] b; 41 | reg [2:0] opcode; 42 | wire [31:0] outau; 43 | 44 | // Instantiation of the design 45 | 46 | arith a1 (.a(a), .b(b), .opcode(opcode), .outau(outau)); 47 | 48 | // Initialization 49 | initial 50 | begin 51 | a = 16'h0000; 52 | b = 16'h0000; 53 | opcode = 3'b000; 54 | end 55 | 56 | // Stimulus 57 | initial 58 | begin 59 | #5 a = 16'h0001; 60 | #5 b = 16'h0010; 61 | 62 | # 5 opcode = 3'b001; 63 | # 5 opcode = 3'b010; 64 | # 5 opcode = 3'b011; 65 | # 5 opcode = 3'b100; 66 | # 5 opcode = 3'b101; 67 | # 5 opcode = 3'b110; 68 | # 5 opcode = 3'b111; 69 | 70 | #5 a = 16'h0100; 71 | #5 b = 16'h0110; 72 | # 5 opcode = 3'b001; 73 | # 5 opcode = 3'b010; 74 | # 5 opcode = 3'b011; 75 | # 5 opcode = 3'b100; 76 | # 5 opcode = 3'b101; 77 | # 5 opcode = 3'b110; 78 | # 5 opcode = 3'b111; 79 | end 80 | endmodule 81 | 82 | 83 | 84 | 85 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/ArithUnit.v.bak: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | //// This module describes a Arithmatic unit of ALU. ///// 3 | /// This will have two inputs of 16 bits each. ///// 4 | /// It has to provide either Arithmatic operation //// 5 | //////////////////////////////////////////////////////////////////////////// 6 | module arith(a,b,opcode,outau); 7 | input [15:0] a; 8 | input [15:0] b; 9 | input [2:0] opcode; 10 | output [31:0] outau; 11 | reg [31:0] outau; 12 | 13 | always@(a,b,opcode) 14 | begin 15 | case(opcode) 16 | 3'b000: outau = {16'h0000, a+b}; 17 | 3'b001: outau = a * b; 18 | 3'b010: if (a > b) begin 19 | outau = a - b; 20 | end 21 | else begin 22 | outau = b - a; 23 | end 24 | 3'b011: if (a > b) begin 25 | outau = a / b; 26 | end 27 | else begin 28 | outau = b /a; 29 | end 30 | default outau = 32'h00000000; 31 | endcase 32 | end 33 | endmodule 34 | 35 | //////////////////////////////////////////////////////////////// 36 | /////// Test bench for the Arithmetic unit /////// 37 | ////////////////////////////////////////////////////////////// 38 | module tb_arith(); 39 | reg [15:0] a; 40 | reg [15:0] b; 41 | reg [2:0] opcode; 42 | wire [31:0] outau; 43 | 44 | // Instantiation of the design 45 | 46 | arith a1 (.a(a), .b(b), .opcode(opcode), .outau(outau)); 47 | 48 | // Initialization 49 | initial 50 | begin 51 | a = 16'h0000; 52 | b = 16'h0000; 53 | opcode = 3'b000; 54 | end 55 | 56 | // Stimulus 57 | initial 58 | begin 59 | #5 a = 16'h0001; 60 | #5 b = 16'h0010; 61 | 62 | #15 opcode = 3'b001; 63 | #15 opcode = 3'b000; 64 | #15 opcode = 3'b010; 65 | 66 | #5 a = 16'h0100; 67 | #5 b = 16'h0110; 68 | #15 opcode = 3'b001; 69 | #15 opcode = 3'b000; 70 | #15 opcode = 3'b010; 71 | end 72 | endmodule 73 | 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Basics.v: -------------------------------------------------------------------------------- 1 | // Sample code for D flip flop in Verilog 2 | // Verilog starts with the module name followed by the parameter list 3 | module dff( d,clk,q,q_b); 4 | input d,clk; // Define the input 5 | output q,q_b; // Define the output 6 | wire d,clk; // To use as input, the signals must be declared as wire 7 | reg q,q_b; // To use as output, the signals must be declared as resgister 8 | 9 | // Wire is used for signals that just connect two points 10 | // Registers are sued to define signals that need to store and output the signals 11 | 12 | always@(posedge clk) // During the positive edge of clock 13 | begin 14 | q<=d; // Assigns q to D 15 | q_b<= !d; // Assigns q_b to not of D 16 | end 17 | endmodule 18 | 19 | // We can write the testbench in the same file or different file 20 | 21 | module tb_dff(); // Test bench does not take in any parameters 22 | reg dtb,clktb; // The input signals are now declared as registers as they store and display value 23 | wire qtb,q_btb; // Output signals just display the values, hence use then as wires 24 | 25 | // Instantiantiation of the DFF module to the testbench using the formal parameters 26 | dff d1 (.d(dtb), .clk(clktb), .q(qtb), .q_b(q_btb)); 27 | 28 | // Initialise the clock and input to 0 before starting to make sure no garbage vlaue 29 | initial 30 | begin 31 | clktb = 0; 32 | dtb=0; 33 | end 34 | 35 | // Make sure the clock changes logic value every 10ns 36 | always #10 clktb = ~clktb; 37 | 38 | // Different input to DFF 39 | initial 40 | begin 41 | #20 dtb = 1'b1; 42 | #20 dtb = 1'b0; 43 | end 44 | endmodule 45 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Basics.v.bak: -------------------------------------------------------------------------------- 1 | // Sample code for D flip flop in Verilog 2 | // Verilog starts with the module name followed by the parameter list 3 | module dff( d,clk,q,q_b); 4 | input d,clk; // Define the input 5 | output q,q_b; // Define the output 6 | wire d,clk; // To use as input, the signals must be declared as wire 7 | reg q,q_b; // To use as output, the signals must be declared as resgister 8 | 9 | // Wire is used for signals that just connect two points 10 | // Registers are sued to define signals that need to store and output the signals 11 | 12 | always@(posedge clk) // During the positive edge of clock 13 | begin 14 | q<=d; // Assigns q to D 15 | q_b<= !d; // Assigns q_b to not of D 16 | end 17 | endmodule 18 | 19 | // We can write the testbench in the same file or different file 20 | 21 | module tb_dff(); // Test bench does not take in any parameters 22 | reg dtb,clktb; // The input signals are now declared as registers as they store and display value 23 | wire qtb,q_btb; // Output signals just display the values, hence use then as wires 24 | 25 | // Instantiantiation of the DFF module to the testbench using the formal parameters 26 | dff d1 (.d(d), .clk(clktb), .q(qtb), .q_b(q_btb)); 27 | 28 | // Initialise the clock and input to 0 before starting to make sure no garbage vlaue 29 | initial 30 | begin 31 | clktb = 0; 32 | dtb=0; 33 | end 34 | 35 | // Make sure the clock changes logic value every 10ns 36 | always #10 clktb = ~clktb; 37 | 38 | // Different input to DFF 39 | initial 40 | begin 41 | #20 dtb = 1'b1; 42 | #20 dtb = 1'b0; 43 | end 44 | endmodule 45 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/CPU.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////// 2 | ///// Design of the 16-Bit CPU is shown below ////// 3 | ///////////////////////////////////////////////////////////////////// 4 | module CPU(clk, en, we_IM, codein, immd, za, zb, eq, gt, lt); 5 | input clk; 6 | input en; 7 | input we_IM; 8 | input [15:0] codein; 9 | input [11:0] immd; 10 | output za; 11 | output zb; 12 | output eq; 13 | output gt; 14 | output lt; 15 | 16 | reg za; 17 | reg zb; 18 | reg eq; 19 | reg gt; 20 | reg lt; 21 | 22 | wire [11:0] curradd; wire [15:0] outIMd; wire [11:0] addressd; wire [3:0] opcodeD; 23 | wire loadIRd, loadAd, loadBd, loadCd, moded, we_DMd, selAd, selBd, loadPCd, incPCd; 24 | wire [11:0] execaddd; wire [15:0] dataAoutd; wire [15:0] dataBoutd; wire [31:0] outALUd; 25 | wire [31:0] currdat; wire [31:0] outDMd; wire [31:0] dataCoutd; 26 | wire zad, zbd, eqd, gtd, ltd; 27 | 28 | 29 | instmem a1 (.clk(clk), .we_IM(we_IM), .dataIM(codein), .addIM(curradd), .outIM(outIMd)); 30 | insReg a2 (.clk(clk), .loadIR(loadIRd), .insin(outIMd), .address(addressd), .opcode(opcodeD)); 31 | controller a3 (.clk(clk), .en(en), .opcode(opcodeD), .loadA(loadAd), .loadB(loadBd), .loadC(loadCd), .loadIR(loadIRd), .loadPC(loadPCd), .incPC(incPCd), .mode(moded), .we_DM(we_DMd), .selA(selAd), .selB(selBd)); 32 | PC a4 (.clk(clk), .loadPC(loadPCd), .incPC(incPCd), .address(addressd), .execadd(execaddd)); 33 | muxB a5 (.clk(clk), .in1(execaddd), .in2(immd), .sel(selBd), .outB(curradd)); 34 | regA a6 (.clk(clk), .loadA(loadAd), .dataAin(outDMd[15:0]), .dataAout(dataAoutd)); 35 | regB a7 (.clk(clk), .loadB(loadBd), .dataBin(outDMd[31:16]), .dataBout(dataBoutd)); 36 | regC a8 (.clk(clk), .loadC(loadCd), .dataCin(currdat), .dataCout(dataCoutd)); 37 | datamem a9 (.clk(clk), .we_DM(we_DMd), .dataDM(dataCoutd), .addDM(addressd), .outDM(outDMd)); 38 | muxA b1 (.clk(clk), .in1(outALUd), .in2({4'b0000,immd}), .sel(selAd), .outA(currdat)); 39 | ALU b2 (.a(dataAoutd), .b(dataBoutd), .opcode(opcodeD[2:0]), .mode(moded), .outALU(outALUd), .za(zad), .zb(zbd), .eq(eqd), .gt(gtd), .lt(ltd)); 40 | 41 | endmodule 42 | 43 | 44 | //////////////////////////////////////////////////////////////////////////////////////// 45 | /////////// Testbench for the CPU to realise few instructions /////// 46 | ////////////////////////////////////////////////////////////////////////////////////// 47 | module tb_CPU(); 48 | reg clk; 49 | reg en; 50 | reg we_IM; 51 | reg [15:0] codein; 52 | reg [11:0] immd; 53 | wire Za; 54 | wire Zb; 55 | wire Eq; 56 | wire Gt; 57 | wire Lt; 58 | 59 | // Instantiation of Module 60 | //clk, en, we_IM, codein, immd, za, zb, eq, gt, lt 61 | CPU C1 (.clk(clk), .en(en), .we_IM(we_IM), .codein(codein), .immd(immd), .za(Za), .zb(Zb), .eq(Eq), .gt(Gt), .lt(Lt)); 62 | 63 | // Initialization of signals 64 | initial 65 | begin 66 | clk = 0; 67 | en = 0; 68 | we_IM = 0; 69 | codein = 16'h0000; 70 | immd = 16'h0000; 71 | end 72 | 73 | // Clock set up 74 | always #10 clk = ~clk; 75 | 76 | // Stimulus 77 | initial 78 | begin 79 | // Idle state to Load state transistion 80 | #10 en = 1; 81 | 82 | #5 we_IM = 1; 83 | codein = 16'h6001; 84 | 85 | #10 we_IM = 0; 86 | 87 | // Provide first instruction set to start the loadA 88 | #20 we_IM = 1; 89 | codein = 16'h4000; 90 | 91 | #10 we_IM = 0; 92 | 93 | // Provide enough Delay to ensure the data has been update 94 | // Wait for some time before doing Load B 95 | #20 we_IM = 1; 96 | codein = 16'h5001; 97 | 98 | // Provide enough Delay to ensure the data has been updated 99 | #10 we_IM = 0; 100 | 101 | // Instruction set for ALU operations 102 | #20 we_IM = 1; 103 | codein = 16'h0010; 104 | 105 | #10 we_IM = 0; 106 | 107 | // Instruction set for ALU operations 108 | #20 we_IM = 1; 109 | codein = 16'h9020; 110 | 111 | #10 we_IM = 0; 112 | 113 | // Instruction set for ALU operations 114 | #20 we_IM = 1; 115 | codein = 16'hE022; 116 | 117 | #10 we_IM = 0; 118 | 119 | // Instruction set for ALU operations 120 | #20 we_IM = 1; 121 | codein = 16'hF0780; 122 | 123 | #10 we_IM = 0; 124 | 125 | // Instruction set for ALU operations 126 | #20 we_IM = 1; 127 | codein = 16'hD067; 128 | 129 | #10 we_IM = 0; 130 | 131 | // Instruction set for ALU operations 132 | #20 we_IM = 1; 133 | codein = 16'h6027; 134 | 135 | #10 we_IM = 0; 136 | 137 | // Instruction set for ALU operations 138 | #20 we_IM = 1; 139 | codein = 16'h7021; 140 | 141 | #10 we_IM = 0; 142 | 143 | // Instruction set for ALU operations 144 | #20 we_IM = 1; 145 | codein = 16'h8022; 146 | 147 | #10 we_IM = 0; 148 | 149 | 150 | // Wait for some time before doing Load C 151 | 152 | 153 | // For JUMP, we need code input followed by a immedeate address 154 | #10 we_IM = 1; 155 | codein = 16'h7111; 156 | #7 we_IM = 0; 157 | immd = 12'hFEB; 158 | 159 | 160 | end 161 | endmodule -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/CPU.v.bak: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////// 2 | ///// Design of the 16-Bit CPU is shown below ////// 3 | ///////////////////////////////////////////////////////////////////// 4 | module CPU(clk, en, we_IM, codein, immd, za, zb, eq, gt, lt); 5 | input clk; 6 | input en; 7 | input we_IM; 8 | input [15:0] codein; 9 | input [11:0] immd; 10 | output za; 11 | output zb; 12 | output eq; 13 | output gt; 14 | output lt; 15 | 16 | reg za; 17 | reg zb; 18 | reg eq; 19 | reg gt; 20 | reg lt; 21 | 22 | wire [11:0] curradd; wire [15:0] outIMd; wire [11:0] addressd; wire [3:0] opcodeD; 23 | wire loadIRd, loadAd, loadBd, loadCd, moded, we_DMd, selAd, selBd, loadPCd, incPCd; 24 | wire [11:0] execaddd; wire [15:0] dataAoutd; wire [15:0] dataBoutd; wire [31:0] outALUd; 25 | wire [31:0] currdat; wire [31:0] outDMd; wire [31:0] dataCoutd; 26 | wire zad, zbd, eqd, gtd, ltd; 27 | 28 | 29 | instmem a1 (.clk(clk), .we_IM(we_IM), .dataIM(codein), .addIM(curradd), .outIM(outIMd)); 30 | insReg a2 (.clk(clk), .loadIR(loadIRd), .insin(outIMd), .address(addressd), .opcode(opcodeD)); 31 | controller a3 (.clk(clk), .en(en), .opcode(opcodeD), .loadA(loadAd), .loadB(loadBd), .loadC(loadCd), .loadIR(loadIRd), .loadPC(loadPCd), .incPC(incPCd), .mode(moded), .we_DM(we_DMd), .selA(selAd), .selB(selBd)); 32 | PC a4 (.clk(clk), .loadPC(loadPCd), .incPC(incPCd), .address(addressd), .execadd(execaddd)); 33 | muxB a5 (.clk(clk), .in1(execaddd), .in2(immd), .sel(selBd), .outB(curradd)); 34 | regA a6 (.clk(clk), .loadA(loadAd), .dataAin(outDMd[15:0]), .dataAout(dataAoutd)); 35 | regB a7 (.clk(clk), .loadB(loadBd), .dataBin(outDMd[31:16]), .dataBout(dataBoutd)); 36 | regC a8 (.clk(clk), .loadC(loadCd), .dataCin(currdat), .dataCout(dataCoutd)); 37 | datamem a9 (.clk(clk), .we_DM(we_DMd), .dataDM(dataCoutd), .addDM(addressd), .outDM(outDMd)); 38 | muxA b1 (.clk(clk), .in1(outALUd), .in2({4'b0000,immd}), .sel(selAd), .outA(currdat)); 39 | ALU b2 (.a(dataAoutd), .b(dataBoutd), .opcode(opcodeD[2:0]), .mode(moded), .outALU(outALUd), .za(zad), .zb(zbd), .eq(eqd), .gt(gtd), .lt(ltd)); 40 | 41 | endmodule 42 | 43 | 44 | //////////////////////////////////////////////////////////////////////////////////////// 45 | /////////// Testbench for the CPU to realise few instructions /////// 46 | ////////////////////////////////////////////////////////////////////////////////////// 47 | module tb_CPU(); 48 | reg clk; 49 | reg en; 50 | reg we_IM; 51 | reg [15:0] codein; 52 | reg [11:0] immd; 53 | wire Za; 54 | wire Zb; 55 | wire Eq; 56 | wire Gt; 57 | wire Lt; 58 | 59 | // Instantiation of Module 60 | //clk, en, we_IM, codein, immd, za, zb, eq, gt, lt 61 | CPU C1 (.clk(clk), .en(en), .we_IM(we_IM), .codein(codein), .immd(immd), .za(Za), .zb(Zb), .eq(Eq), .gt(Gt), .lt(Lt)); 62 | 63 | // Initialization of signals 64 | initial 65 | begin 66 | clk = 0; 67 | en = 0; 68 | we_IM = 0; 69 | codein = 16'h0000; 70 | immd = 16'h0000; 71 | end 72 | 73 | // Clock set up 74 | always #10 clk = ~clk; 75 | 76 | // Stimulus 77 | initial 78 | begin 79 | // Idle state to Load state transistion 80 | #10 en = 1; 81 | 82 | #5 we_IM = 1; 83 | codein = 16'h6001; 84 | 85 | #10 we_IM = 0; 86 | 87 | // Provide first instruction set to start the loadA 88 | #20 we_IM = 1; 89 | codein = 16'h4000; 90 | 91 | #10 we_IM = 0; 92 | 93 | // Provide enough Delay to ensure the data has been update 94 | // Wait for some time before doing Load B 95 | #20 we_IM = 1; 96 | codein = 16'h5001; 97 | 98 | // Provide enough Delay to ensure the data has been updated 99 | #10 we_IM = 0; 100 | 101 | // Instruction set for ALU operations 102 | #20 we_IM = 1; 103 | codein = 16'h0010; 104 | 105 | #10 we_IM = 0; 106 | 107 | // Instruction set for ALU operations 108 | #20 we_IM = 1; 109 | codein = 16'h9020; 110 | 111 | #10 we_IM = 0; 112 | 113 | 114 | // Wait for some time before doing Load C 115 | 116 | 117 | // For JUMP, we need code input followed by a immedeate address 118 | #10 we_IM = 1; 119 | codein = 16'h7111; 120 | #7 we_IM = 0; 121 | immd = 12'hFEB; 122 | 123 | 124 | end 125 | endmodule -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Controller.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | //////// Verilog Program for the controller of the CPU /////// 3 | ////////////////////////////////////////////////////////////////////////////// 4 | module controller ( clk, en, opcode, loadA, loadB, loadC, loadIR, loadPC, incPC, mode, we_DM, selA, selB); 5 | input clk; 6 | input en; 7 | input [3:0] opcode; 8 | output loadA; 9 | output loadB; 10 | output loadC; 11 | output loadIR; 12 | output loadPC; 13 | output incPC; 14 | output mode; 15 | output we_DM; 16 | output selA; 17 | output selB; 18 | 19 | reg loadA; 20 | reg loadB; 21 | reg loadC; 22 | reg loadIR; 23 | reg mode; 24 | reg we_DM; 25 | reg selA; 26 | reg selB; 27 | reg loadPC; 28 | reg incPC; 29 | 30 | // Registers to hold the value of state and next state 31 | 32 | reg [2:0] state; 33 | reg [2:0] next_state; 34 | 35 | parameter reset = 3'b000, load = 3'b010, execute = 3'b100; 36 | 37 | 38 | //Code for operation of the CPU 39 | always@(posedge clk) 40 | begin 41 | 42 | if ( en == 0 ) begin 43 | state = reset; 44 | end 45 | else if (en == 1) begin 46 | state = next_state; 47 | end 48 | end 49 | 50 | 51 | // Now for the Output logic. Output logic depends on OPCODE and Enable signal 52 | always@(*) 53 | begin 54 | if ( en == 0 ) begin 55 | loadA = 0; 56 | loadB = 0; 57 | loadC = 0; 58 | loadIR = 0; 59 | loadPC = 0; 60 | incPC = 0; 61 | mode = 1'bZ; 62 | we_DM = 0; 63 | selA = 1'b0; 64 | selB = 1'b0; 65 | next_state = reset; 66 | end 67 | 68 | else begin 69 | 70 | case(state) 71 | // We just wait for a small duration of time in the same state to see if there is any change in input 72 | reset: begin 73 | loadA = 0; 74 | loadB = 0; 75 | loadC = 0; 76 | loadIR = 0; 77 | loadPC = 0; 78 | incPC = 0; 79 | mode = 1'bZ; 80 | we_DM = 0; 81 | selA = 1'b0; 82 | selB = 1'b0; 83 | next_state = load; 84 | end 85 | 86 | load: begin 87 | loadA = 0; 88 | loadB = 0; 89 | loadC = 0; 90 | loadIR = 1; 91 | loadPC = 1; 92 | incPC = 0; 93 | mode = 1'bZ; 94 | we_DM = 0; 95 | selA = 1'b0; 96 | selB = 1'b0; 97 | next_state = execute; 98 | end 99 | 100 | execute:begin 101 | case(opcode) 102 | // Mode 0, ALU operation for opcode 000 103 | 0000: begin 104 | loadA = 0; 105 | loadB = 0; 106 | loadC = 0; 107 | loadIR = 0; 108 | loadPC = 0; 109 | incPC = 1; 110 | mode = 1'b0; 111 | we_DM = 1; 112 | #5 we_DM = 0; 113 | selA = 1'b0; 114 | selB = 1'b0; 115 | end 116 | // Mode 0, ALU operation for opcode 001 117 | 0001: begin 118 | loadA = 0; 119 | loadB = 0; 120 | loadC = 0; 121 | loadIR = 0; 122 | loadPC = 0; 123 | incPC = 1; 124 | mode = 1'b0; 125 | we_DM = 1; 126 | #5 we_DM = 0; 127 | selA = 1'b0; 128 | selB = 1'b0; 129 | end 130 | // Mode 0, ALU operation for opcode 010 131 | 0010: begin 132 | loadA = 0; 133 | loadB = 0; 134 | loadC = 0; 135 | loadIR = 0; 136 | loadPC = 0; 137 | incPC = 1; 138 | mode = 1'b0; 139 | we_DM = 1; 140 | #5 we_DM = 0; 141 | selA = 1'b0; 142 | selB = 1'b0; 143 | end 144 | // Mode 0, ALU operation for opcode 011 145 | 0011: begin 146 | loadA = 0; 147 | loadB = 0; 148 | loadC = 0; 149 | loadIR = 0; 150 | loadPC = 0; 151 | incPC = 1; 152 | mode = 1'b0; 153 | we_DM = 1; 154 | #5 we_DM = 0; 155 | selA = 1'b0; 156 | selB = 1'b0; 157 | end 158 | // Load A operation 159 | 0100: begin 160 | loadA = 1; 161 | loadB = 0; 162 | loadC = 0; 163 | loadIR = 0; 164 | loadPC = 0; 165 | incPC = 1; 166 | mode = 1'bZ; 167 | we_DM = 1; 168 | #5 we_DM = 0; 169 | selA = 1'b0; 170 | selB = 1'b0; 171 | end 172 | // Load B operation 173 | 0101: begin 174 | loadA = 0; 175 | loadB = 1; 176 | loadC = 0; 177 | loadIR = 0; 178 | loadPC = 0; 179 | incPC = 1; 180 | mode = 1'bZ; 181 | we_DM = 1; 182 | #5 we_DM = 0; 183 | selA = 1'b0; 184 | selB = 1'b0; 185 | end 186 | // Load C operation 187 | 0110: begin 188 | loadA = 0; 189 | loadB = 0; 190 | loadC = 1; 191 | loadIR = 0; 192 | loadPC = 0; 193 | incPC = 1; 194 | mode = 1'b0; 195 | we_DM = 1; 196 | #5 we_DM = 0; 197 | selA = 1'b0; 198 | selB = 1'b0; 199 | end 200 | // JMP translation 201 | 0111: begin 202 | loadA = 0; 203 | loadB = 0; 204 | loadC = 0; 205 | loadIR = 0; 206 | loadPC = 1; 207 | incPC = 1; 208 | mode = 1'b0; 209 | we_DM = 1; 210 | selA = 1'b1; 211 | selB = 1'b1; 212 | end 213 | // Mode 1, ALU operation for opcode 000 214 | 1000: begin 215 | loadA = 0; 216 | loadB = 0; 217 | loadC = 0; 218 | loadIR = 0; 219 | loadPC = 0; 220 | incPC = 1; 221 | mode = 1'b1; 222 | we_DM = 1; 223 | #5 we_DM = 0; 224 | selA = 1'b0; 225 | selB = 1'b0; 226 | end 227 | // Mode 1, ALU operation for opcode 001 228 | 1001: begin 229 | loadA = 0; 230 | loadB = 0; 231 | loadC = 0; 232 | loadIR = 0; 233 | loadPC = 0; 234 | incPC = 1; 235 | mode = 1'b1; 236 | we_DM = 1; 237 | selA = 1'b0; 238 | selB = 1'b0; 239 | end 240 | // Mode 1, ALU operation for opcode 010 241 | 1010: begin 242 | loadA = 0; 243 | loadB = 0; 244 | loadC = 0; 245 | loadIR = 0; 246 | loadPC = 0; 247 | incPC = 1; 248 | mode = 1'b1; 249 | we_DM = 1; 250 | #5 we_DM = 0; 251 | selA = 1'b0; 252 | selB = 1'b0; 253 | end 254 | // Mode 1, ALU operation for opcode 011 255 | 1011: begin 256 | loadA = 0; 257 | loadB = 0; 258 | loadC = 0; 259 | loadIR = 0; 260 | loadPC = 0; 261 | incPC = 1; 262 | mode = 1'b1; 263 | we_DM = 1; 264 | #5 we_DM = 0; 265 | selA = 1'b0; 266 | selB = 1'b0; 267 | end 268 | // Mode 1, ALU operation for opcode 100 269 | 1100: begin 270 | loadA = 0; 271 | loadB = 0; 272 | loadC = 0; 273 | loadIR = 0; 274 | loadPC = 0; 275 | incPC = 1; 276 | mode = 1'b1; 277 | we_DM = 1; 278 | #5 we_DM = 0; 279 | selA = 1'b0; 280 | selB = 1'b0; 281 | end 282 | // Mode 1, ALU operation for opcode 101 283 | 1101: begin 284 | loadA = 0; 285 | loadB = 0; 286 | loadC = 0; 287 | loadIR = 0; 288 | loadPC = 0; 289 | incPC = 1; 290 | mode = 1'b1; 291 | we_DM = 1; 292 | #5 we_DM = 0; 293 | selA = 1'b0; 294 | selB = 1'b0; 295 | end 296 | // Mode 1, ALU operation for opcode 110 297 | 1110: begin 298 | loadA = 0; 299 | loadB = 0; 300 | loadC = 0; 301 | loadIR = 0; 302 | loadPC = 0; 303 | incPC = 1; 304 | mode = 1'b1; 305 | we_DM = 1; 306 | #5 we_DM = 0; 307 | selA = 1'b0; 308 | selB = 1'b0; 309 | end 310 | // Mode 1, ALU operation for opcode 111 311 | 1111: begin 312 | loadA = 0; 313 | loadB = 0; 314 | loadC = 0; 315 | loadIR = 0; 316 | loadPC = 0; 317 | incPC = 1; 318 | mode = 1'b1; 319 | we_DM = 1; 320 | selA = 1'b0; 321 | selB = 1'b0; 322 | end 323 | default: begin 324 | loadA = 0; 325 | loadB = 0; 326 | loadC = 0; 327 | loadIR = 1; 328 | mode = 1'bZ; 329 | we_DM = 0; 330 | selA = 1'b0; 331 | selB = 1'b0; 332 | end 333 | endcase 334 | next_state = load; 335 | end 336 | 337 | default: begin 338 | loadA = 0; 339 | loadB = 0; 340 | loadC = 0; 341 | loadIR = 1; 342 | mode = 1'bZ; 343 | we_DM = 0; 344 | selA = 1'b0; 345 | selB = 1'b0; 346 | next_state = reset; 347 | end 348 | endcase 349 | end 350 | end 351 | endmodule 352 | 353 | /////////////////////////////////////////////////////////////// 354 | ///////// Testbench for controller /////////////////////////// 355 | ////////////////////////////////////////////////////////////// 356 | module tb_controller (); 357 | reg clk; 358 | reg en; 359 | reg [3:0] opcode; 360 | wire loadA; 361 | wire loadB; 362 | wire loadC; 363 | wire loadIR; 364 | wire loadPC; 365 | wire incPC; 366 | wire mode; 367 | wire we_DM; 368 | wire selA; 369 | wire selB; 370 | 371 | // Design instantiation 372 | controller c1 (.clk(clk), .en(en), .opcode(opcode), .loadA(loadA), .loadB(loadB), .loadC(loadC), .loadIR(loadIR), .loadPC(loadPC), .incPC(incPC), .mode(mode), .we_DM(we_DM), .selA(selA), .selB(selB)); 373 | 374 | // initialization 375 | initial 376 | begin 377 | clk = 0; 378 | en = 0; 379 | opcode = 4'b0000; 380 | end 381 | // Clock setup 382 | always #5 clk = ~clk; 383 | 384 | // Stimulus 385 | initial 386 | begin 387 | #10 en = 1; 388 | opcode = 4'b0001; 389 | 390 | #20 opcode = 4'b0001; 391 | 392 | #20 opcode = 4'b0010; 393 | end 394 | endmodule -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Controller.v.bak: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | //////// Verilog Program for the controller of the CPU /////// 3 | ////////////////////////////////////////////////////////////////////////////// 4 | module controller ( clk, en, opcode, loadA, loadB, loadC, loadIR, loadPC, incPC, mode, we_DM, selA, selB); 5 | input clk; 6 | input en; 7 | input [3:0] opcode; 8 | output loadA; 9 | output loadB; 10 | output loadC; 11 | output loadIR; 12 | output loadPC; 13 | output incPC; 14 | output mode; 15 | output we_DM; 16 | output selA; 17 | output selB; 18 | 19 | reg loadA; 20 | reg loadB; 21 | reg loadC; 22 | reg loadIR; 23 | reg mode; 24 | reg we_DM; 25 | reg selA; 26 | reg selB; 27 | reg loadPC; 28 | reg incPC; 29 | 30 | // Registers to hold the value of state and next state 31 | 32 | reg [2:0] state; 33 | reg [2:0] next_state; 34 | 35 | parameter reset = 3'b000, load = 3'b010, execute = 3'b100; 36 | 37 | 38 | //Code for operation of the CPU 39 | always@(posedge clk) 40 | begin 41 | 42 | if ( en == 0 ) begin 43 | state = reset; 44 | end 45 | else if (en == 1) begin 46 | state = next_state; 47 | end 48 | end 49 | 50 | 51 | // Now for the Output logic. Output logic depends on OPCODE and Enable signal 52 | always@(*) 53 | begin 54 | if ( en == 0 ) begin 55 | loadA = 0; 56 | loadB = 0; 57 | loadC = 0; 58 | loadIR = 0; 59 | loadPC = 0; 60 | incPC = 0; 61 | mode = 1'bZ; 62 | we_DM = 0; 63 | selA = 1'b0; 64 | selB = 1'b0; 65 | next_state = reset; 66 | end 67 | 68 | else begin 69 | 70 | case(state) 71 | // We just wait for a small duration of time in the same state to see if there is any change in input 72 | reset: begin 73 | loadA = 0; 74 | loadB = 0; 75 | loadC = 0; 76 | loadIR = 0; 77 | loadPC = 0; 78 | incPC = 0; 79 | mode = 1'bZ; 80 | we_DM = 0; 81 | selA = 1'b0; 82 | selB = 1'b0; 83 | next_state = load; 84 | end 85 | 86 | load: begin 87 | loadA = 0; 88 | loadB = 0; 89 | loadC = 0; 90 | loadIR = 1; 91 | loadPC = 1; 92 | incPC = 0; 93 | mode = 1'bZ; 94 | we_DM = 0; 95 | selA = 1'b0; 96 | selB = 1'b0; 97 | next_state = execute; 98 | end 99 | 100 | execute:begin 101 | case(opcode) 102 | // Mode 0, ALU operation for opcode 000 103 | 0000: begin 104 | loadA = 0; 105 | loadB = 0; 106 | loadC = 0; 107 | loadIR = 0; 108 | loadPC = 0; 109 | incPC = 1; 110 | mode = 1'b0; 111 | we_DM = 1; 112 | selA = 1'b0; 113 | selB = 1'b0; 114 | end 115 | // Mode 0, ALU operation for opcode 001 116 | 0001: begin 117 | loadA = 0; 118 | loadB = 0; 119 | loadC = 0; 120 | loadIR = 0; 121 | loadPC = 0; 122 | incPC = 1; 123 | mode = 1'b0; 124 | we_DM = 1; 125 | selA = 1'b0; 126 | selB = 1'b0; 127 | end 128 | // Mode 0, ALU operation for opcode 010 129 | 0010: begin 130 | loadA = 0; 131 | loadB = 0; 132 | loadC = 0; 133 | loadIR = 0; 134 | loadPC = 0; 135 | incPC = 1; 136 | mode = 1'b0; 137 | we_DM = 1; 138 | selA = 1'b0; 139 | selB = 1'b0; 140 | end 141 | // Mode 0, ALU operation for opcode 011 142 | 0011: begin 143 | loadA = 0; 144 | loadB = 0; 145 | loadC = 0; 146 | loadIR = 0; 147 | loadPC = 0; 148 | incPC = 1; 149 | mode = 1'b0; 150 | we_DM = 1; 151 | selA = 1'b0; 152 | selB = 1'b0; 153 | end 154 | // Load A operation 155 | 0100: begin 156 | loadA = 1; 157 | loadB = 0; 158 | loadC = 0; 159 | loadIR = 0; 160 | loadPC = 0; 161 | incPC = 1; 162 | mode = 1'bZ; 163 | we_DM = 1; 164 | selA = 1'b0; 165 | selB = 1'b0; 166 | end 167 | // Load B operation 168 | 0101: begin 169 | loadA = 0; 170 | loadB = 1; 171 | loadC = 0; 172 | loadIR = 0; 173 | loadPC = 0; 174 | incPC = 1; 175 | mode = 1'bZ; 176 | we_DM = 1; 177 | selA = 1'b0; 178 | selB = 1'b0; 179 | end 180 | // Load C operation 181 | 0110: begin 182 | loadA = 0; 183 | loadB = 0; 184 | loadC = 1; 185 | loadIR = 0; 186 | loadPC = 0; 187 | incPC = 1; 188 | mode = 1'b0; 189 | we_DM = 1; 190 | selA = 1'b0; 191 | selB = 1'b0; 192 | end 193 | // JMP translation 194 | 0111: begin 195 | loadA = 0; 196 | loadB = 0; 197 | loadC = 0; 198 | loadIR = 0; 199 | loadPC = 1; 200 | incPC = 1; 201 | mode = 1'b0; 202 | we_DM = 1; 203 | selA = 1'b1; 204 | selB = 1'b1; 205 | end 206 | // Mode 1, ALU operation for opcode 000 207 | 1000: begin 208 | loadA = 0; 209 | loadB = 0; 210 | loadC = 0; 211 | loadIR = 0; 212 | loadPC = 0; 213 | incPC = 1; 214 | mode = 1'b1; 215 | we_DM = 1; 216 | selA = 1'b0; 217 | selB = 1'b0; 218 | end 219 | // Mode 1, ALU operation for opcode 001 220 | 1001: begin 221 | loadA = 0; 222 | loadB = 0; 223 | loadC = 0; 224 | loadIR = 0; 225 | loadPC = 0; 226 | incPC = 1; 227 | mode = 1'b1; 228 | we_DM = 1; 229 | selA = 1'b0; 230 | selB = 1'b0; 231 | end 232 | // Mode 1, ALU operation for opcode 010 233 | 1010: begin 234 | loadA = 0; 235 | loadB = 0; 236 | loadC = 0; 237 | loadIR = 0; 238 | loadPC = 0; 239 | incPC = 1; 240 | mode = 1'b1; 241 | we_DM = 1; 242 | selA = 1'b0; 243 | selB = 1'b0; 244 | end 245 | // Mode 1, ALU operation for opcode 011 246 | 1011: begin 247 | loadA = 0; 248 | loadB = 0; 249 | loadC = 0; 250 | loadIR = 0; 251 | loadPC = 0; 252 | incPC = 1; 253 | mode = 1'b1; 254 | we_DM = 1; 255 | selA = 1'b0; 256 | selB = 1'b0; 257 | end 258 | // Mode 1, ALU operation for opcode 100 259 | 1100: begin 260 | loadA = 0; 261 | loadB = 0; 262 | loadC = 0; 263 | loadIR = 0; 264 | loadPC = 0; 265 | incPC = 1; 266 | mode = 1'b1; 267 | we_DM = 1; 268 | selA = 1'b0; 269 | selB = 1'b0; 270 | end 271 | // Mode 1, ALU operation for opcode 101 272 | 1101: begin 273 | loadA = 0; 274 | loadB = 0; 275 | loadC = 0; 276 | loadIR = 0; 277 | loadPC = 0; 278 | incPC = 1; 279 | mode = 1'b1; 280 | we_DM = 1; 281 | selA = 1'b0; 282 | selB = 1'b0; 283 | end 284 | // Mode 1, ALU operation for opcode 110 285 | 1110: begin 286 | loadA = 0; 287 | loadB = 0; 288 | loadC = 0; 289 | loadIR = 0; 290 | loadPC = 0; 291 | incPC = 1; 292 | mode = 1'b1; 293 | we_DM = 1; 294 | selA = 1'b0; 295 | selB = 1'b0; 296 | end 297 | // Mode 1, ALU operation for opcode 111 298 | 1111: begin 299 | loadA = 0; 300 | loadB = 0; 301 | loadC = 0; 302 | loadIR = 0; 303 | loadPC = 0; 304 | incPC = 1; 305 | mode = 1'b1; 306 | we_DM = 1; 307 | selA = 1'b0; 308 | selB = 1'b0; 309 | end 310 | default: begin 311 | loadA = 0; 312 | loadB = 0; 313 | loadC = 0; 314 | loadIR = 1; 315 | mode = 1'bZ; 316 | we_DM = 0; 317 | selA = 1'b0; 318 | selB = 1'b0; 319 | end 320 | endcase 321 | next_state = load; 322 | end 323 | 324 | default: begin 325 | loadA = 0; 326 | loadB = 0; 327 | loadC = 0; 328 | loadIR = 1; 329 | mode = 1'bZ; 330 | we_DM = 0; 331 | selA = 1'b0; 332 | selB = 1'b0; 333 | next_state = reset; 334 | end 335 | endcase 336 | end 337 | end 338 | endmodule 339 | 340 | /////////////////////////////////////////////////////////////// 341 | ///////// Testbench for controller /////////////////////////// 342 | ////////////////////////////////////////////////////////////// 343 | module tb_controller (); 344 | reg clk; 345 | reg en; 346 | reg [3:0] opcode; 347 | wire loadA; 348 | wire loadB; 349 | wire loadC; 350 | wire loadIR; 351 | wire loadPC; 352 | wire incPC; 353 | wire mode; 354 | wire we_DM; 355 | wire selA; 356 | wire selB; 357 | 358 | // Design instantiation 359 | controller c1 (.clk(clk), .en(en), .opcode(opcode), .loadA(loadA), .loadB(loadB), .loadC(loadC), .loadIR(loadIR), .loadPC(loadPC), .incPC(incPC), .mode(mode), .we_DM(we_DM), .selA(selA), .selB(selB)); 360 | 361 | // initialization 362 | initial 363 | begin 364 | clk = 0; 365 | en = 0; 366 | opcode = 4'b0000; 367 | end 368 | // Clock setup 369 | always #5 clk = ~clk; 370 | 371 | // Stimulus 372 | initial 373 | begin 374 | #10 en = 1; 375 | opcode = 4'b0001; 376 | 377 | #20 opcode = 4'b0001; 378 | 379 | #20 opcode = 4'b0010; 380 | end 381 | endmodule -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Counter.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////// 2 | // This program is for a 4-bit ------ 3 | // Requirements: ------ 4 | // 4-bit synchronous up counter. ------ 5 | // Active high, synchronous reset. ------ 6 | // Active high enable. ------ 7 | /////////////////////////////////////////////////////////////// 8 | 9 | module counter4b( clk,rst,en,out); 10 | input clk,rst,en; 11 | output [3:0] out; 12 | wire clk, rst,en; 13 | reg [3:0] out; 14 | 15 | always@(posedge clk) 16 | begin 17 | if(rst == 1'b1) 18 | begin 19 | out <= 4'b0000; 20 | end 21 | else if (en == 1'b1) 22 | begin 23 | out <= out + 4'b0001; 24 | end 25 | end 26 | endmodule 27 | ////////////// Test bench to for the counter /////////////// 28 | 29 | module tb_counter4b(); 30 | reg clk,rst,en; 31 | wire [3:0] outtb; 32 | 33 | // Initialise the input signals 34 | initial 35 | begin 36 | clk<=1'b0; 37 | rst<=1'b0; 38 | en<=1'b0; 39 | end 40 | 41 | // Instantiation of the Counter4b module 42 | 43 | counter4b c1(.clk(clk), .rst(rst), .en(en), .out(outtb)); 44 | 45 | // Clock signal every 10ns 46 | 47 | always #10 clk = ~clk; 48 | 49 | // Stimulus for checking the working of counter 50 | 51 | initial 52 | begin 53 | #5 rst <= 1; 54 | #10 en <= 1; 55 | 56 | #10 rst <= 0; 57 | #10 en <= 1; 58 | 59 | #100 en <= 0; 60 | 61 | #10 rst <= 1; 62 | end 63 | endmodule 64 | 65 | 66 | 67 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Counter.v.bak: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////// 2 | // This program is for a 4-bit ------ 3 | // Requirements: ------ 4 | // 4-bit synchronous up counter. ------ 5 | // Active high, synchronous reset. ------ 6 | // Active high enable. ------ 7 | /////////////////////////////////////////////////////////////// 8 | 9 | module counter4b( clk,rst,en,out); 10 | input clk,rst,en; 11 | output [3:0] out; 12 | wire clk, rst,en; 13 | reg [3:0] out; 14 | 15 | always@(posedge clk) 16 | begin 17 | if(rst == 1'b1) 18 | begin 19 | out <= 4'b0000; 20 | end 21 | else if (en == 1'b1) 22 | begin 23 | out <= out + 4'b0001; 24 | end 25 | end 26 | endmodule 27 | ////////////// Test bench to for the counter /////////////// 28 | 29 | module tb_counter4b(); 30 | reg clk,rst,en; 31 | wire [3:0] outtb; 32 | 33 | // Initialise the input signals 34 | initial 35 | begin 36 | clk<=1'b0; 37 | rst<=1'b0; 38 | en<=1'b0; 39 | end 40 | 41 | // Instantiation of the Counter4b module 42 | 43 | counter4b c1(.clk(clk), .rst(rst), .en(en), .out(outtb)); 44 | 45 | // Clock signal every 10ns 46 | 47 | always #10 clk = ~clk; 48 | 49 | // Stimulus for checking the working of counter 50 | 51 | initial 52 | begin 53 | #5 rst = 1; 54 | #10 en = 1; 55 | 56 | #10 rst = 0; 57 | #10 en = 1; 58 | 59 | #100 en = 0; 60 | 61 | #10 rst = 1; 62 | end 63 | endmodule 64 | 65 | 66 | 67 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/DataMemory.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // Program to realise Datamemory in the CPU ///// 3 | //////////////////////////////////////////////////////////////////// 4 | 5 | module datamem(clk, we_DM, dataDM, addDM, outDM); 6 | input clk; 7 | input we_DM; 8 | input [31:0] dataDM; 9 | input [11:0] addDM; 10 | output [31:0] outDM; 11 | 12 | reg [31:0] outDM; 13 | 14 | // Memory is an array stored at particular address 15 | 16 | reg [31:0] mem [0 : 31]; 17 | 18 | always@(posedge clk) 19 | begin 20 | if (we_DM == 1) begin 21 | mem[addDM] = dataDM; 22 | end 23 | 24 | else if (we_DM == 0) begin 25 | outDM = mem[addDM]; 26 | end 27 | end 28 | endmodule 29 | 30 | //////////////////////////////////////////////////////////////////////// 31 | // Test bench for the data memory design used /////// 32 | ////////////////////////////////////////////////////////////////////// 33 | module tb_datamem(); 34 | reg clk; 35 | reg we_DM; 36 | reg [31:0] dataDM; 37 | reg [11:0] addDM; 38 | wire [31:0] outDM; 39 | 40 | // Instantiation of the design 41 | datamem d1 (.clk(clk), .we_DM(we_DM), .dataDM(dataDM), .addDM(addDM), .outDM(outDM)); 42 | 43 | // Initialization of signals 44 | initial 45 | begin 46 | clk <= 0; 47 | we_DM <= 0; 48 | dataDM <= 32'h00000000; 49 | addDM <= 12'h000; 50 | end 51 | 52 | // Clock setup 53 | always #5 clk = ~clk; 54 | 55 | // Address setup 56 | always #60 addDM = addDM + 12'h001; 57 | 58 | // Stimulus 59 | initial 60 | begin 61 | #5 we_DM <= 1; 62 | #5 dataDM <= 32'h1dfe; 63 | #30 we_DM <= 0; 64 | 65 | #30 we_DM <= 1; 66 | #5 dataDM <= 32'h1001; 67 | #30 we_DM <= 0; 68 | end 69 | endmodule 70 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/DataMemory.v.bak: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // Program to realise Datamemory in the CPU ///// 3 | //////////////////////////////////////////////////////////////////// 4 | 5 | module datamem(clk, we_DM, dataDM, addDM, outDM); 6 | input clk; 7 | input we_DM; 8 | input [31:0] dataDM; 9 | input [11:0] addDM; 10 | output [31:0] outDM; 11 | 12 | reg [31:0] outDM; 13 | 14 | // Memory is an array stored at particular address 15 | 16 | reg [31:0] mem [0 : 31]; 17 | 18 | always@(posedge clk) 19 | begin 20 | if (we_DM == 1) begin 21 | mem[addDM] = dataDM; 22 | end 23 | 24 | else if (we_DM == 0) begin 25 | outDM = mem[addDM]; 26 | end 27 | end 28 | endmodule 29 | 30 | //////////////////////////////////////////////////////////////////////// 31 | // Test bench for the data memory design used /////// 32 | ////////////////////////////////////////////////////////////////////// 33 | module tb_datamem(); 34 | reg clk; 35 | reg we_DM; 36 | reg [31:0] dataDM; 37 | reg [11:0] addDM; 38 | wire [31:0] outDM; 39 | 40 | // Instantiation of the design 41 | datamem d1 (.clk(clk), .we_DM(we_DM), .dataDM(dataDM), .addDM(addDM), .outDM(outDM)); 42 | 43 | // Initialization of signals 44 | initial 45 | begin 46 | clk <= 0; 47 | we_DM <= 0; 48 | dataDM <= 32'h00000000; 49 | addDM <= 12'h000; 50 | end 51 | 52 | // Clock setup 53 | always #5 clk = ~clk; 54 | 55 | // Address setup 56 | always #60 addDM = addDM + 12'h001; 57 | 58 | // Stimulus 59 | initial 60 | begin 61 | #5 we_DM <= 1; 62 | #5 dataDM <= 32'h1dfe; 63 | #30 we_DM <= 0; 64 | 65 | #5 we_DM <= 1; 66 | #5 dataDM <= 32'h1001; 67 | #30 we_DM <= 0; 68 | end 69 | endmodule 70 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Encoder16-4.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////// 2 | // Design of a 16-bit Encoder ///// 3 | // The encoder has 16-bit input ///// 4 | // and 4-bit output. ///// 5 | //////////////////////////////////////////////////////////// 6 | 7 | module encode164( out, in, en); 8 | output [3:0] out; 9 | input [15:0] in; 10 | input en; 11 | 12 | reg [3:0] out; 13 | 14 | always@(en or in) 15 | begin 16 | out = 0; 17 | if (en == 1) 18 | begin 19 | case(in) 20 | 16'b0000000000000010: out = 4'b0001; 21 | 16'b0000000000000100: out = 4'b0010; 22 | 16'b0000000000001000: out = 4'b0011; 23 | 16'b0000000000010000: out = 4'b0100; 24 | 16'b0000000000100000: out = 4'b0101; 25 | 16'b0000000001000000: out = 4'b0110; 26 | 16'b0000000010000000: out = 4'b0111; 27 | 16'b0000000100000000: out = 4'b1000; 28 | 16'b0000001000000000: out = 4'b1001; 29 | 16'b0000010000000000: out = 4'b1010; 30 | 16'b0000100000000000: out = 4'b1011; 31 | 16'b0001000000000000: out = 4'b1100; 32 | 16'b0010000000000000: out = 4'b1101; 33 | 16'b0100000000000000: out = 4'b1110; 34 | 16'b1000000000000000: out = 4'b1111; 35 | default out = 4'b0000; 36 | endcase 37 | end 38 | end 39 | endmodule 40 | 41 | ////////////////////////////////////////////////////////////////////// 42 | // Testbench to test the design for working ///// 43 | ///////////////////////////////////////////////////////////////////// 44 | 45 | module tb_encode(); 46 | wire [3:0] out; 47 | reg [15:0] in; 48 | reg en; 49 | 50 | // Instantiation of the design 51 | 52 | encode164 e1(.out(out),.in(in),.en(en)); 53 | 54 | // Initialise the signals 55 | initial 56 | begin 57 | in = 16'b0000000000000000; 58 | en = 0; 59 | end 60 | 61 | initial 62 | begin 63 | #10 en = 1; 64 | #10 in = 16'b0000000000000010; 65 | repeat (14) 66 | begin 67 | #10 in = in << 1; 68 | end 69 | end 70 | endmodule 71 | 72 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/Encoder16-4.v.bak: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////// 2 | // Design of a 16-bit Encoder ///// 3 | // The encoder has 16-bit input ///// 4 | // and 4-bit output. ///// 5 | //////////////////////////////////////////////////////////// 6 | 7 | module encode164( out, in, en); 8 | output [3:0] out; 9 | input [15:0] in; 10 | input en; 11 | 12 | reg [3:0] out; 13 | 14 | always@(en or in) 15 | begin 16 | out = 0; 17 | if (en == 1) 18 | begin 19 | case(in) 20 | 16'b0000000000000010: out = 4'b0001; 21 | 16'b0000000000000100: out = 4'b0010; 22 | 16'b0000000000001000: out = 4'b0011; 23 | 16'b0000000000010000: out = 4'b0100; 24 | 16'b0000000000100000: out = 4'b0101; 25 | 16'b0000000001000000: out = 4'b0110; 26 | 16'b0000000010000000: out = 4'b0111; 27 | 16'b0000000100000000: out = 4'b1000; 28 | 16'b0000001000000000: out = 4'b1001; 29 | 16'b0000010000000000: out = 4'b1010; 30 | 16'b0000100000000000: out = 4'b1011; 31 | 16'b0001000000000000: out = 4'b1100; 32 | 16'b0010000000000000: out = 4'b1101; 33 | 16'b0100000000000000: out = 4'b1110; 34 | 16'b1000000000000000: out = 4'b1111; 35 | default out = 4'b0000; 36 | endcase 37 | end 38 | end 39 | endmodule 40 | 41 | ////////////////////////////////////////////////////////////////////// 42 | // Testbench to test the design for working ///// 43 | ///////////////////////////////////////////////////////////////////// 44 | 45 | module tb_encode(); 46 | wire [3:0] out; 47 | reg [15:0] in; 48 | reg en; 49 | 50 | // Instantiation of the design 51 | 52 | encode164 e1(.out(out),.in(in),.en(en)); 53 | 54 | // Initialise the signals 55 | initial 56 | begin 57 | in = 16'b0000000000000000; 58 | en = 0; 59 | end 60 | 61 | initial 62 | begin 63 | #10 en = 1; 64 | #5 in = 16'b0000000000000010; 65 | repeat (14) 66 | begin 67 | #5 in = in << 1; 68 | end 69 | end 70 | endmodule 71 | 72 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/InstMemory.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // Program to realise Instmemory in the CPU ///// 3 | //////////////////////////////////////////////////////////////////// 4 | 5 | module instmem(clk, we_IM, dataIM, addIM, outIM); 6 | input clk; 7 | input we_IM; 8 | input [15:0] dataIM; 9 | input [11:0] addIM; 10 | output [15:0] outIM; 11 | 12 | reg [15:0] outIM; 13 | 14 | // Memory is an array stored at particular address 15 | 16 | reg [15:0] mem [0 : 15]; 17 | 18 | always@(posedge clk) 19 | begin 20 | if (we_IM == 1) begin 21 | mem[addIM] = dataIM; 22 | end 23 | 24 | else if (we_IM == 0) begin 25 | outIM = mem[addIM]; 26 | end 27 | end 28 | endmodule 29 | 30 | //////////////////////////////////////////////////////////////////////// 31 | // Test bench for the Instruction memory design used /////// 32 | ////////////////////////////////////////////////////////////////////// 33 | module tb_instmem(); 34 | reg clk; 35 | reg we_IM; 36 | reg [15:0] dataIM; 37 | reg [11:0] addIM; 38 | wire [15:0] outIM; 39 | 40 | // Instantiation of the design 41 | instmem d1 (.clk(clk), .we_IM(we_IM), .dataIM(dataIM), .addIM(addIM), .outIM(outIM)); 42 | 43 | 44 | // Initialization of signals 45 | initial 46 | begin 47 | clk <= 0; 48 | we_IM <= 0; 49 | dataIM <= 16'h0000; 50 | addIM <= 12'h000; 51 | end 52 | 53 | // Clock setup 54 | always #5 clk = ~clk; 55 | 56 | // Address setup 57 | always #60 addIM = addIM + 12'h001; 58 | 59 | // Stimulus 60 | initial 61 | begin 62 | #5 we_IM <= 1; 63 | #5 dataIM <= 16'h0234; 64 | #30 we_IM <= 0; 65 | 66 | #60 we_IM <= 1; 67 | #60 dataIM <= 16'h0381; 68 | #90 we_IM <= 0; 69 | end 70 | endmodule 71 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/InstMemory.v.bak: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // Program to realise Instmemory in the CPU ///// 3 | //////////////////////////////////////////////////////////////////// 4 | 5 | module instmem(clk, we_IM, dataIM, addIM, outIM); 6 | input clk; 7 | input we_IM; 8 | input [15:0] dataIM; 9 | input [11:0] addIM; 10 | output [15:0] outIM; 11 | 12 | reg [15:0] outIM; 13 | 14 | // Memory is an array stored at particular address 15 | 16 | reg [15:0] mem [0 : 15]; 17 | 18 | always@(posedge clk) 19 | begin 20 | if (we_IM == 1) begin 21 | mem[addIM] = dataIM; 22 | end 23 | 24 | else if (we_IM == 0) begin 25 | outIM = mem[addIM]; 26 | end 27 | end 28 | endmodule 29 | 30 | //////////////////////////////////////////////////////////////////////// 31 | // Test bench for the Instruction memory design used /////// 32 | ////////////////////////////////////////////////////////////////////// 33 | module tb_instmem(); 34 | reg clk; 35 | reg we_IM; 36 | reg [15:0] dataIM; 37 | reg [11:0] addIM; 38 | wire [15:0] outIM; 39 | 40 | // Instantiation of the design 41 | instmem d1 (.clk(clk), .we_IM(we_IM), .dataIM(dataIM), .addIM(addIM), .outIM(outIM)); 42 | 43 | 44 | // Initialization of signals 45 | initial 46 | begin 47 | clk <= 0; 48 | we_IM <= 0; 49 | dataIM <= 16'h0000; 50 | addIM <= 12'h000; 51 | end 52 | 53 | // Clock setup 54 | always #5 clk = ~clk; 55 | 56 | // Address setup 57 | always #60 addIM = addIM + 12'h001; 58 | 59 | // Stimulus 60 | initial 61 | begin 62 | #5 we_IM <= 1; 63 | #5 data_IM <= 16'h0234; 64 | #30 we_IM <= 0; 65 | 66 | #60 we_IM <= 1; 67 | #60 data_IM <= 16'h0381; 68 | #90 we_IM <= 0; 69 | end 70 | endmodule 71 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/InstReg.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | ////// Instruction Register realization /////// 3 | /////////////////////////////////////////////////////////////// 4 | module insReg ( clk, loadIR, insin, address, opcode); 5 | input clk; 6 | input loadIR; 7 | input [15:0] insin; 8 | output [11:0] address; 9 | output [3:0] opcode; 10 | 11 | reg [11:0] address; 12 | reg [3:0] opcode; 13 | 14 | reg [15:0] temp; 15 | 16 | always@(posedge clk) 17 | begin 18 | if(loadIR == 1) begin 19 | temp <= insin; 20 | end 21 | address <= temp[11:0]; 22 | opcode <= temp[15:12]; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/InstReg.v.bak: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/LogicUnit.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////// 2 | //// This module describes a Logic unit of ALU. ///// 3 | /// This will have two inputs of 16 bits each. ///// 4 | /// It has to provide either logic operation //// 5 | //////////////////////////////////////////////////////////////////////////// 6 | module logic(a,b,opcode,outlu,za,zb,eq,gt,lt); 7 | input [15:0] a; 8 | input [15:0] b; 9 | input [2:0] opcode; 10 | output [31:0] outlu; 11 | output za, zb,eq,gt,lt; 12 | 13 | reg [31:0] outlu; 14 | reg za,zb,eq,gt,lt; 15 | 16 | always@(a,b,opcode) 17 | begin 18 | case(opcode) 19 | 3'b000: outlu = {16'h0000, (a & b)}; 20 | 3'b001: outlu = {16'h0000, (a | b)}; 21 | 3'b010: outlu = {16'h0000, (~(a | b))}; 22 | 3'b100: outlu = {16'h0000, (~ a)}; 23 | 3'b101: outlu = {16'h0000, (~ b)}; 24 | 3'b110: outlu = {16'h0000, (a ^ b)}; 25 | 3'b111: outlu = {16'h0000, (~(a ^ b))}; 26 | default outlu = 32'h00000000; 27 | endcase 28 | end 29 | 30 | always@(a,b) 31 | begin 32 | if( a == b) begin 33 | eq = 1; 34 | end 35 | else begin 36 | eq = 0; 37 | end 38 | 39 | if ( a > b) begin 40 | gt = 1; 41 | end 42 | else begin 43 | gt = 0; 44 | end 45 | 46 | if ( a < b) begin 47 | lt = 1; 48 | end 49 | else begin 50 | lt = 0; 51 | end 52 | 53 | if( a == 16'h0000) begin 54 | za = 1; 55 | end 56 | else begin 57 | za = 0; 58 | end 59 | 60 | if (b == 16'h0000) begin 61 | zb = 1; 62 | end 63 | else begin 64 | zb = 0; 65 | end 66 | end 67 | endmodule 68 | 69 | //////////////////////////////////////////////////////////////// 70 | // Test bench for the logic unit /////// 71 | /////////////////////////////////////////////////////////////// 72 | 73 | module tb_logic(); 74 | reg [15:0] a; 75 | reg [15:0] b; 76 | reg [2:0] opcode; 77 | wire [31:0] outlu; 78 | wire za, zb,eq,gt,lt; 79 | 80 | // Instantiation of the module 81 | 82 | logic l1 (.a(a), .b(b), .opcode(opcode), .outlu(outlu), .za(za), .zb(zb), .eq(eq), .gt(gt), .lt(lt)); 83 | 84 | // Initialization 85 | 86 | initial 87 | begin 88 | a = 16'h0000; 89 | b = 16'h0000; 90 | opcode = 3'b000; 91 | end 92 | 93 | // Stimulus must be writte in such a way that we test all the cases for input conditions. 94 | initial 95 | begin 96 | // When A>B test all the conditions 97 | #10 a = 16'h0009; 98 | b <= 16'h0005; 99 | # 5 opcode = 3'b001; 100 | # 5 opcode = 3'b010; 101 | # 5 opcode = 3'b011; 102 | # 5 opcode = 3'b100; 103 | # 5 opcode = 3'b101; 104 | # 5 opcode = 3'b110; 105 | # 5 opcode = 3'b111; 106 | 107 | // When A b) begin 40 | gt = 1; 41 | end 42 | else begin 43 | gt = 0; 44 | end 45 | 46 | if ( a < b) begin 47 | lt = 1; 48 | end 49 | else begin 50 | lt = 0; 51 | end 52 | 53 | if( a == 16'h0000) begin 54 | za = 1; 55 | end 56 | else begin 57 | za = 0; 58 | end 59 | 60 | if (b == 16'h0000) begin 61 | zb = 1; 62 | end 63 | else begin 64 | zb = 0; 65 | end 66 | end 67 | endmodule 68 | 69 | //////////////////////////////////////////////////////////////// 70 | // Test bench for the logic unit /////// 71 | /////////////////////////////////////////////////////////////// 72 | 73 | module tb_logic(); 74 | reg [15:0] a; 75 | reg [15:0] b; 76 | reg [2:0] opcode; 77 | wire [31:0] outlu; 78 | wire za, zb,eq,gt,lt; 79 | 80 | // Instantiation of the module 81 | 82 | logic l1 (.a(a), .b(b), .opcode(opcode), .outlu(outlu), .za(za), .zb(zb), .eq(eq), .gt(gt), .lt(lt)); 83 | 84 | // Initialization 85 | 86 | initial 87 | begin 88 | a = 16'h0000; 89 | b = 16'h0000; 90 | opcode = 3'b000; 91 | end 92 | 93 | // Stimulus must be writte in such a way that we test all the cases for input conditions. 94 | initial 95 | begin 96 | // When A>B test all the conditions 97 | #10 a = 16'h0009; 98 | b <= 16'h0005; 99 | # 5 opcode = 3'b001; 100 | # 5 opcode = 3'b010; 101 | # 5 opcode = 3'b011; 102 | # 5 opcode = 3'b100; 103 | # 5 opcode = 3'b101; 104 | # 5 opcode = 3'b110; 105 | # 5 opcode = 3'b111; 106 | 107 | // When A" syntax. 79 | ; i.e. 80 | ; vlog -optionset COMPILEDEBUG top.sv 81 | ; vsim -optionset UVMDEBUG my_top 82 | ; 83 | ; Following are some useful examples. 84 | 85 | ; define a vsim optionset for uvm debugging 86 | UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop 87 | 88 | ; define a vopt optionset for debugging 89 | VOPTDEBUG = +acc -debugdb 90 | 91 | 92 | [vcom] 93 | ; VHDL93 variable selects language version as the default. 94 | ; Default is VHDL-2002. 95 | ; Value of 0 or 1987 for VHDL-1987. 96 | ; Value of 1 or 1993 for VHDL-1993. 97 | ; Default or value of 2 or 2002 for VHDL-2002. 98 | ; Value of 3 or 2008 for VHDL-2008 99 | ; Value of 4 or ams99 for VHDL-AMS-1999 100 | ; Value of 5 or ams07 for VHDL-AMS-2007 101 | VHDL93 = 2002 102 | 103 | ; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. 104 | ; ignoreStandardRealVector = 1 105 | 106 | ; Show source line containing error. Default is off. 107 | ; Show_source = 1 108 | 109 | ; Turn off unbound-component warnings. Default is on. 110 | ; Show_Warning1 = 0 111 | 112 | ; Turn off process-without-a-wait-statement warnings. Default is on. 113 | ; Show_Warning2 = 0 114 | 115 | ; Turn off null-range warnings. Default is on. 116 | ; Show_Warning3 = 0 117 | 118 | ; Turn off no-space-in-time-literal warnings. Default is on. 119 | ; Show_Warning4 = 0 120 | 121 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. 122 | ; Show_Warning5 = 0 123 | 124 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. 125 | ; Optimize_1164 = 0 126 | 127 | ; Enable compiler statistics. Specify one or more arguments: 128 | ; [all,none,time,cmd,msg,perf,verbose,list] 129 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 130 | ; Stats = time,cmd,msg 131 | 132 | ; Turn on resolving of ambiguous function overloading in favor of the 133 | ; "explicit" function declaration (not the one automatically created by 134 | ; the compiler for each type declaration). Default is off. 135 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned 136 | ; will match the behavior of synthesis tools. 137 | Explicit = 1 138 | 139 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. 140 | ; NoVital = 1 141 | 142 | ; Turn off VITAL compliance checking. Default is checking on. 143 | ; NoVitalCheck = 1 144 | 145 | ; Ignore VITAL compliance checking errors. Default is to not ignore. 146 | ; IgnoreVitalErrors = 1 147 | 148 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. 149 | ; Show_VitalChecksWarnings = 0 150 | 151 | ; Turn off PSL assertion warning messages. Default is to show warnings. 152 | ; Show_PslChecksWarnings = 0 153 | 154 | ; Enable parsing of embedded PSL assertions. Default is enabled. 155 | ; EmbeddedPsl = 0 156 | 157 | ; Keep silent about case statement static warnings. 158 | ; Default is to give a warning. 159 | ; NoCaseStaticError = 1 160 | 161 | ; Keep silent about warnings caused by aggregates that are not locally static. 162 | ; Default is to give a warning. 163 | ; NoOthersStaticError = 1 164 | 165 | ; Treat as errors: 166 | ; case statement static warnings 167 | ; warnings caused by aggregates that are not locally static 168 | ; Overrides NoCaseStaticError, NoOthersStaticError settings. 169 | ; PedanticErrors = 1 170 | 171 | ; Turn off inclusion of debugging info within design units. 172 | ; Default is to include debugging info. 173 | ; NoDebug = 1 174 | 175 | ; Turn off "Loading..." messages. Default is messages on. 176 | ; Quiet = 1 177 | 178 | ; Turn on some limited synthesis rule compliance checking. Checks only: 179 | ; -- signals used (read) by a process must be in the sensitivity list 180 | ; CheckSynthesis = 1 181 | 182 | ; Activate optimizations on expressions that do not involve signals, 183 | ; waits, or function/procedure/task invocations. Default is off. 184 | ; ScalarOpts = 1 185 | 186 | ; Turns on lint-style checking. 187 | ; Show_Lint = 1 188 | 189 | ; Require the user to specify a configuration for all bindings, 190 | ; and do not generate a compile time default binding for the 191 | ; component. This will result in an elaboration error of 192 | ; 'component not bound' if the user fails to do so. Avoids the rare 193 | ; issue of a false dependency upon the unused default binding. 194 | ; RequireConfigForAllDefaultBinding = 1 195 | 196 | ; Perform default binding at compile time. 197 | ; Default is to do default binding at load time. 198 | ; BindAtCompile = 1; 199 | 200 | ; Inhibit range checking on subscripts of arrays. Range checking on 201 | ; scalars defined with subtypes is inhibited by default. 202 | ; NoIndexCheck = 1 203 | 204 | ; Inhibit range checks on all (implicit and explicit) assignments to 205 | ; scalar objects defined with subtypes. 206 | ; NoRangeCheck = 1 207 | 208 | ; Set the prefix to be honored for synthesis/coverage pragma recognition. 209 | ; Default is "". 210 | ; AddPragmaPrefix = "" 211 | 212 | ; Ignore synthesis and coverage pragmas with this prefix. 213 | ; Default is "". 214 | ; IgnorePragmaPrefix = "" 215 | 216 | ; Turn on code coverage in VHDL design units. Default is off. 217 | ; Coverage = sbceft 218 | 219 | ; Turn off code coverage in VHDL subprograms. Default is on. 220 | ; CoverSub = 0 221 | 222 | ; Automatically exclude VHDL case statement OTHERS choice branches. 223 | ; This includes OTHERS choices in selected signal assigment statements. 224 | ; Default is to not exclude. 225 | ; CoverExcludeDefault = 1 226 | 227 | ; Control compiler and VOPT optimizations that are allowed when 228 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 229 | ; CoverOpt = 3 230 | 231 | ; Turn on or off clkOpt optimization for code coverage. Default is on. 232 | ; CoverClkOpt = 1 233 | 234 | ; Turn on or off clkOpt optimization builtins for code coverage. Default is on. 235 | ; CoverClkOptBuiltins = 0 236 | 237 | ; Inform code coverage optimizations to respect VHDL 'H' and 'L' 238 | ; values on signals in conditions and expressions, and to not automatically 239 | ; convert them to '1' and '0'. Default is to not convert. 240 | ; CoverRespectHandL = 0 241 | 242 | ; Increase or decrease the maximum number of rows allowed in a UDP table 243 | ; implementing a VHDL condition coverage or expression coverage expression. 244 | ; More rows leads to a longer compile time, but more expressions covered. 245 | ; CoverMaxUDPRows = 192 246 | 247 | ; Increase or decrease the maximum number of input patterns that are present 248 | ; in FEC table. This leads to a longer compile time with more expressions 249 | ; covered with FEC metric. 250 | ; CoverMaxFECRows = 192 251 | 252 | ; Increase or decrease the limit on the size of expressions and conditions 253 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 254 | ; to higher compile, optimize and simulation time, but more expressions and 255 | ; conditions are considered for coverage in the design. FecUdpEffort can 256 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 257 | ; 1 - (low) Only small expressions and conditions considered for coverage. 258 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 259 | ; 3 - (high) Very large expressions and conditions considered for coverage. 260 | ; The default setting is 1 (low). 261 | ; FecUdpEffort = 1 262 | 263 | ; Enable or disable Focused Expression Coverage analysis for conditions and 264 | ; expressions. Focused Expression Coverage data is provided by default when 265 | ; expression and/or condition coverage is active. 266 | ; CoverFEC = 0 267 | 268 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 269 | ; UDP Coverage data is disabled by default when expression and/or condition 270 | ; coverage is active. 271 | ; CoverUDP = 1 272 | 273 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 274 | ; Disabling this would convert non-masking conditions in FEC tables to matching 275 | ; input patterns. 276 | ; CoverREC = 1 277 | 278 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 279 | ; for expression/condition coverage. 280 | ; NOTE: Enabling this may have a negative impact on simulation performance. 281 | ; CoverExpandReductionPrefix = 0 282 | 283 | ; Enable or disable short circuit evaluation of conditions and expressions when 284 | ; condition or expression coverage is active. Short circuit evaluation is enabled 285 | ; by default. 286 | ; CoverShortCircuit = 0 287 | 288 | ; Enable code coverage reporting of code that has been optimized away. 289 | ; The default is not to report. 290 | ; CoverReportCancelled = 1 291 | 292 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 293 | ; Default is no deglitching. 294 | ; CoverDeglitchOn = 1 295 | 296 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 297 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 298 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 299 | ; CoverDeglitchPeriod = 0 300 | 301 | ; Use this directory for compiler temporary files instead of "work/_temp" 302 | ; CompilerTempDir = /tmp 303 | 304 | ; Set this to cause the compilers to force data to be committed to disk 305 | ; when the files are closed. 306 | ; SyncCompilerFiles = 1 307 | 308 | ; Add VHDL-AMS declarations to package STANDARD 309 | ; Default is not to add 310 | ; AmsStandard = 1 311 | 312 | ; Range and length checking will be performed on array indices and discrete 313 | ; ranges, and when violations are found within subprograms, errors will be 314 | ; reported. Default is to issue warnings for violations, because subprograms 315 | ; may not be invoked. 316 | ; NoDeferSubpgmCheck = 0 317 | 318 | ; Turn ON detection of FSMs having single bit current state variable. 319 | ; FsmSingle = 1 320 | 321 | ; Turn off reset state transitions in FSM. 322 | ; FsmResetTrans = 0 323 | 324 | ; Turn ON detection of FSM Implicit Transitions. 325 | ; FsmImplicitTrans = 1 326 | 327 | ; Controls whether or not to show immediate assertions with constant expressions 328 | ; in GUI/report/UCDB etc. By default, immediate assertions with constant 329 | ; expressions are shown in GUI/report/UCDB etc. This does not affect 330 | ; evaluation of immediate assertions. 331 | ; ShowConstantImmediateAsserts = 0 332 | 333 | ; Controls how VHDL basic identifiers are stored with the design unit. 334 | ; Does not make the language case-sensitive, affects only how declarations 335 | ; declared with basic identifiers have their names stored and printed 336 | ; (in the GUI, examine, etc.). 337 | ; Default is to preserve the case as originally depicted in the VHDL source. 338 | ; Value of 0 indicates to change all basic identifiers to lower case. 339 | ; PreserveCase = 0 340 | 341 | ; For Configuration Declarations, controls the effect that USE clauses have 342 | ; on visibility inside the configuration items being configured. If 1 343 | ; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, 344 | ; extend the visibility of objects made visible through USE clauses into nested 345 | ; component configurations. 346 | ; OldVHDLConfigurationVisibility = 0 347 | 348 | ; Allows VHDL configuration declarations to be in a different library from 349 | ; the corresponding configured entity. Default is to not allow this for 350 | ; stricter LRM-compliance. 351 | ; SeparateConfigLibrary = 1; 352 | 353 | ; Determine how mode OUT subprogram parameters of type array and record are treated. 354 | ; If 0 (the default), then only VHDL 2008 will do this initialization. 355 | ; If 1, always initialize the mode OUT parameter to its default value. 356 | ; If 2, do not initialize the mode OUT out parameter. 357 | ; Note that prior to release 10.1, all language versions did not initialize mode 358 | ; OUT array and record type parameters, unless overridden here via this mechanism. 359 | ; In release 10.1 and later, only files compiled with VHDL 2008 will cause this 360 | ; initialization, unless overridden here. 361 | ; InitOutCompositeParam = 0 362 | 363 | ; Generate symbols debugging database in only some special cases to save on 364 | ; the number of files in the library. For other design-units, this database is 365 | ; generated on-demand in vsim. 366 | ; Default is to to generate debugging database for all design-units. 367 | ; SmartDbgSym = 1 368 | 369 | ; Enable or disable automatic creation of missing libraries. 370 | ; Default is 1 (enabled) 371 | ; CreateLib = 1 372 | 373 | [vlog] 374 | ; Turn off inclusion of debugging info within design units. 375 | ; Default is to include debugging info. 376 | ; NoDebug = 1 377 | 378 | ; Turn on `protect compiler directive processing. 379 | ; Default is to ignore `protect directives. 380 | ; Protect = 1 381 | 382 | ; Turn off "Loading..." messages. Default is messages on. 383 | ; Quiet = 1 384 | 385 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). 386 | ; Default is off. 387 | ; Hazard = 1 388 | 389 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case 390 | ; insensitivity for module names. Default is no conversion. 391 | ; UpCase = 1 392 | 393 | ; Activate optimizations on expressions that do not involve signals, 394 | ; waits, or function/procedure/task invocations. Default is off. 395 | ; ScalarOpts = 1 396 | 397 | ; Turns on lint-style checking. 398 | ; Show_Lint = 1 399 | 400 | ; Show source line containing error. Default is off. 401 | ; Show_source = 1 402 | 403 | ; Turn on bad option warning. Default is off. 404 | ; Show_BadOptionWarning = 1 405 | 406 | ; Revert back to IEEE 1364-1995 syntax, default is 0 (off). 407 | ; vlog95compat = 1 408 | 409 | ; Turn off PSL warning messages. Default is to show warnings. 410 | ; Show_PslChecksWarnings = 0 411 | 412 | ; Enable parsing of embedded PSL assertions. Default is enabled. 413 | ; EmbeddedPsl = 0 414 | 415 | ; Enable compiler statistics. Specify one or more arguments: 416 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 417 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 418 | ; Stats = time,cmd,msg 419 | 420 | ; Set the threshold for automatically identifying sparse Verilog memories. 421 | ; A memory with depth equal to or more than the sparse memory threshold gets 422 | ; marked as sparse automatically, unless specified otherwise in source code 423 | ; or by +nosparse commandline option of vlog or vopt. 424 | ; The default is 1M. (i.e. memories with depth equal 425 | ; to or greater than 1M are marked as sparse) 426 | ; SparseMemThreshold = 1048576 427 | 428 | ; Set the prefix to be honored for synthesis and coverage pragma recognition. 429 | ; Default is "". 430 | ; AddPragmaPrefix = "" 431 | 432 | ; Ignore synthesis and coverage pragmas with this prefix. 433 | ; Default is "". 434 | ; IgnorePragmaPrefix = "" 435 | 436 | ; Set the option to treat all files specified in a vlog invocation as a 437 | ; single compilation unit. The default value is set to 0 which will treat 438 | ; each file as a separate compilation unit as specified in the P1800 draft standard. 439 | ; MultiFileCompilationUnit = 1 440 | 441 | ; Turn on code coverage in Verilog design units. Default is off. 442 | ; Coverage = sbceft 443 | 444 | ; Automatically exclude Verilog case statement default branches. 445 | ; Default is to not automatically exclude defaults. 446 | ; CoverExcludeDefault = 1 447 | 448 | ; Increase or decrease the maximum number of rows allowed in a UDP table 449 | ; implementing a VHDL condition coverage or expression coverage expression. 450 | ; More rows leads to a longer compile time, but more expressions covered. 451 | ; CoverMaxUDPRows = 192 452 | 453 | ; Increase or decrease the maximum number of input patterns that are present 454 | ; in FEC table. This leads to a longer compile time with more expressions 455 | ; covered with FEC metric. 456 | ; CoverMaxFECRows = 192 457 | 458 | ; Increase or decrease the limit on the size of expressions and conditions 459 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 460 | ; to higher compile, optimize and simulation time, but more expressions and 461 | ; conditions are considered for coverage in the design. FecUdpEffort can 462 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 463 | ; 1 - (low) Only small expressions and conditions considered for coverage. 464 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 465 | ; 3 - (high) Very large expressions and conditions considered for coverage. 466 | ; The default setting is 1 (low). 467 | ; FecUdpEffort = 1 468 | 469 | ; Enable or disable Focused Expression Coverage analysis for conditions and 470 | ; expressions. Focused Expression Coverage data is provided by default when 471 | ; expression and/or condition coverage is active. 472 | ; CoverFEC = 0 473 | 474 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 475 | ; UDP Coverage data is disabled by default when expression and/or condition 476 | ; coverage is active. 477 | ; CoverUDP = 1 478 | 479 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 480 | ; Disabling this would convert non-masking conditions in FEC tables to matching 481 | ; input patterns. 482 | ; CoverREC = 1 483 | 484 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 485 | ; for expression/condition coverage. 486 | ; NOTE: Enabling this may have a negative impact on simulation performance. 487 | ; CoverExpandReductionPrefix = 0 488 | 489 | ; Enable or disable short circuit evaluation of conditions and expressions when 490 | ; condition or expression coverage is active. Short circuit evaluation is enabled 491 | ; by default. 492 | ; CoverShortCircuit = 0 493 | 494 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 495 | ; Default is no deglitching. 496 | ; CoverDeglitchOn = 1 497 | 498 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 499 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 500 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 501 | ; CoverDeglitchPeriod = 0 502 | 503 | ; Turn on code coverage in VLOG `celldefine modules, modules containing 504 | ; specify blocks, and modules included using vlog -v and -y. Default is off. 505 | ; CoverCells = 1 506 | 507 | ; Enable code coverage reporting of code that has been optimized away. 508 | ; The default is not to report. 509 | ; CoverReportCancelled = 1 510 | 511 | ; Control compiler and VOPT optimizations that are allowed when 512 | ; code coverage is on. This is a number from 0 to 5, with the following 513 | ; meanings (the default is 3): 514 | ; 5 -- All allowable optimizations are on. 515 | ; 4 -- Turn off removing unreferenced code. 516 | ; 3 -- Turn off process, always block and if statement merging. 517 | ; 2 -- Turn off expression optimization, converting primitives 518 | ; to continuous assignments, VHDL subprogram inlining. 519 | ; and VHDL clkOpt (converting FF's to builtins). 520 | ; 1 -- Turn off continuous assignment optimizations and clock suppression. 521 | ; 0 -- Turn off Verilog module inlining and VHDL arch inlining. 522 | ; HOWEVER, if fsm coverage is turned on, optimizations will be forced to 523 | ; level 3, with also turning off converting primitives to continuous assigns. 524 | ; CoverOpt = 3 525 | 526 | ; Specify the override for the default value of "cross_num_print_missing" 527 | ; option for the Cross in Covergroups. If not specified then LRM default 528 | ; value of 0 (zero) is used. This is a compile time option. 529 | ; SVCrossNumPrintMissingDefault = 0 530 | 531 | ; Setting following to 1 would cause creation of variables which 532 | ; would represent the value of Coverpoint expressions. This is used 533 | ; in conjunction with "SVCoverpointExprVariablePrefix" option 534 | ; in the modelsim.ini 535 | ; EnableSVCoverpointExprVariable = 0 536 | 537 | ; Specify the override for the prefix used in forming the variable names 538 | ; which represent the Coverpoint expressions. This is used in conjunction with 539 | ; "EnableSVCoverpointExprVariable" option of the modelsim.ini 540 | ; The default prefix is "expr". 541 | ; The variable name is 542 | ; variable name => _ 543 | ; SVCoverpointExprVariablePrefix = expr 544 | 545 | ; Override for the default value of the SystemVerilog covergroup, 546 | ; coverpoint, and cross option.goal (defined to be 100 in the LRM). 547 | ; NOTE: It does not override specific assignments in SystemVerilog 548 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" 549 | ; in the [vsim] section can override this value. 550 | ; SVCovergroupGoalDefault = 100 551 | 552 | ; Override for the default value of the SystemVerilog covergroup, 553 | ; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) 554 | ; NOTE: It does not override specific assignments in SystemVerilog 555 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" 556 | ; in the [vsim] section can override this value. 557 | ; SVCovergroupTypeGoalDefault = 100 558 | 559 | ; Specify the override for the default value of "strobe" option for the 560 | ; Covergroup Type. This is a compile time option which forces "strobe" to 561 | ; a user specified default value and supersedes SystemVerilog specified 562 | ; default value of '0'(zero). NOTE: This can be overriden by a runtime 563 | ; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. 564 | ; SVCovergroupStrobeDefault = 0 565 | 566 | ; Specify the override for the default value of "per_instance" option for the 567 | ; Covergroup variables. This is a compile time option which forces "per_instance" 568 | ; to a user specified default value and supersedes SystemVerilog specified 569 | ; default value of '0'(zero). 570 | ; SVCovergroupPerInstanceDefault = 0 571 | 572 | ; Specify the override for the default value of "get_inst_coverage" option for the 573 | ; Covergroup variables. This is a compile time option which forces 574 | ; "get_inst_coverage" to a user specified default value and supersedes 575 | ; SystemVerilog specified default value of '0'(zero). 576 | ; SVCovergroupGetInstCoverageDefault = 0 577 | 578 | ; 579 | ; A space separated list of resource libraries that contain precompiled 580 | ; packages. The behavior is identical to using the "-L" switch. 581 | ; 582 | ; LibrarySearchPath = [ ...] 583 | LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact 584 | 585 | ; The behavior is identical to the "-mixedansiports" switch. Default is off. 586 | ; MixedAnsiPorts = 1 587 | 588 | ; Enable SystemVerilog 3.1a $typeof() function. Default is off. 589 | ; EnableTypeOf = 1 590 | 591 | ; Only allow lower case pragmas. Default is disabled. 592 | ; AcceptLowerCasePragmaOnly = 1 593 | 594 | ; Set the maximum depth permitted for a recursive include file nesting. 595 | ; IncludeRecursionDepthMax = 5 596 | 597 | ; Turn ON detection of FSMs having single bit current state variable. 598 | ; FsmSingle = 1 599 | 600 | ; Turn off reset state transitions in FSM. 601 | ; FsmResetTrans = 0 602 | 603 | ; Turn off detections of FSMs having x-assignment. 604 | ; FsmXAssign = 0 605 | 606 | ; Turn ON detection of FSM Implicit Transitions. 607 | ; FsmImplicitTrans = 1 608 | 609 | ; List of file suffixes which will be read as SystemVerilog. White space 610 | ; in extensions can be specified with a back-slash: "\ ". Back-slashes 611 | ; can be specified with two consecutive back-slashes: "\\"; 612 | ; SvFileSuffixes = sv svp svh 613 | 614 | ; This setting is the same as the vlog -sv command line switch. 615 | ; Enables SystemVerilog features and keywords when true (1). 616 | ; When false (0), the rules of IEEE Std 1364-2001 are followed and 617 | ; SystemVerilog keywords are ignored. 618 | ; Svlog = 0 619 | 620 | ; Prints attribute placed upon SV packages during package import 621 | ; when true (1). The attribute will be ignored when this 622 | ; entry is false (0). The attribute name is "package_load_message". 623 | ; The value of this attribute is a string literal. 624 | ; Default is true (1). 625 | ; PrintSVPackageLoadingAttribute = 1 626 | 627 | ; Do not show immediate assertions with constant expressions in 628 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 629 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 630 | ; evaluation of immediate assertions. 631 | ; ShowConstantImmediateAsserts = 0 632 | 633 | ; Controls if untyped parameters that are initialized with values greater 634 | ; than 2147483647 are mapped to generics of type INTEGER or ignored. 635 | ; If mapped to VHDL Integers, values greater than 2147483647 636 | ; are mapped to negative values. 637 | ; Default is to map these parameter to generic of type INTEGER 638 | ; ForceUnsignedToVHDLInteger = 1 639 | 640 | ; Enable AMS wreal (wired real) extensions. Default is 0. 641 | ; WrealType = 1 642 | 643 | ; Controls SystemVerilog Language Extensions. These options enable 644 | ; some non-LRM compliant behavior. Valid extensions are: 645 | ; "acum", "atpi", "catx", "daoa", "feci", "fin0", "idcl", 646 | ; "iddp", "pae", "sccts", "spsl", "stop0", "udm0", and "uslt". 647 | ; SvExtensions = uslt,spsl,sccts 648 | 649 | ; Generate symbols debugging database in only some special cases to save on 650 | ; the number of files in the library. For other design-units, this database is 651 | ; generated on-demand in vsim. 652 | ; Default is to to generate debugging database for all design-units. 653 | ; SmartDbgSym = 1 654 | 655 | ; Controls how $unit library entries are named. Valid options are: 656 | ; "file" (generate name based on the first file on the command line) 657 | ; "du" (generate name based on first design unit following an item 658 | ; found in $unit scope) 659 | ; CUAutoName = file 660 | 661 | ; Enable or disable automatic creation of missing libraries. 662 | ; Default is 1 (enabled) 663 | ; CreateLib = 1 664 | 665 | [sccom] 666 | ; Enable use of SCV include files and library. Default is off. 667 | ; UseScv = 1 668 | 669 | ; Add C++ compiler options to the sccom command line by using this variable. 670 | ; CppOptions = -g 671 | 672 | ; Use custom C++ compiler located at this path rather than the default path. 673 | ; The path should point directly at a compiler executable. 674 | ; CppPath = /usr/bin/g++ 675 | 676 | ; Specify the compiler version from the list of support GNU compilers. 677 | ; examples 4.3.3, 4.5.0 678 | ; CppInstall = 4.5.0 679 | 680 | ; Enable verbose messages from sccom. Default is off. 681 | ; SccomVerbose = 1 682 | 683 | ; sccom logfile. Default is no logfile. 684 | ; SccomLogfile = sccom.log 685 | 686 | ; Enable use of SC_MS include files and library. Default is off. 687 | ; UseScMs = 1 688 | 689 | ; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. 690 | ; Sc22Mode = 1 691 | 692 | ; Enable compiler statistics. Specify one or more arguments: 693 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 694 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 695 | ; Stats = time,cmd,msg 696 | 697 | ; Enable or disable automatic creation of missing libraries. 698 | ; Default is 1 (enabled) 699 | ; CreateLib = 1 700 | 701 | [vopt] 702 | ; Turn on code coverage in vopt. Default is off. 703 | ; Coverage = sbceft 704 | 705 | ; Control compiler optimizations that are allowed when 706 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 707 | ; CoverOpt = 3 708 | 709 | ; Increase or decrease the maximum number of rows allowed in a UDP table 710 | ; implementing a VHDL condition coverage or expression coverage expression. 711 | ; More rows leads to a longer compile time, but more expressions covered. 712 | ; CoverMaxUDPRows = 192 713 | 714 | ; Increase or decrease the maximum number of input patterns that are present 715 | ; in FEC table. This leads to a longer compile time with more expressions 716 | ; covered with FEC metric. 717 | ; CoverMaxFECRows = 192 718 | 719 | ; Increase or decrease the limit on the size of expressions and conditions 720 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 721 | ; to higher compile, optimize and simulation time, but more expressions and 722 | ; conditions are considered for coverage in the design. FecUdpEffort can 723 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 724 | ; 1 - (low) Only small expressions and conditions considered for coverage. 725 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 726 | ; 3 - (high) Very large expressions and conditions considered for coverage. 727 | ; The default setting is 1 (low). 728 | ; FecUdpEffort = 1 729 | 730 | ; Enable code coverage reporting of code that has been optimized away. 731 | ; The default is not to report. 732 | ; CoverReportCancelled = 1 733 | 734 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 735 | ; Default is no deglitching. 736 | ; CoverDeglitchOn = 1 737 | 738 | ; Enable compiler statistics. Specify one or more arguments: 739 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 740 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 741 | ; Stats = time,cmd,msg 742 | 743 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 744 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 745 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 746 | ; CoverDeglitchPeriod = 0 747 | 748 | ; Do not show immediate assertions with constant expressions in 749 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 750 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 751 | ; evaluation of immediate assertions. 752 | ; ShowConstantImmediateAsserts = 0 753 | 754 | ; Set the maximum number of iterations permitted for a generate loop. 755 | ; Restricting this permits the implementation to recognize infinite 756 | ; generate loops. 757 | ; GenerateLoopIterationMax = 100000 758 | 759 | ; Set the maximum depth permitted for a recursive generate instantiation. 760 | ; Restricting this permits the implementation to recognize infinite 761 | ; recursions. 762 | ; GenerateRecursionDepthMax = 200 763 | 764 | ; Set the number of processes created during the code generation phase. 765 | ; By default a heuristic is used to set this value. This may be set to 0 766 | ; to disable this feature completely. 767 | ; ParallelJobs = 0 768 | 769 | ; Controls SystemVerilog Language Extensions. These options enable 770 | ; some non-LRM compliant behavior. Valid extensions are "feci", 771 | ; "pae", "uslt", "spsl", "fin0" and "sccts". 772 | ; SvExtensions = uslt,spsl,sccts 773 | 774 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 775 | ; This gives global visibility to all symbols in the shared objects, 776 | ; meaning that subsequently loaded shared objects can bind to symbols 777 | ; in the global shared objects. The list of shared objects should 778 | ; be whitespace delimited. This option is not supported on the 779 | ; Windows or AIX platforms. 780 | ; GlobalSharedObjectList = example1.so example2.so example3.so 781 | 782 | ; Disable SystemVerilog elaboration system task messages 783 | ; IgnoreSVAInfo = 1 784 | ; IgnoreSVAWarning = 1 785 | ; IgnoreSVAError = 1 786 | ; IgnoreSVAFatal = 1 787 | 788 | ; Enable or disable automatic creation of missing libraries. 789 | ; Default is 1 (enabled) 790 | ; CreateLib = 1 791 | 792 | 793 | [vsim] 794 | ; vopt flow 795 | ; Set to turn on automatic optimization of a design. 796 | ; Default is on 797 | VoptFlow = 1 798 | 799 | ; Simulator resolution 800 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. 801 | Resolution = ns 802 | 803 | ; Disable certain code coverage exclusions automatically. 804 | ; Assertions and FSM are exluded from the code coverage by default 805 | ; Set AutoExclusionsDisable = fsm to enable code coverage for fsm 806 | ; Set AutoExclusionsDisable = assertions to enable code coverage for assertions 807 | ; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions 808 | ; Or specify comma or space separated list 809 | ;AutoExclusionsDisable = fsm,assertions 810 | 811 | ; User time unit for run commands 812 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the 813 | ; unit specified for Resolution. For example, if Resolution is 100ps, 814 | ; then UserTimeUnit defaults to ps. 815 | ; Should generally be set to default. 816 | UserTimeUnit = default 817 | 818 | ; Default run length 819 | RunLength = 500 ns 820 | 821 | ; Maximum iterations that can be run without advancing simulation time 822 | IterationLimit = 10000000 823 | 824 | ; Specify libraries to be searched for precompiled modules 825 | ; LibrarySearchPath = [ ...] 826 | 827 | ; Set XPROP assertion fail limit. Default is 5. 828 | ; Any positive integer, -1 for infinity. 829 | ; XpropAssertionLimit = 5 830 | 831 | ; Control PSL and Verilog Assume directives during simulation 832 | ; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts 833 | ; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts 834 | ; SimulateAssumeDirectives = 1 835 | 836 | ; Control the simulation of PSL and SVA 837 | ; These switches can be overridden by the vsim command line switches: 838 | ; -psl, -nopsl, -sva, -nosva. 839 | ; Set SimulatePSL = 0 to disable PSL simulation 840 | ; Set SimulatePSL = 1 to enable PSL simulation (default) 841 | ; SimulatePSL = 1 842 | ; Set SimulateSVA = 0 to disable SVA simulation 843 | ; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) 844 | ; SimulateSVA = 1 845 | 846 | ; Control SVA and VHDL immediate assertion directives during simulation 847 | ; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts 848 | ; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts 849 | ; SimulateImmedAsserts = 1 850 | 851 | ; License feature mappings for Verilog and VHDL 852 | ; qhsimvh Single language VHDL license 853 | ; qhsimvl Single language Verilog license 854 | ; msimhdlsim Language neutral license for either Verilog or VHDL 855 | ; msimhdlmix Second language only, language neutral license for either 856 | ; Verilog or VHDL 857 | ; 858 | ; Directives to license manager can be set either as single value or as 859 | ; space separated multi-values: 860 | ; vhdl Immediately checkout and hold a VHDL license (i.e., one of 861 | ; qhsimvh, msimhdlsim, or msimhdlmix) 862 | ; vlog Immediately checkout and hold a Verilog license (i.e., one of 863 | ; qhsimvl, msimhdlsim, or msimhdlmix) 864 | ; plus Immediately checkout and hold a VHDL license and a Verilog license 865 | ; noqueue Do not wait in the license queue when a license is not available 866 | ; viewsim Try for viewer license but accept simulator license(s) instead 867 | ; of queuing for viewer license (PE ONLY) 868 | ; noviewer Disable checkout of msimviewer license feature (PE ONLY) 869 | ; noslvhdl Disable checkout of qhsimvh license feature 870 | ; noslvlog Disable checkout of qhsimvl license feature 871 | ; nomix Disable checkout of msimhdlmix license feature 872 | ; nolnl Disable checkout of msimhdlsim license feature 873 | ; mixedonly Disable checkout of qhsimvh and qhsimvl license features 874 | ; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features 875 | ; 876 | ; Examples (remove ";" comment character to activate licensing directives): 877 | ; Single directive: 878 | ; License = plus 879 | ; Multi-directive (Note: space delimited directives): 880 | ; License = noqueue plus 881 | 882 | ; Severity level of a VHDL assertion message or of a SystemVerilog severity system task 883 | ; which will cause a running simulation to stop. 884 | ; VHDL assertions and SystemVerilog severity system task that occur with the 885 | ; given severity or higher will cause a running simulation to stop. 886 | ; This value is ignored during elaboration. 887 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 888 | BreakOnAssertion = 3 889 | 890 | ; Severity level of a tool message which will cause a running simulation to 891 | ; stop. This value is ignored during elaboration. Default is to not break. 892 | ; 0 = Note 1 = Warning 2 = Error 3 = Fatal 893 | ;BreakOnMessage = 2 894 | 895 | ; The class debug feature enables more visibility and tracking of class instances 896 | ; during simulation. By default this feature is disabled (0). To enable this 897 | ; feature set ClassDebug to 1. 898 | ; ClassDebug = 1 899 | 900 | ; Message Format conversion specifications: 901 | ; %S - Severity Level of message/assertion 902 | ; %R - Text of message 903 | ; %T - Time of message 904 | ; %D - Delta value (iteration number) of Time 905 | ; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected 906 | ; %i - Instance/Region/Signal pathname with Process name (if available) 907 | ; %I - shorthand for one of these: 908 | ; " %K: %i" 909 | ; " %K: %i File: %F" (when path is not Process or Signal) 910 | ; except that the %i in this case does not report the Process name 911 | ; %O - Process name 912 | ; %P - Instance/Region path without leaf process 913 | ; %F - File name 914 | ; %L - Line number; if assertion message, then line number of assertion or, if 915 | ; assertion is in a subprogram, line from which the call is made 916 | ; %u - Design unit name in form library.primary 917 | ; %U - Design unit name in form library.primary(secondary) 918 | ; %% - The '%' character itself 919 | ; 920 | ; If specific format for Severity Level is defined, use that format. 921 | ; Else, for a message that occurs during elaboration: 922 | ; -- Failure/Fatal message in VHDL region that is not a Process, and in 923 | ; certain non-VHDL regions, uses MessageFormatBreakLine; 924 | ; -- Failure/Fatal message otherwise uses MessageFormatBreak; 925 | ; -- Note/Warning/Error message uses MessageFormat. 926 | ; Else, for a message that occurs during runtime and triggers a breakpoint because 927 | ; of the BreakOnAssertion setting: 928 | ; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; 929 | ; -- otherwise uses MessageFormatBreak. 930 | ; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. 931 | ; 932 | ; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" 933 | ; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" 934 | ; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 935 | ; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 936 | ; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 937 | ; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" 938 | ; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 939 | ; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" 940 | 941 | ; Error File - alternate file for storing error messages 942 | ; ErrorFile = error.log 943 | 944 | ; Simulation Breakpoint messages 945 | ; This flag controls the display of function names when reporting the location 946 | ; where the simulator stops because of a breakpoint or fatal error. 947 | ; Example with function name: # Break in Process ctr at counter.vhd line 44 948 | ; Example without function name: # Break at counter.vhd line 44 949 | ; Default value is 1. 950 | ShowFunctions = 1 951 | 952 | ; Default radix for all windows and commands. 953 | ; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned 954 | ; Flags may be one of: enumnumeric, showbase 955 | DefaultRadix = hexadecimal 956 | DefaultRadixFlags = showbase 957 | ; Set to 1 for make the signal_force VHDL and Verilog functions use the 958 | ; default radix when processing the force value. Prior to 10.2 signal_force 959 | ; used the default radix, now it always uses symbolic unless value explicitly indicates base 960 | ;SignalForceFunctionUseDefaultRadix = 0 961 | 962 | ; VSIM Startup command 963 | ; Startup = do startup.do 964 | 965 | ; VSIM Shutdown file 966 | ; Filename to save u/i formats and configurations. 967 | ; ShutdownFile = restart.do 968 | ; To explicitly disable auto save: 969 | ; ShutdownFile = --disable-auto-save 970 | 971 | ; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. 972 | ; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. 973 | ; BatchMode = 1 974 | 975 | ; File for saving command transcript when -batch option used 976 | ; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero 977 | ; default is unset so command transcript only goes to stdout for better performance 978 | ; BatchTranscriptFile = transcript 979 | 980 | ; File for saving command transcript, this option is ignored when -batch option is used 981 | TranscriptFile = transcript 982 | 983 | ; File for saving command history 984 | ; CommandHistory = cmdhist.log 985 | 986 | ; Specify whether paths in simulator commands should be described 987 | ; in VHDL or Verilog format. 988 | ; For VHDL, PathSeparator = / 989 | ; For Verilog, PathSeparator = . 990 | ; Must not be the same character as DatasetSeparator. 991 | PathSeparator = / 992 | 993 | ; Specify the dataset separator for fully rooted contexts. 994 | ; The default is ':'. For example: sim:/top 995 | ; Must not be the same character as PathSeparator. 996 | DatasetSeparator = : 997 | 998 | ; Specify a unique path separator for the Signal Spy set of functions. 999 | ; The default will be to use the PathSeparator variable. 1000 | ; Must not be the same character as DatasetSeparator. 1001 | ; SignalSpyPathSeparator = / 1002 | 1003 | ; Used to control parsing of HDL identifiers input to the tool. 1004 | ; This includes CLI commands, vsim/vopt/vlog/vcom options, 1005 | ; string arguments to FLI/VPI/DPI calls, etc. 1006 | ; If set to 1, accept either Verilog escaped Id syntax or 1007 | ; VHDL extended id syntax, regardless of source language. 1008 | ; If set to 0, the syntax of the source language must be used. 1009 | ; Each identifier in a hierarchical name may need different syntax, 1010 | ; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or 1011 | ; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" 1012 | ; GenerousIdentifierParsing = 1 1013 | 1014 | ; Disable VHDL assertion messages 1015 | ; IgnoreNote = 1 1016 | ; IgnoreWarning = 1 1017 | ; IgnoreError = 1 1018 | ; IgnoreFailure = 1 1019 | 1020 | ; Disable SystemVerilog assertion messages 1021 | ; IgnoreSVAInfo = 1 1022 | ; IgnoreSVAWarning = 1 1023 | ; IgnoreSVAError = 1 1024 | ; IgnoreSVAFatal = 1 1025 | 1026 | ; Do not print any additional information from Severity System tasks. 1027 | ; Only the message provided by the user is printed along with severity 1028 | ; information. 1029 | ; SVAPrintOnlyUserMessage = 1; 1030 | 1031 | ; Default force kind. May be freeze, drive, deposit, or default 1032 | ; or in other terms, fixed, wired, or charged. 1033 | ; A value of "default" will use the signal kind to determine the 1034 | ; force kind, drive for resolved signals, freeze for unresolved signals 1035 | ; DefaultForceKind = freeze 1036 | 1037 | ; Control the iteration of events when a VHDL signal is forced to a value 1038 | ; This flag can be set to honour the signal update event in next iteration, 1039 | ; the default is to update and propagate in the same iteration. 1040 | ; ForceSigNextIter = 1 1041 | 1042 | ; Enable simulation statistics. Specify one or more arguments: 1043 | ; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] 1044 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 1045 | ; Stats = time,cmd,msg 1046 | 1047 | ; If zero, open files when elaborated; otherwise, open files on 1048 | ; first read or write. Default is 0. 1049 | ; DelayFileOpen = 1 1050 | 1051 | ; Control VHDL files opened for write. 1052 | ; 0 = Buffered, 1 = Unbuffered 1053 | UnbufferedOutput = 0 1054 | 1055 | ; Control the number of VHDL files open concurrently. 1056 | ; This number should always be less than the current ulimit 1057 | ; setting for max file descriptors. 1058 | ; 0 = unlimited 1059 | ConcurrentFileLimit = 40 1060 | 1061 | ; If nonzero, close files as soon as there is either an explicit call to 1062 | ; file_close, or when the file variable's scope is closed. When zero, a 1063 | ; file opened in append mode is not closed in case it is immediately 1064 | ; reopened in append mode; otherwise, the file will be closed at the 1065 | ; point it is reopened. 1066 | ; AppendClose = 1 1067 | 1068 | ; Control the number of hierarchical regions displayed as 1069 | ; part of a signal name shown in the Wave window. 1070 | ; A value of zero tells VSIM to display the full name. 1071 | ; The default is 0. 1072 | ; WaveSignalNameWidth = 0 1073 | 1074 | ; Turn off warnings when changing VHDL constants and generics 1075 | ; Default is 1 to generate warning messages 1076 | ; WarnConstantChange = 0 1077 | 1078 | ; Turn off warnings from accelerated versions of the std_logic_arith, 1079 | ; std_logic_unsigned, and std_logic_signed packages. 1080 | ; StdArithNoWarnings = 1 1081 | 1082 | ; Turn off warnings from accelerated versions of the IEEE numeric_std 1083 | ; and numeric_bit packages. 1084 | ; NumericStdNoWarnings = 1 1085 | 1086 | ; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names 1087 | ; in the design hierarchy. 1088 | ; This style is controlled by the value of the GenerateFormat 1089 | ; value described next. Default is to use new-style names, which 1090 | ; comprise the generate statement label, '(', the value of the generate 1091 | ; parameter, and a closing ')'. 1092 | ; Set this to 1 to use old-style names. 1093 | ; OldVhdlForGenNames = 1 1094 | 1095 | ; Control the format of the old-style VHDL FOR generate statement region 1096 | ; name for each iteration. Do not quote the value. 1097 | ; The format string here must contain the conversion codes %s and %d, 1098 | ; in that order, and no other conversion codes. The %s represents 1099 | ; the generate statement label; the %d represents the generate parameter value 1100 | ; at a particular iteration (this is the position number if the generate parameter 1101 | ; is of an enumeration type). Embedded whitespace is allowed (but discouraged); 1102 | ; leading and trailing whitespace is ignored. 1103 | ; Application of the format must result in a unique region name over all 1104 | ; loop iterations for a particular immediately enclosing scope so that name 1105 | ; lookup can function properly. The default is %s__%d. 1106 | ; GenerateFormat = %s__%d 1107 | 1108 | ; Enable more efficient logging of VHDL Variables. 1109 | ; Logging VHDL variables without this enabled, while possible, is very 1110 | ; inefficient. Enabling this will provide a more efficient logging methodology 1111 | ; at the expense of more memory usage. By default this feature is disabled (0). 1112 | ; To enabled this feature, set this variable to 1. 1113 | ; VhdlVariableLogging = 1 1114 | 1115 | ; Enable logging of VHDL access type variables and their designated objects. 1116 | ; This setting will allow both variables of an access type ("access variables") 1117 | ; and their designated objects ("access objects") to be logged. Logging a 1118 | ; variable of an access type will automatically also cause the designated 1119 | ; object(s) of that variable to be logged as the simulation progresses. 1120 | ; Further, enabling this allows access objects to be logged by name. By default 1121 | ; this feature is disabled (0). To enable this feature, set this variable to 1. 1122 | ; Enabling this will automatically enable the VhdlVariableLogging feature also. 1123 | ; AccessObjDebug = 1 1124 | 1125 | ; Make each VHDL package in a PDU has its own separate copy of the package instead 1126 | ; of sharing the package between PDUs. The default is to share packages. 1127 | ; To ensure that each PDU has its own set of packages, set this variable to 1. 1128 | ; VhdlSeparatePduPackage = 1 1129 | 1130 | ; Specify whether checkpoint files should be compressed. 1131 | ; The default is 1 (compressed). 1132 | ; CheckpointCompressMode = 0 1133 | 1134 | ; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. 1135 | ; Use custom gcc compiler located at this path rather than the default path. 1136 | ; The path should point directly at a compiler executable. 1137 | ; DpiCppPath = /bin/gcc 1138 | 1139 | ; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. 1140 | ; The term "out-of-the-blue" refers to SystemVerilog export function calls 1141 | ; made from C functions that don't have the proper context setup 1142 | ; (as is the case when running under "DPI-C" import functions). 1143 | ; When this is enabled, one can call a DPI export function 1144 | ; (but not task) from any C code. 1145 | ; the setting of this variable can be one of the following values: 1146 | ; 0 : dpioutoftheblue call is disabled (default) 1147 | ; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. 1148 | ; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. 1149 | ; DpiOutOfTheBlue = 1 1150 | 1151 | ; Specify whether continuous assignments are run before other normal priority 1152 | ; processes scheduled in the same iteration. This event ordering minimizes race 1153 | ; differences between optimized and non-optimized designs, and is the default 1154 | ; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set 1155 | ; ImmediateContinuousAssign to 0. 1156 | ; The default is 1 (enabled). 1157 | ; ImmediateContinuousAssign = 0 1158 | 1159 | ; List of dynamically loaded objects for Verilog PLI applications 1160 | ; Veriuser = veriuser.sl 1161 | 1162 | ; Which default VPI object model should the tool conform to? 1163 | ; The 1364 modes are Verilog-only, for backwards compatibility with older 1164 | ; libraries, and SystemVerilog objects are not available in these modes. 1165 | ; 1166 | ; In the absence of a user-specified default, the tool default is the 1167 | ; latest available LRM behavior. 1168 | ; Options for PliCompatDefault are: 1169 | ; VPI_COMPATIBILITY_VERSION_1364v1995 1170 | ; VPI_COMPATIBILITY_VERSION_1364v2001 1171 | ; VPI_COMPATIBILITY_VERSION_1364v2005 1172 | ; VPI_COMPATIBILITY_VERSION_1800v2005 1173 | ; VPI_COMPATIBILITY_VERSION_1800v2008 1174 | ; 1175 | ; Synonyms for each string are also recognized: 1176 | ; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) 1177 | ; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) 1178 | ; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) 1179 | ; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) 1180 | ; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) 1181 | 1182 | 1183 | ; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 1184 | 1185 | ; Specify whether the Verilog system task $fopen or vpi_mcd_open() 1186 | ; will create directories that do not exist when opening the file 1187 | ; in "a" or "w" mode. 1188 | ; The default is 0 (do not create non-existent directories) 1189 | ; CreateDirForFileAccess = 1 1190 | 1191 | ; Specify default options for the restart command. Options can be one 1192 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions 1193 | ; DefaultRestartOptions = -force 1194 | 1195 | 1196 | ; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. 1197 | ; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe. 1198 | ; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". 1199 | ; The list of options must be delimited by commas, without spaces or tabs. 1200 | ; The default is UVMControl = struct 1201 | 1202 | ; Some examples 1203 | ; To turn on all available UVM-aware debug features: 1204 | ; UVMControl = all 1205 | ; To turn on the struct window, mesage logging, and transaction logging: 1206 | ; UVMControl = struct,msglog,trlog 1207 | ; To turn on all options except certe: 1208 | ; UVMControl = all,-certe 1209 | ; To completely disable all UVM-aware debug functionality: 1210 | ; UVMControl = disable 1211 | 1212 | ; Specify the WildcardFilter setting. 1213 | ; A space separated list of object types to be excluded when performing 1214 | ; wildcard matches with log, wave, etc commands. The default value for this variable is: 1215 | ; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" 1216 | ; See "Using the WildcardFilter Preference Variable" in the documentation for 1217 | ; details on how to use this variable and for descriptions of the filter types. 1218 | WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile 1219 | 1220 | ; Specify the WildcardSizeThreshold setting. 1221 | ; This integer setting specifies the size at which objects will be excluded when 1222 | ; performing wildcard matches with log, wave, etc commands. Objects of size equal 1223 | ; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard 1224 | ; matches. The size is a simple calculation of number of bits or items in the object. 1225 | ; The default value is 8k (8192). Setting this value to 0 will disable the checking 1226 | ; of object size against this threshold and allow all objects of any size to be logged. 1227 | WildcardSizeThreshold = 8192 1228 | 1229 | ; Specify whether warning messages are output when objects are filtered out due to the 1230 | ; WildcardSizeThreshold. The default is 0 (no messages generated). 1231 | WildcardSizeThresholdVerbose = 0 1232 | 1233 | ; Turn on (1) or off (0) WLF file compression. 1234 | ; The default is 1 (compress WLF file). 1235 | ; WLFCompress = 0 1236 | 1237 | ; Specify whether to save all design hierarchy (1) in the WLF file 1238 | ; or only regions containing logged signals (0). 1239 | ; The default is 0 (save only regions with logged signals). 1240 | ; WLFSaveAllRegions = 1 1241 | 1242 | ; WLF file time limit. Limit WLF file by time, as closely as possible, 1243 | ; to the specified amount of simulation time. When the limit is exceeded 1244 | ; the earliest times get truncated from the file. 1245 | ; If both time and size limits are specified the most restrictive is used. 1246 | ; UserTimeUnits are used if time units are not specified. 1247 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} 1248 | ; WLFTimeLimit = 0 1249 | 1250 | ; WLF file size limit. Limit WLF file size, as closely as possible, 1251 | ; to the specified number of megabytes. If both time and size limits 1252 | ; are specified then the most restrictive is used. 1253 | ; The default is 0 (no limit). 1254 | ; WLFSizeLimit = 1000 1255 | 1256 | ; Specify whether or not a WLF file should be deleted when the 1257 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. 1258 | ; The default is 0 (do not delete WLF file when simulation ends). 1259 | ; WLFDeleteOnQuit = 1 1260 | 1261 | ; Specify whether or not a WLF file should be optimized during 1262 | ; simulation. If set to 0, the WLF file will not be optimized. 1263 | ; The default is 1, optimize the WLF file. 1264 | ; WLFOptimize = 0 1265 | 1266 | ; Specify the name of the WLF file. 1267 | ; The default is vsim.wlf 1268 | ; WLFFilename = vsim.wlf 1269 | 1270 | ; Specify whether to lock the WLF file. 1271 | ; Locking the file prevents other invocations of ModelSim/Questa tools from 1272 | ; inadvertently overwriting the WLF file. 1273 | ; The default is 1, lock the WLF file. 1274 | ; WLFFileLock = 0 1275 | 1276 | ; Specify the update interval for the WLF file in live simulation. 1277 | ; The interval is given in seconds. 1278 | ; The value is the smallest interval between WLF file updates. The WLF file 1279 | ; will be flushed (updated) after (at least) the interval has elapsed, ensuring 1280 | ; that the data is correct when viewed from a separate viewer. 1281 | ; A value of 0 means that no updating will occur. 1282 | ; The default value is 10 seconds. 1283 | ; WLFUpdateInterval = 10 1284 | 1285 | ; Specify the WLF cache size limit for WLF files. 1286 | ; The value is given in megabytes. A value of 0 turns off the cache. 1287 | ; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). 1288 | ; On Windows, the default value is 1000 (megabytes) to help to avoid filling 1289 | ; process memory. 1290 | ; WLFSimCacheSize allows a different cache size to be set for a live simulation 1291 | ; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize 1292 | ; is not set, it defaults to the WLFCacheSize value. 1293 | ; WLFCacheSize = 2000 1294 | ; WLFSimCacheSize = 500 1295 | 1296 | ; Specify the WLF file event collapse mode. 1297 | ; 0 = Preserve all events and event order. (same as -wlfnocollapse) 1298 | ; 1 = Only record values of logged objects at the end of a simulator iteration. 1299 | ; (same as -wlfcollapsedelta) 1300 | ; 2 = Only record values of logged objects at the end of a simulator time step. 1301 | ; (same as -wlfcollapsetime) 1302 | ; The default is 1. 1303 | ; WLFCollapseMode = 0 1304 | 1305 | ; Specify whether WLF file logging can use threads on multi-processor machines. 1306 | ; If 0, no threads will be used; if 1, threads will be used if the system has 1307 | ; more than one processor. 1308 | ; WLFUseThreads = 1 1309 | 1310 | ; Specify the size of objects that will trigger "large object" messages 1311 | ; at log/wave/list time. The size calculation of the object is the same as that 1312 | ; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. 1313 | ; Setting LargeObjectSize to 0 will disable these messages. 1314 | ; LargeObjectSize = 500000 1315 | 1316 | ; Specify the depth of stack frames returned by $stacktrace([level]). 1317 | ; This depth will be picked up when the optional 'level' argument 1318 | ; is not specified or its value is not a positive integer. 1319 | ; StackTraceDepth = 100 1320 | 1321 | ; Turn on/off undebuggable SystemC type warnings. Default is on. 1322 | ; ShowUndebuggableScTypeWarning = 0 1323 | 1324 | ; Turn on/off unassociated SystemC name warnings. Default is off. 1325 | ; ShowUnassociatedScNameWarning = 1 1326 | 1327 | ; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. 1328 | ; ScShowIeeeDeprecationWarnings = 1 1329 | 1330 | ; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. 1331 | ; ScEnableScSignalWriteCheck = 1 1332 | 1333 | ; Set SystemC default time unit. 1334 | ; Set to fs, ps, ns, us, ms, or sec with optional 1335 | ; prefix of 1, 10, or 100. The default is 1 ns. 1336 | ; The ScTimeUnit value is honored if it is coarser than Resolution. 1337 | ; If ScTimeUnit is finer than Resolution, it is set to the value 1338 | ; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, 1339 | ; then the default time unit will be 1 ns. However if Resolution 1340 | ; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. 1341 | ScTimeUnit = ns 1342 | 1343 | ; Set SystemC sc_main stack size. The stack size is set as an integer 1344 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1345 | ; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends 1346 | ; on the amount of data on the sc_main() stack and the memory required 1347 | ; to succesfully execute the longest function call chain of sc_main(). 1348 | ScMainStackSize = 10 Mb 1349 | 1350 | ; Set SystemC thread stack size. The stack size is set as an integer 1351 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1352 | ; Gb(Giga-byte). The stack size for sc_thread depends 1353 | ; on the amount of data on the sc_thread stack and the memory required 1354 | ; to succesfully execute the thread. 1355 | ; ScStackSize = 1 Mb 1356 | 1357 | ; Turn on/off execution of remainder of sc_main upon quitting the current 1358 | ; simulation session. If the cumulative length of sc_main() in terms of 1359 | ; simulation time units is less than the length of the current simulation 1360 | ; run upon quit or restart, sc_main() will be in the middle of execution. 1361 | ; This switch gives the option to execute the remainder of sc_main upon 1362 | ; quitting simulation. The drawback of not running sc_main till the end 1363 | ; is memory leaks for objects created by sc_main. If on, the remainder of 1364 | ; sc_main will be executed ignoring all delays. This may cause the simulator 1365 | ; to crash if the code in sc_main is dependent on some simulation state. 1366 | ; Default is on. 1367 | ScMainFinishOnQuit = 1 1368 | 1369 | ; Set the SCV relationship name that will be used to identify phase 1370 | ; relations. If the name given to a transactor relation matches this 1371 | ; name, the transactions involved will be treated as phase transactions 1372 | ScvPhaseRelationName = mti_phase 1373 | 1374 | ; Customize the vsim kernel shutdown behavior at the end of the simulation. 1375 | ; Some common causes of the end of simulation are $finish (implicit or explicit), 1376 | ; sc_stop(), tf_dofinish(), and assertion failures. 1377 | ; This should be set to "ask", "exit", or "stop". The default is "ask". 1378 | ; "ask" -- In batch mode, the vsim kernel will abruptly exit. 1379 | ; In GUI mode, a dialog box will pop up and ask for user confirmation 1380 | ; whether or not to quit the simulation. 1381 | ; "stop" -- Cause the simulation to stay loaded in memory. This can make some 1382 | ; post-simulation tasks easier. 1383 | ; "exit" -- The simulation will abruptly exit without asking for any confirmation. 1384 | ; "final" -- Run SystemVerilog final blocks then behave as "stop". 1385 | ; Note: This variable can be overridden with the vsim "-onfinish" command line switch. 1386 | OnFinish = ask 1387 | 1388 | ; Print pending deferred assertion messages. 1389 | ; Deferred assertion messages may be scheduled after the $finish in the same 1390 | ; time step. Deferred assertions scheduled to print after the $finish are 1391 | ; printed before exiting with severity level NOTE since it's not known whether 1392 | ; the assertion is still valid due to being printed in the active region 1393 | ; instead of the reactive region where they are normally printed. 1394 | ; OnFinishPendingAssert = 1; 1395 | 1396 | ; Print "simstats" result. Default is 0. 1397 | ; 0 == do not print simstats 1398 | ; 1 == print at end of simulation 1399 | ; 2 == print at end of each run command and end of simulation 1400 | ; PrintSimStats = 1 1401 | 1402 | ; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages 1403 | ; AssertFile = assert.log 1404 | 1405 | ; Enable assertion counts. Default is off. 1406 | ; AssertionCover = 1 1407 | 1408 | ; Run simulator in assertion debug mode. Default is off. 1409 | ; AssertionDebug = 1 1410 | 1411 | ; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. 1412 | ; AssertionEnable = 0 1413 | 1414 | ; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. 1415 | ; Any positive integer, -1 for infinity. 1416 | ; AssertionLimit = 1 1417 | 1418 | ; Turn on/off concurrent assertion pass log. Default is off. 1419 | ; Assertion pass logging is only enabled when assertion is browseable 1420 | ; and assertion debug is enabled. 1421 | ; AssertionPassLog = 1 1422 | 1423 | ; Turn on/off PSL concurrent assertion fail log. Default is on. 1424 | ; The flag does not affect SVA 1425 | ; AssertionFailLog = 0 1426 | 1427 | ; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. 1428 | ; AssertionFailLocalVarLog = 0 1429 | 1430 | ; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. 1431 | ; 0 = Continue 1 = Break 2 = Exit 1432 | ; AssertionFailAction = 1 1433 | 1434 | ; Enable the active thread monitor in the waveform display when assertion debug is enabled. 1435 | ; AssertionActiveThreadMonitor = 1 1436 | 1437 | ; Control how many waveform rows will be used for displaying the active threads. Default is 5. 1438 | ; AssertionActiveThreadMonitorLimit = 5 1439 | 1440 | ; Assertion thread limit after which assertion would be killed/switched off. 1441 | ; The default is -1 (unlimited). If the number of threads for an assertion go 1442 | ; beyond this limit, the assertion would be either switched off or killed. This 1443 | ; limit applies to only assert directives. 1444 | ;AssertionThreadLimit = -1 1445 | 1446 | ; Action to be taken once the assertion thread limit is reached. Default 1447 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1448 | ; threads are terminated and no new attempts are started. In case of off, the 1449 | ; existing attempts keep on evaluating but no new attempts are started. This 1450 | ; variable applies to only assert directives. 1451 | ;AssertionThreadLimitAction = kill 1452 | 1453 | ; Cover thread limit after which cover would be killed/switched off. 1454 | ; The default is -1 (unlimited). If the number of threads for a cover go 1455 | ; beyond this limit, the cover would be either switched off or killed. This 1456 | ; limit applies to only cover directives. 1457 | ;CoverThreadLimit = -1 1458 | 1459 | ; Action to be taken once the cover thread limit is reached. Default 1460 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1461 | ; threads are terminated and no new attempts are started. In case of off, the 1462 | ; existing attempts keep on evaluating but no new attempts are started. This 1463 | ; variable applies to only cover directives. 1464 | ;CoverThreadLimitAction = kill 1465 | 1466 | 1467 | ; By default immediate assertions do not participate in Assertion Coverage calculations 1468 | ; unless they are executed. This switch causes all immediate assertions in the design 1469 | ; to participate in Assertion Coverage calculations, whether attempted or not. 1470 | ; UnattemptedImmediateAssertions = 0 1471 | 1472 | ; By default immediate covers participate in Coverage calculations 1473 | ; whether they are attempted or not. This switch causes all unattempted 1474 | ; immediate covers in the design to stop participating in Coverage 1475 | ; calculations. 1476 | ; UnattemptedImmediateCovers = 0 1477 | 1478 | ; By default pass action block is not executed for assertions on vacuous 1479 | ; success. The following variable is provided to enable execution of 1480 | ; pass action block on vacuous success. The following variable is only effective 1481 | ; if the user does not disable pass action block execution by using either 1482 | ; system tasks or CLI. Also there is a performance penalty for enabling 1483 | ; the following variable. 1484 | ;AssertionEnableVacuousPassActionBlock = 1 1485 | 1486 | ; As per strict 1850-2005 PSL LRM, an always property can either pass 1487 | ; or fail. However, by default, Questa reports multiple passes and 1488 | ; multiple fails on top always/never property (always/never operator 1489 | ; is the top operator under Verification Directive). The reason 1490 | ; being that Questa reports passes and fails on per attempt of the 1491 | ; top always/never property. Use the following flag to instruct 1492 | ; Questa to strictly follow LRM. With this flag, all assert/never 1493 | ; directives will start an attempt once at start of simulation. 1494 | ; The attempt can either fail, match or match vacuously. 1495 | ; For e.g. if always is the top operator under assert, the always will 1496 | ; keep on checking the property at every clock. If the property under 1497 | ; always fails, the directive will be considered failed and no more 1498 | ; checking will be done for that directive. A top always property, 1499 | ; if it does not fail, will show a pass at end of simulation. 1500 | ; The default value is '0' (i.e. zero is off). For example: 1501 | ; PslOneAttempt = 1 1502 | 1503 | ; Specify the number of clock ticks to represent infinite clock ticks. 1504 | ; This affects eventually!, until! and until_!. If at End of Simulation 1505 | ; (EOS) an active strong-property has not clocked this number of 1506 | ; clock ticks then neither pass or fail (vacuous match) is returned 1507 | ; else respective fail/pass is returned. The default value is '0' (zero) 1508 | ; which effectively does not check for clock tick condition. For example: 1509 | ; PslInfinityThreshold = 5000 1510 | 1511 | ; Control how many thread start times will be preserved for ATV viewing for a given assertion 1512 | ; instance. Default is -1 (ALL). 1513 | ; ATVStartTimeKeepCount = -1 1514 | 1515 | ; Turn on/off code coverage 1516 | ; CodeCoverage = 0 1517 | 1518 | ; This option applies to condition and expression coverage UDP tables. It 1519 | ; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. 1520 | ; If this option is used and a match occurs in more than one row in the UDP table, 1521 | ; none of the counts for all matching rows is incremented. By default, counts are 1522 | ; incremented for all matching rows. 1523 | ; CoverCountAll = 1 1524 | 1525 | ; Turn off automatic inclusion of VHDL integers in toggle coverage. Default 1526 | ; is to include them. 1527 | ; ToggleNoIntegers = 1 1528 | 1529 | ; Set the maximum number of values that are collected for toggle coverage of 1530 | ; VHDL integers. Default is 100; 1531 | ; ToggleMaxIntValues = 100 1532 | 1533 | ; Set the maximum number of values that are collected for toggle coverage of 1534 | ; Verilog real. Default is 100; 1535 | ; ToggleMaxRealValues = 100 1536 | 1537 | ; Turn on automatic inclusion of Verilog integers in toggle coverage, except 1538 | ; for enumeration types. Default is to include them. 1539 | ; ToggleVlogIntegers = 0 1540 | 1541 | ; Turn on automatic inclusion of Verilog real type in toggle coverage, except 1542 | ; for shortreal types. Default is to not include them. 1543 | ; ToggleVlogReal = 1 1544 | 1545 | ; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays 1546 | ; and VHDL arrays-of-arrays in toggle coverage. 1547 | ; Default is to not include them. 1548 | ; ToggleFixedSizeArray = 1 1549 | 1550 | ; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, 1551 | ; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. 1552 | ; This leads to a longer simulation time with bigger arrays covered with toggle coverage. 1553 | ; Default is 1024. 1554 | ; ToggleMaxFixedSizeArray = 1024 1555 | 1556 | ; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized 1557 | ; one-dimensional packed vectors for toggle coverage. Default is 0. 1558 | ; TogglePackedAsVec = 0 1559 | 1560 | ; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for 1561 | ; toggle coverage. Default is 0. 1562 | ; ToggleVlogEnumBits = 0 1563 | 1564 | ; Turn off automatic inclusion of VHDL records in toggle coverage. 1565 | ; Default is to include them. 1566 | ; ToggleVHDLRecords = 0 1567 | 1568 | ; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. 1569 | ; For unlimited width, set to 0. 1570 | ; ToggleWidthLimit = 128 1571 | 1572 | ; Limit the counts that are tracked for toggle coverage. When all edges for a bit have 1573 | ; reached this count, further activity on the bit is ignored. Default is 1. 1574 | ; For unlimited counts, set to 0. 1575 | ; ToggleCountLimit = 1 1576 | 1577 | ; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. 1578 | ; Following is the toggle coverage calculation criteria based on extended toggle mode: 1579 | ; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). 1580 | ; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. 1581 | ; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. 1582 | ; ExtendedToggleMode = 3 1583 | 1584 | ; Enable toggle statistics collection only for ports. Default is 0. 1585 | ; TogglePortsOnly = 1 1586 | 1587 | ; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has 1588 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1589 | ; Default is 1. For unlimited counts, set to 0. 1590 | ; NOTE: Changing this value from its default value may affect simulation performance. 1591 | ; FecCountLimit = 1 1592 | 1593 | ; Limit the counts that are tracked for UDP Coverage. When a bin has 1594 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1595 | ; Default is 1. For unlimited counts, set to 0. 1596 | ; NOTE: Changing this value from its default value may affect simulation performance. 1597 | ; UdpCountLimit = 1 1598 | 1599 | ; Control toggle coverage deglitching period. A period of 0, eliminates delta 1600 | ; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either 1601 | ; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 1602 | ; ToggleDeglitchPeriod = 10.0ps 1603 | 1604 | ; Turn on/off all PSL/SVA cover directive enables. Default is on. 1605 | ; CoverEnable = 0 1606 | 1607 | ; Turn on/off PSL/SVA cover log. Default is off "0". 1608 | ; CoverLog = 1 1609 | 1610 | ; Set "at_least" value for all PSL/SVA cover directives. Default is 1. 1611 | ; CoverAtLeast = 2 1612 | 1613 | ; Set "limit" value for all PSL/SVA cover directives. Default is -1. 1614 | ; Any positive integer, -1 for infinity. 1615 | ; CoverLimit = 1 1616 | 1617 | ; Specify the coverage database filename. 1618 | ; Default is "" (i.e. database is NOT automatically saved on close). 1619 | ; UCDBFilename = vsim.ucdb 1620 | 1621 | ; Specify the maximum limit for the number of Cross (bin) products reported 1622 | ; in XML and UCDB report against a Cross. A warning is issued if the limit 1623 | ; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this 1624 | ; setting. 1625 | ; MaxReportRhsSVCrossProducts = 1000 1626 | 1627 | ; Specify the override for the "auto_bin_max" option for the Covergroups. 1628 | ; If not specified then value from Covergroup "option" is used. 1629 | ; SVCoverpointAutoBinMax = 64 1630 | 1631 | ; Specify the override for the value of "cross_num_print_missing" 1632 | ; option for the Cross in Covergroups. If not specified then value 1633 | ; specified in the "option.cross_num_print_missing" is used. This 1634 | ; is a runtime option. NOTE: This overrides any "cross_num_print_missing" 1635 | ; value specified by user in source file and any SVCrossNumPrintMissingDefault 1636 | ; specified in modelsim.ini. 1637 | ; SVCrossNumPrintMissing = 0 1638 | 1639 | ; Specify whether to use the value of "cross_num_print_missing" 1640 | ; option in report and GUI for the Cross in Covergroups. If not specified then 1641 | ; cross_num_print_missing is ignored for creating reports and displaying 1642 | ; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". 1643 | ; UseSVCrossNumPrintMissing = 0 1644 | 1645 | ; Specify the threshold of Coverpoint wildcard bin value range size, above which 1646 | ; a warning will be triggered. The default is 4K -- 12 wildcard bits. 1647 | ; SVCoverpointWildCardBinValueSizeWarn = 4096 1648 | 1649 | ; Specify the override for the value of "strobe" option for the 1650 | ; Covergroup Type. If not specified then value in "type_option.strobe" 1651 | ; will be used. This is runtime option which forces "strobe" to 1652 | ; user specified value and supersedes user specified values in the 1653 | ; SystemVerilog Code. NOTE: This also overrides the compile time 1654 | ; default value override specified using "SVCovergroupStrobeDefault" 1655 | ; SVCovergroupStrobe = 0 1656 | 1657 | ; Override for explicit assignments in source code to "option.goal" of 1658 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1659 | ; default value of "option.goal" (defined to be 100 in the SystemVerilog 1660 | ; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". 1661 | ; SVCovergroupGoal = 100 1662 | 1663 | ; Override for explicit assignments in source code to "type_option.goal" of 1664 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1665 | ; default value of "type_option.goal" (defined to be 100 in the SystemVerilog 1666 | ; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". 1667 | ; SVCovergroupTypeGoal = 100 1668 | 1669 | ; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() 1670 | ; builtin functions, and report. This setting changes the default values of 1671 | ; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 1672 | ; behavior if explicit assignments are not made on option.get_inst_coverage and 1673 | ; type_option.merge_instances by the user. There are two vsim command line 1674 | ; options, -cvg63 and -nocvg63 to override this setting from vsim command line. 1675 | ; The default value of this variable from release 6.6 onwards is 0. This default 1676 | ; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. 1677 | ; SVCovergroup63Compatibility = 0 1678 | 1679 | ; Enforce the default behavior of covergroup get_coverage() builtin function, GUI 1680 | ; and report. This variable sets the default value of type_option.merge_instances. 1681 | ; There are two vsim command line options, -cvgmergeinstances and 1682 | ; -nocvgmergeinstances to override this setting from vsim command line. 1683 | ; The default value of this variable is 0. This default 1684 | ; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. 1685 | ; SVCovergroupMergeInstancesDefault = 0 1686 | 1687 | ; Enable or disable generation of more detailed information about the sampling 1688 | ; of covergroup, cross, and coverpoints. It provides the details of the number 1689 | ; of times the covergroup instance and type were sampled, as well as details 1690 | ; about why covergroup, cross and coverpoint were not covered. A non-zero value 1691 | ; is to enable this feature. 0 is to disable this feature. Default is 0 1692 | ; SVCovergroupSampleInfo = 0 1693 | 1694 | ; Specify the maximum number of Coverpoint bins in whole design for 1695 | ; all Covergroups. 1696 | ; MaxSVCoverpointBinsDesign = 2147483648 1697 | 1698 | ; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins 1699 | ; MaxSVCoverpointBinsInst = 1048576 1700 | 1701 | ; Specify the maximum number of Cross bins in whole design for 1702 | ; all Covergroups. 1703 | ; MaxSVCrossBinsDesign = 2147483648 1704 | 1705 | ; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins 1706 | ; MaxSVCrossBinsInst = 67108864 1707 | 1708 | ; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. 1709 | ; By default, this variable is set 0, in which case option.no_collect setting will take effect. 1710 | ; If this variable is set to 1, all zero-weight coverage items will not be saved. 1711 | ; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting 1712 | ; of this variable. 1713 | ; CvgZWNoCollect = 1 1714 | 1715 | ; Specify a space delimited list of double quoted TCL style 1716 | ; regular expressions which will be matched against the text of all messages. 1717 | ; If any regular expression is found to be contained within any message, the 1718 | ; status for that message will not be propagated to the UCDB TESTSTATUS. 1719 | ; If no match is detected, then the status will be propagated to the 1720 | ; UCDB TESTSTATUS. More than one such regular expression text is allowed, 1721 | ; and each message text is compared for each regular expression in the list. 1722 | ; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" 1723 | 1724 | ; Set weight for all PSL/SVA cover directives. Default is 1. 1725 | ; CoverWeight = 2 1726 | 1727 | ; Check vsim plusargs. Default is 0 (off). 1728 | ; 0 = Don't check plusargs 1729 | ; 1 = Warning on unrecognized plusarg 1730 | ; 2 = Error and exit on unrecognized plusarg 1731 | ; CheckPlusargs = 1 1732 | 1733 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 1734 | ; This gives global visibility to all symbols in the shared objects, 1735 | ; meaning that subsequently loaded shared objects can bind to symbols 1736 | ; in the global shared objects. The list of shared objects should 1737 | ; be whitespace delimited. This option is not supported on the 1738 | ; Windows or AIX platforms. 1739 | ; GlobalSharedObjectList = example1.so example2.so example3.so 1740 | 1741 | ; Generate the stub definitions for the undefined symbols in the shared libraries being 1742 | ; loaded in the simulation. When this flow is turned on, the undefined symbols will not 1743 | ; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. 1744 | ; The valid arguments are: on, off, verbose. 1745 | ; on : turn on the automatic generation of stub definitions. 1746 | ; off: turn off the flow. The undefined symbols will trigger an immediate load failure. 1747 | ; verbose: Turn on the flow and report the undefined symbols for each shared library. 1748 | ; NOTE: This variable can be overriden with vsim switch "-undefsyms". 1749 | ; The default is off. 1750 | ; 1751 | ; UndefSyms = on 1752 | 1753 | ; Initial seed for the random number generator of the root thread (SystemVerilog). 1754 | ; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. 1755 | ; The default value is 0. 1756 | ; Sv_Seed = 0 1757 | 1758 | ; Specify the solver "engine" that vsim will select for constrained random 1759 | ; generation. 1760 | ; Valid values are: 1761 | ; "auto" - automatically select the best engine for the current 1762 | ; constraint scenario 1763 | ; "bdd" - evaluate all constraint scenarios using the BDD solver engine 1764 | ; "act" - evaluate all constraint scenarios using the ACT solver engine 1765 | ; While the BDD solver engine is generally efficient with constraint scenarios 1766 | ; involving bitwise logical relationships, the ACT solver engine can exhibit 1767 | ; superior performance with constraint scenarios involving large numbers of 1768 | ; random variables related via arithmetic operators (+, *, etc). 1769 | ; NOTE: This variable can be overridden with the vsim "-solveengine" command 1770 | ; line switch. 1771 | ; The default value is "auto". 1772 | ; SolveEngine = auto 1773 | 1774 | ; Specify if the solver should attempt to ignore overflow/underflow semantics 1775 | ; for arithmetic constraints (multiply, addition, subtraction) in order to 1776 | ; improve performance. The "solveignoreoverflow" attribute can be specified on 1777 | ; a per-call basis to randomize() to override this setting. 1778 | ; The default value is 0 (overflow/underflow is not ignored). Set to 1 to 1779 | ; ignore overflow/underflow. 1780 | ; SolveIgnoreOverflow = 0 1781 | 1782 | ; Specifies the maximum size that a dynamic array may be resized to by the 1783 | ; solver. If the solver attempts to resize a dynamic array to a size greater 1784 | ; than the specified limit, the solver will abort with an error. 1785 | ; The default value is 10000. A value of 0 indicates no limit. 1786 | ; SolveArrayResizeMax = 10000 1787 | 1788 | ; Error message severity when randomize() failure is detected (SystemVerilog). 1789 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1790 | ; The default is 0 (no error). 1791 | ; SolveFailSeverity = 0 1792 | 1793 | ; Error message severity for suppressible errors that are detected in a 1794 | ; solve/before constraint. 1795 | ; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" 1796 | ; command line switch. 1797 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1798 | ; The default is 3 (failure). 1799 | ; SolveBeforeErrorSeverity = 3 1800 | 1801 | ; Enable/disable debug information for randomize() failures. 1802 | ; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command 1803 | ; line switch. 1804 | ; The default is 0 (disabled). Set to 1 to enable basic debug (with no 1805 | ; performance penalty). Set to 2 for enhanced debug (will result in slower 1806 | ; runtime performance). 1807 | ; SolveFailDebug = 0 1808 | 1809 | ; Upon encountering a randomize() failure, generate a simplified testcase that 1810 | ; will reproduce the failure. Optionally output the testcase to a file. 1811 | ; Testcases for 'no-solution' failures will only be produced if SolveFailDebug 1812 | ; is enabled (see above). 1813 | ; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" 1814 | ; command line switch. 1815 | ; The default is OFF (do not generate a testcase). To enable testcase 1816 | ; generation, uncomment this variable. To redirect testcase generation to a 1817 | ; file, specify the name of the output file. 1818 | ; SolveFailTestcase = 1819 | 1820 | ; Specify solver timeout threshold (in seconds). randomize() will fail if the 1821 | ; CPU time required to evaluate any randset exceeds the specified timeout. 1822 | ; The default value is 500. A value of 0 will disable timeout failures. 1823 | ; SolveTimeout = 500 1824 | 1825 | ; Specify the maximum size of the solution graph generated by the BDD solver. 1826 | ; This value can be used to force the BDD solver to abort the evaluation of a 1827 | ; complex constraint scenario that cannot be evaluated with finite memory. 1828 | ; This value is specified in 1000s of nodes. 1829 | ; The default value is 10000. A value of 0 indicates no limit. 1830 | ; SolveGraphMaxSize = 10000 1831 | 1832 | ; Specify the maximum number of evaluations that may be performed on the 1833 | ; solution graph by the BDD solver. This value can be used to force the BDD 1834 | ; solver to abort the evaluation of a complex constraint scenario that cannot 1835 | ; be evaluated in finite time. This value is specified in 10000s of evaluations. 1836 | ; The default value is 10000. A value of 0 indicates no limit. 1837 | ; SolveGraphMaxEval = 10000 1838 | 1839 | ; Specify the maximum number of tests that the ACT solver may evaluate before 1840 | ; abandoning an attempt to solve a particular constraint scenario. 1841 | ; The default value is 2000000. A value of 0 indicates no limit. 1842 | ; SolveACTMaxTests = 2000000 1843 | 1844 | ; Specify the maximum number of operations that the ACT solver may perform 1845 | ; before abandoning an attempt to solve a particular constraint scenario. The 1846 | ; value is specified in 1000000s of operations. 1847 | ; The default value is 10000. A value of 0 indicates no limit. 1848 | ; SolveACTMaxOps = 10000 1849 | 1850 | ; Specify the number of times the ACT solver will retry to evaluate a constraint 1851 | ; scenario that fails due to the SolveACTMax[Tests|Ops] threshold. 1852 | ; The default value is 0 (no retry). 1853 | ; SolveACTRetryCount = 0 1854 | 1855 | ; Specify random sequence compatiblity with a prior letter release. This 1856 | ; option is used to get the same random sequences during simulation as 1857 | ; as a prior letter release. Only prior letter releases (of the current 1858 | ; number release) are allowed. 1859 | ; NOTE: Only those random sequence changes due to solver optimizations are 1860 | ; reverted by this variable. Random sequence changes due to solver bugfixes 1861 | ; cannot be un-done. 1862 | ; NOTE: This variable can be overridden with the vsim "-solverev" command 1863 | ; line switch. 1864 | ; Default value set to "" (no compatibility). 1865 | ; SolveRev = 1866 | 1867 | ; Environment variable expansion of command line arguments has been depricated 1868 | ; in favor shell level expansion. Universal environment variable expansion 1869 | ; inside -f files is support and continued support for MGC Location Maps provide 1870 | ; alternative methods for handling flexible pathnames. 1871 | ; The following line may be uncommented and the value set to 1 to re-enable this 1872 | ; deprecated behavior. The default value is 0. 1873 | ; DeprecatedEnvironmentVariableExpansion = 0 1874 | 1875 | ; Specify the memory threshold for the System Verilog garbage collector. 1876 | ; The value is the number of megabytes of class objects that must accumulate 1877 | ; before the garbage collector is run. 1878 | ; The GCThreshold setting is used when class debug mode is disabled to allow 1879 | ; less frequent garbage collection and better simulation performance. 1880 | ; The GCThresholdClassDebug setting is used when class debug mode is enabled 1881 | ; to allow for more frequent garbage collection. 1882 | ; GCThreshold = 100 1883 | ; GCThresholdClassDebug = 5 1884 | 1885 | ; Turn on/off collapsing of bus ports in VCD dumpports output 1886 | DumpportsCollapse = 1 1887 | 1888 | ; Location of Multi-Level Verification Component (MVC) installation. 1889 | ; The default location is the product installation directory. 1890 | MvcHome = $MODEL_TECH/.. 1891 | 1892 | ; Location of InFact installation. The default is $MODEL_TECH/../../infact 1893 | ; 1894 | ; InFactHome = $MODEL_TECH/../../infact 1895 | 1896 | ; Initialize SystemVerilog enums using the base type's default value 1897 | ; instead of the leftmost value. 1898 | ; EnumBaseInit = 1 1899 | 1900 | ; Suppress file type registration. 1901 | ; SuppressFileTypeReg = 1 1902 | 1903 | ; Controls SystemVerilog Language Extensions. These options enable 1904 | ; some non-LRM compliant behavior. Valid extensions are "cfce", 1905 | ; SvExtensions = cfce 1906 | 1907 | ; Controls the formatting of '%p' and '%P' conversion specification, used in $display 1908 | ; and similar system tasks. 1909 | ; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. 1910 | ; The 'I' flag when present causes relevant data types to be expanded and indented into 1911 | ; a more readable format. 1912 | ; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). 1913 | ; 2. SVPrettyPrintFlags=L limits the output to lines. 1914 | ; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). 1915 | ; 3. SVPrettyPrintFlags=C limits the output to characters. 1916 | ; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). 1917 | ; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes 1918 | ; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). 1919 | ; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes 1920 | ; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). 1921 | ; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . 1922 | ; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). 1923 | ; 7. Items 1-6 above can be combined as a comma separated list. 1924 | ; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5) 1925 | ; SVPrettyPrintFlags=I4S 1926 | 1927 | [lmc] 1928 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software 1929 | libsm = $MODEL_TECH/libsm.sl 1930 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) 1931 | ; libsm = $MODEL_TECH/libsm.dll 1932 | ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) 1933 | ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl 1934 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 1935 | ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 1936 | ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) 1937 | ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so 1938 | ; Logic Modeling's SmartModel SWIFT software (Windows NT) 1939 | ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll 1940 | ; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) 1941 | ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so 1942 | ; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) 1943 | ; libswift = $LMC_HOME/lib/linux.lib/libswift.so 1944 | 1945 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software 1946 | libhm = $MODEL_TECH/libhm.sl 1947 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) 1948 | ; libhm = $MODEL_TECH/libhm.dll 1949 | ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) 1950 | ; libsfi = /lib/hp700/libsfi.sl 1951 | ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) 1952 | ; libsfi = /lib/rs6000/libsfi.a 1953 | ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) 1954 | ; libsfi = /lib/sun4.solaris/libsfi.so 1955 | ; Logic Modeling's hardware modeler SFI software (Windows NT) 1956 | ; libsfi = /lib/pcnt/lm_sfi.dll 1957 | ; Logic Modeling's hardware modeler SFI software (Linux) 1958 | ; libsfi = /lib/linux/libsfi.so 1959 | 1960 | [msg_system] 1961 | ; Change a message severity or suppress a message. 1962 | ; The format is: = [,...] 1963 | ; suppress can be used to achieve +nowarn functionality 1964 | ; The format is: suppress = ,,[,,...] 1965 | ; Examples: 1966 | suppress = 8780 ;an explanation can be had by running: verror 8780 1967 | ; note = 3009 1968 | ; warning = 3033 1969 | ; error = 3010,3016 1970 | ; fatal = 3016,3033 1971 | ; suppress = 3009,3016,3601 1972 | ; suppress = 3009,CNNODP,3601,TFMPC 1973 | ; suppress = 8683,8684 1974 | ; The command verror can be used to get the complete 1975 | ; description of a message. 1976 | 1977 | ; Control transcripting of Verilog display system task messages and 1978 | ; PLI/FLI print function call messages. The system tasks include 1979 | ; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They 1980 | ; also include the analogous file I/O tasks that write to STDOUT 1981 | ; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, 1982 | ; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default 1983 | ; is to have messages appear only in the transcript. The other 1984 | ; settings are to send messages to the wlf file only (messages that 1985 | ; are recorded in the wlf file can be viewed in the MsgViewer) or 1986 | ; to both the transcript and the wlf file. The valid values are 1987 | ; tran {transcript only (default)} 1988 | ; wlf {wlf file only} 1989 | ; both {transcript and wlf file} 1990 | ; displaymsgmode = tran 1991 | 1992 | ; Control transcripting of elaboration/runtime messages not 1993 | ; addressed by the displaymsgmode setting. The default is to 1994 | ; have messages appear only in the transcript. The other settings 1995 | ; are to send messages to the wlf file only (messages that are 1996 | ; recorded in the wlf file can be viewed in the MsgViewer) or to both 1997 | ; the transcript and the wlf file. The valid values are 1998 | ; tran {transcript only (default)} 1999 | ; wlf {wlf file only} 2000 | ; both {transcript and wlf file} 2001 | ; msgmode = tran 2002 | 2003 | ; Controls number of displays of a particluar message 2004 | ; default value is 5 2005 | ; MsgLimitCount = 5 2006 | 2007 | [utils] 2008 | ; Default Library Type (while creating a library with "vlib") 2009 | ; 0 - legacy library using subdirectories for design units 2010 | ; 2 - flat library 2011 | ; DefaultLibType = 2 2012 | 2013 | ; Flat Library Page Size (while creating a library with "vlib") 2014 | ; Set the size in bytes for flat library file pages. Libraries containing 2015 | ; very large files may benefit from a larger value. 2016 | ; FlatLibPageSize = 8192 2017 | 2018 | ; Flat Library Page Cleanup Percentage (while creating a library with "vlib") 2019 | ; Set the percentage of total pages deleted before library cleanup can occur. 2020 | ; This setting is applied together with FlatLibPageDeleteThreshold. 2021 | ; FlatLibPageDeletePercentage = 50 2022 | 2023 | ; Flat Library Page Cleanup Threshold (while creating a library with "vlib") 2024 | ; Set the number of pages deleted before library cleanup can occur. 2025 | ; This setting is applied together with FlatLibPageDeletePercentage. 2026 | ; FlatLibPageDeleteThreshold = 1000 2027 | 2028 | [Project] 2029 | ; Warning -- Do not edit the project properties directly. 2030 | ; Property names are dynamic in nature and property 2031 | ; values have special syntax. Changing property data directly 2032 | ; can result in a corrupt MPF file. All project properties 2033 | ; can be modified through project window dialogs. 2034 | Project_Version = 6 2035 | Project_DefaultLib = work 2036 | Project_SortMethod = unused 2037 | Project_Files_Count = 17 2038 | Project_File_0 = V:/Masters/VLSI testing and vrification/Verilog/Controller.v 2039 | Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1559783142 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 2040 | Project_File_1 = V:/Masters/VLSI testing and vrification/Verilog/MuxB.v 2041 | Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1559254421 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 2042 | Project_File_2 = V:/Masters/VLSI testing and vrification/Verilog/InstReg.v 2043 | Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1559253226 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 2044 | Project_File_3 = V:/Masters/VLSI testing and vrification/Verilog/Basics.v 2045 | Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1558905393 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 2046 | Project_File_4 = V:/Masters/VLSI testing and vrification/Verilog/RegA.v 2047 | Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1559085566 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 2048 | Project_File_5 = V:/Masters/VLSI testing and vrification/Verilog/InstMemory.v 2049 | Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1559090916 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 2050 | Project_File_6 = V:/Masters/VLSI testing and vrification/Verilog/CPU.v 2051 | Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1559866680 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 2052 | Project_File_7 = V:/Masters/VLSI testing and vrification/Verilog/Encoder16-4.v 2053 | Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1558913377 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 2054 | Project_File_8 = V:/Masters/VLSI testing and vrification/Verilog/ArithUnit.v 2055 | Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1559079904 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 2056 | Project_File_9 = V:/Masters/VLSI testing and vrification/Verilog/RegB.v 2057 | Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1559085928 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 2058 | Project_File_10 = V:/Masters/VLSI testing and vrification/Verilog/RegC.v 2059 | Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1559086240 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 2060 | Project_File_11 = V:/Masters/VLSI testing and vrification/Verilog/LogicUnit.v 2061 | Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1559081990 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 2062 | Project_File_12 = V:/Masters/VLSI testing and vrification/Verilog/Counter.v 2063 | Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1558911133 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 2064 | Project_File_13 = V:/Masters/VLSI testing and vrification/Verilog/ALU.v 2065 | Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1559082105 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 2066 | Project_File_14 = V:/Masters/VLSI testing and vrification/Verilog/Mux.v 2067 | Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1559687936 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 2068 | Project_File_15 = V:/Masters/VLSI testing and vrification/Verilog/PC.v 2069 | Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1559250607 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 2070 | Project_File_16 = V:/Masters/VLSI testing and vrification/Verilog/DataMemory.v 2071 | Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1559090397 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 2072 | Project_Sim_Count = 0 2073 | Project_Folder_Count = 0 2074 | Echo_Compile_Output = 0 2075 | Save_Compile_Report = 1 2076 | Project_Opt_Count = 0 2077 | ForceSoftPaths = 0 2078 | ProjectStatusDelay = 5000 2079 | VERILOG_DoubleClick = Edit 2080 | VERILOG_CustomDoubleClick = 2081 | SYSTEMVERILOG_DoubleClick = Edit 2082 | SYSTEMVERILOG_CustomDoubleClick = 2083 | VHDL_DoubleClick = Edit 2084 | VHDL_CustomDoubleClick = 2085 | PSL_DoubleClick = Edit 2086 | PSL_CustomDoubleClick = 2087 | TEXT_DoubleClick = Edit 2088 | TEXT_CustomDoubleClick = 2089 | SYSTEMC_DoubleClick = Edit 2090 | SYSTEMC_CustomDoubleClick = 2091 | TCL_DoubleClick = Edit 2092 | TCL_CustomDoubleClick = 2093 | MACRO_DoubleClick = Edit 2094 | MACRO_CustomDoubleClick = 2095 | VCD_DoubleClick = Edit 2096 | VCD_CustomDoubleClick = 2097 | SDF_DoubleClick = Edit 2098 | SDF_CustomDoubleClick = 2099 | XML_DoubleClick = Edit 2100 | XML_CustomDoubleClick = 2101 | LOGFILE_DoubleClick = Edit 2102 | LOGFILE_CustomDoubleClick = 2103 | UCDB_DoubleClick = Edit 2104 | UCDB_CustomDoubleClick = 2105 | TDB_DoubleClick = Edit 2106 | TDB_CustomDoubleClick = 2107 | UPF_DoubleClick = Edit 2108 | UPF_CustomDoubleClick = 2109 | PCF_DoubleClick = Edit 2110 | PCF_CustomDoubleClick = 2111 | PROJECT_DoubleClick = Edit 2112 | PROJECT_CustomDoubleClick = 2113 | VRM_DoubleClick = Edit 2114 | VRM_CustomDoubleClick = 2115 | DEBUGDATABASE_DoubleClick = Edit 2116 | DEBUGDATABASE_CustomDoubleClick = 2117 | DEBUGARCHIVE_DoubleClick = Edit 2118 | DEBUGARCHIVE_CustomDoubleClick = 2119 | Project_Major_Version = 10 2120 | Project_Minor_Version = 4 2121 | -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/vprabhu28/16-Bit-CPU-using-Verilog/4d041aedde7b13a7adf3585a2c3e5fb4b30ffeb8/CPU 16- Bit using Verilog/vsim.wlf -------------------------------------------------------------------------------- /CPU 16- Bit using Verilog/work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | 13 5 | !s112 1.1 6 | !i10d 8192 7 | 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-------------------------------------------------------------------------------- 1 | # 16-Bit-CPU-using-Verilog 2 | Design of a 16-Bit CPU using Verilog 3 | 4 | ---- 5 | # Requirements 6 | 7 | 8 | --- 9 | ## Approach 10 | 11 | To achieve a 16-Bit CPU design, we had to start by designing the individual components. 12 | The components used were: 13 | 14 | 1. ALU 15 | 2. Arithmetic Unit 16 | 3. Logic Unit 17 | 5. Data Memory 18 | 6. Instruction memory 19 | 7. Program Counter 20 | 8. Instruction Register 21 | 9. Multiplexer 22 | 10. Controller 23 | 11. CPU 24 | 25 | ------ 26 | 27 | 28 | ## The Instruction Set 29 | 30 | The instruction set plays a very important role to determine the operation of the CPU. The Code input to the Instruction memory is 16-bit long. This is sent to the instruction register which takes the bits [15:12] as OPCODE and [11:0] as address to start with. 31 | 32 | The instruction set are designed in a way to achieve all the necessary functions. Since the OPCODE controls the activity, the OPCODE is used as described below. 33 | 34 | The last bit of the code input acts as a mode selection for ALU. Remaining 3 are used for the ALU operation. 35 | 36 | 0000 - Mode 0, Arithmetic Unit for ADD 37 | 38 | 0001 - Mode 0, Arithmetic Unit for Multiply 39 | 40 | 0010 - Mode 0, Arithmetic Unit for Subtract 41 | 42 | 0011 - Mode 0, Arithmetic Unit for Division 43 | 44 | 0100 - Instruction set for Load A 45 | 46 | 0101 - Instruction set for Load B 47 | 48 | 0110 - Instruction set for Load C 49 | 50 | 0111 - Instruction set for jumping to immediate address 51 | 52 | 1000 - Mode 1, Logical AND 53 | 54 | 1001 - Mode 1, Logical OR 55 | 56 | 1010 - Mode 1, Logical NAND 57 | 58 | 1011 - Mode 1, Logical NOR 59 | 60 | 1100 - Mode 1, Logical NOT A 61 | 62 | 1101 - Mode 1, Logical NOT B 63 | 64 | 1110 - Mode 1, Logical XOR 65 | 66 | 1111 - Mode 1, Logical XNOR 67 | 68 | ------ 69 | 70 | ## Flow 71 | 72 | The Design is completed using a state machine approach. Three states are used to monitor the action of CPU. The three states used are reset, load and execute. 73 | 74 | In reset state, we initializa all address to base address and code input to 0. All the signals going out from controller are 0. 75 | 76 | In the load state, we initialise the Instruction register with the address and OPCODE to make sure the design is ready for execution. 77 | 78 | In execute state, we provide the function required by the USER based in the Instruction set provided. 79 | 80 | ---- 81 | 82 | ## CODE 83 | 84 | The code for the entire design is provided in the folder. The codes have been executed and checked for proper funtioning. 85 | --------------------------------------------------------------------------------