├── .gitignore ├── LICENSE ├── README.md ├── arduino ├── examples │ ├── ColorInvadersSound.cpp │ └── missileSoundEffects.cpp └── tone_test1 │ ├── pitches.h │ └── tone_test1.ino ├── base └── proj0 │ ├── accel_proc.vhd │ ├── bin2seg7.vhd │ ├── defender_common.vhd │ ├── enemies.vhd │ ├── hud.vhd │ ├── image_gen.vhd │ ├── ip │ ├── ADXL345_controller.vhd │ ├── binary_to_bcd.vhd │ ├── binary_to_bcd_digit.vhd │ ├── dual_boot.sopcinfo │ ├── dual_boot │ │ ├── dual_boot.bsf │ │ ├── dual_boot.cmp │ │ ├── dual_boot.html │ │ ├── dual_boot.qsys │ │ ├── dual_boot.xml │ │ ├── dual_boot_bb.v │ │ ├── dual_boot_inst.v │ │ ├── dual_boot_inst.vhd │ │ └── synthesis │ │ │ ├── dual_boot.debuginfo │ │ │ ├── dual_boot.qip │ │ │ ├── dual_boot.vhd │ │ │ └── submodules │ │ │ ├── altera_dual_boot.v │ │ │ ├── altera_reset_controller.sdc │ │ │ ├── altera_reset_controller.v │ │ │ ├── altera_reset_synchronizer.v │ │ │ └── rtl │ │ │ ├── alt_dual_boot.v │ │ │ └── alt_dual_boot_avmm.v │ ├── gsensor.sv │ ├── single_port_ram.vhd │ ├── spi.sv │ ├── vgaText │ │ ├── BlockRamArbiter.vhd │ │ ├── basicBlockRAM.vhd │ │ ├── commonPak.vhd │ │ ├── fontROM.vhd │ │ ├── tb_and_ex │ │ │ ├── tb_vgaText1.vhd │ │ │ ├── tb_vgaText2.vhd │ │ │ ├── tb_vgaText3.vhd │ │ │ └── vgaText_top.vhd │ │ └── text_line.vhd │ ├── vga_controller.vhd │ └── vga_pll_25_175.vhd │ ├── lfsr8.vhd │ ├── overlays.vhd │ ├── player_ship.vhd │ ├── proj0.qpf │ ├── proj0.qsf │ ├── proj0.qws │ ├── proj0_assignment_defaults.qdf │ ├── proj0_top.vhd │ ├── sound_effects │ ├── clock_div.vhd │ ├── effect_gen.vhd │ ├── effect_gen_tb.do │ ├── effect_gen_tb.vhd │ ├── effect_mem.cmp │ ├── effect_mem.mif │ ├── effect_mem.qip │ ├── effect_mem.vhd │ └── effect_mem_tb.vhd │ └── triangle.vhd ├── bonuses └── proj1 │ ├── accel_proc.vhd │ ├── async_rom_init.vhd │ ├── bin2seg7.vhd │ ├── defender_common.vhd │ ├── enemies.vhd │ ├── hud.vhd │ ├── image_gen.vhd │ ├── ip │ ├── ADXL345_controller.vhd │ ├── binary_to_bcd.vhd │ ├── binary_to_bcd_digit.vhd │ ├── dual_boot.sopcinfo │ ├── dual_boot │ │ ├── dual_boot.bsf │ │ ├── dual_boot.cmp │ │ ├── dual_boot.html │ │ ├── dual_boot.qsys │ │ ├── dual_boot.xml │ │ ├── dual_boot_bb.v │ │ ├── dual_boot_inst.v │ │ ├── dual_boot_inst.vhd │ │ └── synthesis │ │ │ ├── dual_boot.debuginfo │ │ │ ├── dual_boot.qip │ │ │ ├── dual_boot.vhd │ │ │ └── submodules │ │ │ ├── altera_dual_boot.v │ │ │ ├── altera_reset_controller.sdc │ │ │ ├── altera_reset_controller.v │ │ │ ├── altera_reset_synchronizer.v │ │ │ └── rtl │ │ │ ├── alt_dual_boot.v │ │ │ └── alt_dual_boot_avmm.v │ ├── gsensor.sv │ ├── spi.sv │ ├── vgaText │ │ ├── BlockRamArbiter.vhd │ │ ├── basicBlockRAM.vhd │ │ ├── commonPak.vhd │ │ ├── fontROM.vhd │ │ ├── tb_and_ex │ │ │ ├── tb_vgaText1.vhd │ │ │ ├── tb_vgaText2.vhd │ │ │ ├── tb_vgaText3.vhd │ │ │ └── vgaText_top.vhd │ │ └── text_line.vhd │ ├── vga_controller.vhd │ └── vga_pll_25_175.vhd │ ├── lfsr_n.vhd │ ├── overlays.vhd │ ├── pb_debounce.vhd │ ├── player_ship.vhd │ ├── proj1.qpf │ ├── proj1.qsf │ ├── proj1.qws │ ├── proj1_assignment_defaults.qdf │ ├── proj1_top.vhd │ ├── res │ ├── effect_mem.mif │ ├── palette.mif │ └── sprite_data.mif │ ├── sound_effects │ ├── clock_div.vhd │ ├── effect_gen.vhd │ └── tb │ │ ├── effect_gen_tb.do │ │ ├── effect_gen_tb.vhd │ │ └── effect_mem_tb.vhd │ ├── spr_rom_arb.vhd │ ├── sprite_draw.vhd │ ├── starfield.vhd │ ├── sync_ram_init.vhd │ └── terrain.vhd ├── docs └── f21_spec.pdf ├── flash ├── proj0.pof ├── proj0.sof ├── proj1.pof └── proj1.sof ├── img ├── banner.gif ├── board.jpg ├── demo1.gif ├── demo2.gif └── proj1_res_use.png └── test └── effect_test ├── DE10_LITE_Golden_Top.v ├── clock_div.vhd ├── effect_gen.vhd ├── effect_gen_tb.do ├── effect_gen_tb.vhd ├── effect_mem.cmp ├── effect_mem.mif ├── effect_mem.qip ├── effect_mem.vhd ├── effect_mem_tb.vhd ├── effect_test.qpf ├── effect_test.qsf ├── effect_test.qws ├── effect_test_assignment_defaults.qdf └── effect_test_top.vhd /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | **/db/ 3 | **/incremental_db/ 4 | **/devkits/ 5 | **/output_files/ 6 | **/simulation/ 7 | **/greybox_tmp/ 8 | *.rpt 9 | *.bak 10 | *.json 11 | *.qws -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Garrett Carter 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /arduino/examples/missileSoundEffects.cpp: -------------------------------------------------------------------------------- 1 | // Source: https://www.instructables.com/Creating-arcade-game-sounds-on-a-microcontroller/ 2 | // Author: JColvin91 3 | 4 | int buzzerPin = 4; 5 | 6 | void setup(){ 7 | pinMode(buzzerPin, OUTPUT); 8 | //charge the missile 9 | for(int chargingFrequency=0; chargingFrequency<50; chargingFrequency++){ 10 | playFreq(300.251+(chargingFrequency*15), 15); 11 | } 12 | delay(500); 13 | //fire the missile 14 | for(int missileFired=0; missileFired<20; missileFired++){ 15 | playFreq(800.251-(missileFired*15), 10); 16 | } 17 | 18 | delay(1000); 19 | //explosion sound of random frequencies choosen off the 20 | //top of my head 21 | playFreq(550, 40); 22 | playFreq(404, 40); 23 | playFreq(315, 40); 24 | playFreq(494, 40); 25 | playFreq(182, 40); 26 | playFreq(260, 40); 27 | playFreq(455, 40); 28 | playFreq(387, 40); 29 | playFreq(340, 40); 30 | playFreq(550, 40); //begin repeat of the frequencies just played 31 | playFreq(404, 40); 32 | playFreq(315, 40); 33 | playFreq(494, 40); 34 | playFreq(182, 40); 35 | playFreq(260, 40); 36 | playFreq(455, 40); 37 | playFreq(387, 40); 38 | playFreq(340, 40); 39 | 40 | //wah, wah, wah, wahwawawawa 41 | for(double wah=0; wah<4; wah+=6.541){ 42 | playFreq(440+wah, 50); //'A4' gliss to A#4 43 | } 44 | playFreq(466.164, 100); //A#4 45 | delay(80); 46 | for(double wah=0; wah<5; wah+=4.939){ 47 | playFreq(415.305+wah, 50); //Ab4 gliss to A4 48 | } 49 | playFreq(440.000, 100); //A4 50 | delay(80); 51 | for(double wah=0; wah<5; wah+=4.662){ 52 | playFreq(391.995+wah, 50); //G4 gliss to Ab4 53 | } 54 | playFreq(415.305, 100); //Ab4 55 | delay(80); 56 | for(int j=0; j<7; j++){ //oscillate between G4 and Ab4 57 | playFreq(391.995, 70); //G4 58 | playFreq(415.305, 70); //Ab4 59 | } 60 | }//END of setup 61 | 62 | void loop(){ 63 | //do nothing in the loop for now; only testing in the setup 64 | } 65 | 66 | 67 | void playFreq(double freqHz, int durationMs){ 68 | //Calculate the period in microseconds 69 | int periodMicro = int((1/freqHz)*1000000); 70 | int halfPeriod = periodMicro/2; 71 | 72 | //store start time 73 | int startTime = millis(); 74 | 75 | //(millis() - startTime) is elapsed play time 76 | while((millis() - startTime) < durationMs){ 77 | digitalWrite(buzzerPin, HIGH); 78 | delayMicroseconds(halfPeriod); 79 | digitalWrite(buzzerPin, LOW); 80 | delayMicroseconds(halfPeriod); 81 | } 82 | } 83 | 84 | 85 | -------------------------------------------------------------------------------- /arduino/tone_test1/pitches.h: -------------------------------------------------------------------------------- 1 | /************************************************* 2 | * Public Constants 3 | *************************************************/ 4 | 5 | #define NOTE_B0 31 6 | #define NOTE_C1 33 7 | #define NOTE_CS1 35 8 | #define NOTE_D1 37 9 | #define NOTE_DS1 39 10 | #define NOTE_E1 41 11 | #define NOTE_F1 44 12 | #define NOTE_FS1 46 13 | #define NOTE_G1 49 14 | #define NOTE_GS1 52 15 | #define NOTE_A1 55 16 | #define NOTE_AS1 58 17 | #define NOTE_B1 62 18 | #define NOTE_C2 65 19 | #define NOTE_CS2 69 20 | #define NOTE_D2 73 21 | #define NOTE_DS2 78 22 | #define NOTE_E2 82 23 | #define NOTE_F2 87 24 | #define NOTE_FS2 93 25 | #define NOTE_G2 98 26 | #define NOTE_GS2 104 27 | #define NOTE_A2 110 28 | #define NOTE_AS2 117 29 | #define NOTE_B2 123 30 | #define NOTE_C3 131 31 | #define NOTE_CS3 139 32 | #define NOTE_D3 147 33 | #define NOTE_DS3 156 34 | #define NOTE_E3 165 35 | #define NOTE_F3 175 36 | #define NOTE_FS3 185 37 | #define NOTE_G3 196 38 | #define NOTE_GS3 208 39 | #define NOTE_A3 220 40 | #define NOTE_AS3 233 41 | #define NOTE_B3 247 42 | #define NOTE_C4 262 43 | #define NOTE_CS4 277 44 | #define NOTE_D4 294 45 | #define NOTE_DS4 311 46 | #define NOTE_E4 330 47 | #define NOTE_F4 349 48 | #define NOTE_FS4 370 49 | #define NOTE_G4 392 50 | #define NOTE_GS4 415 51 | #define NOTE_A4 440 52 | #define NOTE_AS4 466 53 | #define NOTE_B4 494 54 | #define NOTE_C5 523 55 | #define NOTE_CS5 554 56 | #define NOTE_D5 587 57 | #define NOTE_DS5 622 58 | #define NOTE_E5 659 59 | #define NOTE_F5 698 60 | #define NOTE_FS5 740 61 | #define NOTE_G5 784 62 | #define NOTE_GS5 831 63 | #define NOTE_A5 880 64 | #define NOTE_AS5 932 65 | #define NOTE_B5 988 66 | #define NOTE_C6 1047 67 | #define NOTE_CS6 1109 68 | #define NOTE_D6 1175 69 | #define NOTE_DS6 1245 70 | #define NOTE_E6 1319 71 | #define NOTE_F6 1397 72 | #define NOTE_FS6 1480 73 | #define NOTE_G6 1568 74 | #define NOTE_GS6 1661 75 | #define NOTE_A6 1760 76 | #define NOTE_AS6 1865 77 | #define NOTE_B6 1976 78 | #define NOTE_C7 2093 79 | #define NOTE_CS7 2217 80 | #define NOTE_D7 2349 81 | #define NOTE_DS7 2489 82 | #define NOTE_E7 2637 83 | #define NOTE_F7 2794 84 | #define NOTE_FS7 2960 85 | #define NOTE_G7 3136 86 | #define NOTE_GS7 3322 87 | #define NOTE_A7 3520 88 | #define NOTE_AS7 3729 89 | #define NOTE_B7 3951 90 | #define NOTE_C8 4186 91 | #define NOTE_CS8 4435 92 | #define NOTE_D8 4699 93 | #define NOTE_DS8 4978 94 | -------------------------------------------------------------------------------- /arduino/tone_test1/tone_test1.ino: -------------------------------------------------------------------------------- 1 | // tone_test1: A sound effect sandbox for the "Arduino Apollo" with onboard Piezo on pin D9. 2 | 3 | #include "pitches.h" // must include open source pitches.h found online in libraries folder or make a new tab => https://www.arduino.cc/en/Tutorial/toneMelody 4 | #define BUZZ_PIN 9 5 | 6 | void setup() { 7 | 8 | Serial.begin(9600); 9 | // randomSeed(analogRead(0)); 10 | pinMode(BUZZ_PIN, OUTPUT); 11 | //launch 12 | // for(long freqIn = 200; freqIn < 500; freqIn = freqIn + 2){ 13 | // tone(BUZZ_PIN, freqIn,10); 14 | // } 15 | // delay(10); 16 | 17 | // life lost test 18 | // long blow1; 19 | // long blow2; 20 | // long start_f = 300; 21 | // long stop_f = 50; 22 | 23 | // int i = -1; 24 | // long duration = 500; 25 | 26 | // long steps = 10; 27 | // long top = 1700; 28 | // long bottom = 100; 29 | // long offset_top = 300; 30 | // long offset_bottom = 20; 31 | // long offset_range = (offset_top - offset_bottom); 32 | // long offset_decr = offset_range / steps; 33 | // long offset = offset_top; 34 | // long range = (top - bottom); 35 | // long del = duration / steps; 36 | // long decr = range / steps; 37 | // long center = top; 38 | 39 | // for(int k = 0; k < steps; k++){ 40 | // long freq = center + i * offset; 41 | // long duration = del; 42 | // Serial.println(freq); 43 | // Serial.println(duration); 44 | // tone(BUZZ_PIN, freq, duration); 45 | // delay(del); 46 | // i *= i; 47 | // center -= decr; 48 | // offset -= offset_decr; 49 | // } 50 | 51 | // delay(2000); 52 | 53 | // randomly generated explosion sound 54 | randomSeed(500); 55 | Serial.println("-----random explosion------"); 56 | int numSteps = 20; 57 | int totalDurationMsec = 500; 58 | int waitTime = totalDurationMsec / numSteps; 59 | 60 | for(int k = 0; k < numSteps; k++){ 61 | int blow1 = random(100,500); 62 | // blow2 = random(5,10); 63 | tone(BUZZ_PIN, blow1, waitTime); 64 | delay(waitTime); 65 | 66 | Serial.println(blow1); 67 | Serial.println(waitTime); 68 | } 69 | 70 | delay(2000); 71 | 72 | // Play coin sound 73 | // tone(BUZZ_PIN,NOTE_B5,100); 74 | // delay(100); 75 | // tone(BUZZ_PIN,NOTE_E6,850); 76 | // delay(800); 77 | // noTone(8); 78 | 79 | // delay(2000); // pause 2 seconds 80 | // 81 | // // Play 1-up sound 82 | // tone(BUZZ_PIN,NOTE_E6,125); 83 | // delay(130); 84 | // tone(BUZZ_PIN,NOTE_G6,125); 85 | // delay(130); 86 | // tone(BUZZ_PIN,NOTE_E7,125); 87 | // delay(130); 88 | // tone(BUZZ_PIN,NOTE_C7,125); 89 | // delay(130); 90 | // tone(BUZZ_PIN,NOTE_D7,125); 91 | // delay(130); 92 | // tone(BUZZ_PIN,NOTE_G7,125); 93 | // delay(125); 94 | // noTone(8); 95 | 96 | // delay(2000); // pause 2 seconds 97 | // 98 | // // Play Fireball sound 99 | // tone(BUZZ_PIN,NOTE_G4,35); 100 | // delay(35); 101 | // tone(BUZZ_PIN,NOTE_G5,35); 102 | // delay(35); 103 | // tone(BUZZ_PIN,NOTE_G6,35); 104 | // delay(35); 105 | // noTone(8); 106 | // 107 | // delay(2000); // pause 2 seconds 108 | 109 | //charge the missile 110 | // Serial.println("-----charge-----"); 111 | // for(int chargingFrequency=0; chargingFrequency<50; chargingFrequency++){ 112 | // playFreq(300.251+(chargingFrequency*15), 15); 113 | // } 114 | // delay(500); 115 | // Serial.println("------fire------"); 116 | // //fire the missile 117 | // for(int missileFired=0; missileFired<20; missileFired++){ 118 | // playFreq(800.251-(missileFired*15), 10); 119 | // } 120 | 121 | // delay(1000); 122 | // Serial.println("-------explosion-------"); 123 | // //explosion sound of random frequencies choosen off the 124 | // //top of my head 125 | // playFreq(550, 40); 126 | // playFreq(404, 40); 127 | // playFreq(315, 40); 128 | // playFreq(494, 40); 129 | // playFreq(182, 40); 130 | // playFreq(260, 40); 131 | // playFreq(455, 40); 132 | // playFreq(387, 40); 133 | // playFreq(340, 40); 134 | // playFreq(550, 40); //begin repeat of the frequencies just played 135 | // playFreq(404, 40); 136 | // playFreq(315, 40); 137 | // playFreq(494, 40); 138 | // playFreq(182, 40); 139 | // playFreq(260, 40); 140 | // playFreq(455, 40); 141 | // playFreq(387, 40); 142 | // playFreq(340, 40); 143 | 144 | // Serial.println("-------wah, wah, wah, wahwawawawa---------"); 145 | // //wah, wah, wah, wahwawawawa 146 | // for(double wah=0; wah<4; wah+=6.541){ 147 | // playFreq(440+wah, 50); //'A4' gliss to A#4 148 | // } 149 | // playFreq(466.164, 100); //A#4 150 | // Serial.println("0"); 151 | // Serial.println("80"); 152 | // delay(80); 153 | // for(double wah=0; wah<5; wah+=4.939){ 154 | // playFreq(415.305+wah, 50); //Ab4 gliss to A4 155 | // } 156 | // playFreq(440.000, 100); //A4 157 | // Serial.println("0"); 158 | // Serial.println("80"); 159 | // delay(80); 160 | // for(double wah=0; wah<5; wah+=4.662){ 161 | // playFreq(391.995+wah, 50); //G4 gliss to Ab4 162 | // } 163 | // playFreq(415.305, 100); //Ab4 164 | // Serial.println("0"); 165 | // Serial.println("80"); 166 | // delay(80); 167 | // for(int j=0; j<7; j++){ //oscillate between G4 and Ab4 168 | // playFreq(391.995, 70); //G4 169 | // playFreq(415.305, 70); //Ab4 170 | // } 171 | 172 | 173 | } 174 | 175 | void loop() { 176 | // tone(BUZZ_PIN, map(analogRead(0), 0, 1023, 30, 5000)); 177 | delay(10); 178 | } 179 | 180 | void playFreq(double freqHz, int durationMs){ 181 | Serial.println(round(freqHz)); 182 | Serial.println(durationMs); 183 | //Calculate the period in microseconds 184 | int periodMicro = int((1/freqHz)*1000000); 185 | int halfPeriod = periodMicro/2; 186 | 187 | //store start time 188 | int startTime = millis(); 189 | 190 | //(millis() - startTime) is elapsed play time 191 | while((millis() - startTime) < durationMs){ 192 | digitalWrite(BUZZ_PIN, HIGH); 193 | delayMicroseconds(halfPeriod); 194 | digitalWrite(BUZZ_PIN, LOW); 195 | delayMicroseconds(halfPeriod); 196 | } 197 | } 198 | -------------------------------------------------------------------------------- /base/proj0/accel_proc.vhd: -------------------------------------------------------------------------------- 1 | -- accel_proc: Accelerometer data processing 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.NUMERIC_STD.all; 5 | 6 | entity accel_proc is 7 | generic( 8 | 9 | -- Top value for input range 10 | g_in_max_val : integer := 1; 11 | -- Top value for output range 12 | g_out_max_val : integer := 1 13 | 14 | ); 15 | port ( 16 | -- Raw data from accelerometer 17 | data_x : IN STD_LOGIC_VECTOR(15 downto 0); 18 | data_y : IN STD_LOGIC_VECTOR(15 downto 0); 19 | data_valid : IN STD_LOGIC; 20 | 21 | -- Direction of tilt 22 | -- x+ : left, x- : right 23 | -- y+ : forward, y- : backward 24 | accel_scale_x, accel_scale_y : OUT integer := 0 -- A scaled version of data 25 | ); 26 | end accel_proc; 27 | 28 | ARCHITECTURE behavior OF accel_proc IS 29 | 30 | -- Component declarations 31 | 32 | -- Signal declarations 33 | 34 | BEGIN 35 | 36 | -- Processes 37 | process(data_x, data_y, data_valid) 38 | begin 39 | 40 | -- Sample new data if it's valid, or hold old data 41 | if (data_valid = '1') then 42 | accel_scale_x <= to_integer(signed(data_x))*g_out_max_val/g_in_max_val; 43 | accel_scale_y <= to_integer(signed(data_y))*g_out_max_val/g_in_max_val; 44 | end if; 45 | 46 | end process; 47 | 48 | 49 | 50 | -- Instantiation and port mapping 51 | 52 | -- Concurrent assignments 53 | 54 | 55 | 56 | END behavior; 57 | 58 | -------------------------------------------------------------------------------- /base/proj0/bin2seg7.vhd: -------------------------------------------------------------------------------- 1 | -- bin2seg7: Binary to 7-segment decoder, active low outputs for DE10-Lite 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | library work; 5 | 6 | -- Your block has a four bit input inData(3 downto 0), 7 | -- a blanking bit input (no segments illuminated, or blank, WHEN blanking is high), 8 | -- a dispHex bit input (show 0-0xF WHEN dispHex is high, else show only 0-9 blanking for 0xA-0xF), 9 | -- and dispPoint bit input (illuminate the "decimal point" WHEN high). 10 | -- Your block has eight output bits. Seven bits segA, segB, ..., segG correspond to a segment on the display, while segPoint controls the corresponding "decimal point". 11 | ENTITY bin2seg7 IS 12 | PORT ( inData : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 13 | blanking : IN STD_LOGIC; 14 | dispHex : IN STD_LOGIC; 15 | dispPoint : IN STD_LOGIC; 16 | dispDash : IN STD_LOGIC; 17 | 18 | -- DP, G, F, E, D, C, B, A 19 | outSegs : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); 20 | END bin2seg7; 21 | 22 | ARCHITECTURE behavior OF bin2seg7 IS 23 | 24 | -- Component declarations 25 | 26 | -- Signal declarations 27 | SIGNAL outSegsTmp : STD_LOGIC_VECTOR(7 DOWNTO 0); 28 | 29 | BEGIN 30 | 31 | -- Processes 32 | PROCESS (inData, blanking, dispHex, dispPoint, dispDash) IS 33 | BEGIN 34 | 35 | -- Decimal digits 36 | IF (dispHex = '0') THEN 37 | CASE inData IS 38 | -- inData | DP, G, F, E, D, C, B, A 39 | WHEN "0000" => outSegsTmp <= "00111111"; 40 | WHEN "0001" => outSegsTmp <= "00000110"; 41 | WHEN "0010" => outSegsTmp <= "01011011"; 42 | WHEN "0011" => outSegsTmp <= "01001111"; 43 | WHEN "0100" => outSegsTmp <= "01100110"; 44 | WHEN "0101" => outSegsTmp <= "01101101"; 45 | WHEN "0110" => outSegsTmp <= "01111101"; 46 | WHEN "0111" => outSegsTmp <= "00000111"; 47 | WHEN "1000" => outSegsTmp <= "01111111"; 48 | WHEN "1001" => outSegsTmp <= "01100111"; 49 | 50 | WHEN "1010" => outSegsTmp <= "00000000"; 51 | WHEN "1011" => outSegsTmp <= "00000000"; 52 | WHEN "1100" => outSegsTmp <= "00000000"; 53 | WHEN "1101" => outSegsTmp <= "00000000"; 54 | WHEN "1110" => outSegsTmp <= "00000000"; 55 | WHEN "1111" => outSegsTmp <= "00000000"; 56 | 57 | WHEN OTHERS => outSegsTmp <= "00000000"; 58 | END CASE; 59 | 60 | -- Hex digits 61 | ELSE 62 | CASE inData IS 63 | -- inData | DP, G, F, E, D, C, B, A 64 | WHEN "0000" => outSegsTmp <= "00111111"; 65 | WHEN "0001" => outSegsTmp <= "00000110"; 66 | WHEN "0010" => outSegsTmp <= "01011011"; 67 | WHEN "0011" => outSegsTmp <= "01001111"; 68 | WHEN "0100" => outSegsTmp <= "01100110"; 69 | WHEN "0101" => outSegsTmp <= "01101101"; 70 | WHEN "0110" => outSegsTmp <= "01111101"; 71 | WHEN "0111" => outSegsTmp <= "00000111"; 72 | WHEN "1000" => outSegsTmp <= "01111111"; 73 | WHEN "1001" => outSegsTmp <= "01100111"; 74 | 75 | WHEN "1010" => outSegsTmp <= "01110111"; 76 | WHEN "1011" => outSegsTmp <= "01111100"; 77 | WHEN "1100" => outSegsTmp <= "00111001"; 78 | WHEN "1101" => outSegsTmp <= "01011110"; 79 | WHEN "1110" => outSegsTmp <= "01111001"; 80 | WHEN "1111" => outSegsTmp <= "01110001"; 81 | 82 | WHEN OTHERS => outSegsTmp <= "00000000"; 83 | END CASE; 84 | END IF; 85 | 86 | -- Handle decimal point 87 | IF (dispPoint = '1') THEN 88 | outSegsTmp(7) <= '1'; 89 | ELSE 90 | outSegsTmp(7) <= '0'; 91 | END IF; 92 | 93 | -- Handle dash 94 | IF (dispDash = '1') THEN 95 | outSegsTmp <= "01000000"; -- g only 96 | END IF; 97 | 98 | -- Handle blanking 99 | IF (blanking = '1') THEN 100 | outSegsTmp <= "00000000"; 101 | END IF; 102 | 103 | END PROCESS; 104 | 105 | -- Instantiation and port mapping 106 | 107 | -- Concurrent assignments 108 | outSegs <= (NOT outSegsTmp); -- Active low segment outputs 109 | 110 | 111 | END behavior; 112 | 113 | -------------------------------------------------------------------------------- /base/proj0/defender_common.vhd: -------------------------------------------------------------------------------- 1 | -- defender_common: Package containing common code for FPGA defender 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | package defender_common is 7 | 8 | -- Constants 9 | constant c_num_text_elems: integer := 8; 10 | constant c_screen_width : integer := 640; 11 | constant c_screen_height : integer := 480; 12 | constant c_bar_height : integer := 3; 13 | constant c_bar_offset : integer := 30; 14 | constant c_upper_bar_pos : integer := c_bar_offset - c_bar_height; 15 | constant c_lower_bar_pos : integer := c_screen_height - c_bar_offset; 16 | 17 | constant c_ship_width : integer := 30; 18 | constant c_ship_height : integer := 20; 19 | 20 | -- Initial conditions 21 | constant c_initial_lives : integer := 3; 22 | 23 | -- Game parameters 24 | constant c_extra_life_score_mult : integer := 500; -- After how many points should we award an extra life? 25 | 26 | -- Integer ranges 27 | constant c_max_color : integer := 4095; 28 | constant c_max_speed : integer := 20; 29 | constant c_max_size : integer := 100; 30 | constant c_min_x : integer := -c_max_size; 31 | constant c_max_x : integer := c_screen_width+c_max_size; 32 | constant c_min_y : integer := -c_max_size; 33 | constant c_max_y : integer := c_screen_height+c_max_size; 34 | constant c_max_score : integer := 999999; 35 | constant c_max_lives : integer := 5; 36 | 37 | -- Sounds 38 | constant c_sound_game_start : std_logic_vector(2 downto 0) := "000"; 39 | constant c_sound_player_fire : std_logic_vector(2 downto 0) := "001"; 40 | constant c_sound_enemy_fire : std_logic_vector(2 downto 0) := "010"; 41 | constant c_sound_enemy_destroy : std_logic_vector(2 downto 0) := "011"; 42 | constant c_sound_player_hit : std_logic_vector(2 downto 0) := "011"; 43 | constant c_sound_game_over : std_logic_vector(2 downto 0) := "100"; 44 | 45 | -- Types 46 | type t_point_2d is 47 | record 48 | x : integer range c_min_x to c_max_x; 49 | y : integer range c_min_y to c_max_y; 50 | end record; 51 | 52 | type t_size_2d is 53 | record 54 | w : integer range 0 to c_max_size; 55 | h : integer range 0 to c_max_size; 56 | end record; 57 | 58 | type t_speed_2d is 59 | record 60 | x : integer range -c_max_speed to c_max_speed; 61 | y : integer range -c_max_speed to c_max_speed; 62 | end record; 63 | 64 | -- Functions 65 | function darken(color : integer; shift_val : integer) return integer; 66 | 67 | -- Is the current scan position in range of the rectangle? Provide one point and a size 68 | function in_range_rect(scan_pos : t_point_2d; obj_pos : t_point_2d; obj_size : t_size_2d) return boolean; 69 | -- Provide two points 70 | function in_range_rect_2pt(scan_pos : t_point_2d; top_left : t_point_2d; bott_right : t_point_2d) return boolean; 71 | -- Are the two rectangles intersecting? o1 should be smaller than o2 72 | function collide_rect(o1_pos : t_point_2d; o1_size : t_size_2d; o2_pos : t_point_2d; o2_size : t_size_2d) return boolean; 73 | -- Is the rectangle off screen? 74 | function off_screen_rect(o1_pos : t_point_2d; o1_size : t_size_2d) return boolean; 75 | 76 | end defender_common; 77 | 78 | package body defender_common is 79 | 80 | function darken(color : integer; shift_val : integer) return integer is 81 | variable red : integer := 0; 82 | variable green : integer := 0; 83 | variable blue : integer := 0; 84 | variable color_uns : unsigned(11 downto 0); 85 | variable color_out : integer; 86 | begin 87 | color_uns := to_unsigned(color, color_uns'LENGTH); 88 | red := to_integer(color_uns(11 downto 8)); 89 | green := to_integer(color_uns(7 downto 4)); 90 | blue := to_integer(color_uns(3 downto 0)); 91 | 92 | red := red - shift_val; 93 | green := green - shift_val; 94 | blue := blue - shift_val; 95 | 96 | if (red < 0) then 97 | red := 0; 98 | end if; 99 | if (green < 0) then 100 | green := 0; 101 | end if; 102 | if (blue < 0) then 103 | blue := 0; 104 | end if; 105 | 106 | color_uns := (to_unsigned(red, 4) & to_unsigned(green, 4) & to_unsigned(blue, 4)); 107 | color_out := to_integer(color_uns); 108 | 109 | return color_out; 110 | end function; 111 | 112 | function in_range_rect(scan_pos : t_point_2d; obj_pos : t_point_2d; obj_size : t_size_2d) return boolean is 113 | begin 114 | if (scan_pos.x >= obj_pos.x and scan_pos.x < obj_pos.x + obj_size.w) and -- Inside X 115 | (scan_pos.y >= obj_pos.y and scan_pos.y < obj_pos.y + obj_size.h) then -- Inside Y 116 | 117 | return true; 118 | else 119 | return false; 120 | end if; 121 | end function; 122 | 123 | function in_range_rect_2pt(scan_pos : t_point_2d; top_left : t_point_2d; bott_right : t_point_2d) return boolean is 124 | begin 125 | if (scan_pos.x >= top_left.x and scan_pos.x < bott_right.x) and -- Inside X 126 | (scan_pos.y >= top_left.y and scan_pos.y < bott_right.y) then -- Inside Y 127 | 128 | return true; 129 | else 130 | return false; 131 | end if; 132 | end function; 133 | 134 | 135 | function collide_rect(o1_pos : t_point_2d; o1_size : t_size_2d; o2_pos : t_point_2d; o2_size : t_size_2d) return boolean is 136 | begin 137 | if ( ((o1_pos.x >= o2_pos.x and o1_pos.x <= o2_pos.x + o2_size.w - 1) or (o1_pos.x + o1_size.w - 1 >= o2_pos.x and o1_pos.x + o1_size.w - 1 <= o2_pos.x + o2_size.w - 1)) and 138 | ((o1_pos.y >= o2_pos.y and o1_pos.y <= o2_pos.y + o2_size.h - 1) or (o1_pos.y + o1_size.h - 1 >= o2_pos.y and o1_pos.y + o1_size.h - 1 <= o2_pos.y + o2_size.h - 1)) ) then 139 | 140 | return true; 141 | else 142 | return false; 143 | end if; 144 | end function; 145 | 146 | function off_screen_rect(o1_pos : t_point_2d; o1_size : t_size_2d) return boolean is 147 | begin 148 | if (o1_pos.x + o1_size.w - 1 < 0) or (o1_pos.x > c_screen_width - 1) or (o1_pos.y + o1_size.h - 1 < 0) or (o1_pos.y > c_screen_height - 1) then 149 | return true; 150 | else 151 | return false; 152 | end if; 153 | end function; 154 | 155 | 156 | 157 | 158 | end defender_common; 159 | -------------------------------------------------------------------------------- /base/proj0/ip/ADXL345_controller.vhd: -------------------------------------------------------------------------------- 1 | -- Component for interfacing with the ADXL345 accelerometer. This is really just a wrapper for a verilog controller that actually does the work. 2 | 3 | library IEEE; 4 | use IEEE.STD_LOGIC_1164.ALL; 5 | 6 | entity ADXL345_controller is 7 | 8 | port ( 9 | 10 | reset_n : IN STD_LOGIC; 11 | clk : IN STD_LOGIC; 12 | data_valid : OUT STD_LOGIC; 13 | data_x : OUT STD_LOGIC_VECTOR(15 downto 0); 14 | data_y : OUT STD_LOGIC_VECTOR(15 downto 0); 15 | data_z : OUT STD_LOGIC_VECTOR(15 downto 0); 16 | SPI_SDI : OUT STD_LOGIC; 17 | SPI_SDO : IN STD_LOGIC; 18 | SPI_CSN : OUT STD_LOGIC; 19 | SPI_CLK : OUT STD_LOGIC 20 | 21 | ); 22 | 23 | end ADXL345_controller; 24 | 25 | architecture ADXL345_controller_structural of ADXL345_controller is 26 | 27 | component gsensor is port ( 28 | 29 | reset_n : IN STD_LOGIC; 30 | clk : IN STD_LOGIC; 31 | data_valid : OUT STD_LOGIC; 32 | data_x : OUT STD_LOGIC_VECTOR(15 downto 0); 33 | data_y : OUT STD_LOGIC_VECTOR(15 downto 0); 34 | data_z : OUT STD_LOGIC_VECTOR(15 downto 0); 35 | SPI_SDI : OUT STD_LOGIC; 36 | SPI_SDO : IN STD_LOGIC; 37 | SPI_CSN : OUT STD_LOGIC; 38 | SPI_CLK : OUT STD_LOGIC 39 | 40 | ); 41 | 42 | end component; 43 | 44 | begin 45 | 46 | U0 : gsensor port map(reset_n, clk, data_valid, data_x, data_y, data_z, SPI_SDI, SPI_SDO, SPI_CSN, SPI_CLK); 47 | 48 | end ADXL345_controller_structural; 49 | 50 | -------------------------------------------------------------------------------- /base/proj0/ip/binary_to_bcd.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://forum.digikey.com/t/binary-to-bcd-converter-vhdl/12530 2 | 3 | -------------------------------------------------------------------------------- 4 | -- 5 | -- FileName: binary_to_bcd.vhd 6 | -- Dependencies: binary_to_bcd_digit.vhd 7 | -- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition 8 | -- 9 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 10 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 11 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 12 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 13 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 14 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 15 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 16 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 17 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 18 | -- 19 | -- Version History 20 | -- Version 1.0 6/15/2017 Scott Larson 21 | -- Initial Public Release 22 | -- Version 1.1 6/23/2017 Scott Larson 23 | -- Fixed small corner-case bug 24 | -- Version 1.2 1/16/2018 Scott Larson 25 | -- Fixed reset logic to include resetting the state machine 26 | -- 27 | -------------------------------------------------------------------------------- 28 | 29 | LIBRARY ieee; 30 | USE ieee.std_logic_1164.all; 31 | library work; 32 | 33 | ENTITY binary_to_bcd IS 34 | GENERIC( 35 | bits : INTEGER := 10; --size of the binary input numbers in bits 36 | digits : INTEGER := 3); --number of BCD digits to convert to 37 | PORT( 38 | clk : IN STD_LOGIC; --system clock 39 | reset_n : IN STD_LOGIC; --active low asynchronus reset 40 | ena : IN STD_LOGIC; --latches in new binary number and starts conversion 41 | binary : IN STD_LOGIC_VECTOR(bits-1 DOWNTO 0); --binary number to convert 42 | busy : OUT STD_LOGIC; --indicates conversion in progress 43 | bcd : OUT STD_LOGIC_VECTOR(digits*4-1 DOWNTO 0)); --resulting BCD number 44 | END binary_to_bcd; 45 | 46 | ARCHITECTURE logic OF binary_to_bcd IS 47 | TYPE machine IS(idle, convert); --needed states 48 | SIGNAL state : machine; --state machine 49 | SIGNAL binary_reg : STD_LOGIC_VECTOR(bits-1 DOWNTO 0); --latched in binary number 50 | SIGNAL bcd_reg : STD_LOGIC_VECTOR(digits*4-1 DOWNTO 0); --bcd result register 51 | SIGNAL converter_ena : STD_LOGIC; --enable into each BCD single digit converter 52 | SIGNAL converter_inputs : STD_LOGIC_VECTOR(digits DOWNTO 0); --inputs into each BCD single digit converter 53 | 54 | --binary to BCD single digit converter component 55 | COMPONENT binary_to_bcd_digit IS 56 | PORT( 57 | clk : IN STD_LOGIC; 58 | reset_n : IN STD_LOGIC; 59 | ena : IN STD_LOGIC; 60 | binary : IN STD_LOGIC; 61 | c_out : BUFFER STD_LOGIC; 62 | bcd : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); 63 | END COMPONENT binary_to_bcd_digit; 64 | 65 | BEGIN 66 | 67 | PROCESS(reset_n, clk) 68 | VARIABLE bit_count : INTEGER RANGE 0 TO bits+1 := 0; --counts the binary bits shifted into the converters 69 | BEGIN 70 | IF(reset_n = '0') THEN --asynchronous reset asserted 71 | bit_count := 0; --reset bit counter 72 | busy <= '1'; --indicate not available 73 | converter_ena <= '0'; --disable the converter 74 | bcd <= (OTHERS => '0'); --clear BCD result port 75 | state <= idle; --reset state machine 76 | ELSIF(clk'EVENT AND clk = '1') THEN --system clock rising edge 77 | CASE state IS 78 | 79 | WHEN idle => --idle state 80 | IF(ena = '1') THEN --converter is enabled 81 | busy <= '1'; --indicate conversion in progress 82 | converter_ena <= '1'; --enable the converter 83 | binary_reg <= binary; --latch in binary number for conversion 84 | bit_count := 0; --reset bit counter 85 | state <= convert; --go to convert state 86 | ELSE --converter is not enabled 87 | busy <= '0'; --indicate available 88 | converter_ena <= '0'; --disable the converter 89 | state <= idle; --remain in idle state 90 | END IF; 91 | 92 | WHEN convert => --convert state 93 | IF(bit_count < bits+1) THEN --not all bits shifted in 94 | bit_count := bit_count + 1; --increment bit counter 95 | converter_inputs(0) <= binary_reg(bits-1); --shift next bit into converter 96 | binary_reg <= binary_reg(bits-2 DOWNTO 0) & '0'; --shift binary number register 97 | state <= convert; --remain in convert state 98 | ELSE --all bits shifted in 99 | busy <= '0'; --indicate conversion is complete 100 | converter_ena <= '0'; --disable the converter 101 | bcd <= bcd_reg; --output result 102 | state <= idle; --return to idle state 103 | END IF; 104 | 105 | END CASE; 106 | END IF; 107 | END PROCESS; 108 | 109 | --instantiate the converter logic for the specified number of digits 110 | bcd_digits: FOR i IN 1 to digits GENERATE 111 | digit_0: binary_to_bcd_digit 112 | PORT MAP (clk, reset_n, converter_ena, converter_inputs(i-1), converter_inputs(i), bcd_reg(i*4-1 DOWNTO i*4-4)); 113 | END GENERATE; 114 | 115 | END logic; 116 | 117 | -------------------------------------------------------------------------------- /base/proj0/ip/binary_to_bcd_digit.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://forum.digikey.com/t/binary-to-bcd-converter-vhdl/12530 2 | 3 | -------------------------------------------------------------------------------- 4 | -- 5 | -- FileName: binary_to_bcd_digit.vhd 6 | -- Dependencies: none 7 | -- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition 8 | -- 9 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 10 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 11 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 12 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 13 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 14 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 15 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 16 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 17 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 18 | -- 19 | -- Version History 20 | -- Version 1.0 6/15/2017 Scott Larson 21 | -- Initial Public Release 22 | -- 23 | -------------------------------------------------------------------------------- 24 | 25 | LIBRARY ieee; 26 | USE ieee.std_logic_1164.all; 27 | library work; 28 | 29 | ENTITY binary_to_bcd_digit IS 30 | PORT( 31 | clk : IN STD_LOGIC; --system clock 32 | reset_n : IN STD_LOGIC; --active low asynchronous reset 33 | ena : IN STD_LOGIC; --activate operation 34 | binary : IN STD_LOGIC; --bit shifted into digit 35 | c_out : BUFFER STD_LOGIC; --carry out shifted to next larger digit 36 | bcd : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); --resulting BCD output 37 | END binary_to_bcd_digit; 38 | 39 | ARCHITECTURE logic OF binary_to_bcd_digit IS 40 | SIGNAL prev_ena : STD_LOGIC; --keeps track of the previous enable to identify when enable is first asserted 41 | BEGIN 42 | 43 | c_out <= bcd(3) OR (bcd(2) AND bcd(1)) OR (bcd(2) AND bcd(0)); --assert carry out when register value exceeds 4 44 | 45 | PROCESS(reset_n, clk) 46 | BEGIN 47 | IF(reset_n = '0') THEN --asynchronous reset asserted 48 | prev_ena <= '0'; --clear ena history 49 | bcd <= "0000"; --clear output 50 | ELSIF(clk'EVENT AND clk = '1') THEN --rising edge of system clock 51 | prev_ena <= ena; --keep track of last enable 52 | IF(ena = '1') THEN --operation activated 53 | IF(prev_ena = '0') THEN --first cycle of activation 54 | bcd <= "0000"; --initialize the register 55 | ELSIF(c_out = '1') THEN --register value exceeds 4 56 | bcd(0) <= binary; --shift new bit into first register 57 | bcd(1) <= NOT bcd(0); --set second register to adjusted value 58 | bcd(2) <= NOT (bcd(1) XOR bcd(0)); --set third register to adjusted value 59 | bcd(3) <= bcd(3) AND bcd(0); --set fourth register to adjusted value 60 | ELSE --register value does not exceed 4 61 | bcd <= bcd(2 DOWNTO 0) & binary; --shift register values up and shift in new bit 62 | END IF; 63 | END IF; 64 | END IF; 65 | END PROCESS; 66 | 67 | END logic; 68 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/dual_boot.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2020 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and any partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details, at 20 | https://fpgasoftware.intel.com/eula. 21 | */ 22 | (header "symbol" (version "1.1")) 23 | (symbol 24 | (rect 0 0 224 144) 25 | (text "dual_boot" (rect 84 -1 121 11)(font "Arial" (font_size 10))) 26 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 27 | (port 28 | (pt 0 72) 29 | (input) 30 | (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) 31 | (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) 32 | (line (pt 0 72)(pt 80 72)(line_width 1)) 33 | ) 34 | (port 35 | (pt 0 112) 36 | (input) 37 | (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) 38 | (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) 39 | (line (pt 0 112)(pt 80 112)(line_width 1)) 40 | ) 41 | (drawing 42 | (text "clk" (rect 65 43 148 99)(font "Arial" (color 128 0 0)(font_size 9))) 43 | (text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0))) 44 | (text "reset" (rect 51 83 132 179)(font "Arial" (color 128 0 0)(font_size 9))) 45 | (text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0))) 46 | (text " dual_boot " (rect 180 128 426 266)(font "Arial" )) 47 | (line (pt 80 32)(pt 144 32)(line_width 1)) 48 | (line (pt 144 32)(pt 144 128)(line_width 1)) 49 | (line (pt 80 128)(pt 144 128)(line_width 1)) 50 | (line (pt 80 32)(pt 80 128)(line_width 1)) 51 | (line (pt 81 52)(pt 81 76)(line_width 1)) 52 | (line (pt 82 52)(pt 82 76)(line_width 1)) 53 | (line (pt 81 92)(pt 81 116)(line_width 1)) 54 | (line (pt 82 92)(pt 82 116)(line_width 1)) 55 | (line (pt 0 0)(pt 224 0)(line_width 1)) 56 | (line (pt 224 0)(pt 224 144)(line_width 1)) 57 | (line (pt 0 144)(pt 224 144)(line_width 1)) 58 | (line (pt 0 0)(pt 0 144)(line_width 1)) 59 | ) 60 | ) 61 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/dual_boot.cmp: -------------------------------------------------------------------------------- 1 | component dual_boot is 2 | port ( 3 | clk_clk : in std_logic := 'X'; -- clk 4 | reset_reset_n : in std_logic := 'X' -- reset_n 5 | ); 6 | end component dual_boot; 7 | 8 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/dual_boot.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 67 | 68 | 69 | 70 | 71 | 72 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/dual_boot_bb.v: -------------------------------------------------------------------------------- 1 | 2 | module dual_boot ( 3 | clk_clk, 4 | reset_reset_n); 5 | 6 | input clk_clk; 7 | input reset_reset_n; 8 | endmodule 9 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/dual_boot_inst.v: -------------------------------------------------------------------------------- 1 | dual_boot u0 ( 2 | .clk_clk (), // clk.clk 3 | .reset_reset_n () // reset.reset_n 4 | ); 5 | 6 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/dual_boot_inst.vhd: -------------------------------------------------------------------------------- 1 | component dual_boot is 2 | port ( 3 | clk_clk : in std_logic := 'X'; -- clk 4 | reset_reset_n : in std_logic := 'X' -- reset_n 5 | ); 6 | end component dual_boot; 7 | 8 | u0 : component dual_boot 9 | port map ( 10 | clk_clk => CONNECTED_TO_clk_clk, -- clk.clk 11 | reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n 12 | ); 13 | 14 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/synthesis/submodules/altera_dual_boot.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2020 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | module altera_dual_boot 15 | ( 16 | clk, 17 | nreset, 18 | avmm_rcv_address, 19 | avmm_rcv_writedata, 20 | avmm_rcv_write, 21 | avmm_rcv_read, 22 | avmm_rcv_readdata 23 | ); 24 | parameter LPM_TYPE = "ALTERA_DUAL_BOOT"; 25 | parameter INTENDED_DEVICE_FAMILY = "MAX 10 FPGA"; 26 | parameter A_WIDTH = 3; 27 | parameter WD_WIDTH = 4; 28 | parameter RD_WIDTH = 17; 29 | parameter MAX_DATA_WIDTH = 32; 30 | parameter CONFIG_CYCLE = 28; 31 | parameter RESET_TIMER_CYCLE = 40; 32 | 33 | input clk; 34 | input nreset; 35 | input [A_WIDTH-1:0] avmm_rcv_address; 36 | input [MAX_DATA_WIDTH-1:0] avmm_rcv_writedata; 37 | input avmm_rcv_write; 38 | input avmm_rcv_read; 39 | output [MAX_DATA_WIDTH-1:0] avmm_rcv_readdata; 40 | 41 | alt_dual_boot_avmm alt_dual_boot_avmm_comp 42 | ( 43 | .clk(clk), 44 | .nreset(nreset), 45 | .avmm_rcv_address(avmm_rcv_address), 46 | .avmm_rcv_writedata(avmm_rcv_writedata), 47 | .avmm_rcv_write(avmm_rcv_write), 48 | .avmm_rcv_read(avmm_rcv_read), 49 | .avmm_rcv_readdata(avmm_rcv_readdata) 50 | ); 51 | defparam 52 | alt_dual_boot_avmm_comp.LPM_TYPE = LPM_TYPE, 53 | alt_dual_boot_avmm_comp.INTENDED_DEVICE_FAMILY = INTENDED_DEVICE_FAMILY, 54 | alt_dual_boot_avmm_comp.A_WIDTH = A_WIDTH, 55 | alt_dual_boot_avmm_comp.MAX_DATA_WIDTH = MAX_DATA_WIDTH, 56 | alt_dual_boot_avmm_comp.WD_WIDTH = WD_WIDTH, 57 | alt_dual_boot_avmm_comp.RD_WIDTH = RD_WIDTH, 58 | alt_dual_boot_avmm_comp.CONFIG_CYCLE = CONFIG_CYCLE, 59 | alt_dual_boot_avmm_comp.RESET_TIMER_CYCLE = RESET_TIMER_CYCLE; 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/synthesis/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2020 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/synthesis/submodules/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2020 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/20.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2019/10/06 $ 17 | // $Author: psgswbuild $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/base/proj0/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot.v -------------------------------------------------------------------------------- /base/proj0/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot_avmm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/base/proj0/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot_avmm.v -------------------------------------------------------------------------------- /base/proj0/ip/single_port_ram.vhd: -------------------------------------------------------------------------------- 1 | -- Quartus Prime VHDL Template 2 | -- Single port RAM with single read/write address 3 | 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | 7 | -- vgaText 8 | library work; 9 | use work.commonPak.all; 10 | 11 | entity single_port_ram is 12 | 13 | generic 14 | ( 15 | DATA_WIDTH : natural := 8; 16 | ADDR_WIDTH : natural := 6 17 | ); 18 | 19 | port 20 | ( 21 | clk : in std_logic; 22 | addr : in natural range 0 to 2**ADDR_WIDTH - 1; 23 | data : in std_logic_vector((DATA_WIDTH-1) downto 0); 24 | we : in std_logic := '1'; 25 | q : out std_logic_vector((DATA_WIDTH -1) downto 0) 26 | ); 27 | 28 | end entity; 29 | 30 | architecture rtl of single_port_ram is 31 | 32 | -- Build a 2-D array type for the RAM 33 | subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); 34 | type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; 35 | 36 | -- Declare the RAM signal. 37 | signal ram : memory_t; 38 | 39 | -- Register to hold the address 40 | signal addr_reg : natural range 0 to 2**ADDR_WIDTH-1; 41 | 42 | begin 43 | 44 | process(clk) 45 | begin 46 | if(rising_edge(clk)) then 47 | if(we = '1') then 48 | ram(addr) <= data; 49 | end if; 50 | 51 | -- Register the address for reading 52 | addr_reg <= addr; 53 | end if; 54 | end process; 55 | 56 | q <= ram(addr_reg); 57 | 58 | end rtl; 59 | -------------------------------------------------------------------------------- /base/proj0/ip/vgaText/basicBlockRAM.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | ---------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 11:42:49 11/26/2013 8 | -- Design Name: 9 | -- Module Name: textLineRAM - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | ---------------------------------------------------------------------------------- 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | -- note this line.The package is compiled to this directory by default. 35 | -- so don't forget to include this directory. 36 | library work; 37 | -- this line also is must.This includes the particular package into your program. 38 | use work.commonPak.all; 39 | 40 | entity basicBlockRAM is 41 | generic( 42 | numElements: integer := 128; 43 | dataWidth: integer := 8 44 | ); 45 | port( 46 | clkA: in std_logic; 47 | writeEnableA: in std_logic; 48 | addrA: in std_logic_vector(log2_float(numElements-1) downto 0); 49 | dataOutA: out std_logic_vector(dataWidth-1 downto 0); 50 | dataInA: in std_logic_vector(dataWidth-1 downto 0) 51 | ); 52 | end basicBlockRAM; 53 | 54 | architecture Behavioral of basicBlockRAM is 55 | type rom_type is array (0 to numElements-1) of std_logic_vector(dataWidth-1 downto 0); 56 | signal RAM: rom_type := (others => (others => '0')); 57 | begin 58 | -- addr register to infer block RAM 59 | setRegA: process (clkA) 60 | begin 61 | if rising_edge(clkA) then 62 | -- Write to rom 63 | if(writeEnableA = '1') then 64 | RAM(to_integer(unsigned(addrA))) <= dataInA; 65 | end if; 66 | -- Read from it 67 | dataOutA <= RAM(to_integer(unsigned(addrA))); 68 | end if; 69 | end process; 70 | end Behavioral; 71 | 72 | -------------------------------------------------------------------------------- /base/proj0/ip/vgaText/commonPak.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -- 4 | -- Package File Template 5 | -- 6 | -- Purpose: This package defines supplemental types, subtypes, 7 | -- constants, and functions 8 | -- 9 | -- To use any of the example code shown below, uncomment the lines and modify as necessary 10 | -- 11 | 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.all; 14 | 15 | use ieee.math_real.all; 16 | 17 | package commonPak is 18 | 19 | 20 | 21 | constant ADDR_WIDTH : integer := 11; 22 | constant DATA_WIDTH : integer := 8; 23 | 24 | constant FONT_WIDTH : integer := 8; 25 | constant FONT_HEIGHT : integer := 16; 26 | 27 | constant c_max_color_vga : integer := 4095; 28 | 29 | 30 | ------------------------------------------ 31 | 32 | type point_2d is 33 | record 34 | x : integer; 35 | y : integer; 36 | end record; 37 | 38 | type type_textColorMap is array(natural range <>) of integer range 0 to c_max_color_vga; 39 | 40 | 41 | ------------------------------------------ 42 | 43 | 44 | type type_drawElement is 45 | record 46 | pixelOn: boolean; 47 | rgb: integer range 0 to c_max_color_vga; 48 | end record; 49 | constant init_type_drawElement: type_drawElement := (pixelOn => false, rgb => 0); 50 | type type_drawElementArray is array(natural range <>) of type_drawElement; 51 | 52 | 53 | 54 | ------------------------------------------ 55 | 56 | type type_inArbiterPort is 57 | record 58 | dataRequest: boolean; 59 | addr: std_logic_vector(ADDR_WIDTH-1 downto 0); 60 | writeRequest: boolean; 61 | writeData: std_logic_vector(DATA_WIDTH-1 downto 0); 62 | end record; 63 | constant init_type_inArbiterPort: type_inArbiterPort := (dataRequest => false, addr => (others => '0'), writeRequest => false, writeData => (others => '0')); 64 | type type_inArbiterPortArray is array(natural range <>) of type_inArbiterPort; 65 | 66 | 67 | type type_outArbiterPort is 68 | record 69 | dataWaiting: boolean; 70 | data: std_logic_vector(DATA_WIDTH-1 downto 0); 71 | dataWritten: boolean; 72 | end record; 73 | constant init_type_outArbiterPort: type_outArbiterPort := (dataWaiting => false, data => (others => '0'), dataWritten => false); 74 | type type_outArbiterPortArray is array(natural range <>) of type_outArbiterPort; 75 | 76 | 77 | ---------------------- 78 | 79 | function log2_float(val : positive) return natural; 80 | 81 | end commonPak; 82 | 83 | package body commonPak is 84 | function log2_float(val : positive) return natural is 85 | begin 86 | return integer(ceil(log2(real(val)))); 87 | end function; 88 | end commonPak; 89 | -------------------------------------------------------------------------------- /base/proj0/ip/vgaText/tb_and_ex/tb_vgaText1.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:04:49 07/12/2013 8 | -- Design Name: 9 | -- Module Name: D:/Libraries/EE/FPGA/Basys 2/vgaText/tb_vgaText1.vhd 10 | -- Project Name: vgaText 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: vgaText_top 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | USE std.textio.ALL; 33 | 34 | -- Uncomment the following library declaration if using 35 | -- arithmetic functions with Signed or Unsigned values 36 | --USE ieee.numeric_std.ALL; 37 | 38 | ENTITY tb_vgaText1 IS 39 | END tb_vgaText1; 40 | 41 | ARCHITECTURE behavior OF tb_vgaText1 IS 42 | 43 | -- Component Declaration for the Unit Under Test (UUT) 44 | 45 | COMPONENT vgaText_top 46 | PORT( 47 | clk : IN std_logic; 48 | reset : IN std_logic; 49 | Led : OUT std_logic_vector(7 downto 0); 50 | hsync : OUT std_logic; 51 | vsync : OUT std_logic; 52 | Red : OUT std_logic_vector(2 downto 0); 53 | Green : OUT std_logic_vector(2 downto 0); 54 | Blue : OUT std_logic_vector(2 downto 1) 55 | ); 56 | END COMPONENT; 57 | 58 | 59 | --Inputs 60 | signal clk : std_logic := '0'; 61 | signal reset : std_logic := '0'; 62 | 63 | --Outputs 64 | signal Led : std_logic_vector(7 downto 0); 65 | signal hsync : std_logic; 66 | signal vsync : std_logic; 67 | signal Red : std_logic_vector(2 downto 0); 68 | signal Green : std_logic_vector(2 downto 0); 69 | signal Blue : std_logic_vector(2 downto 1); 70 | 71 | -- Clock period definitions 72 | constant clk_period : time := 10 ns; 73 | 74 | BEGIN 75 | 76 | -- Instantiate the Unit Under Test (UUT) 77 | uut: vgaText_top PORT MAP ( 78 | clk => clk, 79 | reset => reset, 80 | Led => Led, 81 | hsync => hsync, 82 | vsync => vsync, 83 | Red => Red, 84 | Green => Green, 85 | Blue => Blue 86 | ); 87 | 88 | -- Clock process definitions 89 | clk_process :process 90 | begin 91 | clk <= '0'; 92 | wait for clk_period/2; 93 | clk <= '1'; 94 | wait for clk_period/2; 95 | end process; 96 | 97 | 98 | -- Stimulus process 99 | stim_proc: process 100 | --file textFile: text; 101 | begin 102 | --file_open(textFile, "textMemory.txt,", write_mode); 103 | 104 | -- hold reset state for 100 ns. 105 | wait for 100 ns; 106 | 107 | wait for clk_period*10; 108 | 109 | -- insert stimulus here 110 | --writeline(textFile, buf_in); 111 | reset <= '1'; 112 | wait for 1 ms; 113 | reset <= '0'; 114 | 115 | wait; 116 | end process; 117 | 118 | END; 119 | -------------------------------------------------------------------------------- /base/proj0/ip/vgaText/tb_and_ex/tb_vgaText2.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 14:07:14 11/19/2013 8 | -- Design Name: 9 | -- Module Name: D:/Libraries/EE/FPGA/Basys 2/vgaText/tb_vgaText2.vhd 10 | -- Project Name: vgaText 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: vgaText_top 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY tb_vgaText2 IS 38 | END tb_vgaText2; 39 | 40 | ARCHITECTURE behavior OF tb_vgaText2 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT vgaText_top 45 | PORT( 46 | clk : IN std_logic; 47 | reset : IN std_logic; 48 | Led : OUT std_logic_vector(7 downto 0); 49 | hsync : OUT std_logic; 50 | vsync : OUT std_logic; 51 | Red : OUT std_logic_vector(2 downto 0); 52 | Green : OUT std_logic_vector(2 downto 0); 53 | Blue : OUT std_logic_vector(2 downto 1) 54 | ); 55 | END COMPONENT; 56 | 57 | 58 | --Inputs 59 | signal clk : std_logic := '0'; 60 | signal reset : std_logic := '0'; 61 | 62 | --Outputs 63 | signal Led : std_logic_vector(7 downto 0); 64 | signal hsync : std_logic; 65 | signal vsync : std_logic; 66 | signal Red : std_logic_vector(2 downto 0); 67 | signal Green : std_logic_vector(2 downto 0); 68 | signal Blue : std_logic_vector(2 downto 1); 69 | 70 | -- Clock period definitions 71 | constant clk_period : time := 10 ns; 72 | 73 | BEGIN 74 | 75 | -- Instantiate the Unit Under Test (UUT) 76 | uut: vgaText_top PORT MAP ( 77 | clk => clk, 78 | reset => reset, 79 | Led => Led, 80 | hsync => hsync, 81 | vsync => vsync, 82 | Red => Red, 83 | Green => Green, 84 | Blue => Blue 85 | ); 86 | 87 | -- Clock process definitions 88 | clk_process :process 89 | begin 90 | clk <= '0'; 91 | wait for clk_period/2; 92 | clk <= '1'; 93 | wait for clk_period/2; 94 | end process; 95 | 96 | 97 | -- Stimulus process 98 | stim_proc: process 99 | begin 100 | -- hold reset state for 100 ns. 101 | wait for 100 ns; 102 | 103 | wait for clk_period*10; 104 | 105 | -- insert stimulus here 106 | reset <= '1'; 107 | wait for 1 ms; 108 | reset <= '0'; 109 | 110 | wait; 111 | end process; 112 | 113 | END; 114 | -------------------------------------------------------------------------------- /base/proj0/ip/vgaText/tb_and_ex/tb_vgaText3.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 23:04:02 11/25/2013 8 | -- Design Name: 9 | -- Module Name: D:/Libraries/EE/FPGA/Basys 2/vgaText/tb_vgaText3.vhd 10 | -- Project Name: vgaText 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: vgaText_top 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | use IEEE.std_logic_textio.all; 34 | use std.textio.all; 35 | 36 | -- Uncomment the following library declaration if using 37 | -- arithmetic functions with Signed or Unsigned values 38 | USE ieee.numeric_std.ALL; 39 | 40 | 41 | ENTITY tb_vgaText3 IS 42 | END tb_vgaText3; 43 | 44 | ARCHITECTURE behavior OF tb_vgaText3 IS 45 | 46 | -- Component Declaration for the Unit Under Test (UUT) 47 | 48 | COMPONENT vgaText_top 49 | PORT( 50 | clk : IN std_logic; 51 | reset : IN std_logic; 52 | Led : OUT std_logic_vector(7 downto 0); 53 | hsync : OUT std_logic; 54 | vsync : OUT std_logic; 55 | Red : OUT std_logic_vector(2 downto 0); 56 | Green : OUT std_logic_vector(2 downto 0); 57 | Blue : OUT std_logic_vector(2 downto 1) 58 | ); 59 | END COMPONENT; 60 | 61 | 62 | --Inputs 63 | signal clk : std_logic := '0'; 64 | signal reset : std_logic := '0'; 65 | 66 | --Outputs 67 | signal Led : std_logic_vector(7 downto 0); 68 | signal hsync : std_logic; 69 | signal vsync : std_logic; 70 | signal Red : std_logic_vector(2 downto 0); 71 | signal Green : std_logic_vector(2 downto 0); 72 | signal Blue : std_logic_vector(2 downto 1); 73 | 74 | -- Clock period definitions 75 | constant clk_period : time := 20 ns; 76 | 77 | BEGIN 78 | 79 | -- Instantiate the Unit Under Test (UUT) 80 | uut: vgaText_top PORT MAP ( 81 | clk => clk, 82 | reset => reset, 83 | Led => Led, 84 | hsync => hsync, 85 | vsync => vsync, 86 | Red => Red, 87 | Green => Green, 88 | Blue => Blue 89 | ); 90 | 91 | -- Clock process definitions 92 | clk_process :process 93 | begin 94 | clk <= '0'; 95 | wait for clk_period/2; 96 | clk <= '1'; 97 | wait for clk_period/2; 98 | end process; 99 | 100 | 101 | -- Stimulus process 102 | stim_proc: process 103 | begin 104 | -- hold reset state for 100 ns. 105 | wait for 100 ns; 106 | 107 | wait for clk_period*10; 108 | 109 | -- insert stimulus here 110 | reset <= '1'; 111 | wait for 100 ns; 112 | reset <= '0'; 113 | 114 | 115 | wait; 116 | end process; 117 | 118 | 119 | 120 | 121 | 122 | --Write process 123 | process (clk) 124 | file file_pointer: text is out "write.txt"; 125 | variable line_el: line; 126 | begin 127 | 128 | if rising_edge(clk) then 129 | 130 | --line_el := "1"; 131 | 132 | -- Write the time 133 | write(line_el, now); --write the line. 134 | write(line_el, ":"); --write the line. 135 | --writeline(file_pointer, line_el); --write the contents into the file. 136 | 137 | -- Write the hsync 138 | write(line_el, " "); 139 | write(line_el, hsync); --write the line. 140 | --writeline(file_pointer, line_el); --write the contents into the file. 141 | 142 | -- Write the vsync 143 | write(line_el, " "); 144 | write(line_el, vsync); --write the line. 145 | --writeline(file_pointer, line_el); --write the contents into the file. 146 | 147 | -- Write the red 148 | write(line_el, " "); 149 | write(line_el, Red); --write the line. 150 | --writeline(file_pointer, line_el); --write the contents into the file. 151 | 152 | -- Write the green 153 | write(line_el, " "); 154 | write(line_el, Green); --write the line. 155 | --writeline(file_pointer, line_el); --write the contents into the file. 156 | 157 | -- Write the blue 158 | write(line_el, " "); 159 | write(line_el, Blue); --write the line. 160 | 161 | writeline(file_pointer, line_el); --write the contents into the file. 162 | 163 | 164 | end if; 165 | end process; 166 | 167 | 168 | END; 169 | -------------------------------------------------------------------------------- /base/proj0/ip/vga_controller.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://forum.digikey.com/t/vga-controller-vhdl/12794 2 | 3 | -------------------------------------------------------------------------------- 4 | -- 5 | -- FileName: vga_controller.vhd 6 | -- Dependencies: none 7 | -- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version 8 | -- 9 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 10 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 11 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 12 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 13 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 14 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 15 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 16 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 17 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 18 | -- 19 | -- Version History 20 | -- Version 1.0 05/10/2013 Scott Larson 21 | -- Initial Public Release 22 | -- Version 1.1 03/07/2018 Scott Larson 23 | -- Corrected two minor "off-by-one" errors 24 | -- 25 | -------------------------------------------------------------------------------- 26 | 27 | LIBRARY ieee; 28 | USE ieee.std_logic_1164.all; 29 | library work; 30 | 31 | ENTITY vga_controller IS 32 | GENERIC( 33 | h_pulse : INTEGER := 96; --horiztonal sync pulse width in pixels 34 | h_bp : INTEGER := 48; --horiztonal back porch width in pixels 35 | h_pixels : INTEGER := 640; --horiztonal display width in pixels 36 | h_fp : INTEGER := 16; --horiztonal front porch width in pixels 37 | h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative) 38 | v_pulse : INTEGER := 2; --vertical sync pulse width in rows 39 | v_bp : INTEGER := 33; --vertical back porch width in rows 40 | v_pixels : INTEGER := 480; --vertical display width in rows 41 | v_fp : INTEGER := 10; --vertical front porch width in rows 42 | v_pol : STD_LOGIC := '0'); --vertical sync pulse polarity (1 = positive, 0 = negative) 43 | PORT( 44 | pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used 45 | reset_n : IN STD_LOGIC; --active low asycnchronous reset 46 | h_sync : OUT STD_LOGIC; --horiztonal sync pulse 47 | v_sync : OUT STD_LOGIC; --vertical sync pulse 48 | disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time) 49 | column : OUT INTEGER range 0 to h_pixels-1; --horizontal pixel coordinate 50 | row : OUT INTEGER range 0 to v_pixels-1; --vertical pixel coordinate 51 | n_blank : OUT STD_LOGIC; --direct blacking output to DAC 52 | n_sync : OUT STD_LOGIC); --sync-on-green output to DAC 53 | END vga_controller; 54 | 55 | ARCHITECTURE behavior OF vga_controller IS 56 | CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row 57 | CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column 58 | BEGIN 59 | 60 | n_blank <= '1'; --no direct blanking 61 | n_sync <= '0'; --no sync on green 62 | 63 | PROCESS(pixel_clk, reset_n) 64 | VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns) 65 | VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows) 66 | BEGIN 67 | 68 | IF(reset_n = '0') THEN --reset asserted 69 | h_count := 0; --reset horizontal counter 70 | v_count := 0; --reset vertical counter 71 | h_sync <= NOT h_pol; --deassert horizontal sync 72 | v_sync <= NOT v_pol; --deassert vertical sync 73 | disp_ena <= '0'; --disable display 74 | column <= 0; --reset column pixel coordinate 75 | row <= 0; --reset row pixel coordinate 76 | 77 | ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN 78 | 79 | --counters 80 | IF(h_count < h_period - 1) THEN --horizontal counter (pixels) 81 | h_count := h_count + 1; 82 | ELSE 83 | h_count := 0; 84 | IF(v_count < v_period - 1) THEN --veritcal counter (rows) 85 | v_count := v_count + 1; 86 | ELSE 87 | v_count := 0; 88 | END IF; 89 | END IF; 90 | 91 | --horizontal sync signal 92 | IF(h_count < h_pixels + h_fp OR h_count >= h_pixels + h_fp + h_pulse) THEN 93 | h_sync <= NOT h_pol; --deassert horiztonal sync pulse 94 | ELSE 95 | h_sync <= h_pol; --assert horiztonal sync pulse 96 | END IF; 97 | 98 | --vertical sync signal 99 | IF(v_count < v_pixels + v_fp OR v_count >= v_pixels + v_fp + v_pulse) THEN 100 | v_sync <= NOT v_pol; --deassert vertical sync pulse 101 | ELSE 102 | v_sync <= v_pol; --assert vertical sync pulse 103 | END IF; 104 | 105 | --set pixel coordinates 106 | IF(h_count < h_pixels) THEN --horiztonal display time 107 | column <= h_count; --set horiztonal pixel coordinate 108 | END IF; 109 | IF(v_count < v_pixels) THEN --vertical display time 110 | row <= v_count; --set vertical pixel coordinate 111 | END IF; 112 | 113 | --set display enable output 114 | IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time 115 | disp_ena <= '1'; --enable display 116 | ELSE --blanking time 117 | disp_ena <= '0'; --disable display 118 | END IF; 119 | 120 | END IF; 121 | END PROCESS; 122 | 123 | END behavior; -------------------------------------------------------------------------------- /base/proj0/lfsr8.vhd: -------------------------------------------------------------------------------- 1 | -- 8-Bit Linear Feedback Shift Register (lfsr8) 2 | library IEEE; 3 | USE IEEE.std_logic_1164.all; 4 | library work; 5 | 6 | -- For vgaText library 7 | use work.commonPak.all; 8 | -- Common constants 9 | use work.defender_common.all; 10 | 11 | ENTITY lfsr8 IS 12 | PORT ( clock, reset, load, cnt_en : IN STD_LOGIC; 13 | par_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Parallel load 14 | value_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); 15 | END lfsr8; 16 | 17 | ARCHITECTURE behavior OF lfsr8 IS 18 | -- Types 19 | 20 | -- Component declarations 21 | 22 | -- Signal declarations 23 | SIGNAL msb_in : STD_LOGIC; 24 | SIGNAL value : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '1'); -- Internal register 25 | 26 | BEGIN 27 | 28 | PROCESS (clock) BEGIN 29 | 30 | -- Clocked behavior 31 | IF (rising_edge(clock)) THEN 32 | 33 | -- Synch reset 34 | if (reset = '1') THEN 35 | value <= (OTHERS => '1'); -- All 1's is the start state, all 0's is the lockup state 36 | elsif (load = '1') THEN 37 | value <= par_in; 38 | elsif (cnt_en = '1') then 39 | value <= (msb_in & value(7 DOWNTO 1)); -- Shift msb_in from the left 40 | END IF; 41 | 42 | END IF; 43 | 44 | END PROCESS; 45 | 46 | -- Calculate msb_in from tapped positions 47 | PROCESS (value) BEGIN 48 | 49 | -- taps: 8 6 5 4; feedback polynomial: x^8 + x^6 + x^5 + x^4 + 1 50 | -- these taps correspond to bit ordering: 1 to 8, L to R 51 | msb_in <= (value(0) XOR value(2) XOR value(3) XOR value(4)); 52 | 53 | END PROCESS; 54 | 55 | -- Instantiation AND port mapping 56 | 57 | -- Concurrent assignments 58 | value_out <= value; 59 | 60 | END behavior; 61 | 62 | -------------------------------------------------------------------------------- /base/proj0/proj0.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition 22 | # Date created = 11:20:21 October 29, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.1" 27 | DATE = "11:20:21 October 29, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "proj0" 32 | -------------------------------------------------------------------------------- /base/proj0/proj0.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /base/proj0/proj0_top.vhd: -------------------------------------------------------------------------------- 1 | -- proj0: Base "FPGA Defender" game 2 | -- Authors: Garrett Carter & Tyler McCormick 3 | -- Top level entity 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | use ieee.numeric_std.all; 7 | library work; 8 | 9 | -- For vgaText library 10 | use work.commonPak.all; 11 | -- Common constants 12 | use work.defender_common.all; 13 | 14 | entity proj0_top is 15 | PORT( 16 | KEY : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 17 | SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 18 | MAX10_CLK1_50 : IN STD_LOGIC; -- 50 MHz clock input 19 | LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); 20 | ARDUINO_IO : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); 21 | HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 22 | -- Accelerometer I/O 23 | GSENSOR_CS_N : OUT STD_LOGIC; 24 | GSENSOR_SCLK : OUT STD_LOGIC; 25 | GSENSOR_SDI : INOUT STD_LOGIC; 26 | GSENSOR_SDO : INOUT STD_LOGIC; 27 | 28 | -- VGA I/O 29 | VGA_HS : OUT STD_LOGIC; -- horizontal sync pulse 30 | VGA_VS : OUT STD_LOGIC; -- vertical sync pulse 31 | 32 | VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); -- red magnitude output to DAC 33 | VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); -- green magnitude output to DAC 34 | VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0') -- blue magnitude output to DAC 35 | ); 36 | end proj0_top; 37 | 38 | architecture top_level of proj0_top is 39 | 40 | -- Constants 41 | 42 | -- Component declarations 43 | component vga_pll_25_175 is 44 | port( 45 | inclk0 : IN STD_LOGIC := '0'; -- Input clock that gets divided (50 MHz for max10) 46 | c0 : OUT STD_LOGIC -- Output clock for vga timing (25.175 MHz) 47 | ); 48 | end component; 49 | 50 | COMPONENT ADXL345_controller IS 51 | PORT( reset_n : IN STD_LOGIC; 52 | clk : IN STD_LOGIC; 53 | data_valid : OUT STD_LOGIC; 54 | data_x : OUT STD_LOGIC_VECTOR(15 downto 0); 55 | data_y : OUT STD_LOGIC_VECTOR(15 downto 0); 56 | data_z : OUT STD_LOGIC_VECTOR(15 downto 0); 57 | SPI_SDI : OUT STD_LOGIC; 58 | SPI_SDO : IN STD_LOGIC; 59 | SPI_CSN : OUT STD_LOGIC; 60 | SPI_CLK : OUT STD_LOGIC ); 61 | END COMPONENT; 62 | 63 | COMPONENT accel_proc is 64 | port ( 65 | -- Raw data from accelerometer 66 | data_x : IN STD_LOGIC_VECTOR(15 downto 0); 67 | data_y : IN STD_LOGIC_VECTOR(15 downto 0); 68 | data_valid : IN STD_LOGIC; 69 | 70 | -- Direction of tilt 71 | -- x+ : left, x- : right 72 | -- y+ : forward, y- : backward 73 | accel_scale_x, accel_scale_y : OUT integer := 0 -- A scaled version of data 74 | ); 75 | end COMPONENT; 76 | 77 | component dual_boot is 78 | port ( 79 | clk_clk : in std_logic := 'X'; -- clk 80 | reset_reset_n : in std_logic := 'X' -- reset_n 81 | ); 82 | end component; 83 | 84 | -- Signal declarations 85 | SIGNAL KEY_b : STD_LOGIC_VECTOR(1 DOWNTO 0); 86 | signal clk_25_175_MHz, disp_en : STD_LOGIC; 87 | signal row : integer range 0 to c_screen_height-1; 88 | signal column : INTEGER range 0 to c_screen_width-1; 89 | 90 | -- Accelerometer 91 | signal data_x, data_y : STD_LOGIC_VECTOR(15 DOWNTO 0); 92 | signal data_valid : STD_LOGIC; 93 | signal accel_scale_x, accel_scale_y : integer; 94 | 95 | begin 96 | 97 | -- Concurrent assignments 98 | KEY_b <= NOT KEY; 99 | 100 | -- Instantiation and port mapping 101 | 102 | -- Dual boot 103 | U7 : dual_boot port map ( clk_clk => MAX10_CLK1_50, reset_reset_n => '1' ); 104 | 105 | -- VGA 106 | U8 : vga_pll_25_175 port map (inclk0 => MAX10_CLK1_50, c0 => clk_25_175_MHz); 107 | U9 : entity work.vga_controller port map (pixel_clk => clk_25_175_MHz, reset_n => '1', h_sync => VGA_HS, v_sync => VGA_VS, disp_ena => disp_en, column => column, row => row, n_blank => open, n_sync => open); 108 | 109 | -- Accel 110 | U10 : ADXL345_controller PORT MAP (reset_n => '1', clk => MAX10_CLK1_50, data_valid => data_valid, data_x => data_x, data_y => data_y, data_z => open, SPI_SDI => GSENSOR_SDI, SPI_SDO => GSENSOR_SDO, SPI_CSN => GSENSOR_CS_N, SPI_CLK => GSENSOR_SCLK ); 111 | U11 : accel_proc PORT MAP ( data_x => data_x, data_y => data_y, data_valid => data_valid, accel_scale_x => accel_scale_x, accel_scale_y => accel_scale_y ); 112 | 113 | -- Game Logic 114 | U12 : entity work.image_gen port map ( 115 | pixel_clk => clk_25_175_MHz, 116 | disp_en => disp_en, 117 | row => row, 118 | column => column, 119 | red => VGA_R, 120 | green => VGA_G, 121 | blue => VGA_B, 122 | 123 | accel_scale_x => accel_scale_x, 124 | accel_scale_y => accel_scale_y, 125 | KEY => KEY, 126 | SW => SW, 127 | 128 | o_buzzPin => ARDUINO_IO(12), 129 | HEX5 => HEX5, HEX4 => HEX4, HEX3 => HEX3, HEX2 => HEX2, HEX1 => HEX1, HEX0 => HEX0, 130 | LEDR => LEDR 131 | ); 132 | 133 | end top_level; -------------------------------------------------------------------------------- /base/proj0/sound_effects/clock_div.vhd: -------------------------------------------------------------------------------- 1 | -- Configurable n-bit clock divider (clock_div) 2 | LIBRARY IEEE; 3 | USE IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | library work; 6 | 7 | ENTITY clock_div IS 8 | GENERIC (n : NATURAL := 8); 9 | PORT ( clock_in, reset : IN STD_LOGIC; 10 | divisor : IN STD_LOGIC_VECTOR(n DOWNTO 0); -- divisor = 2*(max_cnt+1) 11 | clock_out : OUT STD_LOGIC ); 12 | END clock_div; 13 | 14 | ARCHITECTURE behavior OF clock_div IS 15 | -- Constants 16 | 17 | -- Types 18 | 19 | -- Component declarations 20 | 21 | -- Signal declarations 22 | SIGNAL count : STD_LOGIC_VECTOR(n-1 DOWNTO 0); -- Internal counter 23 | SIGNAL max_cnt : STD_LOGIC_VECTOR(n-1 DOWNTO 0); 24 | SIGNAL temp_clock : STD_LOGIC := '0'; 25 | 26 | BEGIN 27 | 28 | max_cnt <= (divisor(n DOWNTO 1) - '1'); -- Bit shift right (div by 2) then sub 1 29 | 30 | PROCESS (clock_in, reset) BEGIN 31 | 32 | -- Asynch reset 33 | IF (reset = '1') THEN 34 | count <= (OTHERS => '0'); 35 | temp_clock <= '0'; 36 | 37 | -- Clocked behavior 38 | ELSIF (clock_in'event AND clock_in = '1') THEN 39 | 40 | IF (count >= max_cnt) THEN 41 | temp_clock <= NOT temp_clock; 42 | count <= (OTHERS => '0'); 43 | ELSE 44 | count <= count + '1'; 45 | END IF; 46 | 47 | END IF; 48 | 49 | END PROCESS; 50 | 51 | -- Instantiation AND port mapping 52 | 53 | -- Concurrent assignments 54 | clock_out <= temp_clock; 55 | 56 | END behavior; -------------------------------------------------------------------------------- /base/proj0/sound_effects/effect_gen_tb.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /effect_gen_tb/reset_n 4 | add wave -noupdate /effect_gen_tb/test_clk 5 | add wave -noupdate /effect_gen_tb/effect_cmd 6 | add wave -noupdate /effect_gen_tb/buzz_out 7 | add wave -noupdate /effect_gen_tb/UUT/r_state 8 | add wave -noupdate -radix hexadecimal /effect_gen_tb/UUT/r_romAddr 9 | add wave -noupdate -radix unsigned /effect_gen_tb/UUT/w_romData 10 | add wave -noupdate /effect_gen_tb/UUT/r_buzzDisable 11 | add wave -noupdate -radix hexadecimal /effect_gen_tb/UUT/r_buzzDivisor 12 | TreeUpdate [SetDefaultTree] 13 | WaveRestoreCursors {{Cursor 1} {1000 ps} 0} 14 | quietly wave cursor active 1 15 | configure wave -namecolwidth 236 16 | configure wave -valuecolwidth 100 17 | configure wave -justifyvalue left 18 | configure wave -signalnamewidth 0 19 | configure wave -snapdistance 10 20 | configure wave -datasetprefix 0 21 | configure wave -rowmargin 4 22 | configure wave -childrowmargin 2 23 | configure wave -gridoffset 0 24 | configure wave -gridperiod 1 25 | configure wave -griddelta 40 26 | configure wave -timeline 0 27 | configure wave -timelineunits ns 28 | update 29 | WaveRestoreZoom {0 ps} {194325 ps} 30 | run 4000 ns -------------------------------------------------------------------------------- /base/proj0/sound_effects/effect_gen_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Testbench for effect_gen 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.all; 4 | 5 | ENTITY effect_gen_tb IS 6 | END effect_gen_tb; 7 | 8 | ARCHITECTURE behavior OF effect_gen_tb IS 9 | 10 | -- Component declarations 11 | component effect_gen is 12 | port ( 13 | i_clock : in std_logic; 14 | i_reset_n : in std_logic; 15 | 16 | i_launch : in std_logic; 17 | i_playerFire : in std_logic; 18 | i_enemyFire : in std_logic; 19 | i_enemyDestroy : in std_logic; 20 | i_playerDestroy : in std_logic; 21 | 22 | o_buzzPin : out std_logic 23 | ); 24 | end component; 25 | 26 | -- Constants 27 | CONSTANT clock_period: TIME := 20 ns; -- 50 MHz 28 | 29 | -- Signal declarations 30 | signal reset_n : std_logic; 31 | SIGNAL test_clk : STD_LOGIC; 32 | signal effect_cmd : std_logic_vector(4 downto 0); 33 | signal buzz_out : std_logic; 34 | 35 | BEGIN 36 | 37 | -- Instantiation and port mapping 38 | UUT : effect_gen port map ( 39 | i_clock => test_clk, 40 | i_reset_n => reset_n, 41 | 42 | i_launch => effect_cmd(0), 43 | i_playerFire => effect_cmd(1), 44 | i_enemyFire => effect_cmd(2), 45 | i_enemyDestroy => effect_cmd(3), 46 | i_playerDestroy => effect_cmd(4), 47 | 48 | o_buzzPin => buzz_out 49 | ); 50 | 51 | 52 | clock_process: PROCESS 53 | BEGIN 54 | test_clk <= '0'; 55 | WAIT FOR clock_period/2; 56 | test_clk <= '1'; 57 | WAIT FOR clock_period/2; 58 | END PROCESS; 59 | 60 | vectors: PROCESS 61 | BEGIN 62 | reset_n <= '0'; 63 | WAIT FOR 20 ns; 64 | reset_n <= '1'; 65 | effect_cmd <= "00001"; 66 | wait for 100 ns; 67 | WAIT; 68 | END PROCESS; 69 | 70 | 71 | END; 72 | -------------------------------------------------------------------------------- /base/proj0/sound_effects/effect_mem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2020 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and any partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details, at 14 | --https://fpgasoftware.intel.com/eula. 15 | 16 | 17 | component effect_mem 18 | PORT 19 | ( 20 | address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 21 | clock : IN STD_LOGIC := '1'; 22 | q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) 23 | ); 24 | end component; 25 | -------------------------------------------------------------------------------- /base/proj0/sound_effects/effect_mem.mif: -------------------------------------------------------------------------------- 1 | DEPTH = 1024; 2 | WIDTH = 12; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = UNS; 5 | CONTENT 6 | BEGIN 7 | -- Effect program (8 effect slots): 8 | -- n = # of steps (63 max) 9 | -- Step 0...n-1 : freq (hz) and duration (msec) (12 bits each) 10 | 11 | -- Effect 0 : Launch (10 ramp segments of inc max freq, each ramp is 6 steps, 44 msec each) 12 | 000: 60; 13 | 14 | -- Ramp 1 15 | 001: 400; 16 | 002: 44; 17 | 18 | 003: 520; 19 | 004: 44; 20 | 21 | 005: 640; 22 | 006: 44; 23 | 24 | 007: 760; 25 | 008: 44; 26 | 27 | 009: 880; 28 | 00A: 44; 29 | 30 | 00B: 1000; 31 | 00C: 44; 32 | 33 | -- Ramp 2 34 | 00D: 400; 35 | 00E: 44; 36 | 37 | 00F: 587; 38 | 010: 44; 39 | 40 | 011: 773; 41 | 012: 44; 42 | 43 | 013: 960; 44 | 014: 44; 45 | 46 | 015: 1146; 47 | 016: 44; 48 | 49 | 017: 1333; 50 | 018: 44; 51 | 52 | -- Ramp 3 53 | 019: 400; 54 | 01A: 44; 55 | 56 | 01B: 653; 57 | 01C: 44; 58 | 59 | 01D: 906; 60 | 01E: 44; 61 | 62 | 01F: 1160; 63 | 020: 44; 64 | 65 | 021: 1413; 66 | 022: 44; 67 | 68 | 023: 1666; 69 | 024: 44; 70 | 71 | -- Ramp 4 72 | 025: 400; 73 | 026: 44; 74 | 75 | 027: 720; 76 | 028: 44; 77 | 78 | 029: 1040; 79 | 02A: 44; 80 | 81 | 02B: 1360; 82 | 02C: 44; 83 | 84 | 02D: 1680; 85 | 02E: 44; 86 | 87 | 02F: 2000; 88 | 030: 44; 89 | 90 | 91 | -- Ramp 5 92 | 031: 400; 93 | 032: 44; 94 | 95 | 033: 787; 96 | 034: 44; 97 | 98 | 035: 1173; 99 | 036: 44; 100 | 101 | 037: 1560; 102 | 038: 44; 103 | 104 | 039: 1946; 105 | 03A: 44; 106 | 107 | 03B: 2333; 108 | 03C: 44; 109 | 110 | -- Ramp 6 111 | 03D: 400; 112 | 03E: 44; 113 | 114 | 03F: 853; 115 | 040: 44; 116 | 117 | 041: 1306; 118 | 042: 44; 119 | 120 | 043: 1760; 121 | 044: 44; 122 | 123 | 045: 2213; 124 | 046: 44; 125 | 126 | 047: 2666; 127 | 048: 44; 128 | 129 | -- Ramp 7 130 | 049: 400; 131 | 04A: 44; 132 | 133 | 04B: 920; 134 | 04C: 44; 135 | 136 | 04D: 1440; 137 | 04E: 44; 138 | 139 | 04F: 1960; 140 | 050: 44; 141 | 142 | 051: 2480; 143 | 052: 44; 144 | 145 | 053: 3000; 146 | 054: 44; 147 | 148 | -- Ramp 8 149 | 055: 400; 150 | 056: 44; 151 | 152 | 057: 987; 153 | 058: 44; 154 | 155 | 059: 1573; 156 | 05A: 44; 157 | 158 | 05B: 2160; 159 | 05C: 44; 160 | 161 | 05D: 2746; 162 | 05E: 44; 163 | 164 | 05F: 3333; 165 | 060: 44; 166 | 167 | 168 | -- Ramp 9 169 | 061: 400; 170 | 062: 44; 171 | 172 | 063: 1053; 173 | 064: 44; 174 | 175 | 065: 1706; 176 | 066: 44; 177 | 178 | 067: 2360; 179 | 068: 44; 180 | 181 | 069: 3013; 182 | 06A: 44; 183 | 184 | 06B: 3666; 185 | 06C: 44; 186 | 187 | -- Ramp 10 188 | 06D: 400; 189 | 06E: 44; 190 | 191 | 06F: 1120; 192 | 070: 44; 193 | 194 | 071: 1840; 195 | 072: 44; 196 | 197 | 073: 2560; 198 | 074: 44; 199 | 200 | 075: 3280; 201 | 076: 44; 202 | 203 | 077: 4000; 204 | 078: 44; 205 | 206 | 207 | -- Unused 208 | 079: 50; 209 | 07A: 511; 210 | 211 | 07B: 60; 212 | 07C: 511; 213 | 214 | 07D: 70; 215 | 07E: 511; 216 | 217 | 07F: 80; 218 | 219 | -- Effect 1 : Player fire (Ramp down w/ static?) 220 | 080: 12; 221 | 222 | 081: 511; -- Step 0: 10 Hz for 511 msec 223 | 082: 50; 224 | 225 | 083: 475; 226 | 084: 50; 227 | 228 | 085: 450; 229 | 086: 50; 230 | 231 | 087: 425; 232 | 088: 50; 233 | 234 | 089: 400; 235 | 08A: 50; 236 | 237 | 08B: 375; 238 | 08C: 50; 239 | 240 | 08D: 350; 241 | 08E: 50; 242 | 243 | 08F: 300; 244 | 090: 50; 245 | 246 | 091: 250; 247 | 092: 50; 248 | 249 | 093: 200; 250 | 094: 50; 251 | 252 | 095: 150; 253 | 096: 50; 254 | 255 | 097: 100; 256 | 098: 50; 257 | 258 | 259 | -- Effect 2 : Enemy fire (Ramp down, diff range/speed) 260 | 100: 9; 261 | 262 | 101: 400; -- Step 0: 10 Hz for 511 msec 263 | 102: 50; 264 | 265 | 103: 375; 266 | 104: 50; 267 | 268 | 105: 350; 269 | 106: 50; 270 | 271 | 107: 325; 272 | 108: 50; 273 | 274 | 109: 300; 275 | 10A: 50; 276 | 277 | 10B: 250; 278 | 10C: 50; 279 | 280 | 10D: 200; 281 | 10E: 50; 282 | 283 | 10F: 150; 284 | 110: 50; 285 | 286 | 111: 100; 287 | 112: 50; 288 | 289 | -- Effect 3 : Enemy destroy (ramp up) 290 | 180: 12; 291 | 292 | 181: 100; -- Step 0: 10 Hz for 511 msec 293 | 182: 50; 294 | 295 | 183: 125; 296 | 184: 50; 297 | 298 | 185: 150; 299 | 186: 50; 300 | 301 | 187: 175; 302 | 188: 50; 303 | 304 | 189: 200; 305 | 18A: 50; 306 | 307 | 18B: 225; 308 | 18C: 50; 309 | 310 | 18D: 250; 311 | 18E: 50; 312 | 313 | 18F: 300; 314 | 190: 50; 315 | 316 | 191: 350; 317 | 192: 50; 318 | 319 | 193: 400; 320 | 194: 50; 321 | 322 | 195: 475; 323 | 196: 50; 324 | 325 | 197: 511; 326 | 198: 50; 327 | 328 | -- Effect 4 : Player destroy (static explosion or "waa-waa-waa :(" ) 329 | 200: 12; 330 | 331 | 201: 500; -- Step 0: 10 Hz for 511 msec 332 | 202: 100; 333 | 334 | 203: 250; 335 | 204: 100; 336 | 337 | 205: 500; 338 | 206: 100; 339 | 340 | 207: 250; 341 | 208: 100; 342 | 343 | 209: 400; 344 | 20A: 100; 345 | 346 | 20B: 200; 347 | 20C: 100; 348 | 349 | 20D: 400; 350 | 20E: 100; 351 | 352 | 20F: 200; 353 | 210: 100; 354 | 355 | 211: 300; 356 | 212: 100; 357 | 358 | 213: 150; 359 | 214: 100; 360 | 361 | 215: 300; 362 | 216: 100; 363 | 364 | 217: 150; 365 | 218: 100; 366 | 367 | 368 | 369 | -- Effect 5 370 | 280:10; 371 | 372 | -- Effect 6 373 | 300:10; 374 | 375 | -- Effect 7 376 | 380:10; 377 | END; 378 | -------------------------------------------------------------------------------- /base/proj0/sound_effects/effect_mem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "20.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "effect_mem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "effect_mem.cmp"] 6 | -------------------------------------------------------------------------------- /base/proj0/sound_effects/effect_mem.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %ROM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: effect_mem.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 20.1.1 Build 720 11/11/2020 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2020 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and any partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details, at 34 | --https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | LIBRARY ieee; 38 | USE ieee.std_logic_1164.all; 39 | 40 | LIBRARY altera_mf; 41 | USE altera_mf.altera_mf_components.all; 42 | 43 | ENTITY effect_mem IS 44 | PORT 45 | ( 46 | address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 47 | clock : IN STD_LOGIC := '1'; 48 | q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) 49 | ); 50 | END effect_mem; 51 | 52 | 53 | ARCHITECTURE SYN OF effect_mem IS 54 | 55 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0); 56 | 57 | BEGIN 58 | q <= sub_wire0(11 DOWNTO 0); 59 | 60 | altsyncram_component : altsyncram 61 | GENERIC MAP ( 62 | address_aclr_a => "NONE", 63 | clock_enable_input_a => "BYPASS", 64 | clock_enable_output_a => "BYPASS", 65 | init_file => "./effect_mem.mif", 66 | intended_device_family => "MAX 10", 67 | lpm_hint => "ENABLE_RUNTIME_MOD=NO", 68 | lpm_type => "altsyncram", 69 | numwords_a => 1024, 70 | operation_mode => "ROM", 71 | outdata_aclr_a => "NONE", 72 | outdata_reg_a => "UNREGISTERED", 73 | widthad_a => 10, 74 | width_a => 12, 75 | width_byteena_a => 1 76 | ) 77 | PORT MAP ( 78 | address_a => address, 79 | clock0 => clock, 80 | q_a => sub_wire0 81 | ); 82 | 83 | 84 | 85 | END SYN; 86 | 87 | -- ============================================================ 88 | -- CNX file retrieval info 89 | -- ============================================================ 90 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 91 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 92 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 93 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 94 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 95 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 96 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 97 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 98 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 99 | -- Retrieval info: PRIVATE: Clken NUMERIC "0" 100 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 101 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 102 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 103 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" 104 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 105 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 106 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 107 | -- Retrieval info: PRIVATE: MIFfilename STRING "../effect_mem.mif" 108 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" 109 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 110 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 111 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 112 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 113 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 114 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 115 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" 116 | -- Retrieval info: PRIVATE: WidthData NUMERIC "12" 117 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 118 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 119 | -- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 120 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 121 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 122 | -- Retrieval info: CONSTANT: INIT_FILE STRING "../effect_mem.mif" 123 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" 124 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 125 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 126 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" 127 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 128 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 129 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 130 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" 131 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "12" 132 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 133 | -- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" 134 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 135 | -- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]" 136 | -- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 137 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 138 | -- Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0 139 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.vhd TRUE 140 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.inc FALSE 141 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.cmp TRUE 142 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.bsf FALSE 143 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem_inst.vhd FALSE 144 | -- Retrieval info: LIB_FILE: altera_mf 145 | -------------------------------------------------------------------------------- /base/proj0/sound_effects/effect_mem_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Testbench for effect_mem 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.all; 4 | use ieee.NUMERIC_STD.all; 5 | 6 | ENTITY effect_mem_tb IS 7 | END effect_mem_tb; 8 | 9 | ARCHITECTURE behavior OF effect_mem_tb IS 10 | 11 | -- Component declarations 12 | component effect_mem is 13 | port 14 | ( 15 | address : in std_logic_vector (9 downto 0); 16 | clock : in std_logic := '1'; 17 | q : out std_logic_vector (8 downto 0) 18 | ); 19 | end component; 20 | 21 | -- Constants 22 | CONSTANT clock_period: TIME := 20 ns; -- 50 MHz 23 | 24 | -- Signal declarations 25 | signal reset_n : std_logic; 26 | SIGNAL test_clk : STD_LOGIC; 27 | signal mem_addr : std_logic_vector(9 downto 0); 28 | signal mem_data : std_logic_vector(8 downto 0); 29 | 30 | BEGIN 31 | 32 | -- Instantiation and port mapping 33 | UUT : effect_mem port map ( 34 | address => mem_addr, 35 | clock => test_clk, 36 | 37 | q => mem_data 38 | 39 | ); 40 | 41 | 42 | clock_process: PROCESS 43 | BEGIN 44 | test_clk <= '0'; 45 | WAIT FOR clock_period/2; 46 | test_clk <= '1'; 47 | WAIT FOR clock_period/2; 48 | END PROCESS; 49 | 50 | vectors: PROCESS 51 | BEGIN 52 | mem_addr <= "00" & X"00"; 53 | WAIT FOR 80 ns; 54 | mem_addr <= "00" & X"01"; 55 | WAIT FOR 80 ns; 56 | mem_addr <= "00" & X"02"; 57 | WAIT FOR 80 ns; 58 | mem_addr <= "00" & X"03"; 59 | WAIT FOR 80 ns; 60 | mem_addr <= "00" & X"04"; 61 | WAIT FOR 80 ns; 62 | mem_addr <= "00" & X"05"; 63 | WAIT FOR 80 ns; 64 | mem_addr <= "00" & X"06"; 65 | WAIT FOR 80 ns; 66 | 67 | WAIT; 68 | END PROCESS; 69 | 70 | 71 | END; 72 | -------------------------------------------------------------------------------- /base/proj0/triangle.vhd: -------------------------------------------------------------------------------- 1 | -- triangle: A circuit to render a triangle 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | library work; 6 | 7 | -- For vgaText library 8 | use work.commonPak.all; 9 | -- Common constants 10 | use work.defender_common.all; 11 | 12 | entity triangle is 13 | generic ( 14 | g_width : integer := 30; 15 | g_height : integer := 20 16 | ); 17 | port ( 18 | i_row : in integer range 0 to c_screen_height-1; 19 | i_column : in integer range 0 to c_screen_width-1; 20 | i_xPos : in integer; 21 | i_yPos : in integer; 22 | 23 | o_draw : out std_logic 24 | ); 25 | end entity triangle; 26 | 27 | architecture rtl of triangle is 28 | 29 | begin 30 | -- Set draw output 31 | process(i_row, i_column, i_xPos, i_yPos) 32 | begin 33 | 34 | if (i_column >= i_xPos and i_column <= i_xPos+g_width and i_row >= i_yPos and i_row <= i_yPos+g_height) and -- Inside Rectangle 35 | (i_row > ((i_column - i_xPos) * g_height / g_width) + i_yPos) then -- Below hypotenuse of triangle 36 | 37 | o_draw <= '1'; 38 | else 39 | o_draw <= '0'; 40 | end if; 41 | end process; 42 | end architecture rtl; -------------------------------------------------------------------------------- /bonuses/proj1/accel_proc.vhd: -------------------------------------------------------------------------------- 1 | -- accel_proc: Accelerometer data processing 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.NUMERIC_STD.all; 5 | 6 | entity accel_proc is 7 | generic( 8 | 9 | -- Top value for input range 10 | g_in_max_val : integer := 1; 11 | -- Top value for output range 12 | g_out_max_val : integer := 1 13 | 14 | ); 15 | port ( 16 | -- Raw data from accelerometer 17 | data_x : IN STD_LOGIC_VECTOR(15 downto 0); 18 | data_y : IN STD_LOGIC_VECTOR(15 downto 0); 19 | data_valid : IN STD_LOGIC; 20 | 21 | -- Direction of tilt 22 | -- x+ : left, x- : right 23 | -- y+ : forward, y- : backward 24 | accel_scale_x, accel_scale_y : OUT integer := 0 -- A scaled version of data 25 | ); 26 | end accel_proc; 27 | 28 | ARCHITECTURE behavior OF accel_proc IS 29 | 30 | -- Component declarations 31 | 32 | -- Signal declarations 33 | 34 | BEGIN 35 | 36 | -- Processes 37 | process(data_x, data_y, data_valid) 38 | begin 39 | 40 | -- Sample new data if it's valid, or hold old data 41 | if (data_valid = '1') then 42 | accel_scale_x <= to_integer(signed(data_x))*g_out_max_val/g_in_max_val; 43 | accel_scale_y <= to_integer(signed(data_y))*g_out_max_val/g_in_max_val; 44 | end if; 45 | 46 | end process; 47 | 48 | 49 | 50 | -- Instantiation and port mapping 51 | 52 | -- Concurrent assignments 53 | 54 | 55 | 56 | END behavior; 57 | 58 | -------------------------------------------------------------------------------- /bonuses/proj1/async_rom_init.vhd: -------------------------------------------------------------------------------- 1 | -- async_rom_init: asynchronous ROM with initial values. 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | library work; 7 | use work.defender_common.all; 8 | 9 | entity async_rom_init is 10 | generic( 11 | numElements: integer := 128; 12 | dataWidth: integer := 8; 13 | initFile: string := "ram.mif" 14 | ); 15 | port( 16 | addrA: in std_logic_vector(ceil_log2(numElements)-1 downto 0); 17 | dataOutA: out std_logic_vector(dataWidth-1 downto 0) 18 | ); 19 | end async_rom_init; 20 | 21 | architecture Behavioral of async_rom_init is 22 | type rom_type is array (0 to numElements-1) of std_logic_vector(dataWidth-1 downto 0); 23 | signal ROM: rom_type; 24 | attribute ram_init_file : string; 25 | attribute ram_init_file of ROM : signal is initFile; 26 | 27 | begin 28 | dataOutA <= ROM(to_integer(unsigned(addrA))); 29 | end Behavioral; 30 | 31 | -------------------------------------------------------------------------------- /bonuses/proj1/bin2seg7.vhd: -------------------------------------------------------------------------------- 1 | -- bin2seg7: Binary to 7-segment decoder, active low outputs for DE10-Lite 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | library work; 5 | 6 | -- Your block has a four bit input inData(3 downto 0), 7 | -- a blanking bit input (no segments illuminated, or blank, WHEN blanking is high), 8 | -- a dispHex bit input (show 0-0xF WHEN dispHex is high, else show only 0-9 blanking for 0xA-0xF), 9 | -- and dispPoint bit input (illuminate the "decimal point" WHEN high). 10 | -- Your block has eight output bits. Seven bits segA, segB, ..., segG correspond to a segment on the display, while segPoint controls the corresponding "decimal point". 11 | ENTITY bin2seg7 IS 12 | PORT ( inData : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 13 | blanking : IN STD_LOGIC; 14 | dispHex : IN STD_LOGIC; 15 | dispPoint : IN STD_LOGIC; 16 | dispDash : IN STD_LOGIC; 17 | 18 | -- DP, G, F, E, D, C, B, A 19 | outSegs : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); 20 | END bin2seg7; 21 | 22 | ARCHITECTURE behavior OF bin2seg7 IS 23 | 24 | -- Component declarations 25 | 26 | -- Signal declarations 27 | SIGNAL outSegsTmp : STD_LOGIC_VECTOR(7 DOWNTO 0); 28 | 29 | BEGIN 30 | 31 | -- Processes 32 | PROCESS (inData, blanking, dispHex, dispPoint, dispDash) IS 33 | BEGIN 34 | 35 | -- Decimal digits 36 | IF (dispHex = '0') THEN 37 | CASE inData IS 38 | -- inData | DP, G, F, E, D, C, B, A 39 | WHEN "0000" => outSegsTmp <= "00111111"; 40 | WHEN "0001" => outSegsTmp <= "00000110"; 41 | WHEN "0010" => outSegsTmp <= "01011011"; 42 | WHEN "0011" => outSegsTmp <= "01001111"; 43 | WHEN "0100" => outSegsTmp <= "01100110"; 44 | WHEN "0101" => outSegsTmp <= "01101101"; 45 | WHEN "0110" => outSegsTmp <= "01111101"; 46 | WHEN "0111" => outSegsTmp <= "00000111"; 47 | WHEN "1000" => outSegsTmp <= "01111111"; 48 | WHEN "1001" => outSegsTmp <= "01100111"; 49 | 50 | WHEN "1010" => outSegsTmp <= "00000000"; 51 | WHEN "1011" => outSegsTmp <= "00000000"; 52 | WHEN "1100" => outSegsTmp <= "00000000"; 53 | WHEN "1101" => outSegsTmp <= "00000000"; 54 | WHEN "1110" => outSegsTmp <= "00000000"; 55 | WHEN "1111" => outSegsTmp <= "00000000"; 56 | 57 | WHEN OTHERS => outSegsTmp <= "00000000"; 58 | END CASE; 59 | 60 | -- Hex digits 61 | ELSE 62 | CASE inData IS 63 | -- inData | DP, G, F, E, D, C, B, A 64 | WHEN "0000" => outSegsTmp <= "00111111"; 65 | WHEN "0001" => outSegsTmp <= "00000110"; 66 | WHEN "0010" => outSegsTmp <= "01011011"; 67 | WHEN "0011" => outSegsTmp <= "01001111"; 68 | WHEN "0100" => outSegsTmp <= "01100110"; 69 | WHEN "0101" => outSegsTmp <= "01101101"; 70 | WHEN "0110" => outSegsTmp <= "01111101"; 71 | WHEN "0111" => outSegsTmp <= "00000111"; 72 | WHEN "1000" => outSegsTmp <= "01111111"; 73 | WHEN "1001" => outSegsTmp <= "01100111"; 74 | 75 | WHEN "1010" => outSegsTmp <= "01110111"; 76 | WHEN "1011" => outSegsTmp <= "01111100"; 77 | WHEN "1100" => outSegsTmp <= "00111001"; 78 | WHEN "1101" => outSegsTmp <= "01011110"; 79 | WHEN "1110" => outSegsTmp <= "01111001"; 80 | WHEN "1111" => outSegsTmp <= "01110001"; 81 | 82 | WHEN OTHERS => outSegsTmp <= "00000000"; 83 | END CASE; 84 | END IF; 85 | 86 | -- Handle decimal point 87 | IF (dispPoint = '1') THEN 88 | outSegsTmp(7) <= '1'; 89 | ELSE 90 | outSegsTmp(7) <= '0'; 91 | END IF; 92 | 93 | -- Handle dash 94 | IF (dispDash = '1') THEN 95 | outSegsTmp <= "01000000"; -- g only 96 | END IF; 97 | 98 | -- Handle blanking 99 | IF (blanking = '1') THEN 100 | outSegsTmp <= "00000000"; 101 | END IF; 102 | 103 | END PROCESS; 104 | 105 | -- Instantiation and port mapping 106 | 107 | -- Concurrent assignments 108 | outSegs <= (NOT outSegsTmp); -- Active low segment outputs 109 | 110 | 111 | END behavior; 112 | 113 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/ADXL345_controller.vhd: -------------------------------------------------------------------------------- 1 | -- Component for interfacing with the ADXL345 accelerometer. This is really just a wrapper for a verilog controller that actually does the work. 2 | 3 | 4 | library IEEE; 5 | use IEEE.STD_LOGIC_1164.ALL; 6 | 7 | entity ADXL345_controller is 8 | 9 | port ( 10 | 11 | reset_n : IN STD_LOGIC; 12 | clk : IN STD_LOGIC; 13 | data_valid : OUT STD_LOGIC; 14 | data_x : OUT STD_LOGIC_VECTOR(15 downto 0); 15 | data_y : OUT STD_LOGIC_VECTOR(15 downto 0); 16 | data_z : OUT STD_LOGIC_VECTOR(15 downto 0); 17 | SPI_SDI : OUT STD_LOGIC; 18 | SPI_SDO : IN STD_LOGIC; 19 | SPI_CSN : OUT STD_LOGIC; 20 | SPI_CLK : OUT STD_LOGIC 21 | 22 | ); 23 | 24 | end ADXL345_controller; 25 | 26 | architecture ADXL345_controller_structural of ADXL345_controller is 27 | 28 | component gsensor is port ( 29 | 30 | reset_n : IN STD_LOGIC; 31 | clk : IN STD_LOGIC; 32 | data_valid : OUT STD_LOGIC; 33 | data_x : OUT STD_LOGIC_VECTOR(15 downto 0); 34 | data_y : OUT STD_LOGIC_VECTOR(15 downto 0); 35 | data_z : OUT STD_LOGIC_VECTOR(15 downto 0); 36 | SPI_SDI : OUT STD_LOGIC; 37 | SPI_SDO : IN STD_LOGIC; 38 | SPI_CSN : OUT STD_LOGIC; 39 | SPI_CLK : OUT STD_LOGIC 40 | 41 | ); 42 | 43 | end component; 44 | 45 | begin 46 | 47 | U0 : gsensor port map(reset_n, clk, data_valid, data_x, data_y, data_z, SPI_SDI, SPI_SDO, SPI_CSN, SPI_CLK); 48 | 49 | end ADXL345_controller_structural; 50 | 51 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/binary_to_bcd.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://forum.digikey.com/t/binary-to-bcd-converter-vhdl/12530 2 | 3 | -------------------------------------------------------------------------------- 4 | -- 5 | -- FileName: binary_to_bcd.vhd 6 | -- Dependencies: binary_to_bcd_digit.vhd 7 | -- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition 8 | -- 9 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 10 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 11 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 12 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 13 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 14 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 15 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 16 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 17 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 18 | -- 19 | -- Version History 20 | -- Version 1.0 6/15/2017 Scott Larson 21 | -- Initial Public Release 22 | -- Version 1.1 6/23/2017 Scott Larson 23 | -- Fixed small corner-case bug 24 | -- Version 1.2 1/16/2018 Scott Larson 25 | -- Fixed reset logic to include resetting the state machine 26 | -- 27 | -------------------------------------------------------------------------------- 28 | 29 | LIBRARY ieee; 30 | USE ieee.std_logic_1164.all; 31 | library work; 32 | 33 | ENTITY binary_to_bcd IS 34 | GENERIC( 35 | bits : INTEGER := 10; --size of the binary input numbers in bits 36 | digits : INTEGER := 3); --number of BCD digits to convert to 37 | PORT( 38 | clk : IN STD_LOGIC; --system clock 39 | reset_n : IN STD_LOGIC; --active low asynchronus reset 40 | ena : IN STD_LOGIC; --latches in new binary number and starts conversion 41 | binary : IN STD_LOGIC_VECTOR(bits-1 DOWNTO 0); --binary number to convert 42 | busy : OUT STD_LOGIC; --indicates conversion in progress 43 | bcd : OUT STD_LOGIC_VECTOR(digits*4-1 DOWNTO 0)); --resulting BCD number 44 | END binary_to_bcd; 45 | 46 | ARCHITECTURE logic OF binary_to_bcd IS 47 | TYPE machine IS(idle, convert); --needed states 48 | SIGNAL state : machine; --state machine 49 | SIGNAL binary_reg : STD_LOGIC_VECTOR(bits-1 DOWNTO 0); --latched in binary number 50 | SIGNAL bcd_reg : STD_LOGIC_VECTOR(digits*4-1 DOWNTO 0); --bcd result register 51 | SIGNAL converter_ena : STD_LOGIC; --enable into each BCD single digit converter 52 | SIGNAL converter_inputs : STD_LOGIC_VECTOR(digits DOWNTO 0); --inputs into each BCD single digit converter 53 | 54 | --binary to BCD single digit converter component 55 | COMPONENT binary_to_bcd_digit IS 56 | PORT( 57 | clk : IN STD_LOGIC; 58 | reset_n : IN STD_LOGIC; 59 | ena : IN STD_LOGIC; 60 | binary : IN STD_LOGIC; 61 | c_out : BUFFER STD_LOGIC; 62 | bcd : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); 63 | END COMPONENT binary_to_bcd_digit; 64 | 65 | BEGIN 66 | 67 | PROCESS(reset_n, clk) 68 | VARIABLE bit_count : INTEGER RANGE 0 TO bits+1 := 0; --counts the binary bits shifted into the converters 69 | BEGIN 70 | IF(reset_n = '0') THEN --asynchronous reset asserted 71 | bit_count := 0; --reset bit counter 72 | busy <= '1'; --indicate not available 73 | converter_ena <= '0'; --disable the converter 74 | bcd <= (OTHERS => '0'); --clear BCD result port 75 | state <= idle; --reset state machine 76 | ELSIF(clk'EVENT AND clk = '1') THEN --system clock rising edge 77 | CASE state IS 78 | 79 | WHEN idle => --idle state 80 | IF(ena = '1') THEN --converter is enabled 81 | busy <= '1'; --indicate conversion in progress 82 | converter_ena <= '1'; --enable the converter 83 | binary_reg <= binary; --latch in binary number for conversion 84 | bit_count := 0; --reset bit counter 85 | state <= convert; --go to convert state 86 | ELSE --converter is not enabled 87 | busy <= '0'; --indicate available 88 | converter_ena <= '0'; --disable the converter 89 | state <= idle; --remain in idle state 90 | END IF; 91 | 92 | WHEN convert => --convert state 93 | IF(bit_count < bits+1) THEN --not all bits shifted in 94 | bit_count := bit_count + 1; --increment bit counter 95 | converter_inputs(0) <= binary_reg(bits-1); --shift next bit into converter 96 | binary_reg <= binary_reg(bits-2 DOWNTO 0) & '0'; --shift binary number register 97 | state <= convert; --remain in convert state 98 | ELSE --all bits shifted in 99 | busy <= '0'; --indicate conversion is complete 100 | converter_ena <= '0'; --disable the converter 101 | bcd <= bcd_reg; --output result 102 | state <= idle; --return to idle state 103 | END IF; 104 | 105 | END CASE; 106 | END IF; 107 | END PROCESS; 108 | 109 | --instantiate the converter logic for the specified number of digits 110 | bcd_digits: FOR i IN 1 to digits GENERATE 111 | digit_0: binary_to_bcd_digit 112 | PORT MAP (clk, reset_n, converter_ena, converter_inputs(i-1), converter_inputs(i), bcd_reg(i*4-1 DOWNTO i*4-4)); 113 | END GENERATE; 114 | 115 | END logic; 116 | 117 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/binary_to_bcd_digit.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://forum.digikey.com/t/binary-to-bcd-converter-vhdl/12530 2 | 3 | -------------------------------------------------------------------------------- 4 | -- 5 | -- FileName: binary_to_bcd_digit.vhd 6 | -- Dependencies: none 7 | -- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition 8 | -- 9 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY 10 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT 11 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 12 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY 13 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL 14 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF 15 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 16 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), 17 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. 18 | -- 19 | -- Version History 20 | -- Version 1.0 6/15/2017 Scott Larson 21 | -- Initial Public Release 22 | -- 23 | -------------------------------------------------------------------------------- 24 | 25 | LIBRARY ieee; 26 | USE ieee.std_logic_1164.all; 27 | library work; 28 | 29 | ENTITY binary_to_bcd_digit IS 30 | PORT( 31 | clk : IN STD_LOGIC; --system clock 32 | reset_n : IN STD_LOGIC; --active low asynchronous reset 33 | ena : IN STD_LOGIC; --activate operation 34 | binary : IN STD_LOGIC; --bit shifted into digit 35 | c_out : BUFFER STD_LOGIC; --carry out shifted to next larger digit 36 | bcd : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); --resulting BCD output 37 | END binary_to_bcd_digit; 38 | 39 | ARCHITECTURE logic OF binary_to_bcd_digit IS 40 | SIGNAL prev_ena : STD_LOGIC; --keeps track of the previous enable to identify when enable is first asserted 41 | BEGIN 42 | 43 | c_out <= bcd(3) OR (bcd(2) AND bcd(1)) OR (bcd(2) AND bcd(0)); --assert carry out when register value exceeds 4 44 | 45 | PROCESS(reset_n, clk) 46 | BEGIN 47 | IF(reset_n = '0') THEN --asynchronous reset asserted 48 | prev_ena <= '0'; --clear ena history 49 | bcd <= "0000"; --clear output 50 | ELSIF(clk'EVENT AND clk = '1') THEN --rising edge of system clock 51 | prev_ena <= ena; --keep track of last enable 52 | IF(ena = '1') THEN --operation activated 53 | IF(prev_ena = '0') THEN --first cycle of activation 54 | bcd <= "0000"; --initialize the register 55 | ELSIF(c_out = '1') THEN --register value exceeds 4 56 | bcd(0) <= binary; --shift new bit into first register 57 | bcd(1) <= NOT bcd(0); --set second register to adjusted value 58 | bcd(2) <= NOT (bcd(1) XOR bcd(0)); --set third register to adjusted value 59 | bcd(3) <= bcd(3) AND bcd(0); --set fourth register to adjusted value 60 | ELSE --register value does not exceed 4 61 | bcd <= bcd(2 DOWNTO 0) & binary; --shift register values up and shift in new bit 62 | END IF; 63 | END IF; 64 | END IF; 65 | END PROCESS; 66 | 67 | END logic; 68 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/dual_boot.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2020 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and any partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details, at 20 | https://fpgasoftware.intel.com/eula. 21 | */ 22 | (header "symbol" (version "1.1")) 23 | (symbol 24 | (rect 0 0 224 144) 25 | (text "dual_boot" (rect 84 -1 121 11)(font "Arial" (font_size 10))) 26 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 27 | (port 28 | (pt 0 72) 29 | (input) 30 | (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) 31 | (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) 32 | (line (pt 0 72)(pt 80 72)(line_width 1)) 33 | ) 34 | (port 35 | (pt 0 112) 36 | (input) 37 | (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) 38 | (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) 39 | (line (pt 0 112)(pt 80 112)(line_width 1)) 40 | ) 41 | (drawing 42 | (text "clk" (rect 65 43 148 99)(font "Arial" (color 128 0 0)(font_size 9))) 43 | (text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0))) 44 | (text "reset" (rect 51 83 132 179)(font "Arial" (color 128 0 0)(font_size 9))) 45 | (text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0))) 46 | (text " dual_boot " (rect 180 128 426 266)(font "Arial" )) 47 | (line (pt 80 32)(pt 144 32)(line_width 1)) 48 | (line (pt 144 32)(pt 144 128)(line_width 1)) 49 | (line (pt 80 128)(pt 144 128)(line_width 1)) 50 | (line (pt 80 32)(pt 80 128)(line_width 1)) 51 | (line (pt 81 52)(pt 81 76)(line_width 1)) 52 | (line (pt 82 52)(pt 82 76)(line_width 1)) 53 | (line (pt 81 92)(pt 81 116)(line_width 1)) 54 | (line (pt 82 92)(pt 82 116)(line_width 1)) 55 | (line (pt 0 0)(pt 224 0)(line_width 1)) 56 | (line (pt 224 0)(pt 224 144)(line_width 1)) 57 | (line (pt 0 144)(pt 224 144)(line_width 1)) 58 | (line (pt 0 0)(pt 0 144)(line_width 1)) 59 | ) 60 | ) 61 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/dual_boot.cmp: -------------------------------------------------------------------------------- 1 | component dual_boot is 2 | port ( 3 | clk_clk : in std_logic := 'X'; -- clk 4 | reset_reset_n : in std_logic := 'X' -- reset_n 5 | ); 6 | end component dual_boot; 7 | 8 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/dual_boot.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 67 | 68 | 69 | 70 | 71 | 72 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/dual_boot_bb.v: -------------------------------------------------------------------------------- 1 | 2 | module dual_boot ( 3 | clk_clk, 4 | reset_reset_n); 5 | 6 | input clk_clk; 7 | input reset_reset_n; 8 | endmodule 9 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/dual_boot_inst.v: -------------------------------------------------------------------------------- 1 | dual_boot u0 ( 2 | .clk_clk (), // clk.clk 3 | .reset_reset_n () // reset.reset_n 4 | ); 5 | 6 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/dual_boot_inst.vhd: -------------------------------------------------------------------------------- 1 | component dual_boot is 2 | port ( 3 | clk_clk : in std_logic := 'X'; -- clk 4 | reset_reset_n : in std_logic := 'X' -- reset_n 5 | ); 6 | end component dual_boot; 7 | 8 | u0 : component dual_boot 9 | port map ( 10 | clk_clk => CONNECTED_TO_clk_clk, -- clk.clk 11 | reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n 12 | ); 13 | 14 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/synthesis/submodules/altera_dual_boot.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2020 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | module altera_dual_boot 15 | ( 16 | clk, 17 | nreset, 18 | avmm_rcv_address, 19 | avmm_rcv_writedata, 20 | avmm_rcv_write, 21 | avmm_rcv_read, 22 | avmm_rcv_readdata 23 | ); 24 | parameter LPM_TYPE = "ALTERA_DUAL_BOOT"; 25 | parameter INTENDED_DEVICE_FAMILY = "MAX 10 FPGA"; 26 | parameter A_WIDTH = 3; 27 | parameter WD_WIDTH = 4; 28 | parameter RD_WIDTH = 17; 29 | parameter MAX_DATA_WIDTH = 32; 30 | parameter CONFIG_CYCLE = 28; 31 | parameter RESET_TIMER_CYCLE = 40; 32 | 33 | input clk; 34 | input nreset; 35 | input [A_WIDTH-1:0] avmm_rcv_address; 36 | input [MAX_DATA_WIDTH-1:0] avmm_rcv_writedata; 37 | input avmm_rcv_write; 38 | input avmm_rcv_read; 39 | output [MAX_DATA_WIDTH-1:0] avmm_rcv_readdata; 40 | 41 | alt_dual_boot_avmm alt_dual_boot_avmm_comp 42 | ( 43 | .clk(clk), 44 | .nreset(nreset), 45 | .avmm_rcv_address(avmm_rcv_address), 46 | .avmm_rcv_writedata(avmm_rcv_writedata), 47 | .avmm_rcv_write(avmm_rcv_write), 48 | .avmm_rcv_read(avmm_rcv_read), 49 | .avmm_rcv_readdata(avmm_rcv_readdata) 50 | ); 51 | defparam 52 | alt_dual_boot_avmm_comp.LPM_TYPE = LPM_TYPE, 53 | alt_dual_boot_avmm_comp.INTENDED_DEVICE_FAMILY = INTENDED_DEVICE_FAMILY, 54 | alt_dual_boot_avmm_comp.A_WIDTH = A_WIDTH, 55 | alt_dual_boot_avmm_comp.MAX_DATA_WIDTH = MAX_DATA_WIDTH, 56 | alt_dual_boot_avmm_comp.WD_WIDTH = WD_WIDTH, 57 | alt_dual_boot_avmm_comp.RD_WIDTH = RD_WIDTH, 58 | alt_dual_boot_avmm_comp.CONFIG_CYCLE = CONFIG_CYCLE, 59 | alt_dual_boot_avmm_comp.RESET_TIMER_CYCLE = RESET_TIMER_CYCLE; 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/synthesis/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2020 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/synthesis/submodules/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2020 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/20.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2019/10/06 $ 17 | // $Author: psgswbuild $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/bonuses/proj1/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot.v -------------------------------------------------------------------------------- /bonuses/proj1/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot_avmm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/bonuses/proj1/ip/dual_boot/synthesis/submodules/rtl/alt_dual_boot_avmm.v -------------------------------------------------------------------------------- /bonuses/proj1/ip/vgaText/basicBlockRAM.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | ---------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 11:42:49 11/26/2013 8 | -- Design Name: 9 | -- Module Name: textLineRAM - Behavioral 10 | -- Project Name: 11 | -- Target Devices: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | ---------------------------------------------------------------------------------- 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | -- note this line.The package is compiled to this directory by default. 35 | -- so don't forget to include this directory. 36 | library work; 37 | -- this line also is must.This includes the particular package into your program. 38 | use work.commonPak.all; 39 | 40 | entity basicBlockRAM is 41 | generic( 42 | numElements: integer := 128; 43 | dataWidth: integer := 8 44 | ); 45 | port( 46 | clkA: in std_logic; 47 | writeEnableA: in std_logic; 48 | addrA: in std_logic_vector(log2_float(numElements-1) downto 0); 49 | dataOutA: out std_logic_vector(dataWidth-1 downto 0); 50 | dataInA: in std_logic_vector(dataWidth-1 downto 0) 51 | ); 52 | end basicBlockRAM; 53 | 54 | architecture Behavioral of basicBlockRAM is 55 | type rom_type is array (0 to numElements-1) of std_logic_vector(dataWidth-1 downto 0); 56 | signal RAM: rom_type := (others => (others => '0')); 57 | begin 58 | -- addr register to infer block RAM 59 | setRegA: process (clkA) 60 | begin 61 | if rising_edge(clkA) then 62 | -- Write to rom 63 | if(writeEnableA = '1') then 64 | RAM(to_integer(unsigned(addrA))) <= dataInA; 65 | end if; 66 | -- Read from it 67 | dataOutA <= RAM(to_integer(unsigned(addrA))); 68 | end if; 69 | end process; 70 | end Behavioral; 71 | 72 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/vgaText/commonPak.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -- 4 | -- Package File Template 5 | -- 6 | -- Purpose: This package defines supplemental types, subtypes, 7 | -- constants, and functions 8 | -- 9 | -- To use any of the example code shown below, uncomment the lines and modify as necessary 10 | -- 11 | 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.all; 14 | 15 | use ieee.math_real.all; 16 | 17 | package commonPak is 18 | 19 | 20 | 21 | constant ADDR_WIDTH : integer := 11; 22 | constant DATA_WIDTH : integer := 8; 23 | 24 | constant FONT_WIDTH : integer := 8; 25 | constant FONT_HEIGHT : integer := 16; 26 | 27 | constant c_max_color_vga : integer := 4095; 28 | 29 | 30 | ------------------------------------------ 31 | 32 | type point_2d is 33 | record 34 | x : integer; 35 | y : integer; 36 | end record; 37 | 38 | type type_textColorMap is array(natural range <>) of integer range 0 to c_max_color_vga; 39 | 40 | 41 | ------------------------------------------ 42 | 43 | 44 | type type_drawElement is 45 | record 46 | pixelOn: boolean; 47 | rgb: integer range 0 to c_max_color_vga; 48 | end record; 49 | constant init_type_drawElement: type_drawElement := (pixelOn => false, rgb => 0); 50 | type type_drawElementArray is array(natural range <>) of type_drawElement; 51 | 52 | 53 | 54 | ------------------------------------------ 55 | 56 | type type_inArbiterPort is 57 | record 58 | dataRequest: boolean; 59 | addr: std_logic_vector(ADDR_WIDTH-1 downto 0); 60 | writeRequest: boolean; 61 | writeData: std_logic_vector(DATA_WIDTH-1 downto 0); 62 | end record; 63 | constant init_type_inArbiterPort: type_inArbiterPort := (dataRequest => false, addr => (others => '0'), writeRequest => false, writeData => (others => '0')); 64 | type type_inArbiterPortArray is array(natural range <>) of type_inArbiterPort; 65 | 66 | 67 | type type_outArbiterPort is 68 | record 69 | dataWaiting: boolean; 70 | data: std_logic_vector(DATA_WIDTH-1 downto 0); 71 | dataWritten: boolean; 72 | end record; 73 | constant init_type_outArbiterPort: type_outArbiterPort := (dataWaiting => false, data => (others => '0'), dataWritten => false); 74 | type type_outArbiterPortArray is array(natural range <>) of type_outArbiterPort; 75 | 76 | 77 | ---------------------- 78 | 79 | function log2_float(val : positive) return natural; 80 | 81 | end commonPak; 82 | 83 | package body commonPak is 84 | function log2_float(val : positive) return natural is 85 | begin 86 | return integer(ceil(log2(real(val)))); 87 | end function; 88 | end commonPak; 89 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/vgaText/tb_and_ex/tb_vgaText1.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:04:49 07/12/2013 8 | -- Design Name: 9 | -- Module Name: D:/Libraries/EE/FPGA/Basys 2/vgaText/tb_vgaText1.vhd 10 | -- Project Name: vgaText 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: vgaText_top 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | USE std.textio.ALL; 33 | 34 | -- Uncomment the following library declaration if using 35 | -- arithmetic functions with Signed or Unsigned values 36 | --USE ieee.numeric_std.ALL; 37 | 38 | ENTITY tb_vgaText1 IS 39 | END tb_vgaText1; 40 | 41 | ARCHITECTURE behavior OF tb_vgaText1 IS 42 | 43 | -- Component Declaration for the Unit Under Test (UUT) 44 | 45 | COMPONENT vgaText_top 46 | PORT( 47 | clk : IN std_logic; 48 | reset : IN std_logic; 49 | Led : OUT std_logic_vector(7 downto 0); 50 | hsync : OUT std_logic; 51 | vsync : OUT std_logic; 52 | Red : OUT std_logic_vector(2 downto 0); 53 | Green : OUT std_logic_vector(2 downto 0); 54 | Blue : OUT std_logic_vector(2 downto 1) 55 | ); 56 | END COMPONENT; 57 | 58 | 59 | --Inputs 60 | signal clk : std_logic := '0'; 61 | signal reset : std_logic := '0'; 62 | 63 | --Outputs 64 | signal Led : std_logic_vector(7 downto 0); 65 | signal hsync : std_logic; 66 | signal vsync : std_logic; 67 | signal Red : std_logic_vector(2 downto 0); 68 | signal Green : std_logic_vector(2 downto 0); 69 | signal Blue : std_logic_vector(2 downto 1); 70 | 71 | -- Clock period definitions 72 | constant clk_period : time := 10 ns; 73 | 74 | BEGIN 75 | 76 | -- Instantiate the Unit Under Test (UUT) 77 | uut: vgaText_top PORT MAP ( 78 | clk => clk, 79 | reset => reset, 80 | Led => Led, 81 | hsync => hsync, 82 | vsync => vsync, 83 | Red => Red, 84 | Green => Green, 85 | Blue => Blue 86 | ); 87 | 88 | -- Clock process definitions 89 | clk_process :process 90 | begin 91 | clk <= '0'; 92 | wait for clk_period/2; 93 | clk <= '1'; 94 | wait for clk_period/2; 95 | end process; 96 | 97 | 98 | -- Stimulus process 99 | stim_proc: process 100 | --file textFile: text; 101 | begin 102 | --file_open(textFile, "textMemory.txt,", write_mode); 103 | 104 | -- hold reset state for 100 ns. 105 | wait for 100 ns; 106 | 107 | wait for clk_period*10; 108 | 109 | -- insert stimulus here 110 | --writeline(textFile, buf_in); 111 | reset <= '1'; 112 | wait for 1 ms; 113 | reset <= '0'; 114 | 115 | wait; 116 | end process; 117 | 118 | END; 119 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/vgaText/tb_and_ex/tb_vgaText2.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 14:07:14 11/19/2013 8 | -- Design Name: 9 | -- Module Name: D:/Libraries/EE/FPGA/Basys 2/vgaText/tb_vgaText2.vhd 10 | -- Project Name: vgaText 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: vgaText_top 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY tb_vgaText2 IS 38 | END tb_vgaText2; 39 | 40 | ARCHITECTURE behavior OF tb_vgaText2 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT vgaText_top 45 | PORT( 46 | clk : IN std_logic; 47 | reset : IN std_logic; 48 | Led : OUT std_logic_vector(7 downto 0); 49 | hsync : OUT std_logic; 50 | vsync : OUT std_logic; 51 | Red : OUT std_logic_vector(2 downto 0); 52 | Green : OUT std_logic_vector(2 downto 0); 53 | Blue : OUT std_logic_vector(2 downto 1) 54 | ); 55 | END COMPONENT; 56 | 57 | 58 | --Inputs 59 | signal clk : std_logic := '0'; 60 | signal reset : std_logic := '0'; 61 | 62 | --Outputs 63 | signal Led : std_logic_vector(7 downto 0); 64 | signal hsync : std_logic; 65 | signal vsync : std_logic; 66 | signal Red : std_logic_vector(2 downto 0); 67 | signal Green : std_logic_vector(2 downto 0); 68 | signal Blue : std_logic_vector(2 downto 1); 69 | 70 | -- Clock period definitions 71 | constant clk_period : time := 10 ns; 72 | 73 | BEGIN 74 | 75 | -- Instantiate the Unit Under Test (UUT) 76 | uut: vgaText_top PORT MAP ( 77 | clk => clk, 78 | reset => reset, 79 | Led => Led, 80 | hsync => hsync, 81 | vsync => vsync, 82 | Red => Red, 83 | Green => Green, 84 | Blue => Blue 85 | ); 86 | 87 | -- Clock process definitions 88 | clk_process :process 89 | begin 90 | clk <= '0'; 91 | wait for clk_period/2; 92 | clk <= '1'; 93 | wait for clk_period/2; 94 | end process; 95 | 96 | 97 | -- Stimulus process 98 | stim_proc: process 99 | begin 100 | -- hold reset state for 100 ns. 101 | wait for 100 ns; 102 | 103 | wait for clk_period*10; 104 | 105 | -- insert stimulus here 106 | reset <= '1'; 107 | wait for 1 ms; 108 | reset <= '0'; 109 | 110 | wait; 111 | end process; 112 | 113 | END; 114 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/vgaText/tb_and_ex/tb_vgaText3.vhd: -------------------------------------------------------------------------------- 1 | -- Source: https://github.com/MadLittleMods/FP-V-GA-Text 2 | 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 23:04:02 11/25/2013 8 | -- Design Name: 9 | -- Module Name: D:/Libraries/EE/FPGA/Basys 2/vgaText/tb_vgaText3.vhd 10 | -- Project Name: vgaText 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: vgaText_top 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | use IEEE.std_logic_textio.all; 34 | use std.textio.all; 35 | 36 | -- Uncomment the following library declaration if using 37 | -- arithmetic functions with Signed or Unsigned values 38 | USE ieee.numeric_std.ALL; 39 | 40 | 41 | ENTITY tb_vgaText3 IS 42 | END tb_vgaText3; 43 | 44 | ARCHITECTURE behavior OF tb_vgaText3 IS 45 | 46 | -- Component Declaration for the Unit Under Test (UUT) 47 | 48 | COMPONENT vgaText_top 49 | PORT( 50 | clk : IN std_logic; 51 | reset : IN std_logic; 52 | Led : OUT std_logic_vector(7 downto 0); 53 | hsync : OUT std_logic; 54 | vsync : OUT std_logic; 55 | Red : OUT std_logic_vector(2 downto 0); 56 | Green : OUT std_logic_vector(2 downto 0); 57 | Blue : OUT std_logic_vector(2 downto 1) 58 | ); 59 | END COMPONENT; 60 | 61 | 62 | --Inputs 63 | signal clk : std_logic := '0'; 64 | signal reset : std_logic := '0'; 65 | 66 | --Outputs 67 | signal Led : std_logic_vector(7 downto 0); 68 | signal hsync : std_logic; 69 | signal vsync : std_logic; 70 | signal Red : std_logic_vector(2 downto 0); 71 | signal Green : std_logic_vector(2 downto 0); 72 | signal Blue : std_logic_vector(2 downto 1); 73 | 74 | -- Clock period definitions 75 | constant clk_period : time := 20 ns; 76 | 77 | BEGIN 78 | 79 | -- Instantiate the Unit Under Test (UUT) 80 | uut: vgaText_top PORT MAP ( 81 | clk => clk, 82 | reset => reset, 83 | Led => Led, 84 | hsync => hsync, 85 | vsync => vsync, 86 | Red => Red, 87 | Green => Green, 88 | Blue => Blue 89 | ); 90 | 91 | -- Clock process definitions 92 | clk_process :process 93 | begin 94 | clk <= '0'; 95 | wait for clk_period/2; 96 | clk <= '1'; 97 | wait for clk_period/2; 98 | end process; 99 | 100 | 101 | -- Stimulus process 102 | stim_proc: process 103 | begin 104 | -- hold reset state for 100 ns. 105 | wait for 100 ns; 106 | 107 | wait for clk_period*10; 108 | 109 | -- insert stimulus here 110 | reset <= '1'; 111 | wait for 100 ns; 112 | reset <= '0'; 113 | 114 | 115 | wait; 116 | end process; 117 | 118 | 119 | 120 | 121 | 122 | --Write process 123 | process (clk) 124 | file file_pointer: text is out "write.txt"; 125 | variable line_el: line; 126 | begin 127 | 128 | if rising_edge(clk) then 129 | 130 | --line_el := "1"; 131 | 132 | -- Write the time 133 | write(line_el, now); --write the line. 134 | write(line_el, ":"); --write the line. 135 | --writeline(file_pointer, line_el); --write the contents into the file. 136 | 137 | -- Write the hsync 138 | write(line_el, " "); 139 | write(line_el, hsync); --write the line. 140 | --writeline(file_pointer, line_el); --write the contents into the file. 141 | 142 | -- Write the vsync 143 | write(line_el, " "); 144 | write(line_el, vsync); --write the line. 145 | --writeline(file_pointer, line_el); --write the contents into the file. 146 | 147 | -- Write the red 148 | write(line_el, " "); 149 | write(line_el, Red); --write the line. 150 | --writeline(file_pointer, line_el); --write the contents into the file. 151 | 152 | -- Write the green 153 | write(line_el, " "); 154 | write(line_el, Green); --write the line. 155 | --writeline(file_pointer, line_el); --write the contents into the file. 156 | 157 | -- Write the blue 158 | write(line_el, " "); 159 | write(line_el, Blue); --write the line. 160 | 161 | writeline(file_pointer, line_el); --write the contents into the file. 162 | 163 | 164 | end if; 165 | end process; 166 | 167 | 168 | END; 169 | -------------------------------------------------------------------------------- /bonuses/proj1/ip/vga_controller.vhd: -------------------------------------------------------------------------------- 1 | -- vga_controller: inspired by digikey code and project F blog 2 | -- Source: https://forum.digikey.com/t/vga-controller-vhdl/12794 3 | -- Source: https://projectf.io/posts/fpga-graphics/ 4 | 5 | library IEEE; 6 | use IEEE.std_logic_1164.all; 7 | use IEEE.numeric_std.all; 8 | library work; 9 | 10 | ENTITY vga_controller IS 11 | GENERIC( 12 | H_RES : INTEGER := 640; --horiztonal display width in pixels 13 | V_RES : INTEGER := 480; --vertical display width in rows 14 | H_FP : INTEGER := 16; --horiztonal front porch width in pixels 15 | H_SYNC : INTEGER := 96; --horiztonal sync pulse width in pixels 16 | H_BP : INTEGER := 48; --horiztonal back porch width in pixels 17 | V_FP : INTEGER := 10; --vertical front porch width in rows 18 | V_SYNC : INTEGER := 2; --vertical sync pulse width in rows 19 | V_BP : INTEGER := 33; --vertical back porch width in rows 20 | H_POL : STD_LOGIC := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative) 21 | V_POL : STD_LOGIC := '0' --vertical sync pulse polarity (1 = positive, 0 = negative) 22 | ); 23 | PORT( 24 | pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used 25 | reset_n : IN STD_LOGIC; --active low synchronous reset 26 | hsync : OUT STD_LOGIC; --horiztonal sync pulse 27 | vsync : OUT STD_LOGIC; --vertical sync pulse 28 | de : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time) 29 | frame : out STD_LOGIC; -- high at start of frame 30 | line : out STD_LOGIC; -- high at start of active line 31 | sx : OUT INTEGER range -(H_SYNC+H_FP+H_BP) to H_RES-1; -- signed horizontal pixel coordinate 32 | sy : OUT INTEGER range -(V_SYNC+V_FP+V_BP) to V_RES-1 -- signed vertical pixel coordinate 33 | ); 34 | END vga_controller; 35 | 36 | ARCHITECTURE behavior OF vga_controller IS 37 | -- horizontal timings 38 | constant H_STA : integer := 0 - H_FP - H_SYNC - H_BP; -- horizontal start 39 | constant HS_STA : integer := H_STA + H_FP; -- sync start 40 | constant HS_END : integer := HS_STA + H_SYNC; -- sync end 41 | constant HA_STA : integer := 0; -- active start 42 | constant HA_END : integer := H_RES - 1; -- active end 43 | 44 | -- vertical timings 45 | constant V_STA : integer := 0 - V_FP - V_SYNC - V_BP; -- vertical start 46 | constant VS_STA : integer := V_STA + V_FP; -- sync start 47 | constant VS_END : integer := VS_STA + V_SYNC; -- sync end 48 | constant VA_STA : integer := 0; -- active start 49 | constant VA_END : integer := V_RES - 1; -- active end 50 | 51 | signal x : INTEGER range -(H_SYNC+H_FP+H_BP) to H_RES-1; -- signed horizontal pixel coordinate 52 | signal y : INTEGER range -(V_SYNC+V_FP+V_BP) to V_RES-1; -- signed vertical pixel coordinate 53 | BEGIN 54 | 55 | -- generate horizontal and vertical sync with correct polarity 56 | process(pixel_clk) 57 | begin 58 | if rising_edge(pixel_clk) then 59 | 60 | if (x > HS_STA and x <= HS_END) then 61 | hsync <= H_POL; -- Assert 62 | else 63 | hsync <= not H_POL; -- Deassert 64 | end if; 65 | 66 | -- Assert vsync 67 | if (y > VS_STA and y <= VS_END) then 68 | vsync <= V_POL; -- Assert 69 | else 70 | vsync <= not V_POL; -- Deassert 71 | end if; 72 | 73 | end if; 74 | end process; 75 | 76 | -- control signals 77 | process(pixel_clk) 78 | begin 79 | if rising_edge(pixel_clk) then 80 | 81 | if (y >= VA_STA and x >= HA_STA) then 82 | de <= '1'; 83 | else 84 | de <= '0'; 85 | end if; 86 | 87 | if (y = V_STA and x = H_STA) then 88 | frame <= '1'; 89 | else 90 | frame <= '0'; 91 | end if; 92 | 93 | if (y >= VA_STA and x = H_STA) then 94 | line <= '1'; 95 | else 96 | line <= '0'; 97 | end if; 98 | 99 | 100 | if (reset_n = '0') then frame <= '0'; end if; -- don't assert frame in reset 101 | 102 | end if; 103 | end process; 104 | 105 | -- calculate horizontal and vertical screen position 106 | process(pixel_clk) 107 | begin 108 | if rising_edge(pixel_clk) then 109 | 110 | if (x = HA_END) then -- last pixel on line? 111 | x <= H_STA; 112 | if (y = VA_END) then -- last line on screen? 113 | y <= V_STA; 114 | else 115 | y <= y + 1; 116 | end if; 117 | else 118 | x <= x + 1; 119 | end if; 120 | 121 | if (reset_n = '0') then 122 | x <= H_STA; 123 | y <= V_STA; 124 | end if; 125 | 126 | end if; 127 | end process; 128 | 129 | -- delay screen position to match sync and control signals 130 | process(pixel_clk) 131 | begin 132 | if rising_edge(pixel_clk) then 133 | 134 | sx <= x; 135 | sy <= y; 136 | 137 | if (reset_n = '0') then 138 | sx <= H_STA; 139 | sy <= V_STA; 140 | end if; 141 | 142 | end if; 143 | end process; 144 | 145 | END behavior; -------------------------------------------------------------------------------- /bonuses/proj1/lfsr_n.vhd: -------------------------------------------------------------------------------- 1 | -- lfsr_n: Generic Linear Feedback Shift Register 2 | -- Inspired By: https://projectf.io/posts/fpga-graphics/ 3 | library IEEE; 4 | use IEEE.std_logic_1164.all; 5 | use IEEE.numeric_std.all; 6 | library work; 7 | 8 | -- Common constants 9 | use work.defender_common.all; 10 | 11 | ENTITY lfsr_n IS 12 | generic ( 13 | g_taps : std_logic_vector := "10111000"; -- Use taps that give maximal length period 14 | g_init_seed : std_logic_vector := X"FF" -- Must be non-zero 15 | ); 16 | PORT ( 17 | i_clock : in std_logic; 18 | i_reset : in std_logic; -- Synch reset 19 | i_load : in std_logic; -- Synch load. Register loads value on i_data when asserted. 20 | i_cnt_en : IN STD_LOGIC; -- Count enable. 21 | i_data : IN STD_LOGIC_VECTOR(g_taps'length-1 DOWNTO 0); -- Parallel load 22 | o_value : OUT STD_LOGIC_VECTOR(g_taps'length-1 DOWNTO 0) -- Output of the LFSR 23 | ); 24 | END lfsr_n; 25 | 26 | ARCHITECTURE behavior OF lfsr_n IS 27 | -- Types 28 | 29 | -- Component declarations 30 | 31 | -- Signal declarations 32 | SIGNAL sreg : STD_LOGIC_VECTOR(g_taps'length-1 DOWNTO 0) := g_init_seed; -- Internal register 33 | 34 | BEGIN 35 | 36 | PROCESS (i_clock) BEGIN 37 | 38 | -- Clocked behavior 39 | IF (rising_edge(i_clock)) THEN 40 | 41 | -- Generate next number in the sequence 42 | if (i_cnt_en = '1') then 43 | if (sreg(0) = '1') then 44 | sreg <= ('0' & sreg(g_taps'length-1 downto 1)) xor g_taps; 45 | else 46 | sreg <= ('0' & sreg(g_taps'length-1 downto 1)); 47 | end if; 48 | end if; 49 | -- Load external value 50 | if (i_load = '1') then 51 | sreg <= i_data; 52 | end if; 53 | -- Reset to initial seed 54 | if (i_reset = '1') then 55 | sreg <= g_init_seed; 56 | end if; 57 | 58 | END IF; 59 | 60 | END PROCESS; 61 | 62 | -- Instantiation AND port mapping 63 | 64 | -- Concurrent assignments 65 | o_value <= sreg; 66 | 67 | END behavior; 68 | 69 | -------------------------------------------------------------------------------- /bonuses/proj1/pb_debounce.vhd: -------------------------------------------------------------------------------- 1 | -- pb_debounce: Synchronize and debounce pushbuttons 2 | -- Inspired By: https://projectf.io/posts/fpga-graphics/ 3 | library IEEE; 4 | use IEEE.std_logic_1164.all; 5 | use IEEE.numeric_std.all; 6 | 7 | entity pb_debounce is 8 | generic ( 9 | g_pol : std_logic := '0'; -- PB polarity: 0 for active low, 1 for active high 10 | g_clk_freq_in : integer := 25175000; -- 25.175 MHz; 11 | g_delay_msec : integer := 10 12 | ); 13 | port ( 14 | i_clk : in std_logic; 15 | i_pb : in std_logic; 16 | 17 | o_pb_state : out std_logic; -- "clean" output state of PB, active high 18 | o_pb_down : out std_logic; -- One clock cycle pulse for "down" event 19 | o_pb_up : out std_logic -- One clock cycle pulse for "up" event 20 | 21 | ); 22 | end entity pb_debounce; 23 | 24 | architecture rtl of pb_debounce is 25 | -- Constants 26 | constant c_clks_per_msec : integer := (g_clk_freq_in)/(1e3); 27 | 28 | -- Signals 29 | signal pb_sync_0, pb_sync_1, pb_sync_2, pb_inv : std_logic; 30 | signal cnt_clks : integer range 0 to c_clks_per_msec-1 := 0; 31 | signal cnt_msec : integer range 0 to g_delay_msec-1 := 0; 32 | signal pb_state, pb_down, pb_up : std_logic := '0'; 33 | signal idle, clks_max, msec_max : std_logic; 34 | 35 | begin 36 | -- Synchronizer 37 | pb_sync_0 <= i_pb when rising_edge(i_clk); 38 | pb_sync_1 <= pb_sync_0 when rising_edge(i_clk); 39 | pb_sync_2 <= pb_sync_1 when rising_edge(i_clk); 40 | 41 | pb_inv <= pb_sync_2 when g_pol = '1' else not pb_sync_2; -- Only use pb_inv in below clocked logic 42 | 43 | -- Status signals 44 | idle <= '1' when (pb_state = pb_inv) else '0'; -- Has the PB input has changed from our current output? 45 | clks_max <= '1' when (cnt_clks = c_clks_per_msec-1) else '0'; -- Clock counter has reached max 46 | msec_max <= '1' when (cnt_msec = g_delay_msec-1) else '0'; -- msec delay counter has reached max 47 | pb_down <= '1' when (idle = '0' and msec_max = '1' and pb_state = '0') else '0'; -- State is about to switch high 48 | pb_up <= '1' when (idle = '0' and msec_max = '1' and pb_state = '1') else '0'; -- State is about to switch low 49 | 50 | -- Update counters 51 | cnt: process(i_clk) 52 | begin 53 | if rising_edge(i_clk) then 54 | if idle = '1' then 55 | cnt_clks <= 0; 56 | cnt_msec <= 0; 57 | else 58 | cnt_clks <= cnt_clks+1; 59 | 60 | -- A msec has passed 61 | if clks_max = '1' then 62 | cnt_clks <= 0; 63 | cnt_msec <= cnt_msec+1; 64 | end if; 65 | 66 | -- Total duration has elapsed 67 | if msec_max = '1' then 68 | pb_state <= not pb_state; -- Invert output, should now match the input 69 | end if; 70 | end if; 71 | end if; 72 | end process cnt; 73 | 74 | -- Outputs 75 | o_pb_state <= pb_state; 76 | o_pb_down <= pb_down; 77 | o_pb_up <= pb_up; 78 | 79 | end architecture rtl; -------------------------------------------------------------------------------- /bonuses/proj1/proj1.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition 22 | # Date created = 18:43:39 November 11, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.1" 27 | DATE = "18:43:39 November 11, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "proj1" 32 | -------------------------------------------------------------------------------- /bonuses/proj1/proj1.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/bonuses/proj1/proj1.qws -------------------------------------------------------------------------------- /bonuses/proj1/proj1_top.vhd: -------------------------------------------------------------------------------- 1 | -- proj1: "FPGA Defender" game with bonuses 2 | -- Authors: Garrett Carter & Tyler McCormick 3 | -- Top level entity 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | use ieee.numeric_std.all; 7 | library work; 8 | 9 | -- For vgaText library 10 | use work.commonPak.all; 11 | -- Common constants 12 | use work.defender_common.all; 13 | 14 | entity proj1_top is 15 | PORT( 16 | KEY : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 17 | SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 18 | MAX10_CLK1_50 : IN STD_LOGIC; -- 50 MHz clock input 19 | LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); 20 | ARDUINO_IO : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); 21 | HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 22 | -- Accelerometer I/O 23 | GSENSOR_CS_N : OUT STD_LOGIC; 24 | GSENSOR_SCLK : OUT STD_LOGIC; 25 | GSENSOR_SDI : INOUT STD_LOGIC; 26 | GSENSOR_SDO : INOUT STD_LOGIC; 27 | 28 | -- VGA I/O 29 | VGA_HS : OUT STD_LOGIC; -- horizontal sync pulse 30 | VGA_VS : OUT STD_LOGIC; -- vertical sync pulse 31 | 32 | VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); -- red magnitude output to DAC 33 | VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); -- green magnitude output to DAC 34 | VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0') -- blue magnitude output to DAC 35 | ); 36 | end proj1_top; 37 | 38 | architecture top_level of proj1_top is 39 | 40 | -- Constants 41 | 42 | -- Component declarations 43 | component vga_pll_25_175 is 44 | port( 45 | inclk0 : IN STD_LOGIC := '0'; -- Input clock that gets divided (50 MHz for max10) 46 | c0 : OUT STD_LOGIC -- Output clock for vga timing (25.175 MHz) 47 | ); 48 | end component; 49 | 50 | COMPONENT ADXL345_controller IS 51 | PORT( reset_n : IN STD_LOGIC; 52 | clk : IN STD_LOGIC; 53 | data_valid : OUT STD_LOGIC; 54 | data_x : OUT STD_LOGIC_VECTOR(15 downto 0); 55 | data_y : OUT STD_LOGIC_VECTOR(15 downto 0); 56 | data_z : OUT STD_LOGIC_VECTOR(15 downto 0); 57 | SPI_SDI : OUT STD_LOGIC; 58 | SPI_SDO : IN STD_LOGIC; 59 | SPI_CSN : OUT STD_LOGIC; 60 | SPI_CLK : OUT STD_LOGIC ); 61 | END COMPONENT; 62 | 63 | COMPONENT accel_proc is 64 | port ( 65 | -- Raw data from accelerometer 66 | data_x : IN STD_LOGIC_VECTOR(15 downto 0); 67 | data_y : IN STD_LOGIC_VECTOR(15 downto 0); 68 | data_valid : IN STD_LOGIC; 69 | 70 | -- Direction of tilt 71 | -- x+ : left, x- : right 72 | -- y+ : forward, y- : backward 73 | accel_scale_x, accel_scale_y : OUT integer := 0 -- A scaled version of data 74 | ); 75 | end COMPONENT; 76 | 77 | component dual_boot is 78 | port ( 79 | clk_clk : in std_logic := 'X'; -- clk 80 | reset_reset_n : in std_logic := 'X' -- reset_n 81 | ); 82 | end component; 83 | 84 | -- Signal declarations 85 | signal clk_25_175_MHz, disp_en : STD_LOGIC; 86 | signal scan_pos : t_point_2d; 87 | signal frame : std_logic; 88 | signal line : std_logic; 89 | signal KEY_state, KEY_down, KEY_up : std_logic_vector(1 downto 0); 90 | signal SW_state, SW_down, SW_up : std_logic_vector(9 downto 0); 91 | 92 | -- Accelerometer 93 | signal data_x, data_y : STD_LOGIC_VECTOR(15 DOWNTO 0); 94 | signal data_valid : STD_LOGIC; 95 | signal accel_scale_x, accel_scale_y : integer; 96 | 97 | begin 98 | 99 | -- Concurrent assignments 100 | 101 | -- Instantiation and port mapping 102 | 103 | sw_deb: for i in 0 to 9 generate 104 | sw_deb_x : entity work.pb_debounce 105 | generic map ( 106 | g_pol => '1' 107 | ) 108 | port map ( 109 | i_clk => clk_25_175_MHz, 110 | i_pb => SW(i), 111 | o_pb_state => SW_state(i), 112 | o_pb_down => SW_down(i), 113 | o_pb_up => SW_up(i) 114 | ); 115 | end generate sw_deb; 116 | 117 | pb_deb: for i in 0 to 1 generate 118 | pb_deb_x : entity work.pb_debounce port map ( 119 | i_clk => clk_25_175_MHz, 120 | i_pb => KEY(i), 121 | o_pb_state => KEY_state(i), 122 | o_pb_down => KEY_down(i), 123 | o_pb_up => KEY_up(i) 124 | ); 125 | end generate pb_deb; 126 | 127 | -- Dual boot 128 | U7 : dual_boot port map ( clk_clk => MAX10_CLK1_50, reset_reset_n => '1' ); 129 | 130 | -- VGA 131 | U8 : vga_pll_25_175 port map ( 132 | inclk0 => MAX10_CLK1_50, 133 | c0 => clk_25_175_MHz 134 | ); 135 | 136 | U9 : entity work.vga_controller port map ( 137 | pixel_clk => clk_25_175_MHz, 138 | reset_n => '1', 139 | hsync => VGA_HS, 140 | vsync => VGA_VS, 141 | de => disp_en, 142 | frame => frame, 143 | line => line, 144 | sx => scan_pos.x, 145 | sy => scan_pos.y 146 | ); 147 | 148 | -- Accel 149 | U10 : ADXL345_controller PORT MAP (reset_n => '1', clk => MAX10_CLK1_50, data_valid => data_valid, data_x => data_x, data_y => data_y, data_z => open, SPI_SDI => GSENSOR_SDI, SPI_SDO => GSENSOR_SDO, SPI_CSN => GSENSOR_CS_N, SPI_CLK => GSENSOR_SCLK ); 150 | U11 : accel_proc PORT MAP ( data_x => data_x, data_y => data_y, data_valid => data_valid, accel_scale_x => accel_scale_x, accel_scale_y => accel_scale_y ); 151 | 152 | -- Game Logic 153 | U12 : entity work.image_gen port map ( 154 | pixel_clk => clk_25_175_MHz, 155 | disp_en => disp_en, 156 | i_scan_pos => scan_pos, 157 | frame => frame, 158 | line => line, 159 | red => VGA_R, 160 | green => VGA_G, 161 | blue => VGA_B, 162 | 163 | accel_scale_x => accel_scale_x, 164 | accel_scale_y => accel_scale_y, 165 | KEY_state => KEY_state, 166 | KEY_down => KEY_down, 167 | KEY_up => KEY_up, 168 | SW_state => SW_state, 169 | 170 | o_buzzPin => ARDUINO_IO(12), 171 | HEX5 => HEX5, HEX4 => HEX4, HEX3 => HEX3, HEX2 => HEX2, HEX1 => HEX1, HEX0 => HEX0, 172 | LEDR => LEDR 173 | ); 174 | 175 | end top_level; -------------------------------------------------------------------------------- /bonuses/proj1/res/palette.mif: -------------------------------------------------------------------------------- 1 | -- 16 color palette for FPGA Defender sprites 2 | DEPTH = 16; 3 | WIDTH = 12; 4 | ADDRESS_RADIX = HEX; 5 | DATA_RADIX = HEX; 6 | CONTENT 7 | BEGIN 8 | 9 | -- 16 colors of 12 bits each (4 bits each for RGB) 10 | 11 | -- Palette values: 12 | 0: 000; -- black 13 | 1: 515; -- transparent 14 | 2: 888; -- grey 15 | 3: F00; -- red 16 | 4: F0F; -- fuchsia 17 | 5: 808; -- purple 18 | 6: 00F; -- blue 19 | 7: FB0; -- orange 20 | 8: 0F0; -- lime 21 | 9: 080; -- green 22 | A: 0FF; -- aqua 23 | B: 800; -- maroon 24 | C: FFF; -- XXX 25 | D: FFF; -- XXX 26 | E: FFF; -- XXX 27 | F: FFF; -- white 28 | END; 29 | -------------------------------------------------------------------------------- /bonuses/proj1/sound_effects/clock_div.vhd: -------------------------------------------------------------------------------- 1 | -- Configurable n-bit clock divider (clock_div) 2 | LIBRARY IEEE; 3 | USE IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | library work; 6 | 7 | ENTITY clock_div IS 8 | GENERIC (n : NATURAL := 8); 9 | PORT ( clock_in, reset : IN STD_LOGIC; 10 | divisor : IN STD_LOGIC_VECTOR(n DOWNTO 0); -- divisor = 2*(max_cnt+1) 11 | clock_out : OUT STD_LOGIC ); 12 | END clock_div; 13 | 14 | ARCHITECTURE behavior OF clock_div IS 15 | -- Constants 16 | 17 | -- Types 18 | 19 | -- Component declarations 20 | 21 | -- Signal declarations 22 | SIGNAL count : STD_LOGIC_VECTOR(n-1 DOWNTO 0); -- Internal counter 23 | SIGNAL max_cnt : STD_LOGIC_VECTOR(n-1 DOWNTO 0); 24 | SIGNAL temp_clock : STD_LOGIC := '0'; 25 | 26 | BEGIN 27 | 28 | max_cnt <= (divisor(n DOWNTO 1) - '1'); -- Bit shift right (div by 2) then sub 1 29 | 30 | PROCESS (clock_in, reset) BEGIN 31 | 32 | -- Asynch reset 33 | IF (reset = '1') THEN 34 | count <= (OTHERS => '0'); 35 | temp_clock <= '0'; 36 | 37 | -- Clocked behavior 38 | ELSIF (clock_in'event AND clock_in = '1') THEN 39 | 40 | IF (count >= max_cnt) THEN 41 | temp_clock <= NOT temp_clock; 42 | count <= (OTHERS => '0'); 43 | ELSE 44 | count <= count + '1'; 45 | END IF; 46 | 47 | END IF; 48 | 49 | END PROCESS; 50 | 51 | -- Instantiation AND port mapping 52 | 53 | -- Concurrent assignments 54 | clock_out <= temp_clock; 55 | 56 | END behavior; -------------------------------------------------------------------------------- /bonuses/proj1/sound_effects/tb/effect_gen_tb.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /effect_gen_tb/reset_n 4 | add wave -noupdate /effect_gen_tb/test_clk 5 | add wave -noupdate /effect_gen_tb/effect_cmd 6 | add wave -noupdate /effect_gen_tb/buzz_out 7 | add wave -noupdate /effect_gen_tb/UUT/r_state 8 | add wave -noupdate -radix hexadecimal /effect_gen_tb/UUT/r_romAddr 9 | add wave -noupdate -radix unsigned /effect_gen_tb/UUT/w_romData 10 | add wave -noupdate /effect_gen_tb/UUT/r_buzzDisable 11 | add wave -noupdate -radix hexadecimal /effect_gen_tb/UUT/r_buzzDivisor 12 | TreeUpdate [SetDefaultTree] 13 | WaveRestoreCursors {{Cursor 1} {1000 ps} 0} 14 | quietly wave cursor active 1 15 | configure wave -namecolwidth 236 16 | configure wave -valuecolwidth 100 17 | configure wave -justifyvalue left 18 | configure wave -signalnamewidth 0 19 | configure wave -snapdistance 10 20 | configure wave -datasetprefix 0 21 | configure wave -rowmargin 4 22 | configure wave -childrowmargin 2 23 | configure wave -gridoffset 0 24 | configure wave -gridperiod 1 25 | configure wave -griddelta 40 26 | configure wave -timeline 0 27 | configure wave -timelineunits ns 28 | update 29 | WaveRestoreZoom {0 ps} {194325 ps} 30 | run 4000 ns -------------------------------------------------------------------------------- /bonuses/proj1/sound_effects/tb/effect_gen_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Testbench for effect_gen 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.all; 4 | 5 | ENTITY effect_gen_tb IS 6 | END effect_gen_tb; 7 | 8 | ARCHITECTURE behavior OF effect_gen_tb IS 9 | 10 | -- Component declarations 11 | component effect_gen is 12 | port ( 13 | i_clock : in std_logic; 14 | i_reset_n : in std_logic; 15 | 16 | i_launch : in std_logic; 17 | i_playerFire : in std_logic; 18 | i_enemyFire : in std_logic; 19 | i_enemyDestroy : in std_logic; 20 | i_playerDestroy : in std_logic; 21 | 22 | o_buzzPin : out std_logic 23 | ); 24 | end component; 25 | 26 | -- Constants 27 | CONSTANT clock_period: TIME := 20 ns; -- 50 MHz 28 | 29 | -- Signal declarations 30 | signal reset_n : std_logic; 31 | SIGNAL test_clk : STD_LOGIC; 32 | signal effect_cmd : std_logic_vector(4 downto 0); 33 | signal buzz_out : std_logic; 34 | 35 | BEGIN 36 | 37 | -- Instantiation and port mapping 38 | UUT : effect_gen port map ( 39 | i_clock => test_clk, 40 | i_reset_n => reset_n, 41 | 42 | i_launch => effect_cmd(0), 43 | i_playerFire => effect_cmd(1), 44 | i_enemyFire => effect_cmd(2), 45 | i_enemyDestroy => effect_cmd(3), 46 | i_playerDestroy => effect_cmd(4), 47 | 48 | o_buzzPin => buzz_out 49 | ); 50 | 51 | 52 | clock_process: PROCESS 53 | BEGIN 54 | test_clk <= '0'; 55 | WAIT FOR clock_period/2; 56 | test_clk <= '1'; 57 | WAIT FOR clock_period/2; 58 | END PROCESS; 59 | 60 | vectors: PROCESS 61 | BEGIN 62 | reset_n <= '0'; 63 | WAIT FOR 20 ns; 64 | reset_n <= '1'; 65 | effect_cmd <= "00001"; 66 | wait for 100 ns; 67 | WAIT; 68 | END PROCESS; 69 | 70 | 71 | END; 72 | -------------------------------------------------------------------------------- /bonuses/proj1/sound_effects/tb/effect_mem_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Testbench for effect_mem 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.all; 4 | use ieee.NUMERIC_STD.all; 5 | 6 | ENTITY effect_mem_tb IS 7 | END effect_mem_tb; 8 | 9 | ARCHITECTURE behavior OF effect_mem_tb IS 10 | 11 | -- Component declarations 12 | component effect_mem is 13 | port 14 | ( 15 | address : in std_logic_vector (9 downto 0); 16 | clock : in std_logic := '1'; 17 | q : out std_logic_vector (8 downto 0) 18 | ); 19 | end component; 20 | 21 | -- Constants 22 | CONSTANT clock_period: TIME := 20 ns; -- 50 MHz 23 | 24 | -- Signal declarations 25 | signal reset_n : std_logic; 26 | SIGNAL test_clk : STD_LOGIC; 27 | signal mem_addr : std_logic_vector(9 downto 0); 28 | signal mem_data : std_logic_vector(8 downto 0); 29 | 30 | BEGIN 31 | 32 | -- Instantiation and port mapping 33 | UUT : effect_mem port map ( 34 | address => mem_addr, 35 | clock => test_clk, 36 | 37 | q => mem_data 38 | 39 | ); 40 | 41 | 42 | clock_process: PROCESS 43 | BEGIN 44 | test_clk <= '0'; 45 | WAIT FOR clock_period/2; 46 | test_clk <= '1'; 47 | WAIT FOR clock_period/2; 48 | END PROCESS; 49 | 50 | vectors: PROCESS 51 | BEGIN 52 | mem_addr <= "00" & X"00"; 53 | WAIT FOR 80 ns; 54 | mem_addr <= "00" & X"01"; 55 | WAIT FOR 80 ns; 56 | mem_addr <= "00" & X"02"; 57 | WAIT FOR 80 ns; 58 | mem_addr <= "00" & X"03"; 59 | WAIT FOR 80 ns; 60 | mem_addr <= "00" & X"04"; 61 | WAIT FOR 80 ns; 62 | mem_addr <= "00" & X"05"; 63 | WAIT FOR 80 ns; 64 | mem_addr <= "00" & X"06"; 65 | WAIT FOR 80 ns; 66 | 67 | WAIT; 68 | END PROCESS; 69 | 70 | 71 | END; 72 | -------------------------------------------------------------------------------- /bonuses/proj1/starfield.vhd: -------------------------------------------------------------------------------- 1 | -- starfield: Generate an animated starfield using a LFSR 2 | -- Inspired By: https://projectf.io/posts/fpga-graphics/ 3 | library IEEE; 4 | use IEEE.std_logic_1164.all; 5 | use IEEE.numeric_std.all; 6 | library work; 7 | 8 | use work.defender_common.all; 9 | 10 | 11 | entity starfield is 12 | generic ( 13 | g_width : integer := 800; 14 | g_height : integer := 525; 15 | g_incr : integer := -1; -- Larger negative numbers will increase speed of animation 16 | g_seed : std_logic_vector(20 downto 0) := std_logic_vector(to_unsigned(16#1FFFFF#, 21)); -- Seed for the LFSR 17 | g_mask : std_logic_vector(20 downto 0) := std_logic_vector(to_unsigned(16#FFF#, 21)) -- More ones will increase the density 18 | ); 19 | port ( 20 | i_clock : in std_logic; 21 | i_anim_en : in std_logic; -- Animation Enable 22 | i_draw_en : in std_logic; -- Draw Enable 23 | i_reset : in std_logic; 24 | 25 | o_sf_on : out std_logic; -- Star on 26 | o_sf_bright : out std_logic_vector(7 downto 0) -- Star brightness 27 | ); 28 | end entity starfield; 29 | 30 | architecture rtl of starfield is 31 | 32 | -- Constants 33 | constant c_reset_cnt : integer := g_width * g_height + g_incr - 1; -- counter starts at zero, so sub 1 34 | constant c_reset_cnt_pause : integer := g_width * g_height - 1; -- Reset count to show a "paused" starfield 35 | 36 | -- Signals 37 | signal sf_reg : std_logic_vector(20 downto 0); 38 | signal sf_cnt : integer range 0 to 2**21-1 := 0; 39 | signal lfsr_rst : std_logic; 40 | 41 | begin 42 | 43 | process(i_clock) 44 | begin 45 | if rising_edge(i_clock) then 46 | 47 | sf_cnt <= sf_cnt + 1; 48 | if (sf_cnt = c_reset_cnt and i_anim_en = '1') then 49 | sf_cnt <= 0; 50 | elsif (sf_cnt = c_reset_cnt_pause and i_anim_en = '0') then 51 | sf_cnt <= 0; 52 | end if; 53 | 54 | if (i_reset = '1') then 55 | sf_cnt <= 0; 56 | end if; 57 | end if; 58 | end process; 59 | 60 | -- select some bits to form stars 61 | process(sf_reg, i_draw_en) 62 | begin 63 | if ((sf_reg or g_mask) = "111111111111111111111") then 64 | o_sf_on <= '1'; 65 | else 66 | o_sf_on <= '0'; 67 | end if; 68 | o_sf_bright <= sf_reg(7 downto 0); 69 | 70 | if i_draw_en = '0' then 71 | o_sf_on <= '0'; 72 | o_sf_bright <= (others => '0'); 73 | end if; 74 | end process; 75 | 76 | lfsr_rst <= '1' when (sf_cnt = 0) else '0'; 77 | 78 | -- Instantiation 79 | prng: entity work.lfsr_n 80 | generic map ( 81 | g_taps => "101000000000000000000", 82 | g_init_seed => g_seed 83 | ) 84 | port map ( 85 | i_clock => i_clock, 86 | i_reset => lfsr_rst, 87 | i_load => '0', 88 | i_cnt_en => '1', 89 | i_data => (others => '0'), 90 | o_value => sf_reg 91 | ); 92 | 93 | end architecture rtl; -------------------------------------------------------------------------------- /bonuses/proj1/sync_ram_init.vhd: -------------------------------------------------------------------------------- 1 | -- sync_ram_init: Synchronous block RAM with initial values. Can be used as a rom 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | library work; 7 | use work.defender_common.all; 8 | 9 | entity sync_ram_init is 10 | generic( 11 | numElements: integer := 128; 12 | dataWidth: integer := 8; 13 | initFile: string := "ram.mif" 14 | ); 15 | port( 16 | clkA: in std_logic; 17 | writeEnableA: in std_logic; 18 | addrA: in std_logic_vector(ceil_log2(numElements)-1 downto 0); 19 | dataOutA: out std_logic_vector(dataWidth-1 downto 0); 20 | dataInA: in std_logic_vector(dataWidth-1 downto 0) 21 | ); 22 | end sync_ram_init; 23 | 24 | architecture Behavioral of sync_ram_init is 25 | type rom_type is array (0 to numElements-1) of std_logic_vector(dataWidth-1 downto 0); 26 | signal RAM: rom_type; 27 | attribute ram_init_file : string; 28 | attribute ram_init_file of RAM : signal is initFile; 29 | 30 | begin 31 | -- addr register to infer block RAM 32 | setRegA: process (clkA) 33 | begin 34 | if rising_edge(clkA) then 35 | -- Write to rom 36 | if(writeEnableA = '1') then 37 | RAM(to_integer(unsigned(addrA))) <= dataInA; 38 | end if; 39 | -- Read from it 40 | dataOutA <= RAM(to_integer(unsigned(addrA))); 41 | end if; 42 | end process; 43 | end Behavioral; 44 | 45 | -------------------------------------------------------------------------------- /bonuses/proj1/terrain.vhd: -------------------------------------------------------------------------------- 1 | -- terrain: Logic and graphics generation 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | library work; 6 | 7 | -- For vgaText library 8 | use work.commonPak.all; 9 | -- Common constants 10 | use work.defender_common.all; 11 | 12 | entity terrain is 13 | port ( 14 | i_clock : in std_logic; 15 | i_anim_en : in std_logic; 16 | 17 | -- Control Signals 18 | i_scan_pos : in t_point_2d; 19 | i_draw_en : in std_logic; 20 | 21 | o_color : out integer range 0 to c_max_color; 22 | o_draw : out std_logic 23 | ); 24 | end entity terrain; 25 | 26 | architecture rtl of terrain is 27 | 28 | -- Constants 29 | 30 | 31 | -- Types 32 | 33 | -- Signals 34 | signal w_sf_on : std_logic_vector(2 downto 0); 35 | signal w_sf_bright_0 : std_logic_vector(7 downto 0); 36 | signal w_sf_bright_1 : std_logic_vector(7 downto 0); 37 | signal w_sf_bright_2 : std_logic_vector(7 downto 0); 38 | 39 | 40 | begin 41 | 42 | 43 | -- Set draw output 44 | process(i_scan_pos) 45 | variable r_draw_tmp : std_logic := '0'; 46 | variable r_color_tmp : integer range 0 to c_max_color := 0; 47 | 48 | begin 49 | 50 | r_draw_tmp := '0'; 51 | r_color_tmp := 0; 52 | 53 | -- Draw the starfields, varying levels of white 54 | if (w_sf_on(0) = '1') then 55 | r_color_tmp := to_integer(unsigned(w_sf_bright_0(7 downto 4) & w_sf_bright_0(7 downto 4) & w_sf_bright_0(7 downto 4))); 56 | r_draw_tmp := '1'; 57 | end if; 58 | if (w_sf_on(1) = '1') then 59 | r_color_tmp := to_integer(unsigned(w_sf_bright_1(7 downto 4) & w_sf_bright_1(7 downto 4) & w_sf_bright_1(7 downto 4))); 60 | r_draw_tmp := '1'; 61 | end if; 62 | if (w_sf_on(2) = '1') then 63 | r_color_tmp := to_integer(unsigned(w_sf_bright_2(7 downto 4) & w_sf_bright_2(7 downto 4) & w_sf_bright_2(7 downto 4))); 64 | r_draw_tmp := '1'; 65 | end if; 66 | 67 | -- Override all drawing 68 | if (i_draw_en = '0') then 69 | r_draw_tmp := '0'; 70 | r_color_tmp := 0; 71 | end if; 72 | 73 | -- Assign outputs 74 | o_draw <= r_draw_tmp; 75 | o_color <= r_color_tmp; 76 | end process; 77 | 78 | 79 | -- Instantiation 80 | sf0: entity work.starfield 81 | generic map ( 82 | g_incr => -1, 83 | g_seed => std_logic_vector(to_unsigned(16#9A9A9#, 21)) 84 | ) 85 | port map ( 86 | i_clock => i_clock, 87 | i_anim_en => i_anim_en, 88 | i_draw_en => i_draw_en, 89 | i_reset => '0', 90 | o_sf_on => w_sf_on(0), 91 | o_sf_bright => w_sf_bright_0 92 | ); 93 | 94 | sf1: entity work.starfield 95 | generic map ( 96 | g_incr => -2, 97 | g_seed => std_logic_vector(to_unsigned(16#A9A9A#, 21)) 98 | ) 99 | port map ( 100 | i_clock => i_clock, 101 | i_anim_en => i_anim_en, 102 | i_draw_en => i_draw_en, 103 | i_reset => '0', 104 | o_sf_on => w_sf_on(1), 105 | o_sf_bright => w_sf_bright_1 106 | ); 107 | 108 | sf2: entity work.starfield 109 | generic map ( 110 | g_incr => -4, 111 | g_mask => std_logic_vector(to_unsigned(16#7FF#, 21)) 112 | ) 113 | port map ( 114 | i_clock => i_clock, 115 | i_anim_en => i_anim_en, 116 | i_draw_en => i_draw_en, 117 | i_reset => '0', 118 | o_sf_on => w_sf_on(2), 119 | o_sf_bright => w_sf_bright_2 120 | ); 121 | 122 | end architecture rtl; -------------------------------------------------------------------------------- /docs/f21_spec.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/docs/f21_spec.pdf -------------------------------------------------------------------------------- /flash/proj0.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/flash/proj0.pof -------------------------------------------------------------------------------- /flash/proj0.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/flash/proj0.sof -------------------------------------------------------------------------------- /flash/proj1.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/flash/proj1.pof -------------------------------------------------------------------------------- /flash/proj1.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/flash/proj1.sof -------------------------------------------------------------------------------- /img/banner.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/img/banner.gif -------------------------------------------------------------------------------- /img/board.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/img/board.jpg -------------------------------------------------------------------------------- /img/demo1.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/img/demo1.gif -------------------------------------------------------------------------------- /img/demo2.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/img/demo2.gif -------------------------------------------------------------------------------- /img/proj1_res_use.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/img/proj1_res_use.png -------------------------------------------------------------------------------- /test/effect_test/DE10_LITE_Golden_Top.v: -------------------------------------------------------------------------------- 1 | // ============================================================================ 2 | // Ver :| Author :| Mod. Date :| Changes Made: 3 | // V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file 4 | // ============================================================================ 5 | 6 | 7 | //======================================================= 8 | // This code is generated by Terasic System Builder 9 | //======================================================= 10 | 11 | `define ENABLE_ADC_CLOCK 12 | `define ENABLE_CLOCK1 13 | `define ENABLE_CLOCK2 14 | `define ENABLE_SDRAM 15 | `define ENABLE_HEX0 16 | `define ENABLE_HEX1 17 | `define ENABLE_HEX2 18 | `define ENABLE_HEX3 19 | `define ENABLE_HEX4 20 | `define ENABLE_HEX5 21 | `define ENABLE_KEY 22 | `define ENABLE_LED 23 | `define ENABLE_SW 24 | `define ENABLE_VGA 25 | `define ENABLE_ACCELEROMETER 26 | `define ENABLE_ARDUINO 27 | `define ENABLE_GPIO 28 | 29 | module DE10_LITE_Golden_Top( 30 | 31 | //////////// ADC CLOCK: 3.3-V LVTTL ////////// 32 | `ifdef ENABLE_ADC_CLOCK 33 | input ADC_CLK_10, 34 | `endif 35 | //////////// CLOCK 1: 3.3-V LVTTL ////////// 36 | `ifdef ENABLE_CLOCK1 37 | input MAX10_CLK1_50, 38 | `endif 39 | //////////// CLOCK 2: 3.3-V LVTTL ////////// 40 | `ifdef ENABLE_CLOCK2 41 | input MAX10_CLK2_50, 42 | `endif 43 | 44 | //////////// SDRAM: 3.3-V LVTTL ////////// 45 | `ifdef ENABLE_SDRAM 46 | output [12:0] DRAM_ADDR, 47 | output [1:0] DRAM_BA, 48 | output DRAM_CAS_N, 49 | output DRAM_CKE, 50 | output DRAM_CLK, 51 | output DRAM_CS_N, 52 | inout [15:0] DRAM_DQ, 53 | output DRAM_LDQM, 54 | output DRAM_RAS_N, 55 | output DRAM_UDQM, 56 | output DRAM_WE_N, 57 | `endif 58 | 59 | //////////// SEG7: 3.3-V LVTTL ////////// 60 | `ifdef ENABLE_HEX0 61 | output [7:0] HEX0, 62 | `endif 63 | `ifdef ENABLE_HEX1 64 | output [7:0] HEX1, 65 | `endif 66 | `ifdef ENABLE_HEX2 67 | output [7:0] HEX2, 68 | `endif 69 | `ifdef ENABLE_HEX3 70 | output [7:0] HEX3, 71 | `endif 72 | `ifdef ENABLE_HEX4 73 | output [7:0] HEX4, 74 | `endif 75 | `ifdef ENABLE_HEX5 76 | output [7:0] HEX5, 77 | `endif 78 | 79 | //////////// KEY: 3.3 V SCHMITT TRIGGER ////////// 80 | `ifdef ENABLE_KEY 81 | input [1:0] KEY, 82 | `endif 83 | 84 | //////////// LED: 3.3-V LVTTL ////////// 85 | `ifdef ENABLE_LED 86 | output [9:0] LEDR, 87 | `endif 88 | 89 | //////////// SW: 3.3-V LVTTL ////////// 90 | `ifdef ENABLE_SW 91 | input [9:0] SW, 92 | `endif 93 | 94 | //////////// VGA: 3.3-V LVTTL ////////// 95 | `ifdef ENABLE_VGA 96 | output [3:0] VGA_B, 97 | output [3:0] VGA_G, 98 | output VGA_HS, 99 | output [3:0] VGA_R, 100 | output VGA_VS, 101 | `endif 102 | 103 | //////////// Accelerometer: 3.3-V LVTTL ////////// 104 | `ifdef ENABLE_ACCELEROMETER 105 | output GSENSOR_CS_N, 106 | input [2:1] GSENSOR_INT, 107 | output GSENSOR_SCLK, 108 | inout GSENSOR_SDI, 109 | inout GSENSOR_SDO, 110 | `endif 111 | 112 | //////////// Arduino: 3.3-V LVTTL ////////// 113 | `ifdef ENABLE_ARDUINO 114 | inout [15:0] ARDUINO_IO, 115 | inout ARDUINO_RESET_N, 116 | `endif 117 | 118 | //////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL ////////// 119 | `ifdef ENABLE_GPIO 120 | inout [35:0] GPIO 121 | `endif 122 | ); 123 | 124 | 125 | 126 | //======================================================= 127 | // REG/WIRE declarations 128 | //======================================================= 129 | 130 | 131 | 132 | 133 | //======================================================= 134 | // Structural coding 135 | //======================================================= 136 | 137 | 138 | 139 | endmodule 140 | -------------------------------------------------------------------------------- /test/effect_test/clock_div.vhd: -------------------------------------------------------------------------------- 1 | -- Configurable n-bit clock divider (clock_div) 2 | LIBRARY IEEE; 3 | USE IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | 6 | ENTITY clock_div IS 7 | GENERIC (n : NATURAL := 8); 8 | PORT ( clock_in, reset : IN STD_LOGIC; 9 | divisor : IN STD_LOGIC_VECTOR(n DOWNTO 0); -- divisor = 2*(max_cnt+1) 10 | clock_out : OUT STD_LOGIC ); 11 | END clock_div; 12 | 13 | ARCHITECTURE behavior OF clock_div IS 14 | -- Constants 15 | 16 | -- Types 17 | 18 | -- Component declarations 19 | 20 | -- Signal declarations 21 | SIGNAL count : STD_LOGIC_VECTOR(n-1 DOWNTO 0); -- Internal counter 22 | SIGNAL max_cnt : STD_LOGIC_VECTOR(n-1 DOWNTO 0); 23 | SIGNAL temp_clock : STD_LOGIC := '0'; 24 | 25 | BEGIN 26 | 27 | max_cnt <= (divisor(n DOWNTO 1) - '1'); -- Bit shift right (div by 2) then sub 1 28 | 29 | PROCESS (clock_in, reset) BEGIN 30 | 31 | -- Asynch reset 32 | IF (reset = '1') THEN 33 | count <= (OTHERS => '0'); 34 | temp_clock <= '0'; 35 | 36 | -- Clocked behavior 37 | ELSIF (clock_in'event AND clock_in = '1') THEN 38 | 39 | IF (count >= max_cnt) THEN 40 | temp_clock <= NOT temp_clock; 41 | count <= (OTHERS => '0'); 42 | ELSE 43 | count <= count + '1'; 44 | END IF; 45 | 46 | END IF; 47 | 48 | END PROCESS; 49 | 50 | -- Instantiation AND port mapping 51 | 52 | -- Concurrent assignments 53 | clock_out <= temp_clock; 54 | 55 | END behavior; -------------------------------------------------------------------------------- /test/effect_test/effect_gen_tb.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /effect_gen_tb/reset_n 4 | add wave -noupdate /effect_gen_tb/test_clk 5 | add wave -noupdate /effect_gen_tb/effect_cmd 6 | add wave -noupdate /effect_gen_tb/buzz_out 7 | add wave -noupdate /effect_gen_tb/UUT/r_state 8 | add wave -noupdate -radix hexadecimal /effect_gen_tb/UUT/r_romAddr 9 | add wave -noupdate -radix unsigned /effect_gen_tb/UUT/w_romData 10 | add wave -noupdate /effect_gen_tb/UUT/r_buzzDisable 11 | add wave -noupdate -radix hexadecimal /effect_gen_tb/UUT/r_buzzDivisor 12 | TreeUpdate [SetDefaultTree] 13 | WaveRestoreCursors {{Cursor 1} {1000 ps} 0} 14 | quietly wave cursor active 1 15 | configure wave -namecolwidth 236 16 | configure wave -valuecolwidth 100 17 | configure wave -justifyvalue left 18 | configure wave -signalnamewidth 0 19 | configure wave -snapdistance 10 20 | configure wave -datasetprefix 0 21 | configure wave -rowmargin 4 22 | configure wave -childrowmargin 2 23 | configure wave -gridoffset 0 24 | configure wave -gridperiod 1 25 | configure wave -griddelta 40 26 | configure wave -timeline 0 27 | configure wave -timelineunits ns 28 | update 29 | WaveRestoreZoom {0 ps} {194325 ps} 30 | run 4000 ns -------------------------------------------------------------------------------- /test/effect_test/effect_gen_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Testbench for effect_gen 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.all; 4 | 5 | ENTITY effect_gen_tb IS 6 | END effect_gen_tb; 7 | 8 | ARCHITECTURE behavior OF effect_gen_tb IS 9 | 10 | -- Component declarations 11 | component effect_gen is 12 | port ( 13 | i_clock : in std_logic; 14 | i_reset_n : in std_logic; 15 | 16 | i_launch : in std_logic; 17 | i_playerFire : in std_logic; 18 | i_enemyFire : in std_logic; 19 | i_enemyDestroy : in std_logic; 20 | i_playerDestroy : in std_logic; 21 | 22 | o_buzzPin : out std_logic 23 | ); 24 | end component; 25 | 26 | -- Constants 27 | CONSTANT clock_period: TIME := 20 ns; -- 50 MHz 28 | 29 | -- Signal declarations 30 | signal reset_n : std_logic; 31 | SIGNAL test_clk : STD_LOGIC; 32 | signal effect_cmd : std_logic_vector(4 downto 0); 33 | signal buzz_out : std_logic; 34 | 35 | BEGIN 36 | 37 | -- Instantiation and port mapping 38 | UUT : effect_gen port map ( 39 | i_clock => test_clk, 40 | i_reset_n => reset_n, 41 | 42 | i_launch => effect_cmd(0), 43 | i_playerFire => effect_cmd(1), 44 | i_enemyFire => effect_cmd(2), 45 | i_enemyDestroy => effect_cmd(3), 46 | i_playerDestroy => effect_cmd(4), 47 | 48 | o_buzzPin => buzz_out 49 | ); 50 | 51 | 52 | clock_process: PROCESS 53 | BEGIN 54 | test_clk <= '0'; 55 | WAIT FOR clock_period/2; 56 | test_clk <= '1'; 57 | WAIT FOR clock_period/2; 58 | END PROCESS; 59 | 60 | vectors: PROCESS 61 | BEGIN 62 | reset_n <= '0'; 63 | WAIT FOR 20 ns; 64 | reset_n <= '1'; 65 | effect_cmd <= "00001"; 66 | wait for 100 ns; 67 | WAIT; 68 | END PROCESS; 69 | 70 | 71 | END; 72 | -------------------------------------------------------------------------------- /test/effect_test/effect_mem.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2020 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and any partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details, at 14 | --https://fpgasoftware.intel.com/eula. 15 | 16 | 17 | component effect_mem 18 | PORT 19 | ( 20 | address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 21 | clock : IN STD_LOGIC := '1'; 22 | q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) 23 | ); 24 | end component; 25 | -------------------------------------------------------------------------------- /test/effect_test/effect_mem.mif: -------------------------------------------------------------------------------- 1 | DEPTH = 1024; 2 | WIDTH = 12; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = UNS; 5 | CONTENT 6 | BEGIN 7 | -- Effect program (8 effect slots): 8 | -- n = # of steps (63 max) 9 | -- Step 0...n-1 : freq (hz) and duration (msec) (12 bits each) 10 | 11 | -- Effect 0 : Launch (10 ramp segments of inc max freq, each ramp is 6 steps, 44 msec each) 12 | 000: 60; 13 | 14 | -- Ramp 1 15 | 001: 400; 16 | 002: 44; 17 | 18 | 003: 520; 19 | 004: 44; 20 | 21 | 005: 640; 22 | 006: 44; 23 | 24 | 007: 760; 25 | 008: 44; 26 | 27 | 009: 880; 28 | 00A: 44; 29 | 30 | 00B: 1000; 31 | 00C: 44; 32 | 33 | -- Ramp 2 34 | 00D: 400; 35 | 00E: 44; 36 | 37 | 00F: 587; 38 | 010: 44; 39 | 40 | 011: 773; 41 | 012: 44; 42 | 43 | 013: 960; 44 | 014: 44; 45 | 46 | 015: 1146; 47 | 016: 44; 48 | 49 | 017: 1333; 50 | 018: 44; 51 | 52 | -- Ramp 3 53 | 019: 400; 54 | 01A: 44; 55 | 56 | 01B: 653; 57 | 01C: 44; 58 | 59 | 01D: 906; 60 | 01E: 44; 61 | 62 | 01F: 1160; 63 | 020: 44; 64 | 65 | 021: 1413; 66 | 022: 44; 67 | 68 | 023: 1666; 69 | 024: 44; 70 | 71 | -- Ramp 4 72 | 025: 400; 73 | 026: 44; 74 | 75 | 027: 720; 76 | 028: 44; 77 | 78 | 029: 1040; 79 | 02A: 44; 80 | 81 | 02B: 1360; 82 | 02C: 44; 83 | 84 | 02D: 1680; 85 | 02E: 44; 86 | 87 | 02F: 2000; 88 | 030: 44; 89 | 90 | 91 | -- Ramp 5 92 | 031: 400; 93 | 032: 44; 94 | 95 | 033: 787; 96 | 034: 44; 97 | 98 | 035: 1173; 99 | 036: 44; 100 | 101 | 037: 1560; 102 | 038: 44; 103 | 104 | 039: 1946; 105 | 03A: 44; 106 | 107 | 03B: 2333; 108 | 03C: 44; 109 | 110 | -- Ramp 6 111 | 03D: 400; 112 | 03E: 44; 113 | 114 | 03F: 853; 115 | 040: 44; 116 | 117 | 041: 1306; 118 | 042: 44; 119 | 120 | 043: 1760; 121 | 044: 44; 122 | 123 | 045: 2213; 124 | 046: 44; 125 | 126 | 047: 2666; 127 | 048: 44; 128 | 129 | -- Ramp 7 130 | 049: 400; 131 | 04A: 44; 132 | 133 | 04B: 920; 134 | 04C: 44; 135 | 136 | 04D: 1440; 137 | 04E: 44; 138 | 139 | 04F: 1960; 140 | 050: 44; 141 | 142 | 051: 2480; 143 | 052: 44; 144 | 145 | 053: 3000; 146 | 054: 44; 147 | 148 | -- Ramp 8 149 | 055: 400; 150 | 056: 44; 151 | 152 | 057: 987; 153 | 058: 44; 154 | 155 | 059: 1573; 156 | 05A: 44; 157 | 158 | 05B: 2160; 159 | 05C: 44; 160 | 161 | 05D: 2746; 162 | 05E: 44; 163 | 164 | 05F: 3333; 165 | 060: 44; 166 | 167 | 168 | -- Ramp 9 169 | 061: 400; 170 | 062: 44; 171 | 172 | 063: 1053; 173 | 064: 44; 174 | 175 | 065: 1706; 176 | 066: 44; 177 | 178 | 067: 2360; 179 | 068: 44; 180 | 181 | 069: 3013; 182 | 06A: 44; 183 | 184 | 06B: 3666; 185 | 06C: 44; 186 | 187 | -- Ramp 10 188 | 06D: 400; 189 | 06E: 44; 190 | 191 | 06F: 1120; 192 | 070: 44; 193 | 194 | 071: 1840; 195 | 072: 44; 196 | 197 | 073: 2560; 198 | 074: 44; 199 | 200 | 075: 3280; 201 | 076: 44; 202 | 203 | 077: 4000; 204 | 078: 44; 205 | 206 | 207 | -- Unused 208 | 079: 50; 209 | 07A: 511; 210 | 211 | 07B: 60; 212 | 07C: 511; 213 | 214 | 07D: 70; 215 | 07E: 511; 216 | 217 | 07F: 80; 218 | 219 | -- Effect 1 : Player fire (Ramp down w/ static?) 220 | 080: 12; 221 | 222 | 081: 511; -- Step 0: 10 Hz for 511 msec 223 | 082: 50; 224 | 225 | 083: 475; 226 | 084: 50; 227 | 228 | 085: 450; 229 | 086: 50; 230 | 231 | 087: 425; 232 | 088: 50; 233 | 234 | 089: 400; 235 | 08A: 50; 236 | 237 | 08B: 375; 238 | 08C: 50; 239 | 240 | 08D: 350; 241 | 08E: 50; 242 | 243 | 08F: 300; 244 | 090: 50; 245 | 246 | 091: 250; 247 | 092: 50; 248 | 249 | 093: 200; 250 | 094: 50; 251 | 252 | 095: 150; 253 | 096: 50; 254 | 255 | 097: 100; 256 | 098: 50; 257 | 258 | 259 | -- Effect 2 : Enemy fire (Ramp down, diff range/speed) 260 | 100: 9; 261 | 262 | 101: 400; -- Step 0: 10 Hz for 511 msec 263 | 102: 50; 264 | 265 | 103: 375; 266 | 104: 50; 267 | 268 | 105: 350; 269 | 106: 50; 270 | 271 | 107: 325; 272 | 108: 50; 273 | 274 | 109: 300; 275 | 10A: 50; 276 | 277 | 10B: 250; 278 | 10C: 50; 279 | 280 | 10D: 200; 281 | 10E: 50; 282 | 283 | 10F: 150; 284 | 110: 50; 285 | 286 | 111: 100; 287 | 112: 50; 288 | 289 | -- Effect 3 : Enemy destroy (ramp up) 290 | 180: 12; 291 | 292 | 181: 100; -- Step 0: 10 Hz for 511 msec 293 | 182: 50; 294 | 295 | 183: 125; 296 | 184: 50; 297 | 298 | 185: 150; 299 | 186: 50; 300 | 301 | 187: 175; 302 | 188: 50; 303 | 304 | 189: 200; 305 | 18A: 50; 306 | 307 | 18B: 225; 308 | 18C: 50; 309 | 310 | 18D: 250; 311 | 18E: 50; 312 | 313 | 18F: 300; 314 | 190: 50; 315 | 316 | 191: 350; 317 | 192: 50; 318 | 319 | 193: 400; 320 | 194: 50; 321 | 322 | 195: 475; 323 | 196: 50; 324 | 325 | 197: 511; 326 | 198: 50; 327 | 328 | -- Effect 4 : Player destroy (static explosion or "waa-waa-waa :(" ) 329 | 200: 12; 330 | 331 | 201: 500; -- Step 0: 10 Hz for 511 msec 332 | 202: 100; 333 | 334 | 203: 250; 335 | 204: 100; 336 | 337 | 205: 500; 338 | 206: 100; 339 | 340 | 207: 250; 341 | 208: 100; 342 | 343 | 209: 400; 344 | 20A: 100; 345 | 346 | 20B: 200; 347 | 20C: 100; 348 | 349 | 20D: 400; 350 | 20E: 100; 351 | 352 | 20F: 200; 353 | 210: 100; 354 | 355 | 211: 300; 356 | 212: 100; 357 | 358 | 213: 150; 359 | 214: 100; 360 | 361 | 215: 300; 362 | 216: 100; 363 | 364 | 217: 150; 365 | 218: 100; 366 | 367 | 368 | 369 | -- Effect 5 370 | 280:10; 371 | 372 | -- Effect 6 373 | 300:10; 374 | 375 | -- Effect 7 376 | 380:10; 377 | END; 378 | -------------------------------------------------------------------------------- /test/effect_test/effect_mem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "20.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "effect_mem.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "effect_mem.cmp"] 6 | -------------------------------------------------------------------------------- /test/effect_test/effect_mem.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %ROM: 1-PORT% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: altsyncram 5 | 6 | -- ============================================================ 7 | -- File Name: effect_mem.vhd 8 | -- Megafunction Name(s): 9 | -- altsyncram 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 20.1.1 Build 720 11/11/2020 SJ Lite Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 2020 Intel Corporation. All rights reserved. 22 | --Your use of Intel Corporation's design tools, logic functions 23 | --and other software and tools, and any partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Intel Program License 28 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | --the Intel FPGA IP License Agreement, or other applicable license 30 | --agreement, including, without limitation, that your use is for 31 | --the sole purpose of programming logic devices manufactured by 32 | --Intel and sold by Intel or its authorized distributors. Please 33 | --refer to the applicable agreement for further details, at 34 | --https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | LIBRARY ieee; 38 | USE ieee.std_logic_1164.all; 39 | 40 | LIBRARY altera_mf; 41 | USE altera_mf.altera_mf_components.all; 42 | 43 | ENTITY effect_mem IS 44 | PORT 45 | ( 46 | address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); 47 | clock : IN STD_LOGIC := '1'; 48 | q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) 49 | ); 50 | END effect_mem; 51 | 52 | 53 | ARCHITECTURE SYN OF effect_mem IS 54 | 55 | SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0); 56 | 57 | BEGIN 58 | q <= sub_wire0(11 DOWNTO 0); 59 | 60 | altsyncram_component : altsyncram 61 | GENERIC MAP ( 62 | address_aclr_a => "NONE", 63 | clock_enable_input_a => "BYPASS", 64 | clock_enable_output_a => "BYPASS", 65 | init_file => "../effect_mem.mif", 66 | intended_device_family => "MAX 10", 67 | lpm_hint => "ENABLE_RUNTIME_MOD=NO", 68 | lpm_type => "altsyncram", 69 | numwords_a => 1024, 70 | operation_mode => "ROM", 71 | outdata_aclr_a => "NONE", 72 | outdata_reg_a => "UNREGISTERED", 73 | widthad_a => 10, 74 | width_a => 12, 75 | width_byteena_a => 1 76 | ) 77 | PORT MAP ( 78 | address_a => address, 79 | clock0 => clock, 80 | q_a => sub_wire0 81 | ); 82 | 83 | 84 | 85 | END SYN; 86 | 87 | -- ============================================================ 88 | -- CNX file retrieval info 89 | -- ============================================================ 90 | -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 91 | -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 92 | -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" 93 | -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 94 | -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 95 | -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 96 | -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 97 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 98 | -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 99 | -- Retrieval info: PRIVATE: Clken NUMERIC "0" 100 | -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 101 | -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 102 | -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 103 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" 104 | -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 105 | -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 106 | -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 107 | -- Retrieval info: PRIVATE: MIFfilename STRING "../effect_mem.mif" 108 | -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" 109 | -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 110 | -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" 111 | -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" 112 | -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 113 | -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" 114 | -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 115 | -- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" 116 | -- Retrieval info: PRIVATE: WidthData NUMERIC "12" 117 | -- Retrieval info: PRIVATE: rden NUMERIC "0" 118 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 119 | -- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 120 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 121 | -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 122 | -- Retrieval info: CONSTANT: INIT_FILE STRING "../effect_mem.mif" 123 | -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" 124 | -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 125 | -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 126 | -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" 127 | -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 128 | -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 129 | -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 130 | -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" 131 | -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "12" 132 | -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 133 | -- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" 134 | -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 135 | -- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]" 136 | -- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 137 | -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 138 | -- Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0 139 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.vhd TRUE 140 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.inc FALSE 141 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.cmp TRUE 142 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem.bsf FALSE 143 | -- Retrieval info: GEN_FILE: TYPE_NORMAL effect_mem_inst.vhd FALSE 144 | -- Retrieval info: LIB_FILE: altera_mf 145 | -------------------------------------------------------------------------------- /test/effect_test/effect_mem_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Testbench for effect_mem 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.all; 4 | use ieee.NUMERIC_STD.all; 5 | 6 | ENTITY effect_mem_tb IS 7 | END effect_mem_tb; 8 | 9 | ARCHITECTURE behavior OF effect_mem_tb IS 10 | 11 | -- Component declarations 12 | component effect_mem is 13 | port 14 | ( 15 | address : in std_logic_vector (9 downto 0); 16 | clock : in std_logic := '1'; 17 | q : out std_logic_vector (8 downto 0) 18 | ); 19 | end component; 20 | 21 | -- Constants 22 | CONSTANT clock_period: TIME := 20 ns; -- 50 MHz 23 | 24 | -- Signal declarations 25 | signal reset_n : std_logic; 26 | SIGNAL test_clk : STD_LOGIC; 27 | signal mem_addr : std_logic_vector(9 downto 0); 28 | signal mem_data : std_logic_vector(8 downto 0); 29 | 30 | BEGIN 31 | 32 | -- Instantiation and port mapping 33 | UUT : effect_mem port map ( 34 | address => mem_addr, 35 | clock => test_clk, 36 | 37 | q => mem_data 38 | 39 | ); 40 | 41 | 42 | clock_process: PROCESS 43 | BEGIN 44 | test_clk <= '0'; 45 | WAIT FOR clock_period/2; 46 | test_clk <= '1'; 47 | WAIT FOR clock_period/2; 48 | END PROCESS; 49 | 50 | vectors: PROCESS 51 | BEGIN 52 | mem_addr <= "00" & X"00"; 53 | WAIT FOR 80 ns; 54 | mem_addr <= "00" & X"01"; 55 | WAIT FOR 80 ns; 56 | mem_addr <= "00" & X"02"; 57 | WAIT FOR 80 ns; 58 | mem_addr <= "00" & X"03"; 59 | WAIT FOR 80 ns; 60 | mem_addr <= "00" & X"04"; 61 | WAIT FOR 80 ns; 62 | mem_addr <= "00" & X"05"; 63 | WAIT FOR 80 ns; 64 | mem_addr <= "00" & X"06"; 65 | WAIT FOR 80 ns; 66 | 67 | WAIT; 68 | END PROCESS; 69 | 70 | 71 | END; 72 | -------------------------------------------------------------------------------- /test/effect_test/effect_test.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition 22 | # Date created = 16:24:34 October 09, 2021 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.1" 27 | DATE = "16:24:34 October 09, 2021" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "effect_test" 32 | -------------------------------------------------------------------------------- /test/effect_test/effect_test.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/w3arycod3r/fpga-defender/fbf955fd9b7b3da9db6014a283e0389be92a8646/test/effect_test/effect_test.qws -------------------------------------------------------------------------------- /test/effect_test/effect_test_top.vhd: -------------------------------------------------------------------------------- 1 | -- Buzzer effect tester 2 | -- Top level entity 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | use ieee.numeric_std.all; 6 | 7 | entity effect_test_top is 8 | PORT( 9 | KEY : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 10 | SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 11 | MAX10_CLK1_50 : IN STD_LOGIC; -- 50 MHz clock input 12 | LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); 13 | ARDUINO_IO : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); 14 | HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 15 | -- Accelerometer I/O 16 | GSENSOR_CS_N : OUT STD_LOGIC; 17 | GSENSOR_SCLK : OUT STD_LOGIC; 18 | GSENSOR_SDI : INOUT STD_LOGIC; 19 | GSENSOR_SDO : INOUT STD_LOGIC; 20 | 21 | -- VGA I/O 22 | VGA_HS : OUT STD_LOGIC; -- horizontal sync pulse 23 | VGA_VS : OUT STD_LOGIC; -- vertical sync pulse 24 | 25 | VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); -- red magnitude output to DAC 26 | VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); -- green magnitude output to DAC 27 | VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0') -- blue magnitude output to DAC 28 | ); 29 | end effect_test_top; 30 | 31 | architecture top_level of effect_test_top is 32 | 33 | -- Component declarations 34 | component effect_gen is 35 | port ( 36 | i_clock : in std_logic; 37 | i_reset_n : in std_logic; 38 | 39 | i_effectSel : in std_logic_vector(2 downto 0); 40 | i_effectTrig : in std_logic; 41 | o_buzzPin : out std_logic 42 | ); 43 | end component; 44 | 45 | -- Signal declarations 46 | signal KEY_b : std_logic_vector(1 downto 0) ; 47 | 48 | begin 49 | -- Concurrent assignments 50 | KEY_b <= not KEY; 51 | 52 | -- Clear displays 53 | HEX5 <= (OTHERS => '1'); 54 | HEX4 <= (OTHERS => '1'); 55 | HEX3 <= (OTHERS => '1'); 56 | HEX2 <= (OTHERS => '1'); 57 | HEX1 <= (OTHERS => '1'); 58 | HEX0 <= (OTHERS => '1'); 59 | 60 | 61 | -- Instantiation and port mapping 62 | U1 : effect_gen port map ( 63 | i_clock => MAX10_CLK1_50, 64 | i_reset_n => KEY(0), 65 | 66 | i_effectSel => SW(2 downto 0), 67 | i_effectTrig => KEY_b(1), 68 | 69 | o_buzzPin => ARDUINO_IO(12) 70 | ); 71 | 72 | end top_level; --------------------------------------------------------------------------------