├── Project ├── project1 │ ├── Arch_project1.docx │ ├── bi_mode.cc │ ├── bi_mode.hh │ ├── project1_handout_1.pdf │ └── source │ │ ├── gshare.cc │ │ ├── gshare.hh │ │ ├── yags.cc │ │ └── yags.hh ├── project2 │ ├── 18640_Project_2_F2015(1).pdf │ └── handin │ │ ├── config_1 │ │ ├── config_2 │ │ ├── o3 │ │ ├── FUPool.py │ │ ├── FuncUnitConfig.py │ │ ├── O3CPU.py │ │ ├── O3Checker.py │ │ ├── SConscript │ │ ├── SConsopts │ │ ├── base_dyn_inst.cc │ │ ├── checker.cc │ │ ├── checker.hh │ │ ├── comm.hh │ │ ├── commit.cc │ │ ├── commit.hh │ │ ├── commit_impl.hh │ │ ├── cpu.cc │ │ ├── cpu.hh │ │ ├── cpu_policy.hh │ │ ├── decode.cc │ │ ├── decode.hh │ │ ├── decode_impl.hh │ │ ├── dep_graph.hh │ │ ├── deriv.cc │ │ ├── deriv.hh │ │ ├── dyn_inst.cc │ │ ├── dyn_inst.hh │ │ ├── dyn_inst_impl.hh │ │ ├── fetch.cc │ │ ├── fetch.hh │ │ ├── fetch_impl.hh │ │ ├── free_list.cc │ │ ├── free_list.hh │ │ ├── fu_pool.cc │ │ ├── fu_pool.hh │ │ ├── iew.cc │ │ ├── iew.hh │ │ ├── iew_impl.hh │ │ ├── impl.hh │ │ ├── inst_queue.cc │ │ ├── inst_queue.hh │ │ ├── inst_queue_impl.hh │ │ ├── isa_specific.hh │ │ ├── lsq.cc │ │ ├── lsq.hh │ │ ├── lsq_impl.hh │ │ ├── lsq_unit.cc │ │ ├── lsq_unit.hh │ │ ├── lsq_unit_impl.hh │ │ ├── mem_dep_unit.cc │ │ ├── mem_dep_unit.hh │ │ ├── mem_dep_unit_impl.hh │ │ ├── regfile.cc │ │ ├── regfile.hh │ │ ├── rename.cc │ │ ├── rename.hh │ │ ├── rename_impl.hh │ │ ├── rename_map.cc │ │ ├── rename_map.hh │ │ ├── rob.cc │ │ ├── rob.hh │ │ ├── rob_impl.hh │ │ ├── scoreboard.cc │ │ ├── scoreboard.hh │ │ ├── store_set.cc │ │ ├── store_set.hh │ │ ├── thread_context.cc │ │ ├── thread_context.hh │ │ ├── thread_context_impl.hh │ │ └── thread_state.hh │ │ ├── pro2_report.docx │ │ ├── stat_1 │ │ └── stat_2 ├── project3 │ ├── Part1 │ │ ├── base.cc │ │ ├── base.hh │ │ ├── blk.cc │ │ ├── blk.hh │ │ ├── cacheset.hh │ │ ├── lfu_WLT.cc │ │ ├── lfu_WLT.hh │ │ ├── lru.cc │ │ ├── lru.hh │ │ ├── packet.cc │ │ └── packet.hh │ ├── Part2 │ │ ├── MI_example-cache.sm │ │ └── MI_example-dir.sm │ ├── Project3.pdf │ └── report.docx └── project4 │ ├── 18640_project4-4.pdf │ ├── 18640_project4 │ └── mmm │ │ ├── Makefile │ │ ├── README.txt │ │ ├── mmm_all_in_one.c │ │ ├── mmm_multi_thread_scalar.c │ │ ├── mmm_multi_thread_simd.c │ │ ├── mmm_single_thread_scalar.c │ │ └── mmm_single_thread_simd.c │ ├── Project_4_18-640_Fall_15_pdf.pdf │ ├── group7 │ ├── mmm_multi_thread_scalar │ │ ├── consuming_max_time.PNG │ │ ├── mmm_multi_thread_scalar.PNG │ │ └── mmm_multi_thread_scalar.txt │ ├── mmm_multi_thread_simd │ │ ├── consuming_max_time.PNG │ │ ├── mmm_multi_thread_simd.PNG │ │ └── mmm_multi_thread_simd.txt │ ├── mmm_single_thread_scalar │ │ ├── consuming_max_time.PNG │ │ ├── mmm_single_thread_scalar.PNG │ │ └── mmm_single_thread_scalar.txt │ └── mmm_single_thread_simd │ │ ├── consuming_max_time.PNG │ │ ├── mmm_single_thread_simd.PNG │ │ └── mmm_single_thread_simd.txt │ └── report.docx └── README.md /Project/project1/Arch_project1.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project1/Arch_project1.docx -------------------------------------------------------------------------------- /Project/project1/bi_mode.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Anthony Gutierrez 29 | */ 30 | 31 | /* @file 32 | * Implementation of a bi-mode branch predictor 33 | */ 34 | 35 | #ifndef __CPU_PRED_BI_MODE_PRED_HH__ 36 | #define __CPU_PRED_BI_MODE_PRED_HH__ 37 | 38 | #include "cpu/pred/bpred_unit.hh" 39 | #include "cpu/pred/sat_counter.hh" 40 | 41 | /** 42 | * Implements a bi-mode branch predictor. The bi-mode predictor is a two-level 43 | * branch predictor that has three seprate history arrays: a taken array, a 44 | * not-taken array, and a choice array. The taken/not-taken arrays are indexed 45 | * by a hash of the PC and the global history. The choice array is indexed by 46 | * the PC only. Because the taken/not-taken arrays use the same index, they must 47 | * be the same size. 48 | * 49 | * The bi-mode branch predictor aims to eliminate the destructive aliasing that 50 | * occurs when two branches of opposite biases share the same global history 51 | * pattern. By separating the predictors into taken/not-taken arrays, and using 52 | * the branch's PC to choose between the two, destructive aliasing is reduced. 53 | */ 54 | 55 | class BiModeBP : public BPredUnit 56 | { 57 | public: 58 | BiModeBP(const Params *params); 59 | void uncondBranch(void * &bp_history); 60 | void squash(void *bp_history); 61 | bool lookup(Addr branch_addr, void * &bp_history); 62 | void btbUpdate(Addr branch_addr, void * &bp_history); 63 | void update(Addr branch_addr, bool taken, void *bp_history, bool squashed); 64 | void retireSquashed(void *bp_history); 65 | 66 | private: 67 | void updateGlobalHistReg(bool taken); 68 | 69 | struct BPHistory { 70 | unsigned globalHistoryReg; 71 | // was the taken array's prediction used? 72 | // true: takenPred used 73 | // false: notPred used 74 | bool takenUsed; 75 | // prediction of the taken array 76 | // true: predict taken 77 | // false: predict not-taken 78 | bool takenPred; 79 | // prediction of the not-taken array 80 | // true: predict taken 81 | // false: predict not-taken 82 | bool notTakenPred; 83 | // the final taken/not-taken prediction 84 | // true: predict taken 85 | // false: predict not-taken 86 | bool finalPred; 87 | }; 88 | 89 | // choice predictors 90 | std::vector choiceCounters; 91 | // taken direction predictors 92 | std::vector takenCounters; 93 | // not-taken direction predictors 94 | std::vector notTakenCounters; 95 | 96 | unsigned instShiftAmt; 97 | 98 | unsigned globalHistoryReg; 99 | unsigned globalHistoryBits; 100 | unsigned historyRegisterMask; 101 | 102 | unsigned choicePredictorSize; 103 | unsigned choiceCtrBits; 104 | unsigned choiceHistoryMask; 105 | unsigned globalPredictorSize; 106 | unsigned globalCtrBits; 107 | unsigned globalHistoryMask; 108 | 109 | unsigned choiceThreshold; 110 | unsigned takenThreshold; 111 | unsigned notTakenThreshold; 112 | }; 113 | 114 | #endif // __CPU_PRED_BI_MODE_PRED_HH__ 115 | -------------------------------------------------------------------------------- /Project/project1/project1_handout_1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project1/project1_handout_1.pdf -------------------------------------------------------------------------------- /Project/project1/source/gshare.cc: -------------------------------------------------------------------------------- 1 | /* @file 2 | * Implementation of a Gshare branch predictor 3 | * 4 | * 18-640 Foundations of Computer Architecture 5 | * Carnegie Mellon University 6 | * 7 | */ 8 | 9 | #include "base/bitfield.hh" 10 | #include "base/intmath.hh" 11 | #include "cpu/pred/gshare.hh" 12 | 13 | /* 14 | * Constructor for GshareBP 15 | */ 16 | GshareBP::GshareBP(const Params *params) 17 | : BPredUnit(params), instShiftAmt(params->instShiftAmt), 18 | globalHistoryReg(0), 19 | globalHistoryBits(ceilLog2(params->localPredictorSize)), 20 | localPredictorSize(params->localPredictorSize), 21 | localCtrBits(params->localCtrBits) 22 | { 23 | if (!isPowerOf2(localPredictorSize)) 24 | fatal("Invalid local predictor size.\n"); 25 | 26 | localCtrs.resize(localPredictorSize); 27 | 28 | for (int i = 0; i < localPredictorSize; ++i) { 29 | localCtrs[i].setBits(localCtrBits); 30 | } 31 | 32 | historyRegisterMask = mask(globalHistoryBits); 33 | localPredictorMask = localPredictorSize -1; 34 | 35 | localThreshold = (ULL(1) << (localCtrBits - 1)) - 1; 36 | } 37 | /* 38 | * Reset Data Structures 39 | */ 40 | void 41 | GshareBP::reset() 42 | { 43 | for (int i = 0; i < localPredictorSize; ++i) { 44 | localCtrs[i].reset(); 45 | } 46 | //globalHistoryReg = 0; 47 | } 48 | 49 | 50 | /* 51 | * Actions for an unconditional branch 52 | */ 53 | void 54 | GshareBP::uncondBranch(void * &bpHistory) 55 | { 56 | BPHistory *history = new BPHistory; 57 | history->globalHistoryReg = globalHistoryReg; 58 | history->finalPred = true; 59 | bpHistory = static_cast(history); 60 | updateGlobalHistReg(true); 61 | } 62 | 63 | /* 64 | * Lookup the actual branch prediction. 65 | */ 66 | 67 | bool 68 | GshareBP::lookup(Addr branchAddr, void * &bpHistory) 69 | { 70 | unsigned localPredictorIdx = (((branchAddr >> instShiftAmt)//XOR 71 | ^ globalHistoryReg) 72 | & localPredictorMask); 73 | 74 | assert(localPredictorIdx < localPredictorSize ); 75 | 76 | bool finalPrediction = localCtrs[localPredictorIdx].read() 77 | > localThreshold; 78 | 79 | BPHistory *history = new BPHistory; 80 | history->globalHistoryReg = globalHistoryReg; 81 | 82 | history->finalPred = finalPrediction; 83 | 84 | 85 | bpHistory = static_cast(history); 86 | updateGlobalHistReg(finalPrediction); 87 | 88 | return finalPrediction; 89 | } 90 | 91 | /* 92 | * BTB Update actions 93 | */ 94 | void 95 | GshareBP::btbUpdate(Addr branchAddr, void * &bpHistory) 96 | { 97 | globalHistoryReg &= (historyRegisterMask & ~ULL(1)); 98 | } 99 | 100 | /* 101 | * Update data structures after getting actual decison 102 | */ 103 | void 104 | GshareBP::update(Addr branchAddr, bool taken, void *bpHistory, bool squashed) 105 | { 106 | if (bpHistory) { 107 | BPHistory *history = static_cast(bpHistory); 108 | 109 | unsigned localPredictorIdx = (((branchAddr >> instShiftAmt) 110 | ^ history->globalHistoryReg) 111 | & localPredictorMask); 112 | 113 | assert(localPredictorIdx < localPredictorSize); 114 | 115 | if (taken) 116 | { 117 | localCtrs[localPredictorIdx].increment(); 118 | } else { 119 | localCtrs[localPredictorIdx].decrement(); 120 | } 121 | 122 | if (squashed) { 123 | if (taken) { 124 | globalHistoryReg = (history->globalHistoryReg << 1) | 1; 125 | } else { 126 | globalHistoryReg = (history->globalHistoryReg << 1); 127 | } 128 | globalHistoryReg &= historyRegisterMask; 129 | } else { 130 | delete history; 131 | } 132 | } 133 | } 134 | 135 | /* 136 | * Global History Registor Update 137 | */ 138 | void 139 | GshareBP::updateGlobalHistReg(bool taken) 140 | { 141 | globalHistoryReg = taken ? (globalHistoryReg << 1) | 1 : 142 | (globalHistoryReg << 1); 143 | globalHistoryReg &= historyRegisterMask; 144 | } 145 | 146 | /* 147 | * Actions for squash 148 | */ 149 | void 150 | GshareBP::squash(void *bpHistory) { 151 | BPHistory *history = static_cast(bpHistory); 152 | globalHistoryReg = history->globalHistoryReg; 153 | 154 | delete history; 155 | } 156 | -------------------------------------------------------------------------------- /Project/project1/source/gshare.hh: -------------------------------------------------------------------------------- 1 | /* @file 2 | * Header file for Gshare branch predictor 3 | * 4 | * 18-640 Foundations of Computer Architecture 5 | * Carnegie Mellon University 6 | * 7 | */ 8 | 9 | #ifndef __CPU_PRED_GSHARE_PRED_HH__ 10 | #define __CPU_PRED_GSHARE_PRED_HH__ 11 | 12 | #include "cpu/pred/bpred_unit.hh" 13 | #include "cpu/pred/sat_counter.hh" 14 | 15 | /* 16 | * Feel free to make any modifications, this is a skeleton code 17 | * to get you started. 18 | * Note: Do not change name of class 19 | */ 20 | class GshareBP : public BPredUnit 21 | { 22 | public: 23 | GshareBP(const Params *params); 24 | void uncondBranch(void * &bp_history); 25 | void squash(void *bp_history); 26 | bool lookup(Addr branch_addr, void * &bp_history); 27 | void btbUpdate(Addr branch_addr, void * &bp_history); 28 | void update(Addr branch_addr, bool taken, void *bp_history, bool squashed); 29 | void reset(); 30 | 31 | private: 32 | void updateGlobalHistReg(bool taken); 33 | 34 | struct BPHistory { 35 | unsigned globalHistoryReg; 36 | bool finalPred; 37 | }; 38 | 39 | unsigned instShiftAmt; 40 | 41 | unsigned globalHistoryReg; 42 | unsigned globalHistoryBits; 43 | unsigned historyRegisterMask; 44 | 45 | /** Local counters. */ 46 | std::vector localCtrs; 47 | /** Number of counters in the local predictor. */ 48 | unsigned localPredictorSize; 49 | /** Number of bits of the local predictor's counters. */ 50 | unsigned localCtrBits; 51 | 52 | unsigned localPredictorMask; 53 | 54 | unsigned localThreshold; 55 | }; 56 | 57 | #endif // __CPU_PRED_GSHARE_PRED_HH__ 58 | -------------------------------------------------------------------------------- /Project/project1/source/yags.cc: -------------------------------------------------------------------------------- 1 | /* @file 2 | * Implementation of a YAGS branch predictor 3 | * 4 | * 18-640 Foundations of Computer Architecture 5 | * Carnegie Mellon University 6 | * 7 | */ 8 | 9 | #include "base/bitfield.hh" 10 | #include "base/intmath.hh" 11 | #include "cpu/pred/yags.hh" 12 | 13 | 14 | /* 15 | * Constructor for YagsBP 16 | */ 17 | YagsBP::YagsBP(const Params *params) 18 | : BPredUnit(params), instShiftAmt(params->instShiftAmt), 19 | globalHistoryReg(0), 20 | globalHistoryBits(ceilLog2(params->globalPredictorSize)), 21 | choicePredictorSize(params->choicePredictorSize), 22 | choiceCtrBits(params->choiceCtrBits), 23 | globalPredictorSize(params->globalPredictorSize), 24 | globalCtrBits(params->globalCtrBits) 25 | { 26 | if (!isPowerOf2(choicePredictorSize)) 27 | fatal("Invalid choice predictor size.\n"); 28 | if (!isPowerOf2(globalPredictorSize)) 29 | fatal("Invalid global history predictor size.\n"); 30 | choiceCounters.resize(choicePredictorSize); 31 | takenCounters.resize(globalPredictorSize); 32 | notTakenCounters.resize(globalPredictorSize); 33 | takenTags.resize(globalPredictorSize); 34 | notTakenTags.resize(globalPredictorSize); 35 | for (int i = 0; i < choicePredictorSize; ++i) { 36 | choiceCounters[i].setBits(choiceCtrBits); 37 | } 38 | for (int i = 0; i < globalPredictorSize; ++i) { 39 | takenCounters[i].setBits(globalCtrBits); 40 | notTakenCounters[i].setBits(globalCtrBits); 41 | //takenTags[i]=0; 42 | //notTakenTags[i]=0; 43 | } 44 | historyRegisterMask = mask(globalHistoryBits); 45 | choiceHistoryMask = choicePredictorSize - 1; 46 | globalHistoryMask = globalPredictorSize - 1; 47 | 48 | choiceThreshold = (ULL(1) << (choiceCtrBits - 1)) - 1; 49 | takenThreshold = (ULL(1) << (choiceCtrBits - 1)) - 1; 50 | notTakenThreshold = (ULL(1) << (choiceCtrBits - 1)) - 1; 51 | } 52 | 53 | /* 54 | * Actions for an unconditional branch 55 | */ 56 | void 57 | YagsBP::uncondBranch(void * &bpHistory) 58 | { 59 | BPHistory *history = new BPHistory; 60 | history->globalHistoryReg = globalHistoryReg; 61 | history->takenUsed = true; 62 | history->takenPred = true; 63 | history->notTakenPred = true; 64 | history->finalPred = true; 65 | history->cacheUsed = false; 66 | bpHistory = static_cast(history); 67 | updateGlobalHistReg(true); 68 | } 69 | 70 | /* 71 | * Actions for squash 72 | */ 73 | void 74 | YagsBP::squash(void *bpHistory) 75 | { 76 | BPHistory *history = static_cast(bpHistory); 77 | globalHistoryReg = history->globalHistoryReg; 78 | 79 | delete history; 80 | } 81 | 82 | /* 83 | * Lookup the actual branch prediction. 84 | */ 85 | bool 86 | YagsBP::lookup(Addr branchAddr, void * &bpHistory) 87 | { 88 | unsigned tagMask = (ULL(1) << 8) - 1; 89 | unsigned choiceHistoryIdx = ((branchAddr >> instShiftAmt) 90 | & choiceHistoryMask); 91 | unsigned globalHistoryIdx = (((branchAddr >> instShiftAmt) 92 | ^ globalHistoryReg) 93 | & globalHistoryMask); 94 | 95 | unsigned leastSigAddr = branchAddr & tagMask; 96 | unsigned tagsIdx = globalHistoryIdx; 97 | assert(choiceHistoryIdx < choicePredictorSize); 98 | assert(globalHistoryIdx < globalPredictorSize); 99 | 100 | bool choicePrediction = choiceCounters[choiceHistoryIdx].read() 101 | > choiceThreshold; 102 | bool takenGHBPrediction = takenCounters[globalHistoryIdx].read() 103 | > takenThreshold; 104 | bool notTakenGHBPrediction = notTakenCounters[globalHistoryIdx].read() 105 | > notTakenThreshold; 106 | 107 | 108 | bool cacheUsed = false; 109 | bool finalPrediction; 110 | BPHistory *history = new BPHistory; 111 | 112 | history->globalHistoryReg = globalHistoryReg; 113 | history->takenUsed = choicePrediction; 114 | 115 | history->takenPred = takenGHBPrediction; 116 | history->notTakenPred = notTakenGHBPrediction; 117 | 118 | 119 | if (choicePrediction) { 120 | //fatal("Invalid choice predictor size.\n"); 121 | if(notTakenTags[tagsIdx]!=leastSigAddr){ 122 | 123 | 124 | finalPrediction = choicePrediction; 125 | 126 | }else { 127 | 128 | finalPrediction = notTakenGHBPrediction; 129 | cacheUsed = true; 130 | 131 | } 132 | } 133 | else { 134 | if(takenTags[tagsIdx] !=leastSigAddr){ 135 | //takenTags[tagsIdx] = leastSigAddr; 136 | finalPrediction = choicePrediction; 137 | 138 | }else { 139 | //if(takenTags[tagsIdx] == leastSigAddr) 140 | finalPrediction = takenGHBPrediction; 141 | cacheUsed = true; 142 | //else 143 | // finalPrediction = choicePrediction; 144 | } 145 | } 146 | history->finalPred = finalPrediction; 147 | history->cacheUsed = cacheUsed; 148 | bpHistory = static_cast(history); 149 | updateGlobalHistReg(finalPrediction); 150 | 151 | return finalPrediction; 152 | } 153 | 154 | /* 155 | * BTB Update actions 156 | */ 157 | void 158 | YagsBP::btbUpdate(Addr branchAddr, void * &bpHistory) 159 | { 160 | globalHistoryReg &= (historyRegisterMask & ~ULL(1)); 161 | } 162 | 163 | /* 164 | * Update data structures after getting actual decison 165 | */ 166 | void 167 | YagsBP::update(Addr branchAddr, bool taken, void *bpHistory, bool squashed) 168 | { 169 | 170 | if (bpHistory) { 171 | unsigned tagMask = (ULL(1) << 8) - 1; 172 | BPHistory *history = static_cast(bpHistory); 173 | unsigned choiceHistoryIdx = ((branchAddr >> instShiftAmt) 174 | & choiceHistoryMask); 175 | unsigned globalHistoryIdx = (((branchAddr >> instShiftAmt) 176 | ^ history->globalHistoryReg) 177 | & globalHistoryMask); 178 | 179 | unsigned leastSigAddr = branchAddr & tagMask; 180 | 181 | assert(choiceHistoryIdx < choicePredictorSize); 182 | assert(globalHistoryIdx < globalPredictorSize); 183 | 184 | if(history->cacheUsed){ 185 | if (history->takenUsed) { 186 | if (taken) { 187 | notTakenCounters[globalHistoryIdx].increment(); 188 | } else { 189 | notTakenCounters[globalHistoryIdx].decrement(); 190 | } 191 | } else { 192 | if (taken) { 193 | takenCounters[globalHistoryIdx].increment(); 194 | } else { 195 | takenCounters[globalHistoryIdx].decrement(); 196 | } 197 | } 198 | } 199 | else{ 200 | if(history->finalPred!=taken){ 201 | if(taken){ 202 | takenTags[globalHistoryIdx]=leastSigAddr; 203 | } 204 | else{ 205 | notTakenTags[globalHistoryIdx]=leastSigAddr; 206 | } 207 | } 208 | } 209 | 210 | 211 | 212 | if(history->cacheUsed){ 213 | if (history->finalPred == taken) { 214 | 215 | if (taken == history->takenUsed) { 216 | if (taken) { 217 | choiceCounters[choiceHistoryIdx].increment(); 218 | } else { 219 | choiceCounters[choiceHistoryIdx].decrement(); 220 | } 221 | } 222 | } else { 223 | 224 | if (taken) { 225 | choiceCounters[choiceHistoryIdx].increment(); 226 | 227 | 228 | } else { 229 | choiceCounters[choiceHistoryIdx].decrement(); 230 | 231 | } 232 | } 233 | }else{ 234 | 235 | if(taken){ 236 | choiceCounters[choiceHistoryIdx].increment(); 237 | }else { 238 | choiceCounters[choiceHistoryIdx].decrement(); 239 | } 240 | 241 | } 242 | if (squashed) { 243 | if (taken) { 244 | globalHistoryReg = (history->globalHistoryReg << 1) | 1; 245 | } else { 246 | globalHistoryReg = (history->globalHistoryReg << 1); 247 | } 248 | globalHistoryReg &= historyRegisterMask; 249 | } else { 250 | delete history; 251 | } 252 | } 253 | 254 | } 255 | 256 | /* 257 | * Retire Squashed Instruction 258 | */ 259 | void 260 | YagsBP::retireSquashed(void *bp_history) 261 | { 262 | BPHistory *history = static_cast(bp_history); 263 | delete history; 264 | } 265 | 266 | /* 267 | * Global History Registor Update 268 | */ 269 | void 270 | YagsBP::updateGlobalHistReg(bool taken) 271 | { 272 | globalHistoryReg = taken ? (globalHistoryReg << 1) | 1 : 273 | (globalHistoryReg << 1); 274 | globalHistoryReg &= historyRegisterMask; 275 | } 276 | -------------------------------------------------------------------------------- /Project/project1/source/yags.hh: -------------------------------------------------------------------------------- 1 | /* @file 2 | * Header file for YAGS branch predictor 3 | * 4 | * 18-640 Foundations of Computer Architecture 5 | * Carnegie Mellon University 6 | * 7 | */ 8 | 9 | #ifndef __CPU_PRED_YAGS_PRED_HH__ 10 | #define __CPU_PRED_YAGS_PRED_HH__ 11 | 12 | #include "cpu/pred/bpred_unit.hh" 13 | #include "cpu/pred/sat_counter.hh" 14 | 15 | /* 16 | * Feel free to make any modifications, this is a skeleton code 17 | * to get you started. 18 | * Note: Do not change name of class 19 | */ 20 | class YagsBP : public BPredUnit 21 | { 22 | public: 23 | YagsBP(const Params *params); 24 | void uncondBranch(void * &bp_history); 25 | void squash(void *bp_history); 26 | bool lookup(Addr branch_addr, void * &bp_history); 27 | void btbUpdate(Addr branch_addr, void * &bp_history); 28 | void update(Addr branch_addr, bool taken, void *bp_history, bool squashed); 29 | void retireSquashed(void *bp_history); 30 | 31 | private: 32 | void updateGlobalHistReg(bool taken); 33 | 34 | struct BPHistory { 35 | unsigned globalHistoryReg; 36 | // was the taken array's prediction used? 37 | // true: takenPred used 38 | // false: notPred used 39 | bool takenUsed; 40 | // prediction of the taken array 41 | // true: predict taken 42 | // false: predict not-taken 43 | bool takenPred; 44 | // prediction of the not-taken array 45 | // true: predict taken 46 | // false: predict not-taken 47 | bool notTakenPred; 48 | // the final taken/not-taken prediction 49 | // true: predict taken 50 | // false: predict not-taken 51 | bool finalPred; 52 | 53 | bool cacheUsed; 54 | }; 55 | 56 | // choice predictors 57 | std::vector choiceCounters; 58 | // taken direction predictors 59 | std::vector takenCounters; 60 | // not-taken direction predictors 61 | std::vector notTakenCounters; 62 | 63 | std::vector takenTags; 64 | 65 | std::vector notTakenTags; 66 | unsigned instShiftAmt; 67 | 68 | unsigned globalHistoryReg; 69 | unsigned globalHistoryBits; 70 | unsigned historyRegisterMask; 71 | 72 | unsigned choicePredictorSize; 73 | unsigned choiceCtrBits; 74 | unsigned choiceHistoryMask; 75 | unsigned globalPredictorSize; 76 | unsigned globalCtrBits; 77 | unsigned globalHistoryMask; 78 | 79 | unsigned choiceThreshold; 80 | unsigned takenThreshold; 81 | unsigned notTakenThreshold; 82 | }; 83 | 84 | #endif // __CPU_PRED_YAGS_PRED_HH__ 85 | -------------------------------------------------------------------------------- /Project/project2/18640_Project_2_F2015(1).pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project2/18640_Project_2_F2015(1).pdf -------------------------------------------------------------------------------- /Project/project2/handin/o3/FUPool.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2006-2007 The Regents of The University of Michigan 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are 6 | # met: redistributions of source code must retain the above copyright 7 | # notice, this list of conditions and the following disclaimer; 8 | # redistributions in binary form must reproduce the above copyright 9 | # notice, this list of conditions and the following disclaimer in the 10 | # documentation and/or other materials provided with the distribution; 11 | # neither the name of the copyright holders nor the names of its 12 | # contributors may be used to endorse or promote products derived from 13 | # this software without specific prior written permission. 14 | # 15 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | # 27 | # Authors: Kevin Lim 28 | 29 | from m5.SimObject import SimObject 30 | from m5.params import * 31 | from FuncUnit import * 32 | from FuncUnitConfig import * 33 | 34 | class FUPool(SimObject): 35 | type = 'FUPool' 36 | cxx_header = "cpu/o3/fu_pool.hh" 37 | FUList = VectorParam.FUDesc("list of FU's for this pool") 38 | 39 | class DefaultFUPool(FUPool): 40 | FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), 41 | SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ] 42 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/FuncUnitConfig.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2010 ARM Limited 2 | # All rights reserved. 3 | # 4 | # The license below extends only to copyright in the software and shall 5 | # not be construed as granting a license to any other intellectual 6 | # property including but not limited to intellectual property relating 7 | # to a hardware implementation of the functionality of the software 8 | # licensed hereunder. You may use the software subject to the license 9 | # terms below provided that you ensure that this notice is replicated 10 | # unmodified and in its entirety in all distributions of the software, 11 | # modified or unmodified, in source code or in binary form. 12 | # 13 | # Copyright (c) 2006-2007 The Regents of The University of Michigan 14 | # All rights reserved. 15 | # 16 | # Redistribution and use in source and binary forms, with or without 17 | # modification, are permitted provided that the following conditions are 18 | # met: redistributions of source code must retain the above copyright 19 | # notice, this list of conditions and the following disclaimer; 20 | # redistributions in binary form must reproduce the above copyright 21 | # notice, this list of conditions and the following disclaimer in the 22 | # documentation and/or other materials provided with the distribution; 23 | # neither the name of the copyright holders nor the names of its 24 | # contributors may be used to endorse or promote products derived from 25 | # this software without specific prior written permission. 26 | # 27 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 | # 39 | # Authors: Kevin Lim 40 | 41 | from m5.SimObject import SimObject 42 | from m5.params import * 43 | from FuncUnit import * 44 | 45 | class IntALU(FUDesc): 46 | opList = [ OpDesc(opClass='IntAlu') ] 47 | count = 6 48 | 49 | class IntMultDiv(FUDesc): 50 | opList = [ OpDesc(opClass='IntMult', opLat=3), 51 | OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] 52 | count=2 53 | 54 | class FP_ALU(FUDesc): 55 | opList = [ OpDesc(opClass='FloatAdd', opLat=2), 56 | OpDesc(opClass='FloatCmp', opLat=2), 57 | OpDesc(opClass='FloatCvt', opLat=2) ] 58 | count = 4 59 | 60 | class FP_MultDiv(FUDesc): 61 | opList = [ OpDesc(opClass='FloatMult', opLat=4), 62 | OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), 63 | OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] 64 | count = 2 65 | 66 | class SIMD_Unit(FUDesc): 67 | opList = [ OpDesc(opClass='SimdAdd'), 68 | OpDesc(opClass='SimdAddAcc'), 69 | OpDesc(opClass='SimdAlu'), 70 | OpDesc(opClass='SimdCmp'), 71 | OpDesc(opClass='SimdCvt'), 72 | OpDesc(opClass='SimdMisc'), 73 | OpDesc(opClass='SimdMult'), 74 | OpDesc(opClass='SimdMultAcc'), 75 | OpDesc(opClass='SimdShift'), 76 | OpDesc(opClass='SimdShiftAcc'), 77 | OpDesc(opClass='SimdSqrt'), 78 | OpDesc(opClass='SimdFloatAdd'), 79 | OpDesc(opClass='SimdFloatAlu'), 80 | OpDesc(opClass='SimdFloatCmp'), 81 | OpDesc(opClass='SimdFloatCvt'), 82 | OpDesc(opClass='SimdFloatDiv'), 83 | OpDesc(opClass='SimdFloatMisc'), 84 | OpDesc(opClass='SimdFloatMult'), 85 | OpDesc(opClass='SimdFloatMultAcc'), 86 | OpDesc(opClass='SimdFloatSqrt') ] 87 | count = 4 88 | 89 | class ReadPort(FUDesc): 90 | opList = [ OpDesc(opClass='MemRead') ] 91 | count = 0 92 | 93 | class WritePort(FUDesc): 94 | opList = [ OpDesc(opClass='MemWrite') ] 95 | count = 0 96 | 97 | class RdWrPort(FUDesc): 98 | opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] 99 | count = 4 100 | 101 | class IprPort(FUDesc): 102 | opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] 103 | count = 1 104 | 105 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/O3CPU.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2005-2007 The Regents of The University of Michigan 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are 6 | # met: redistributions of source code must retain the above copyright 7 | # notice, this list of conditions and the following disclaimer; 8 | # redistributions in binary form must reproduce the above copyright 9 | # notice, this list of conditions and the following disclaimer in the 10 | # documentation and/or other materials provided with the distribution; 11 | # neither the name of the copyright holders nor the names of its 12 | # contributors may be used to endorse or promote products derived from 13 | # this software without specific prior written permission. 14 | # 15 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | # 27 | # Authors: Kevin Lim 28 | 29 | from m5.defines import buildEnv 30 | from m5.params import * 31 | from m5.proxy import * 32 | from BaseCPU import BaseCPU 33 | from FUPool import * 34 | from O3Checker import O3Checker 35 | from BranchPredictor import BranchPredictor 36 | 37 | class DerivO3CPU(BaseCPU): 38 | type = 'DerivO3CPU' 39 | cxx_header = 'cpu/o3/deriv.hh' 40 | 41 | @classmethod 42 | def memory_mode(cls): 43 | return 'timing' 44 | 45 | @classmethod 46 | def require_caches(cls): 47 | return True 48 | 49 | @classmethod 50 | def support_take_over(cls): 51 | return True 52 | 53 | activity = Param.Unsigned(0, "Initial count") 54 | 55 | cachePorts = Param.Unsigned(200, "Cache Ports") 56 | 57 | decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 58 | renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 59 | iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 60 | "delay") 61 | commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 62 | fetchWidth = Param.Unsigned(8, "Fetch width") 63 | fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 64 | 65 | renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 66 | iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 67 | "delay") 68 | commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 69 | fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 70 | decodeWidth = Param.Unsigned(8, "Decode width") 71 | 72 | iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 73 | "delay") 74 | commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 75 | decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 76 | renameWidth = Param.Unsigned(8, "Rename width") 77 | 78 | commitToIEWDelay = Param.Cycles(1, "Commit to " 79 | "Issue/Execute/Writeback delay") 80 | renameToIEWDelay = Param.Cycles(2, "Rename to " 81 | "Issue/Execute/Writeback delay") 82 | issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 83 | "to the IEW stage)") 84 | dispatchWidth = Param.Unsigned(8, "Dispatch width") 85 | issueWidth = Param.Unsigned(8, "Issue width") 86 | wbWidth = Param.Unsigned(8, "Writeback width") 87 | wbDepth = Param.Unsigned(1, "Writeback depth") 88 | fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 89 | 90 | iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 91 | "delay") 92 | renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 93 | commitWidth = Param.Unsigned(8, "Commit width") 94 | squashWidth = Param.Unsigned(8, "Squash width") 95 | trapLatency = Param.Cycles(13, "Trap latency") 96 | fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 97 | 98 | backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 99 | forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 100 | 101 | LQEntries = Param.Unsigned(32, "Number of load queue entries") 102 | SQEntries = Param.Unsigned(32, "Number of store queue entries") 103 | LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 104 | LSQCheckLoads = Param.Bool(True, 105 | "Should dependency violations be checked for loads & stores or just stores") 106 | store_set_clear_period = Param.Unsigned(250000, 107 | "Number of load/store insts before the dep predictor should be invalidated") 108 | LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 109 | SSITSize = Param.Unsigned(1024, "Store set ID table size") 110 | 111 | numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 112 | 113 | numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 114 | numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 115 | "registers") 116 | # most ISAs don't use condition-code regs, so default is 0 117 | _defaultNumPhysCCRegs = 0 118 | if buildEnv['TARGET_ISA'] == 'x86': 119 | # For x86, each CC reg is used to hold only a subset of the 120 | # flags, so we need 4-5 times the number of CC regs as 121 | # physical integer regs to be sure we don't run out. In 122 | # typical real machines, CC regs are not explicitly renamed 123 | # (it's a side effect of int reg renaming), so they should 124 | # never be the bottleneck here. 125 | _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 126 | numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 127 | "Number of physical cc registers") 128 | numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 129 | numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 130 | 131 | smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 132 | smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 133 | smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 134 | smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 135 | smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 136 | smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 137 | smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 138 | smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 139 | smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 140 | 141 | branchPred = Param.BranchPredictor(BranchPredictor(numThreads = 142 | Parent.numThreads), 143 | "Branch Predictor") 144 | needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 145 | "Enable TSO Memory model") 146 | 147 | def addCheckerCpu(self): 148 | if buildEnv['TARGET_ISA'] in ['arm']: 149 | from ArmTLB import ArmTLB 150 | 151 | self.checker = O3Checker(workload=self.workload, 152 | exitOnError=False, 153 | updateOnError=True, 154 | warnOnlyOnLoadError=True) 155 | self.checker.itb = ArmTLB(size = self.itb.size) 156 | self.checker.dtb = ArmTLB(size = self.dtb.size) 157 | self.checker.cpu_id = self.cpu_id 158 | 159 | else: 160 | print "ERROR: Checker only supported under ARM ISA!" 161 | exit(1) 162 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/O3Checker.py: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2007 The Regents of The University of Michigan 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are 6 | # met: redistributions of source code must retain the above copyright 7 | # notice, this list of conditions and the following disclaimer; 8 | # redistributions in binary form must reproduce the above copyright 9 | # notice, this list of conditions and the following disclaimer in the 10 | # documentation and/or other materials provided with the distribution; 11 | # neither the name of the copyright holders nor the names of its 12 | # contributors may be used to endorse or promote products derived from 13 | # this software without specific prior written permission. 14 | # 15 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | # 27 | # Authors: Nathan Binkert 28 | 29 | from m5.params import * 30 | from CheckerCPU import CheckerCPU 31 | 32 | class O3Checker(CheckerCPU): 33 | type = 'O3Checker' 34 | cxx_header = 'cpu/o3/checker.hh' 35 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/SConscript: -------------------------------------------------------------------------------- 1 | # -*- mode:python -*- 2 | 3 | # Copyright (c) 2006 The Regents of The University of Michigan 4 | # All rights reserved. 5 | # 6 | # Redistribution and use in source and binary forms, with or without 7 | # modification, are permitted provided that the following conditions are 8 | # met: redistributions of source code must retain the above copyright 9 | # notice, this list of conditions and the following disclaimer; 10 | # redistributions in binary form must reproduce the above copyright 11 | # notice, this list of conditions and the following disclaimer in the 12 | # documentation and/or other materials provided with the distribution; 13 | # neither the name of the copyright holders nor the names of its 14 | # contributors may be used to endorse or promote products derived from 15 | # this software without specific prior written permission. 16 | # 17 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | # 29 | # Authors: Nathan Binkert 30 | 31 | import sys 32 | 33 | Import('*') 34 | 35 | if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: 36 | DebugFlag('CommitRate') 37 | DebugFlag('IEW') 38 | DebugFlag('IQ') 39 | 40 | if 'O3CPU' in env['CPU_MODELS']: 41 | SimObject('FUPool.py') 42 | SimObject('FuncUnitConfig.py') 43 | SimObject('O3CPU.py') 44 | 45 | Source('base_dyn_inst.cc') 46 | Source('commit.cc') 47 | Source('cpu.cc') 48 | Source('deriv.cc') 49 | Source('decode.cc') 50 | Source('dyn_inst.cc') 51 | Source('fetch.cc') 52 | Source('free_list.cc') 53 | Source('fu_pool.cc') 54 | Source('iew.cc') 55 | Source('inst_queue.cc') 56 | Source('lsq.cc') 57 | Source('lsq_unit.cc') 58 | Source('mem_dep_unit.cc') 59 | Source('regfile.cc') 60 | Source('rename.cc') 61 | Source('rename_map.cc') 62 | Source('rob.cc') 63 | Source('scoreboard.cc') 64 | Source('store_set.cc') 65 | Source('thread_context.cc') 66 | 67 | DebugFlag('LSQ') 68 | DebugFlag('LSQUnit') 69 | DebugFlag('MemDepUnit') 70 | DebugFlag('O3CPU') 71 | DebugFlag('ROB') 72 | DebugFlag('Rename') 73 | DebugFlag('Scoreboard') 74 | DebugFlag('StoreSet') 75 | DebugFlag('Writeback') 76 | 77 | CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 78 | 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 79 | 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 80 | 81 | SimObject('O3Checker.py') 82 | Source('checker.cc') 83 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/SConsopts: -------------------------------------------------------------------------------- 1 | # -*- mode:python -*- 2 | 3 | # Copyright (c) 2006 The Regents of The University of Michigan 4 | # All rights reserved. 5 | # 6 | # Redistribution and use in source and binary forms, with or without 7 | # modification, are permitted provided that the following conditions are 8 | # met: redistributions of source code must retain the above copyright 9 | # notice, this list of conditions and the following disclaimer; 10 | # redistributions in binary form must reproduce the above copyright 11 | # notice, this list of conditions and the following disclaimer in the 12 | # documentation and/or other materials provided with the distribution; 13 | # neither the name of the copyright holders nor the names of its 14 | # contributors may be used to endorse or promote products derived from 15 | # this software without specific prior written permission. 16 | # 17 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | # 29 | # Authors: Nathan Binkert 30 | 31 | Import('*') 32 | 33 | CpuModel('O3CPU', 'o3_cpu_exec.cc', 34 | '#include "cpu/o3/isa_specific.hh"', 35 | { 'CPU_exec_context': 'O3DynInst' }, 36 | default=True) 37 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/base_dyn_inst.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2006 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/cpu.hh" 32 | #include "cpu/o3/isa_specific.hh" 33 | #include "cpu/base_dyn_inst_impl.hh" 34 | 35 | // Explicit instantiation 36 | template class BaseDynInst; 37 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/checker.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011 ARM Limited 3 | * All rights reserved 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2006 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Kevin Lim 41 | */ 42 | 43 | #include "cpu/checker/cpu_impl.hh" 44 | #include "cpu/o3/checker.hh" 45 | #include "params/O3Checker.hh" 46 | 47 | class MemObject; 48 | 49 | template 50 | class Checker; 51 | 52 | //////////////////////////////////////////////////////////////////////// 53 | // 54 | // CheckerCPU Simulation Object 55 | // 56 | O3Checker * 57 | O3CheckerParams::create() 58 | { 59 | O3Checker::Params *params = new O3Checker::Params(); 60 | params->name = name; 61 | params->numThreads = numThreads; 62 | params->max_insts_any_thread = 0; 63 | params->max_insts_all_threads = 0; 64 | params->max_loads_any_thread = 0; 65 | params->max_loads_all_threads = 0; 66 | params->exitOnError = exitOnError; 67 | params->updateOnError = updateOnError; 68 | params->warnOnlyOnLoadError = warnOnlyOnLoadError; 69 | params->clk_domain = clk_domain; 70 | params->tracer = tracer; 71 | // Hack to touch all parameters. Consider not deriving Checker 72 | // from BaseCPU..it's not really a CPU in the end. 73 | Counter temp; 74 | temp = max_insts_any_thread; 75 | temp = max_insts_all_threads; 76 | temp = max_loads_any_thread; 77 | temp = max_loads_all_threads; 78 | temp++; 79 | Tick temp2 = progress_interval; 80 | params->progress_interval = 0; 81 | temp2++; 82 | 83 | params->itb = itb; 84 | params->dtb = dtb; 85 | params->isa = isa; 86 | params->system = system; 87 | params->cpu_id = cpu_id; 88 | params->profile = profile; 89 | params->interrupts = NULL; 90 | params->workload = workload; 91 | 92 | O3Checker *cpu = new O3Checker(params); 93 | return cpu; 94 | } 95 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/checker.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011 ARM Limited 3 | * All rights reserved 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2006 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Kevin Lim 41 | */ 42 | 43 | #ifndef __CPU_O3_CHECKER_HH__ 44 | #define __CPU_O3_CHECKER_HH__ 45 | 46 | #include "cpu/checker/cpu.hh" 47 | #include "cpu/o3/dyn_inst.hh" 48 | #include "cpu/o3/impl.hh" 49 | 50 | /** 51 | * Specific non-templated derived class used for SimObject configuration. 52 | */ 53 | class O3Checker : public Checker 54 | { 55 | public: 56 | O3Checker(Params *p) 57 | : Checker(p) 58 | { } 59 | }; 60 | 61 | #endif // __CPU_O3_CHECKER_HH__ 62 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/comm.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011 ARM Limited 3 | * All rights reserved 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Kevin Lim 41 | */ 42 | 43 | #ifndef __CPU_O3_COMM_HH__ 44 | #define __CPU_O3_COMM_HH__ 45 | 46 | #include 47 | 48 | #include "arch/types.hh" 49 | #include "base/types.hh" 50 | #include "cpu/inst_seq.hh" 51 | #include "sim/faults.hh" 52 | 53 | // Typedef for physical register index type. Although the Impl would be the 54 | // most likely location for this, there are a few classes that need this 55 | // typedef yet are not templated on the Impl. For now it will be defined here. 56 | typedef short int PhysRegIndex; 57 | 58 | /** Struct that defines the information passed from fetch to decode. */ 59 | template 60 | struct DefaultFetchDefaultDecode { 61 | typedef typename Impl::DynInstPtr DynInstPtr; 62 | 63 | int size; 64 | 65 | DynInstPtr insts[Impl::MaxWidth]; 66 | Fault fetchFault; 67 | InstSeqNum fetchFaultSN; 68 | bool clearFetchFault; 69 | }; 70 | 71 | /** Struct that defines the information passed from decode to rename. */ 72 | template 73 | struct DefaultDecodeDefaultRename { 74 | typedef typename Impl::DynInstPtr DynInstPtr; 75 | 76 | int size; 77 | 78 | DynInstPtr insts[Impl::MaxWidth]; 79 | }; 80 | 81 | /** Struct that defines the information passed from rename to IEW. */ 82 | template 83 | struct DefaultRenameDefaultIEW { 84 | typedef typename Impl::DynInstPtr DynInstPtr; 85 | 86 | int size; 87 | 88 | DynInstPtr insts[Impl::MaxWidth]; 89 | }; 90 | 91 | /** Struct that defines the information passed from IEW to commit. */ 92 | template 93 | struct DefaultIEWDefaultCommit { 94 | typedef typename Impl::DynInstPtr DynInstPtr; 95 | 96 | int size; 97 | 98 | DynInstPtr insts[Impl::MaxWidth]; 99 | DynInstPtr mispredictInst[Impl::MaxThreads]; 100 | Addr mispredPC[Impl::MaxThreads]; 101 | InstSeqNum squashedSeqNum[Impl::MaxThreads]; 102 | TheISA::PCState pc[Impl::MaxThreads]; 103 | 104 | bool squash[Impl::MaxThreads]; 105 | bool branchMispredict[Impl::MaxThreads]; 106 | bool branchTaken[Impl::MaxThreads]; 107 | bool includeSquashInst[Impl::MaxThreads]; 108 | }; 109 | 110 | template 111 | struct IssueStruct { 112 | typedef typename Impl::DynInstPtr DynInstPtr; 113 | 114 | int size; 115 | 116 | DynInstPtr insts[Impl::MaxWidth]; 117 | }; 118 | 119 | /** Struct that defines all backwards communication. */ 120 | template 121 | struct TimeBufStruct { 122 | typedef typename Impl::DynInstPtr DynInstPtr; 123 | struct decodeComm { 124 | TheISA::PCState nextPC; 125 | DynInstPtr mispredictInst; 126 | DynInstPtr squashInst; 127 | InstSeqNum doneSeqNum; 128 | Addr mispredPC; 129 | uint64_t branchAddr; 130 | unsigned branchCount; 131 | bool squash; 132 | bool predIncorrect; 133 | bool branchMispredict; 134 | bool branchTaken; 135 | }; 136 | 137 | decodeComm decodeInfo[Impl::MaxThreads]; 138 | 139 | struct renameComm { 140 | }; 141 | 142 | renameComm renameInfo[Impl::MaxThreads]; 143 | 144 | struct iewComm { 145 | // Also eventually include skid buffer space. 146 | unsigned freeIQEntries; 147 | unsigned freeLSQEntries; 148 | 149 | unsigned iqCount; 150 | unsigned ldstqCount; 151 | 152 | unsigned dispatched; 153 | unsigned dispatchedToLSQ; 154 | bool usedIQ; 155 | bool usedLSQ; 156 | }; 157 | 158 | iewComm iewInfo[Impl::MaxThreads]; 159 | 160 | struct commitComm { 161 | ///////////////////////////////////////////////////////////////////// 162 | // This code has been re-structured for better packing of variables 163 | // instead of by stage which is the more logical way to arrange the 164 | // data. 165 | // F = Fetch 166 | // D = Decode 167 | // I = IEW 168 | // R = Rename 169 | // As such each member is annotated with who consumes it 170 | // e.g. bool variable name // *F,R for Fetch and Rename 171 | ///////////////////////////////////////////////////////////////////// 172 | 173 | /// The pc of the next instruction to execute. This is the next 174 | /// instruction for a branch mispredict, but the same instruction for 175 | /// order violation and the like 176 | TheISA::PCState pc; // *F 177 | 178 | /// Provide fetch the instruction that mispredicted, if this 179 | /// pointer is not-null a misprediction occured 180 | DynInstPtr mispredictInst; // *F 181 | 182 | /// Instruction that caused the a non-mispredict squash 183 | DynInstPtr squashInst; // *F 184 | 185 | /// Hack for now to send back an uncached access to the IEW stage. 186 | DynInstPtr uncachedLoad; // *I 187 | 188 | /// Communication specifically to the IQ to tell the IQ that it can 189 | /// schedule a non-speculative instruction. 190 | InstSeqNum nonSpecSeqNum; // *I 191 | 192 | /// Represents the instruction that has either been retired or 193 | /// squashed. Similar to having a single bus that broadcasts the 194 | /// retired or squashed sequence number. 195 | InstSeqNum doneSeqNum; // *F, I 196 | 197 | /// Tell Rename how many free entries it has in the ROB 198 | unsigned freeROBEntries; // *R 199 | 200 | bool squash; // *F, D, R, I 201 | bool robSquashing; // *F, D, R, I 202 | 203 | /// Rename should re-read number of free rob entries 204 | bool usedROB; // *R 205 | 206 | /// Notify Rename that the ROB is empty 207 | bool emptyROB; // *R 208 | 209 | /// Was the branch taken or not 210 | bool branchTaken; // *F 211 | /// If an interrupt is pending and fetch should stall 212 | bool interruptPending; // *F 213 | /// If the interrupt ended up being cleared before being handled 214 | bool clearInterrupt; // *F 215 | 216 | /// Hack for now to send back an uncached access to the IEW stage. 217 | bool uncached; // *I 218 | 219 | }; 220 | 221 | commitComm commitInfo[Impl::MaxThreads]; 222 | 223 | bool decodeBlock[Impl::MaxThreads]; 224 | bool decodeUnblock[Impl::MaxThreads]; 225 | bool renameBlock[Impl::MaxThreads]; 226 | bool renameUnblock[Impl::MaxThreads]; 227 | bool iewBlock[Impl::MaxThreads]; 228 | bool iewUnblock[Impl::MaxThreads]; 229 | bool commitBlock[Impl::MaxThreads]; 230 | bool commitUnblock[Impl::MaxThreads]; 231 | }; 232 | 233 | #endif //__CPU_O3_COMM_HH__ 234 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/commit.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/commit_impl.hh" 32 | #include "cpu/o3/isa_specific.hh" 33 | 34 | template class DefaultCommit; 35 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/cpu_policy.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions are 8 | * met: redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer; 10 | * redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution; 13 | * neither the name of the copyright holders nor the names of its 14 | * contributors may be used to endorse or promote products derived from 15 | * this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | * Authors: Kevin Lim 30 | */ 31 | 32 | #ifndef __CPU_O3_CPU_POLICY_HH__ 33 | #define __CPU_O3_CPU_POLICY_HH__ 34 | 35 | #include "cpu/o3/comm.hh" 36 | #include "cpu/o3/commit.hh" 37 | #include "cpu/o3/decode.hh" 38 | #include "cpu/o3/fetch.hh" 39 | #include "cpu/o3/free_list.hh" 40 | #include "cpu/o3/iew.hh" 41 | #include "cpu/o3/inst_queue.hh" 42 | #include "cpu/o3/lsq.hh" 43 | #include "cpu/o3/lsq_unit.hh" 44 | #include "cpu/o3/mem_dep_unit.hh" 45 | #include "cpu/o3/regfile.hh" 46 | #include "cpu/o3/rename.hh" 47 | #include "cpu/o3/rename_map.hh" 48 | #include "cpu/o3/rob.hh" 49 | #include "cpu/o3/store_set.hh" 50 | 51 | /** 52 | * Struct that defines the key classes to be used by the CPU. All 53 | * classes use the typedefs defined here to determine what are the 54 | * classes of the other stages and communication buffers. In order to 55 | * change a structure such as the IQ, simply change the typedef here 56 | * to use the desired class instead, and recompile. In order to 57 | * create a different CPU to be used simultaneously with this one, see 58 | * the alpha_impl.hh file for instructions. 59 | */ 60 | template 61 | struct SimpleCPUPolicy 62 | { 63 | /** Typedef for the freelist of registers. */ 64 | typedef UnifiedFreeList FreeList; 65 | /** Typedef for the rename map. */ 66 | typedef UnifiedRenameMap RenameMap; 67 | /** Typedef for the ROB. */ 68 | typedef ::ROB ROB; 69 | /** Typedef for the instruction queue/scheduler. */ 70 | typedef InstructionQueue IQ; 71 | /** Typedef for the memory dependence unit. */ 72 | typedef ::MemDepUnit MemDepUnit; 73 | /** Typedef for the LSQ. */ 74 | typedef ::LSQ LSQ; 75 | /** Typedef for the thread-specific LSQ units. */ 76 | typedef ::LSQUnit LSQUnit; 77 | 78 | /** Typedef for fetch. */ 79 | typedef DefaultFetch Fetch; 80 | /** Typedef for decode. */ 81 | typedef DefaultDecode Decode; 82 | /** Typedef for rename. */ 83 | typedef DefaultRename Rename; 84 | /** Typedef for Issue/Execute/Writeback. */ 85 | typedef DefaultIEW IEW; 86 | /** Typedef for commit. */ 87 | typedef DefaultCommit Commit; 88 | 89 | /** The struct for communication between fetch and decode. */ 90 | typedef DefaultFetchDefaultDecode FetchStruct; 91 | 92 | /** The struct for communication between decode and rename. */ 93 | typedef DefaultDecodeDefaultRename DecodeStruct; 94 | 95 | /** The struct for communication between rename and IEW. */ 96 | typedef DefaultRenameDefaultIEW RenameStruct; 97 | 98 | /** The struct for communication between IEW and commit. */ 99 | typedef DefaultIEWDefaultCommit IEWStruct; 100 | 101 | /** The struct for communication within the IEW stage. */ 102 | typedef ::IssueStruct IssueStruct; 103 | 104 | /** The struct for all backwards communication. */ 105 | typedef TimeBufStruct TimeStruct; 106 | 107 | }; 108 | 109 | #endif //__CPU_O3_CPU_POLICY_HH__ 110 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/decode.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/decode_impl.hh" 32 | #include "cpu/o3/isa_specific.hh" 33 | 34 | template class DefaultDecode; 35 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/deriv.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include 32 | 33 | #include "cpu/o3/deriv.hh" 34 | #include "params/DerivO3CPU.hh" 35 | 36 | DerivO3CPU * 37 | DerivO3CPUParams::create() 38 | { 39 | ThreadID actual_num_threads; 40 | if (FullSystem) { 41 | // Full-system only supports a single thread for the moment. 42 | actual_num_threads = 1; 43 | } else { 44 | if (workload.size() > numThreads) { 45 | fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU", 46 | workload.size(), numThreads); 47 | } else if (workload.size() == 0) { 48 | fatal("Must specify at least one workload!"); 49 | } 50 | 51 | // In non-full-system mode, we infer the number of threads from 52 | // the workload if it's not explicitly specified. 53 | actual_num_threads = 54 | (numThreads >= workload.size()) ? numThreads : workload.size(); 55 | } 56 | 57 | numThreads = actual_num_threads; 58 | 59 | // Default smtFetchPolicy to "RoundRobin", if necessary. 60 | std::string round_robin_policy = "RoundRobin"; 61 | std::string single_thread = "SingleThread"; 62 | 63 | if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0) 64 | smtFetchPolicy = round_robin_policy; 65 | else 66 | smtFetchPolicy = smtFetchPolicy; 67 | 68 | return new DerivO3CPU(this); 69 | } 70 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/deriv.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #ifndef __CPU_O3_DERIV_HH__ 32 | #define __CPU_O3_DERIV_HH__ 33 | 34 | #include "cpu/o3/cpu.hh" 35 | #include "cpu/o3/impl.hh" 36 | #include "params/DerivO3CPU.hh" 37 | 38 | class DerivO3CPU : public FullO3CPU 39 | { 40 | public: 41 | DerivO3CPU(DerivO3CPUParams *p) 42 | : FullO3CPU(p) 43 | { } 44 | }; 45 | 46 | #endif // __CPU_O3_DERIV_HH__ 47 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/dyn_inst.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Gabe Black 29 | */ 30 | 31 | #include "cpu/o3/dyn_inst_impl.hh" 32 | #include "cpu/o3/impl.hh" 33 | 34 | // Force instantiation of BaseO3DynInst for all the implementations that 35 | // are needed. 36 | template class BaseO3DynInst; 37 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/fetch.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/fetch_impl.hh" 32 | #include "cpu/o3/isa_specific.hh" 33 | 34 | template class DefaultFetch; 35 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/free_list.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions are 8 | * met: redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer; 10 | * redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution; 13 | * neither the name of the copyright holders nor the names of its 14 | * contributors may be used to endorse or promote products derived from 15 | * this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | * Authors: Kevin Lim 30 | */ 31 | 32 | #include "arch/registers.hh" 33 | #include "base/trace.hh" 34 | #include "config/the_isa.hh" 35 | #include "cpu/o3/free_list.hh" 36 | #include "debug/FreeList.hh" 37 | 38 | UnifiedFreeList::UnifiedFreeList(const std::string &_my_name, 39 | PhysRegFile *_regFile) 40 | : _name(_my_name), regFile(_regFile) 41 | { 42 | DPRINTF(FreeList, "Creating new free list object.\n"); 43 | 44 | // Have the register file initialize the free list since it knows 45 | // about its internal organization 46 | regFile->initFreeList(this); 47 | } 48 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/free_list.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions are 8 | * met: redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer; 10 | * redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution; 13 | * neither the name of the copyright holders nor the names of its 14 | * contributors may be used to endorse or promote products derived from 15 | * this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | * Authors: Kevin Lim 30 | */ 31 | 32 | #ifndef __CPU_O3_FREE_LIST_HH__ 33 | #define __CPU_O3_FREE_LIST_HH__ 34 | 35 | #include 36 | #include 37 | 38 | #include "base/misc.hh" 39 | #include "base/trace.hh" 40 | #include "cpu/o3/comm.hh" 41 | #include "cpu/o3/regfile.hh" 42 | #include "debug/FreeList.hh" 43 | 44 | /** 45 | * Free list for a single class of registers (e.g., integer 46 | * or floating point). Because the register class is implicitly 47 | * determined by the rename map instance being accessed, all 48 | * architectural register index parameters and values in this class 49 | * are relative (e.g., %fp2 is just index 2). 50 | */ 51 | class SimpleFreeList 52 | { 53 | private: 54 | 55 | /** The actual free list */ 56 | std::queue freeRegs; 57 | 58 | public: 59 | 60 | SimpleFreeList() {}; 61 | 62 | /** Add a physical register to the free list */ 63 | void addReg(PhysRegIndex reg) { freeRegs.push(reg); } 64 | 65 | /** Get the next available register from the free list */ 66 | PhysRegIndex getReg() 67 | { 68 | assert(!freeRegs.empty()); 69 | PhysRegIndex free_reg = freeRegs.front(); 70 | freeRegs.pop(); 71 | return free_reg; 72 | } 73 | 74 | /** Return the number of free registers on the list. */ 75 | unsigned numFreeRegs() const { return freeRegs.size(); } 76 | 77 | /** True iff there are free registers on the list. */ 78 | bool hasFreeRegs() const { return !freeRegs.empty(); } 79 | }; 80 | 81 | 82 | /** 83 | * FreeList class that simply holds the list of free integer and floating 84 | * point registers. Can request for a free register of either type, and 85 | * also send back free registers of either type. This is a very simple 86 | * class, but it should be sufficient for most implementations. Like all 87 | * other classes, it assumes that the indices for the floating point 88 | * registers starts after the integer registers end. Hence the variable 89 | * numPhysicalIntRegs is logically equivalent to the baseFP dependency. 90 | * Note that while this most likely should be called FreeList, the name 91 | * "FreeList" is used in a typedef within the CPU Policy, and therefore no 92 | * class can be named simply "FreeList". 93 | * @todo: Give a better name to the base FP dependency. 94 | */ 95 | class UnifiedFreeList 96 | { 97 | private: 98 | 99 | /** The object name, for DPRINTF. We have to declare this 100 | * explicitly because Scoreboard is not a SimObject. */ 101 | const std::string _name; 102 | 103 | /** The list of free integer registers. */ 104 | SimpleFreeList intList; 105 | 106 | /** The list of free floating point registers. */ 107 | SimpleFreeList floatList; 108 | 109 | /** The list of free condition-code registers. */ 110 | SimpleFreeList ccList; 111 | 112 | /** 113 | * The register file object is used only to distinguish integer 114 | * from floating-point physical register indices. 115 | */ 116 | PhysRegFile *regFile; 117 | 118 | /* 119 | * We give UnifiedRenameMap internal access so it can get at the 120 | * internal per-class free lists and associate those with its 121 | * per-class rename maps. See UnifiedRenameMap::init(). 122 | */ 123 | friend class UnifiedRenameMap; 124 | 125 | public: 126 | /** Constructs a free list. 127 | * @param _numPhysicalIntRegs Number of physical integer registers. 128 | * @param reservedIntRegs Number of integer registers already 129 | * used by initial mappings. 130 | * @param _numPhysicalFloatRegs Number of physical fp registers. 131 | * @param reservedFloatRegs Number of fp registers already 132 | * used by initial mappings. 133 | */ 134 | UnifiedFreeList(const std::string &_my_name, PhysRegFile *_regFile); 135 | 136 | /** Gives the name of the freelist. */ 137 | std::string name() const { return _name; }; 138 | 139 | /** Returns a pointer to the condition-code free list */ 140 | SimpleFreeList *getCCList() { return &ccList; } 141 | 142 | /** Gets a free integer register. */ 143 | PhysRegIndex getIntReg() { return intList.getReg(); } 144 | 145 | /** Gets a free fp register. */ 146 | PhysRegIndex getFloatReg() { return floatList.getReg(); } 147 | 148 | /** Gets a free cc register. */ 149 | PhysRegIndex getCCReg() { return ccList.getReg(); } 150 | 151 | /** Adds a register back to the free list. */ 152 | void addReg(PhysRegIndex freed_reg); 153 | 154 | /** Adds an integer register back to the free list. */ 155 | void addIntReg(PhysRegIndex freed_reg) { intList.addReg(freed_reg); } 156 | 157 | /** Adds a fp register back to the free list. */ 158 | void addFloatReg(PhysRegIndex freed_reg) { floatList.addReg(freed_reg); } 159 | 160 | /** Adds a cc register back to the free list. */ 161 | void addCCReg(PhysRegIndex freed_reg) { ccList.addReg(freed_reg); } 162 | 163 | /** Checks if there are any free integer registers. */ 164 | bool hasFreeIntRegs() const { return intList.hasFreeRegs(); } 165 | 166 | /** Checks if there are any free fp registers. */ 167 | bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); } 168 | 169 | /** Checks if there are any free cc registers. */ 170 | bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); } 171 | 172 | /** Returns the number of free integer registers. */ 173 | unsigned numFreeIntRegs() const { return intList.numFreeRegs(); } 174 | 175 | /** Returns the number of free fp registers. */ 176 | unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); } 177 | 178 | /** Returns the number of free cc registers. */ 179 | unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); } 180 | }; 181 | 182 | inline void 183 | UnifiedFreeList::addReg(PhysRegIndex freed_reg) 184 | { 185 | DPRINTF(FreeList,"Freeing register %i.\n", freed_reg); 186 | //Might want to add in a check for whether or not this register is 187 | //already in there. A bit vector or something similar would be useful. 188 | if (regFile->isIntPhysReg(freed_reg)) { 189 | intList.addReg(freed_reg); 190 | } else if (regFile->isFloatPhysReg(freed_reg)) { 191 | floatList.addReg(freed_reg); 192 | } else { 193 | assert(regFile->isCCPhysReg(freed_reg)); 194 | ccList.addReg(freed_reg); 195 | } 196 | 197 | // These assert conditions ensure that the number of free 198 | // registers are not more than the # of total Physical Registers. 199 | // If this were false, it would mean that registers 200 | // have been freed twice, overflowing the free register 201 | // pool and potentially crashing SMT workloads. 202 | // ---- 203 | // Comment out for now so as to not potentially break 204 | // CMP and single-threaded workloads 205 | // ---- 206 | // assert(freeIntRegs.size() <= numPhysicalIntRegs); 207 | // assert(freeFloatRegs.size() <= numPhysicalFloatRegs); 208 | } 209 | 210 | 211 | #endif // __CPU_O3_FREE_LIST_HH__ 212 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/fu_pool.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013 ARM Limited 3 | * All rights reserved 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2006 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Kevin Lim 41 | */ 42 | 43 | #include 44 | 45 | #include "cpu/o3/fu_pool.hh" 46 | #include "cpu/func_unit.hh" 47 | 48 | using namespace std; 49 | 50 | //////////////////////////////////////////////////////////////////////////// 51 | // 52 | // A pool of function units 53 | // 54 | 55 | inline void 56 | FUPool::FUIdxQueue::addFU(int fu_idx) 57 | { 58 | funcUnitsIdx.push_back(fu_idx); 59 | ++size; 60 | } 61 | 62 | inline int 63 | FUPool::FUIdxQueue::getFU() 64 | { 65 | int retval = funcUnitsIdx[idx++]; 66 | 67 | if (idx == size) 68 | idx = 0; 69 | 70 | return retval; 71 | } 72 | 73 | FUPool::~FUPool() 74 | { 75 | fuListIterator i = funcUnits.begin(); 76 | fuListIterator end = funcUnits.end(); 77 | for (; i != end; ++i) 78 | delete *i; 79 | } 80 | 81 | 82 | // Constructor 83 | FUPool::FUPool(const Params *p) 84 | : SimObject(p) 85 | { 86 | numFU = 0; 87 | 88 | funcUnits.clear(); 89 | 90 | for (int i = 0; i < Num_OpClasses; ++i) { 91 | maxOpLatencies[i] = Cycles(0); 92 | maxIssueLatencies[i] = Cycles(0); 93 | } 94 | 95 | // 96 | // Iterate through the list of FUDescData structures 97 | // 98 | const vector ¶mList = p->FUList; 99 | for (FUDDiterator i = paramList.begin(); i != paramList.end(); ++i) { 100 | 101 | // 102 | // Don't bother with this if we're not going to create any FU's 103 | // 104 | if ((*i)->number) { 105 | // 106 | // Create the FuncUnit object from this structure 107 | // - add the capabilities listed in the FU's operation 108 | // description 109 | // 110 | // We create the first unit, then duplicate it as needed 111 | // 112 | FuncUnit *fu = new FuncUnit; 113 | 114 | OPDDiterator j = (*i)->opDescList.begin(); 115 | OPDDiterator end = (*i)->opDescList.end(); 116 | for (; j != end; ++j) { 117 | // indicate that this pool has this capability 118 | capabilityList.set((*j)->opClass); 119 | 120 | // Add each of the FU's that will have this capability to the 121 | // appropriate queue. 122 | for (int k = 0; k < (*i)->number; ++k) 123 | fuPerCapList[(*j)->opClass].addFU(numFU + k); 124 | 125 | // indicate that this FU has the capability 126 | fu->addCapability((*j)->opClass, (*j)->opLat, (*j)->issueLat); 127 | 128 | if ((*j)->opLat > maxOpLatencies[(*j)->opClass]) 129 | maxOpLatencies[(*j)->opClass] = (*j)->opLat; 130 | 131 | if ((*j)->issueLat > maxIssueLatencies[(*j)->opClass]) 132 | maxIssueLatencies[(*j)->opClass] = (*j)->issueLat; 133 | } 134 | 135 | numFU++; 136 | 137 | // Add the appropriate number of copies of this FU to the list 138 | fu->name = (*i)->name() + "(0)"; 139 | funcUnits.push_back(fu); 140 | 141 | for (int c = 1; c < (*i)->number; ++c) { 142 | ostringstream s; 143 | numFU++; 144 | FuncUnit *fu2 = new FuncUnit(*fu); 145 | 146 | s << (*i)->name() << "(" << c << ")"; 147 | fu2->name = s.str(); 148 | funcUnits.push_back(fu2); 149 | } 150 | } 151 | } 152 | 153 | unitBusy.resize(numFU); 154 | 155 | for (int i = 0; i < numFU; i++) { 156 | unitBusy[i] = false; 157 | } 158 | } 159 | 160 | void 161 | FUPool::annotateMemoryUnits(Cycles hit_latency) 162 | { 163 | maxOpLatencies[MemReadOp] = hit_latency; 164 | 165 | fuListIterator i = funcUnits.begin(); 166 | fuListIterator iend = funcUnits.end(); 167 | for (; i != iend; ++i) { 168 | if ((*i)->provides(MemReadOp)) 169 | (*i)->opLatency(MemReadOp) = hit_latency; 170 | 171 | if ((*i)->provides(MemWriteOp)) 172 | (*i)->opLatency(MemWriteOp) = hit_latency; 173 | } 174 | } 175 | 176 | int 177 | FUPool::getUnit(OpClass capability) 178 | { 179 | // If this pool doesn't have the specified capability, 180 | // return this information to the caller 181 | if (!capabilityList[capability]) 182 | return -2; 183 | 184 | int fu_idx = fuPerCapList[capability].getFU(); 185 | int start_idx = fu_idx; 186 | 187 | // Iterate through the circular queue if needed, stopping if we've reached 188 | // the first element again. 189 | while (unitBusy[fu_idx]) { 190 | fu_idx = fuPerCapList[capability].getFU(); 191 | if (fu_idx == start_idx) { 192 | // No FU available 193 | return -1; 194 | } 195 | } 196 | 197 | assert(fu_idx < numFU); 198 | 199 | unitBusy[fu_idx] = true; 200 | 201 | return fu_idx; 202 | } 203 | 204 | void 205 | FUPool::freeUnitNextCycle(int fu_idx) 206 | { 207 | assert(unitBusy[fu_idx]); 208 | unitsToBeFreed.push_back(fu_idx); 209 | } 210 | 211 | void 212 | FUPool::processFreeUnits() 213 | { 214 | while (!unitsToBeFreed.empty()) { 215 | int fu_idx = unitsToBeFreed.back(); 216 | unitsToBeFreed.pop_back(); 217 | 218 | assert(unitBusy[fu_idx]); 219 | 220 | unitBusy[fu_idx] = false; 221 | } 222 | } 223 | 224 | void 225 | FUPool::dump() 226 | { 227 | cout << "Function Unit Pool (" << name() << ")\n"; 228 | cout << "======================================\n"; 229 | cout << "Free List:\n"; 230 | 231 | for (int i = 0; i < numFU; ++i) { 232 | if (unitBusy[i]) { 233 | continue; 234 | } 235 | 236 | cout << " [" << i << "] : "; 237 | 238 | cout << funcUnits[i]->name << " "; 239 | 240 | cout << "\n"; 241 | } 242 | 243 | cout << "======================================\n"; 244 | cout << "Busy List:\n"; 245 | for (int i = 0; i < numFU; ++i) { 246 | if (!unitBusy[i]) { 247 | continue; 248 | } 249 | 250 | cout << " [" << i << "] : "; 251 | 252 | cout << funcUnits[i]->name << " "; 253 | 254 | cout << "\n"; 255 | } 256 | } 257 | 258 | bool 259 | FUPool::isDrained() const 260 | { 261 | bool is_drained = true; 262 | for (int i = 0; i < numFU; i++) 263 | is_drained = is_drained && !unitBusy[i]; 264 | 265 | return is_drained; 266 | } 267 | 268 | // 269 | 270 | //////////////////////////////////////////////////////////////////////////// 271 | // 272 | // The SimObjects we use to get the FU information into the simulator 273 | // 274 | //////////////////////////////////////////////////////////////////////////// 275 | 276 | // 277 | // FUPool - Contails a list of FUDesc objects to make available 278 | // 279 | 280 | // 281 | // The FuPool object 282 | // 283 | FUPool * 284 | FUPoolParams::create() 285 | { 286 | return new FUPool(this); 287 | } 288 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/fu_pool.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013 ARM Limited 3 | * All rights reserved 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2006 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Kevin Lim 41 | */ 42 | 43 | #ifndef __CPU_O3_FU_POOL_HH__ 44 | #define __CPU_O3_FU_POOL_HH__ 45 | 46 | #include 47 | #include 48 | #include 49 | #include 50 | 51 | #include "cpu/op_class.hh" 52 | #include "params/FUPool.hh" 53 | #include "sim/sim_object.hh" 54 | 55 | class FUDesc; 56 | class FuncUnit; 57 | 58 | /** 59 | * Pool of FU's, specific to the new CPU model. The old FU pool had lists of 60 | * free units and busy units, and whenever a FU was needed it would iterate 61 | * through the free units to find a FU that provided the capability. This pool 62 | * has lists of units specific to each of the capabilities, and whenever a FU 63 | * is needed, it iterates through that list to find a free unit. The previous 64 | * FU pool would have to be ticked each cycle to update which units became 65 | * free. This FU pool lets the IEW stage handle freeing units, which frees 66 | * them as their scheduled execution events complete. This limits units in this 67 | * model to either have identical issue and op latencies, or 1 cycle issue 68 | * latencies. 69 | */ 70 | class FUPool : public SimObject 71 | { 72 | private: 73 | /** Maximum op execution latencies, per op class. */ 74 | Cycles maxOpLatencies[Num_OpClasses]; 75 | /** Maximum issue latencies, per op class. */ 76 | Cycles maxIssueLatencies[Num_OpClasses]; 77 | 78 | /** Bitvector listing capabilities of this FU pool. */ 79 | std::bitset capabilityList; 80 | 81 | /** Bitvector listing which FUs are busy. */ 82 | std::vector unitBusy; 83 | 84 | /** List of units to be freed at the end of this cycle. */ 85 | std::vector unitsToBeFreed; 86 | 87 | /** 88 | * Class that implements a circular queue to hold FU indices. The hope is 89 | * that FUs that have been just used will be moved to the end of the queue 90 | * by iterating through it, thus leaving free units at the head of the 91 | * queue. 92 | */ 93 | class FUIdxQueue { 94 | public: 95 | /** Constructs a circular queue of FU indices. */ 96 | FUIdxQueue() 97 | : idx(0), size(0) 98 | { } 99 | 100 | /** Adds a FU to the queue. */ 101 | inline void addFU(int fu_idx); 102 | 103 | /** Returns the index of the FU at the head of the queue, and changes 104 | * the index to the next element. 105 | */ 106 | inline int getFU(); 107 | 108 | private: 109 | /** Circular queue index. */ 110 | int idx; 111 | 112 | /** Size of the queue. */ 113 | int size; 114 | 115 | /** Queue of FU indices. */ 116 | std::vector funcUnitsIdx; 117 | }; 118 | 119 | /** Per op class queues of FUs that provide that capability. */ 120 | FUIdxQueue fuPerCapList[Num_OpClasses]; 121 | 122 | /** Number of FUs. */ 123 | int numFU; 124 | 125 | /** Functional units. */ 126 | std::vector funcUnits; 127 | 128 | typedef std::vector::iterator fuListIterator; 129 | 130 | public: 131 | typedef FUPoolParams Params; 132 | /** Constructs a FU pool. */ 133 | FUPool(const Params *p); 134 | ~FUPool(); 135 | 136 | /** Annotates units that provide memory operations. Included only because 137 | * old FU pool provided this function. 138 | */ 139 | void annotateMemoryUnits(Cycles hit_latency); 140 | 141 | /** 142 | * Gets a FU providing the requested capability. Will mark the unit as busy, 143 | * but leaves the freeing of the unit up to the IEW stage. 144 | * @param capability The capability requested. 145 | * @return Returns -2 if the FU pool does not have the capability, -1 if 146 | * there is no free FU, and the FU's index otherwise. 147 | */ 148 | int getUnit(OpClass capability); 149 | 150 | /** Frees a FU at the end of this cycle. */ 151 | void freeUnitNextCycle(int fu_idx); 152 | 153 | /** Frees all FUs on the list. */ 154 | void processFreeUnits(); 155 | 156 | /** Returns the total number of FUs. */ 157 | int size() { return numFU; } 158 | 159 | /** Debugging function used to dump FU information. */ 160 | void dump(); 161 | 162 | /** Returns the operation execution latency of the given capability. */ 163 | Cycles getOpLatency(OpClass capability) { 164 | return maxOpLatencies[capability]; 165 | } 166 | 167 | /** Returns the issue latency of the given capability. */ 168 | Cycles getIssueLatency(OpClass capability) { 169 | return maxIssueLatencies[capability]; 170 | } 171 | 172 | /** Have all the FUs drained? */ 173 | bool isDrained() const; 174 | 175 | /** Takes over from another CPU's thread. */ 176 | void takeOverFrom() {}; 177 | }; 178 | 179 | #endif // __CPU_O3_FU_POOL_HH__ 180 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/iew.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/iew_impl.hh" 32 | #include "cpu/o3/inst_queue.hh" 33 | #include "cpu/o3/isa_specific.hh" 34 | 35 | template class DefaultIEW; 36 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/impl.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #ifndef __CPU_O3_IMPL_HH__ 32 | #define __CPU_O3_IMPL_HH__ 33 | 34 | #include "arch/isa_traits.hh" 35 | #include "config/the_isa.hh" 36 | #include "cpu/o3/cpu_policy.hh" 37 | 38 | // Forward declarations. 39 | template 40 | class BaseO3DynInst; 41 | 42 | template 43 | class FullO3CPU; 44 | 45 | /** Implementation specific struct that defines several key types to the 46 | * CPU, the stages within the CPU, the time buffers, and the DynInst. 47 | * The struct defines the ISA, the CPU policy, the specific DynInst, the 48 | * specific O3CPU, and all of the structs from the time buffers to do 49 | * communication. 50 | * This is one of the key things that must be defined for each hardware 51 | * specific CPU implementation. 52 | */ 53 | struct O3CPUImpl 54 | { 55 | /** The type of MachInst. */ 56 | typedef TheISA::MachInst MachInst; 57 | 58 | /** The CPU policy to be used, which defines all of the CPU stages. */ 59 | typedef SimpleCPUPolicy CPUPol; 60 | 61 | /** The DynInst type to be used. */ 62 | typedef BaseO3DynInst DynInst; 63 | 64 | /** The refcounted DynInst pointer to be used. In most cases this is 65 | * what should be used, and not DynInst *. 66 | */ 67 | typedef RefCountingPtr DynInstPtr; 68 | 69 | /** The O3CPU type to be used. */ 70 | typedef FullO3CPU O3CPU; 71 | 72 | /** Same typedef, but for CPUType. BaseDynInst may not always use 73 | * an O3 CPU, so it's clearer to call it CPUType instead in that 74 | * case. 75 | */ 76 | typedef O3CPU CPUType; 77 | 78 | enum { 79 | MaxWidth = 8, 80 | MaxThreads = 4 81 | }; 82 | }; 83 | 84 | #endif // __CPU_O3_SPARC_IMPL_HH__ 85 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/inst_queue.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/inst_queue_impl.hh" 32 | #include "cpu/o3/isa_specific.hh" 33 | 34 | // Force instantiation of InstructionQueue. 35 | template class InstructionQueue; 36 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/isa_specific.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2006 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Korey Sewell 29 | */ 30 | 31 | #include "cpu/o3/dyn_inst.hh" 32 | #include "cpu/o3/impl.hh" 33 | #include "cpu/base.hh" 34 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/lsq.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Korey Sewell 29 | */ 30 | 31 | #include "cpu/o3/isa_specific.hh" 32 | #include "cpu/o3/lsq_impl.hh" 33 | 34 | // Force the instantiation of LDSTQ for all the implementations we care about. 35 | template class LSQ; 36 | 37 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/lsq_unit.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | * Korey Sewell 30 | */ 31 | 32 | #include "cpu/o3/isa_specific.hh" 33 | #include "cpu/o3/lsq_unit_impl.hh" 34 | 35 | // Force the instantiation of LDSTQ for all the implementations we care about. 36 | template class LSQUnit; 37 | 38 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/mem_dep_unit.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/isa_specific.hh" 32 | #include "cpu/o3/mem_dep_unit_impl.hh" 33 | #include "cpu/o3/store_set.hh" 34 | 35 | #ifdef DEBUG 36 | template <> 37 | int 38 | MemDepUnit::MemDepEntry::memdep_count = 0; 39 | template <> 40 | int 41 | MemDepUnit::MemDepEntry::memdep_insert = 0; 42 | template <> 43 | int 44 | MemDepUnit::MemDepEntry::memdep_erase = 0; 45 | #endif 46 | 47 | // Force instantation of memory dependency unit using store sets and 48 | // O3CPUImpl. 49 | template class MemDepUnit; 50 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/regfile.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions are 8 | * met: redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer; 10 | * redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution; 13 | * neither the name of the copyright holders nor the names of its 14 | * contributors may be used to endorse or promote products derived from 15 | * this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | * Authors: Kevin Lim 30 | * Gabe Black 31 | * Steve Reinhardt 32 | */ 33 | 34 | #include "cpu/o3/free_list.hh" 35 | #include "cpu/o3/regfile.hh" 36 | 37 | 38 | PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs, 39 | unsigned _numPhysicalFloatRegs, 40 | unsigned _numPhysicalCCRegs) 41 | : intRegFile(_numPhysicalIntRegs), 42 | floatRegFile(_numPhysicalFloatRegs), 43 | ccRegFile(_numPhysicalCCRegs), 44 | baseFloatRegIndex(_numPhysicalIntRegs), 45 | baseCCRegIndex(_numPhysicalIntRegs + _numPhysicalFloatRegs), 46 | totalNumRegs(_numPhysicalIntRegs 47 | + _numPhysicalFloatRegs 48 | + _numPhysicalCCRegs) 49 | { 50 | if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) { 51 | // Just make this a warning and go ahead and allocate them 52 | // anyway, to keep from having to add checks everywhere 53 | warn("Non-zero number of physical CC regs specified, even though\n" 54 | " ISA does not use them.\n"); 55 | } 56 | } 57 | 58 | 59 | void 60 | PhysRegFile::initFreeList(UnifiedFreeList *freeList) 61 | { 62 | // Initialize the free lists. 63 | PhysRegIndex reg_idx = 0; 64 | 65 | // The initial batch of registers are the integer ones 66 | while (reg_idx < baseFloatRegIndex) { 67 | freeList->addIntReg(reg_idx++); 68 | } 69 | 70 | // The next batch of the registers are the floating-point physical 71 | // registers; put them onto the floating-point free list. 72 | while (reg_idx < baseCCRegIndex) { 73 | freeList->addFloatReg(reg_idx++); 74 | } 75 | 76 | // The rest of the registers are the condition-code physical 77 | // registers; put them onto the condition-code free list. 78 | while (reg_idx < totalNumRegs) { 79 | freeList->addCCReg(reg_idx++); 80 | } 81 | } 82 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/rename.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/isa_specific.hh" 32 | #include "cpu/o3/rename_impl.hh" 33 | 34 | template class DefaultRename; 35 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/rename_map.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions are 8 | * met: redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer; 10 | * redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution; 13 | * neither the name of the copyright holders nor the names of its 14 | * contributors may be used to endorse or promote products derived from 15 | * this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | * Authors: Kevin Lim 30 | */ 31 | 32 | #include 33 | 34 | #include "cpu/o3/rename_map.hh" 35 | #include "debug/Rename.hh" 36 | 37 | using namespace std; 38 | 39 | /**** SimpleRenameMap methods ****/ 40 | 41 | SimpleRenameMap::SimpleRenameMap() 42 | : freeList(NULL) 43 | { 44 | } 45 | 46 | 47 | void 48 | SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList, 49 | RegIndex _zeroReg) 50 | { 51 | assert(freeList == NULL); 52 | assert(map.empty()); 53 | 54 | map.resize(size); 55 | freeList = _freeList; 56 | zeroReg = _zeroReg; 57 | } 58 | 59 | SimpleRenameMap::RenameInfo 60 | SimpleRenameMap::rename(RegIndex arch_reg) 61 | { 62 | PhysRegIndex renamed_reg; 63 | 64 | // Record the current physical register that is renamed to the 65 | // requested architected register. 66 | PhysRegIndex prev_reg = map[arch_reg]; 67 | 68 | // If it's not referencing the zero register, then rename the 69 | // register. 70 | if (arch_reg != zeroReg) { 71 | renamed_reg = freeList->getReg(); 72 | 73 | map[arch_reg] = renamed_reg; 74 | } else { 75 | // Otherwise return the zero register so nothing bad happens. 76 | assert(prev_reg == zeroReg); 77 | renamed_reg = zeroReg; 78 | } 79 | 80 | DPRINTF(Rename, "Renamed reg %d to physical reg %d old mapping was %d\n", 81 | arch_reg, renamed_reg, prev_reg); 82 | 83 | return RenameInfo(renamed_reg, prev_reg); 84 | } 85 | 86 | 87 | /**** UnifiedRenameMap methods ****/ 88 | 89 | void 90 | UnifiedRenameMap::init(PhysRegFile *_regFile, 91 | RegIndex _intZeroReg, 92 | RegIndex _floatZeroReg, 93 | UnifiedFreeList *freeList) 94 | { 95 | regFile = _regFile; 96 | 97 | intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 98 | 99 | floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 100 | 101 | ccMap.init(TheISA::NumFloatRegs, &(freeList->ccList), (RegIndex)-1); 102 | } 103 | 104 | 105 | UnifiedRenameMap::RenameInfo 106 | UnifiedRenameMap::rename(RegIndex arch_reg) 107 | { 108 | RegIndex rel_arch_reg; 109 | 110 | switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 111 | case IntRegClass: 112 | return renameInt(rel_arch_reg); 113 | 114 | case FloatRegClass: 115 | return renameFloat(rel_arch_reg); 116 | 117 | case CCRegClass: 118 | return renameCC(rel_arch_reg); 119 | 120 | case MiscRegClass: 121 | return renameMisc(rel_arch_reg); 122 | 123 | default: 124 | panic("rename rename(): unknown reg class %s\n", 125 | RegClassStrings[regIdxToClass(arch_reg)]); 126 | } 127 | } 128 | 129 | 130 | PhysRegIndex 131 | UnifiedRenameMap::lookup(RegIndex arch_reg) const 132 | { 133 | RegIndex rel_arch_reg; 134 | 135 | switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 136 | case IntRegClass: 137 | return lookupInt(rel_arch_reg); 138 | 139 | case FloatRegClass: 140 | return lookupFloat(rel_arch_reg); 141 | 142 | case CCRegClass: 143 | return lookupCC(rel_arch_reg); 144 | 145 | case MiscRegClass: 146 | return lookupMisc(rel_arch_reg); 147 | 148 | default: 149 | panic("rename lookup(): unknown reg class %s\n", 150 | RegClassStrings[regIdxToClass(arch_reg)]); 151 | } 152 | } 153 | 154 | void 155 | UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg) 156 | { 157 | RegIndex rel_arch_reg; 158 | 159 | switch (regIdxToClass(arch_reg, &rel_arch_reg)) { 160 | case IntRegClass: 161 | return setIntEntry(rel_arch_reg, phys_reg); 162 | 163 | case FloatRegClass: 164 | return setFloatEntry(rel_arch_reg, phys_reg); 165 | 166 | case CCRegClass: 167 | return setCCEntry(rel_arch_reg, phys_reg); 168 | 169 | case MiscRegClass: 170 | // Misc registers do not actually rename, so don't change 171 | // their mappings. We end up here when a commit or squash 172 | // tries to update or undo a hardwired misc reg nmapping, 173 | // which should always be setting it to what it already is. 174 | assert(phys_reg == lookupMisc(rel_arch_reg)); 175 | return; 176 | 177 | default: 178 | panic("rename setEntry(): unknown reg class %s\n", 179 | RegClassStrings[regIdxToClass(arch_reg)]); 180 | } 181 | } 182 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/rob.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | * Nathan Binkert 30 | */ 31 | 32 | #include "cpu/o3/isa_specific.hh" 33 | #include "cpu/o3/rob_impl.hh" 34 | 35 | // Force instantiation of InstructionQueue. 36 | template class ROB; 37 | 38 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/scoreboard.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2005-2006 The Regents of The University of Michigan 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions are 8 | * met: redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer; 10 | * redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution; 13 | * neither the name of the copyright holders nor the names of its 14 | * contributors may be used to endorse or promote products derived from 15 | * this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | * Authors: Korey Sewell 30 | * Kevin Lim 31 | */ 32 | 33 | #include "config/the_isa.hh" 34 | #include "cpu/o3/scoreboard.hh" 35 | #include "debug/Scoreboard.hh" 36 | 37 | Scoreboard::Scoreboard(const std::string &_my_name, 38 | unsigned _numPhysicalRegs, unsigned _numMiscRegs, 39 | PhysRegIndex _zeroRegIdx, PhysRegIndex _fpZeroRegIdx) 40 | : _name(_my_name), 41 | regScoreBoard(_numPhysicalRegs, true), 42 | numPhysRegs(_numPhysicalRegs), 43 | numTotalRegs(_numPhysicalRegs + _numMiscRegs), 44 | zeroRegIdx(_zeroRegIdx), fpZeroRegIdx(_fpZeroRegIdx) 45 | { 46 | } 47 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/scoreboard.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2005-2006 The Regents of The University of Michigan 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions are 8 | * met: redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer; 10 | * redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution; 13 | * neither the name of the copyright holders nor the names of its 14 | * contributors may be used to endorse or promote products derived from 15 | * this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | * 29 | * Authors: Korey Sewell 30 | * Kevin Lim 31 | * Steve Reinhardt 32 | */ 33 | 34 | #ifndef __CPU_O3_SCOREBOARD_HH__ 35 | #define __CPU_O3_SCOREBOARD_HH__ 36 | 37 | #include 38 | #include 39 | #include 40 | 41 | #include "base/trace.hh" 42 | #include "config/the_isa.hh" 43 | #include "cpu/o3/comm.hh" 44 | #include "debug/Scoreboard.hh" 45 | 46 | /** 47 | * Implements a simple scoreboard to track which registers are 48 | * ready. This class operates on the unified physical register space, 49 | * so integer and floating-point registers are not distinguished. For 50 | * convenience, it also accepts operations on the physical-space 51 | * mapping of misc registers, which are numbered starting after the 52 | * end of the actual physical register file. However, there is no 53 | * actual scoreboard for misc registers, and they are always 54 | * considered ready. 55 | */ 56 | class Scoreboard 57 | { 58 | private: 59 | /** The object name, for DPRINTF. We have to declare this 60 | * explicitly because Scoreboard is not a SimObject. */ 61 | const std::string _name; 62 | 63 | /** Scoreboard of physical integer registers, saying whether or not they 64 | * are ready. */ 65 | std::vector regScoreBoard; 66 | 67 | /** The number of actual physical registers */ 68 | unsigned numPhysRegs; 69 | 70 | /** 71 | * The total number of registers which can be indexed, including 72 | * the misc registers that come after the physical registers and 73 | * which are hardwired to be always considered ready. 74 | */ 75 | unsigned numTotalRegs; 76 | 77 | /** The index of the zero register. */ 78 | PhysRegIndex zeroRegIdx; 79 | 80 | /** The index of the FP zero register. */ 81 | PhysRegIndex fpZeroRegIdx; 82 | 83 | bool isZeroReg(PhysRegIndex idx) const 84 | { 85 | return (idx == zeroRegIdx || 86 | (THE_ISA == ALPHA_ISA && idx == fpZeroRegIdx)); 87 | } 88 | 89 | public: 90 | /** Constructs a scoreboard. 91 | * @param _numPhysicalRegs Number of physical registers. 92 | * @param _numMiscRegs Number of miscellaneous registers. 93 | * @param _zeroRegIdx Index of the zero register. 94 | * @param _fpZeroRegIdx Index of the FP zero register (if any, currently 95 | * used only for Alpha). 96 | */ 97 | Scoreboard(const std::string &_my_name, 98 | unsigned _numPhysicalRegs, 99 | unsigned _numMiscRegs, 100 | PhysRegIndex _zeroRegIdx, 101 | PhysRegIndex _fpZeroRegIdx); 102 | 103 | /** Destructor. */ 104 | ~Scoreboard() {} 105 | 106 | /** Returns the name of the scoreboard. */ 107 | std::string name() const { return _name; }; 108 | 109 | /** Checks if the register is ready. */ 110 | bool getReg(PhysRegIndex reg_idx) const 111 | { 112 | assert(reg_idx < numTotalRegs); 113 | 114 | if (reg_idx >= numPhysRegs) { 115 | // misc regs are always ready 116 | return true; 117 | } 118 | 119 | bool ready = regScoreBoard[reg_idx]; 120 | 121 | if (isZeroReg(reg_idx)) 122 | assert(ready); 123 | 124 | return ready; 125 | } 126 | 127 | /** Sets the register as ready. */ 128 | void setReg(PhysRegIndex reg_idx) 129 | { 130 | assert(reg_idx < numTotalRegs); 131 | 132 | if (reg_idx >= numPhysRegs) { 133 | // misc regs are always ready, ignore attempts to change that 134 | return; 135 | } 136 | 137 | DPRINTF(Scoreboard, "Setting reg %i as ready\n", reg_idx); 138 | 139 | assert(reg_idx < numTotalRegs); 140 | regScoreBoard[reg_idx] = true; 141 | } 142 | 143 | /** Sets the register as not ready. */ 144 | void unsetReg(PhysRegIndex reg_idx) 145 | { 146 | assert(reg_idx < numTotalRegs); 147 | 148 | if (reg_idx >= numPhysRegs) { 149 | // misc regs are always ready, ignore attempts to change that 150 | return; 151 | } 152 | 153 | // zero reg should never be marked unready 154 | if (isZeroReg(reg_idx)) 155 | return; 156 | 157 | regScoreBoard[reg_idx] = false; 158 | } 159 | 160 | }; 161 | 162 | #endif 163 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/store_set.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #ifndef __CPU_O3_STORE_SET_HH__ 32 | #define __CPU_O3_STORE_SET_HH__ 33 | 34 | #include 35 | #include 36 | #include 37 | #include 38 | 39 | #include "base/types.hh" 40 | #include "cpu/inst_seq.hh" 41 | 42 | struct ltseqnum { 43 | bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 44 | { 45 | return lhs > rhs; 46 | } 47 | }; 48 | 49 | /** 50 | * Implements a store set predictor for determining if memory 51 | * instructions are dependent upon each other. See paper "Memory 52 | * Dependence Prediction using Store Sets" by Chrysos and Emer. SSID 53 | * stands for Store Set ID, SSIT stands for Store Set ID Table, and 54 | * LFST is Last Fetched Store Table. 55 | */ 56 | class StoreSet 57 | { 58 | public: 59 | typedef unsigned SSID; 60 | 61 | public: 62 | /** Default constructor. init() must be called prior to use. */ 63 | StoreSet() { }; 64 | 65 | /** Creates store set predictor with given table sizes. */ 66 | StoreSet(uint64_t clear_period, int SSIT_size, int LFST_size); 67 | 68 | /** Default destructor. */ 69 | ~StoreSet(); 70 | 71 | /** Initializes the store set predictor with the given table sizes. */ 72 | void init(uint64_t clear_period, int SSIT_size, int LFST_size); 73 | 74 | /** Records a memory ordering violation between the younger load 75 | * and the older store. */ 76 | void violation(Addr store_PC, Addr load_PC); 77 | 78 | /** Clears the store set predictor every so often so that all the 79 | * entries aren't used and stores are constantly predicted as 80 | * conflicting. 81 | */ 82 | void checkClear(); 83 | 84 | /** Inserts a load into the store set predictor. This does nothing but 85 | * is included in case other predictors require a similar function. 86 | */ 87 | void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 88 | 89 | /** Inserts a store into the store set predictor. Updates the 90 | * LFST if the store has a valid SSID. */ 91 | void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid); 92 | 93 | /** Checks if the instruction with the given PC is dependent upon 94 | * any store. @return Returns the sequence number of the store 95 | * instruction this PC is dependent upon. Returns 0 if none. 96 | */ 97 | InstSeqNum checkInst(Addr PC); 98 | 99 | /** Records this PC/sequence number as issued. */ 100 | void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 101 | 102 | /** Squashes for a specific thread until the given sequence number. */ 103 | void squash(InstSeqNum squashed_num, ThreadID tid); 104 | 105 | /** Resets all tables. */ 106 | void clear(); 107 | 108 | /** Debug function to dump the contents of the store list. */ 109 | void dump(); 110 | 111 | private: 112 | /** Calculates the index into the SSIT based on the PC. */ 113 | inline int calcIndex(Addr PC) 114 | { return (PC >> offsetBits) & indexMask; } 115 | 116 | /** Calculates a Store Set ID based on the PC. */ 117 | inline SSID calcSSID(Addr PC) 118 | { return ((PC ^ (PC >> 10)) % LFSTSize); } 119 | 120 | /** The Store Set ID Table. */ 121 | std::vector SSIT; 122 | 123 | /** Bit vector to tell if the SSIT has a valid entry. */ 124 | std::vector validSSIT; 125 | 126 | /** Last Fetched Store Table. */ 127 | std::vector LFST; 128 | 129 | /** Bit vector to tell if the LFST has a valid entry. */ 130 | std::vector validLFST; 131 | 132 | /** Map of stores that have been inserted into the store set, but 133 | * not yet issued or squashed. 134 | */ 135 | std::map storeList; 136 | 137 | typedef std::map::iterator SeqNumMapIt; 138 | 139 | /** Number of loads/stores to process before wiping predictor so all 140 | * entries don't get saturated 141 | */ 142 | uint64_t clearPeriod; 143 | 144 | /** Store Set ID Table size, in entries. */ 145 | int SSITSize; 146 | 147 | /** Last Fetched Store Table size, in entries. */ 148 | int LFSTSize; 149 | 150 | /** Mask to obtain the index. */ 151 | int indexMask; 152 | 153 | // HACK: Hardcoded for now. 154 | int offsetBits; 155 | 156 | /** Number of memory operations predicted since last clear of predictor */ 157 | int memOpsPred; 158 | }; 159 | 160 | #endif // __CPU_O3_STORE_SET_HH__ 161 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/thread_context.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * Authors: Kevin Lim 29 | */ 30 | 31 | #include "cpu/o3/impl.hh" 32 | #include "cpu/o3/thread_context.hh" 33 | #include "cpu/o3/thread_context_impl.hh" 34 | 35 | template class O3ThreadContext; 36 | 37 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/thread_context_impl.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2010-2012 ARM Limited 3 | * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 | * All rights reserved 5 | * 6 | * The license below extends only to copyright in the software and shall 7 | * not be construed as granting a license to any other intellectual 8 | * property including but not limited to intellectual property relating 9 | * to a hardware implementation of the functionality of the software 10 | * licensed hereunder. You may use the software subject to the license 11 | * terms below provided that you ensure that this notice is replicated 12 | * unmodified and in its entirety in all distributions of the software, 13 | * modified or unmodified, in source code or in binary form. 14 | * 15 | * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 | * All rights reserved. 17 | * 18 | * Redistribution and use in source and binary forms, with or without 19 | * modification, are permitted provided that the following conditions are 20 | * met: redistributions of source code must retain the above copyright 21 | * notice, this list of conditions and the following disclaimer; 22 | * redistributions in binary form must reproduce the above copyright 23 | * notice, this list of conditions and the following disclaimer in the 24 | * documentation and/or other materials provided with the distribution; 25 | * neither the name of the copyright holders nor the names of its 26 | * contributors may be used to endorse or promote products derived from 27 | * this software without specific prior written permission. 28 | * 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 | * 41 | * Authors: Kevin Lim 42 | * Korey Sewell 43 | */ 44 | 45 | #ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 46 | #define __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 47 | 48 | #include "arch/kernel_stats.hh" 49 | #include "arch/registers.hh" 50 | #include "config/the_isa.hh" 51 | #include "cpu/o3/thread_context.hh" 52 | #include "cpu/quiesce_event.hh" 53 | #include "debug/O3CPU.hh" 54 | 55 | template 56 | FSTranslatingPortProxy& 57 | O3ThreadContext::getVirtProxy() 58 | { 59 | return thread->getVirtProxy(); 60 | } 61 | 62 | template 63 | void 64 | O3ThreadContext::dumpFuncProfile() 65 | { 66 | thread->dumpFuncProfile(); 67 | } 68 | 69 | template 70 | void 71 | O3ThreadContext::takeOverFrom(ThreadContext *old_context) 72 | { 73 | ::takeOverFrom(*this, *old_context); 74 | TheISA::Decoder *newDecoder = getDecoderPtr(); 75 | TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 76 | newDecoder->takeOverFrom(oldDecoder); 77 | 78 | thread->kernelStats = old_context->getKernelStats(); 79 | thread->funcExeInst = old_context->readFuncExeInst(); 80 | 81 | thread->noSquashFromTC = false; 82 | thread->trapPending = false; 83 | } 84 | 85 | template 86 | void 87 | O3ThreadContext::activate(Cycles delay) 88 | { 89 | DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 90 | threadId()); 91 | 92 | if (thread->status() == ThreadContext::Active) 93 | return; 94 | 95 | thread->lastActivate = curTick(); 96 | thread->setStatus(ThreadContext::Active); 97 | 98 | // status() == Suspended 99 | cpu->activateContext(thread->threadId(), delay); 100 | } 101 | 102 | template 103 | void 104 | O3ThreadContext::suspend(Cycles delay) 105 | { 106 | DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 107 | threadId()); 108 | 109 | if (thread->status() == ThreadContext::Suspended) 110 | return; 111 | 112 | thread->lastActivate = curTick(); 113 | thread->lastSuspend = curTick(); 114 | 115 | thread->setStatus(ThreadContext::Suspended); 116 | cpu->suspendContext(thread->threadId()); 117 | } 118 | 119 | template 120 | void 121 | O3ThreadContext::halt(Cycles delay) 122 | { 123 | DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 124 | threadId()); 125 | 126 | if (thread->status() == ThreadContext::Halted) 127 | return; 128 | 129 | thread->setStatus(ThreadContext::Halted); 130 | cpu->haltContext(thread->threadId()); 131 | } 132 | 133 | template 134 | void 135 | O3ThreadContext::regStats(const std::string &name) 136 | { 137 | if (FullSystem) { 138 | thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 139 | thread->kernelStats->regStats(name + ".kern"); 140 | } 141 | } 142 | 143 | template 144 | Tick 145 | O3ThreadContext::readLastActivate() 146 | { 147 | return thread->lastActivate; 148 | } 149 | 150 | template 151 | Tick 152 | O3ThreadContext::readLastSuspend() 153 | { 154 | return thread->lastSuspend; 155 | } 156 | 157 | template 158 | void 159 | O3ThreadContext::profileClear() 160 | { 161 | thread->profileClear(); 162 | } 163 | 164 | template 165 | void 166 | O3ThreadContext::profileSample() 167 | { 168 | thread->profileSample(); 169 | } 170 | 171 | template 172 | void 173 | O3ThreadContext::copyArchRegs(ThreadContext *tc) 174 | { 175 | // Prevent squashing 176 | thread->noSquashFromTC = true; 177 | TheISA::copyRegs(tc, this); 178 | thread->noSquashFromTC = false; 179 | 180 | if (!FullSystem) 181 | this->thread->funcExeInst = tc->readFuncExeInst(); 182 | } 183 | 184 | template 185 | void 186 | O3ThreadContext::clearArchRegs() 187 | { 188 | cpu->isa[thread->threadId()]->clear(); 189 | } 190 | 191 | template 192 | uint64_t 193 | O3ThreadContext::readIntRegFlat(int reg_idx) 194 | { 195 | return cpu->readArchIntReg(reg_idx, thread->threadId()); 196 | } 197 | 198 | template 199 | TheISA::FloatReg 200 | O3ThreadContext::readFloatRegFlat(int reg_idx) 201 | { 202 | return cpu->readArchFloatReg(reg_idx, thread->threadId()); 203 | } 204 | 205 | template 206 | TheISA::FloatRegBits 207 | O3ThreadContext::readFloatRegBitsFlat(int reg_idx) 208 | { 209 | return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 210 | } 211 | 212 | template 213 | TheISA::CCReg 214 | O3ThreadContext::readCCRegFlat(int reg_idx) 215 | { 216 | return cpu->readArchCCReg(reg_idx, thread->threadId()); 217 | } 218 | 219 | template 220 | void 221 | O3ThreadContext::setIntRegFlat(int reg_idx, uint64_t val) 222 | { 223 | cpu->setArchIntReg(reg_idx, val, thread->threadId()); 224 | 225 | conditionalSquash(); 226 | } 227 | 228 | template 229 | void 230 | O3ThreadContext::setFloatRegFlat(int reg_idx, FloatReg val) 231 | { 232 | cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 233 | 234 | conditionalSquash(); 235 | } 236 | 237 | template 238 | void 239 | O3ThreadContext::setFloatRegBitsFlat(int reg_idx, FloatRegBits val) 240 | { 241 | cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 242 | 243 | conditionalSquash(); 244 | } 245 | 246 | template 247 | void 248 | O3ThreadContext::setCCRegFlat(int reg_idx, TheISA::CCReg val) 249 | { 250 | cpu->setArchCCReg(reg_idx, val, thread->threadId()); 251 | 252 | conditionalSquash(); 253 | } 254 | 255 | template 256 | void 257 | O3ThreadContext::pcState(const TheISA::PCState &val) 258 | { 259 | cpu->pcState(val, thread->threadId()); 260 | 261 | conditionalSquash(); 262 | } 263 | 264 | template 265 | void 266 | O3ThreadContext::pcStateNoRecord(const TheISA::PCState &val) 267 | { 268 | cpu->pcState(val, thread->threadId()); 269 | 270 | conditionalSquash(); 271 | } 272 | 273 | template 274 | int 275 | O3ThreadContext::flattenIntIndex(int reg) 276 | { 277 | return cpu->isa[thread->threadId()]->flattenIntIndex(reg); 278 | } 279 | 280 | template 281 | int 282 | O3ThreadContext::flattenFloatIndex(int reg) 283 | { 284 | return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); 285 | } 286 | 287 | template 288 | int 289 | O3ThreadContext::flattenCCIndex(int reg) 290 | { 291 | return cpu->isa[thread->threadId()]->flattenCCIndex(reg); 292 | } 293 | 294 | template 295 | void 296 | O3ThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 297 | { 298 | cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 299 | 300 | conditionalSquash(); 301 | } 302 | 303 | #endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ 304 | template 305 | void 306 | O3ThreadContext::setMiscReg(int misc_reg, const MiscReg &val) 307 | { 308 | cpu->setMiscReg(misc_reg, val, thread->threadId()); 309 | 310 | conditionalSquash(); 311 | } 312 | 313 | -------------------------------------------------------------------------------- /Project/project2/handin/o3/thread_state.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012 ARM Limited 3 | * All rights reserved 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2006 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Kevin Lim 41 | */ 42 | 43 | #ifndef __CPU_O3_THREAD_STATE_HH__ 44 | #define __CPU_O3_THREAD_STATE_HH__ 45 | 46 | #include "base/callback.hh" 47 | #include "base/output.hh" 48 | #include "cpu/thread_context.hh" 49 | #include "cpu/thread_state.hh" 50 | #include "sim/full_system.hh" 51 | #include "sim/sim_exit.hh" 52 | 53 | class EndQuiesceEvent; 54 | class Event; 55 | class FunctionalMemory; 56 | class FunctionProfile; 57 | class Process; 58 | class ProfileNode; 59 | 60 | /** 61 | * Class that has various thread state, such as the status, the 62 | * current instruction being processed, whether or not the thread has 63 | * a trap pending or is being externally updated, the ThreadContext 64 | * pointer, etc. It also handles anything related to a specific 65 | * thread's process, such as syscalls and checking valid addresses. 66 | */ 67 | template 68 | struct O3ThreadState : public ThreadState { 69 | typedef ThreadContext::Status Status; 70 | typedef typename Impl::O3CPU O3CPU; 71 | 72 | private: 73 | /** Pointer to the CPU. */ 74 | O3CPU *cpu; 75 | public: 76 | /* This variable controls if writes to a thread context should cause a all 77 | * dynamic/speculative state to be thrown away. Nominally this is the 78 | * desired behavior because the external thread context write has updated 79 | * some state that could be used by an inflight instruction, however there 80 | * are some cases like in a fault/trap handler where this behavior would 81 | * lead to successive restarts and forward progress couldn't be made. This 82 | * variable controls if the squashing will occur. 83 | */ 84 | bool noSquashFromTC; 85 | 86 | /** Whether or not the thread is currently waiting on a trap, and 87 | * thus able to be externally updated without squashing. 88 | */ 89 | bool trapPending; 90 | 91 | O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process) 92 | : ThreadState(_cpu, _thread_num, _process), 93 | cpu(_cpu), noSquashFromTC(false), trapPending(false) 94 | { 95 | if (!FullSystem) 96 | return; 97 | 98 | if (cpu->params()->profile) { 99 | profile = new FunctionProfile( 100 | cpu->params()->system->kernelSymtab); 101 | Callback *cb = 102 | new MakeCallback(this); 104 | registerExitCallback(cb); 105 | } 106 | 107 | // let's fill with a dummy node for now so we don't get a segfault 108 | // on the first cycle when there's no node available. 109 | static ProfileNode dummyNode; 110 | profileNode = &dummyNode; 111 | profilePC = 3; 112 | } 113 | 114 | void serialize(std::ostream &os) 115 | { 116 | ThreadState::serialize(os); 117 | // Use the ThreadContext serialization helper to serialize the 118 | // TC. 119 | ::serialize(*tc, os); 120 | } 121 | 122 | void unserialize(Checkpoint *cp, const std::string §ion) 123 | { 124 | // Prevent squashing - we don't have any instructions in 125 | // flight that we need to squash since we just instantiated a 126 | // clean system. 127 | noSquashFromTC = true; 128 | ThreadState::unserialize(cp, section); 129 | // Use the ThreadContext serialization helper to unserialize 130 | // the TC. 131 | ::unserialize(*tc, cp, section); 132 | noSquashFromTC = false; 133 | } 134 | 135 | /** Pointer to the ThreadContext of this thread. */ 136 | ThreadContext *tc; 137 | 138 | /** Returns a pointer to the TC of this thread. */ 139 | ThreadContext *getTC() { return tc; } 140 | 141 | /** Handles the syscall. */ 142 | void syscall(int64_t callnum) { process->syscall(callnum, tc); } 143 | 144 | void dumpFuncProfile() 145 | { 146 | std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 147 | profile->dump(tc, *os); 148 | } 149 | }; 150 | 151 | #endif // __CPU_O3_THREAD_STATE_HH__ 152 | -------------------------------------------------------------------------------- /Project/project2/handin/pro2_report.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project2/handin/pro2_report.docx -------------------------------------------------------------------------------- /Project/project3/Part1/base.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 ARM Limited 3 | * All rights reserved. 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Erik Hallnor 41 | * Ron Dreslinski 42 | */ 43 | 44 | /** 45 | * @file 46 | * Definitions of BaseTags. 47 | */ 48 | 49 | #include "config/the_isa.hh" 50 | #include "cpu/smt.hh" //maxThreadsPerCPU 51 | #include "mem/cache/tags/base.hh" 52 | #include "mem/cache/base.hh" 53 | #include "sim/sim_exit.hh" 54 | 55 | using namespace std; 56 | 57 | BaseTags::BaseTags(const Params *p) 58 | : ClockedObject(p), blkSize(p->block_size), size(p->size), 59 | hitLatency(p->hit_latency) 60 | { 61 | } 62 | 63 | void 64 | BaseTags::setCache(BaseCache *_cache) 65 | { 66 | cache = _cache; 67 | } 68 | 69 | void 70 | BaseTags::regStats() 71 | { 72 | using namespace Stats; 73 | replacements 74 | .init(maxThreadsPerCPU) 75 | .name(name() + ".replacements") 76 | .desc("number of replacements") 77 | .flags(total) 78 | ; 79 | 80 | tagsInUse 81 | .name(name() + ".tagsinuse") 82 | .desc("Cycle average of tags in use") 83 | ; 84 | 85 | totalRefs 86 | .name(name() + ".total_refs") 87 | .desc("Total number of references to valid blocks.") 88 | ; 89 | 90 | sampledRefs 91 | .name(name() + ".sampled_refs") 92 | .desc("Sample count of references to valid blocks.") 93 | ; 94 | 95 | avgRefs 96 | .name(name() + ".avg_refs") 97 | .desc("Average number of references to valid blocks.") 98 | ; 99 | 100 | avgRefs = totalRefs/sampledRefs; 101 | 102 | warmupCycle 103 | .name(name() + ".warmup_cycle") 104 | .desc("Cycle when the warmup percentage was hit.") 105 | ; 106 | 107 | occupancies 108 | .init(cache->system->maxMasters()) 109 | .name(name() + ".occ_blocks") 110 | .desc("Average occupied blocks per requestor") 111 | .flags(nozero | nonan) 112 | ; 113 | for (int i = 0; i < cache->system->maxMasters(); i++) { 114 | occupancies.subname(i, cache->system->getMasterName(i)); 115 | } 116 | 117 | avgOccs 118 | .name(name() + ".occ_percent") 119 | .desc("Average percentage of cache occupancy") 120 | .flags(nozero | total) 121 | ; 122 | for (int i = 0; i < cache->system->maxMasters(); i++) { 123 | avgOccs.subname(i, cache->system->getMasterName(i)); 124 | } 125 | 126 | avgOccs = occupancies / Stats::constant(numBlocks); 127 | 128 | registerExitCallback(new BaseTagsCallback(this)); 129 | } 130 | -------------------------------------------------------------------------------- /Project/project3/Part1/base.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013 ARM Limited 3 | * All rights reserved. 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Erik Hallnor 41 | * Ron Dreslinski 42 | */ 43 | 44 | /** 45 | * @file 46 | * Declaration of a common base class for cache tagstore objects. 47 | */ 48 | 49 | #ifndef __BASE_TAGS_HH__ 50 | #define __BASE_TAGS_HH__ 51 | 52 | #include 53 | 54 | #include "base/callback.hh" 55 | #include "base/statistics.hh" 56 | #include "params/BaseTags.hh" 57 | #include "sim/clocked_object.hh" 58 | 59 | class BaseCache; 60 | 61 | /** 62 | * A common base class of Cache tagstore objects. 63 | */ 64 | class BaseTags : public ClockedObject 65 | { 66 | protected: 67 | /** The block size of the cache. */ 68 | const unsigned blkSize; 69 | /** The size of the cache. */ 70 | const unsigned size; 71 | /** The hit latency of the cache. */ 72 | const Cycles hitLatency; 73 | 74 | /** Pointer to the parent cache. */ 75 | BaseCache *cache; 76 | 77 | /** 78 | * The number of tags that need to be touched to meet the warmup 79 | * percentage. 80 | */ 81 | int warmupBound; 82 | /** Marked true when the cache is warmed up. */ 83 | bool warmedUp; 84 | 85 | /** the number of blocks in the cache */ 86 | unsigned numBlocks; 87 | 88 | // Statistics 89 | /** 90 | * @addtogroup CacheStatistics 91 | * @{ 92 | */ 93 | 94 | /** Number of replacements of valid blocks per thread. */ 95 | Stats::Vector replacements; 96 | /** Per cycle average of the number of tags that hold valid data. */ 97 | Stats::Average tagsInUse; 98 | 99 | /** The total number of references to a block before it is replaced. */ 100 | Stats::Scalar totalRefs; 101 | 102 | /** 103 | * The number of reference counts sampled. This is different from 104 | * replacements because we sample all the valid blocks when the simulator 105 | * exits. 106 | */ 107 | Stats::Scalar sampledRefs; 108 | 109 | /** 110 | * Average number of references to a block before is was replaced. 111 | * @todo This should change to an average stat once we have them. 112 | */ 113 | Stats::Formula avgRefs; 114 | 115 | /** The cycle that the warmup percentage was hit. */ 116 | Stats::Scalar warmupCycle; 117 | 118 | /** Average occupancy of each requestor using the cache */ 119 | Stats::AverageVector occupancies; 120 | 121 | /** Average occ % of each requestor using the cache */ 122 | Stats::Formula avgOccs; 123 | 124 | /** 125 | * @} 126 | */ 127 | 128 | public: 129 | typedef BaseTagsParams Params; 130 | BaseTags(const Params *p); 131 | 132 | /** 133 | * Destructor. 134 | */ 135 | virtual ~BaseTags() {} 136 | 137 | /** 138 | * Set the parent cache back pointer. 139 | * @param _cache Pointer to parent cache. 140 | */ 141 | void setCache(BaseCache *_cache); 142 | 143 | /** 144 | * Register local statistics. 145 | */ 146 | void regStats(); 147 | 148 | /** 149 | * Average in the reference count for valid blocks when the simulation 150 | * exits. 151 | */ 152 | virtual void cleanupRefs() {} 153 | 154 | /** 155 | *iterated through all blocks and clear all locks 156 | *Needed to clear all lock tracking at once 157 | */ 158 | virtual void clearLocks() {} 159 | 160 | /** 161 | * Print all tags used 162 | */ 163 | virtual std::string print() const = 0; 164 | }; 165 | 166 | class BaseTagsCallback : public Callback 167 | { 168 | BaseTags *tags; 169 | public: 170 | BaseTagsCallback(BaseTags *t) : tags(t) {} 171 | virtual void process() { tags->cleanupRefs(); }; 172 | }; 173 | 174 | #endif //__BASE_TAGS_HH__ 175 | -------------------------------------------------------------------------------- /Project/project3/Part1/blk.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2007 The Regents of The University of Michigan 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are 7 | * met: redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer; 9 | * redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution; 12 | * neither the name of the copyright holders nor the names of its 13 | * contributors may be used to endorse or promote products derived from 14 | * this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | */ 28 | 29 | #include "base/cprintf.hh" 30 | #include "mem/cache/blk.hh" 31 | 32 | void 33 | CacheBlkPrintWrapper::print(std::ostream &os, int verbosity, 34 | const std::string &prefix) const 35 | { 36 | ccprintf(os, "%sblk %c%c%c\n", prefix, 37 | blk->isValid() ? 'V' : '-', 38 | blk->isWritable() ? 'E' : '-', 39 | blk->isDirty() ? 'M' : '-'); 40 | } 41 | 42 | -------------------------------------------------------------------------------- /Project/project3/Part1/cacheset.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 ARM Limited 3 | * All rights reserved. 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2009 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Lisa Hsu 41 | */ 42 | 43 | /** 44 | * @file 45 | * Declaration of an associative set 46 | */ 47 | 48 | #ifndef __CACHESET_HH__ 49 | #define __CACHESET_HH__ 50 | 51 | #include 52 | 53 | #include "mem/cache/blk.hh" // base class 54 | 55 | /** 56 | * An associative set of cache blocks. 57 | */ 58 | template 59 | class CacheSet 60 | { 61 | public: 62 | /** The associativity of this set. */ 63 | int assoc; 64 | 65 | /** Cache blocks in this set, maintained in LRU order 0 = MRU. */ 66 | Blktype **blks; 67 | 68 | /** 69 | * Find a block matching the tag in this set. 70 | * @param way_id The id of the way that matches the tag. 71 | * @param tag The Tag to find. 72 | * @return Pointer to the block if found. Set way_id to assoc if none found 73 | */ 74 | Blktype* findBlk(Addr tag, int& way_id) const ; 75 | Blktype* findBlk(Addr tag) const ; 76 | 77 | /** 78 | * Move the given block to the head of the list. 79 | * @param blk The block to move. 80 | */ 81 | void moveToHead(Blktype *blk); 82 | 83 | /** 84 | * Move the given block to the tail of the list. 85 | * @param blk The block to move 86 | */ 87 | void moveToTail(Blktype *blk); 88 | 89 | }; 90 | 91 | template 92 | Blktype* 93 | CacheSet::findBlk(Addr tag, int& way_id) const 94 | { 95 | /** 96 | * Way_id returns the id of the way that matches the block 97 | * If no block is found way_id is set to assoc. 98 | */ 99 | way_id = assoc; 100 | for (int i = 0; i < assoc; ++i) { 101 | if (blks[i]->tag == tag && blks[i]->isValid()) { 102 | way_id = i; 103 | return blks[i]; 104 | } 105 | } 106 | return NULL; 107 | } 108 | 109 | template 110 | Blktype* 111 | CacheSet::findBlk(Addr tag) const 112 | { 113 | int ignored_way_id; 114 | return findBlk(tag, ignored_way_id); 115 | } 116 | 117 | template 118 | void 119 | CacheSet::moveToHead(Blktype *blk) 120 | { 121 | // nothing to do if blk is already head 122 | if (blks[0] == blk) 123 | return; 124 | 125 | // write 'next' block into blks[i], moving up from MRU toward LRU 126 | // until we overwrite the block we moved to head. 127 | 128 | // start by setting up to write 'blk' into blks[0] 129 | int i = 0; 130 | Blktype *next = blk; 131 | 132 | do { 133 | assert(i < assoc); 134 | // swap blks[i] and next 135 | Blktype *tmp = blks[i]; 136 | blks[i] = next; 137 | next = tmp; 138 | ++i; 139 | } while (next != blk); 140 | } 141 | 142 | template 143 | void 144 | CacheSet::moveToTail(Blktype *blk) 145 | { 146 | // nothing to do if blk is already tail 147 | if (blks[assoc - 1] == blk) 148 | return; 149 | 150 | // write 'next' block into blks[i], moving from LRU to MRU 151 | // until we overwrite the block we moved to tail. 152 | 153 | // start by setting up to write 'blk' into tail 154 | int i = assoc - 1; 155 | Blktype *next = blk; 156 | 157 | do { 158 | assert(i >= 0); 159 | // swap blks[i] and next 160 | Blktype *tmp = blks[i]; 161 | blks[i] = next; 162 | next = tmp; 163 | --i; 164 | } while (next != blk); 165 | } 166 | 167 | #endif 168 | -------------------------------------------------------------------------------- /Project/project3/Part1/lfu_WLT.hh: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013 ARM Limited 3 | * All rights reserved. 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Erik Hallnor 41 | */ 42 | 43 | /** 44 | * @file 45 | * Declaration of a LFU tag store. 46 | */ 47 | 48 | #ifndef __MEM_CACHE_TAGS_LFU_HH__ 49 | #define __MEM_CACHE_TAGS_LFU_HH__ 50 | 51 | #include 52 | #include 53 | #include 54 | 55 | #include "mem/cache/tags/base.hh" 56 | #include "mem/cache/tags/cacheset.hh" 57 | #include "mem/cache/blk.hh" 58 | #include "mem/packet.hh" 59 | #include "params/LFU.hh" 60 | 61 | class BaseCache; 62 | 63 | 64 | /** 65 | * A LFU cache tag store. 66 | * @sa \ref gem5MemorySystem "gem5 Memory System" 67 | */ 68 | class LFU : public BaseTags 69 | { 70 | public: 71 | /** Typedef the block type used in this tag store. */ 72 | typedef CacheBlk BlkType; 73 | /** Typedef for a list of pointers to the local block class. */ 74 | typedef std::list BlkList; 75 | /** Typedef the set type used in this tag store. */ 76 | typedef CacheSet SetType; 77 | 78 | 79 | protected: 80 | /** The associativity of the cache. */ 81 | const unsigned assoc; 82 | /** The number of sets in the cache. */ 83 | const unsigned numSets; 84 | 85 | /** The cache sets. */ 86 | SetType *sets; 87 | 88 | /** The cache blocks. */ 89 | BlkType *blks; 90 | /** The data blocks, 1 per cache block. */ 91 | uint8_t *dataBlks; 92 | 93 | /** The amount to shift the address to get the set. */ 94 | int setShift; 95 | /** The amount to shift the address to get the tag. */ 96 | int tagShift; 97 | /** Mask out all bits that aren't part of the set index. */ 98 | unsigned setMask; 99 | /** Mask out all bits that aren't part of the block offset. */ 100 | unsigned blkMask; 101 | 102 | public: 103 | 104 | /** Convenience typedef. */ 105 | typedef LFUParams Params; 106 | 107 | /** 108 | * Construct and initialize this tag store. 109 | */ 110 | LFU(const Params *p); 111 | 112 | /** 113 | * Destructor 114 | */ 115 | virtual ~LFU(); 116 | 117 | /** 118 | * Return the block size. 119 | * @return the block size. 120 | */ 121 | unsigned 122 | getBlockSize() const 123 | { 124 | return blkSize; 125 | } 126 | 127 | /** 128 | * Return the subblock size. In the case of LFU it is always the block 129 | * size. 130 | * @return The block size. 131 | */ 132 | unsigned 133 | getSubBlockSize() const 134 | { 135 | return blkSize; 136 | } 137 | 138 | /** 139 | * Invalidate the given block. 140 | * @param blk The block to invalidate. 141 | */ 142 | void invalidate(BlkType *blk); 143 | 144 | /** 145 | * Access block and update replacement data. May not succeed, in which case 146 | * NULL pointer is returned. This has all the implications of a cache 147 | * access and should only be used as such. Returns the access latency as a side effect. 148 | * @param addr The address to find. 149 | * @param asid The address space ID. 150 | * @param lat The access latency. 151 | * @return Pointer to the cache block if found. 152 | */ 153 | BlkType* accessBlock(Addr addr, Cycles &lat, int context_src); 154 | 155 | /** 156 | * Finds the given address in the cache, do not update replacement data. 157 | * i.e. This is a no-side-effect find of a block. 158 | * @param addr The address to find. 159 | * @param asid The address space ID. 160 | * @return Pointer to the cache block if found. 161 | */ 162 | BlkType* findBlock(Addr addr) const; 163 | 164 | /** 165 | * Find a block to evict for the address provided. 166 | * @param addr The addr to a find a replacement candidate for. 167 | * @param writebacks List for any writebacks to be performed. 168 | * @return The candidate block. 169 | */ 170 | BlkType* findVictim(Addr addr, PacketList &writebacks); 171 | 172 | /** 173 | * Insert the new block into the cache. For LFU this means inserting into 174 | * the MRU position of the set. 175 | * @param pkt Packet holding the address to update 176 | * @param blk The block to update. 177 | */ 178 | void insertBlock(PacketPtr pkt, BlkType *blk); 179 | 180 | /** 181 | * Generate the tag from the given address. 182 | * @param addr The address to get the tag from. 183 | * @return The tag of the address. 184 | */ 185 | Addr extractTag(Addr addr) const 186 | { 187 | return (addr >> tagShift); 188 | } 189 | 190 | /** 191 | * Calculate the set index from the address. 192 | * @param addr The address to get the set from. 193 | * @return The set index of the address. 194 | */ 195 | int extractSet(Addr addr) const 196 | { 197 | return ((addr >> setShift) & setMask); 198 | } 199 | 200 | /** 201 | * Get the block offset from an address. 202 | * @param addr The address to get the offset of. 203 | * @return The block offset. 204 | */ 205 | int extractBlkOffset(Addr addr) const 206 | { 207 | return (addr & blkMask); 208 | } 209 | 210 | /** 211 | * Align an address to the block size. 212 | * @param addr the address to align. 213 | * @return The block address. 214 | */ 215 | Addr blkAlign(Addr addr) const 216 | { 217 | return (addr & ~(Addr)blkMask); 218 | } 219 | 220 | /** 221 | * Regenerate the block address from the tag. 222 | * @param tag The tag of the block. 223 | * @param set The set of the block. 224 | * @return The block address. 225 | */ 226 | Addr regenerateBlkAddr(Addr tag, unsigned set) const 227 | { 228 | return ((tag << tagShift) | ((Addr)set << setShift)); 229 | } 230 | 231 | /** 232 | * Return the hit latency. 233 | * @return the hit latency. 234 | */ 235 | Cycles getHitLatency() const 236 | { 237 | return hitLatency; 238 | } 239 | /** 240 | *iterated through all blocks and clear all locks 241 | *Needed to clear all lock tracking at once 242 | */ 243 | virtual void clearLocks(); 244 | 245 | /** 246 | * Called at end of simulation to complete average block reference stats. 247 | */ 248 | virtual void cleanupRefs(); 249 | 250 | /** 251 | * Print all tags used 252 | */ 253 | virtual std::string print() const; 254 | 255 | /** 256 | * Visit each block in the tag store and apply a visitor to the 257 | * block. 258 | * 259 | * The visitor should be a function (or object that behaves like a 260 | * function) that takes a cache block reference as its parameter 261 | * and returns a bool. A visitor can request the traversal to be 262 | * stopped by returning false, returning true causes it to be 263 | * called for the next block in the tag store. 264 | * 265 | * \param visitor Visitor to call on each block. 266 | */ 267 | template 268 | void forEachBlk(V &visitor) { 269 | for (unsigned i = 0; i < numSets * assoc; ++i) { 270 | if (!visitor(blks[i])) 271 | return; 272 | } 273 | } 274 | }; 275 | 276 | #endif // __MEM_CACHE_TAGS_LFU_HH__ 277 | -------------------------------------------------------------------------------- /Project/project3/Part1/lru.cc: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2012-2013 ARM Limited 3 | * All rights reserved. 4 | * 5 | * The license below extends only to copyright in the software and shall 6 | * not be construed as granting a license to any other intellectual 7 | * property including but not limited to intellectual property relating 8 | * to a hardware implementation of the functionality of the software 9 | * licensed hereunder. You may use the software subject to the license 10 | * terms below provided that you ensure that this notice is replicated 11 | * unmodified and in its entirety in all distributions of the software, 12 | * modified or unmodified, in source code or in binary form. 13 | * 14 | * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted provided that the following conditions are 19 | * met: redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer; 21 | * redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in the 23 | * documentation and/or other materials provided with the distribution; 24 | * neither the name of the copyright holders nor the names of its 25 | * contributors may be used to endorse or promote products derived from 26 | * this software without specific prior written permission. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * Authors: Erik Hallnor 41 | */ 42 | 43 | /** 44 | * @file 45 | * Definitions of LRU tag store. 46 | */ 47 | 48 | #include 49 | 50 | #include "base/intmath.hh" 51 | #include "debug/Cache.hh" 52 | #include "debug/CacheRepl.hh" 53 | #include "mem/cache/tags/lru.hh" 54 | #include "mem/cache/base.hh" 55 | #include "sim/core.hh" 56 | 57 | using namespace std; 58 | 59 | LRU::LRU(const Params *p) 60 | :BaseTags(p), assoc(p->assoc), 61 | numSets(p->size / (p->block_size * p->assoc)) 62 | { 63 | // Check parameters 64 | if (blkSize < 4 || !isPowerOf2(blkSize)) { 65 | fatal("Block size must be at least 4 and a power of 2"); 66 | } 67 | if (numSets <= 0 || !isPowerOf2(numSets)) { 68 | fatal("# of sets must be non-zero and a power of 2"); 69 | } 70 | if (assoc <= 0) { 71 | fatal("associativity must be greater than zero"); 72 | } 73 | if (hitLatency <= 0) { 74 | fatal("access latency must be greater than zero"); 75 | } 76 | 77 | blkMask = blkSize - 1; 78 | setShift = floorLog2(blkSize); 79 | setMask = numSets - 1; 80 | tagShift = setShift + floorLog2(numSets); 81 | warmedUp = false; 82 | /** @todo Make warmup percentage a parameter. */ 83 | warmupBound = numSets * assoc; 84 | 85 | sets = new SetType[numSets]; 86 | blks = new BlkType[numSets * assoc]; 87 | // allocate data storage in one big chunk 88 | numBlocks = numSets * assoc; 89 | dataBlks = new uint8_t[numBlocks * blkSize]; 90 | 91 | unsigned blkIndex = 0; // index into blks array 92 | for (unsigned i = 0; i < numSets; ++i) { 93 | sets[i].assoc = assoc; 94 | 95 | sets[i].blks = new BlkType*[assoc]; 96 | 97 | // link in the data blocks 98 | for (unsigned j = 0; j < assoc; ++j) { 99 | // locate next cache block 100 | BlkType *blk = &blks[blkIndex]; 101 | blk->data = &dataBlks[blkSize*blkIndex]; 102 | ++blkIndex; 103 | 104 | // invalidate new cache block 105 | blk->invalidate(); 106 | 107 | //EGH Fix Me : do we need to initialize blk? 108 | 109 | // Setting the tag to j is just to prevent long chains in the hash 110 | // table; won't matter because the block is invalid 111 | blk->tag = j; 112 | blk->whenReady = 0; 113 | blk->isTouched = false; 114 | blk->size = blkSize; 115 | sets[i].blks[j]=blk; 116 | blk->set = i; 117 | } 118 | } 119 | } 120 | 121 | LRU::~LRU() 122 | { 123 | delete [] dataBlks; 124 | delete [] blks; 125 | delete [] sets; 126 | } 127 | 128 | LRU::BlkType* 129 | LRU::accessBlock(Addr addr, Cycles &lat, int master_id) 130 | { 131 | Addr tag = extractTag(addr); 132 | unsigned set = extractSet(addr); 133 | BlkType *blk = sets[set].findBlk(tag); 134 | lat = hitLatency; 135 | if (blk != NULL) { 136 | // move this block to head of the MRU list 137 | sets[set].moveToHead(blk); 138 | DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n", 139 | set, regenerateBlkAddr(tag, set)); 140 | if (blk->whenReady > curTick() 141 | && cache->ticksToCycles(blk->whenReady - curTick()) > hitLatency) { 142 | lat = cache->ticksToCycles(blk->whenReady - curTick()); 143 | } 144 | blk->refCount += 1; /** Number of references to this block since it was brought in. */ 145 | } 146 | 147 | return blk; 148 | } 149 | 150 | 151 | LRU::BlkType* 152 | LRU::findBlock(Addr addr) const 153 | { 154 | Addr tag = extractTag(addr); 155 | unsigned set = extractSet(addr); 156 | BlkType *blk = sets[set].findBlk(tag); 157 | return blk; 158 | } 159 | 160 | LRU::BlkType* 161 | LRU::findVictim(Addr addr, PacketList &writebacks) 162 | { 163 | unsigned set = extractSet(addr); 164 | // grab a replacement candidate 165 | BlkType *blk = sets[set].blks[assoc-1]; 166 | 167 | if (blk->isValid()) { 168 | DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n", 169 | set, regenerateBlkAddr(blk->tag, set)); 170 | } 171 | return blk; 172 | } 173 | 174 | void 175 | LRU::insertBlock(PacketPtr pkt, BlkType *blk) 176 | { 177 | Addr addr = pkt->getAddr(); 178 | MasterID master_id = pkt->req->masterId(); 179 | if (!blk->isTouched) { 180 | tagsInUse++; 181 | blk->isTouched = true; 182 | if (!warmedUp && tagsInUse.value() >= warmupBound) { 183 | warmedUp = true; 184 | warmupCycle = curTick(); 185 | } 186 | } 187 | 188 | // If we're replacing a block that was previously valid update 189 | // stats for it. This can't be done in findBlock() because a 190 | // found block might not actually be replaced there if the 191 | // coherence protocol says it can't be. 192 | if (blk->isValid()) { 193 | replacements[0]++; 194 | totalRefs += blk->refCount; 195 | ++sampledRefs; 196 | blk->refCount = 0; 197 | 198 | // deal with evicted block 199 | assert(blk->srcMasterId < cache->system->maxMasters()); 200 | occupancies[blk->srcMasterId]--; 201 | 202 | blk->invalidate(); 203 | } 204 | 205 | blk->isTouched = true; 206 | // Set tag for new block. Caller is responsible for setting status. 207 | blk->tag = extractTag(addr); 208 | 209 | // deal with what we are bringing in 210 | assert(master_id < cache->system->maxMasters()); 211 | occupancies[master_id]++; 212 | blk->srcMasterId = master_id; 213 | 214 | unsigned set = extractSet(addr); 215 | sets[set].moveToHead(blk); 216 | } 217 | 218 | void 219 | LRU::invalidate(BlkType *blk) 220 | { 221 | assert(blk); 222 | assert(blk->isValid()); 223 | tagsInUse--; 224 | assert(blk->srcMasterId < cache->system->maxMasters()); 225 | occupancies[blk->srcMasterId]--; 226 | blk->srcMasterId = Request::invldMasterId; 227 | 228 | // should be evicted before valid blocks 229 | unsigned set = blk->set; 230 | sets[set].moveToTail(blk); 231 | } 232 | 233 | void 234 | LRU::clearLocks() 235 | { 236 | for (int i = 0; i < numBlocks; i++){ 237 | blks[i].clearLoadLocks(); 238 | } 239 | } 240 | 241 | LRU * 242 | LRUParams::create() 243 | { 244 | return new LRU(this); 245 | } 246 | std::string 247 | LRU::print() const { 248 | std::string cache_state; 249 | for (unsigned i = 0; i < numSets; ++i) { 250 | // link in the data blocks 251 | for (unsigned j = 0; j < assoc; ++j) { 252 | BlkType *blk = sets[i].blks[j]; 253 | if (blk->isValid()) 254 | cache_state += csprintf("\tset: %d block: %d %s\n", i, j, 255 | blk->print()); 256 | } 257 | } 258 | if (cache_state.empty()) 259 | cache_state = "no valid tags\n"; 260 | return cache_state; 261 | } 262 | 263 | void 264 | LRU::cleanupRefs() 265 | { 266 | for (unsigned i = 0; i < numSets*assoc; ++i) { 267 | if (blks[i].isValid()) { 268 | totalRefs += blks[i].refCount; 269 | ++sampledRefs; 270 | } 271 | } 272 | } 273 | -------------------------------------------------------------------------------- /Project/project3/Project3.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project3/Project3.pdf -------------------------------------------------------------------------------- /Project/project3/report.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project3/report.docx -------------------------------------------------------------------------------- /Project/project4/18640_project4-4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/18640_project4-4.pdf -------------------------------------------------------------------------------- /Project/project4/18640_project4/mmm/Makefile: -------------------------------------------------------------------------------- 1 | all: mmm_all_in_one mmm_single_thread_scalar mmm_single_thread_simd mmm_multi_thread_scalar mmm_multi_thread_simd 2 | 3 | mmm_all_in_one: mmm_all_in_one.c 4 | gcc -msse4 -g -o mmm_all_in_one mmm_all_in_one.c -lpthread 5 | 6 | mmm_single_thread_scalar: mmm_single_thread_scalar.c 7 | gcc -msse4 -g -o mmm_single_thread_scalar mmm_single_thread_scalar.c -lpthread 8 | 9 | mmm_single_thread_simd: mmm_single_thread_simd.c 10 | gcc -msse4 -g -o mmm_single_thread_simd mmm_single_thread_simd.c -lpthread 11 | 12 | mmm_multi_thread_scalar: mmm_multi_thread_scalar.c 13 | gcc -msse4 -g -o mmm_multi_thread_scalar mmm_multi_thread_scalar.c -lpthread 14 | 15 | mmm_multi_thread_simd: mmm_multi_thread_simd.c 16 | gcc -msse4 -g -o mmm_multi_thread_simd mmm_multi_thread_simd.c -lpthread 17 | 18 | clean: 19 | del mmm_all_in_one.exe mmm_single_thread_scalar.exe mmm_single_thread_simd.exe mmm_multi_thread_scalar.exe mmm_multi_thread_simd.exe 20 | -------------------------------------------------------------------------------- /Project/project4/18640_project4/mmm/README.txt: -------------------------------------------------------------------------------- 1 | Before you compile by mingw32's gcc, make sure you have installed mingw32-pthreads-w32 (class:dev) in the MinGW Installation Manager. -------------------------------------------------------------------------------- /Project/project4/18640_project4/mmm/mmm_multi_thread_scalar.c: -------------------------------------------------------------------------------- 1 | /* 2 | * 18-640 F15 Project 4 3 | * mmm.c: Matrix-Matrix Multiplication 4 | * Guanglin Xu 5 | * 6 | * some helper functions are acquired from Internet. 7 | * 8 | */ 9 | 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | 17 | #define N 1024// matrix width. You can try 512, 1024, 2048. 18 | #define NB 4 // block width. N and NB must be evenly divisible. 19 | 20 | // blocked building block. 21 | void mmm_blocked_building_block(float *A, float *BT, float *CT) { 22 | int i, j, k; 23 | for (j = 0; jthreadid; 50 | A = param->A; 51 | BT = param->B; 52 | CT = param->C; 53 | 54 | j = threadid * NB; 55 | for (i = 0; i < N; i += NB) { 56 | for (k = 0; k < N; k += NB) { 57 | mmm_blocked_building_block(&(A[i * N + k]), &(BT[j * N + k]), &(CT[j * N + i])); 58 | } 59 | } 60 | 61 | /* each thread instance calls pthread_exit( ) when 62 | finished to sync up with pthread_join() call in main(). */ 63 | pthread_exit(NULL); 64 | } 65 | 66 | #define NUMTHREADS (N/NB) 67 | void mmm_block_pthread(float *A, float *BT, float *CT) { 68 | 69 | /* allocate bookkeeping data structure for NUMTHREADS threads */ 70 | pthread_t threads[NUMTHREADS]; 71 | int rc; 72 | long threadid; 73 | 74 | thread_params params[NUMTHREADS]; 75 | 76 | /* call pthread_create to spawn NUMTHREADS executions of 77 | Bash() as threads */ 78 | for (threadid = 0; threadid < NUMTHREADS; threadid++) { 79 | params[threadid].threadid = threadid; 80 | params[threadid].A = A; 81 | params[threadid].B = BT; 82 | params[threadid].C = CT; 83 | 84 | /* spawn Bash as pthreads sending threadid as argument */ 85 | rc = pthread_create(&threads[threadid], NULL, thread_func_multi_thread, 86 | (void *)¶ms[threadid]); 87 | if (rc) { 88 | printf("ERROR; return code from pthread_create() is %d\n", rc); 89 | } 90 | } 91 | 92 | /* The calls to pthread_join() will block until 93 | the designated thread (that is "threads[threadid]") 94 | has exited. */ 95 | { 96 | void *status; 97 | for (threadid = 0; threadid < NUMTHREADS; threadid++) { 98 | pthread_join(threads[threadid], &status); 99 | } 100 | } 101 | } 102 | 103 | int main() { 104 | 105 | struct timeval start_time, end_time; 106 | 107 | float *A = (float*)malloc(N * N * sizeof(float)); // input matrix A 108 | float *B = (float*)malloc(N * N * sizeof(float)); // input matrix B 109 | float *BT = (float*)malloc(N * N * sizeof(float)); // B transpose for SIMD. 110 | float *CT_multithread = (float*)malloc(N * N * sizeof(float)); 111 | assert(A != NULL); 112 | assert(B != NULL); 113 | assert(BT != NULL); 114 | assert(CT_multithread != NULL); 115 | assert(N >= NB); 116 | assert((N%NB) == 0); 117 | 118 | // init matrices randomly 119 | int x, y; 120 | srand(time(NULL)); 121 | for (x = 0; x < N; x++) { 122 | for (y = 0; y < N; y++) { 123 | A[x * N + y] = (float)rand() * 5 / RAND_MAX; 124 | B[x * N + y] = (float)rand() * 5 / RAND_MAX; 125 | } 126 | } 127 | for (x = 0; x < N; x++) { 128 | for (y = 0; y < N; y++) { 129 | BT[y * N + x] = B[x * N + y]; 130 | CT_multithread[y * N + x] = 0; 131 | } 132 | } 133 | 134 | double dur; 135 | 136 | // multi-threading blocked MMM 137 | gettimeofday(&start_time, NULL); 138 | mmm_block_pthread(A, BT, CT_multithread); 139 | gettimeofday(&end_time, NULL); 140 | dur = (end_time.tv_sec - start_time.tv_sec) * 1e6 141 | + (end_time.tv_usec - start_time.tv_usec); 142 | printf( 143 | "%d-by-%d multi-threading blocked MMM: %0.1f (microsec) = %0.1f (sec)\n", 144 | N, N, 145 | (end_time.tv_sec - start_time.tv_sec) * 1e6 146 | + (end_time.tv_usec - start_time.tv_usec), dur / 1000000); 147 | 148 | free(A); 149 | free(B); 150 | free(BT); 151 | free(CT_multithread); 152 | return 0; 153 | } 154 | -------------------------------------------------------------------------------- /Project/project4/18640_project4/mmm/mmm_single_thread_scalar.c: -------------------------------------------------------------------------------- 1 | /* 2 | * 18-640 F15 Project 4 3 | * mmm.c: Matrix-Matrix Multiplication 4 | * Guanglin Xu 5 | * 6 | * some helper functions are acquired from Internet. 7 | * 8 | */ 9 | 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | 16 | #define N 1024// matrix width 17 | #define NB 32 // block width. N and NB must be evenly divisible. 18 | 19 | // blocked building block. 20 | void mmm_blocked_building_block(float *A, float *B, float *C) { 21 | int i, j, k; 22 | for(j=0; j=NB); 57 | assert((N%NB)==0); 58 | 59 | // init matrices randomly 60 | int x, y; 61 | srand(time(NULL)); 62 | for (x = 0; x < N; x++) { 63 | for (y = 0; y < N; y++) { 64 | A[x * N + y] = (float) rand() * 5 / RAND_MAX; 65 | B[x * N + y] = (float) rand() * 5 / RAND_MAX; 66 | } 67 | } 68 | for (x = 0; x < N; x++) { 69 | for (y = 0; y < N; y++) { 70 | BT[y * N + x] = B[x * N + y]; 71 | CT_blocked[y * N + x] = 0; 72 | } 73 | } 74 | 75 | double dur; 76 | 77 | // single thread blocked MMM 78 | gettimeofday(&start_time, NULL); 79 | mmm_blocked(A, BT, CT_blocked); 80 | gettimeofday(&end_time, NULL); 81 | dur = (end_time.tv_sec - start_time.tv_sec) * 1e6 82 | + (end_time.tv_usec - start_time.tv_usec); 83 | printf( 84 | "%d-by-%d single thread blocked MMM: %0.1f (microsec) = %0.1f (sec)\n", 85 | N, N, 86 | (end_time.tv_sec - start_time.tv_sec) * 1e6 87 | + (end_time.tv_usec - start_time.tv_usec), dur / 1000000); 88 | 89 | free(A); 90 | free(B); 91 | free(BT); 92 | free(CT_blocked); 93 | return 0; 94 | } 95 | -------------------------------------------------------------------------------- /Project/project4/Project_4_18-640_Fall_15_pdf.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/Project_4_18-640_Fall_15_pdf.pdf -------------------------------------------------------------------------------- /Project/project4/group7/mmm_multi_thread_scalar/consuming_max_time.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_multi_thread_scalar/consuming_max_time.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_multi_thread_scalar/mmm_multi_thread_scalar.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_multi_thread_scalar/mmm_multi_thread_scalar.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_multi_thread_scalar/mmm_multi_thread_scalar.txt: -------------------------------------------------------------------------------- 1 | Elapsed Time: 8.275s 2 | Clockticks: 32,494,800,000 3 | Instructions Retired: 32,459,400,000 4 | CPI Rate: 1.001 5 | MUX Reliability: 1.000 6 | Retiring uOps: 0.500 7 | MS Assists: 0.011 8 | FP Assists: 0.000 9 | Wasted Work: 10 | Branch Mispredict: 0.021 11 | SMC Machine Clear: 0.000 12 | Back-end Issues: 13 | Memory Latency: 14 | LLC Miss: 0.000 15 | LLC Hit: 0.024 16 | DTLB Overhead: 0.000 17 | Contested Accesses: 0.000 18 | Page Walk: 0.001 19 | Bus Lock: 0.000 20 | Memory Reissues: 21 | Split Loads: 0.000 22 | Split Stores: 0.000 23 | Loads Blocked by Store Forwarding: 0.002 24 | Divider: 0.001 25 | Front-end Issues: 0.016 26 | ICache Misses: 0.000 27 | ITLB Overhead: 0.000 28 | Total Thread Count: 253 29 | Paused Time: 0s 30 | 31 | 32 | 33 | Elapsed Time: 9.922s 34 | CPU Time: 28.675s 35 | Effective Time: 28.595s 36 | Idle: 0.080s 37 | Poor: 1.806s 38 | Ok: 6.548s 39 | Ideal: 20.161s 40 | Over: 0s 41 | Spin Time: 0.080s 42 | Overhead Time: 0s 43 | Instructions Retired: 45,397,849,460 44 | Estimated Call Count: 2,801,121 45 | CPI Rate: 1.000 46 | Wait Rate: 2,034.435 47 | CPU Frequency Ratio: 1.187 48 | Context Switch Time: 1525.431s 49 | Wait Time: 1251.178s 50 | Inactive Time: 274.253s 51 | Estimated Call Count: 2,801,121 52 | Total Thread Count: 257 53 | Paused Time: 1.724s 54 | -------------------------------------------------------------------------------- /Project/project4/group7/mmm_multi_thread_simd/consuming_max_time.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_multi_thread_simd/consuming_max_time.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_multi_thread_simd/mmm_multi_thread_simd.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_multi_thread_simd/mmm_multi_thread_simd.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_multi_thread_simd/mmm_multi_thread_simd.txt: -------------------------------------------------------------------------------- 1 | Elapsed Time: 2.053s 2 | Clockticks: 10,700,800,000 3 | Instructions Retired: 2,799,600,000 4 | CPI Rate: 3.822 5 | MUX Reliability: 1.000 6 | Retiring uOps: 0.134 7 | MS Assists: 0.012 8 | FP Assists: 0.000 9 | Wasted Work: 10 | Branch Mispredict: 0.002 11 | SMC Machine Clear: 0.000 12 | Back-end Issues: 13 | Memory Latency: 14 | LLC Miss: 1.000 15 | LLC Hit: 0.133 16 | DTLB Overhead: 0.006 17 | Contested Accesses: 0.000 18 | Page Walk: 0.118 19 | Bus Lock: 0.000 20 | Memory Reissues: 21 | Split Loads: 0.000 22 | Split Stores: 0.000 23 | Loads Blocked by Store Forwarding: 0.185 24 | Divider: 0.006 25 | Front-end Issues: 0.009 26 | ICache Misses: 0.009 27 | ITLB Overhead: 0.001 28 | Total Thread Count: 257 29 | Paused Time: 0s 30 | 31 | 32 | 33 | 34 | 35 | Elapsed Time: 2.270s 36 | CPU Time: 6.976s 37 | Effective Time: 6.849s 38 | Idle: 0.047s 39 | Poor: 0.892s 40 | Ok: 1.621s 41 | Ideal: 4.289s 42 | Over: 0s 43 | Spin Time: 0.126s 44 | Overhead Time: 0s 45 | Instructions Retired: 2,780,144,486 46 | Estimated Call Count: 2,962,766 47 | CPI Rate: 3.987 48 | Wait Rate: 440.442 49 | CPU Frequency Ratio: 1.192 50 | Context Switch Time: 299.888s 51 | Wait Time: 268.669s 52 | Inactive Time: 31.219s 53 | Estimated Call Count: 2,962,766 54 | Total Thread Count: 257 55 | Paused Time: 0.127s 56 | -------------------------------------------------------------------------------- /Project/project4/group7/mmm_single_thread_scalar/consuming_max_time.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_single_thread_scalar/consuming_max_time.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_single_thread_scalar/mmm_single_thread_scalar.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_single_thread_scalar/mmm_single_thread_scalar.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_single_thread_scalar/mmm_single_thread_scalar.txt: -------------------------------------------------------------------------------- 1 | Elapsed Time: 31.424s 2 | Clockticks: 55,483,200,000 3 | Instructions Retired: 44,528,200,000 4 | CPI Rate: 1.246 5 | MUX Reliability: 1.000 6 | Retiring uOps: 0.403 7 | MS Assists: 0.005 8 | FP Assists: 0.000 9 | Wasted Work: 10 | Branch Mispredict: 0.006 11 | SMC Machine Clear: 0.000 12 | Back-end Issues: 13 | Memory Latency: 14 | LLC Miss: 0.009 15 | LLC Hit: 0.247 16 | DTLB Overhead: 0.000 17 | Contested Accesses: 0.000 18 | Page Walk: 0.003 19 | Bus Lock: 0.000 20 | Memory Reissues: 21 | Split Loads: 0.000 22 | Split Stores: 0.000 23 | Loads Blocked by Store Forwarding: 0.001 24 | Divider: 0.002 25 | Front-end Issues: 0.004 26 | ICache Misses: 0.000 27 | ITLB Overhead: 0.000 28 | Total Thread Count: 1 29 | Paused Time: 0s 30 | 31 | 32 | 33 | Elapsed Time: 31.102s 34 | CPU Time: 30.623s 35 | Effective Time: 30.623s 36 | Idle: 0.132s 37 | Poor: 30.490s 38 | Ok: 0s 39 | Ideal: 0s 40 | Over: 0s 41 | Spin Time: 0s 42 | Overhead Time: 0s 43 | Instructions Retired: 44,392,593,643 44 | Estimated Call Count: 2,200,935 45 | CPI Rate: 1.246 46 | Wait Rate: 0.462 47 | CPU Frequency Ratio: 1.354 48 | Context Switch Time: 0.048s 49 | Wait Time: 0.001s 50 | Inactive Time: 0.046s 51 | Estimated Call Count: 2,200,935 52 | Total Thread Count: 1 53 | Paused Time: 0s 54 | -------------------------------------------------------------------------------- /Project/project4/group7/mmm_single_thread_simd/consuming_max_time.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_single_thread_simd/consuming_max_time.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_single_thread_simd/mmm_single_thread_simd.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/group7/mmm_single_thread_simd/mmm_single_thread_simd.PNG -------------------------------------------------------------------------------- /Project/project4/group7/mmm_single_thread_simd/mmm_single_thread_simd.txt: -------------------------------------------------------------------------------- 1 | Elapsed Time: 5.429s 2 | Clockticks: 8,338,600,000 3 | Instructions Retired: 2,795,200,000 4 | CPI Rate: 2.983 5 | MUX Reliability: 1.000 6 | Retiring uOps: 0.182 7 | MS Assists: 0.021 8 | FP Assists: 0.000 9 | Wasted Work: 10 | Branch Mispredict: 0.000 11 | SMC Machine Clear: 0.000 12 | Back-end Issues: 13 | Memory Latency: 14 | LLC Miss: 1.000 15 | LLC Hit: 0.161 16 | DTLB Overhead: 0.008 17 | Contested Accesses: 0.000 18 | Page Walk: 0.148 19 | Bus Lock: 0.000 20 | Memory Reissues: 21 | Split Loads: 0.000 22 | Split Stores: 0.000 23 | Loads Blocked by Store Forwarding: 0.261 24 | Divider: 0.003 25 | Front-end Issues: 0.004 26 | ICache Misses: 0.000 27 | ITLB Overhead: 0.003 28 | Total Thread Count: 1 29 | Paused Time: 0s 30 | 31 | 32 | 33 | 34 | Elapsed Time: 4.838s 35 | CPU Time: 4.742s 36 | Effective Time: 4.742s 37 | Idle: 0.005s 38 | Poor: 4.737s 39 | Ok: 0s 40 | Ideal: 0s 41 | Over: 0s 42 | Spin Time: 0s 43 | Overhead Time: 0s 44 | Instructions Retired: 2,758,110,045 45 | Estimated Call Count: 19,033,093 46 | CPI Rate: 3.033 47 | Wait Rate: 0.437 48 | CPU Frequency Ratio: 1.323 49 | Context Switch Time: 0.013s 50 | Wait Time: 0.002s 51 | Inactive Time: 0.011s 52 | Estimated Call Count: 19,033,093 53 | Total Thread Count: 1 54 | Paused Time: 0s 55 | -------------------------------------------------------------------------------- /Project/project4/report.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wangluting/CMU-18640-Foundations-of-Computer-Architecture/3c1d63d67f8f54e8e3ac9ef6266fae164492860b/Project/project4/report.docx -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # CMU-18640-Foundations-of-Computer-Architecture 2 | This is the course taught by Prof.John Shen and Prof. Onur Mutlu from CMU 3 | ### Course content 4 | - Pipelined Processor 5 | - RAW, WAR, WAW hazards 6 | - Superscalar Implemetation 7 | - Dynamic Branch Prediction 8 | - Register Renaming 9 | - Tomasulo's Algorithm 10 | - Dynamic Scheduling and OOO Execution 11 | - VLIW 12 | - Multithreading and Multicore 13 | - Memory Resource Management 14 | - Interconnection Networks 15 | - Heterogeneous System 16 | 17 | ### Projects 18 | - 1. Branch Prediction 19 | - Analysis of Tournament and Bi-mode Predictor 20 | - Implement gshare and YAGS Predictor 21 | - 2. Modern Tomasulo’s Algorithm and Out-of-Order Execution 22 | - Model and simulate Modernized Tomasulo's Algorithm 23 | - Out of Order Model in Gem5 24 | - 3. Real-life Cache Modeling 25 | - Implement cache replacement policy LFU LRU 26 | - Design a cache coherence protocol 27 | - Analyze coherence mechanism i.e. directory-based and snooping-based 28 | - 4. Intel Compute Stick for computationally expensive tasks 29 | - Optimization of Matrix Matrix Multiply 30 | - OpenCV libraries for adge and line detection 31 | - Digit detect 32 | --------------------------------------------------------------------------------