├── doc └── cpu_top.pdf ├── simulator ├── benchmark │ ├── qsort │ │ ├── qsort │ │ ├── qsort.c │ │ └── qsort50.c │ ├── factorial │ │ ├── factorial.c │ │ ├── run_mips.sh │ │ ├── factorial-O2.asm │ │ ├── factorial-O1.asm │ │ ├── factorial-O3.asm │ │ └── factorial-O0.asm │ ├── fib │ │ ├── run_mips.sh │ │ ├── fib.c │ │ ├── fib-O1.asm │ │ ├── fib-O3.asm │ │ ├── fib-O2.asm │ │ └── fib-O0.asm │ ├── fir │ │ ├── run_mips.sh │ │ └── fir.c │ ├── mmult │ │ ├── run_mips.sh │ │ └── mmult.c │ ├── median │ │ ├── run_mips.sh │ │ └── median.c │ ├── crc │ │ ├── crc8int.c │ │ └── crc32int.c │ └── bubble │ │ ├── bubble.c │ │ ├── bubble-O1.asm │ │ ├── bubble-O2.asm │ │ └── bubble-O3.asm ├── src │ ├── Sourceline.py │ ├── bcolors.py │ ├── elf32instr.py │ ├── Checker.py │ ├── elf32parser.py │ └── Instruction.py ├── runSimulations.sh └── README.md ├── tb ├── arith-imm │ ├── Makefile │ ├── run.do │ ├── defines_pipeline.v │ └── test_tb.v ├── arith-reg │ ├── Makefile │ ├── simulated.txt │ ├── run.do │ ├── defines_pipeline.v │ └── test_tb.v ├── wave.do ├── run.do ├── fib_tb_output └── test_tb.v ├── readme.txt ├── ccode ├── fib.c └── fib_c_output └── rtl ├── readme.txt ├── primitive ├── glbl.v └── RAM32M.v ├── data_mem_infer.v ├── offset_add.v ├── ex2.v ├── ex3.v ├── ex4.v ├── ex1.v ├── status_register.v ├── defines.v ├── fetch.v ├── input_map.v ├── alu_intermediate_shreg.v ├── ex_o_shreg.v ├── execute.v ├── cpu_core.v └── alu_core.v /doc/cpu_top.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/warclab/idea/HEAD/doc/cpu_top.pdf -------------------------------------------------------------------------------- /simulator/benchmark/qsort/qsort: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/warclab/idea/HEAD/simulator/benchmark/qsort/qsort -------------------------------------------------------------------------------- /tb/arith-imm/Makefile: -------------------------------------------------------------------------------- 1 | clean: 2 | rm -rf bitmask.v defines.v data_mem.v vsim.wlf transcript work data.mif 3 | -------------------------------------------------------------------------------- /tb/arith-reg/Makefile: -------------------------------------------------------------------------------- 1 | clean: 2 | rm -rf bitmask.v defines.v data_mem.v vsim.wlf transcript work data.mif 3 | -------------------------------------------------------------------------------- /tb/arith-reg/simulated.txt: -------------------------------------------------------------------------------- 1 | 31 00000003 2 | 30 00000007 3 | 29 00000004 4 | 28 fffffff0 5 | 27 0000000b 6 | 26 00000001 7 | 25 00000000 8 | 24 ffffffff 9 | 23 ffffffff 10 | 22 00000007 11 | -------------------------------------------------------------------------------- /readme.txt: -------------------------------------------------------------------------------- 1 | iDEA Soft-Core Processor v1.00 2 | School of Computer Engineering 3 | Nanyang Technological University 4 | 5 | Any questions, contact: 6 | HuiYan Cheah hycheah1@e.ntu.edu.sg 7 | 8 | Folders: 9 | 1. rtl/ -- Source and testbench files for iDEA soft-core processor. 10 | 2. ccode/ -- C program. 11 | 3. doc/ -- Documentation, diagram of processor. 12 | 4. tools/ -- Future work. Compiler and tool support will be added in due course. 13 | -------------------------------------------------------------------------------- /tb/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave /test_tb/clk 4 | add wave /test_tb/rst 5 | add wave -radix hexadecimal /test_tb/reg_addr_0 6 | add wave -radix hexadecimal /test_tb/reg_addr_1 7 | add wave -radix hexadecimal /test_tb/reg_addr_2 8 | add wave -radix hexadecimal /test_tb/reg_addr_3 9 | add wave -radix hexadecimal /test_tb/reg_addr_4 10 | add wave -radix hexadecimal /test_tb/clk_count 11 | add wave -radix hexadecimal /test_tb/inst_count 12 | -------------------------------------------------------------------------------- /ccode/fib.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main () 4 | { 5 | int n = 50; 6 | int a = 0; 7 | int b = 1; 8 | int sum; 9 | int i; 10 | 11 | // Here we call the fibonacci function 12 | 13 | for ( i = 0; i < n; i++) 14 | { 15 | sum = a + b; 16 | a = b; 17 | b = sum; 18 | // Values are printed after a and b are re-assigned. 19 | printf("a: %u, b: %u, sum: %u\n", a, b, sum); 20 | } 21 | 22 | // Finally, return 0 23 | 24 | return 0; 25 | } 26 | -------------------------------------------------------------------------------- /rtl/readme.txt: -------------------------------------------------------------------------------- 1 | Design files: 2 | alu_core.v 3 | control.v 4 | cpu_core.v 5 | cpu_top.v 6 | data_mem_infer.v 7 | decode.v 8 | defines.v 9 | ex1.v 10 | ex2.v 11 | ex3.v 12 | ex4.v 13 | execute.v 14 | fetch.v 15 | input_map.v 16 | inst_mem_infer.v 17 | offset_add.v 18 | regfile.v 19 | status_register.v 20 | 21 | Xilinx primitive models: 22 | primitive/ 23 | DSP48E1.v 24 | glbl.v 25 | RAM32M.v 26 | RAMB36E1.v 27 | 28 | Testbench: 29 | test_tb.v 30 | 31 | Modelsim script: 32 | wave.do 33 | run.do 34 | 35 | Simulation output: 36 | fib_tb_output 37 | -------------------------------------------------------------------------------- /simulator/benchmark/factorial/factorial.c: -------------------------------------------------------------------------------- 1 | #include 2 | // iteration 28 3 | // sample size 8 4 | 5 | const unsigned int number = 8; // number of iterations 6 | const unsigned int output[] = {1,1,2,6,24,120,720,5040,40320}; 7 | 8 | int main() 9 | { 10 | //int counter = 0; 11 | unsigned int main_result = 0; 12 | unsigned int c[] = {1,1,1,1,1,1,1,1}; 13 | unsigned int i, j; 14 | 15 | for (j=0; j < number; j++) { 16 | for (i=0; i < j; i++){ 17 | c[j] = c[j] * (i+1); 18 | 19 | //counter = counter + 1; 20 | } 21 | } 22 | 23 | for (j=0; j < number; j++) { 24 | main_result += (output[j] != c[j]); 25 | } 26 | 27 | //printf("%d\n", counter); 28 | 29 | return main_result; 30 | } 31 | -------------------------------------------------------------------------------- /simulator/benchmark/fib/run_mips.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | mips-elf-gcc -O0 -c -g fib.c 3 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fib.o > fib-O0.asm 4 | #mips-elf-objdump -d -S -M no-aliases fib.o > fib-O0.asm # prints full inst instead of pseudo-inst 5 | #mips-elf-objdump -d -S -M gpr-names=numeric fib.o > fib-O0.asm # prints reg number instead of reg name 6 | 7 | mips-elf-gcc -O1 -c -g fib.c 8 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fib.o > fib-O1.asm 9 | 10 | mips-elf-gcc -O2 -c -g fib.c 11 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fib.o > fib-O2.asm 12 | 13 | mips-elf-gcc -O3 -c -g fib.c 14 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fib.o > fib-O3.asm 15 | 16 | #http://linux.die.net/man/1/objdump 17 | #http://sourceware.org/binutils/docs/binutils/objdump.html 18 | -------------------------------------------------------------------------------- /simulator/benchmark/fir/run_mips.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | mips-elf-gcc -O0 -c -g fir.c 3 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fir.o > fir-O0.asm 4 | #mips-elf-objdump -d -S -M no-aliases fir.o > fir-O0.asm # prints full inst instead of pseudo-inst 5 | #mips-elf-objdump -d -S -M gpr-names=numeric fir.o > fir-O0.asm # prints reg number instead of reg name 6 | 7 | mips-elf-gcc -O1 -c -g fir.c 8 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fir.o > fir-O1.asm 9 | 10 | mips-elf-gcc -O2 -c -g fir.c 11 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fir.o > fir-O2.asm 12 | 13 | mips-elf-gcc -O3 -c -g fir.c 14 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data fir.o > fir-O3.asm 15 | 16 | #http://linux.die.net/man/1/objdump 17 | #http://sourceware.org/binutils/docs/binutils/objdump.html 18 | -------------------------------------------------------------------------------- /simulator/benchmark/mmult/run_mips.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | mips-elf-gcc -O0 -c -g mmult.c 3 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data mmult.o > mmult-O0.asm 4 | #mips-elf-objdump -d -S -M no-aliases mmult.o > mmult-O0.asm # prints full inst instead of pseudo-inst 5 | #mips-elf-objdump -d -S -M gpr-names=numeric mmult.o > mmult-O0.asm # prints reg number instead of reg name 6 | 7 | mips-elf-gcc -O1 -c -g mmult.c 8 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data mmult.o > mmult-O1.asm 9 | 10 | mips-elf-gcc -O2 -c -g mmult.c 11 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data mmult.o > mmult-O2.asm 12 | 13 | mips-elf-gcc -O3 -c -g mmult.c 14 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data mmult.o > mmult-O3.asm 15 | 16 | #http://linux.die.net/man/1/objdump 17 | #http://sourceware.org/binutils/docs/binutils/objdump.html 18 | -------------------------------------------------------------------------------- /simulator/benchmark/median/run_mips.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | mips-elf-gcc -O0 -c -g median.c 3 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data median.o > median-O0.asm 4 | #mips-elf-objdump -d -S -M no-aliases median.o > median-O0.asm # prints full inst instead of pseudo-inst 5 | #mips-elf-objdump -d -S -M gpr-names=numeric median.o > median-O0.asm # prints reg number instead of reg name 6 | 7 | mips-elf-gcc -O1 -c -g median.c 8 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data median.o > median-O1.asm 9 | 10 | mips-elf-gcc -O2 -c -g median.c 11 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data median.o > median-O2.asm 12 | 13 | mips-elf-gcc -O3 -c -g median.c 14 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data median.o > median-O3.asm 15 | 16 | #http://linux.die.net/man/1/objdump 17 | #http://sourceware.org/binutils/docs/binutils/objdump.html 18 | -------------------------------------------------------------------------------- /simulator/benchmark/factorial/run_mips.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/sh 2 | mips-elf-gcc -O0 -c -g factorial.c 3 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data factorial.o > factorial-O0.asm 4 | #mips-elf-objdump -d -S -M no-aliases fir.o > fir-O0.asm # prints full inst instead of pseudo-inst 5 | #mips-elf-objdump -d -S -M gpr-names=numeric fir.o > fir-O0.asm # prints reg number instead of reg name 6 | 7 | mips-elf-gcc -O1 -c -g factorial.c 8 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data factorial.o > factorial-O1.asm 9 | 10 | mips-elf-gcc -O2 -c -g factorial.c 11 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data factorial.o > factorial-O2.asm 12 | 13 | mips-elf-gcc -O3 -c -g factorial.c 14 | mips-elf-objdump -D -S -M no-aliases -j .rodata -j .text -j .bss -j .data factorial.o > factorial-O3.asm 15 | 16 | #http://linux.die.net/man/1/objdump 17 | #http://sourceware.org/binutils/docs/binutils/objdump.html 18 | -------------------------------------------------------------------------------- /simulator/benchmark/crc/crc8int.c: -------------------------------------------------------------------------------- 1 | // Website origin: http://www.pololu.com/docs/0J44/6.7.6 2 | // CRC calculator: http://ghsi.de/CRC/index.php?Polynom=10010001&Message=01+83 3 | // Conversion algorithms: http://archive.online-convert.com/ 4 | 5 | //#include 6 | 7 | int main () 8 | { 9 | long CRC7_POLY = 0x91; 10 | long length = 50; 11 | long i, j; 12 | long message[61] = {0x83, 0x01, 0x00, 0x25, 0x23, 0xff, 0x01, 0xa0, 0xca, 0x20, 13 | 0x28, 0x15, 0x97, 0x31, 0xaf, 0x99, 0x1f, 0x42, 0x53, 0x23, 14 | 0x15, 0x00, 0x17, 0x45, 0x2f, 0x65, 0x42, 0x12, 0x93, 0xa4, 15 | 0x52, 0x23, 0x90, 0xa6, 0x1f, 0x66, 0xbc, 0x04, 0x33, 0xd6, 16 | 0xa4, 0x42, 0x15, 0x05, 0x3f, 0xd0, 0x9c, 0x02, 0x43, 0x9c, 17 | 0xa2, 0x00, 0x00, 0x30, 0x74, 0xa1, 0xbb, 0x15, 0x75, 0x1a, 0x01}; 18 | 19 | long crc = 0x0; 20 | 21 | for (i = 0; i < length; i++) 22 | { 23 | crc ^= message[i]; 24 | for (j = 0; j < 8; j++) 25 | { 26 | if (crc & 1) 27 | crc ^= CRC7_POLY; 28 | crc >>= 1; 29 | } 30 | } 31 | 32 | //printf("%d %x h\n", i, crc); 33 | 34 | return 0; 35 | } 36 | -------------------------------------------------------------------------------- /tb/run.do: -------------------------------------------------------------------------------- 1 | ###################################################################### 2 | # Modelsim simulation .do file template 3 | ###################################################################### 4 | 5 | # Create work library 6 | rm -rf work 7 | vlib work 8 | 9 | set primitive "../rtl/primitive" 10 | set rtl "../rtl" 11 | 12 | # Primitive simulation model 13 | vlog "$primitive/glbl.v" 14 | vlog "$primitive/RAM32M.v" 15 | vlog "$primitive/DSP48E1.v" 16 | vlog "$primitive/RAMB36E1.v" 17 | 18 | # Design RTL 19 | vlog "$rtl/decode.v" 20 | vlog "$rtl/alu_core.v" 21 | vlog "$rtl/control.v" 22 | vlog "$rtl/cpu_core.v" 23 | vlog "$rtl/cpu_top.v" 24 | vlog "$rtl/data_mem_infer.v" 25 | vlog "$rtl/defines.v" 26 | vlog "$rtl/ex1.v" 27 | vlog "$rtl/ex2.v" 28 | vlog "$rtl/ex3.v" 29 | vlog "$rtl/ex4.v" 30 | vlog "$rtl/execute.v" 31 | vlog "$rtl/fetch.v" 32 | vlog "$rtl/input_map.v" 33 | vlog "$rtl/inst_mem_infer.v" 34 | vlog "$rtl/offset_add.v" 35 | vlog "$rtl/regfile.v" 36 | vlog "$rtl/status_register.v" 37 | vlog "test_tb.v" 38 | 39 | # Call vsim to invoke simulator 40 | vsim -voptargs="+acc" -t 1ps -lib work test_tb glbl 41 | 42 | # Source the wave do file 43 | do wave.do 44 | 45 | # Set the window types 46 | log -r * 47 | #add wave -radix hexadecimal * 48 | 49 | # Run simulation 50 | run -all 51 | -------------------------------------------------------------------------------- /tb/arith-imm/run.do: -------------------------------------------------------------------------------- 1 | ###################################################################### 2 | # Modelsim simulation .do file template 3 | ###################################################################### 4 | set primitive "./../../../rtl/primitive" 5 | set rtl "./../../../rtl" 6 | 7 | # Create work library 8 | rm -rf work 9 | vlib work 10 | cp -f $rtl/defines.v . 11 | cp -f $rtl/bitmask.v . 12 | cp -f $rtl/data_mem.v . 13 | cp -r $rtl/data.mif . 14 | 15 | # Primitive simulation model 16 | vlog "$primitive/glbl.v" 17 | vlog "$primitive/RAM32M.v" 18 | vlog "$primitive/DSP48E1.v" 19 | vlog "$primitive/RAMB36E1.v" 20 | 21 | # Design RTL 22 | vlog "defines.v" 23 | vlog "bitmask.v" 24 | vlog "$rtl/decode.v" 25 | vlog "$rtl/alu_core.v" 26 | vlog "$rtl/control.v" 27 | vlog "$rtl/cpu_core.v" 28 | vlog "$rtl/cpu_top.v" 29 | vlog "data_mem.v" 30 | vlog "$rtl/alu_intermediate_shreg.v" 31 | vlog "$rtl/if_o_shreg.v" 32 | vlog "$rtl/ex_o_shreg.v" 33 | vlog "$rtl/execute.v" 34 | vlog "$rtl/fetch.v" 35 | vlog "$rtl/input_map.v" 36 | vlog "inst_mem.v" 37 | vlog "$rtl/effective_addr.v" 38 | vlog "$rtl/regfile.v" 39 | vlog "test_tb.v" 40 | 41 | # Call vsim to invoke simulator 42 | vsim -voptargs="+acc" -t 1ps -lib work test_tb glbl 43 | 44 | # Source the wave do file 45 | #do wave.do 46 | 47 | # Set the window types 48 | log -r * 49 | add wave -radix hexadecimal * 50 | 51 | # Run simulation 52 | run -all 53 | -------------------------------------------------------------------------------- /tb/arith-reg/run.do: -------------------------------------------------------------------------------- 1 | ###################################################################### 2 | # Modelsim simulation .do file template 3 | ###################################################################### 4 | set primitive "./../../../rtl-pipeline/primitive" 5 | set rtl "./../../../rtl-pipeline" 6 | 7 | # Create work library 8 | rm -rf work 9 | vlib work 10 | cp -f $rtl/defines.v . 11 | cp -f $rtl/bitmask.v . 12 | cp -f $rtl/data_mem.v . 13 | cp -r $rtl/data.mif . 14 | 15 | # Primitive simulation model 16 | vlog "$primitive/glbl.v" 17 | vlog "$primitive/RAM32M.v" 18 | vlog "$primitive/DSP48E1.v" 19 | vlog "$primitive/RAMB36E1.v" 20 | 21 | # Design RTL 22 | vlog "defines.v" 23 | vlog "bitmask.v" 24 | vlog "$rtl/decode.v" 25 | vlog "$rtl/alu_core.v" 26 | vlog "$rtl/control.v" 27 | vlog "$rtl/cpu_core.v" 28 | vlog "$rtl/cpu_top.v" 29 | vlog "data_mem.v" 30 | vlog "$rtl/alu_intermediate_shreg.v" 31 | vlog "$rtl/id_intermediate_shreg.v" 32 | vlog "$rtl/if_o_shreg.v" 33 | vlog "$rtl/ex_o_shreg.v" 34 | vlog "$rtl/execute.v" 35 | vlog "$rtl/fetch.v" 36 | vlog "$rtl/input_map.v" 37 | vlog "inst_mem.v" 38 | vlog "$rtl/effective_addr.v" 39 | vlog "$rtl/regfile.v" 40 | vlog "test_tb.v" 41 | 42 | # Call vsim to invoke simulator 43 | vsim -voptargs="+acc" -t 1ps -lib work test_tb glbl 44 | 45 | # Source the wave do file 46 | #do wave.do 47 | 48 | # Set the window types 49 | log -r * 50 | add wave -radix hexadecimal * 51 | 52 | # Run simulation 53 | run -all 54 | -------------------------------------------------------------------------------- /simulator/benchmark/bubble/bubble.c: -------------------------------------------------------------------------------- 1 | /* Bubble sort code */ 2 | // iteration 1225 3 | // sample size 50 4 | #include 5 | 6 | const int output[50] = {0, 0, 1, 1, 2, 2, 3, 4, 5, 6, 7 | 8, 8, 8, 9, 9, 11, 11, 12, 15, 15, 8 | 15, 17, 17, 18, 19, 20, 21, 21, 21, 21, 9 | 22, 22, 22, 24, 24, 25, 25, 31, 32, 35, 10 | 36, 38, 41, 45, 47, 50, 51, 54, 55, 65}; 11 | int main() 12 | { 13 | //int counter = 0; 14 | int n = 50; 15 | int i, c, d, swap; 16 | int main_result = 0; 17 | int array[50] = {36, 38, 41, 24, 47, 50, 51, 32, 15, 65, 18 | 15, 21, 17, 18, 19, 20, 17, 21, 21, 21, 19 | 22, 54, 22, 45, 24, 25, 25, 31, 22, 35, 20 | 2, 0, 1, 1, 0, 2, 3, 4, 5, 6, 21 | 8, 8, 8, 9, 9, 11, 55, 12, 15, 11}; 22 | 23 | for (c = 0 ; c < ( n - 1 ); c++) 24 | { 25 | for (d = 0 ; d < n - c - 1; d++) 26 | { 27 | if (array[d] > array[d+1]) /* For decreasing order use < */ 28 | { 29 | swap = array[d]; 30 | array[d] = array[d+1]; 31 | array[d+1] = swap; 32 | } 33 | //counter = counter + 1; 34 | } 35 | } 36 | 37 | for (i = 0; i < 50; i++){ 38 | 39 | main_result += (output[i] != array[i]); 40 | 41 | //printf("%d, ", array[i]); 42 | } 43 | //printf ("%d\n", main_result); 44 | //printf("%d\n", counter); 45 | 46 | return main_result; 47 | } 48 | -------------------------------------------------------------------------------- /rtl/primitive/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | 3 | `timescale 1 ps / 1 ps 4 | 5 | module glbl (); 6 | 7 | parameter ROC_WIDTH = 100000; 8 | parameter TOC_WIDTH = 0; 9 | 10 | //-------- STARTUP Globals -------------- 11 | wire GSR; 12 | wire GTS; 13 | wire GWE; 14 | wire PRLD; 15 | tri1 p_up_tmp; 16 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 17 | 18 | wire PROGB_GLBL; 19 | 20 | reg GSR_int; 21 | reg GTS_int; 22 | reg PRLD_int; 23 | 24 | //-------- JTAG Globals -------------- 25 | wire JTAG_TDO_GLBL; 26 | wire JTAG_TCK_GLBL; 27 | wire JTAG_TDI_GLBL; 28 | wire JTAG_TMS_GLBL; 29 | wire JTAG_TRST_GLBL; 30 | 31 | reg JTAG_CAPTURE_GLBL; 32 | reg JTAG_RESET_GLBL; 33 | reg JTAG_SHIFT_GLBL; 34 | reg JTAG_UPDATE_GLBL; 35 | reg JTAG_RUNTEST_GLBL; 36 | 37 | reg JTAG_SEL1_GLBL = 0; 38 | reg JTAG_SEL2_GLBL = 0 ; 39 | reg JTAG_SEL3_GLBL = 0; 40 | reg JTAG_SEL4_GLBL = 0; 41 | 42 | reg JTAG_USER_TDO1_GLBL = 1'bz; 43 | reg JTAG_USER_TDO2_GLBL = 1'bz; 44 | reg JTAG_USER_TDO3_GLBL = 1'bz; 45 | reg JTAG_USER_TDO4_GLBL = 1'bz; 46 | 47 | assign (weak1, weak0) GSR = GSR_int; 48 | assign (weak1, weak0) GTS = GTS_int; 49 | assign (weak1, weak0) PRLD = PRLD_int; 50 | 51 | initial begin 52 | GSR_int = 1'b1; 53 | PRLD_int = 1'b1; 54 | #(ROC_WIDTH) 55 | GSR_int = 1'b0; 56 | PRLD_int = 1'b0; 57 | end 58 | 59 | initial begin 60 | GTS_int = 1'b1; 61 | #(TOC_WIDTH) 62 | GTS_int = 1'b0; 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /simulator/src/Sourceline.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | ################################################################## 4 | # 5 | # iDEA Simulator 6 | # Sourceline.py 7 | # 8 | # NOT USED! 9 | # Supposed to contain debug information for instructions 10 | # 11 | # Fredrik Brosser 2013-05-14 12 | # 13 | ################################################################## 14 | 15 | 16 | class Sourceline(object): 17 | 18 | def __init__(self, **input): 19 | self.instr = None 20 | self.opcode = None 21 | self.addr = None 22 | self.line = None 23 | self.comment = None 24 | 25 | for key in input: 26 | if key in self.values.keys(): 27 | self.values[key] = input[key] 28 | else: 29 | self.controls[key] = input[key] 30 | 31 | @property 32 | def instr(self): 33 | """ Get this line's instruction """ 34 | return self.instr 35 | 36 | @property 37 | def opcode(self): 38 | """ Get this line's opcode """ 39 | return opcode 40 | 41 | @property 42 | def addr(self): 43 | """ Get this line's memory address as given in asm file """ 44 | return self.addr 45 | 46 | @property 47 | def line(self): 48 | """ Get this line's line number """ 49 | return self.line 50 | 51 | @property 52 | def comment(self): 53 | """ Get this line's comment (if any) """ 54 | return self.comment 55 | 56 | def __str__(self): 57 | str = "%s %s\t %s %s %s" % (self.line, self.addr, ":", self.opcode, self.instr, self.comment) 58 | return str 59 | -------------------------------------------------------------------------------- /simulator/benchmark/mmult/mmult.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | // iteration 125 4 | // sample size 5x5 5 | 6 | const int a[5][5] = { {1, 2, 3, 4, 5}, 7 | {6, 7, 8, 9, 10}, 8 | {11, 12, 13, 14, 15}, 9 | {16, 17, 18, 19, 20}, 10 | {21, 22, 23, 24, 25}}; 11 | 12 | const int b[5][5] = { {1, 0, 1, 0, 1}, 13 | {1, 1, 1, 1, 1}, 14 | {1, 1, 1, 0, 0}, 15 | {0, 0, 0, 1, 1}, 16 | {1, 0, 1, 0, 1}}; 17 | 18 | const int output[5][5] = { {11, 5, 11, 6, 12}, 19 | {31, 15, 31, 16, 32}, 20 | {51, 25, 51, 26, 52}, 21 | {71, 35, 71, 36, 72}, 22 | {91, 45, 91, 46, 92}}; 23 | 24 | int main() 25 | { 26 | //int counter = 0; 27 | 28 | int volatile c[5][5]; 29 | int i, j, k; 30 | int x, y; 31 | int sum = 0; 32 | 33 | int main_result = 0; 34 | 35 | for (i = 0; i < 5; i++) { 36 | for (j = 0; j < 5; j++) { 37 | sum = 0; 38 | for (k = 0; k < 5 ; k++) { 39 | sum = sum + a[i][k] * b[k][j]; 40 | c[i][j]=sum; 41 | 42 | //counter = counter + 1; 43 | } 44 | } 45 | } 46 | 47 | for (x = 0; x < 5; x++){ 48 | for (y = 0; y < 5; y++) { 49 | main_result += (output[x][y] != c[x][y]); 50 | // printf("c[%i][%i] = %i\n", i, j, c[i][j]); 51 | } 52 | } 53 | 54 | //printf("%d\n", counter); 55 | //printf("%d\n", main_result); 56 | 57 | return main_result; 58 | } 59 | -------------------------------------------------------------------------------- /simulator/benchmark/fir/fir.c: -------------------------------------------------------------------------------- 1 | #include "stdio.h" 2 | // gcc -o fir fir.c 3 | // ./fir.exe 4 | 5 | // iteration 250 6 | // sample size 50 7 | 8 | const int data[54] = { 45, 1, 22, 53, 10, 12, 13, 25, 33, 14, 9 | 12, 36, 12, 2, 24, 15, 5, 3, 42, 13, 10 | 33, 25, 35, 25, 14, 31, 41, 17, 15, 22, 11 | 16, 26, 22, 29, 25, 11, 33, 20, 21, 9, 12 | 25, 21, 4, 21, 14, 14, 32, 30, 13, 1, 13 | 0, 0, 0, 0}; // Padded line for y[49] 14 | 15 | const int output[50] = { 1176, 1112, 716, 720, 816, 970, 911, 846, 865, 800, 16 | 588, 591, 621, 432, 552, 710, 1047, 985, 1231, 1174, 17 | 1147, 1010, 1099, 1221, 1121, 887, 809, 830, 861, 1003, 18 | 1031, 1000, 949, 913, 1012, 813, 797, 747, 763, 662, 19 | 590, 664, 719, 937, 1043, 815, 453, 170, 44, 3}; 20 | 21 | int main () { 22 | 23 | //int counter = 0; 24 | int i; 25 | int main_result = 0; 26 | 27 | int k, n; 28 | int sum; 29 | 30 | int ndata = 50; 31 | int ncoeff = 5; 32 | int /*short*/ coeff[5] = { 3, 5, 15, 12, 7}; 33 | int y[50]; 34 | 35 | for (n = 0; n < ndata; n++) { 36 | sum = 0; 37 | for (k = 0; k < ncoeff; k++) { 38 | sum = sum + coeff[k] * data[k+n]; 39 | y[n] = sum; 40 | 41 | //counter = counter + 1; 42 | } 43 | } 44 | 45 | for (i = 0; i < 50; i++){ 46 | main_result += (output[i] != y[i]); 47 | } 48 | //printf ("%d\n", main_result); 49 | //printf ("%d\n", counter); 50 | 51 | return main_result; 52 | } 53 | -------------------------------------------------------------------------------- /ccode/fib_c_output: -------------------------------------------------------------------------------- 1 | a: 1, b: 1, sum: 1 2 | a: 1, b: 2, sum: 2 3 | a: 2, b: 3, sum: 3 4 | a: 3, b: 5, sum: 5 5 | a: 5, b: 8, sum: 8 6 | a: 8, b: 13, sum: 13 7 | a: 13, b: 21, sum: 21 8 | a: 21, b: 34, sum: 34 9 | a: 34, b: 55, sum: 55 10 | a: 55, b: 89, sum: 89 11 | a: 89, b: 144, sum: 144 12 | a: 144, b: 233, sum: 233 13 | a: 233, b: 377, sum: 377 14 | a: 377, b: 610, sum: 610 15 | a: 610, b: 987, sum: 987 16 | a: 987, b: 1597, sum: 1597 17 | a: 1597, b: 2584, sum: 2584 18 | a: 2584, b: 4181, sum: 4181 19 | a: 4181, b: 6765, sum: 6765 20 | a: 6765, b: 10946, sum: 10946 21 | a: 10946, b: 17711, sum: 17711 22 | a: 17711, b: 28657, sum: 28657 23 | a: 28657, b: 46368, sum: 46368 24 | a: 46368, b: 75025, sum: 75025 25 | a: 75025, b: 121393, sum: 121393 26 | a: 121393, b: 196418, sum: 196418 27 | a: 196418, b: 317811, sum: 317811 28 | a: 317811, b: 514229, sum: 514229 29 | a: 514229, b: 832040, sum: 832040 30 | a: 832040, b: 1346269, sum: 1346269 31 | a: 1346269, b: 2178309, sum: 2178309 32 | a: 2178309, b: 3524578, sum: 3524578 33 | a: 3524578, b: 5702887, sum: 5702887 34 | a: 5702887, b: 9227465, sum: 9227465 35 | a: 9227465, b: 14930352, sum: 14930352 36 | a: 14930352, b: 24157817, sum: 24157817 37 | a: 24157817, b: 39088169, sum: 39088169 38 | a: 39088169, b: 63245986, sum: 63245986 39 | a: 63245986, b: 102334155, sum: 102334155 40 | a: 102334155, b: 165580141, sum: 165580141 41 | a: 165580141, b: 267914296, sum: 267914296 42 | a: 267914296, b: 433494437, sum: 433494437 43 | a: 433494437, b: 701408733, sum: 701408733 44 | a: 701408733, b: 1134903170, sum: 1134903170 45 | a: 1134903170, b: 1836311903, sum: 1836311903 46 | a: 1836311903, b: 2971215073, sum: 2971215073 47 | a: 2971215073, b: 512559680, sum: 512559680 48 | a: 512559680, b: 3483774753, sum: 3483774753 49 | a: 3483774753, b: 3996334433, sum: 3996334433 50 | a: 3996334433, b: 3185141890, sum: 3185141890 51 | -------------------------------------------------------------------------------- /simulator/benchmark/median/median.c: -------------------------------------------------------------------------------- 1 | #include 2 | // iteration 144 3 | // sample size 20 4 | 5 | // Good tutorial on median filter: http://www.librow.com/articles/article-1 6 | // window size 5 7 | const int signal[20] = {1, 2, 3, 4, 5, 8 | 6, 7, 8, 9, 10, 9 | 11, 12, 13, 14, 15, 10 | 16, 17, 18, 19, 20}; 11 | 12 | const int output[16] = {3, 4, 5, 6, 7, 13 | 8, 9, 10, 11, 12, 14 | 13, 14, 15, 16, 17, 15 | 18}; /*N - window_size - 1*/ 16 | 17 | int main () { 18 | 19 | //int counter = 0; 20 | 21 | int i, j, k; 22 | int min, temp; 23 | int N = 20; 24 | int window[5]; 25 | int result[20]; 26 | 27 | int main_result = 0; 28 | 29 | // Move window through all elements of input signal 30 | for (i = 2; i < N - 2; i++) { 31 | // Pick up the window elements 32 | for (j = 0; j < 5; j++) { 33 | window[j] = signal[i - 2 + j]; 34 | } 35 | // Sort the elements (only half of them) 36 | for (j = 0; j < 3; j++) { 37 | min = j; 38 | for (k = j + 1; k < 5; k++) { 39 | if (window[k] < window[min]) { 40 | min = k; 41 | } 42 | 43 | //counter = counter + 1; 44 | } 45 | // Put found minimum element in temp 46 | temp = window[j]; 47 | window[j] = window[min]; 48 | window[min] = temp; 49 | } 50 | // Get the result 51 | result[i - 2] = window[2]; 52 | } 53 | 54 | for (i = 0; i < 16 /*N - (window size -1)*/; i++){ 55 | main_result += (result[i] != output[i]); 56 | //printf("%i: %i\n", i, result[i]); 57 | } 58 | //printf("%d\n", counter); 59 | //printf("%i\n", main_result); 60 | 61 | return main_result; 62 | } 63 | -------------------------------------------------------------------------------- /simulator/src/bcolors.py: -------------------------------------------------------------------------------- 1 | ################################################################## 2 | # 3 | # iDEA Simulator 4 | # bcolors.py 5 | # 6 | # Debug colour output formatting 7 | # Fredrik Brosser 2013-05-14 8 | # 9 | ################################################################## 10 | 11 | 12 | class bcolors: 13 | 14 | ## Colour definitions 15 | HEADER = '\033[95m' 16 | OKBLUE = '\033[94m' 17 | OKGREEN = '\033[92m' 18 | WARNING = '\033[93m' 19 | FAIL = '\033[91m' 20 | ENDC = '\033[0m' 21 | 22 | ## Constructor 23 | def __init__(self): 24 | self.defaultErrorMsg = "Error" 25 | 26 | ## Disable colour output 27 | def disable(self): 28 | self.HEADER = '' 29 | self.OKBLUE = '' 30 | self.OKGREEN = '' 31 | self.WARNING = '' 32 | self.FAIL = '' 33 | self.ENDC = '' 34 | 35 | ## Print information for a successful test in Green 36 | # s : Name/Filename of test 37 | # stats : Statistics displayed for the test 38 | def printPass(self, s, stats): 39 | n = 1 40 | i = 40 41 | while i > 4: 42 | if (len(s) < i): 43 | n += 1 44 | i -= 8 45 | printstr = self.OKGREEN + "Passed \t| " + s + "\t" 46 | for stat in stats: 47 | printstr += str(stat) + "\t" 48 | printstr += self.ENDC 49 | print printstr 50 | 51 | ## Print a single statistic only (core cycles) 52 | def printCoreOnly(self, ccore): 53 | printstr = self.OKGREEN + str(ccore) + self.ENDC 54 | print printstr 55 | 56 | ## Print information for a failed test in Red 57 | # s : Name/Filename of test 58 | # errorMsg : Error message to be displayed 59 | def printFail(self, s, errorMsg): 60 | print self.FAIL + "Failed \t|\t " + s + "\t" + errorMsg + self.ENDC 61 | 62 | ## Print general error message 63 | # errorMsg : Error message to be displayed 64 | def printError(self, errorMsg): 65 | print self.FAIL + errorMsg + self.ENDC 66 | 67 | # END of bcolors.py -------------------------------------------------------------------------------- /rtl/data_mem_infer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /****************************************************************************************** 3 | Copyright (c) 2016 HuiYan Cheah. 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms are permitted provided that 7 | the above copyright notice and this paragraph are duplicated in all such forms 8 | and that any documentation, advertising materials, and other materials related 9 | to such distribution and use acknowledge that the software was developed by 10 | Nanyang Technological University. The name of Nanyang Technological University 11 | may not be used to endorse or promote products derived from this software 12 | without specific prior written permission. THIS SOFTWARE IS PROVIDED ``AS IS'' 13 | AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, 14 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 15 | 16 | * iDEA Soft-Core Processor 17 | * HuiYan Cheah, 2016 hycheah1@e.ntu.edu.sg 18 | * School of Computer Engineering 19 | * Nanyang Technological University 20 | * 21 | * This processor is a proof-of-concept of the usability of the DSP48E1 as 22 | * the execution unit of a general-purpose processor. It is not a full-blown processor. 23 | * 24 | * Description: 25 | * Data Memory of size 512 x 32. 26 | * Block RAM is inferred through behavioural description. 27 | * Inferred Block RAM mode is No Change to obtain maximum frequency. 28 | * Internal output register is enabled. 29 | * 30 | 31 | ******************************************************************************************/ 32 | `include "defines.v" 33 | 34 | module data_mem ( 35 | input clk, 36 | input we_i, 37 | input [`dm_addr_width-1:0] addr_i, 38 | input [31:0] din_i, 39 | output reg [31:0] dout_o 40 | ); 41 | 42 | reg [31:0] ram0 [0:`dm_depth-1]; 43 | reg [31:0] dout_r0; 44 | 45 | always@ (posedge clk) // No change 46 | begin 47 | if (we_i) 48 | ram0[addr_i] <= din_i; 49 | else 50 | dout_r0 <= ram0[addr_i]; 51 | end 52 | 53 | always@ (posedge clk) 54 | begin 55 | dout_o <= dout_r0; 56 | end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /simulator/benchmark/fib/fib.c: -------------------------------------------------------------------------------- 1 | // gcc -o fib fib.c 2 | // ./fib.exe > output 3 | 4 | // iteration 45 5 | // sample size 45 6 | 7 | /** 8 | * You'll notice that we need to include a header file that 9 | * contains functions we need to use. Being a compiled language, 10 | * it's inefficient to include functions that aren't needed. 11 | * stdio.h contains functions for reading from and writing to the console 12 | */ 13 | 14 | #include 15 | 16 | /** 17 | * In C, the program executes the main function. You should also take note 18 | * that we must declare a return type for the function. In this case, it's 19 | * an integer, and we return 0 to indicate successful completion of the 20 | * program. 21 | */ 22 | const int output[45] = { 1, 2, 3, 5, 8, 23 | 13, 21, 34, 55, 89, 24 | 144, 233, 377, 610, 987, 25 | 1597, 2584, 4181, 6765, 10946, 26 | 17711, 28657, 46368, 75025, 121393, 27 | 196418, 317811, 514229, 832040, 1346269, 28 | 2178309, 3524578, 5702887, 9227465, 14930352, 29 | 24157817, 39088169, 63245986, 102334155, 165580141, 30 | 267914296, 433494437, 701408733, 1134903170, 1836311903/*, 31 | 2971215073, 512559680, 3483774753, 3996334433, 3185141890*/ }; // warning: this decimal constant is unsigned only in ISO C90 32 | 33 | int main () 34 | { 35 | /* Notice that we need to declare our variables, and their type */ 36 | 37 | //int counter = 0; 38 | int n = 45; 39 | int a = 0; 40 | int b = 1; 41 | int i; 42 | 43 | volatile int sum[n]; 44 | 45 | int main_result = 0; 46 | 47 | for ( i = 0; i < n; i++) 48 | { 49 | sum[i] = a + b; 50 | a = b; 51 | b = sum[i]; 52 | 53 | //counter = counter + 1; 54 | } 55 | 56 | for (i = 0; i < n; i++){ 57 | main_result += (output[i] != sum[i]); 58 | //printf("%u, ", sum[i]); 59 | } 60 | //printf ("%d\n", main_result); 61 | //printf("%d\n", counter); 62 | 63 | return main_result; 64 | } 65 | -------------------------------------------------------------------------------- /rtl/primitive/RAM32M.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAM32M.v,v 1.5 2010/01/14 00:42:01 yanx Exp $ 2 | /////////////////////////////////////////////////////////////////////////////// 3 | // Copyright (c) 1995/2004 Xilinx, Inc. 4 | // All Right Reserved. 5 | /////////////////////////////////////////////////////////////////////////////// 6 | // ____ ____ 7 | // / /\/ / 8 | // /___/ \ / Vendor : Xilinx 9 | // \ \ \/ Version : 10.1 10 | // \ \ Description : Xilinx Function Simulation Library Component 11 | // / / 32-Deep by 8-bit Wide Multi Port RAM 12 | // /___/ /\ Filename : RAM32M.v 13 | // \ \ / \ Timestamp : 14 | // \___\/\___\ 15 | // 16 | // Revision: 17 | // 03/21/06 - Initial version. 18 | // 01/13/10 - Remove notifier block (CR544157) 19 | // End Revision 20 | 21 | `timescale 1 ps/1 ps 22 | 23 | module RAM32M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE); 24 | 25 | parameter INIT_A = 64'h0000000000000000; 26 | parameter INIT_B = 64'h0000000000000000; 27 | parameter INIT_C = 64'h0000000000000000; 28 | parameter INIT_D = 64'h0000000000000000; 29 | 30 | output [1:0] DOA; 31 | output [1:0] DOB; 32 | output [1:0] DOC; 33 | output [1:0] DOD; 34 | input [4:0] ADDRA; 35 | input [4:0] ADDRB; 36 | input [4:0] ADDRC; 37 | input [4:0] ADDRD; 38 | input [1:0] DIA; 39 | input [1:0] DIB; 40 | input [1:0] DIC; 41 | input [1:0] DID; 42 | input WCLK; 43 | input WE; 44 | 45 | reg [63:0] mem_a, mem_b, mem_c, mem_d; 46 | 47 | initial begin 48 | mem_a = INIT_A; 49 | mem_b = INIT_B; 50 | mem_c = INIT_C; 51 | mem_d = INIT_D; 52 | end 53 | 54 | always @(posedge WCLK) 55 | if (WE) begin 56 | mem_a[2*ADDRD] <= #100 DIA[0]; 57 | mem_a[2*ADDRD + 1] <= #100 DIA[1]; 58 | mem_b[2*ADDRD] <= #100 DIB[0]; 59 | mem_b[2*ADDRD + 1] <= #100 DIB[1]; 60 | mem_c[2*ADDRD] <= #100 DIC[0]; 61 | mem_c[2*ADDRD + 1] <= #100 DIC[1]; 62 | mem_d[2*ADDRD] <= #100 DID[0]; 63 | mem_d[2*ADDRD + 1] <= #100 DID[1]; 64 | end 65 | 66 | assign DOA[0] = mem_a[2*ADDRA]; 67 | assign DOA[1] = mem_a[2*ADDRA + 1]; 68 | assign DOB[0] = mem_b[2*ADDRB]; 69 | assign DOB[1] = mem_b[2*ADDRB + 1]; 70 | assign DOC[0] = mem_c[2*ADDRC]; 71 | assign DOC[1] = mem_c[2*ADDRC + 1]; 72 | assign DOD[0] = mem_d[2*ADDRD]; 73 | assign DOD[1] = mem_d[2*ADDRD + 1]; 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /rtl/offset_add.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /****************************************************************************************** 3 | Copyright (c) 2016 HuiYan Cheah. 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms are permitted provided that 7 | the above copyright notice and this paragraph are duplicated in all such forms 8 | and that any documentation, advertising materials, and other materials related 9 | to such distribution and use acknowledge that the software was developed by 10 | Nanyang Technological University. The name of Nanyang Technological University 11 | may not be used to endorse or promote products derived from this software 12 | without specific prior written permission. THIS SOFTWARE IS PROVIDED ``AS IS'' 13 | AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, 14 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 15 | 16 | * iDEA Soft-Core Processor 17 | * HuiYan Cheah 2016, hycheah1@e.ntu.edu.sg 18 | * School of Computer Engineering 19 | * Nanyang Technological University 20 | * 21 | * This processor is a proof-of-concept of the usability of the DSP48E1 as 22 | * the execution unit of a general-purpose processor. It is not a full-blown processor. 23 | * 24 | * Description: 25 | * Calcutes the address for data memory access for store or load. 26 | * 27 | 28 | ******************************************************************************************/ 29 | `include "defines.v" 30 | 31 | module offset_add( 32 | input rst, 33 | input clk, 34 | input en_i, 35 | input [`dm_addr_width-1:0] data_ra_i, 36 | input [`dm_addr_width-1:0] data_rb_i, 37 | input [`datawidth-1:0] data_rc_i, 38 | output reg [`dm_addr_width-1:0] addr_datamem_o, 39 | output reg [`datawidth-1:0] data_datamem_o 40 | ); 41 | 42 | reg [`dm_addr_width-1:0] addr_datamem; 43 | reg [`datawidth-1:0] data_datamem; 44 | 45 | always@(en_i or data_ra_i or data_rb_i or data_rc_i) 46 | begin 47 | if (en_i) 48 | begin 49 | addr_datamem = data_ra_i + data_rb_i; 50 | data_datamem = data_rc_i; 51 | end 52 | else 53 | begin 54 | addr_datamem = data_ra_i; 55 | data_datamem = data_rc_i; 56 | end 57 | end 58 | 59 | always@ (posedge clk) 60 | begin 61 | if (rst) 62 | begin 63 | addr_datamem_o <= {`dm_addr_width{1'b0}}; 64 | data_datamem_o <= {`datawidth{1'b0}}; 65 | end 66 | else 67 | begin 68 | addr_datamem_o <= addr_datamem; 69 | data_datamem_o <= data_datamem; 70 | end 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /tb/fib_tb_output: -------------------------------------------------------------------------------- 1 | a: 1, b: 2, sum: 3 2 | a: 0, b: 1, sum: 0 3 | a: 1, b: 1, sum: 1 4 | a: 1, b: 2, sum: 2 5 | a: 2, b: 3, sum: 3 6 | a: 3, b: 5, sum: 5 7 | a: 5, b: 8, sum: 8 8 | a: 8, b: 13, sum: 13 9 | a: 13, b: 21, sum: 21 10 | a: 21, b: 34, sum: 34 11 | a: 34, b: 55, sum: 55 12 | a: 55, b: 89, sum: 89 13 | a: 89, b: 144, sum: 144 14 | a: 144, b: 233, sum: 233 15 | a: 233, b: 377, sum: 377 16 | a: 377, b: 610, sum: 610 17 | a: 610, b: 987, sum: 987 18 | a: 987, b: 1597, sum: 1597 19 | a: 1597, b: 2584, sum: 2584 20 | a: 2584, b: 4181, sum: 4181 21 | a: 4181, b: 6765, sum: 6765 22 | a: 6765, b: 10946, sum: 10946 23 | a: 10946, b: 17711, sum: 17711 24 | a: 17711, b: 28657, sum: 28657 25 | a: 28657, b: 46368, sum: 46368 26 | a: 46368, b: 75025, sum: 75025 27 | a: 75025, b: 121393, sum: 121393 28 | a: 121393, b: 196418, sum: 196418 29 | a: 196418, b: 317811, sum: 317811 30 | a: 317811, b: 514229, sum: 514229 31 | a: 514229, b: 832040, sum: 832040 32 | a: 832040, b: 1346269, sum: 1346269 33 | a: 1346269, b: 2178309, sum: 2178309 34 | a: 2178309, b: 3524578, sum: 3524578 35 | a: 3524578, b: 5702887, sum: 5702887 36 | a: 5702887, b: 9227465, sum: 9227465 37 | a: 9227465, b: 14930352, sum: 14930352 38 | a: 14930352, b: 24157817, sum: 24157817 39 | a: 24157817, b: 39088169, sum: 39088169 40 | a: 39088169, b: 63245986, sum: 63245986 41 | a: 63245986, b: 102334155, sum: 102334155 42 | a: 102334155, b: 165580141, sum: 165580141 43 | a: 165580141, b: 267914296, sum: 267914296 44 | a: 267914296, b: 433494437, sum: 433494437 45 | a: 433494437, b: 701408733, sum: 701408733 46 | a: 701408733, b: 1134903170, sum: 1134903170 47 | a: 1134903170, b: 1836311903, sum: 1836311903 48 | a: 1836311903, b: 2971215073, sum: 2971215073 49 | a: 2971215073, b: 512559680, sum: 512559680 50 | a: 512559680, b: 3483774753, sum: 3483774753 51 | a: 3483774753, b: 3996334433, sum: 3996334433 52 | Testbench: Instruction count is 256 53 | Testbench: Clock cycle count is 1414 54 | -------------------------------------------------------------------------------- /simulator/runSimulations.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Bash script to run all benchmark simulations 3 | # To run this script, do: 4 | # $ chmod +x runSimulations.sh 5 | # $ ./runSimulations.sh option 6 | #