├── .gitignore ├── .gitmodules ├── CHANGES.md ├── CMake.in ├── CMakeLists.txt ├── CONTRIBUTING ├── LICENSE ├── MAINTAINERS ├── README.md ├── app ├── CMakeLists.txt ├── wddr_boot │ ├── CMakeLists.txt │ └── main.c └── wddr_main │ ├── CMakeLists.txt │ └── main.c ├── configure ├── dev ├── CMakeLists.txt ├── channel │ └── device.c ├── cmn │ └── device.c ├── ctrl │ └── device.c ├── dfi │ ├── buffer.c │ ├── command.c │ ├── device.c │ └── packet.c ├── dram │ └── device.c ├── fsw │ └── device.c ├── messenger │ └── device.c ├── pll │ └── device.c └── wddr │ ├── CMakeLists.txt │ └── device.c ├── docker └── run.sh ├── drivers ├── CMakeLists.txt ├── ca │ ├── ca_bscan.c │ ├── ca_dp.c │ ├── ca_driver.c │ ├── ca_egress.c │ ├── ca_gearbox.c │ ├── ca_lpde.c │ ├── ca_pi.c │ └── ca_top.c ├── cmn │ ├── cmn_clk.c │ ├── cmn_ibias.c │ ├── cmn_pmon.c │ ├── cmn_rstn.c │ ├── cmn_vref.c │ └── cmn_zqcal.c ├── ctrl │ └── ctrl_clk.c ├── dfi │ ├── dfi_dp.c │ ├── dfi_fifo.c │ ├── dfi_intf.c │ └── dfi_top.c ├── dq │ ├── dq_bscan.c │ ├── dq_dp.c │ ├── dq_driver.c │ ├── dq_egress.c │ ├── dq_gearbox.c │ ├── dq_lpde.c │ ├── dq_pi.c │ ├── dq_receiver.c │ ├── dq_sa.c │ └── dq_top.c ├── fsw │ ├── fsw_csp.c │ └── fsw_ctrl.c ├── pll │ └── driver.c ├── vco │ └── driver.c └── wddr │ ├── CMakeLists.txt │ └── driver.c ├── firmware ├── CMakeLists.txt ├── phy_api.c └── phy_task.c └── include ├── compiler.h ├── dev ├── channel │ └── device.h ├── cmn │ └── device.h ├── ctrl │ └── device.h ├── dfi │ ├── buffer.h │ ├── command.h │ ├── device.h │ ├── intf.h │ └── packet.h ├── dram │ └── device.h ├── fsw │ └── device.h ├── messenger │ ├── device.h │ └── messages_wddr.h ├── pll │ └── device.h ├── vco │ └── device.h └── wddr │ ├── boot_options.h │ ├── device.h │ ├── irq_map.h │ ├── phy_config.h │ └── phy_defs.h ├── drivers ├── ca │ ├── ca_bscan.h │ ├── ca_dp.h │ ├── ca_driver.h │ ├── ca_egress.h │ ├── ca_gearbox.h │ ├── ca_lpde.h │ ├── ca_pi.h │ ├── ca_reg.h │ ├── ca_top.h │ └── driver.h ├── cmn │ ├── cmn_clk.h │ ├── cmn_ibias.h │ ├── cmn_pmon.h │ ├── cmn_reg.h │ ├── cmn_rstn.h │ ├── cmn_vref.h │ ├── cmn_zqcal.h │ └── driver.h ├── ctrl │ ├── ctrl_clk.h │ ├── ctrl_reg.h │ └── driver.h ├── dfi │ ├── dfi_dp.h │ ├── dfi_fifo.h │ ├── dfi_intf.h │ ├── dfi_reg.h │ ├── dfi_ret.h │ ├── dfi_top.h │ ├── dfich_reg.h │ └── driver.h ├── dq │ ├── dq_bscan.h │ ├── dq_dp.h │ ├── dq_driver.h │ ├── dq_egress.h │ ├── dq_gearbox.h │ ├── dq_lpde.h │ ├── dq_pi.h │ ├── dq_receiver.h │ ├── dq_reg.h │ ├── dq_sa.h │ ├── dq_top.h │ └── driver.h ├── fsw │ ├── driver.h │ ├── fsw_csp.h │ ├── fsw_ctrl.h │ └── fsw_reg.h ├── pll │ └── driver.h ├── vco │ └── driver.h └── wddr │ ├── ddr_ca_csr.h │ ├── ddr_cmn_csr.h │ ├── ddr_ctrl_csr.h │ ├── ddr_dfi_csr.h │ ├── ddr_dfich_csr.h │ ├── ddr_dq_csr.h │ ├── ddr_fsw_csr.h │ ├── ddr_mvp_pll_csr.h │ ├── driver.h │ └── memory_map.h ├── error.h ├── firmware ├── firmware.h ├── phy_api.h └── phy_task.h └── table ├── ca └── table.h ├── channel └── table.h ├── cmn └── table.h ├── dfi └── table.h ├── dp └── table.h ├── dq └── table.h ├── dram └── table.h ├── driver └── table.h ├── gearbox ├── rx_table.h ├── table.h └── tx_table.h ├── lpde └── table.h ├── pi ├── rx_table.h ├── table.h └── tx_table.h ├── pll └── table.h ├── pmon └── table.h ├── receiver └── table.h ├── sensamp └── table.h ├── vco └── table.h ├── vref └── table.h ├── wddr ├── table.h ├── table_defs.h └── table_vals.h └── zqcal └── table.h /.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | VERSION 3 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "rtos"] 2 | path = rtos 3 | url = git@github.com:waviousllc/wav-rtos-sw.git 4 | -------------------------------------------------------------------------------- /CHANGES.md: -------------------------------------------------------------------------------- 1 | # Version 1.0.0 2 | - Initial stable release 3 | -------------------------------------------------------------------------------- /CMake.in: -------------------------------------------------------------------------------- 1 | # Setup Toplevel directory 2 | set(WAV_WDDR_TOP_LEVEL ${CMAKE_CURRENT_LIST_DIR}) 3 | 4 | set(RTOS_HEAP_ALLOC_SCHEME "4") 5 | include(${WAV_WDDR_TOP_LEVEL}/rtos/CMake.in) 6 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) 2 | project("WAV-LPDDR-SW" C ASM) 3 | cmake_minimum_required(VERSION 3.13) 4 | 5 | # Set the output folder where your program will be created 6 | set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/build) 7 | set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/build) 8 | set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) 9 | 10 | # Make sure everything is built for correct architecture 11 | set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS}") 12 | set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG") 13 | 14 | # Build configuration 15 | include(${CMAKE_CURRENT_LIST_DIR}/CMake.in) 16 | 17 | # Build versioning 18 | set(VERSION_UPDATE_FROM_GIT TRUE) 19 | find_package(BuildInfo REQUIRED) 20 | 21 | add_compile_options( 22 | -O2 23 | -g 24 | -Wall 25 | -Wextra 26 | -Werror 27 | -Wno-unused-parameter 28 | -fdata-sections 29 | -ffunction-sections 30 | -std=c11 31 | ) 32 | endif() 33 | 34 | ################################################################################ 35 | ## CONFIGURATIONS 36 | ################################################################################ 37 | # Set flag for skipping PLL calibration at boot 38 | set(CONFIG_CALIBRATE_PLL true CACHE BOOL "Flag to indicate if PLL calibration is performed at boot.") 39 | message("PLL CAL: ${CONFIG_CALIBRATE_PLL}") 40 | 41 | # Set flag for skipping ZQCAL calibration at boot 42 | set(CONFIG_CALIBRATE_ZQCAL true CACHE BOOL "Flag to indicate if ZQCAL calibration is performed at boot.") 43 | message("ZQCAL CAL: ${CONFIG_CALIBRATE_ZQCAL}") 44 | 45 | # Set flag for skipping Sense Amp calibration at boot 46 | set(CONFIG_CALIBRATE_SA true CACHE BOOL "Flag to indicate if SA calibration is performed at boot.") 47 | message("SA CAL: ${CONFIG_CALIBRATE_SA}") 48 | 49 | # Set flag for skipping DRAM training at boot 50 | set(CONFIG_DRAM_TRAIN false CACHE BOOL "Flag to indicate if DRAM training is performed at boot.") 51 | message("DRAM_TRAIN: ${CONFIG_DRAM_TRAIN}") 52 | 53 | # Set flag for performing periodic calibration 54 | set(CONFIG_CAL_PERIODIC false CACHE BOOL "Flag to indicate if periodic calibraiton is performed.") 55 | message("PERIODIC CAL: ${CONFIG_CAL_PERIODIC}") 56 | 57 | ################################################################################ 58 | ## SOURCE DIRECTORIES 59 | ################################################################################/ 60 | # Build subdirectories 61 | add_subdirectory(${WAV_RTOS_TOP_LEVEL}) 62 | add_subdirectory(drivers) 63 | add_subdirectory(dev) 64 | add_subdirectory(firmware) 65 | add_subdirectory(app) 66 | -------------------------------------------------------------------------------- /CONTRIBUTING: -------------------------------------------------------------------------------- 1 | Contributing 2 | ============ 3 | 4 | When contributing to this repository, please begin all interactions by opening 5 | an issue at: 6 | 7 | https://github.com/waviousllc/wav-lpddr-sw/issues 8 | 9 | Please follow the guidelines below for contributing to the 'WAV-LPDDR-SW' 10 | project. 11 | 12 | Pull Request 13 | ============ 14 | 15 | 1. Create a feature branch with format 'dev// branched 16 | from main-staging 17 | 2. Make changes on the feature branch 18 | 3. Push changes to remote end 19 | 4. Open a Pull Request for merging 'dev//' branch into 20 | main-staging 21 | 5. Request reviews from those in 'MAINTAINERS' file 22 | 6. As changes are requested, modify with 'git comit --amend' and force push back 23 | to feature branch 24 | 7. Upon successful review, select 'Rebase and Merge' option to rebase feature 25 | changes into main-staging branch 26 | 27 | Commit Format 28 | ============= 29 | 30 | Commits follow the format below: 31 | 32 | Line 1: [Short Title for Commit] 33 | Line 2: 34 | Line 3: Fixes: 35 | Line 4-N: - ; Prefix with "-" 36 | Line N+1: 37 | Line N+2: Features: 38 | Line N+3-M: - ; Prefix with "-" 39 | -------------------------------------------------------------------------------- /MAINTAINERS: -------------------------------------------------------------------------------- 1 | About 2 | ===== 3 | 4 | This file contains information about people who are responsible for 5 | this project and its contents. The person's name, github username, and email 6 | address are listed. 7 | 8 | Initial contributions to this project were made by those listed under 9 | the 'Credits' section of this file. Please refer to 'Current Maintainers' 10 | section for those actively contributing to this project. 11 | 12 | All names are listed in alphabetical order by last name. 13 | 14 | To report problems with WAV-LPDDR-SW or for general questions, 15 | please file an issue at: 16 | 17 | https://github.com/waviousllc/wav-lpddr-sw/issues 18 | 19 | Maintainers 20 | =========== 21 | 22 | Current Maintainers 23 | 24 | John Basista @wavious-jbasista 25 | Renatas Jakushokas @jakushok 26 | William Patty @wavious-wpatty 27 | 28 | 29 | Credits 30 | 31 | Tanya Vanessa Abaya - 32 | John Basista @wavious-jbasista 33 | Steven Bridges @lsteveol 34 | Sushma Chilukuri @sushmachilukuri 35 | Mike Clovis @pmclovis 36 | Hanan Cohen @hannanc 37 | Sasha Hadzibabic - 38 | Renatas Jakushokas @jakushok 39 | William Patty @wavious-wpatty 40 | -------------------------------------------------------------------------------- /app/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(wddr_boot) 2 | add_subdirectory(wddr_main) 3 | -------------------------------------------------------------------------------- /app/wddr_boot/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") 2 | project("wddr_boot" C ASM) 3 | 4 | # Directories 5 | set(LINKER_SCRIPT "${WAV_RTOS_TOP_LEVEL}/bsp/${CONFIG_TARGET_BOARD}/metal.freertos.lds") 6 | set(APP_DIR "${CMAKE_CURRENT_LIST_DIR}") 7 | 8 | # Source Files 9 | set(SOURCE_FILES 10 | ${APP_DIR}/main.c 11 | ) 12 | 13 | add_executable( 14 | ${PROJECT_NAME} 15 | ${SOURCE_FILES} 16 | ) 17 | 18 | target_compile_options( 19 | ${PROJECT_NAME} 20 | PRIVATE 21 | -Wno-missing-field-initializers 22 | ) 23 | 24 | target_include_directories( 25 | ${PROJECT_NAME} 26 | PRIVATE 27 | ${APP_DIR} 28 | ${WAV_BUILD_TOP_LEVEL}/include 29 | ) 30 | 31 | target_compile_definitions( 32 | ${PROJECT_NAME} 33 | PRIVATE 34 | -DGIT_SHA=\"${VERSION_GIT_SHA}\" 35 | -DGIT_DIRTY=${VERSION_DIRTY} 36 | -DGIT_AHEAD=${VERSION_AHEAD} 37 | -DFW_VERSION_MAJOR=${VERSION_MAJOR} 38 | -DFW_VERSION_MINOR=${VERSION_MINOR} 39 | -DFW_VERSION_PATCH=${VERSION_PATCH} 40 | ) 41 | 42 | target_link_libraries( 43 | ${PROJECT_NAME} 44 | phy_firmware 45 | ) 46 | 47 | target_link_options( 48 | ${PROJECT_NAME} 49 | PUBLIC 50 | -T ${LINKER_SCRIPT} 51 | -Wl,--defsym,__stack_size=0x200 52 | -Wl,--defsym,__heap_size=0x0 53 | -Wl,--build-id 54 | ) 55 | 56 | bsp_post_build(${PROJECT_NAME}) 57 | -------------------------------------------------------------------------------- /app/wddr_main/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") 2 | project("wddr_main" C ASM) 3 | 4 | # Directories 5 | set(LINKER_SCRIPT "${WAV_RTOS_TOP_LEVEL}/bsp/${CONFIG_TARGET_BOARD}/metal.freertos.lds") 6 | set(APP_DIR "${CMAKE_CURRENT_LIST_DIR}") 7 | 8 | # Source Files 9 | set(SOURCE_FILES 10 | ${APP_DIR}/main.c 11 | ) 12 | 13 | add_executable( 14 | ${PROJECT_NAME} 15 | ${SOURCE_FILES} 16 | ) 17 | 18 | target_compile_options( 19 | ${PROJECT_NAME} 20 | PRIVATE 21 | -Wno-missing-field-initializers 22 | ) 23 | 24 | target_include_directories( 25 | ${PROJECT_NAME} 26 | PRIVATE 27 | ${APP_DIR} 28 | ${WAV_BUILD_TOP_LEVEL}/include 29 | ) 30 | 31 | target_compile_definitions( 32 | ${PROJECT_NAME} 33 | PRIVATE 34 | -DGIT_SHA=\"${VERSION_GIT_SHA}\" 35 | -DGIT_DIRTY=${VERSION_DIRTY} 36 | -DGIT_AHEAD=${VERSION_AHEAD} 37 | -DFW_VERSION_MAJOR=${VERSION_MAJOR} 38 | -DFW_VERSION_MINOR=${VERSION_MINOR} 39 | -DFW_VERSION_PATCH=${VERSION_PATCH} 40 | ) 41 | 42 | target_link_libraries( 43 | ${PROJECT_NAME} 44 | phy_firmware 45 | ) 46 | 47 | target_link_options( 48 | ${PROJECT_NAME} 49 | PUBLIC 50 | -T ${LINKER_SCRIPT} 51 | -Wl,--defsym,__stack_size=0x200 52 | -Wl,--defsym,__heap_size=0x0 53 | -Wl,--build-id 54 | ) 55 | 56 | bsp_post_build(${PROJECT_NAME}) 57 | -------------------------------------------------------------------------------- /configure: -------------------------------------------------------------------------------- 1 | #! /bin/sh 2 | # Configures build environment for appropriate target architecture 3 | 4 | # Definitions 5 | BUILD_DIR="build" 6 | BUILD_TYPE="" 7 | CONFIG_CAL_PLL="true" 8 | CONFIG_CAL_ZQCAL="true" 9 | CONFIG_CAL_SA="true" 10 | CONFIG_DRAM_TRAIN="true" 11 | CONFIG_CAL_PERIODIC="true" 12 | 13 | # Common build prep function 14 | init_build_common() { 15 | mkdir -p ${BUILD_DIR} 16 | } 17 | 18 | init_lpddr() { 19 | cd ${BUILD_DIR} 20 | cmake .. -DCMAKE_TOOLCHAIN_FILE="../rtos/toolchain/riscv.toolchain" \ 21 | -DCONFIG_SRC_ARCH="riscv" \ 22 | -DCONFIG_TARGET_ARCH="riscv32" \ 23 | -DCONFIG_TARGET_BOARD="wavious-mcu" \ 24 | -DCONFIG_CALIBRATE_PLL=${CONFIG_CAL_PLL} \ 25 | -DCONFIG_CALIBRATE_ZQCAL=${CONFIG_CAL_ZQCAL} \ 26 | -DCONFIG_CALIBRATE_SA=${CONFIG_CAL_SA} \ 27 | -DCONFIG_DRAM_TRAIN=${CONFIG_DRAM_TRAIN} \ 28 | -DCONFIG_CAL_PERIODIC=${CONFIG_CAL_PERIODIC} \ 29 | -DCMAKE_BUILD_TYPE=${BUILD_TYPE} 30 | cd .. 31 | } 32 | 33 | print_help() { 34 | echo "Usage: configure [OPTIONS]\n" 35 | echo "This program configures CMAKE for wavious lpddr project\n" 36 | echo "Options:" 37 | echo "-t, --build_type " 38 | echo "--no-pll-cal (disables PLL calibration)" 39 | echo "--no-zqcal-cal (disables ZQCAL calibration)" 40 | echo "--no-sa-cal (disables SA calibration)" 41 | echo "--dram-train (enables DRAM training at boot)" 42 | echo "--periodic-cal (enables periodic calibration)" 43 | } 44 | 45 | PARAMS="" 46 | while [ $# -gt 0 ]; do 47 | case "$1" in 48 | -t | --build_type) 49 | BUILD_TYPE=$2 50 | shift 2 51 | ;; 52 | --no-pll-cal) 53 | CONFIG_CAL_PLL="false" 54 | shift 1 55 | ;; 56 | --no-zqcal-cal) 57 | CONFIG_CAL_ZQCAL="false" 58 | shift 1 59 | ;; 60 | --no-sa-cal) 61 | CONFIG_CAL_SA="false" 62 | shift 1 63 | ;; 64 | --dram-train) 65 | CONFIG_DRAM_TRAIN="true" 66 | ;; 67 | --periodic-cal) 68 | CONFIG_CAL_PERIODIC="true" 69 | shift 1 70 | ;; 71 | -h | --help) 72 | print_help 73 | exit 74 | ;; 75 | --) # end argument parsing 76 | shift 77 | break 78 | ;; 79 | -*|--*=) # unsupported flags 80 | echo "Error: Unsupported flag $1" >&2 81 | exit 1 82 | ;; 83 | *) # preserve positional arguments 84 | PARAMS="$PARAMS $1" 85 | shift 86 | ;; 87 | esac 88 | done 89 | # set positional arguments in their proper place 90 | eval set -- "$PARAMS" 91 | 92 | init_build_common 93 | init_lpddr 94 | -------------------------------------------------------------------------------- /dev/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(wddr) 2 | -------------------------------------------------------------------------------- /dev/cmn/device.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | #define ZQCAL_PCAL_CODE_MIN (0) 10 | #define ZQCAL_PCAL_CODE_MAX (0x3f) 11 | #define ZQCAL_NCAL_CODE_MIN (0) 12 | #define ZQCAL_NCAL_CODE_MAX (0x1f) 13 | 14 | void cmn_init(cmn_dev_t *cmn_dev, uint32_t base) 15 | { 16 | cmn_dev->cmn_reg = (cmn_reg_t *)(base + WDDR_MEMORY_MAP_CMN); 17 | } 18 | 19 | void cmn_enable(cmn_dev_t *cmn_dev) 20 | { 21 | cmn_vref_set_mode_enable(cmn_dev, WDDR_MSR_0); 22 | cmn_vref_set_mode_enable(cmn_dev, WDDR_MSR_1); 23 | cmn_ibias_enable(cmn_dev); 24 | } 25 | 26 | void cmn_ibias_enable(cmn_dev_t *cmn_dev) 27 | { 28 | cmn_ibias_set_state_reg_if(cmn_dev->cmn_reg, IBIAS_STATE_ENABLE); 29 | } 30 | 31 | void cmn_ibias_disable(cmn_dev_t *cmn_dev) 32 | { 33 | cmn_ibias_set_state_reg_if(cmn_dev->cmn_reg, IBIAS_STATE_DISABLE); 34 | } 35 | 36 | void cmn_pmon_run(cmn_dev_t *cmn_dev, uint32_t *count) 37 | { 38 | cmn_pmon_set_state_reg_if(cmn_dev->cmn_reg, PMON_STATE_ENABLED); 39 | cmn_pmon_get_status_count_reg_if(cmn_dev->cmn_reg, count); 40 | cmn_pmon_set_state_reg_if(cmn_dev->cmn_reg, PMON_STATE_DISABLED); 41 | } 42 | 43 | void cmn_pmon_configure(cmn_dev_t *cmn_dev, pmon_cfg_t *cfg) 44 | { 45 | cmn_pmon_configure_reg_if(cmn_dev->cmn_reg, cfg->refclk_count, cfg->init_wait); 46 | } 47 | 48 | void cmn_vref_set_mode_enable(cmn_dev_t *cmn_dev, wddr_msr_t msr) 49 | { 50 | cmn_vref_set_state_reg_if(cmn_dev->cmn_reg, msr, VREF_STATE_ENABLED); 51 | } 52 | 53 | void cmn_vref_set_mode_disable(cmn_dev_t *cmn_dev, wddr_msr_t msr) 54 | { 55 | cmn_vref_set_state_reg_if(cmn_dev->cmn_reg, msr, VREF_STATE_DISABLED); 56 | } 57 | 58 | void cmn_vref_set_mode_hiz(cmn_dev_t *cmn_dev, wddr_msr_t msr) 59 | { 60 | cmn_vref_set_state_reg_if(cmn_dev->cmn_reg, msr, VREF_STATE_HIZ); 61 | } 62 | 63 | static void zqcal_calibrate_common(cmn_dev_t *cmn_dev, 64 | zqcal_mode_t mode, 65 | uint8_t max_code, 66 | uint8_t *code) 67 | { 68 | uint8_t zqval; 69 | uint8_t tmp_code; 70 | 71 | tmp_code = *code; 72 | cmn_zqcal_set_mode_reg_if(cmn_dev->cmn_reg, mode); 73 | do 74 | { 75 | cmn_zqcal_set_code_reg_if(cmn_dev->cmn_reg, mode, tmp_code); 76 | // TODO: need wait for it to settle? 77 | cmn_zqcal_get_output_reg_if(cmn_dev->cmn_reg, &zqval); 78 | *code = tmp_code++; 79 | } while (zqval && tmp_code <= max_code); 80 | } 81 | 82 | static wddr_return_t zqcal_calibrate_voh(cmn_dev_t *cmn_dev, 83 | zqcal_voh_t voh, 84 | zqcal_cfg_t *cfg) 85 | { 86 | uint8_t n_code = ZQCAL_NCAL_CODE_MIN; 87 | uint8_t p_code = ZQCAL_PCAL_CODE_MIN; 88 | 89 | cmn_zqcal_set_voh_reg_if(cmn_dev->cmn_reg, voh); 90 | 91 | zqcal_calibrate_common(cmn_dev, 92 | ZQCAL_MODE_PULL_DOWN, 93 | ZQCAL_NCAL_CODE_MAX, 94 | &n_code); 95 | 96 | if (n_code == ZQCAL_NCAL_CODE_MIN) 97 | { 98 | return WDDR_ERROR_ZQCAL_NCAL_AT_MIN; 99 | } 100 | 101 | if (n_code == ZQCAL_NCAL_CODE_MAX) 102 | { 103 | return WDDR_ERROR_ZQCAL_NCAL_AT_MAX; 104 | } 105 | 106 | zqcal_calibrate_common(cmn_dev, 107 | ZQCAL_MODE_PULL_UP, 108 | ZQCAL_PCAL_CODE_MAX, 109 | &p_code); 110 | 111 | if (p_code == ZQCAL_PCAL_CODE_MIN) 112 | { 113 | return WDDR_ERROR_ZQCAL_PCAL_AT_MIN; 114 | } 115 | 116 | if (p_code == ZQCAL_PCAL_CODE_MAX) 117 | { 118 | return WDDR_ERROR_ZQCAL_PCAL_AT_MAX; 119 | } 120 | 121 | cfg->code[voh][ZQCAL_N_CAL] = n_code; 122 | cfg->code[voh][ZQCAL_P_CAL] = p_code; 123 | return WDDR_SUCCESS; 124 | } 125 | 126 | wddr_return_t cmn_zqcal_calibrate(cmn_dev_t *cmn_dev, zqcal_cfg_t *cfg) 127 | { 128 | wddr_return_t ret; 129 | cmn_zqcal_set_state_reg_if(cmn_dev->cmn_reg, ZQCAL_STATE_ENABLED); 130 | for (uint8_t voh = ZQCAL_VOH_0P5; voh < ZQCAL_VOH_NUM; voh++) 131 | { 132 | ret = zqcal_calibrate_voh(cmn_dev, (zqcal_voh_t) voh, cfg); 133 | if (ret) 134 | { 135 | break; 136 | } 137 | } 138 | cmn_zqcal_set_state_reg_if(cmn_dev->cmn_reg, ZQCAL_STATE_DISABLED); 139 | return ret; 140 | } 141 | -------------------------------------------------------------------------------- /dev/ctrl/device.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void ctrl_init(ctrl_dev_t *ctrl_dev, uint32_t base) 10 | { 11 | ctrl_dev->ctrl_reg = (ctrl_reg_t *)(base + WDDR_MEMORY_MAP_CTRL); 12 | } 13 | -------------------------------------------------------------------------------- /dev/dfi/buffer.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | /** 10 | * @brief DFI Buffer Write Packets 11 | * 12 | * @details Writes all packets in given TX Packet Buffer to the IG FIFO. 13 | * 14 | * @param[in] dfi pointer to DFI device. 15 | * @param[in] packet_list pointer to list of packets to write. 16 | * 17 | * @return returns whether all packets were written to IG FIFO. 18 | * @retval DFI_SUCCESS if all packets successfully written. 19 | * @retval DFI_ERROR_FIFO_FULL if IG FIFO is full before all 20 | * packets have been written. 21 | */ 22 | static dfi_return_t dfi_buffer_write_packets(dfi_dev_t *dfi, 23 | const List_t *packet_list); 24 | 25 | void dfi_buffer_enable(dfi_dev_t *dfi) 26 | { 27 | dfi_fifo_enable_clock_reg_if(dfi->dfich_reg); 28 | } 29 | 30 | void dfi_buffer_disable(dfi_dev_t *dfi) 31 | { 32 | dfi_fifo_set_mode_reg_if(dfi->dfich_reg, false); 33 | } 34 | 35 | dfi_return_t dfi_buffer_fill_packets(dfi_dev_t *dfi, 36 | const List_t *packet_list) 37 | { 38 | dfi_buffer_enable(dfi); 39 | return dfi_buffer_write_packets(dfi, packet_list); 40 | } 41 | 42 | void dfi_buffer_send_packets(dfi_dev_t *dfi, bool should_block) 43 | { 44 | dfi_fifo_send_packets_reg_if(dfi->dfich_reg); 45 | } 46 | 47 | dfi_return_t dfi_buffer_fill_and_send_packets(dfi_dev_t *dfi, 48 | const List_t *packet_list) 49 | { 50 | dfi_return_t ret; 51 | 52 | ret = dfi_buffer_fill_packets(dfi, packet_list); 53 | 54 | if (ret != DFI_SUCCESS) 55 | { 56 | return ret; 57 | } 58 | 59 | dfi_buffer_send_packets(dfi, true); 60 | return DFI_SUCCESS; 61 | } 62 | 63 | static dfi_return_t dfi_buffer_write_packets(dfi_dev_t *dfi, 64 | const List_t *packet_list) 65 | { 66 | dfi_return_t ret = DFI_SUCCESS; 67 | const packet_item_t *packet_item; 68 | const ListItem_t *next; 69 | 70 | // Should have at least one packet 71 | if (listLIST_IS_EMPTY(packet_list)) 72 | { 73 | return DFI_ERROR; 74 | } 75 | 76 | next = listGET_HEAD_ENTRY(packet_list); 77 | 78 | /** 79 | * Send all packets except the last packet. 80 | * The last packet is empty except for timestamp. 81 | */ 82 | do 83 | { 84 | packet_item = (packet_item_t *) listGET_LIST_ITEM_OWNER(next); 85 | next = listGET_NEXT(next); 86 | ret = dfi_fifo_write_ig_reg_if(dfi->dfich_reg, packet_item->packet.raw_data); 87 | } while (next != listGET_END_MARKER(packet_list) && ret == DFI_SUCCESS); 88 | return ret; 89 | } 90 | 91 | dfi_return_t dfi_buffer_read_packets(dfi_dev_t *dfi, 92 | dfi_rx_packet_buffer_t *rx_buffer, 93 | uint8_t num_packets) 94 | { 95 | dfi_return_t ret; 96 | uint8_t nn = 0; 97 | 98 | if (num_packets > DFI_FIFO_DEPTH) 99 | { 100 | return DFI_ERROR; 101 | } 102 | 103 | do 104 | { 105 | 106 | ret = dfi_fifo_read_eg_reg_if(dfi->dfich_reg, rx_buffer->buffer[nn].raw_data); 107 | } while(++nn < num_packets && ret == DFI_SUCCESS); 108 | return ret; 109 | } 110 | -------------------------------------------------------------------------------- /dev/messenger/device.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | /* Kernel includes. */ 8 | #include 9 | 10 | /* LPDDR includes. */ 11 | #include 12 | #include 13 | #include 14 | #include 15 | 16 | /** 17 | * @brief Messenger Validate Register Interface 18 | * 19 | * @details Register Interface function for validating a message from the MCU. 20 | * 21 | * @param[in] dev generic pointer to messenger device. 22 | * @param[out] buff pointer to where to store data. 23 | * @param[in] len amount of data to send. 24 | * 25 | * @return returns if message is valid. 26 | * @retval true if message is valid. 27 | * @retval false otherwise. 28 | */ 29 | static bool wddr_messenger_validate(void *dev, void *buff, size_t len); 30 | 31 | void wddr_messenger_init(wddr_message_interface_t *messenger) 32 | { 33 | xMessengerInterfaceRegisterPhyInterface((void *) messenger, 34 | MEMORY_MAP_WAV_MCU_INTF, 35 | messenger_send_reg_if, 36 | messenger_receive_reg_if, 37 | wddr_messenger_validate); 38 | 39 | messenger_init_reg_if(messenger, MEMORY_MAP_WAV_MCU_INTF, MCU_FAST_IRQ_HOST2PHY_REQ, MCU_FAST_IRQ_PHY2HOST_ACK); 40 | } 41 | 42 | void wddr_messenger_send(wddr_message_interface_t *messenger, Message_t *message) 43 | { 44 | xSendMessage(messenger->address, message); 45 | } 46 | 47 | bool wddr_messenger_receive(wddr_message_interface_t *messenger, Message_t *message) 48 | { 49 | return (xReceiveMessage(messenger->address, message) == pdTRUE); 50 | } 51 | 52 | static bool wddr_messenger_validate(void *dev, void *buff, size_t len) 53 | { 54 | if (messenger_validate_reg_if(dev, buff, len)) 55 | { 56 | return true; 57 | } 58 | 59 | Message_t *msg = (Message_t *) buff; 60 | 61 | switch(msg->id) 62 | { 63 | case MESSAGE_WDDR_FREQ_PREP_REQ: 64 | case MESSAGE_WDDR_FREQ_PREP_RESP: 65 | return true; 66 | default: 67 | break; 68 | } 69 | 70 | return false; 71 | } 72 | -------------------------------------------------------------------------------- /dev/wddr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | FILE( 2 | GLOB_RECURSE 3 | WDDR_DEV_SOURCES 4 | ${WAV_WDDR_TOP_LEVEL}/dev/*/*.c 5 | ) 6 | 7 | set( 8 | INCLUDE 9 | ${WAV_WDDR_TOP_LEVEL}/include/dev/ 10 | ) 11 | 12 | add_library( 13 | wddr 14 | STATIC 15 | ${WDDR_DEV_SOURCES} 16 | ) 17 | 18 | target_include_directories( 19 | wddr 20 | PUBLIC 21 | ${INCLUDE} 22 | ) 23 | 24 | add_library( 25 | wddr_ext 26 | INTERFACE 27 | ) 28 | 29 | target_link_libraries( 30 | wddr 31 | wddr_driver 32 | wddr_ext 33 | ) 34 | -------------------------------------------------------------------------------- /docker/run.sh: -------------------------------------------------------------------------------- 1 | DOCKER_NAME=$1 2 | if [[ -z `docker ps -q -f name=${DOCKER_NAME}-${USER}` ]] ; then 3 | docker run \ 4 | --volume ${PWD}:/usr/local/build/src/ \ 5 | --rm --name ${DOCKER_NAME}-${USER} -it \ 6 | ${DOCKER_NAME}:latest bash 7 | else 8 | docker exec -it ${DOCKER_NAME}-${USER} bash 9 | fi 10 | -------------------------------------------------------------------------------- /drivers/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(wddr) 2 | -------------------------------------------------------------------------------- /drivers/ca/ca_bscan.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | 8 | /******************************************************************************* 9 | ** CA 10 | *******************************************************************************/ 11 | void ca_dq_bscan_get_status_reg_if(ca_reg_t *ca_reg, uint8_t *status) 12 | { 13 | *status = ca_reg->DDR_CA_DQ_RX_BSCAN_STA; 14 | } 15 | 16 | /******************************************************************************* 17 | ** CK 18 | *******************************************************************************/ 19 | void ca_dqs_bscan_get_status_reg_if(ca_reg_t *ca_reg, uint8_t *status) 20 | { 21 | *status = ca_reg->DDR_CA_DQS_RX_BSCAN_STA; 22 | } 23 | -------------------------------------------------------------------------------- /drivers/ca/ca_egress.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | #include 9 | 10 | /******************************************************************************* 11 | ** CA 12 | *******************************************************************************/ 13 | void ca_dq_egress_ana_set_mode_reg_if(ca_reg_t *ca_reg, 14 | wddr_msr_t msr, 15 | uint8_t bit, 16 | egress_ana_mode_t mode) 17 | { 18 | configASSERT(bit < WDDR_PHY_CA_SLICE_NUM); 19 | ca_reg->DDR_CA_DQ_TX_EGRESS_ANA_CFG[msr][bit] = mode; 20 | } 21 | 22 | void ca_dq_egress_dig_set_mode_reg_if(ca_reg_t *ca_reg, 23 | wddr_msr_t msr, 24 | uint8_t bit, 25 | egress_dig_mode_t mode) 26 | { 27 | configASSERT(bit < WDDR_PHY_CA_SLICE_NUM); 28 | ca_reg->DDR_CA_DQ_TX_EGRESS_DIG_CFG[msr][bit] = mode; 29 | } 30 | 31 | /******************************************************************************* 32 | ** CK 33 | *******************************************************************************/ 34 | void ca_dqs_egress_ana_set_mode_reg_if(ca_reg_t *ca_reg, 35 | wddr_msr_t msr, 36 | uint8_t bit, 37 | egress_ana_mode_t mode) 38 | { 39 | configASSERT(bit < WDDR_PHY_CK_SLICE_NUM); 40 | ca_reg->DDR_CA_DQS_TX_EGRESS_ANA_CFG[msr][bit] = mode; 41 | } 42 | 43 | void ca_dqs_egress_dig_set_mode_reg_if(ca_reg_t *ca_reg, 44 | wddr_msr_t msr, 45 | uint8_t bit, 46 | egress_dig_mode_t mode) 47 | { 48 | configASSERT(bit < WDDR_PHY_CK_SLICE_NUM); 49 | ca_reg->DDR_CA_DQS_TX_EGRESS_DIG_CFG[msr][bit] = mode; 50 | 51 | } 52 | -------------------------------------------------------------------------------- /drivers/ca/ca_gearbox.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | /******************************************************************************* 10 | ** CA 11 | *******************************************************************************/ 12 | void ca_dq_rx_gb_set_mode_reg_if(ca_reg_t *ca_reg, 13 | wddr_msr_t msr, 14 | const rx_gb_cfg_t *cfg) 15 | { 16 | uint32_t reg_val = ca_reg->DDR_CA_DQ_RX_CFG[msr]; 17 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQ_RX_M0_CFG_RGB_MODE, cfg->data_mode); 18 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQ_RX_M0_CFG_FGB_MODE, cfg->fifo_mode); 19 | ca_reg->DDR_CA_DQ_RX_CFG[msr] = reg_val; 20 | } 21 | 22 | /******************************************************************************* 23 | ** CK 24 | *******************************************************************************/ 25 | void ca_dqs_rx_gb_set_mode_reg_if(ca_reg_t *ca_reg, 26 | wddr_msr_t msr, 27 | const rx_gb_cfg_t *cfg) 28 | { 29 | uint32_t reg_val = ca_reg->DDR_CA_DQS_RX_CFG[msr]; 30 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_RX_M0_CFG_RGB_MODE, cfg->data_mode); 31 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_RX_M0_CFG_FGB_MODE, cfg->fifo_mode); 32 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_RX_M0_CFG_WCK_MODE, cfg->wck_mode); 33 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_RX_M0_CFG_PRE_FILTER_SEL, cfg->pre_filter_sel); 34 | ca_reg->DDR_CA_DQS_RX_CFG[msr] = reg_val; 35 | } 36 | 37 | void ca_dqs_tx_gb_set_mode_reg_if(ca_reg_t *ca_reg, 38 | wddr_msr_t msr, 39 | const tx_gb_cfg_t *cfg) 40 | { 41 | uint32_t reg_val = ca_reg->DDR_CA_DQS_TX_CFG[msr]; 42 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_TX_M0_CFG_TGB_MODE, cfg->data_mode); 43 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_TX_M0_CFG_WGB_MODE, cfg->write_mode); 44 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_TX_M0_CFG_CK2WCK_RATIO, cfg->ck2wck_ratio); 45 | ca_reg->DDR_CA_DQS_TX_CFG[msr] = reg_val; 46 | } 47 | -------------------------------------------------------------------------------- /drivers/ca/ca_lpde.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | #include 9 | 10 | /******************************************************************************* 11 | ** CA 12 | *******************************************************************************/ 13 | void ca_dq_lpde_set_cfg_reg_if(ca_reg_t *ca_reg, 14 | wddr_msr_t msr, 15 | wddr_rank_t rank, 16 | uint8_t bit, 17 | bool enable, 18 | uint32_t cfg) 19 | { 20 | uint32_t reg_val = cfg; 21 | configASSERT(bit < WDDR_PHY_CA_SLICE_NUM); 22 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQ_TX_LPDE_M0_R0_CFG_0_EN, enable); 23 | ca_reg->DDR_CA_DQ_TX_LPDE_CFG[msr][rank][bit] = cfg; 24 | } 25 | 26 | /******************************************************************************* 27 | ** CK 28 | *******************************************************************************/ 29 | void ca_dqs_lpde_set_cfg_reg_if(ca_reg_t *ca_reg, 30 | wddr_msr_t msr, 31 | wddr_rank_t rank, 32 | uint8_t bit, 33 | bool enable, 34 | uint32_t cfg) 35 | { 36 | uint32_t reg_val = cfg; 37 | configASSERT(bit < WDDR_PHY_CK_TXRX_SLICE_NUM); 38 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_TX_LPDE_M0_R0_CFG_0_EN, enable); 39 | ca_reg->DDR_CA_DQS_TX_LPDE_CFG[msr][rank][bit] = cfg; 40 | } 41 | 42 | void ca_dqs_lpde_rx_sdr_set_cfg_reg_if(ca_reg_t *ca_reg, 43 | wddr_msr_t msr, 44 | wddr_rank_t rank, 45 | bool enable, 46 | uint32_t cfg) 47 | { 48 | uint32_t reg_val = cfg; 49 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_DQS_RX_SDR_LPDE_M0_R0_CFG_EN, enable); 50 | ca_reg->DDR_CA_DQS_RX_SDR_LPDE_CFG[msr][rank] = cfg; 51 | } 52 | -------------------------------------------------------------------------------- /drivers/ca/ca_top.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void ca_top_set_chip_select_reg_if(ca_reg_t *ca_reg, 10 | wddr_rank_t rank_sel, 11 | bool override) 12 | { 13 | uint32_t reg_val = ca_reg->DDR_CA_TOP_CFG; 14 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_TOP_CFG_WCS_SW_OVR_VAL, rank_sel); 15 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_TOP_CFG_RCS_SW_OVR_VAL, rank_sel); 16 | ca_reg->DDR_CA_TOP_CFG = reg_val; 17 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_TOP_CFG_WCS_SW_OVR, override); 18 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_TOP_CFG_RCS_SW_OVR, override); 19 | ca_reg->DDR_CA_TOP_CFG = reg_val; 20 | } 21 | 22 | void ca_top_clear_fifo_reg_if(ca_reg_t *ca_reg) 23 | { 24 | uint32_t reg_val = ca_reg->DDR_CA_TOP_CFG; 25 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_TOP_CFG_FIFO_CLR, 0x1); 26 | ca_reg->DDR_CA_TOP_CFG = reg_val; 27 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CA_TOP_CFG_FIFO_CLR, 0x0); 28 | ca_reg->DDR_CA_TOP_CFG = reg_val; 29 | } 30 | 31 | void ca_top_get_chip_select_status_reg_if(ca_reg_t *ca_reg, 32 | uint8_t *wcs, 33 | uint8_t *rcs) 34 | { 35 | uint32_t reg_val = ca_reg->DDR_CA_TOP_STA; 36 | *wcs = GET_REG_FIELD(reg_val, DDR_CA_TOP_STA_WCS); 37 | *rcs = GET_REG_FIELD(reg_val, DDR_CA_TOP_STA_RCS); 38 | } 39 | -------------------------------------------------------------------------------- /drivers/cmn/cmn_clk.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void cmn_clk_ctrl_set_pll0_div_clk_rst_reg_if(cmn_reg_t *cmn_reg, bool enable) 10 | { 11 | uint32_t reg_val = cmn_reg->DDR_CMN_CLK_CTRL_CFG; 12 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_CLK_CTRL_CFG_PLL0_DIV_CLK_RST, enable); 13 | cmn_reg->DDR_CMN_CLK_CTRL_CFG = reg_val; 14 | } 15 | 16 | void cmn_clk_ctrl_set_gfcm_en_reg_if(cmn_reg_t *cmn_reg, bool enable) 17 | { 18 | uint32_t reg_val = cmn_reg->DDR_CMN_CLK_CTRL_CFG; 19 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_CLK_CTRL_CFG_GFCM_EN, enable); 20 | cmn_reg->DDR_CMN_CLK_CTRL_CFG = reg_val; 21 | } 22 | 23 | void cmn_clk_ctrl_set_pll0_div_clk_en_reg_if(cmn_reg_t *cmn_reg, bool enable) 24 | { 25 | uint32_t reg_val = cmn_reg->DDR_CMN_CLK_CTRL_CFG; 26 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_CLK_CTRL_CFG_PLL0_DIV_CLK_EN, enable); 27 | cmn_reg->DDR_CMN_CLK_CTRL_CFG = reg_val; 28 | } 29 | -------------------------------------------------------------------------------- /drivers/cmn/cmn_ibias.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void cmn_ibias_set_state_reg_if(cmn_reg_t *cmn_reg, ibias_state_t state) 10 | { 11 | uint32_t reg_val = cmn_reg->DDR_CMN_IBIAS_CFG; 12 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_IBIAS_CFG_EN, state); 13 | cmn_reg->DDR_CMN_IBIAS_CFG = reg_val; 14 | } 15 | -------------------------------------------------------------------------------- /drivers/cmn/cmn_pmon.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void cmn_pmon_set_state_reg_if(cmn_reg_t *cmn_reg, pmon_state_t state) 10 | { 11 | uint32_t reg_val; 12 | 13 | reg_val = UPDATE_REG_FIELD(0x0, DDR_CMN_PMON_ANA_CFG_NAND_EN, state); 14 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_ANA_CFG_NOR_EN, state); 15 | cmn_reg->DDR_CMN_PMON_ANA_CFG = reg_val; 16 | 17 | if (state == PMON_STATE_ENABLED) 18 | { 19 | // reset digital values of PMONs 20 | reg_val = cmn_reg->DDR_CMN_PMON_DIG_CFG; 21 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_CFG_REFCLK_RST, 0x1); 22 | cmn_reg->DDR_CMN_PMON_DIG_CFG = reg_val; 23 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_CFG_REFCLK_RST, 0x0); 24 | cmn_reg->DDR_CMN_PMON_DIG_CFG = reg_val; 25 | } 26 | 27 | reg_val = cmn_reg->DDR_CMN_PMON_DIG_NAND_CFG; 28 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_NAND_CFG_COUNT_EN, state); 29 | cmn_reg->DDR_CMN_PMON_DIG_NAND_CFG = reg_val; 30 | 31 | reg_val = cmn_reg->DDR_CMN_PMON_DIG_NOR_CFG; 32 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_NOR_CFG_COUNT_EN, state); 33 | cmn_reg->DDR_CMN_PMON_DIG_NOR_CFG = reg_val; 34 | } 35 | 36 | void cmn_pmon_configure_reg_if(cmn_reg_t *cmn_reg, 37 | uint16_t refcount, 38 | uint8_t init_wait) 39 | { 40 | uint32_t reg_val = cmn_reg->DDR_CMN_PMON_DIG_NAND_CFG; 41 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_NAND_CFG_REFCOUNT, refcount); 42 | cmn_reg->DDR_CMN_PMON_DIG_NAND_CFG = reg_val; 43 | 44 | reg_val = cmn_reg->DDR_CMN_PMON_DIG_NOR_CFG; 45 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_NOR_CFG_REFCOUNT, refcount); 46 | cmn_reg->DDR_CMN_PMON_DIG_NOR_CFG = reg_val; 47 | 48 | reg_val = cmn_reg->DDR_CMN_PMON_DIG_CFG; 49 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_CFG_INITWAIT, init_wait); 50 | cmn_reg->DDR_CMN_PMON_DIG_CFG = reg_val; 51 | } 52 | 53 | static void __cmn_pmon_get_status_count_reg_if(volatile uint32_t *status_addr, 54 | volatile uint32_t *cfg_addr, 55 | uint32_t *count) 56 | { 57 | uint32_t reg_val; 58 | uint32_t refcount; 59 | uint8_t done = 0; 60 | 61 | do 62 | { 63 | reg_val = *status_addr; 64 | done = GET_REG_FIELD(reg_val, DDR_CMN_PMON_NAND_STA_DONE); 65 | } while (done == 0x0); 66 | *count = GET_REG_FIELD(reg_val, DDR_CMN_PMON_NAND_STA_COUNT); 67 | 68 | reg_val = *cfg_addr; 69 | refcount = GET_REG_FIELD(reg_val, DDR_CMN_PMON_DIG_NAND_CFG_REFCOUNT); 70 | *count = *count / refcount; 71 | } 72 | 73 | void cmn_pmon_get_status_count_reg_if(cmn_reg_t *cmn_reg, uint32_t *count) 74 | { 75 | uint32_t nand_count; 76 | uint32_t nor_count; 77 | __cmn_pmon_get_status_count_reg_if(&cmn_reg->DDR_CMN_PMON_NAND_STA, &cmn_reg->DDR_CMN_PMON_DIG_NAND_CFG, &nand_count); 78 | __cmn_pmon_get_status_count_reg_if(&cmn_reg->DDR_CMN_PMON_NOR_STA, &cmn_reg->DDR_CMN_PMON_DIG_NOR_CFG, &nor_count); 79 | *count = (nand_count >> 1) + (nor_count >> 1); 80 | } 81 | -------------------------------------------------------------------------------- /drivers/cmn/cmn_rstn.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void cmn_rstn_set_pin_reg_if(cmn_reg_t *cmn_reg, bool override, bool high) 10 | { 11 | uint32_t reg_val = cmn_reg->DDR_CMN_RSTN_CFG; 12 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_RSTN_CFG_RSTN_OVR_VAL, high); 13 | cmn_reg->DDR_CMN_RSTN_CFG = reg_val; 14 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_RSTN_CFG_RSTN_OVR_SEL, override); 15 | cmn_reg->DDR_CMN_RSTN_CFG = reg_val; 16 | } 17 | 18 | void cmn_rstn_get_rstn_loopback_reg_if(cmn_reg_t *cmn_reg, 19 | uint8_t *rstn_lb) 20 | { 21 | *rstn_lb = GET_REG_FIELD(cmn_reg->DDR_CMN_RSTN_STA, DDR_CMN_RSTN_STA_RSTN_LPBK); 22 | } 23 | -------------------------------------------------------------------------------- /drivers/cmn/cmn_vref.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void cmn_vref_set_state_reg_if(cmn_reg_t *cmn_reg, 10 | wddr_msr_t msr, 11 | vref_state_t state) 12 | { 13 | uint32_t reg_val = cmn_reg->DDR_CMN_VREF_CFG[msr]; 14 | switch(state) 15 | { 16 | case VREF_STATE_DISABLED: 17 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_EN, 0x0); 18 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_HIZ, 0x0); 19 | break; 20 | case VREF_STATE_ENABLED: 21 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_EN, 0x1); 22 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_HIZ, 0x0); 23 | break; 24 | case VREF_STATE_HIZ: 25 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_EN, 0x0); 26 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_HIZ, 0x1); 27 | break; 28 | default: 29 | return; 30 | } 31 | cmn_reg->DDR_CMN_VREF_CFG[msr] = reg_val; 32 | } 33 | 34 | void cmn_vref_set_code_reg_if(cmn_reg_t *cmn_reg, 35 | wddr_msr_t msr, 36 | uint32_t code) 37 | { 38 | uint32_t reg_val = cmn_reg->DDR_CMN_VREF_CFG[msr]; 39 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_CTRL, code); 40 | cmn_reg->DDR_CMN_VREF_CFG[msr] = reg_val; 41 | } 42 | 43 | void cmn_vref_set_pwr_mode_reg_if(cmn_reg_t *cmn_reg, 44 | wddr_msr_t msr, 45 | vref_pwr_mode_t pwr_mode) 46 | { 47 | uint32_t reg_val = cmn_reg->DDR_CMN_VREF_CFG[msr]; 48 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_VREF_M0_CFG_PWR, pwr_mode); 49 | cmn_reg->DDR_CMN_VREF_CFG[msr] = reg_val; 50 | } 51 | -------------------------------------------------------------------------------- /drivers/cmn/cmn_zqcal.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void cmn_zqcal_set_state_reg_if(cmn_reg_t *cmn_reg, zqcal_state_t state) 10 | { 11 | uint32_t reg_val = cmn_reg->DDR_CMN_ZQCAL_CFG; 12 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_ZQCAL_CFG_CAL_EN, state); 13 | cmn_reg->DDR_CMN_ZQCAL_CFG = reg_val; 14 | } 15 | 16 | void cmn_zqcal_set_mode_reg_if(cmn_reg_t *cmn_reg, zqcal_mode_t mode) 17 | { 18 | uint32_t reg_val = cmn_reg->DDR_CMN_ZQCAL_CFG; 19 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_ZQCAL_CFG_PD_SEL, mode); 20 | cmn_reg->DDR_CMN_ZQCAL_CFG = reg_val; 21 | } 22 | 23 | void cmn_zqcal_set_code_reg_if(cmn_reg_t *cmn_reg, zqcal_mode_t mode, uint8_t code) 24 | { 25 | uint32_t reg_val = cmn_reg->DDR_CMN_ZQCAL_CFG; 26 | 27 | switch(mode) 28 | { 29 | case ZQCAL_MODE_PULL_UP: 30 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_ZQCAL_CFG_PCAL, code); 31 | break; 32 | case ZQCAL_MODE_PULL_DOWN: 33 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_ZQCAL_CFG_NCAL, code); 34 | break; 35 | default: 36 | return; 37 | } 38 | 39 | cmn_reg->DDR_CMN_ZQCAL_CFG = reg_val; 40 | } 41 | 42 | void cmn_zqcal_set_voh_reg_if(cmn_reg_t *cmn_reg, zqcal_voh_t voh) 43 | { 44 | uint32_t reg_val = cmn_reg->DDR_CMN_ZQCAL_CFG; 45 | switch(voh) 46 | { 47 | case ZQCAL_VOH_0P5: 48 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_ZQCAL_CFG_VOL_0P6_SEL, 0x0); 49 | break; 50 | case ZQCAL_VOH_0P6: 51 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CMN_ZQCAL_CFG_VOL_0P6_SEL, 0x1); 52 | break; 53 | default: 54 | return; 55 | } 56 | 57 | cmn_reg->DDR_CMN_ZQCAL_CFG = reg_val; 58 | } 59 | 60 | void cmn_zqcal_get_output_reg_if(cmn_reg_t *cmn_reg, uint8_t *val) 61 | { 62 | *val = GET_REG_FIELD(cmn_reg->DDR_CMN_ZQCAL_STA, DDR_CMN_ZQCAL_STA_COMP); 63 | } 64 | -------------------------------------------------------------------------------- /drivers/ctrl/ctrl_clk.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void ctrl_clk_set_pll_clk_en_reg_if(ctrl_reg_t *ctrl_reg, bool enable) 10 | { 11 | uint32_t reg_val = ctrl_reg->DDR_CTRL_CLK_CFG; 12 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CTRL_CLK_CFG_PLL_CLK_EN, enable); 13 | ctrl_reg->DDR_CTRL_CLK_CFG = reg_val; 14 | } 15 | 16 | void ctrl_clk_set_mcu_gfm_sel_reg_if(ctrl_reg_t *ctrl_reg, 17 | clk_mcu_gfm_sel_t sel) 18 | { 19 | uint32_t reg_val = ctrl_reg->DDR_CTRL_CLK_CFG; 20 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_CTRL_CLK_CFG_MCU_GFM_SEL, sel); 21 | ctrl_reg->DDR_CTRL_CLK_CFG = reg_val; 22 | } 23 | 24 | void ctrl_clk_get_mcu_gfm_sel_status_reg_if(ctrl_reg_t *ctrl_reg, 25 | uint8_t *gfm_sel0, 26 | uint8_t *gfm_sel1) 27 | { 28 | uint32_t reg_val = ctrl_reg->DDR_CTRL_CLK_STA; 29 | *gfm_sel0 = GET_REG_FIELD(reg_val, DDR_CTRL_CLK_STA_MCU_GFM_SEL0); 30 | *gfm_sel1 = GET_REG_FIELD(reg_val, DDR_CTRL_CLK_STA_MCU_GFM_SEL1); 31 | } 32 | 33 | void ctrl_clk_get_dfi_clk_status_reg_if(ctrl_reg_t *ctrl_reg, 34 | uint8_t *dfi_clk_on) 35 | { 36 | uint32_t reg_val = ctrl_reg->DDR_CTRL_CLK_STA; 37 | *dfi_clk_on = GET_REG_FIELD(reg_val, DDR_CTRL_CLK_STA_DFI_CLK_ON); 38 | } 39 | -------------------------------------------------------------------------------- /drivers/dfi/dfi_top.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void dfi_set_ca_loopback_sel_reg_if(dfi_reg_t *dfi_reg, 10 | uint8_t channel_sel) 11 | { 12 | uint32_t reg_val = dfi_reg->DDR_DFI_TOP_0_CFG; 13 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DFI_TOP_0_CFG_CA_LPBK_SEL, channel_sel); 14 | dfi_reg->DDR_DFI_TOP_0_CFG = reg_val; 15 | } 16 | -------------------------------------------------------------------------------- /drivers/dq/dq_bscan.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | 8 | /******************************************************************************* 9 | ** DQ 10 | *******************************************************************************/ 11 | void dq_dq_bscan_get_status_reg_if(dq_reg_t *dq_reg, uint8_t *status) 12 | { 13 | *status = dq_reg->DDR_DQ_DQ_RX_BSCAN_STA; 14 | } 15 | 16 | /******************************************************************************* 17 | ** DQS 18 | *******************************************************************************/ 19 | void dq_dqs_bscan_get_status_reg_if(dq_reg_t *dq_reg, uint8_t *status) 20 | { 21 | *status = dq_reg->DDR_DQ_DQS_RX_BSCAN_STA; 22 | } 23 | -------------------------------------------------------------------------------- /drivers/dq/dq_egress.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | #include 9 | 10 | /******************************************************************************* 11 | ** DQ 12 | *******************************************************************************/ 13 | void dq_dq_egress_ana_set_mode_reg_if(dq_reg_t *dq_reg, 14 | wddr_msr_t msr, 15 | uint8_t bit, 16 | egress_ana_mode_t mode) 17 | { 18 | configASSERT(bit < WDDR_PHY_DQ_SLICE_NUM); 19 | dq_reg->DDR_DQ_DQ_TX_EGRESS_ANA_CFG[msr][bit] = mode; 20 | } 21 | 22 | void dq_dq_egress_dig_set_mode_reg_if(dq_reg_t *dq_reg, 23 | wddr_msr_t msr, 24 | uint8_t bit, 25 | egress_dig_mode_t mode) 26 | { 27 | configASSERT(bit < WDDR_PHY_DQ_SLICE_NUM); 28 | dq_reg->DDR_DQ_DQ_TX_EGRESS_DIG_CFG[msr][bit] = mode; 29 | } 30 | 31 | /******************************************************************************* 32 | ** DQS 33 | *******************************************************************************/ 34 | void dq_dqs_egress_ana_set_mode_reg_if(dq_reg_t *dq_reg, 35 | wddr_msr_t msr, 36 | uint8_t bit, 37 | egress_ana_mode_t mode) 38 | { 39 | configASSERT(bit < WDDR_PHY_DQS_SLICE_NUM); 40 | dq_reg->DDR_DQ_DQS_TX_EGRESS_ANA_CFG[msr][bit] = mode; 41 | } 42 | 43 | void dq_dqs_egress_dig_set_mode_reg_if(dq_reg_t *dq_reg, 44 | wddr_msr_t msr, 45 | uint8_t bit, 46 | egress_dig_mode_t mode) 47 | { 48 | configASSERT(bit < WDDR_PHY_DQS_SLICE_NUM); 49 | dq_reg->DDR_DQ_DQS_TX_EGRESS_DIG_CFG[msr][bit] = mode; 50 | 51 | } 52 | -------------------------------------------------------------------------------- /drivers/dq/dq_gearbox.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | /******************************************************************************* 10 | ** DQ 11 | *******************************************************************************/ 12 | void dq_dq_rx_gb_set_mode_reg_if(dq_reg_t *dq_reg, 13 | wddr_msr_t msr, 14 | const rx_gb_cfg_t *cfg) 15 | { 16 | uint32_t reg_val = dq_reg->DDR_DQ_DQ_RX_CFG[msr]; 17 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQ_RX_M0_CFG_RGB_MODE, cfg->data_mode); 18 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQ_RX_M0_CFG_FGB_MODE, cfg->fifo_mode); 19 | dq_reg->DDR_DQ_DQ_RX_CFG[msr] = reg_val; 20 | } 21 | 22 | /******************************************************************************* 23 | ** DQS 24 | *******************************************************************************/ 25 | void dq_dqs_rx_gb_set_mode_reg_if(dq_reg_t *dq_reg, 26 | wddr_msr_t msr, 27 | const rx_gb_cfg_t *cfg) 28 | { 29 | uint32_t reg_val = dq_reg->DDR_DQ_DQS_RX_CFG[msr]; 30 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_M0_CFG_RGB_MODE, cfg->data_mode); 31 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_M0_CFG_FGB_MODE, cfg->fifo_mode); 32 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_M0_CFG_WCK_MODE, cfg->wck_mode); 33 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_M0_CFG_PRE_FILTER_SEL, cfg->pre_filter_sel); 34 | dq_reg->DDR_DQ_DQS_RX_CFG[msr] = reg_val; 35 | } 36 | 37 | void dq_dqs_tx_gb_set_mode_reg_if(dq_reg_t *dq_reg, 38 | wddr_msr_t msr, 39 | const tx_gb_cfg_t *cfg) 40 | { 41 | uint32_t reg_val = dq_reg->DDR_DQ_DQS_TX_CFG[msr]; 42 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_TX_M0_CFG_TGB_MODE, cfg->data_mode); 43 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_TX_M0_CFG_WGB_MODE, cfg->write_mode); 44 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_TX_M0_CFG_CK2WCK_RATIO, cfg->ck2wck_ratio); 45 | dq_reg->DDR_DQ_DQS_TX_CFG[msr] = reg_val; 46 | } 47 | -------------------------------------------------------------------------------- /drivers/dq/dq_lpde.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | #include 9 | 10 | /******************************************************************************* 11 | ** DQ 12 | *******************************************************************************/ 13 | void dq_dq_lpde_set_cfg_reg_if(dq_reg_t *dq_reg, 14 | wddr_msr_t msr, 15 | wddr_rank_t rank, 16 | uint8_t bit, 17 | bool enable, 18 | uint32_t cfg) 19 | { 20 | uint32_t reg_val = cfg; 21 | configASSERT(bit < WDDR_PHY_DQ_SLICE_NUM); 22 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQ_TX_LPDE_M0_R0_CFG_0_EN, enable); 23 | dq_reg->DDR_DQ_DQ_TX_LPDE_CFG[msr][rank][bit] = cfg; 24 | } 25 | 26 | /******************************************************************************* 27 | ** DQS 28 | *******************************************************************************/ 29 | void dq_dqs_lpde_set_cfg_reg_if(dq_reg_t *dq_reg, 30 | wddr_msr_t msr, 31 | wddr_rank_t rank, 32 | uint8_t bit, 33 | bool enable, 34 | uint32_t cfg) 35 | { 36 | uint32_t reg_val = cfg; 37 | 38 | configASSERT(bit < WDDR_PHY_DQS_TXRX_SLICE_NUM); 39 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_TX_LPDE_M0_R0_CFG_0_EN, enable); 40 | dq_reg->DDR_DQ_DQS_TX_LPDE_CFG[msr][rank][bit] = cfg; 41 | } 42 | 43 | void dq_dqs_lpde_rx_sdr_set_cfg_reg_if(dq_reg_t *dq_reg, 44 | wddr_msr_t msr, 45 | wddr_rank_t rank, 46 | bool enable, 47 | uint32_t cfg) 48 | { 49 | uint32_t reg_val = cfg; 50 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_SDR_LPDE_M0_R0_CFG_EN, enable); 51 | dq_reg->DDR_DQ_DQS_RX_SDR_LPDE_CFG[msr][rank] = cfg; 52 | } 53 | -------------------------------------------------------------------------------- /drivers/dq/dq_receiver.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | #include 9 | 10 | #define RECEIVER_DISABLE (0) 11 | #define RECEIVER_ENABLE (1) 12 | 13 | /******************************************************************************* 14 | ** DQS 15 | *******************************************************************************/ 16 | void dq_dqs_receiver_set_state_reg_if(dq_reg_t *dq_reg, 17 | wddr_msr_t msr, 18 | wddr_rank_t rank, 19 | receiver_state_t state) 20 | { 21 | uint32_t reg_val = dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank]; 22 | switch(state) 23 | { 24 | case REC_STATE_DISABLE: 25 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_EN, RECEIVER_DISABLE); 26 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_RXCAL_EN, RECEIVER_DISABLE); 27 | break; 28 | case REC_STATE_ENABLE: 29 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_EN, RECEIVER_ENABLE); 30 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_RXCAL_EN, RECEIVER_DISABLE); 31 | break; 32 | case REC_STATE_CAL: 33 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_EN, RECEIVER_ENABLE); 34 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_RXCAL_EN, RECEIVER_ENABLE); 35 | break; 36 | default: 37 | return; 38 | } 39 | dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank] = reg_val; 40 | } 41 | 42 | void dq_dqs_receiver_set_mode_reg_if(dq_reg_t *dq_reg, 43 | wddr_msr_t msr, 44 | wddr_rank_t rank, 45 | receiver_mode_t mode, 46 | receiver_path_state_t path_state) 47 | { 48 | uint32_t reg_val = dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank]; 49 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_SE_MODE, mode); 50 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_DCPATH_EN, path_state); 51 | dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank] = reg_val; 52 | } 53 | 54 | void dq_dqs_receiver_set_code_reg_if(dq_reg_t *dq_reg, 55 | wddr_msr_t msr, 56 | wddr_rank_t rank, 57 | uint8_t code[REC_PN_SIDE_NUM][REC_TC_SIDE_NUM]) 58 | { 59 | uint32_t reg_val = dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank]; 60 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_CAL_P_C, code[REC_P_SIDE][REC_C_SIDE]); 61 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_CAL_P_T, code[REC_P_SIDE][REC_T_SIDE]); 62 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_CAL_N_C, code[REC_N_SIDE][REC_C_SIDE]); 63 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_CAL_N_T, code[REC_N_SIDE][REC_T_SIDE]); 64 | dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank] = reg_val; 65 | } 66 | 67 | void dq_dqs_receiver_set_feedback_resistor_reg_if(dq_reg_t *dq_reg, 68 | wddr_msr_t msr, 69 | wddr_rank_t rank, 70 | uint8_t feedback_resistor) 71 | { 72 | uint32_t reg_val = dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank]; 73 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_CMN_M0_R0_CFG_FB_EN, feedback_resistor); 74 | dq_reg->DDR_DQ_DQS_RX_IO_CMN_CFG[msr][rank] = reg_val; 75 | } 76 | 77 | void dq_dqs_receiver_set_delay_reg_if(dq_reg_t *dq_reg, 78 | wddr_msr_t msr, 79 | wddr_rank_t rank, 80 | uint8_t bit, 81 | uint16_t delay, 82 | receiver_tc_side_mask_t side) 83 | { 84 | configASSERT(bit < WDDR_PHY_DQS_TXRX_SLICE_NUM); 85 | uint32_t reg_val = dq_reg->DDR_DQ_DQS_RX_IO_CFG[msr][rank][bit]; 86 | if (side & REC_T_SIDE_MASK) 87 | { 88 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_M0_R0_CFG_0_DLY_CTRL_T, delay); 89 | } 90 | 91 | if (side & REC_C_SIDE_MASK) 92 | { 93 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_DQS_RX_IO_M0_R0_CFG_0_DLY_CTRL_C, delay); 94 | } 95 | dq_reg->DDR_DQ_DQS_RX_IO_CFG[msr][rank][bit] = reg_val; 96 | } 97 | -------------------------------------------------------------------------------- /drivers/dq/dq_top.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void dq_top_set_chip_select_reg_if(dq_reg_t *dq_reg, 10 | wddr_rank_t rank_sel, 11 | bool override) 12 | { 13 | uint32_t reg_val = dq_reg->DDR_DQ_TOP_CFG; 14 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_TOP_CFG_WCS_SW_OVR_VAL, rank_sel); 15 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_TOP_CFG_RCS_SW_OVR_VAL, rank_sel); 16 | dq_reg->DDR_DQ_TOP_CFG = reg_val; 17 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_TOP_CFG_WCS_SW_OVR, override); 18 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_TOP_CFG_RCS_SW_OVR, override); 19 | dq_reg->DDR_DQ_TOP_CFG = reg_val; 20 | } 21 | 22 | void dq_top_clear_fifo_reg_if(dq_reg_t *dq_reg) 23 | { 24 | uint32_t reg_val = dq_reg->DDR_DQ_TOP_CFG; 25 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_TOP_CFG_FIFO_CLR, 0x1); 26 | dq_reg->DDR_DQ_TOP_CFG = reg_val; 27 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_DQ_TOP_CFG_FIFO_CLR, 0x0); 28 | dq_reg->DDR_DQ_TOP_CFG = reg_val; 29 | } 30 | 31 | void dq_top_get_chip_select_status_reg_if(dq_reg_t *dq_reg, 32 | uint8_t *wcs, 33 | uint8_t *rcs) 34 | { 35 | uint32_t reg_val = dq_reg->DDR_DQ_TOP_STA; 36 | *wcs = GET_REG_FIELD(reg_val, DDR_DQ_TOP_STA_WCS); 37 | *rcs = GET_REG_FIELD(reg_val, DDR_DQ_TOP_STA_RCS); 38 | } 39 | -------------------------------------------------------------------------------- /drivers/fsw/fsw_csp.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | 9 | void fsw_csp_set_clk_disable_over_val_reg_if(fsw_reg_t *fsw_reg, 10 | bool enable) 11 | { 12 | uint32_t reg_val = fsw_reg->DDR_FSW_CSP_1_CFG; 13 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CSP_1_CFG_CLK_DISABLE_OVR_VAL, enable); 14 | fsw_reg->DDR_FSW_CSP_1_CFG = reg_val; 15 | } 16 | 17 | void fsw_csp_sync_reg_if(fsw_reg_t *fsw_reg) 18 | { 19 | uint32_t csp_status; 20 | 21 | // Sync Request 22 | uint32_t reg_val = fsw_reg->DDR_FSW_CSP_1_CFG; 23 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CSP_1_CFG_REQ_OVR, 0x1); 24 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CSP_1_CFG_REQ_OVR_VAL, 0x1); 25 | fsw_reg->DDR_FSW_CSP_1_CFG = reg_val; 26 | do 27 | { 28 | csp_status = fsw_reg->DDR_FSW_CSP_STA; 29 | } while (GET_REG_FIELD(csp_status, DDR_FSW_CSP_STA_REQ_COMPLETE) != 1); 30 | 31 | // Turn off Override 32 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CSP_1_CFG_REQ_OVR_VAL, 0x0); 33 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CSP_1_CFG_REQ_COMPLETE_STA_CLR, 0x1); 34 | fsw_reg->DDR_FSW_CSP_1_CFG = reg_val; 35 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CSP_1_CFG_REQ_OVR, 0x0); 36 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CSP_1_CFG_REQ_COMPLETE_STA_CLR, 0x0); 37 | fsw_reg->DDR_FSW_CSP_1_CFG = reg_val; 38 | } 39 | -------------------------------------------------------------------------------- /drivers/fsw/fsw_ctrl.c: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * Copyright (c) 2021 Wavious LLC. 4 | * 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | #include 8 | #include 9 | 10 | void fsw_ctrl_set_msr_vco_ovr_val_reg_if(fsw_reg_t *fsw_reg, 11 | uint8_t msr, 12 | uint8_t vco_id) 13 | { 14 | uint32_t reg_val = fsw_reg->DDR_FSW_CTRL_CFG; 15 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_MSR_OVR_VAL, msr); 16 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_VCO_SEL_OVR_VAL, vco_id); 17 | fsw_reg->DDR_FSW_CTRL_CFG = reg_val; 18 | } 19 | 20 | void fsw_ctrl_set_msr_vco_ovr_reg_if(fsw_reg_t *fsw_reg, bool enable) 21 | { 22 | uint32_t reg_val = fsw_reg->DDR_FSW_CTRL_CFG; 23 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_VCO_SEL_OVR, enable); 24 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_MSR_OVR, enable); 25 | fsw_reg->DDR_FSW_CTRL_CFG = reg_val; 26 | } 27 | 28 | void fsw_ctrl_set_msr_toggle_en_reg_if(fsw_reg_t *fsw_reg, bool enable) 29 | { 30 | uint32_t reg_val = fsw_reg->DDR_FSW_CTRL_CFG; 31 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_MSR_TOGGLE_EN, enable); 32 | fsw_reg->DDR_FSW_CTRL_CFG = reg_val; 33 | } 34 | 35 | void fsw_ctrl_set_vco_toggle_en_reg_if(fsw_reg_t *fsw_reg, bool enable) 36 | { 37 | uint32_t reg_val = fsw_reg->DDR_FSW_CTRL_CFG; 38 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_VCO_TOGGLE_EN, enable); 39 | fsw_reg->DDR_FSW_CTRL_CFG = reg_val; 40 | } 41 | 42 | void fsw_ctrl_set_prep_done_reg_if(fsw_reg_t *fsw_reg, bool done) 43 | { 44 | uint32_t reg_val = fsw_reg->DDR_FSW_CTRL_CFG; 45 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_PREP_DONE, done); 46 | fsw_reg->DDR_FSW_CTRL_CFG = reg_val; 47 | } 48 | 49 | void fsw_ctrl_set_post_work_done_reg_if(fsw_reg_t *fsw_reg, 50 | bool override, 51 | bool done) 52 | { 53 | uint32_t reg_val = fsw_reg->DDR_FSW_CTRL_CFG; 54 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_PSTWORK_DONE, done); 55 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_FSW_CTRL_CFG_PSTWORK_DONE_OVR, override); 56 | fsw_reg->DDR_FSW_CTRL_CFG = reg_val; 57 | } 58 | 59 | uint8_t fsw_ctrl_get_current_msr_reg_if(fsw_reg_t *fsw_reg) 60 | { 61 | // Double flip to ensure only read as one or zero 62 | return !!GET_REG_FIELD(fsw_reg->DDR_FSW_CTRL_STA, DDR_FSW_CTRL_STA_CMN_MSR); 63 | } 64 | -------------------------------------------------------------------------------- /drivers/pll/driver.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | #include 9 | 10 | void pll_init_reg_if(pll_dev_t *pll, uint32_t base) 11 | { 12 | pll->base = base; 13 | } 14 | 15 | void pll_reset_reg_if(pll_dev_t *pll) 16 | { 17 | uint32_t reg_val; 18 | reg_val = reg_read(pll->base + DDR_MVP_PLL_CORE_OVERRIDES__ADR); 19 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_MVP_PLL_CORE_OVERRIDES_CORE_RESET_MUX, 0x1); 20 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_MVP_PLL_CORE_OVERRIDES_CORE_RESET, 0x0); 21 | reg_write(pll->base + DDR_MVP_PLL_CORE_OVERRIDES__ADR, reg_val); 22 | } 23 | 24 | void pll_set_vco_sel_reg_if(pll_dev_t *pll, vco_index_t vco_id) 25 | { 26 | uint32_t reg_val; 27 | reg_val = reg_read(pll->base + DDR_MVP_PLL_CORE_OVERRIDES__ADR); 28 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_MVP_PLL_CORE_OVERRIDES_CORE_VCO_SEL_MUX, 0x1); 29 | reg_val = UPDATE_REG_FIELD(reg_val, DDR_MVP_PLL_CORE_OVERRIDES_CORE_VCO_SEL, vco_id); 30 | reg_write(pll->base + DDR_MVP_PLL_CORE_OVERRIDES__ADR, reg_val); 31 | } 32 | 33 | void pll_switch_vco_reg_if(pll_dev_t *pll) 34 | { 35 | uint32_t reg_val; 36 | // Switch VCO 37 | reg_val = UPDATE_REG_FIELD(0, DDR_MVP_PLL_CORE_SWTICH_VCO_CORE_SWITCH_VCO, 0x1); 38 | reg_write(pll->base + DDR_MVP_PLL_CORE_SWTICH_VCO__ADR, reg_val); 39 | } 40 | -------------------------------------------------------------------------------- /drivers/wddr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | FILE( 2 | GLOB_RECURSE 3 | WDDR_DRIVER_SOURCES 4 | ${WAV_WDDR_TOP_LEVEL}/drivers/*/*.c 5 | ) 6 | 7 | set( 8 | INCLUDE_DIRECTORY 9 | ${WAV_WDDR_TOP_LEVEL}/include/drivers 10 | ${WAV_WDDR_TOP_LEVEL}/include/dev 11 | ${WAV_WDDR_TOP_LEVEL}/include/table 12 | ${WAV_WDDR_TOP_LEVEL}/include 13 | ) 14 | 15 | add_library( 16 | wddr_driver 17 | STATIC 18 | ${WDDR_DRIVER_SOURCES} 19 | ) 20 | 21 | target_include_directories( 22 | wddr_driver 23 | PUBLIC 24 | ${INCLUDE_DIRECTORY} 25 | ) 26 | 27 | target_link_libraries( 28 | wddr_driver 29 | messenger_driver 30 | kernel 31 | ) 32 | -------------------------------------------------------------------------------- /drivers/wddr/driver.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #include 7 | #include 8 | #include 9 | 10 | void wddr_clear_fifo_reg_if(wddr_dev_t *wddr, wddr_channel_t channel) 11 | { 12 | ca_top_clear_fifo_reg_if(wddr->channel[channel].ca_reg); 13 | dq_top_clear_fifo_reg_if(wddr->channel[channel].dq_reg[WDDR_DQ_BYTE_0]); 14 | dq_top_clear_fifo_reg_if(wddr->channel[channel].dq_reg[WDDR_DQ_BYTE_1]); 15 | } 16 | 17 | void wddr_set_dram_resetn_pin_reg_if(wddr_dev_t *wddr, bool override, bool high) 18 | { 19 | cmn_rstn_set_pin_reg_if(wddr->cmn.cmn_reg, override, high); 20 | } 21 | 22 | void wddr_set_chip_select_reg_if(wddr_dev_t *wddr, wddr_channel_t channel, wddr_rank_t rank, bool override) 23 | { 24 | ca_top_set_chip_select_reg_if(wddr->channel[channel].ca_reg, rank, override); 25 | dq_top_set_chip_select_reg_if(wddr->channel[channel].dq_reg[WDDR_DQ_BYTE_0], rank, override); 26 | dq_top_set_chip_select_reg_if(wddr->channel[channel].dq_reg[WDDR_DQ_BYTE_1], rank, override); 27 | } 28 | 29 | void wddr_read_bscan_result_reg_if(wddr_dev_t *wddr, wddr_dq_byte_t dq_byte, wddr_channel_t channel, uint8_t *result) 30 | { 31 | // Read BSCAN 32 | dq_dq_bscan_get_status_reg_if(wddr->channel[channel].dq_reg[dq_byte], result); 33 | } 34 | -------------------------------------------------------------------------------- /firmware/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(LIB_NAME phy_firmware) 2 | 3 | set( 4 | SRC 5 | ${CMAKE_CURRENT_LIST_DIR}/phy_task.c 6 | ${CMAKE_CURRENT_LIST_DIR}/phy_api.c 7 | ) 8 | 9 | add_library( 10 | ${LIB_NAME} 11 | STATIC 12 | ${SRC} 13 | ) 14 | 15 | target_compile_options( 16 | ${LIB_NAME} 17 | PRIVATE 18 | -Wno-missing-field-initializers 19 | ) 20 | 21 | target_compile_definitions( 22 | ${LIB_NAME} 23 | PRIVATE 24 | -DCONFIG_CAL_PERIODIC=${CONFIG_CAL_PERIODIC} 25 | -DCONFIG_CALIBRATE_PLL=${CONFIG_CALIBRATE_PLL} 26 | -DCONFIG_CALIBRATE_ZQCAL=${CONFIG_CALIBRATE_ZQCAL} 27 | -DCONFIG_CALIBRATE_SA=${CONFIG_CALIBRATE_SA} 28 | -DCONFIG_DRAM_TRAIN=${CONFIG_DRAM_TRAIN} 29 | ) 30 | 31 | target_include_directories( 32 | ${LIB_NAME} 33 | PUBLIC 34 | ${INCLUDE_DIRECTORY} 35 | ) 36 | 37 | target_link_libraries( 38 | ${LIB_NAME} 39 | wddr 40 | ) 41 | -------------------------------------------------------------------------------- /firmware/phy_api.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | /* Firmware includes. */ 8 | #include 9 | 10 | /******************************************************************************* 11 | ** MACROS 12 | *******************************************************************************/ 13 | #define PREP_TIMEOUT (pdMS_TO_TICKS(5)) // 5 milliseconds 14 | #define BOOT_TRY_COUNT (1) 15 | #define PREP_TRY_COUNT (3) 16 | 17 | /******************************************************************************* 18 | ** FUNCTION DECLARATIONS 19 | *******************************************************************************/ 20 | /** Internal Function for sending blocking message to the FW */ 21 | static UBaseType_t __send_fw_msg(fw_msg_t *msg, 22 | TickType_t xTicksToWait, 23 | uint8_t try_count); 24 | 25 | /******************************************************************************* 26 | ** IMPLEMENTATIONS 27 | *******************************************************************************/ 28 | void firmware_phy_init(void) 29 | { 30 | fw_phy_task_init(); 31 | } 32 | 33 | UBaseType_t firmware_phy_start(bool calibrate, bool train_dram) 34 | { 35 | fw_msg_t msg; 36 | fw_phy_start_cfg_t cfg = { 37 | .calibrate = calibrate, 38 | .train_dram = train_dram, 39 | }; 40 | msg.event = FW_PHY_EVENT_BOOT; 41 | msg.data = &cfg; 42 | return __send_fw_msg(&msg, portMAX_DELAY, BOOT_TRY_COUNT); 43 | } 44 | 45 | UBaseType_t firmware_phy_prep_switch(uint8_t freq_id) 46 | { 47 | fw_msg_t msg; 48 | msg.event = FW_PHY_EVENT_PREP; 49 | msg.data = (void *) (uintptr_t) freq_id; 50 | return __send_fw_msg(&msg, PREP_TIMEOUT, PREP_TRY_COUNT); 51 | } 52 | 53 | static UBaseType_t __send_fw_msg(fw_msg_t *msg, TickType_t xTicksToWait, uint8_t ucTryCount) 54 | { 55 | UBaseType_t resp; 56 | 57 | msg->xSender = xTaskGetCurrentTaskHandle(); 58 | 59 | // Clear notifications 60 | xTaskNotifyWait(0, 0, NULL, 0); 61 | 62 | do 63 | { 64 | // Send message 65 | fw_phy_task_notify(msg); 66 | 67 | // Wait for it to be handled 68 | xTaskNotifyWait(0, 0, &resp, xTicksToWait); 69 | 70 | if (resp == FW_RESP_RETRY) 71 | { 72 | continue; 73 | } 74 | 75 | return resp == FW_RESP_SUCCESS ? pdPASS : pdFAIL; 76 | } while (--ucTryCount); 77 | 78 | return pdFAIL; 79 | } 80 | -------------------------------------------------------------------------------- /include/compiler.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _COMPILER_H_ 7 | #define _COMPILER_H_ 8 | 9 | #define __UNUSED__ __attribute__((unused)) 10 | #define __INTERRUPT__ __attribute__((interrupt)) 11 | #define __FALLTHROUGH__ __attribute__((fallthrough)) 12 | #define __PACKED__ __attribute__((__packed__)) 13 | #define __ALIGNED_4__ __attribute__((aligned(4))) 14 | #define __ALIGNED_8__ __attribute__((aligned(8))) 15 | #define __O1__ __attribute__((optimize("O1"))) 16 | #define __O2__ __attribute__((optimize("O2"))) 17 | #define __O3__ __attribute__((optimize("O3"))) 18 | 19 | #endif /* _COMPILER_H_ */ 20 | -------------------------------------------------------------------------------- /include/dev/cmn/device.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_DEV_H_ 7 | #define _CMN_DEV_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | 13 | /** 14 | * @brief Common Device Structure 15 | * 16 | * @details Common device structure that aggegrates components common to all 17 | * channels. 18 | * 19 | * cmn_reg Common Register Space 20 | */ 21 | typedef struct common_device 22 | { 23 | cmn_reg_t *cmn_reg; 24 | } cmn_dev_t; 25 | 26 | /** 27 | * @biref Common Device Initialization 28 | * 29 | * @details Initializes Common Device. 30 | * 31 | * @param[in] cmn_dev pointer to common device. 32 | * @param[in] base base address of cmn_dev register space. 33 | * 34 | * @return void. 35 | */ 36 | void cmn_init(cmn_dev_t *cmn_dev, uint32_t base); 37 | 38 | /** 39 | * @brief Common Device Enable 40 | * 41 | * @details Enables entire common device (vref and bias current) 42 | * 43 | * @param[in] cmn_dev pointer to common device. 44 | * 45 | * @return void. 46 | */ 47 | void cmn_enable(cmn_dev_t *cmn_dev); 48 | 49 | /** 50 | * @brief Common Bias Current Enable 51 | * 52 | * @details Enables the Bias current. 53 | * 54 | * @param[in] cmn_dev pointer to common device. 55 | * 56 | * @return void. 57 | */ 58 | void cmn_ibias_enable(cmn_dev_t *cmn_dev); 59 | 60 | /** 61 | * @brief Common Bias Current Disable 62 | * 63 | * @details Disables the Bias current. 64 | * 65 | * @param[in] cmn_dev pointer to common device. 66 | * 67 | * @return void. 68 | */ 69 | void cmn_ibias_disable(cmn_dev_t *cmn_dev); 70 | 71 | /** 72 | * @brief Process Monitor Run 73 | * 74 | * @details Runs Process Monitor Estimation. 75 | * 76 | * @param[in] cmn_dev pointer to common device. 77 | * @param[out] count pointer to where to store measured estimation. 78 | * 79 | * @return void 80 | */ 81 | void cmn_pmon_run(cmn_dev_t *cmn_dev, uint32_t *count); 82 | 83 | /** 84 | * @brief Common Process Monitor Configure 85 | * 86 | * @details Configures Process Monitor. 87 | * 88 | * @param[in] cmn_dev pointer to common device. 89 | * @param[in] cfg pointer to process monitor configuration to use. 90 | * 91 | * @return void 92 | */ 93 | void cmn_pmon_configure(cmn_dev_t *cmn_dev, pmon_cfg_t *cfg); 94 | 95 | /** 96 | * @brief Common Voltage Reference Set Mode Enable 97 | * 98 | * @details Places the Voltage Reference device into Enabled mode. 99 | * 100 | * @param[in] cmn_dev pointer to common device. 101 | * @param[in] msr which MSR register set to use. 102 | * 103 | * @return void 104 | */ 105 | void cmn_vref_set_mode_enable(cmn_dev_t *cmn_dev, wddr_msr_t msr); 106 | 107 | /** 108 | * @brief Common Voltage Reference Set Mode Disable 109 | * 110 | * @details Places the Voltage Reference device into Disabled mode. 111 | * 112 | * @param[in] cmn_dev pointer to common device. 113 | * @param[in] msr which MSR register set to use. 114 | * 115 | * @return void 116 | */ 117 | void cmn_vref_set_mode_disable(cmn_dev_t *cmn_dev, wddr_msr_t msr); 118 | 119 | /** 120 | * @brief Common Voltage Reference Set Mode HIZ 121 | * 122 | * @details Places the Voltage Reference device into HI-Z mode. 123 | * 124 | * @param[in] cmn_dev pointer to common device. 125 | * @param[in] msr which MSR register set to use. 126 | * 127 | * @return void 128 | */ 129 | void cmn_vref_set_mode_hiz(cmn_dev_t *cmn_dev, wddr_msr_t msr); 130 | 131 | /** 132 | * @brief ZQCAL Calibrate 133 | * 134 | * @details Perform ZQCAL calibration procedure. 135 | * 136 | * @param[in] cmn_dev pointer to common device. 137 | * @param[out] cfg pointer to ZQCAL configuration structure to fill in 138 | * with calibrated values. 139 | * 140 | * @return returns whether calibraton completed successfully. 141 | * @retval WDDR_SUCCESS if successful. 142 | * @retval WDDR_ERROR_ZQCAL_NCAL_AT_MIN if minimum code is used for NCAL. 143 | * @retval WDDR_ERROR_ZQCAL_NCAL_AT_MAX if maximum code is used for NCAL. 144 | * @retval WDDR_ERROR_ZQCAL_PCAL_AT_MIN if minimum code is used for PCAL. 145 | * @retval WDDR_ERROR_ZQCAL_PCAL_AT_MAX if maximum code is used for PCAL. 146 | */ 147 | wddr_return_t cmn_zqcal_calibrate(cmn_dev_t *cmn_dev, zqcal_cfg_t *cfg); 148 | 149 | #endif /* _CMN_DEV_H_ */ 150 | -------------------------------------------------------------------------------- /include/dev/ctrl/device.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CTRL_DEV_H_ 7 | #define _CTRL_DEV_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief Control Device Structure 14 | * 15 | * @details Control device structure that abstracts PHY CTRL register space. 16 | * 17 | * ctrl_reg Control Register Space 18 | */ 19 | typedef struct control_device 20 | { 21 | ctrl_reg_t *ctrl_reg; 22 | } ctrl_dev_t; 23 | 24 | /** 25 | * @biref Control Device Initialization 26 | * 27 | * @details Initializes Control Device. 28 | * 29 | * @param[in] ctrl_dev pointer to control device. 30 | * @param[in] base base address of control register space. 31 | * 32 | * @return void. 33 | */ 34 | void ctrl_init(ctrl_dev_t *ctrl_dev, uint32_t base); 35 | 36 | #endif /* _CTRL_DEV_H_ */ 37 | -------------------------------------------------------------------------------- /include/dev/dfi/buffer.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DFI_BUFFER_DEV_H_ 7 | #define _DFI_BUFFER_DEV_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | #define DFI_FIFO_DEPTH (64) 15 | #define DFI_IG_FIFO_LOAD_NUM (TX_PACKET_SIZE_WORDS) 16 | #define DFI_EG_FIFO_LOAD_NUM (RX_PACKET_SIZE_WORDS) 17 | /** 18 | * @brief DFI Buffer Enable 19 | * 20 | * @details Enables DFI Buffer. Needs to be called before packets can be 21 | * loaded into the IG FIFO or read from EG FIFO. 22 | * 23 | * @param[in] dfi pointer to DFI device. 24 | * 25 | * @return void 26 | */ 27 | void dfi_buffer_enable(dfi_dev_t *dfi); 28 | 29 | /** 30 | * @brief DFI Buffer Disable 31 | * 32 | * @details Disables DFI Buffer. Needs to be called once done with DFI interface. 33 | * 34 | * @param[in] dfi pointer to DFI device. 35 | * 36 | * @return void 37 | */ 38 | void dfi_buffer_disable(dfi_dev_t *dfi); 39 | 40 | /** 41 | * @brief DFI Buffer Fill Packets 42 | * 43 | * @details Fills in IG FIFO with given TX Packet Buffer. 44 | * 45 | * @param[in] dfi pointer to DFI device. 46 | * @param[in] packet_list pointer to list of packets to write. 47 | * 48 | * @return returns whether all packets were written to IG FIFO. 49 | * @retval DFI_SUCCESS if all packets successfully written. 50 | * @retval DFI_ERROR_FIFO_FULL if IG FIFO is full before all 51 | * packets have been written. 52 | */ 53 | dfi_return_t dfi_buffer_fill_packets(dfi_dev_t *dfi, 54 | const List_t *packet_list); 55 | 56 | /** 57 | * @brief DFI Buffer Send Packets 58 | * 59 | * @details Sends the packets in the IG FIFO. 60 | * 61 | * @param[in] dfi pointer to DFI Buffer device. 62 | * 63 | * @return void 64 | */ 65 | void dfi_buffer_send_packets(dfi_dev_t *dfi); 66 | 67 | /** 68 | * @brief DFI Buffer Fill and Send Packets 69 | * 70 | * @details Fills IG FIFO with packets and then immediately sends them. 71 | * 72 | * @param[in] dfi pointer to DFI device. 73 | * @param[in] packet_list pointer to list of packets to write. 74 | * 75 | * @return returns whether all packets were written to IG FIFO. 76 | * @retval DFI_SUCCESS if all packets successfully written. 77 | * @retval DFI_ERROR_FIFO_FULL if IG FIFO is full before all 78 | * packets have been written. 79 | */ 80 | dfi_return_t dfi_buffer_fill_and_send_packets(dfi_dev_t *dfi, 81 | const List_t *packet_list); 82 | 83 | /** 84 | * @brief DFI Buffer Read Packets 85 | * 86 | * @details Read given number of packets from the EG FIFO. 87 | * 88 | * @param[in] dfi pointer to DFI device. 89 | * @param[out] rx_buffer pointer to the RX Packet buffer to read into. 90 | * @param[inout] num_packets number of packets to read / were read. 91 | * 92 | * @return returns if requested number of packets were read. 93 | * @retval DFI_SUCCESS if number of packets requested were read. 94 | * @retval DFI_ERROR_FIFO_EMPTY if EG FIFO is empty before 95 | * number of requested packets have been read. 96 | */ 97 | dfi_return_t dfi_buffer_read_packets(dfi_dev_t *dfi, 98 | dfi_rx_packet_buffer_t *rx_buffer, 99 | uint8_t num_packets); 100 | 101 | #endif /* _DFI_BUFFER_DEV_H_ */ 102 | -------------------------------------------------------------------------------- /include/dev/dfi/device.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DFI_DEV_H_ 7 | #define _DFI_DEV_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief DFI Device Structure 14 | * 15 | * @details DFI Device structure that agregrates all DFI components. 16 | * 17 | * dfi_reg DFI register space. 18 | * dfich_reg DFI Channel register space. 19 | */ 20 | typedef struct dfi_dev_t 21 | { 22 | dfi_reg_t *dfi_reg; 23 | dfich_reg_t *dfich_reg; 24 | } dfi_dev_t; 25 | 26 | /** 27 | * @brief DFI Device Initialzation 28 | * 29 | * @details Initializes DFI Device at device level. 30 | * 31 | * @param[in] dfi pointer to DFI device. 32 | * @param[in] base base address of DFI device. 33 | * 34 | * @return void 35 | */ 36 | void dfi_init(dfi_dev_t *dfi, uint32_t base); 37 | 38 | #endif /* _DFI_DEV_H_ */ 39 | -------------------------------------------------------------------------------- /include/dev/dfi/intf.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DFI_INTF_DEV_H_ 7 | #define _DFI_INTF_DEV_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief DFI PHY Master Request 13 | * 14 | * @details Request Memory Controller through DFI interface for PHY to have 15 | * Master control of the DRAM. 16 | * 17 | * @param[in] dfi pointer to DFI device. 18 | * @param[in] req PHYMSTR request parameters. 19 | * 20 | * @return void. 21 | */ 22 | void dfi_phymstr_req(dfi_dev_t *dfi, dfi_phymstr_req_t *req); 23 | 24 | /** 25 | * @brief DFI PHY Master Exit 26 | * 27 | * @details Release PHY control of DRAM back to the Memory Controller. 28 | * 29 | * @param[in] dfi pointer to DFI device. 30 | * 31 | * @return void. 32 | */ 33 | void dfi_phymstr_exit(dfi_dev_t *dfi); 34 | 35 | /** 36 | * @brief DFI Control Update Deassert Acknowledge 37 | * 38 | * @details Deassert Acknowledge indicating that IOCAL Update has been performed 39 | * via CTRLUPD ACK interface. 40 | * 41 | * @param[in] dfi pointer to DFI device. 42 | * 43 | * @return void. 44 | */ 45 | void dfi_ctrlupd_deassert_ack(dfi_dev_t *dfi); 46 | 47 | /** 48 | * @brief DFI Control Update Enable 49 | * 50 | * @details Allows the PHY to handle all CTRLUPD Requests from the Memory 51 | * Controller. 52 | * 53 | * @param[in] dfi pointer to DFI device. 54 | * 55 | * @return void. 56 | */ 57 | void dfi_ctrlupd_enable(dfi_dev_t *dfi); 58 | 59 | /** 60 | * @brief DFI Control Update Disable 61 | * 62 | * @details Forces the PHY to ignore all CTRLUPD Requests from the Memory 63 | * Controller. 64 | * 65 | * @param[in] dfi pointer to DFI device. 66 | * 67 | * @return void. 68 | */ 69 | void dfi_ctrlupd_disable(dfi_dev_t *dfi); 70 | 71 | /** 72 | * @brief DFI PHY Update Request 73 | * 74 | * @details Request Memory Controller through DFI PHYUPD interface to allow 75 | * PHY to update PHY CSRs. 76 | * 77 | * @param[in] dfi pointer to DFI device. 78 | * @param[in] type PHYUPD type requested. 79 | * 80 | * @return void. 81 | */ 82 | void dfi_phyupd_req(dfi_dev_t *dfi, dfi_phyupd_type_t type); 83 | 84 | /** 85 | * @brief DFI PHY Update Exit 86 | * 87 | * @details Signals to Memory Controller that PHY is done with previously 88 | * requested update. 89 | * 90 | * @param[in] dfi pointer to DFI device. 91 | * 92 | * @return void. 93 | */ 94 | void dfi_phyupd_exit(dfi_dev_t *dfi); 95 | 96 | #endif /* _DFI_INTF_DEV_H_ */ 97 | -------------------------------------------------------------------------------- /include/dev/fsw/device.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _FSW_DEV_H_ 7 | #define _FSW_DEV_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | 13 | /** 14 | * @brief Frequency Switch Modes 15 | * 16 | * SW Mode where software initiates frequency switch. 17 | * DFI Mode where DFI interface initiates frequency switch. 18 | */ 19 | typedef enum fsw_mode 20 | { 21 | FSW_MODE_SW, 22 | FSW_MODE_DFI, 23 | } fsw_mode_t; 24 | 25 | /** 26 | * @brief Frequency Switch Device Structure 27 | * 28 | * fsw_reg Poniter to Frequency Switch register space. 29 | * mode The current Frequency Switch mode of the FSW device. After boot, 30 | * mode is always FSW_MODE_DFI and all switches have to be initaited 31 | * via the DFI interface. 32 | */ 33 | typedef struct fsw_device 34 | { 35 | fsw_reg_t *fsw_reg; 36 | fsw_mode_t mode; 37 | } fsw_dev_t; 38 | 39 | /** 40 | * @brief Frequency Switch Device Initialization 41 | * 42 | * @details Initializes the Frequency Switch Device. 43 | * 44 | * @param[in] dev pointer to Frequency Switch device to init. 45 | * @param[in] base base address of fsw register space. 46 | * 47 | * @return void. 48 | */ 49 | void fsw_init(fsw_dev_t *dev, uint32_t base); 50 | 51 | /** 52 | * @brief Frequency Switch Switch To DFI Mode. 53 | * 54 | * @details Switches the Frequency Switch device to DFI mode. This means that 55 | * frequency switches are initiated via the DFI interface (INIT_START). 56 | * Should be called after PHY boots. 57 | * 58 | * @param[in] fsw_dev pointer to Frequency Switch device. 59 | * @param[in] dfi_dev pointer to DFI device. 60 | * 61 | * @return void. 62 | */ 63 | void fsw_switch_to_dfi_mode(fsw_dev_t *fsw_dev, dfi_dev_t *dfi_dev); 64 | 65 | /** 66 | * @brief Frequency Switch Get Current Mode Switch Register (MSR) 67 | * 68 | * @details Returns the current Mode Switch Register configured in the PHY. 69 | * PHY supports two concurrent configurations. The MSR indicates which 70 | * of the configurations the PHY uses currently. 71 | * 72 | * @return returns current Mode Switch Register value. 73 | * @retval possible values are WDDR_MSR_0 and WDDR_MSR_1. 74 | */ 75 | wddr_msr_t fsw_get_current_msr(fsw_dev_t *dev); 76 | 77 | /** 78 | * @brief Frequency Switch Get Next Mode Switch Register (MSR) 79 | * 80 | * @details Returns the next Mode Switch Register configured in the PHY. 81 | * PHY supports two concurrent configurations. The MSR indicates which 82 | * of the configurations the PHY uses currently. This function returns 83 | * the next MSR not in use. 84 | * 85 | * @return returns current Mode Switch Register value. 86 | * @retval possible values are WDDR_MSR_0 and WDDR_MSR_1. 87 | */ 88 | wddr_msr_t fsw_get_next_msr(fsw_dev_t *dev); 89 | 90 | #endif /* _FSW_DEV_H_ */ 91 | -------------------------------------------------------------------------------- /include/dev/messenger/device.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _MESSENGER_DEV_H_ 7 | #define _MESSENGER_DEV_H_ 8 | 9 | /* Standard includes. */ 10 | #include 11 | 12 | /* Kernel includes. */ 13 | #include 14 | #include 15 | 16 | /** @brief WDDR Message Interface Structure */ 17 | typedef message_interface_t wddr_message_interface_t; 18 | 19 | /** 20 | * @brief WDDR Messenger Interface Initialization 21 | * 22 | * @details Initializes WDDR Messenger Interface. 23 | * 24 | * @param[in] messenger pointer to WDDR Messenger Interface. 25 | * 26 | * @return void 27 | */ 28 | void wddr_messenger_init(wddr_message_interface_t *messenger); 29 | 30 | /** 31 | * @brief WDDR Messenger Interface Send Message 32 | * 33 | * @details Initializes WDDR Messenger Interface. 34 | * 35 | * @param[in] messenger pointer to WDDR Messenger Interface. 36 | * @param[out] message pointer to message to send. 37 | * 38 | * @return void 39 | */ 40 | void wddr_messenger_send(wddr_message_interface_t *messenger, Message_t *message); 41 | 42 | /** 43 | * @brief WDDR Messenger Interface Receive Message 44 | * 45 | * @details Initializes WDDR Messenger Interface. 46 | * 47 | * @param[in] messenger pointer to WDDR Messenger Interface. 48 | * @param[out] message pointer to store received message. 49 | * 50 | * @return if message has been successfully received. 51 | * @retval true if message received successfully. 52 | * @retval false if message not able to be received. 53 | */ 54 | bool wddr_messenger_receive(wddr_message_interface_t *messenger, Message_t *message); 55 | 56 | #endif /* _MESSENGER_DEV_H_ */ 57 | -------------------------------------------------------------------------------- /include/dev/messenger/messages_wddr.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _MESSAGES_WDDR_H_ 7 | #define _MESSAGES_WDDR_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief WDDR Specific Message Enumeration 13 | * 14 | * @details These messages are supported by the WDDR device. 15 | * 16 | * FREQ_PREP_REQ frequency prep request message. 17 | * FREQ_PREP_RESP frequency prep response message. 18 | * END_OF_MESSAGES indicates number of general messages. 19 | */ 20 | typedef enum messages_wddr_t { 21 | MESSAGE_WDDR_FREQ_PREP_REQ = 0x00020002, 22 | MESSAGE_WDDR_FREQ_PREP_RESP, 23 | MESSAGE_WDDR_END_OF_MESSAGES, 24 | } messages_wddr_t; 25 | 26 | #define WDDR_DEVICE_ID (0x00000002) 27 | 28 | #define WDDR_FREQ_PREP_REQ__FREQ_ID__MSK (0x000000FF) 29 | #define WDDR_FREQ_PREP_REQ__FREQ_ID__SHFT (0x00000000) 30 | 31 | #define WDDR_FREQ_PREP_RSP__STATUS__MSK (0x000000FF) 32 | #define WDDR_FREQ_PREP_RSP__STATUS__SHFT (0x00000000) 33 | #define WDDR_FREQ_PREP_RSP__FREQ_ID__MSK (0x0000FF00) 34 | #define WDDR_FREQ_PREP_RSP__FREQ_ID__SHFT (0x00000008) 35 | #define WDDR_FREQ_PREP_RSP__RESP_CODE__MSK (0x00FF0000) 36 | #define WDDR_FREQ_PREP_RSP__RESP_CODE__SHFT (0x00000010) 37 | 38 | // WDDR specific Boot Start Config Data 39 | #define WDDR_BOOT_REQ__CAL__MSK (0x00000001) 40 | #define WDDR_BOOT_REQ__CAL__SHFT (0x00000000) 41 | #define WDDR_BOOT_REQ__TRAIN__MSK (0x00000002) 42 | #define WDDR_BOOT_REQ__TRAIN__SHFT (0x00000001) 43 | 44 | #endif /* _MESSAGES_WDDR_H_ */ 45 | -------------------------------------------------------------------------------- /include/dev/vco/device.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _VCO_DEV_H_ 7 | #define _VCO_DEV_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief VCO Device Structure 13 | * 14 | * @details Structure used to store state of VCO device. 15 | * 16 | * base base address of the VCO device. 17 | * vco_id id of the VCO. 18 | * freq_id current frequency that VCO is configured to output. 19 | */ 20 | typedef struct vco_dev_t 21 | { 22 | uint32_t base; 23 | uint8_t vco_id; 24 | uint8_t freq_id; 25 | } vco_dev_t; 26 | 27 | #endif /* _VCO_DEV_H_ */ 28 | -------------------------------------------------------------------------------- /include/dev/wddr/boot_options.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _WDDR_BOOT_OPTIONS_H_ 7 | #define _WDDR_BOOT_OPTIONS_H_ 8 | 9 | #include 10 | #include 11 | 12 | #define SET_BOOT_OPTION(option_name, option_val) \ 13 | (SET_REG_FIELD(option_name, option_val)) 14 | 15 | #define GET_BOOT_OPTION(option_name, option_val) \ 16 | (GET_REG_FIELD(option_name, option_val)) 17 | 18 | #define UPDATE_BOOT_OPTION(cfg, option_name, option_val) \ 19 | (UPDATE_REG_FIELD(cfg, option_name, option_val)) 20 | 21 | #define WDDR_BOOT_OPTION_PLL_CAL__MSK (0x00000001) 22 | #define WDDR_BOOT_OPTION_PLL_CAL__SHFT (0x00000000) 23 | #define WDDR_BOOT_OPTION_ZQCAL_CAL__MSK (0x00000002) 24 | #define WDDR_BOOT_OPTION_ZQCAL_CAL__SHFT (0x00000001) 25 | #define WDDR_BOOT_OPTION_SA_CAL__MSK (0x00000004) 26 | #define WDDR_BOOT_OPTION_SA_CAL__SHFT (0x00000002) 27 | #define WDDR_BOOT_OPTION_TRAIN_DRAM__MSK (0x00000008) 28 | #define WDDR_BOOT_OPTION_TRAIN_DRAM__SHFT (0x00000003) 29 | 30 | #define WDDR_BOOT_CONFIG_NONE (0x00000000) 31 | 32 | /** 33 | * @brief WDDR Boot Configuration Type 34 | * 35 | * @details Type used to represent boot options mask. The following macros 36 | * should be used: 37 | * 38 | * SET_BOOT_OPTION 39 | * GET_BOOT_OPTION 40 | * UPDATE_BOOT_OPTION 41 | * 42 | * The option definitions above are used 43 | * 44 | * // Enable PLL calibration 45 | * cfg = SET_REG_FIELD(WDDR_BOOT_OPTION_PLL_CAL, 0x1); 46 | * 47 | * ..... 48 | * 49 | * if (GET_REG_FIELD(WDDR_BOOT_OPTION_PLL_CAL)) 50 | * { 51 | * // perform calibration 52 | * } 53 | */ 54 | typedef uint32_t wddr_boot_cfg_t; 55 | 56 | #endif /* _WDDR_BOOT_OPTIONS_H_ */ 57 | -------------------------------------------------------------------------------- /include/dev/wddr/irq_map.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _WDDR_IRQ_MAP_H_ 7 | #define _WDDR_IRQ_MAP_H_ 8 | 9 | #define FAST_IRQ_STICKY_MASK(irq) (1 << irq) 10 | 11 | // IRQ Defintions (28 real interrupts) 12 | // Used for Sticky Bits 13 | typedef enum wddr_irq_t 14 | { 15 | DDR_IRQ_HOST2PHY_REQ, 16 | DDR_IRQ_PHY2HOST_ACK, 17 | DDR_IRQ_CH0_IBUF_EMPTY, 18 | DDR_IRQ_CH0_IBUF_FULL, 19 | DDR_IRQ_CH0_EBUF_NOT_EMPTY, 20 | DDR_IRQ_CH0_EBUF_FULL, 21 | DDR_IRQ_INIT_START, 22 | DDR_IRQ_INIT_COMPLETE, 23 | DDR_IRQ_LP_DATA_REQ, 24 | DDR_IRQ_LP_CTRL_REQ, 25 | DDR_IRQ_PLL, 26 | DDR_IRQ_EXT_0, 27 | DDR_IRQ_EXT_1, 28 | DDR_IRQ_CTRLUPD_REQ_ASSERTION, 29 | DDR_IRQ_CTRLUPD_REQ_DEASSERTION, 30 | DDR_IRQ_PHYUPD_ACK, 31 | DDR_IRQ_PHYMSTR_ACK, 32 | DDR_IRQ_AHB_ADR_DET_0, 33 | DDR_IRQ_AHB_ADR_DET_1, 34 | DDR_IRQ_CH1_0_IDX, 35 | DDR_IRQ_CH1_1_IDX, 36 | DDR_IRQ_CH0_IBUF_OVERFLOW, 37 | DDR_IRQ_CH0_EBUF_OVERFLOW, 38 | DDR_IRQ_CH1_IBUF_EMPTY, 39 | DDR_IRQ_CH1_IBUF_FULL, 40 | DDR_IRQ_CH1_EBUF_NOT_EMPTY, 41 | DDR_IRQ_CH1_EBUF_FULL, 42 | DDR_IRQ_CH1_IBUF_OVERFLOW, 43 | DDR_IRQ_CH1_EBUF_OVERFLOW, 44 | } wddr_irq_t; 45 | 46 | // Fast IRQ Defintions (15 bus interrupts connected to MCU) 47 | typedef enum mcu_fast_irq_t 48 | { 49 | MCU_FAST_IRQ_HOST2PHY_REQ = 16, 50 | MCU_FAST_IRQ_PHY2HOST_ACK, 51 | MCU_FAST_IRQ_IBUF, 52 | MCU_FAST_IRQ_EBUF, 53 | MCU_FAST_IRQ_INIT_START, 54 | MCU_FAST_IRQ_INIT_COMPLETE, 55 | MCU_FAST_IRQ_LP_REQ, 56 | MCU_FAST_IRQ_PLL, 57 | MCU_FAST_IRQ_EXT_0, 58 | MCU_FAST_IRQ_EXT_1, 59 | MCU_FAST_IRQ_CTRLUPD_REQ, 60 | MCU_FAST_IRQ_PHYUPD_ACK, 61 | MCU_FAST_IRQ_PHYMSTR_ACK, 62 | MCU_FAST_IRQ_AHB_DET, 63 | MCU_FAST_IRQ_CH1, 64 | } mcu_fast_irq_t; 65 | 66 | #endif /* _WDDR_IRQ_MAP_H_ */ 67 | -------------------------------------------------------------------------------- /include/dev/wddr/phy_config.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _WDDR_PHY_CONFIG_H_ 7 | #define _WDDR_PHY_CONFIG_H_ 8 | #include 9 | 10 | // TODO: This should be generated by external script 11 | #define WDDR_PHY_BOOT_FREQ (0) 12 | #define WDDR_PHY_CFG (WDDR_PHY_CFG_DDR) 13 | #define WDDR_PHY_RANK (2) 14 | #define WDDR_PHY_DQ_SLICE_NUM (9) 15 | #define WDDR_PHY_DQS_SLICE_NUM (DQS_SLICE_NUM) 16 | #define WDDR_PHY_DQS_TXRX_SLICE_NUM (2) 17 | #define WDDR_PHY_CA_SLICE_NUM (CA_SLICE_NUM) 18 | #define WDDR_PHY_CK_SLICE_NUM (1) 19 | #define WDDR_PHY_CK_TXRX_SLICE_NUM (1) 20 | #define WDDR_PHY_DQ_BYTE_NUM (WDDR_DQ_BYTE_TOTAL) 21 | #define WDDR_PHY_CHANNEL_NUM (WDDR_CHANNEL_TOTAL) 22 | #define WDDR_PHY_MAX_FREQ_RATIO (WDDR_PHY_FREQ_RATIO_1TO2) 23 | 24 | #endif /* _WDDR_PHY_CONFIG_H_ */ 25 | -------------------------------------------------------------------------------- /include/dev/wddr/phy_defs.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _WDDR_PHY_DEFS_H_ 7 | #define _WDDR_PHY_DEFS_H_ 8 | 9 | #define WDDR_PHY_FREQ_RATIO_1TO1 (0) 10 | #define WDDR_PHY_FREQ_RATIO_1TO2 (1) 11 | #define WDDR_PHY_FREQ_RATIO_1TO4 (2) 12 | 13 | /** 14 | * @brief WDDR PHY Channel Index Enuemrations 15 | * 16 | * @details Enumerations for supported channels in 17 | * the DDR PHY. 18 | * 19 | * @note Each channel is composed of 2 DQ Blocks and 20 | * 1 CA Block. 21 | * 22 | * CHANNEL_0 Channel 0 index. 23 | * CHANNEL_1 Channel 1 index. 24 | */ 25 | typedef enum wddr_channel_t 26 | { 27 | WDDR_CHANNEL_0, 28 | WDDR_CHANNEL_1, 29 | WDDR_CHANNEL_TOTAL, 30 | } wddr_channel_t; 31 | 32 | /** 33 | * @brief WDDR PHY Configuration Enumerations 34 | * 35 | * @details Enumerations for supported PHY Hardware configurations. 36 | * 37 | * DDR mode used for LPDDR4/5 38 | * QDR mode used for GDDR6 39 | */ 40 | typedef enum wddr_phy_cfg_t 41 | { 42 | WDDR_PHY_CFG_DDR = 2, 43 | WDDR_PHY_CFG_QDR = 4, 44 | } wddr_phy_cfg_t; 45 | 46 | /** 47 | * @brief WDDR PHY Rank Index Enumerations 48 | * 49 | * @details Enumeration to specify rank index 50 | * 51 | * RANK_0 Rank 0 index. 52 | * RANK_1 Rank 1 index. 53 | */ 54 | typedef enum wddr_rank_t 55 | { 56 | WDDR_RANK_0 = 0, 57 | WDDR_RANK_1 = 1 58 | } wddr_rank_t; 59 | 60 | /** 61 | * @brief WDDR PHY DQ Byte Enumerations 62 | * 63 | * @details Specifies a DQ Byte index. 64 | * 65 | * DQ_BYTE_0 DQ Byte 0 index. 66 | * DQ_BYTE_1 DQ Byte 1 index. 67 | * 68 | */ 69 | typedef enum wddr_dq_byte_t 70 | { 71 | WDDR_DQ_BYTE_0, 72 | WDDR_DQ_BYTE_1, 73 | WDDR_DQ_BYTE_TOTAL, 74 | } wddr_dq_byte_t; 75 | 76 | /** 77 | * @brief WDDR PHY DQS Slice Enumerations 78 | * 79 | * @details Enumerations for which slice is assocaited with a particular 80 | * DQS signal. 81 | * 82 | * WCK 83 | * DQS DQ Strobe 84 | * REN Read Enable 85 | * OE Output Enable 86 | * IE Input Enable 87 | * RE Receive Enable 88 | * WCK_OE WCK Output Enable 89 | * WCS Write Chip Select 90 | * RCS Read Chip Select 91 | */ 92 | typedef enum wddr_dqs_slice_t 93 | { 94 | DQS_SLICE_WCK, 95 | DQS_SLICE_DQS, 96 | DQS_SLICE_REN, 97 | DQS_SLICE_OE, 98 | DQS_SLICE_IE, 99 | DQS_SLICE_RE, 100 | DQS_SLICE_WCK_OE, 101 | DQS_SLICE_WCS, 102 | DQS_SLICE_RCS, 103 | DQS_SLICE_NUM, 104 | } wddr_dqs_slice_t; 105 | 106 | /** 107 | * @brief WDDR PHY CA Slice Enumerations 108 | * 109 | * CA Command Address 110 | * CS_0 Chip Select 0 111 | * CS_1 Chip Select 1 112 | * CKE_0 CKE 0 113 | * CKE_1 CKE 1 114 | */ 115 | typedef enum wddr_ca_slice_t 116 | { 117 | CA_SLICE_CA = 6, 118 | CA_SLICE_CS_0, 119 | CA_SLICE_CS_1, 120 | CA_SLICE_CKE_0, 121 | CA_SLICE_CKE_1, 122 | CA_SLICE_NUM, 123 | } wddr_ca_slice_t; 124 | 125 | /** 126 | * @brief WDDR PHY Slice Type Enumerations 127 | * 128 | * @details Mapping of supported slice types. 129 | * 130 | * DQ Data 131 | * DQS Data Strobe 132 | * CA Command Address 133 | * CK Clock 134 | */ 135 | typedef enum wddr_slice_type_t 136 | { 137 | WDDR_SLICE_TYPE_DQ, 138 | WDDR_SLICE_TYPE_DQS, 139 | WDDR_SLICE_TYPE_CA, 140 | WDDR_SLICE_TYPE_CK, 141 | } wddr_slice_type_t; 142 | 143 | /** 144 | * @brief WDDR PHY Routing Mode Enumerations 145 | * 146 | * @details Supported Routing Modes. 147 | * 148 | * MISSION Normal mission routing mode. 149 | * EXTERNAL_LB External Loopback routing mode. 150 | */ 151 | typedef enum wddr_routing_mode_t 152 | { 153 | WDDR_ROUTING_MODE_MISSION, 154 | WDDR_ROUTING_MODE_EXTERNAL_LB, 155 | } wddr_routing_mode_t; 156 | 157 | /** 158 | * @brief WDDR PHY Mode Select Register (MSR) Enumerations 159 | * 160 | * @details Supported MSR Values. 161 | * 162 | * 0 Mode Set Register Value 0 163 | * 1 Mode Set Register Value 1 164 | */ 165 | typedef enum wddr_msr_t 166 | { 167 | WDDR_MSR_0, 168 | WDDR_MSR_1 169 | } wddr_msr_t; 170 | 171 | /** 172 | * @brief WDDR Frequency Ratio Enumeration 173 | * 174 | * @details DFI frequency to DRAM frequency ratio. 175 | * 176 | * 1TO1 1 DRAM tCK = (1 << 0) DFI tCK 177 | * 1TO2 1 DRAM tCK = (1 << 1) DFI tCK 178 | * 1TO4 1 DRAM tCK = (1 << 2) DFI tCK 179 | */ 180 | typedef enum wddr_freq_ratio_t 181 | { 182 | WDDR_FREQ_RATIO_1TO1 = WDDR_PHY_FREQ_RATIO_1TO1, 183 | WDDR_FREQ_RATIO_1TO2 = WDDR_PHY_FREQ_RATIO_1TO2, 184 | WDDR_FREQ_RATIO_1TO4 = WDDR_PHY_FREQ_RATIO_1TO4, 185 | } wddr_freq_ratio_t; 186 | 187 | #endif /* _WDDR_PHY_DEFS_H_ */ 188 | -------------------------------------------------------------------------------- /include/drivers/ca/ca_bscan.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CA_BSCAN_H_ 7 | #define _CA_BSCAN_H_ 8 | 9 | #include 10 | #include "ca_reg.h" 11 | 12 | /******************************************************************************* 13 | ** CA 14 | *******************************************************************************/ 15 | /** 16 | * @brief CA DQ BSCAN Get Status Register Interface 17 | * 18 | * @details Gets the CA slice BSCAN status. 19 | * 20 | * @param[in] ca_reg pointer to CA register space. 21 | * @param[out] status pointer to where to store bscan status. 22 | * 23 | * @return void. 24 | */ 25 | void ca_dq_bscan_get_status_reg_if(ca_reg_t *ca_reg, uint8_t *status); 26 | 27 | /******************************************************************************* 28 | ** CK 29 | *******************************************************************************/ 30 | /** 31 | * @brief CA DQS BSCAN Get Status Register Interface 32 | * 33 | * @details Gets the CK slice BSCAN status. 34 | * 35 | * @param[in] ca_reg pointer to CA register space. 36 | * @param[out] status pointer to where to store bscan status. 37 | * 38 | * @return void. 39 | */ 40 | void ca_dqs_bscan_get_status_reg_if(ca_reg_t *ca_reg, uint8_t *status); 41 | 42 | #endif /* _CA_BSCAN_H_ */ 43 | -------------------------------------------------------------------------------- /include/drivers/ca/ca_egress.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CA_EGRESS_H_ 7 | #define _CA_EGRESS_H_ 8 | 9 | #include 10 | #include "ca_reg.h" 11 | #include 12 | 13 | /******************************************************************************* 14 | ** CA 15 | *******************************************************************************/ 16 | /** 17 | * @brief CA DQ Egress Analog Set Mode Register Interface 18 | * 19 | * @details Sets Egress analog mode. 20 | * 21 | * @param[in] ca_reg pointer to CA register space. 22 | * @param[in] msr which MSR register set to use. 23 | * @param[in] bit which bit register set to use. 24 | * @param[in] mode egress mode to set. 25 | * 26 | * @return void 27 | */ 28 | void ca_dq_egress_ana_set_mode_reg_if(ca_reg_t *ca_reg, 29 | wddr_msr_t msr, 30 | uint8_t bit, 31 | egress_ana_mode_t mode); 32 | 33 | /** 34 | * @brief CA DQ Egress Digital Set Mode Register Interface 35 | * 36 | * @details Sets Egress digital mode. 37 | * 38 | * @param[in] ca_reg pointer to CA register space. 39 | * @param[in] msr which MSR register set to use. 40 | * @param[in] bit which bit register set to use. 41 | * @param[in] mode egress mode to set. 42 | * 43 | * @return void 44 | */ 45 | void ca_dq_egress_dig_set_mode_reg_if(ca_reg_t *ca_reg, 46 | wddr_msr_t msr, 47 | uint8_t bit, 48 | egress_dig_mode_t mode); 49 | 50 | /******************************************************************************* 51 | ** CK 52 | *******************************************************************************/ 53 | /** 54 | * @brief CA DQS Egress Analog Set Mode Register Interface 55 | * 56 | * @details Sets Egress analog mode. 57 | * 58 | * @param[in] ca_reg pointer to CA register space. 59 | * @param[in] msr which MSR register set to use. 60 | * @param[in] bit which bit register set to use. 61 | * @param[in] mode egress mode to set. 62 | * 63 | * @return void 64 | */ 65 | void ca_dqs_egress_ana_set_mode_reg_if(ca_reg_t *ca_reg, 66 | wddr_msr_t msr, 67 | uint8_t bit, 68 | egress_ana_mode_t mode); 69 | 70 | /** 71 | * @brief CA DQS Egress Digital Set Mode Register Interface 72 | * 73 | * @details Sets Egress digital mode. 74 | * 75 | * @param[in] ca_reg pointer to CA register space. 76 | * @param[in] msr which MSR register set to use. 77 | * @param[in] bit which bit register set to use. 78 | * @param[in] mode egress mode to set. 79 | * 80 | * @return void 81 | */ 82 | void ca_dqs_egress_dig_set_mode_reg_if(ca_reg_t *ca_reg, 83 | wddr_msr_t msr, 84 | uint8_t bit, 85 | egress_dig_mode_t mode); 86 | 87 | #endif /* _CA_EGRESS_H_ */ 88 | -------------------------------------------------------------------------------- /include/drivers/ca/ca_gearbox.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CA_GEARBOX_H_ 7 | #define _CA_GEARBOX_H_ 8 | 9 | #include 10 | #include "ca_reg.h" 11 | #include 12 | #include 13 | #include 14 | 15 | /******************************************************************************* 16 | ** CA 17 | *******************************************************************************/ 18 | /** 19 | * @brief CA DQ Receive (RX) Gearbox Set Mode Register Interface 20 | * 21 | * @details Configures RX Gearbox for given mode. 22 | * 23 | * @param[in] ca_reg pointer to CA register space. 24 | * @param[in] msr which MSR register set to use. 25 | * @param[in] cfg pointer to RX gearbox configuration. 26 | * 27 | * @return void 28 | */ 29 | void ca_dq_rx_gb_set_mode_reg_if(ca_reg_t *ca_reg, 30 | wddr_msr_t msr, 31 | const rx_gb_cfg_t *cfg); 32 | 33 | /******************************************************************************* 34 | ** CK 35 | *******************************************************************************/ 36 | /** 37 | * @brief CA DQ Receive (RX) Gearbox Set Mode Register Interface 38 | * 39 | * @details Configures RX Gearbox for given mode. 40 | * 41 | * @param[in] ca_reg pointer to CA register space. 42 | * @param[in] msr which MSR register set to use. 43 | * @param[in] cfg pointer to RX gearbox configuration. 44 | * 45 | * @return void 46 | */ 47 | void ca_dqs_rx_gb_set_mode_reg_if(ca_reg_t *ca_reg, 48 | wddr_msr_t msr, 49 | const rx_gb_cfg_t *cfg); 50 | 51 | /** 52 | * @brief CA DQ Transmit (TX) Gearbox Set Mode Register Interface 53 | * 54 | * @details Configures TX Gearbox for given mode. 55 | * 56 | * @param[in] ca_reg pointer to CA register space. 57 | * @param[in] msr which MSR register set to use. 58 | * @param[in] cfg pointer to TX gearbox configuration. 59 | * 60 | * @return void 61 | */ 62 | void ca_dqs_tx_gb_set_mode_reg_if(ca_reg_t *ca_reg, 63 | wddr_msr_t msr, 64 | const tx_gb_cfg_t *cfg); 65 | 66 | #endif /* _CA_GEARBOX_H_ */ 67 | -------------------------------------------------------------------------------- /include/drivers/ca/ca_lpde.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CA_LPDE_H_ 7 | #define _CA_LPDE_H_ 8 | 9 | #include 10 | #include "ca_reg.h" 11 | 12 | /******************************************************************************* 13 | ** CA 14 | *******************************************************************************/ 15 | /** 16 | * @brief CA DQ LPDE Set Configuration Register Interface 17 | * 18 | * @details Configures TX LPDE. 19 | * 20 | * @param[in] ca_reg pointer to CA register space. 21 | * @param[in] msr which MSR register set to use. 22 | * @param[in] rank which rank register set to use. 23 | * @param[in] bit which bit register set to use. 24 | * @param[in] enable flag to indicate if LPDE should be enabled. 25 | * @param[in] cfg raw LPDE configuration (code and gear). 26 | */ 27 | void ca_dq_lpde_set_cfg_reg_if(ca_reg_t *ca_reg, 28 | wddr_msr_t msr, 29 | wddr_rank_t rank, 30 | uint8_t bit, 31 | bool enable, 32 | uint32_t cfg); 33 | 34 | /******************************************************************************* 35 | ** CK 36 | *******************************************************************************/ 37 | /** 38 | * @brief CA DQS LPDE Set Configuration Register Interface 39 | * 40 | * @details Configures TX LPDE. 41 | * 42 | * @param[in] ca_reg pointer to CA register space. 43 | * @param[in] msr which MSR register set to use. 44 | * @param[in] rank which rank register set to use. 45 | * @param[in] bit which bit register set to use. 46 | * @param[in] enable flag to indicate if LPDE should be enabled. 47 | * @param[in] cfg raw LPDE configuration (code and gear). 48 | */ 49 | void ca_dqs_lpde_set_cfg_reg_if(ca_reg_t *ca_reg, 50 | wddr_msr_t msr, 51 | wddr_rank_t rank, 52 | uint8_t bit, 53 | bool enable, 54 | uint32_t cfg); 55 | 56 | /** 57 | * @brief CA DQS LPDE RX SDR Set Configuration Register Interface 58 | * 59 | * @details Configures RX SDR LPDE. 60 | * 61 | * @param[in] ca_reg pointer to CA register space. 62 | * @param[in] msr which MSR register set to use. 63 | * @param[in] rank which rank register set to use. 64 | * @param[in] bit which bit register set to use. 65 | * @param[in] enable flag to indicate if LPDE should be enabled. 66 | * @param[in] cfg raw LPDE configuration (code and gear). 67 | */ 68 | void ca_dqs_lpde_rx_sdr_set_cfg_reg_if(ca_reg_t *ca_reg, 69 | wddr_msr_t msr, 70 | wddr_rank_t rank, 71 | bool enable, 72 | uint32_t cfg); 73 | 74 | #endif /* _CA_LPDE_H_ */ 75 | -------------------------------------------------------------------------------- /include/drivers/ca/ca_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _CA_REG_H_ 8 | #define _CA_REG_H_ 9 | 10 | /* Standard includes. */ 11 | #include 12 | 13 | /** 14 | * @brief CA Register Layout 15 | * 16 | * @details Layout of register address space of CA CSRs. This structure should 17 | * be "overlayed" by pointing to the base address of a given CA byte. 18 | * 19 | * @note See hardware documentation for information about these registers. 20 | * 21 | * @todo Update MSR, RANK and bits with phy_config constants 22 | */ 23 | typedef struct ca_reg 24 | { 25 | volatile uint32_t DDR_CA_TOP_CFG; 26 | volatile uint32_t DDR_CA_TOP_STA; 27 | volatile uint32_t DDR_CA_DQ_RX_BSCAN_STA; 28 | volatile uint32_t DDR_CA_DQ_RX_CFG[2]; 29 | volatile uint32_t DDR_CA_DQ_RX_IO_CFG[2][2][11]; 30 | volatile uint32_t DDR_CA_DQ_RX_IO_STA; 31 | volatile uint32_t DDR_CA_DQ_RX_SA_CFG[2][2][11]; 32 | volatile uint32_t DDR_CA_DQ_RX_SA_DLY_CFG[2][2][11]; 33 | volatile uint32_t DDR_CA_DQ_RX_SA_STA[11]; 34 | volatile uint32_t DDR_CA_DQ_TX_BSCAN_CFG; 35 | volatile uint32_t DDR_CA_DQ_TX_EGRESS_ANA_CFG[2][11]; 36 | volatile uint32_t DDR_CA_DQ_TX_EGRESS_DIG_CFG[2][11]; 37 | volatile uint32_t DDR_CA_DQ_TX_ODR_PI_CFG[2][2]; 38 | volatile uint32_t DDR_CA_DQ_TX_QDR_PI_0_CFG[2][2]; 39 | volatile uint32_t DDR_CA_DQ_TX_QDR_PI_1_CFG[2][2]; 40 | volatile uint32_t DDR_CA_DQ_TX_DDR_PI_0_CFG[2][2]; 41 | volatile uint32_t DDR_CA_DQ_TX_DDR_PI_1_CFG[2][2]; 42 | volatile uint32_t DDR_CA_DQ_TX_PI_RT_CFG[2][2]; 43 | volatile uint32_t DDR_CA_DQ_TX_RT_CFG[2][2]; 44 | volatile uint32_t DDR_CA_DQ_TX_SDR_CFG[2][2][11]; 45 | volatile uint32_t DDR_CA_DQ_TX_SDR_X_SEL_CFG[2][2][11]; 46 | volatile uint32_t DDR_CA_DQ_TX_SDR_FC_DLY_CFG[2][2][11]; 47 | volatile uint32_t DDR_CA_DQ_TX_DDR_CFG[2][2][11]; 48 | volatile uint32_t DDR_CA_DQ_TX_DDR_X_SEL_CFG[2][2][11]; 49 | volatile uint32_t DDR_CA_DQ_TX_QDR_CFG[2][2][11]; 50 | volatile uint32_t DDR_CA_DQ_TX_QDR_X_SEL_CFG[2][2][11]; 51 | volatile uint32_t DDR_CA_DQ_TX_LPDE_CFG[2][2][11]; 52 | volatile uint32_t DDR_CA_DQ_TX_IO_CFG[2][11]; 53 | volatile uint32_t DDR_CA_DQS_RX_CFG[2]; 54 | volatile uint32_t DDR_CA_DQS_RX_BSCAN_STA; 55 | volatile uint32_t DDR_CA_DQS_RX_SDR_LPDE_CFG[2][2]; 56 | volatile uint32_t DDR_CA_DQS_RX_REN_PI_CFG[2][2]; 57 | volatile uint32_t DDR_CA_DQS_RX_RCS_PI_CFG[2][2]; 58 | volatile uint32_t DDR_CA_DQS_RX_RDQS_PI_0_CFG[2][2]; 59 | volatile uint32_t DDR_CA_DQS_RX_RDQS_PI_1_CFG[2][2]; 60 | volatile uint32_t DDR_CA_DQS_RX_PI_STA; 61 | volatile uint32_t DDR_CA_DQS_RX_IO_CFG[2][2][1]; 62 | volatile uint32_t DDR_CA_DQS_RX_IO_CMN_CFG[2][2]; 63 | volatile uint32_t DDR_CA_DQS_RX_IO_STA; 64 | volatile uint32_t DDR_CA_DQS_RX_SA_CFG[2][2][1]; 65 | volatile uint32_t DDR_CA_DQS_RX_SA_CMN_CFG; 66 | volatile uint32_t DDR_CA_DQS_TX_CFG[2]; 67 | volatile uint32_t DDR_CA_DQS_TX_BSCAN_CTRL_CFG; 68 | volatile uint32_t DDR_CA_DQS_TX_BSCAN_CFG; 69 | volatile uint32_t DDR_CA_DQS_TX_EGRESS_ANA_CFG[2][1]; 70 | volatile uint32_t DDR_CA_DQS_TX_EGRESS_DIG_CFG[2][1]; 71 | volatile uint32_t DDR_CA_DQS_TX_ODR_PI_CFG[2][2]; 72 | volatile uint32_t DDR_CA_DQS_TX_QDR_PI_0_CFG[2][2]; 73 | volatile uint32_t DDR_CA_DQS_TX_QDR_PI_1_CFG[2][2]; 74 | volatile uint32_t DDR_CA_DQS_TX_DDR_PI_0_CFG[2][2]; 75 | volatile uint32_t DDR_CA_DQS_TX_DDR_PI_1_CFG[2][2]; 76 | volatile uint32_t DDR_CA_DQS_TX_PI_RT_CFG[2][2]; 77 | volatile uint32_t DDR_CA_DQS_TX_SDR_PI_CFG[2][2]; 78 | volatile uint32_t DDR_CA_DQS_TX_DFI_PI_CFG[2][2]; 79 | volatile uint32_t DDR_CA_DQS_TX_RT_CFG[2][2]; 80 | volatile uint32_t DDR_CA_DQS_TX_SDR_CFG[2][2][1]; 81 | volatile uint32_t DDR_CA_DQS_TX_SDR_X_SEL_CFG[2][2][1]; 82 | volatile uint32_t DDR_CA_DQS_TX_SDR_FC_DLY_CFG[2][2][1]; 83 | volatile uint32_t DDR_CA_DQS_TX_DDR_CFG[2][2][1]; 84 | volatile uint32_t DDR_CA_DQS_TX_DDR_X_SEL_CFG[2][2][1]; 85 | volatile uint32_t DDR_CA_DQS_TX_QDR_CFG[2][2][1]; 86 | volatile uint32_t DDR_CA_DQS_TX_QDR_X_SEL_CFG[2][2][1]; 87 | volatile uint32_t DDR_CA_DQS_TX_LPDE_CFG[2][2][1]; 88 | volatile uint32_t DDR_CA_DQS_TX_IO_CFG[2][1]; 89 | volatile uint32_t DDR_CA_DQS_TX_IO_CMN_CFG[2][2]; 90 | } ca_reg_t; 91 | 92 | #endif /* _CA_REG_H_ */ 93 | -------------------------------------------------------------------------------- /include/drivers/ca/ca_top.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CA_TOP_H_ 7 | #define _CA_TOP_H_ 8 | 9 | #include 10 | #include "ca_reg.h" 11 | 12 | /** 13 | * @brief CA TOP Set Chip Select Register Interface 14 | * 15 | * @details Sets the read and write chip select value seen by the PHY. 16 | * 17 | * @param[in] ca_reg pointer to CA register space. 18 | * @param[in] rank_sel rank select value to override. 19 | * @param[in] override flag to indicate if CS should be overridden. 20 | * 21 | * @return void. 22 | */ 23 | void ca_top_set_chip_select_reg_if(ca_reg_t *ca_reg, 24 | wddr_rank_t rank_sel, 25 | bool override); 26 | 27 | /** 28 | * @brief CA TOP Clear FIFO Register Interface 29 | * 30 | * @details Clears receive fifo associated with CA. 31 | * 32 | * @param[in] ca_reg pointer to CA register space. 33 | * 34 | * @return void. 35 | */ 36 | void ca_top_clear_fifo_reg_if(ca_reg_t *ca_reg); 37 | 38 | /** 39 | * @brief CA TOP Get Chip Select Status Register Interface 40 | * 41 | * @details Return the current write (wcs) and read (rcs) chip select values. 42 | * 43 | * @param[in] ca_reg pointer to CA register space. 44 | * @param[out] wcs pointer to store write chip select status. 45 | * @param[out] rcs pointer to store read chip select status. 46 | * 47 | * @return void. 48 | */ 49 | void ca_top_get_chip_select_status_reg_if(ca_reg_t *ca_reg, 50 | uint8_t *wcs, 51 | uint8_t *rcs); 52 | 53 | #endif /* _CA_TOP_H_ */ 54 | -------------------------------------------------------------------------------- /include/drivers/ca/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CA_DRIVER_H_ 7 | #define _CA_DRIVER_H_ 8 | 9 | #include "ca_bscan.h" 10 | #include "ca_dp.h" 11 | #include "ca_driver.h" 12 | #include "ca_egress.h" 13 | #include "ca_gearbox.h" 14 | #include "ca_lpde.h" 15 | #include "ca_pi.h" 16 | #include "ca_reg.h" 17 | #include "ca_top.h" 18 | #include 19 | 20 | #endif /* _CA_DRIVER_H_ */ 21 | -------------------------------------------------------------------------------- /include/drivers/cmn/cmn_clk.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_CLK_H_ 7 | #define _CMN_CLK_H_ 8 | 9 | #include 10 | #include "cmn_reg.h" 11 | 12 | /** 13 | * @brief Common Clock Control Set PLL0 Clock Divider Reset Enable Register Interface 14 | * 15 | * @details Sets whether the PLL0 clock divider reset is enabled. 16 | * 17 | * @param[in] cmn_reg pointer to CTRL register space. 18 | * @param[in] enable flag to indicate if pll clock divider 19 | * reset is enabled. 20 | * 21 | * @return void 22 | */ 23 | void cmn_clk_ctrl_set_pll0_div_clk_rst_reg_if(cmn_reg_t *cmn_reg, bool enable); 24 | 25 | /** 26 | * @brief Clock Common Control Set GFCM Enable Register Interface 27 | * 28 | * @details Sets GFCM Enable via CSR. 29 | * 30 | * @param[in] cmn_reg pointer to CTRL register space. 31 | * @param[in] enable flag to indicate if GFM should be enabled. 32 | * 33 | * @return void 34 | */ 35 | void cmn_clk_ctrl_set_gfcm_en_reg_if(cmn_reg_t *cmn_reg, bool enable); 36 | 37 | /** 38 | * @brief Clock Common Control Set PLL0 Clock Divider Enable Register Interface 39 | * 40 | * @details Sets PLL0 Clock Divider Enable via CSR. 41 | * 42 | * @param[in] cmn_reg pointer to CTRL register space. 43 | * @param[in] enable flag to indicate if pll clock divider should be 44 | * enabled. 45 | * 46 | * @return void 47 | */ 48 | void cmn_clk_ctrl_set_pll0_div_clk_en_reg_if(cmn_reg_t *cmn_reg, bool enable); 49 | 50 | #endif /* _CMN_CLK_H_ */ 51 | -------------------------------------------------------------------------------- /include/drivers/cmn/cmn_ibias.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_IBIAS_H_ 7 | #define _CMN_IBIAS_H_ 8 | 9 | #include "cmn_reg.h" 10 | 11 | /** 12 | * @brief Bias Current Device State 13 | * 14 | * DISABLE Bias Current Device disabled. 15 | * ENABLE Bias Current Device enabled. 16 | */ 17 | typedef enum ibias_state_t 18 | { 19 | IBIAS_STATE_DISABLE, 20 | IBIAS_STATE_ENABLE, 21 | } ibias_state_t; 22 | 23 | /** 24 | * @brief Common Bias Current Set State Register Interface 25 | * 26 | * @details Sets the state of the bias current. 27 | * 28 | * @param[in] cmn_reg pointer to CTRL register space. 29 | * @param[in] state state requested to change to. 30 | * 31 | * @return void 32 | */ 33 | void cmn_ibias_set_state_reg_if(cmn_reg_t *cmn_reg, ibias_state_t state); 34 | 35 | #endif /* _CMN_IBIAS_H_ */ 36 | -------------------------------------------------------------------------------- /include/drivers/cmn/cmn_pmon.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_PMON_H_ 7 | #define _CMN_PMON_H_ 8 | 9 | #include "cmn_reg.h" 10 | 11 | /** 12 | * @brief PMON State Enumerations 13 | * 14 | * DISABLED PMON Disabled. 15 | * ENABLED PMON Enabled. 16 | */ 17 | typedef enum pmon_state_t 18 | { 19 | PMON_STATE_DISABLED, 20 | PMON_STATE_ENABLED, 21 | } pmon_state_t; 22 | 23 | /** 24 | * @brief Common Process Monitor Set State Register Interface 25 | * 26 | * @details Sets the process monitor state. 27 | * 28 | * @param[in] cmn_reg pointer to CTRL register space. 29 | * @param[in] state state requested to change to. 30 | * 31 | * @return void. 32 | */ 33 | void cmn_pmon_set_state_reg_if(cmn_reg_t *cmn_reg, pmon_state_t state); 34 | 35 | /** 36 | * @brief Common Process Monitor Configure Register Interface 37 | * 38 | * @details Configures process monitor. 39 | * 40 | * @param[in] cmn_reg pointer to CTRL register space. 41 | * @param[in] refcount number of refclks to sample for. 42 | * @param[in] init_wait number of refclks to wait before starting. 43 | * 44 | * @return void 45 | */ 46 | void cmn_pmon_configure_reg_if(cmn_reg_t *cmn_reg, 47 | uint16_t refcount, 48 | uint8_t init_wait); 49 | 50 | /** 51 | * @brief Common Process Monitor Get Status Count Register Interface 52 | * 53 | * @details Gets status count of process monitor. 54 | * 55 | * @param[in] cmn_reg pointer to CTRL register space. 56 | * @param[out] count pointer to store current status count. 57 | * 58 | * @return void 59 | */ 60 | void cmn_pmon_get_status_count_reg_if(cmn_reg_t *cmn_reg, uint32_t *count); 61 | 62 | #endif /* _CMN_PMON_H_ */ 63 | -------------------------------------------------------------------------------- /include/drivers/cmn/cmn_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _CMN_REG_H_ 8 | #define _CMN_REG_H_ 9 | 10 | /* Standard includes. */ 11 | #include 12 | 13 | /** 14 | * @brief Common Register Layout 15 | * 16 | * @details Layout of register address space of CMN CSRs. This structure should 17 | * be "overlayed" by pointing to the base address of CMN register 18 | * space in the memory map. 19 | * 20 | * @note See hardware documentation for information about these registers. 21 | */ 22 | typedef struct cmn_reg 23 | { 24 | volatile uint32_t reserved0[2]; 25 | volatile uint32_t DDR_CMN_VREF_CFG[2]; 26 | volatile uint32_t DDR_CMN_ZQCAL_CFG; 27 | volatile uint32_t DDR_CMN_ZQCAL_STA; 28 | volatile uint32_t DDR_CMN_IBIAS_CFG; 29 | volatile uint32_t DDR_CMN_TEST_CFG; 30 | volatile uint32_t DDR_CMN_LDO_CFG[2]; 31 | volatile uint32_t DDR_CMN_CLK_CTRL_CFG; 32 | volatile uint32_t reserved1[3]; 33 | volatile uint32_t DDR_CMN_PMON_ANA_CFG; 34 | volatile uint32_t DDR_CMN_PMON_DIG_CFG; 35 | volatile uint32_t DDR_CMN_PMON_DIG_NAND_CFG; 36 | volatile uint32_t DDR_CMN_PMON_DIG_NOR_CFG; 37 | volatile uint32_t DDR_CMN_PMON_NAND_STA; 38 | volatile uint32_t DDR_CMN_PMON_NOR_STA; 39 | volatile uint32_t DDR_CMN_CLK_STA; 40 | volatile uint32_t DDR_CMN_RSTN_CFG; 41 | volatile uint32_t DDR_CMN_RSTN_STA; 42 | } cmn_reg_t; 43 | 44 | #endif /* _CMN_REG_H_ */ 45 | -------------------------------------------------------------------------------- /include/drivers/cmn/cmn_rstn.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_RSTN_H_ 7 | #define _CMN_RSTN_H_ 8 | 9 | #include "cmn_reg.h" 10 | 11 | /** 12 | * @brief Common RESETN Set Pin Register Interface 13 | * 14 | * @details Sets the state of the RESETN pin to the DRAM. Driving RESETN high 15 | * releases the RESET of the DRAM chip. 16 | * 17 | * @param[in] cmn_reg pointer to CTRL register space. 18 | * @param[in] override flag to indicate if SW should override RESETN poin 19 | * state. 20 | * @param[in] high flag to indicate if RESETN pin should be driven 21 | * high. 22 | * 23 | * @return void. 24 | */ 25 | void cmn_rstn_set_pin_reg_if(cmn_reg_t *cmn_reg, bool override, bool high); 26 | 27 | /** 28 | * @brief Common RESETN Get Pin Register Interface 29 | * 30 | * @details Gets the value of RESETN loopack. 31 | * 32 | * @param[in] cmn_reg pointer to CTRL register space. 33 | * @param[in] rstn_lb RESETN loopback value. 34 | * 35 | * @return void. 36 | */ 37 | void cmn_rstn_get_loopback_reg_if(cmn_reg_t *cmn_reg, uint8_t *rstn_lb); 38 | 39 | #endif /* _CMN_RSTN_H_ */ 40 | -------------------------------------------------------------------------------- /include/drivers/cmn/cmn_vref.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_VREF_H_ 7 | #define _CMN_VREF_H_ 8 | 9 | #include "cmn_reg.h" 10 | #include 11 | #include 12 | 13 | /** 14 | * @brief Voltage Reference State Enumeration 15 | * 16 | * DISABLED Disabled state. 17 | * HIZ Hi-Z state. 18 | * ENABLED Enabled state. 19 | */ 20 | typedef enum vref_state_t 21 | { 22 | VREF_STATE_DISABLED, 23 | VREF_STATE_HIZ, 24 | VREF_STATE_ENABLED 25 | } vref_state_t; 26 | 27 | /** 28 | * @brief Common Voltage Reference Set State Register Interface 29 | * 30 | * @details Sets the state of the voltage reference. 31 | * 32 | * @param[in] cmn_reg pointer to CTRL register space. 33 | * @param[in] msr which msr register set to use. 34 | * @param[in] state state to set. 35 | * 36 | * @return void. 37 | */ 38 | void cmn_vref_set_state_reg_if(cmn_reg_t *cmn_reg, 39 | wddr_msr_t msr, 40 | vref_state_t state); 41 | 42 | /** 43 | * @brief Common Voltage Reference Set Code Register Interface 44 | * 45 | * @details Sets the code (level) of the voltage reference. 46 | * 47 | * @param[in] cmn_reg pointer to CTRL register space. 48 | * @param[in] msr which msr register set to use. 49 | * @param[in] code code to set. 50 | * 51 | * @return void. 52 | */ 53 | void cmn_vref_set_code_reg_if(cmn_reg_t *cmn_reg, 54 | wddr_msr_t msr, 55 | uint32_t code); 56 | 57 | /** 58 | * @brief Common Voltage Reference Set Power Mode Register Interface 59 | * 60 | * @details Sets the power mode of the voltage reference. 61 | * 62 | * @param[in] cmn_reg pointer to CTRL register space. 63 | * @param[in] msr which msr register set to use. 64 | * @param[in] pwr_mode power mode to set. 65 | * 66 | * @return void. 67 | */ 68 | void cmn_vref_set_pwr_mode_reg_if(cmn_reg_t *cmn_reg, 69 | wddr_msr_t msr, 70 | vref_pwr_mode_t pwr_mode); 71 | 72 | #endif /* _CMN_VREF_H_ */ 73 | -------------------------------------------------------------------------------- /include/drivers/cmn/cmn_zqcal.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_ZQCAL_H_ 7 | #define _CMN_ZQCAL_H_ 8 | 9 | #include "cmn_reg.h" 10 | #include 11 | 12 | /** 13 | * @brief ZQCAL State Enumeration 14 | * 15 | * DISABLED Disabled state. 16 | * ENABLED Enabled state. 17 | */ 18 | typedef enum zqcal_state_t 19 | { 20 | ZQCAL_STATE_DISABLED, 21 | ZQCAL_STATE_ENABLED 22 | } zqcal_state_t; 23 | 24 | /** 25 | * @brief ZQCAL Mode Enumeration 26 | * 27 | * ZQCAL_MODE_PULL_UP Pull up (p side). 28 | * ZQCAL_MODE_PULL_DOWN Pull down (n side). 29 | */ 30 | typedef enum zqcal_mode_t 31 | { 32 | ZQCAL_MODE_PULL_UP, 33 | ZQCAL_MODE_PULL_DOWN 34 | } zqcal_mode_t; 35 | 36 | /** 37 | * @brief Common ZQCAL Set State Register Interface 38 | * 39 | * @details Sets the state of ZQCAL. 40 | * 41 | * @param[in] cmn_reg pointer to CTRL register space. 42 | * @param[in] state state to set. 43 | * 44 | * @return void. 45 | */ 46 | void cmn_zqcal_set_state_reg_if(cmn_reg_t *cmn_reg, zqcal_state_t state); 47 | 48 | /** 49 | * @brief Common ZQCAL Set Mode Register Interface 50 | * 51 | * @details Sets the mode of ZQCAL. 52 | * 53 | * @param[in] cmn_reg pointer to CTRL register space. 54 | * @param[in] mode mode to set. 55 | * 56 | * @return void. 57 | */ 58 | void cmn_zqcal_set_mode_reg_if(cmn_reg_t *cmn_reg, zqcal_mode_t mode); 59 | 60 | /** 61 | * @brief Common ZQCAL Set Code Register Interface 62 | * 63 | * @details Sets the code of ZQCAL given current mode. 64 | * 65 | * @param[in] cmn_reg pointer to CTRL register space. 66 | * @param[in] mode mode of zqcal. Determines if P or N code is set. 67 | * @param[in] code code to set. 68 | * 69 | * @return void. 70 | */ 71 | void cmn_zqcal_set_code_reg_if(cmn_reg_t *cmn_reg, zqcal_mode_t mode, uint8_t code); 72 | 73 | /** 74 | * @brief Common ZQCAL Set VOH Register Interface 75 | * 76 | * @details Sets the VOH of ZQCAL. 77 | * 78 | * @param[in] cmn_reg pointer to CTRL register space. 79 | * @param[in] voh voh to set. 80 | * 81 | * @return void. 82 | */ 83 | void cmn_zqcal_set_voh_reg_if(cmn_reg_t *cmn_reg, zqcal_voh_t voh); 84 | 85 | /** 86 | * @brief Common ZQCAL Get Comparator Ouptut Register Interface 87 | * 88 | * @details Gets the comparator output result of ZQCAL. 89 | * 90 | * @param[in] cmn_reg pointer to CTRL register space. 91 | * @param[out] val pointer of where to store comparator value. 92 | * 93 | * @return void 94 | */ 95 | void cmn_zqcal_get_output_reg_if(cmn_reg_t *cmn_reg, uint8_t *val); 96 | 97 | #endif /* _CMN_ZQCAL_H_ */ 98 | -------------------------------------------------------------------------------- /include/drivers/cmn/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CMN_DRIVER_H_ 7 | #define _CMN_DRIVER_H_ 8 | 9 | #include "cmn_clk.h" 10 | #include "cmn_ibias.h" 11 | #include "cmn_pmon.h" 12 | #include "cmn_reg.h" 13 | #include "cmn_rstn.h" 14 | #include "cmn_vref.h" 15 | #include "cmn_zqcal.h" 16 | #include 17 | 18 | #endif /* _CMN_DRIVER_H_ */ 19 | -------------------------------------------------------------------------------- /include/drivers/ctrl/ctrl_clk.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CTRL_CLK_H_ 7 | #define _CTRL_CLK_H_ 8 | 9 | #include 10 | #include "ctrl_reg.h" 11 | 12 | /** 13 | * @brief MCU Clock Glitch Free Mux Select Enumeration 14 | * 15 | * REFCLK MCU Clock Source is Refclk. 16 | * PLL_VCO0 MCU Clock Source is PLL VCO0. 17 | */ 18 | typedef enum clk_mcu_gfm_sel_t 19 | { 20 | CLK_MCU_GFM_SEL_REFCLK, 21 | CLK_MCU_GFM_SEL_PLL_VCO0, 22 | } clk_mcu_gfm_sel_t; 23 | 24 | /** 25 | * @brief Control Clock Set PLL Clock Enable Register Interface 26 | * 27 | * @details Sets PLL clock enable. 28 | * 29 | * @param[in] ctrl_reg pointer to CTRL register space. 30 | * @param[in] enable flag to indicate if pll clock should be enabled. 31 | * 32 | * @return void 33 | */ 34 | void ctrl_clk_set_pll_clk_en_reg_if(ctrl_reg_t *ctrl_reg, bool enable); 35 | 36 | /** 37 | * @brief Control Clock Set MCU GFM Select Register Interface 38 | * 39 | * @details Sets MCU GFM Select. 40 | * 41 | * @param[in] ctrl_reg pointer to CTRL register space. 42 | * @param[in] sel desired MCU GFM clock select value. 43 | * 44 | * @return void 45 | */ 46 | void ctrl_clk_set_mcu_gfm_sel_reg_if(ctrl_reg_t *ctrl_reg, 47 | clk_mcu_gfm_sel_t sel); 48 | 49 | /** 50 | * @brief Control Clock Get MCU GFM Select Status Register Interface 51 | * 52 | * @details Gets MCU GFM selection. 53 | * 54 | * @param[in] ctrl_reg pointer to CTRL register space. 55 | * @param[in] gfm_sel0 pointer to store gfm_sel0 value. 56 | * @param[in] gfm_sel1 pointer to store gfm_sel1 value. 57 | * 58 | * @return void 59 | */ 60 | void ctrl_clk_get_mcu_gfm_sel_status_reg_if(ctrl_reg_t *ctrl_reg, 61 | uint8_t *gfm_sel0, 62 | uint8_t *gfm_sel1); 63 | /** 64 | * @brief Control Clock Get DFI Clock Status Register Interface 65 | * 66 | * @details Gets DFI Clock status. 67 | * 68 | * @param[in] ctrl_reg pointer to CTRL register space. 69 | * @param[in] dfi_clk_on pointer to store status of DFI clock. 70 | * 71 | * @return void 72 | */ 73 | void ctrl_clk_get_dfi_clk_status_reg_if(ctrl_reg_t *ctrl_reg, 74 | uint8_t *dfi_clk_on); 75 | 76 | #endif /* _CTRL_CLK_H_ */ 77 | -------------------------------------------------------------------------------- /include/drivers/ctrl/ctrl_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _CTRL_REG_H_ 8 | #define _CTRL_REG_H_ 9 | 10 | /* Standard includes. */ 11 | #include 12 | 13 | /** 14 | * @brief Control Register Layout 15 | * 16 | * @details Layout of register address space of CTRL CSRs. This structure should 17 | * be "overlayed" by pointing to the base address of CTRL register 18 | * space in the memory map. 19 | * 20 | * @note See hardware documentation for information about these registers. 21 | */ 22 | typedef struct ctrl_reg 23 | { 24 | volatile uint32_t DDR_CTRL_CLK_CFG; 25 | volatile uint32_t DDR_CTRL_CLK_STA; 26 | volatile uint32_t DDR_CTRL_AHB_SNOOP_CFG; 27 | volatile uint32_t DDR_CTRL_AHB_SNOOP_STA; 28 | volatile uint32_t DDR_CTRL_AHB_SNOOP_DATA_STA; 29 | volatile uint32_t DDR_CTRL_AHB_SNOOP_PATTERN_CFG; 30 | volatile uint32_t DDR_CTRL_AHB_SNOOP_PATTERN_0_CFG; 31 | volatile uint32_t DDR_CTRL_AHB_SNOOP_PATTERN_1_CFG; 32 | volatile uint32_t DDR_CTRL_AHB_SNOOP_PATTERN_STA; 33 | volatile uint32_t DDR_CTRL_DEBUG_CFG; 34 | volatile uint32_t DDR_CTRL_DEBUG1_CFG; 35 | } ctrl_reg_t; 36 | 37 | #endif /* _CTRL_REG_H_ */ 38 | -------------------------------------------------------------------------------- /include/drivers/ctrl/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CTRL_DRIVER_H_ 7 | #define _CTRL_DRIVER_H_ 8 | 9 | #include "ctrl_clk.h" 10 | #include 11 | 12 | #endif /* _CTRL_DRIVER_H_ */ 13 | -------------------------------------------------------------------------------- /include/drivers/dfi/dfi_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _DFI_REG_H_ 8 | #define _DFI_REG_H_ 9 | 10 | /* Standard includes. */ 11 | #include 12 | 13 | /** 14 | * @brief DFI Register Layout 15 | * 16 | * @details Layout of register address space of DFI CSRs. This structure should 17 | * be "overlayed" by pointing to the base address of DFI register 18 | * space in the memory map. 19 | * 20 | * @note See hardware documentation for information about these registers. 21 | */ 22 | typedef struct dfi_reg 23 | { 24 | volatile uint32_t DDR_DFI_TOP_0_CFG; 25 | volatile uint32_t DDR_DFI_DATA_BIT_ENABLE_CFG; 26 | volatile uint32_t DDR_DFI_PHYFREQ_RANGE_CFG; 27 | volatile uint32_t DDR_DFI_STATUS_IF_CFG; 28 | volatile uint32_t DDR_DFI_STATUS_IF_STA; 29 | volatile uint32_t DDR_DFI_STATUS_IF_EVENT_0_CFG; 30 | volatile uint32_t DDR_DFI_STATUS_IF_EVENT_1_CFG; 31 | volatile uint32_t DDR_DFI_CTRLUPD_IF_CFG; 32 | volatile uint32_t DDR_DFI_CTRLUPD_IF_STA; 33 | volatile uint32_t DDR_DFI_CTRLUPD_IF_EVENT_0_CFG; 34 | volatile uint32_t DDR_DFI_CTRLUPD_IF_EVENT_1_CFG; 35 | volatile uint32_t DDR_DFI_LP_CTRL_IF_CFG; 36 | volatile uint32_t DDR_DFI_LP_CTRL_IF_STA; 37 | volatile uint32_t DDR_DFI_LP_CTRL_IF_EVENT_0_CFG; 38 | volatile uint32_t DDR_DFI_LP_CTRL_IF_EVENT_1_CFG; 39 | volatile uint32_t DDR_DFI_LP_DATA_IF_CFG; 40 | volatile uint32_t DDR_DFI_LP_DATA_IF_STA; 41 | volatile uint32_t DDR_DFI_LP_DATA_IF_EVENT_0_CFG; 42 | volatile uint32_t DDR_DFI_LP_DATA_IF_EVENT_1_CFG; 43 | volatile uint32_t DDR_DFI_PHYUPD_IF_CFG; 44 | volatile uint32_t DDR_DFI_PHYUPD_IF_STA; 45 | volatile uint32_t DDR_DFI_PHYMSTR_IF_CFG; 46 | volatile uint32_t DDR_DFI_PHYMSTR_IF_STA; 47 | volatile uint32_t DDR_DFI_DEBUG_CFG; 48 | } dfi_reg_t; 49 | 50 | #endif /* _DFI_REG_H_ */ 51 | -------------------------------------------------------------------------------- /include/drivers/dfi/dfi_ret.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _DFI_RET_H_ 8 | #define _DFI_RET_H_ 9 | 10 | /** 11 | * @brief DFI Return Type Enumerations 12 | * 13 | * SUCCESS no error. 14 | * ERROR general error. 15 | * ERROR_FIFO_FULL error that fifo is full. 16 | * ERROR_FIFO_EMPTY error that fifo is empty. 17 | */ 18 | typedef enum { 19 | DFI_SUCCESS, 20 | DFI_ERROR, 21 | DFI_ERROR_FIFO_FULL, 22 | DFI_ERROR_FIFO_EMPTY, 23 | } dfi_return_t; 24 | 25 | #endif /* _DFI_RET_H_ */ 26 | -------------------------------------------------------------------------------- /include/drivers/dfi/dfi_top.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DFI_TOP_H_ 7 | #define _DFI_TOP_H_ 8 | 9 | #include "dfi_reg.h" 10 | 11 | /** 12 | * @brief DFI Set CA Loopback Select Register Interface 13 | * 14 | * @details Selects which channel is used for CA loopback. 15 | * 16 | * 17 | * @param[in] dfi_reg pointer to DFI register space. 18 | * @param[in] channel_sel which channel to select. 19 | * 20 | * @return void. 21 | */ 22 | void dfi_set_ca_loopback_sel_reg_if(dfi_reg_t *dfi_reg, 23 | uint8_t channel_sel); 24 | 25 | #endif /* _DFI_TOP_H_ */ 26 | -------------------------------------------------------------------------------- /include/drivers/dfi/dfich_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _DFICH_REG_H_ 8 | #define _DFICH_REG_H_ 9 | 10 | /* Standard includes. */ 11 | #include 12 | 13 | /** 14 | * @brief DFICH Register Layout 15 | * 16 | * @details Layout of register address space of DFICH CSRs. This structure should 17 | * be "overlayed" by pointing to the base address of DFICH register 18 | * space in the memory map. 19 | * 20 | * @note See hardware documentation for information about these registers. 21 | */ 22 | typedef struct dfich_reg 23 | { 24 | volatile uint32_t DDR_DFICH_TOP_1_CFG; 25 | volatile uint32_t DDR_DFICH_TOP_2_CFG; 26 | volatile uint32_t DDR_DFICH_TOP_3_CFG; 27 | volatile uint32_t DDR_DFICH_TOP_STA; 28 | volatile uint32_t DDR_DFICH_IG_DATA_CFG; 29 | volatile uint32_t DDR_DFICH_EG_DATA_STA; 30 | volatile uint32_t DDR_DFICH_WRC_CFG[2]; 31 | volatile uint32_t DDR_DFICH_WRCCTRL_CFG[2]; 32 | volatile uint32_t DDR_DFICH_CKCTRL_CFG[2]; 33 | volatile uint32_t DDR_DFICH_RDC_CFG[2]; 34 | volatile uint32_t DDR_DFICH_RCTRL_CFG[2]; 35 | volatile uint32_t DDR_DFICH_WCTRL_CFG[2]; 36 | volatile uint32_t DDR_DFICH_WENCTRL_CFG[2]; 37 | volatile uint32_t DDR_DFICH_WCKCTRL_CFG[2]; 38 | volatile uint32_t DDR_DFICH_WRD_CFG[2]; 39 | volatile uint32_t DDR_DFICH_RDD_CFG[2]; 40 | volatile uint32_t DDR_DFICH_CTRL0_CFG[2]; 41 | volatile uint32_t DDR_DFICH_CTRL1_CFG[2]; 42 | volatile uint32_t DDR_DFICH_CTRL2_CFG[2]; 43 | volatile uint32_t DDR_DFICH_CTRL3_CFG[2]; 44 | volatile uint32_t DDR_DFICH_CTRL4_CFG[2]; 45 | volatile uint32_t DDR_DFICH_CTRL5_CFG[2]; 46 | } dfich_reg_t; 47 | 48 | #endif /* _DFICH_REG_H_ */ 49 | -------------------------------------------------------------------------------- /include/drivers/dfi/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DFI_DRIVER_H_ 7 | #define _DFI_DRIVER_H_ 8 | 9 | #include "dfi_dp.h" 10 | #include "dfi_fifo.h" 11 | #include "dfi_intf.h" 12 | #include "dfi_ret.h" 13 | #include "dfi_top.h" 14 | #include 15 | #include 16 | 17 | #endif /* _DFI_DRIVER_H_ */ 18 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_bscan.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_BSCAN_H_ 7 | #define _DQ_BSCAN_H_ 8 | 9 | #include 10 | #include "dq_reg.h" 11 | 12 | /******************************************************************************* 13 | ** DQ 14 | *******************************************************************************/ 15 | /** 16 | * @brief DQ DQ BSCAN Get Status Register Interface 17 | * 18 | * @details Gets the DQ slice BSCAN status. 19 | * 20 | * @param[in] dq_reg pointer to DQ Byte register space. 21 | * @param[out] status pointer to where to store bscan status. 22 | * 23 | * @return void. 24 | */ 25 | void dq_dq_bscan_get_status_reg_if(dq_reg_t *dq_reg, uint8_t *status); 26 | 27 | /******************************************************************************* 28 | ** DQS 29 | *******************************************************************************/ 30 | /** 31 | * @brief DQ DQS BSCAN Get Status Register Interface 32 | * 33 | * @details Gets the DQS slice BSCAN status. 34 | * 35 | * @param[in] dq_reg pointer to DQ Byte register space. 36 | * @param[out] status pointer to where to store bscan status. 37 | * 38 | * @return void. 39 | */ 40 | void dq_dqs_bscan_get_status_reg_if(dq_reg_t *dq_reg, uint8_t *status); 41 | 42 | #endif /* _DQ_BSCAN_H_ */ 43 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_egress.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_EGRESS_H_ 7 | #define _DQ_EGRESS_H_ 8 | 9 | #include 10 | #include "dq_reg.h" 11 | #include 12 | 13 | /******************************************************************************* 14 | ** DQ 15 | *******************************************************************************/ 16 | /** 17 | * @brief DQ DQ Egress Analog Set Mode Register Interface 18 | * 19 | * @details Sets Egress analog mode. 20 | * 21 | * @param[in] dq_reg pointer to DQ Byte register space. 22 | * @param[in] msr which MSR register set to use. 23 | * @param[in] bit which bit register set to use. 24 | * @param[in] mode egress mode to set. 25 | * 26 | * @return void 27 | */ 28 | void dq_dq_egress_ana_set_mode_reg_if(dq_reg_t *dq_reg, 29 | wddr_msr_t msr, 30 | uint8_t bit, 31 | egress_ana_mode_t mode); 32 | 33 | /** 34 | * @brief DQ DQ Egress Digital Set Mode Register Interface 35 | * 36 | * @details Sets Egress digital mode. 37 | * 38 | * @param[in] dq_reg pointer to DQ Byte register space. 39 | * @param[in] msr which MSR register set to use. 40 | * @param[in] bit which bit register set to use. 41 | * @param[in] mode egress mode to set. 42 | * 43 | * @return void 44 | */ 45 | void dq_dq_egress_dig_set_mode_reg_if(dq_reg_t *dq_reg, 46 | wddr_msr_t msr, 47 | uint8_t bit, 48 | egress_dig_mode_t mode); 49 | 50 | /******************************************************************************* 51 | ** DQS 52 | *******************************************************************************/ 53 | /** 54 | * @brief DQ DQS Egress Analog Set Mode Register Interface 55 | * 56 | * @details Sets Egress analog mode. 57 | * 58 | * @param[in] dq_reg pointer to DQ Byte register space. 59 | * @param[in] msr which MSR register set to use. 60 | * @param[in] bit which bit register set to use. 61 | * @param[in] mode egress mode to set. 62 | * 63 | * @return void 64 | */ 65 | void dq_dqs_egress_ana_set_mode_reg_if(dq_reg_t *dq_reg, 66 | wddr_msr_t msr, 67 | uint8_t bit, 68 | egress_ana_mode_t mode); 69 | 70 | /** 71 | * @brief DQ DQS Egress Digital Set Mode Register Interface 72 | * 73 | * @details Sets Egress digital mode. 74 | * 75 | * @param[in] dq_reg pointer to DQ Byte register space. 76 | * @param[in] msr which MSR register set to use. 77 | * @param[in] bit which bit register set to use. 78 | * @param[in] mode egress mode to set. 79 | * 80 | * @return void 81 | */ 82 | void dq_dqs_egress_dig_set_mode_reg_if(dq_reg_t *dq_reg, 83 | wddr_msr_t msr, 84 | uint8_t bit, 85 | egress_dig_mode_t mode); 86 | 87 | #endif /* _DQ_EGRESS_H_ */ 88 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_gearbox.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_GEARBOX_H_ 7 | #define _DQ_GEARBOX_H_ 8 | 9 | #include 10 | #include "dq_reg.h" 11 | #include 12 | #include 13 | #include 14 | 15 | /******************************************************************************* 16 | ** DQ 17 | *******************************************************************************/ 18 | /** 19 | * @brief DQ DQ Receive (RX) Gearbox Set Mode Register Interface 20 | * 21 | * @details Configures RX Gearbox for given mode. 22 | * 23 | * @param[in] dq_reg pointer to DQ Byte register space. 24 | * @param[in] msr which MSR register set to use. 25 | * @param[in] cfg pointer to RX gearbox configuration. 26 | * 27 | * @return void 28 | */ 29 | void dq_dq_rx_gb_set_mode_reg_if(dq_reg_t *dq_reg, 30 | wddr_msr_t msr, 31 | const rx_gb_cfg_t *cfg); 32 | 33 | /******************************************************************************* 34 | ** DQS 35 | *******************************************************************************/ 36 | /** 37 | * @brief DQ DQS Receive (RX) Gearbox Set Mode Register Interface 38 | * 39 | * @details Configures RX Gearbox for given mode. 40 | * 41 | * @param[in] dq_reg pointer to DQ Byte register space. 42 | * @param[in] msr which MSR register set to use. 43 | * @param[in] cfg pointer to RX gearbox configuration. 44 | * 45 | * @return void 46 | */ 47 | void dq_dqs_rx_gb_set_mode_reg_if(dq_reg_t *dq_reg, 48 | wddr_msr_t msr, 49 | const rx_gb_cfg_t *cfg); 50 | 51 | /** 52 | * @brief DQ DQS Transmit (TX) Gearbox Set Mode Register Interface 53 | * 54 | * @details Configures TX Gearbox for given mode. 55 | * 56 | * @param[in] dq_reg pointer to DQ Byte register space. 57 | * @param[in] msr which MSR register set to use. 58 | * @param[in] cfg pointer to TX gearbox configuration. 59 | * 60 | * @return void 61 | */ 62 | void dq_dqs_tx_gb_set_mode_reg_if(dq_reg_t *dq_reg, 63 | wddr_msr_t msr, 64 | const tx_gb_cfg_t *cfg); 65 | #endif /* _DQ_GEARBOX_H_ */ 66 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_lpde.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_LPDE_H_ 7 | #define _DQ_LPDE_H_ 8 | 9 | #include 10 | #include "dq_reg.h" 11 | 12 | /******************************************************************************* 13 | ** DQ 14 | *******************************************************************************/ 15 | /** 16 | * @brief DQ DQ LPDE Set Configuration Register Interface 17 | * 18 | * @details Configures TX LPDE. 19 | * 20 | * @param[in] dq_reg pointer to DQ Byte register space. 21 | * @param[in] msr which MSR register set to use. 22 | * @param[in] rank which rank register set to use. 23 | * @param[in] bit which bit register set to use. 24 | * @param[in] enable flag to indicate if LPDE should be enabled. 25 | * @param[in] cfg raw LPDE configuration (code and gear). 26 | */ 27 | void dq_dq_lpde_set_cfg_reg_if(dq_reg_t *dq_reg, 28 | wddr_msr_t msr, 29 | wddr_rank_t rank, 30 | uint8_t bit, 31 | bool enable, 32 | uint32_t cfg); 33 | 34 | /******************************************************************************* 35 | ** DQS 36 | *******************************************************************************/ 37 | /** 38 | * @brief DQ DQS LPDE Set Configuration Register Interface 39 | * 40 | * @details Configures TX LPDE. 41 | * 42 | * @param[in] dq_reg pointer to DQ Byte register space. 43 | * @param[in] msr which MSR register set to use. 44 | * @param[in] rank which rank register set to use. 45 | * @param[in] bit which bit register set to use. 46 | * @param[in] enable flag to indicate if LPDE should be enabled. 47 | * @param[in] cfg raw LPDE configuration (code and gear). 48 | */ 49 | void dq_dqs_lpde_set_cfg_reg_if(dq_reg_t *dq_reg, 50 | wddr_msr_t msr, 51 | wddr_rank_t rank, 52 | uint8_t bit, 53 | bool enable, 54 | uint32_t cfg); 55 | 56 | /** 57 | * @brief DQ DQS LPDE RX SDR Set Configuration Register Interface 58 | * 59 | * @details Configures RX SDR LPDE. 60 | * 61 | * @param[in] dq_reg pointer to DQ Byte register space. 62 | * @param[in] msr which MSR register set to use. 63 | * @param[in] rank which rank register set to use. 64 | * @param[in] enable flag to indicate if LPDE should be enabled. 65 | * @param[in] cfg raw LPDE configuration (code and gear). 66 | */ 67 | void dq_dqs_lpde_rx_sdr_set_cfg_reg_if(dq_reg_t *dq_reg, 68 | wddr_msr_t msr, 69 | wddr_rank_t rank, 70 | bool enable, 71 | uint32_t cfg); 72 | 73 | #endif /* _DQ_LPDE_H_ */ 74 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_receiver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_RECEIVER_H_ 7 | #define _DQ_RECEIVER_H_ 8 | 9 | #include 10 | #include "dq_reg.h" 11 | #include 12 | 13 | /** 14 | * @brief Receiver State Enumerations 15 | * 16 | * @details Supported Receiver States. 17 | * 18 | * DISABLE receiver not operational. 19 | * CAL receiver in calibration mode. 20 | * ENABLE receiver is enabled. 21 | */ 22 | typedef enum receiver_state_t 23 | { 24 | REC_STATE_DISABLE, 25 | REC_STATE_CAL, 26 | REC_STATE_ENABLE 27 | } receiver_state_t; 28 | 29 | /******************************************************************************* 30 | ** DQS 31 | *******************************************************************************/ 32 | /** 33 | * @brief DQ DQS Receiver Set State Register Interface 34 | * 35 | * @details Sets the state of the receiver. 36 | * 37 | * @param[in] dq_reg pointer to DQ Byte register space. 38 | * @param[in] msr which MSR register set to use. 39 | * @param[in] rank which rank register set to use. 40 | * @param[in] state state to set. 41 | * 42 | * @return void 43 | */ 44 | void dq_dqs_receiver_set_state_reg_if(dq_reg_t *dq_reg, 45 | wddr_msr_t msr, 46 | wddr_rank_t rank, 47 | receiver_state_t state); 48 | 49 | /** 50 | * @brief DQ DQS Receiver Set Mode Register Interface 51 | * 52 | * @details Sets the mode of the receiver. 53 | * 54 | * @param[in] dq_reg pointer to DQ Byte register space. 55 | * @param[in] msr which MSR register set to use. 56 | * @param[in] rank which rank register set to use. 57 | * @param[in] mode mode to set. 58 | * @param[in] path_state path state to set. 59 | * 60 | * @return void 61 | */ 62 | void dq_dqs_receiver_set_mode_reg_if(dq_reg_t *dq_reg, 63 | wddr_msr_t msr, 64 | wddr_rank_t rank, 65 | receiver_mode_t mode, 66 | receiver_path_state_t path_state); 67 | 68 | /** 69 | * @brief DQ DQS Receiver Set Code Register Interface 70 | * 71 | * @details Sets the calibration codes of the receiver. 72 | * 73 | * @param[in] dq_reg pointer to DQ Byte register space. 74 | * @param[in] msr which MSR register set to use. 75 | * @param[in] rank which rank register set to use. 76 | * @param[in] code codes to set for PN and TC side. 77 | * 78 | * @return void 79 | */ 80 | void dq_dqs_receiver_set_code_reg_if(dq_reg_t *dq_reg, 81 | wddr_msr_t msr, 82 | wddr_rank_t rank, 83 | uint8_t code[REC_PN_SIDE_NUM][REC_TC_SIDE_NUM]); 84 | 85 | /** 86 | * @brief DQ DQS Receiver Set Feedback Resistor Register Interface 87 | * 88 | * @details Sets the feedback resistor of the receiver. 89 | * 90 | * @param[in] dq_reg pointer to DQ Byte register space. 91 | * @param[in] msr which MSR register set to use. 92 | * @param[in] rank which rank register set to use. 93 | * @param[in] feedback_resistor feedback resistor value to set. 94 | * 95 | * @return void 96 | */ 97 | void dq_dqs_receiver_set_feedback_resistor_reg_if(dq_reg_t *dq_reg, 98 | wddr_msr_t msr, 99 | wddr_rank_t rank, 100 | uint8_t feedback_resistor); 101 | 102 | /** 103 | * @brief DQ DQS Receiver Set Delay Register Interface 104 | * 105 | * @details Sets the delay of the receiver. 106 | * 107 | * @param[in] dq_reg pointer to DQ Byte register space. 108 | * @param[in] msr which MSR register set to use. 109 | * @param[in] rank which rank register set to use. 110 | * @param[in] rank which bit register set to use. 111 | * @param[in] delay delay value to set. 112 | * @param[in] side which side of receiver to delay. 113 | * 114 | * @return void 115 | */ 116 | void dq_dqs_receiver_set_delay_reg_if(dq_reg_t *dq_reg, 117 | wddr_msr_t msr, 118 | wddr_rank_t rank, 119 | uint8_t bit, 120 | uint16_t delay, 121 | receiver_tc_side_mask_t side); 122 | 123 | #endif /* _DQ_RECEIVER_H_ */ 124 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _DQ_REG_H_ 8 | #define _DQ_REG_H_ 9 | 10 | /* Standard includes. */ 11 | #include 12 | 13 | /** 14 | * @brief DQ Register Layout 15 | * 16 | * @details Layout of register address space of DQ CSRs. This structure should 17 | * be "overlayed" by pointing to the base address of a given DQ byte. 18 | * 19 | * @note See hardware documentation for information about these registers. 20 | * 21 | * @todo Update MSR, RANK and bits with phy_config constants 22 | */ 23 | typedef struct dq_reg 24 | { 25 | volatile uint32_t DDR_DQ_TOP_CFG; 26 | volatile uint32_t DDR_DQ_TOP_STA; 27 | volatile uint32_t DDR_DQ_DQ_RX_BSCAN_STA; 28 | volatile uint32_t DDR_DQ_DQ_RX_CFG[2]; 29 | volatile uint32_t DDR_DQ_DQ_RX_IO_CFG[2][2][9]; 30 | volatile uint32_t DDR_DQ_DQ_RX_IO_STA; 31 | volatile uint32_t DDR_DQ_DQ_RX_SA_CFG[2][2][9]; 32 | volatile uint32_t DDR_DQ_DQ_RX_SA_DLY_CFG[2][2][9]; 33 | volatile uint32_t DDR_DQ_DQ_RX_SA_STA[9]; 34 | volatile uint32_t DDR_DQ_DQ_TX_BSCAN_CFG; 35 | volatile uint32_t DDR_DQ_DQ_TX_EGRESS_ANA_CFG[2][9]; 36 | volatile uint32_t DDR_DQ_DQ_TX_EGRESS_DIG_CFG[2][9]; 37 | volatile uint32_t DDR_DQ_DQ_TX_ODR_PI_CFG[2][2]; 38 | volatile uint32_t DDR_DQ_DQ_TX_QDR_PI_0_CFG[2][2]; 39 | volatile uint32_t DDR_DQ_DQ_TX_QDR_PI_1_CFG[2][2]; 40 | volatile uint32_t DDR_DQ_DQ_TX_DDR_PI_0_CFG[2][2]; 41 | volatile uint32_t DDR_DQ_DQ_TX_DDR_PI_1_CFG[2][2]; 42 | volatile uint32_t DDR_DQ_DQ_TX_PI_RT_CFG[2][2]; 43 | volatile uint32_t DDR_DQ_DQ_TX_RT_CFG[2][2]; 44 | volatile uint32_t DDR_DQ_DQ_TX_SDR_CFG[2][2][9]; 45 | volatile uint32_t DDR_DQ_DQ_TX_SDR_X_SEL_CFG[2][2][9]; 46 | volatile uint32_t DDR_DQ_DQ_TX_SDR_FC_DLY_CFG[2][2][9]; 47 | volatile uint32_t DDR_DQ_DQ_TX_DDR_CFG[2][2][9]; 48 | volatile uint32_t DDR_DQ_DQ_TX_DDR_X_SEL_CFG[2][2][9]; 49 | volatile uint32_t DDR_DQ_DQ_TX_QDR_CFG[2][2][9]; 50 | volatile uint32_t DDR_DQ_DQ_TX_QDR_X_SEL_CFG[2][2][9]; 51 | volatile uint32_t DDR_DQ_DQ_TX_LPDE_CFG[2][2][9]; 52 | volatile uint32_t DDR_DQ_DQ_TX_IO_CFG[2][9]; 53 | volatile uint32_t DDR_DQ_DQS_RX_CFG[2]; 54 | volatile uint32_t DDR_DQ_DQS_RX_BSCAN_STA; 55 | volatile uint32_t DDR_DQ_DQS_RX_SDR_LPDE_CFG[2][2]; 56 | volatile uint32_t DDR_DQ_DQS_RX_REN_PI_CFG[2][2]; 57 | volatile uint32_t DDR_DQ_DQS_RX_RCS_PI_CFG[2][2]; 58 | volatile uint32_t DDR_DQ_DQS_RX_RDQS_PI_0_CFG[2][2]; 59 | volatile uint32_t DDR_DQ_DQS_RX_RDQS_PI_1_CFG[2][2]; 60 | volatile uint32_t DDR_DQ_DQS_RX_PI_STA; 61 | volatile uint32_t DDR_DQ_DQS_RX_IO_CFG[2][2][2]; 62 | volatile uint32_t DDR_DQ_DQS_RX_IO_CMN_CFG[2][2]; 63 | volatile uint32_t DDR_DQ_DQS_RX_IO_STA; 64 | volatile uint32_t DDR_DQ_DQS_RX_SA_CFG[2][2][2]; 65 | volatile uint32_t DDR_DQ_DQS_RX_SA_CMN_CFG; 66 | volatile uint32_t DDR_DQ_DQS_TX_CFG[2]; 67 | volatile uint32_t DDR_DQ_DQS_TX_BSCAN_CTRL_CFG; 68 | volatile uint32_t DDR_DQ_DQS_TX_BSCAN_CFG; 69 | volatile uint32_t DDR_DQ_DQS_TX_EGRESS_ANA_CFG[2][9]; 70 | volatile uint32_t DDR_DQ_DQS_TX_EGRESS_DIG_CFG[2][9]; 71 | volatile uint32_t DDR_DQ_DQS_TX_ODR_PI_CFG[2][2]; 72 | volatile uint32_t DDR_DQ_DQS_TX_QDR_PI_0_CFG[2][2]; 73 | volatile uint32_t DDR_DQ_DQS_TX_QDR_PI_1_CFG[2][2]; 74 | volatile uint32_t DDR_DQ_DQS_TX_DDR_PI_0_CFG[2][2]; 75 | volatile uint32_t DDR_DQ_DQS_TX_DDR_PI_1_CFG[2][2]; 76 | volatile uint32_t DDR_DQ_DQS_TX_PI_RT_CFG[2][2]; 77 | volatile uint32_t DDR_DQ_DQS_TX_SDR_PI_CFG[2][2]; 78 | volatile uint32_t DDR_DQ_DQS_TX_DFI_PI_CFG[2][2]; 79 | volatile uint32_t DDR_DQ_DQS_TX_RT_CFG[2][2]; 80 | volatile uint32_t DDR_DQ_DQS_TX_SDR_CFG[2][2][9]; 81 | volatile uint32_t DDR_DQ_DQS_TX_SDR_X_SEL_CFG[2][2][9]; 82 | volatile uint32_t DDR_DQ_DQS_TX_SDR_FC_DLY_CFG[2][2][9]; 83 | volatile uint32_t DDR_DQ_DQS_TX_DDR_CFG[2][2][9]; 84 | volatile uint32_t DDR_DQ_DQS_TX_DDR_X_SEL_CFG[2][2][9]; 85 | volatile uint32_t DDR_DQ_DQS_TX_QDR_CFG[2][2][9]; 86 | volatile uint32_t DDR_DQ_DQS_TX_QDR_X_SEL_CFG[2][2][9]; 87 | volatile uint32_t DDR_DQ_DQS_TX_LPDE_CFG[2][2][2]; 88 | volatile uint32_t DDR_DQ_DQS_TX_IO_CFG[2][2]; 89 | volatile uint32_t DDR_DQ_DQS_TX_IO_CMN_CFG[2][2]; 90 | } dq_reg_t; 91 | 92 | #endif /* _DQ_REG_H_ */ 93 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_sa.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_SA_H_ 7 | #define _DQ_SA_H_ 8 | 9 | #include 10 | #include "dq_reg.h" 11 | #include 12 | 13 | /** 14 | * @brief Sense Amp (Sensamp) State Enumerations 15 | * 16 | * @details Enumerations for valid states that Sensamp device an be in. 17 | * 18 | * DYNAMIC sensamp device dynamically controlled by PHY logic. 19 | * ENABLED sensamp device forced enable. 20 | * CAL_ENABELED sensamp device forced enable and in calibration mode. 21 | */ 22 | typedef enum sensamp_state_t 23 | { 24 | SA_STATE_DYNAMIC, 25 | SA_STATE_ENABLED, 26 | SA_STATE_CAL_ENABLED 27 | } sensamp_state_t; 28 | 29 | /******************************************************************************* 30 | ** DQ 31 | *******************************************************************************/ 32 | /** 33 | * @brief DQ DQ Sensamp Get Status Register Interface 34 | * 35 | * @details Retrieves current status of the sensamp associated with a given bit. 36 | * 37 | * @param[in] dq_reg pointer to DQ Byte register space. 38 | * @param[in] bit which bit register set to use. 39 | * @param[in] sa_index which sa index to get status from. 40 | * @param[out] status pointer to where to store status. 41 | * 42 | * @return void 43 | */ 44 | void dq_dq_sa_get_status_reg_if(dq_reg_t *dq_reg, 45 | uint8_t bit, 46 | sensamp_index_t sa_index, 47 | uint8_t *status); 48 | 49 | /** 50 | * @brief DQ DQ Sensamp Clear Cal Code Register Interface 51 | * 52 | * @details Clears stored calibration code for all SA indices. 53 | * 54 | * @param[in] dq_reg pointer to DQ Byte register space. 55 | * @param[in] msr which MSR register set to use. 56 | * @param[in] rank which rank register set to use. 57 | * @param[in] bit which bit register set to use. 58 | * 59 | * @return void. 60 | */ 61 | void dq_dq_sa_clear_cal_code_reg_if(dq_reg_t *dq_reg, 62 | wddr_msr_t msr, 63 | wddr_rank_t rank, 64 | uint8_t bit); 65 | 66 | /** 67 | * @brief DQ DQ Sensamp Set Cal Code Register Interface 68 | * 69 | * @details Sets stored calibration code for given SA index. 70 | * 71 | * @param[in] dq_reg pointer to DQ Byte register space. 72 | * @param[in] msr which MSR register set to use. 73 | * @param[in] rank which rank register set to use. 74 | * @param[in] bit which bit register set to use. 75 | * @param[in] sa_index which SA index to set. 76 | * @param[in] code calibration code to set. 77 | * 78 | * @return void. 79 | */ 80 | void dq_dq_sa_set_cal_code_reg_if(dq_reg_t *dq_reg, 81 | wddr_msr_t msr, 82 | wddr_rank_t rank, 83 | uint8_t bit, 84 | sensamp_index_t sa_index, 85 | uint8_t code); 86 | 87 | /******************************************************************************* 88 | ** DQS 89 | *******************************************************************************/ 90 | /** 91 | * @brief DQ DQS Sensamp Set State Register Interface 92 | * 93 | * @details Sets state for all Sensamps for the given byte. 94 | * 95 | * @param[in] dq_reg pointer to DQ Byte register space. 96 | * @param[in] state state to set. 97 | * 98 | * @return void. 99 | */ 100 | void dq_dqs_sa_cmn_set_state_reg_if(dq_reg_t *dq_reg, 101 | sensamp_state_t state); 102 | 103 | #endif /* _DQ_SA_H_ */ 104 | -------------------------------------------------------------------------------- /include/drivers/dq/dq_top.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_TOP_H_ 7 | #define _DQ_TOP_H_ 8 | 9 | #include 10 | #include "dq_reg.h" 11 | 12 | /** 13 | * @brief DQ TOP Set Chip Select Register Interface 14 | * 15 | * @details Sets the read and write chip select value seen by the PHY. 16 | * 17 | * @param[in] dq_reg pointer to DQ Byte register space. 18 | * @param[in] rank_sel rank select value to override. 19 | * @param[in] override flag to indicate if CS should be overridden. 20 | * 21 | * @return void. 22 | */ 23 | void dq_top_set_chip_select_reg_if(dq_reg_t *dq_reg, 24 | wddr_rank_t rank_sel, 25 | bool override); 26 | 27 | /** 28 | * @brief DQ TOP Clear FIFO Register Interface 29 | * 30 | * @details Clears receive fifo associated with DQ Byte. 31 | * 32 | * @param[in] dq_reg pointer to DQ Byte register space. 33 | * 34 | * @return void. 35 | */ 36 | void dq_top_clear_fifo_reg_if(dq_reg_t *dq_reg); 37 | 38 | /** 39 | * @brief DQ TOP Get Chip Select Status Register Interface 40 | * 41 | * @details Return the current write (wcs) and read (rcs) chip select values. 42 | * 43 | * @param[in] dq_reg pointer to DQ Byte register space. 44 | * @param[out] wcs pointer to store write chip select status. 45 | * @param[out] rcs pointer to store read chip select status. 46 | * 47 | * @return void. 48 | */ 49 | void dq_top_get_chip_select_status_reg_if(dq_reg_t *dq_reg, 50 | uint8_t *wcs, 51 | uint8_t *rcs); 52 | 53 | #endif /* _DQ_TOP_H_ */ 54 | -------------------------------------------------------------------------------- /include/drivers/dq/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DQ_DRIVER_H_ 7 | #define _DQ_DRIVER_H_ 8 | 9 | #include "dq_bscan.h" 10 | #include "dq_dp.h" 11 | #include "dq_driver.h" 12 | #include "dq_egress.h" 13 | #include "dq_gearbox.h" 14 | #include "dq_lpde.h" 15 | #include "dq_pi.h" 16 | #include "dq_receiver.h" 17 | #include "dq_sa.h" 18 | #include "dq_top.h" 19 | #include 20 | 21 | #endif /* _DQ_DRIVER_H_ */ 22 | -------------------------------------------------------------------------------- /include/drivers/fsw/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _FSW_DRIVER_H_ 7 | #define _FSW_DRIVER_H_ 8 | 9 | #include "fsw_ctrl.h" 10 | #include "fsw_csp.h" 11 | #include 12 | 13 | #endif /* _FSW_DRIVER_H_ */ 14 | -------------------------------------------------------------------------------- /include/drivers/fsw/fsw_csp.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _FSW_CSP_H_ 7 | #define _FSW_CSP_H_ 8 | 9 | #include "fsw_reg.h" 10 | 11 | /** 12 | * @brief HW Frequency Switch (FSW) Clock Disable Override Register Interface 13 | * 14 | * @details Sets the override value of FSW CSP Clock Disable via CSR. 15 | * 16 | * @param[in] fsw_reg pointer to frequency switch register space. 17 | * @param[in] enable desired override state. 18 | * 19 | * @return void 20 | */ 21 | void fsw_csp_set_clk_disable_over_val_reg_if(fsw_reg_t *fsw_reg, 22 | bool enable); 23 | 24 | /** 25 | * @brief HW Frequency Switch (FSW) CSP Sync Register Interface 26 | * 27 | * @details Performs CSP Sync procedure via CSR. 28 | * 29 | * @param[in] fsw_reg pointer to frequency switch register space. 30 | * 31 | * @return void 32 | */ 33 | void fsw_csp_sync_reg_if(fsw_reg_t *fsw_reg); 34 | 35 | #endif /* _FSW_CSP_H_ */ 36 | -------------------------------------------------------------------------------- /include/drivers/fsw/fsw_ctrl.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _FSW_CTRL_H_ 7 | #define _FSW_CTRL_H_ 8 | 9 | #include 10 | #include "fsw_reg.h" 11 | 12 | /** 13 | * @brief HW Frequency Switch (FSW) MSR/VCO Value Override Register Interface 14 | * 15 | * @details Sets the override value of MSR and VCO via CSR. 16 | * 17 | * @param[in] fsw_reg pointer to frequency switch register space. 18 | * @param[in] msr desired MSR override. 19 | * @param[in] vco_id desired VCO ID override. 20 | * 21 | * @return void. 22 | */ 23 | void fsw_ctrl_set_msr_vco_ovr_val_reg_if(fsw_reg_t *fsw_reg, 24 | uint8_t msr, 25 | uint8_t vco_id); 26 | 27 | /** 28 | * @brief HW Frequency Switch (FSW) MSR/VCO Override Register Interface 29 | * 30 | * @details Sets the override enable of MSR and VCO via CSR. 31 | * 32 | * @param[in] fsw_reg pointer to frequency switch register space. 33 | * @param[in] enable desired override state. 34 | * 35 | * @return void. 36 | */ 37 | void fsw_ctrl_set_msr_vco_ovr_reg_if(fsw_reg_t *fsw_reg, bool enable); 38 | 39 | /** 40 | * @brief HW Frequency Switch (FSW) MSR Toggle Enable Register Interface 41 | * 42 | * @details Sets if MSR toggle should be enabled during frequency switch. 43 | * 44 | * @param[in] fsw_reg pointer to frequency switch register space. 45 | * @param[in] enable desired toggle state. 46 | * 47 | * @return void. 48 | */ 49 | void fsw_ctrl_set_msr_toggle_en_reg_if(fsw_reg_t *fsw_reg, bool enable); 50 | 51 | /** 52 | * @brief HW Frequency Switch (FSW) VCO Toggle Enable Register Interface 53 | * 54 | * @details Sets if VCO toggle should be enabled during frequency switch. 55 | * 56 | * @param[in] fsw_reg pointer to frequency switch register space. 57 | * @param[in] enable desired toggle state. 58 | * 59 | * @return void. 60 | */ 61 | void fsw_ctrl_set_vco_toggle_en_reg_if(fsw_reg_t *fsw_reg, bool enable); 62 | 63 | /** 64 | * @brief HW Frequency Switch (FSW) Set Prep Done Register Interface 65 | * 66 | * @details Sets PREP_DONE state via CSR. 67 | * 68 | * @param[in] fsw_reg pointer to frequency switch register space. 69 | * @param[in] done state of prep. 70 | * 71 | * @return void. 72 | */ 73 | void fsw_ctrl_set_prep_done_reg_if(fsw_reg_t *fsw_reg, bool done); 74 | 75 | /** 76 | * @brief HW Frequency Switch (FSW) Set Post Work Done Register Interface 77 | * 78 | * @details Sets the Post Work Done status and override state via CSR. 79 | * 80 | * @param[in] fsw_reg pointer to frequency switch register space. 81 | * @param[in] override state of override. 82 | * @param[in] done state of post work done. 83 | * 84 | * @return void. 85 | */ 86 | void fsw_ctrl_set_post_work_done_reg_if(fsw_reg_t *fsw_reg, 87 | bool override, 88 | bool done); 89 | 90 | /** 91 | * @brief HW Frequency Switch Get Current MSR Register Interface 92 | * 93 | * @details Gets the current Mode Switch Register (MSR) in the PHY. 94 | * 95 | * @param[in] fsw_reg pointer to frequency switch register space. 96 | * 97 | * @return returns current Mode Switch Register value. 98 | * @retval Possible MSRs values are 0 and 1. 99 | */ 100 | uint8_t fsw_ctrl_get_current_msr_reg_if(fsw_reg_t *fsw_reg); 101 | 102 | #endif /* _FSW_CTRL_H_ */ 103 | -------------------------------------------------------------------------------- /include/drivers/fsw/fsw_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | 7 | #ifndef _FSW_REG_H_ 8 | #define _FSW_REG_H_ 9 | 10 | /* Standard includes. */ 11 | #include 12 | 13 | /** 14 | * @brief FSW Register Layout 15 | * 16 | * @details Layout of register address space of FSW CSRs. This structure should 17 | * be "overlayed" by pointing to the base address of FSW register space 18 | * in the memory map. 19 | * 20 | * @note See hardware documentation for information about these registers. 21 | */ 22 | typedef struct fsw_reg 23 | { 24 | volatile uint32_t DDR_FSW_CTRL_CFG; 25 | volatile uint32_t DDR_FSW_CTRL_STA; 26 | volatile uint32_t DDR_FSW_DEBUG_CFG; 27 | volatile uint32_t reserved0[8]; 28 | volatile uint32_t DDR_FSW_CSP_0_CFG; 29 | volatile uint32_t DDR_FSW_CSP_1_CFG; 30 | volatile uint32_t DDR_FSW_CSP_STA; 31 | } fsw_reg_t; 32 | 33 | #endif /* _FSW_REG_H_ */ 34 | -------------------------------------------------------------------------------- /include/drivers/pll/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PLL_DRIVER_H_ 7 | #define _PLL_DRIVER_H_ 8 | #include 9 | #include 10 | 11 | /** 12 | * @brief Phase Lock Loop (PLL) Initialization Register Interface 13 | * 14 | * @details Initializes PLL device at register interface level. 15 | * 16 | * @param[in] pll pointer to PLL device. 17 | * @param[in] base base address of PLL device. 18 | * 19 | * @return void 20 | */ 21 | void pll_init_reg_if(pll_dev_t *pll, uint32_t base); 22 | 23 | /** 24 | * @brief Phase Lock Loop (PLL) Reset Register Interface 25 | * 26 | * @details Takes PLL device out of reset. 27 | * 28 | * @param[in] pll pointer to PLL device. 29 | * 30 | * @return void 31 | */ 32 | void pll_reset_reg_if(pll_dev_t *pll); 33 | 34 | /** 35 | * @brief Phase Lock Loop (PLL) Set VCO Selection Register Interface 36 | * 37 | * @details Sets the VCO that PLL should move to on next switch. 38 | * 39 | * @param[in] pll pointer to PLL device. 40 | * @param[in] vco_id id of the VCO device to select. 41 | * 42 | * @return void 43 | */ 44 | void pll_set_vco_sel_reg_if(pll_dev_t *pll, vco_index_t vco_id); 45 | 46 | /** 47 | * @brief Phase Lock Loop (PLL) Switch VCO Register Interface 48 | * 49 | * @details Performs switch of PLL to next VCO configured via 50 | * pll_set_vco_sel_reg_if. 51 | * 52 | * @param[in] pll pointer to PLL device. 53 | * 54 | * @return void 55 | */ 56 | void pll_switch_vco_reg_if(pll_dev_t *pll); 57 | 58 | #endif /* _PLL_DRIVER_H_ */ 59 | -------------------------------------------------------------------------------- /include/drivers/wddr/driver.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _WDDR_DRIVER_H_ 7 | #define _WDDR_DRIVER_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief Wavious DDR (WDDR) Clear FIFO Register Interface 14 | * 15 | * @details Clears FIFOs in all channels. 16 | * 17 | * @param[in] wddr pointer to WDDR device. 18 | * @param[in] channel channel to set. 19 | * 20 | * @return void 21 | */ 22 | void wddr_clear_fifo_reg_if(wddr_dev_t *wddr, wddr_channel_t channel); 23 | 24 | /** 25 | * @brief Wavious DDR (WDDR) Set RESETN Pin Register Interface 26 | * 27 | * @details Sets the state of the RESETN pin to the DRAM. Driving RESETN high 28 | * releases the RESET of the DRAM chip. 29 | * 30 | * @param[in] wddr pointer to WDDR device. 31 | * @param[in] override flag to indicate if SW should override RESETN pin 32 | * state. 33 | * @param[in] high flag to indicate if RESETN pin should be driven 34 | * high. 35 | * 36 | * @return void 37 | */ 38 | void wddr_set_dram_resetn_pin_reg_if(wddr_dev_t *wddr, 39 | bool override, 40 | bool high); 41 | 42 | /** 43 | * @brief Wavious DDR (WDDR) Set Chip Select Register Interface 44 | * 45 | * @details Sets the state of Write and Read Chip Select for all channels. 46 | * 47 | * @param[in] wddr pointer to WDDR device. 48 | * @param[in] channel channel to set. 49 | * @param[in] override flag to indicate if SW should override CS state. 50 | * @param[in] rank rank / chipselect value to set. 51 | * 52 | * @return void 53 | */ 54 | void wddr_set_chip_select_reg_if(wddr_dev_t *wddr, 55 | wddr_channel_t channel, 56 | wddr_rank_t rank, 57 | bool override); 58 | 59 | /** 60 | * @brief Wavious DDR (WDDR) Read Boundary Scan Result Register Interface 61 | * 62 | * @details Reads the boundary scan value for specified dq_byte and channel. 63 | * 64 | * @param[in] wddr pointer to WDDR device. 65 | * @param[in] dq_byte dq_byte to read bscan for. 66 | * @param[in] channel channel to read bscan for. 67 | * @param[out] result pointer to store bscan result in. 68 | * 69 | * @return void 70 | */ 71 | void wddr_read_bscan_result_reg_if(wddr_dev_t *wddr, 72 | wddr_dq_byte_t dq_byte, 73 | wddr_channel_t channel, 74 | uint8_t *result); 75 | 76 | #endif /* _WDDR_DRIVER_H_ */ 77 | -------------------------------------------------------------------------------- /include/drivers/wddr/memory_map.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _WDDR_MEMORY_MAP_H_ 7 | #define _WDDR_MEMORY_MAP_H_ 8 | 9 | #include 10 | #include "ddr_ca_csr.h" 11 | #include "ddr_cmn_csr.h" 12 | #include "ddr_ctrl_csr.h" 13 | #include "ddr_dfi_csr.h" 14 | #include "ddr_dfich_csr.h" 15 | #include "ddr_dq_csr.h" 16 | #include "ddr_mvp_pll_csr.h" 17 | #include "ddr_fsw_csr.h" 18 | 19 | // Common MCU registers (same for all Wavious MCUs) 20 | #define WDDR_MEMORY_MAP_MCU_INTF (MEMORY_MAP_WAV_MCU_INTF) 21 | #define WDDR_MEMORY_MAP_MCU (MEMORY_MAP_WAV_MCU) 22 | #define WDDR_MEMORY_MAP_MCU_ITCM (MEMORY_MAP_WAV_MCU_ITCM) 23 | #define WDDR_MEMORY_MAP_MCU_DTCM (MEMORY_MAP_WAV_MCU_DTCM) 24 | 25 | // DDR PHY Specific 26 | // Mask used for MSR Switching (PHY offsets only) 27 | #define WDDR_MEMORY_MAP_REL_MASK (0x0000FFFF) 28 | 29 | // Common Analog / Common Clock Analog 30 | #define WDDR_MEMORY_MAP_CMN (0x00090000) 31 | 32 | // MVP PLL 33 | #define WDDR_MEMORY_MAP_PLL (0x00098000) 34 | 35 | // CTRL / Debug / Test 36 | #define WDDR_MEMORY_MAP_FSW (0x000A0000) 37 | #define WDDR_MEMORY_MAP_CTRL (0x000B0000) 38 | 39 | // DFI 40 | #define WDDR_MEMORY_MAP_DFI (0x000C0000) 41 | #define WDDR_MEMORY_MAP_DFI_CH0 (0x000D0000) 42 | 43 | // PHY Channel 0 44 | #define WDDR_MEMORY_MAP_CH0_DQ0 (0x000F0000) 45 | #define WDDR_MEMORY_MAP_CH0_DQ1 (0x00100000) 46 | #define WDDR_MEMORY_MAP_CH0_CA (0x00110000) 47 | 48 | // PHY Channel 1 49 | #define WDDR_MEMORY_MAP_CH1_DQ0 (0x00120000) 50 | #define WDDR_MEMORY_MAP_CH1_DQ1 (0x00130000) 51 | #define WDDR_MEMORY_MAP_CH1_CA (0x00140000) 52 | 53 | // RESERVED 54 | #define WDDR_MEMORY_MAP_PHY_SLV_RSVD (0x00150000) 55 | 56 | // Relative Offsets 57 | #define WDDR_MEMORY_MAP_PHY_CH_START (WDDR_MEMORY_MAP_CH0_DQ0) 58 | #define WDDR_MEMORY_MAP_PHY_CH_OFFSET (WDDR_MEMORY_MAP_CH1_DQ0 - WDDR_MEMORY_MAP_PHY_CH_START) 59 | #define WDDR_MEMORY_MAP_PHY_DQ_OFFSET (WDDR_MEMORY_MAP_CH0_DQ1 - WDDR_MEMORY_MAP_PHY_CH_START) 60 | #define WDDR_MEMORY_MAP_PHY_CA_OFFSET (WDDR_MEMORY_MAP_CH0_CA - WDDR_MEMORY_MAP_PHY_CH_START) 61 | 62 | #endif /* _WDDR_MEMORY_MAP_H_ */ 63 | -------------------------------------------------------------------------------- /include/error.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _ERROR_H_ 7 | #define _ERROR_H_ 8 | 9 | #define ASSERT_ERROR(cause) \ 10 | do { \ 11 | return cause; \ 12 | } while(0) 13 | 14 | #define PROPAGATE_ERROR(func) \ 15 | do { \ 16 | int err = func; \ 17 | if (err) \ 18 | { \ 19 | return err; \ 20 | } \ 21 | } while(0) 22 | 23 | /** 24 | * @brief WLPDDR Return Value Enumerations 25 | * 26 | * @details Common return types. 27 | * 28 | * SUCCESS No errors. 29 | * ERROR At least one error. 30 | * ERROR_NOT_VALID_FREQ Invalid frequency requested. 31 | * ERROR_DFI_LOAD_BUFFER_FULL The DFI load buffer is full. 32 | * ERROR_DFI_PACKET_FIFO_FULL The DFI Packet FIFO is full. 33 | * ERROR_ZQCAL_CODE_AT_MIN The ZQCAL code is at the min value. 34 | * ERROR_ZQCAL_CODE_AT_MAX The ZQCAL code is at the max value. 35 | */ 36 | typedef enum wddr_return_t 37 | { 38 | /* COMMON RETURN CODES */ 39 | WDDR_SUCCESS, 40 | WDDR_ERROR, 41 | WDDR_ERROR_NOT_VALID_FREQ, 42 | /* IP SPECIFIC RETURN CODES */ 43 | WDDR_ERROR_DFI_PACKET_FIFO_FULL, 44 | WDDR_ERROR_DFI_PACKET_FIFO_EMPTY, 45 | WDDR_ERROR_ZQCAL_PCAL_AT_MIN, 46 | WDDR_ERROR_ZQCAL_PCAL_AT_MAX, 47 | WDDR_ERROR_ZQCAL_NCAL_AT_MIN, 48 | WDDR_ERROR_ZQCAL_NCAL_AT_MAX, 49 | } wddr_return_t; 50 | 51 | #endif /* _ERROR_H_ */ 52 | -------------------------------------------------------------------------------- /include/firmware/firmware.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _FIRMWARE_H_ 7 | #define _FIRMWARE_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief Firmware Response Enumerations 14 | * 15 | * SUCCESS firmware request was successful. 16 | * FAILURE firmware request failed. 17 | * RETRY firmware request couldn't be processed. Caller should retry. 18 | */ 19 | typedef enum firmware_response 20 | { 21 | FW_RESP_SUCCESS, 22 | FW_RESP_FAILURE, 23 | FW_RESP_RETRY, 24 | FW_RESP_NUM, 25 | } fw_response_t; 26 | 27 | /** 28 | * @brief Firmware Message Structure 29 | * 30 | * @details Structure passed to PHY firmware for processing. 31 | * 32 | * event Firmware event associated with the message. 33 | * data pointer to message specific data to process. 34 | * xSender pointer to task that sent the message. 35 | */ 36 | typedef struct firmware_message 37 | { 38 | uint8_t event; 39 | void *data; 40 | TaskHandle_t xSender; 41 | } fw_msg_t; 42 | 43 | #endif /* _FIRMWARE_H_ */ 44 | -------------------------------------------------------------------------------- /include/firmware/phy_api.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _FIRMWARE_PHY_API_H_ 7 | #define _FIRMWARE_PHY_API_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief Firmware PHY Initialization 13 | * 14 | * @details API to initialize the PHY Firmware. Should be the first thing 15 | * called in main. 16 | * 17 | * @return void. 18 | */ 19 | void firmware_phy_init(void); 20 | 21 | /** 22 | * @brief Firmware PHY Start 23 | * 24 | * @details Starts the PHY Firmware. Must be called after FreeRTOS threads 25 | * are running. Typically, this would be called by the Main Task. 26 | * 27 | * @param[in] calibrate flag to indicate if PHY should be calibrated. 28 | * @param[in] train_dram flag to indicate if PHY should train DRAM. 29 | * 30 | * @return returns whether PHY Firmware was started successfully. 31 | * @retval pdPASS if started successfully. 32 | * @retval pdFAIL otherwise. 33 | */ 34 | UBaseType_t firmware_phy_start(bool calibrate, bool train_dram); 35 | 36 | /** 37 | * @brief Firmware PHY Prepare Frequency Switch 38 | * 39 | * @details Requests the firmware to begin prepping PHY for a frequency 40 | * switch. 41 | * 42 | * @param[in] freq_id The frequency to prepare. 43 | * 44 | * @return returns whether PHY was prepared successfully. 45 | * @retval pdPASS if prepared successfully. 46 | * @retval pdFAIL otherwise. 47 | */ 48 | UBaseType_t firmware_phy_prep_switch(uint8_t freq_id); 49 | 50 | #endif /* _FIRMWARE_PHY_API_H_ */ 51 | -------------------------------------------------------------------------------- /include/firmware/phy_task.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _FIRMWARE_PHY_TASK_H_ 7 | #define _FIRMWARE_PHY_TASK_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief PHY Firmware Events 14 | * 15 | * BOOT Event used to boot the PHY. 16 | * PREP Event used to request PHY Manager to prep for a switch. 17 | * PHYUPD_REQ Event used to request PHYUPD. 18 | * PHYMSTR_REQ Event used to request PHYMSTR control. 19 | * PHYMSTR_EXIT Event used to exit PHYMSTR control. 20 | * INIT_START Event used to indicate INIT_START assert occurred. 21 | * INIT_COMPLETE Event used to indicate INIT_COMPLETE ack occurred. 22 | * PLL_INIT_LOCK Event used to indicate PLL initally locked. 23 | * PLL_LOCK Event used to indicate PLL locked. 24 | * PLL_LOSS_LOCK Event used to indicate PLL lost lock. 25 | * PHYMSTR_ACK Event used to indicate that PHYMSTR_REQ was acknowledged. 26 | * PHYMSTR_ABORT Event used to indicate that PHYMSTR_REQ should be aborted. 27 | * PHYUPD_ACK Event used to indicate that PHUPD_REQ was acknowledged. 28 | * PHYUPD_ABORT Event used to indicate that PHUPD_REQ should be aborted. 29 | * CTRLUPD_ASSERT Event used to indicate CTRLUPD REQ was asserted. 30 | * CTRLUPD_DEASSERT Event used to indicate CTRLUPD REQ was dasserted. 31 | * LP_DATA_REQ Event used to indicate LP_DATA REQ was asserted. 32 | * LP_CTRL_REQ Event used to indicate LP_CTRL_REQ was asserted. 33 | */ 34 | typedef enum firmware_phy_event 35 | { 36 | FW_PHY_EVENT_BOOT, 37 | FW_PHY_EVENT_PREP, 38 | FW_PHY_EVENT_PHYUPD_REQ, 39 | FW_PHY_EVENT_PHYMSTR_REQ, 40 | FW_PHY_EVENT_PHYMSTR_EXIT, 41 | FW_PHY_EVENT_INIT_START, 42 | FW_PHY_EVENT_INIT_COMPLETE, 43 | FW_PHY_EVENT_PLL_INIT_LOCK, 44 | FW_PHY_EVENT_PLL_LOCK, 45 | FW_PHY_EVENT_PLL_LOSS_LOCK, 46 | FW_PHY_EVENT_PHYMSTR_ACK, 47 | FW_PHY_EVENT_PHYMSTR_ABORT, 48 | FW_PHY_EVENT_PHYUPD_ACK, 49 | FW_PHY_EVENT_PHYUPD_ABORT, 50 | FW_PHY_EVENT_CTRLUPD_ASSERT, 51 | FW_PHY_EVENT_CTRLUPD_DEASSERT, 52 | FW_PHY_EVENT_LP_DATA_REQ, 53 | FW_PHY_EVENT_LP_CTRL_REQ, 54 | FW_PHY_EVENT_NUM, 55 | } fw_phy_event_t; 56 | 57 | /** 58 | * @brief Firmware PHY Start Configuration Structure 59 | * 60 | * calibrate Flag to indicate if PHY should be calibrated. 61 | * train_dram Flag to indicate if PHY should train DRAM. 62 | */ 63 | typedef struct fw_phy_start_config 64 | { 65 | bool calibrate; 66 | bool train_dram; 67 | } fw_phy_start_cfg_t; 68 | 69 | /** 70 | * @brief Firmware PHY Task Initialization 71 | * 72 | * @details Initializes PHY Firmware Task. 73 | * 74 | * @return void. 75 | */ 76 | void fw_phy_task_init(void); 77 | 78 | /** 79 | * @brief Firmware PHY Task Notify 80 | * 81 | * @details Notify firmware PHY task of an event via the given message. 82 | * 83 | * @param[in] msg pointer to message to send. 84 | * 85 | * @return void. 86 | */ 87 | void fw_phy_task_notify(fw_msg_t *msg); 88 | 89 | /** 90 | * @brief Firmware PHY Task Notify ISR 91 | * 92 | * @details ISR friendly version of Firmware PHY Task Notify. 93 | * 94 | * @param[in] msg pointer to message to send. 95 | * @param[out] pxHigherPriorityTaskWoken set to indicate if higher priority 96 | * task was woken. 97 | * 98 | * @return void. 99 | */ 100 | void fw_phy_task_notify_isr(fw_msg_t *msg, 101 | BaseType_t *pxHigherPriorityTaskWoken); 102 | 103 | #endif /* _FIRMWARE_PHY_TASK_H_ */ 104 | -------------------------------------------------------------------------------- /include/table/ca/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CA_TABLE_H_ 7 | #define _CA_TABLE_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | 18 | /************************************************************************* 19 | ** Receive Path 20 | *************************************************************************/ 21 | /** 22 | * @brief CA RX Path Frequency Configuration Structure 23 | * 24 | * @details Per-Frequency configuration data for all devices in Receive CA 25 | * path. 26 | * 27 | * rank.ck.sdr_lpde CK SDR LPDE data for each rank. 28 | * rank_cmn.cmn.gearbox CA/CK Gearbox data. 29 | */ 30 | typedef struct ca_rx_path_freq_cfg_t 31 | { 32 | struct 33 | { 34 | struct 35 | { 36 | lpde_cfg_t sdr_lpde; 37 | } ck; 38 | } rank[WDDR_PHY_RANK]; 39 | struct 40 | { 41 | struct 42 | { 43 | const rx_gb_cfg_t gearbox; 44 | } cmn; 45 | } rank_cmn; 46 | } ca_rx_path_freq_cfg_t; 47 | 48 | /************************************************************************* 49 | ** Transmit Path 50 | *************************************************************************/ 51 | /** 52 | * @brief CA TX Path Frequency Configuration Structure 53 | * 54 | * @details Per-Frequency configuration structure for CA TX Path. 55 | * 56 | * rank.ca.lpde LPDE CA bit configuration data. 57 | * rank.ca.pipeline CA Pipeline bit configuration data. 58 | * rank.ca.pi CA PI configuration data. 59 | * rank.ca.rt CA Retimer Pipeline configuration data. 60 | * rank.ck.pipeline CK Pipeline bit configuration data. 61 | * rank.ck.pi CK PI configuration data. 62 | * rank.ck.driver CK Driver common configuration data. 63 | * rank.ck.lpde LPDE CK bit configuration data. 64 | * rank.ck.rt CK Retimer Pipeline configuration data. 65 | * rank_cmn.ca.driver CA Driver configuration data. 66 | * rank_cmn.ck.driver CK Driver configuration data. 67 | * rank_cmn.ck.gearbox CK Gearbox configuration data. 68 | * rank_cmn.cmn.egress Common digital and analog egress configuration data. 69 | */ 70 | typedef struct ca_tx_path_freq_cfg_t 71 | { 72 | struct 73 | { 74 | struct { 75 | lpde_cfg_t lpde[WDDR_PHY_CA_SLICE_NUM]; 76 | pipeline_bit_cfg_t pipeline; 77 | tx_pi_cfg_t pi; 78 | rt_pipeline_cfg_t rt; 79 | } ca; 80 | 81 | struct { 82 | pipeline_bit_cfg_t pipeline; 83 | tx_pi_cfg_t pi; 84 | driver_cmn_cfg_t driver; 85 | lpde_cfg_t lpde[WDDR_PHY_CK_TXRX_SLICE_NUM]; 86 | rt_pipeline_cfg_t rt; 87 | } ck; 88 | } rank[WDDR_PHY_RANK]; 89 | struct 90 | { 91 | struct { 92 | const driver_cfg_t driver; 93 | } ca; 94 | struct { 95 | const driver_cfg_t driver; 96 | const tx_gb_cfg_t gearbox; 97 | } ck; 98 | struct { 99 | const egress_bit_cfg_t egress; 100 | } cmn; 101 | } rank_cmn; 102 | } ca_tx_path_freq_cfg_t; 103 | 104 | /************************************************************************* 105 | ** Aggregate Path 106 | *************************************************************************/ 107 | /** 108 | * @brief CA Path Frequency Configuration Structure 109 | * 110 | * @details Per-Frequency Configuration data for entire CA Path. 111 | * 112 | * tx TX path. 113 | * rx RX path. 114 | */ 115 | typedef struct ca_path_freq_cfg_t 116 | { 117 | ca_tx_path_freq_cfg_t tx; 118 | ca_rx_path_freq_cfg_t rx; 119 | } ca_path_freq_cfg_t; 120 | 121 | #endif /* _CA_TABLE_H_ */ 122 | -------------------------------------------------------------------------------- /include/table/channel/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _CHANNEL_TABLE_H_ 7 | #define _CHANNEL_TABLE_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | 13 | /** 14 | * @brief Channel Frequency Configuration Structure 15 | * 16 | * @details Stores all configuration data for entire channel for a specific 17 | * frequency. 18 | * 19 | * dq per-frequency configuration data for both DQ bytes. 20 | * ca per-frequency configuration data for CA. 21 | */ 22 | typedef struct channel_freq_cfg_t 23 | { 24 | dq_path_freq_cfg_t dq[WDDR_PHY_DQ_BYTE_NUM]; 25 | ca_path_freq_cfg_t ca; 26 | } channel_freq_cfg_t; 27 | 28 | /** 29 | * @brief Channel Common Frequency Configuration Structure 30 | * 31 | * @details Stores all configuration data for entire channel that is common 32 | * across all frequencies. 33 | * 34 | * dq frequency independent configuration data for both DQ bytes. 35 | */ 36 | typedef struct channel_common_cfg_t 37 | { 38 | dq_path_common_cfg_t dq[WDDR_PHY_DQ_BYTE_NUM]; 39 | } channel_common_cfg_t; 40 | 41 | #endif /* _CHANNEL_TABLE_H_ */ 42 | -------------------------------------------------------------------------------- /include/table/cmn/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PATH_COMMON_TABLE_H_ 7 | #define _PATH_COMMON_TABLE_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | 13 | /** 14 | * @brief Common Path Frequency Configuration Structure 15 | * 16 | * @details Per-Frequency Configuration data for Common Path. 17 | * 18 | * vref Voltage Reference configuration data. 19 | */ 20 | typedef struct common_path_freq_cfg_t 21 | { 22 | vref_cfg_t vref; 23 | } common_path_freq_cfg_t; 24 | 25 | /** 26 | * @brief Common Path Common Frequency Configuration Structure 27 | * 28 | * @details Frequency independent Configuration data for Common Path. 29 | * 30 | * pmon Process Monitor calibration data. 31 | * zqcal ZQCAL calibration data. 32 | */ 33 | typedef struct common_path_common_cfg_t 34 | { 35 | pmon_cfg_t pmon; 36 | zqcal_cfg_t zqcal; 37 | } common_path_common_cfg_t; 38 | 39 | #endif /* _PATH_COMMON_TABLE_H_ */ 40 | -------------------------------------------------------------------------------- /include/table/dp/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PIPELINE_TABLE_H_ 7 | #define _PIPELINE_TABLE_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief SDR Pipeline Configuration Structure 14 | * 15 | * @details Per frequency SDR Pipeline configuration data. 16 | * 17 | * x_sel Phase Select configuration. 18 | * fc_delay Full Cycle Delay value. 19 | * pipe_en Pipe Enable (half cycle delay) value. 20 | */ 21 | typedef struct sdr_pipeline_cfg_t 22 | { 23 | uint32_t x_sel; 24 | uint16_t fc_delay; 25 | uint16_t pipe_en; 26 | } sdr_pipeline_cfg_t; 27 | 28 | /** 29 | * @brief DDR Pipeline Configuration Structure 30 | * 31 | * @details Per frequency DDR Pipeline configuration data. 32 | * 33 | * x_sel Phase Select configuration. 34 | * pipe_en Pipe Enable (half cycle delay) value. 35 | */ 36 | typedef struct ddr_pipeline_cfg_t 37 | { 38 | uint32_t x_sel; 39 | uint16_t pipe_en; 40 | } ddr_pipeline_cfg_t; 41 | 42 | /** 43 | * @brief QDR Pipeline Configuration Structure 44 | * 45 | * @details Per frequency QDR Pipeline configuration data. 46 | * 47 | * x_sel Phase Select configuration. 48 | * pipe_en Pipe Enable (half cycle delay) value. 49 | */ 50 | typedef struct qdr_pipeline_cfg_t 51 | { 52 | uint32_t x_sel; 53 | uint16_t pipe_en; 54 | } qdr_pipeline_cfg_t; 55 | 56 | /** 57 | * @brief Retimer (RT) Pipeline Configuration Structure 58 | * 59 | * @details Per frequency RT Pipeline configuration data. 60 | * 61 | * pipe_en Pipe Enable (half cycle delay) value. 62 | */ 63 | typedef struct rt_pipeline_cfg_t 64 | { 65 | uint16_t pipe_en; 66 | } rt_pipeline_cfg_t; 67 | 68 | /** 69 | * @brief Egress Digital Mode Enumerations 70 | * 71 | * @details Supported WDDR Egress Digital Modes. 72 | * 73 | * @note DDR prefix must be here for not very interesting reasons. 74 | */ 75 | typedef enum egress_dig_mode_t 76 | { 77 | DDR_DIG_EGRESS_SDR = 1, 78 | DDR_DIG_EGRESS_DDR_2TO1 = 2, 79 | DDR_DIG_EGRESS_QDR_2TO1 = 4, 80 | DDR_DIG_EGRESS_ODR_2TO1 = 8, 81 | DDR_DIG_EGRESS_QDR_4TO1 = 16, 82 | DDR_DIG_EGRESS_ODR_4TO1 = 32, 83 | DDR_DIG_EGRESS_BSCAN = 64, 84 | } egress_dig_mode_t; 85 | 86 | /** 87 | * @brief Egress Analog Mode Enumerations 88 | * 89 | * @details Supported WDDR Egress Analog Modes. 90 | * 91 | * @note DDR prefix must be here for not very interesting reasons. 92 | */ 93 | typedef enum egress_ana_mode_t 94 | { 95 | DDR_ANA_EGRESS_BYPASS = 1, 96 | DDR_ANA_EGRESS_DDR_2TO1 = 2, 97 | DDR_ANA_EGRESS_QDR_2TO1 = 4, 98 | DDR_ANA_EGRESS_ODR_2TO1 = 8, 99 | DDR_ANA_EGRESS_QDR_4TO1 = 16, 100 | DDR_ANA_EGRESS_ODR_4TO1 = 32, 101 | } egress_ana_mode_t; 102 | 103 | /** 104 | * @brief Pipeline Bit Configuration Structure 105 | * 106 | * @details Per frequency configuration data for each bit in the pipeline. 107 | * 108 | * sdr sdr dp parameters. 109 | * ddr ddr dp parameters. 110 | * qdr qdr dp parameters. 111 | */ 112 | typedef struct pipeline_bit_cfg_t 113 | { 114 | sdr_pipeline_cfg_t sdr; 115 | ddr_pipeline_cfg_t ddr; 116 | qdr_pipeline_cfg_t qdr; 117 | } pipeline_bit_cfg_t; 118 | 119 | /** 120 | * @brief Egress Bit Configuration Structure 121 | * 122 | * @details Per-bit settings for analog and digital egress modes. 123 | * 124 | * dig_mode digital egress mode. 125 | * ana_mode analog egress mode. 126 | */ 127 | typedef struct egress_bit_cfg_t 128 | { 129 | const egress_dig_mode_t dig_mode; 130 | const egress_ana_mode_t ana_mode; 131 | } egress_bit_cfg_t; 132 | 133 | #endif /* _PIPELINE_TABLE_H_ */ 134 | -------------------------------------------------------------------------------- /include/table/dram/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DRAM_TABLE_H_ 7 | #define _DRAM_TABLE_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief DRAM Configuration Structure 14 | * 15 | * @details Per-Frequency DRAM configuration data. 16 | * 17 | * ratio DFI to DRAM Clock ratio. 18 | * t_vref_ca_long CA VREF LONG in cycles. 19 | * txsr Self-Refresh Exit timing. 20 | * mr1 Mode Register 1 (Toggle Preamble). 21 | * mr2 Mode Register 2 (Read / Write Latency). 22 | * mr11 Mode Register 11 (CA / DQ ODT). 23 | * mr12 Mode Register 12 (CA VREF). 24 | * mr14 Mode Register 14 (DQ VREF). 25 | * phy_wr_lat Write Enable Offset (DFI). 26 | * phy_wr_en Write Data Offset (DFI). 27 | * phy_rd_en Read Enable Offset (DFI). 28 | * t_sh_train Setup / Hold cycles for CBT. 29 | */ 30 | typedef struct dram_freq_cfg_t 31 | { 32 | const wddr_freq_ratio_t ratio; 33 | const uint16_t t_vref_ca_long; 34 | const uint16_t txsr; 35 | const uint8_t mr1; 36 | uint8_t mr2; 37 | const uint8_t mr11; 38 | uint8_t mr12; 39 | uint8_t mr14; 40 | const uint8_t phy_wr_lat; 41 | const uint8_t phy_wr_en; 42 | const uint8_t phy_rd_en; 43 | const uint8_t t_sh_train; 44 | } dram_freq_cfg_t; 45 | 46 | #endif /* _DRAM_TABLE_H_ */ 47 | -------------------------------------------------------------------------------- /include/table/driver/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _DRIVER_TABLE_H_ 7 | #define _DRIVER_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief Driver Mode Enumerations 13 | * 14 | * DIFF Differential mode. 15 | * SE Single-ended mode. 16 | */ 17 | typedef enum driver_mode_t 18 | { 19 | DRIVER_MODE_DIFF, 20 | DRIVER_MODE_SE, 21 | } driver_mode_t; 22 | 23 | /** 24 | * @brief Driver Loopback Mode Enumerations 25 | * 26 | * DISABLE Driver is not in loopback mode. 27 | * ENABLE Driver is in loopback mode. 28 | */ 29 | typedef enum driver_loopback_mode_t 30 | { 31 | DRIVER_LOOPBACK_MODE_DISABLE, 32 | DRIVER_LOOPBACK_MODE_ENABLE, 33 | } driver_loopback_mode_t; 34 | 35 | /** 36 | * @brief Driver P/N Calibration Enumerations 37 | * 38 | * @details Indices for P and N calibration codes. 39 | * 40 | * P_CAL Driver P cal index. 41 | * N_CAL Driver N cal index. 42 | * PN_CAL_NUM Max Driver P/N indices. 43 | */ 44 | typedef enum driver_pn_side_t 45 | { 46 | DRVR_P_CAL, 47 | DRVR_N_CAL, 48 | DRVR_PN_CAL_NUM, 49 | } driver_pn_side_t; 50 | 51 | /** 52 | * @brief Driver Impedance Enumerations 53 | * 54 | * HIZ High-Z impedance. 55 | * 240 240 ohm impedance. 56 | * 120 120 ohm impedance. 57 | * 80 80 ohm impedance. 58 | * 60 60 ohm impedance. 59 | * 48 48 ohm impedance. 60 | * 40 40 ohm impedance. 61 | */ 62 | typedef enum driver_impedance_t 63 | { 64 | DRIVER_IMPEDANCE_HIZ, 65 | DRIVER_IMPEDANCE_240, 66 | DRIVER_IMPEDANCE_120, 67 | DRIVER_IMPEDANCE_80, 68 | DRIVER_IMPEDANCE_60, 69 | DRIVER_IMPEDANCE_48, 70 | DRIVER_IMPEDANCE_40 71 | } driver_impedance_t; 72 | 73 | /** 74 | * @brief Driver Common Configuration Structure 75 | * 76 | * @details Configuration data for Driver common to both slice in TX path. 77 | * 78 | * mode driver mode. 79 | * code pointer to calibrated P/N codes. This points to ZQCAL table. 80 | */ 81 | typedef struct driver_cmn_cfg_t 82 | { 83 | const driver_mode_t mode; 84 | uint8_t *const code; 85 | } driver_cmn_cfg_t; 86 | 87 | /** 88 | * @brief Driver Configuration Structure 89 | * 90 | * @details Configuration data for Driver for a specific slice in TX Path. 91 | * 92 | * tx_impd transmit impedance configuration. 93 | * rx_impd receive impdedance configuration. 94 | * override driver override configuration. 95 | */ 96 | typedef struct driver_cfg_t 97 | { 98 | const driver_impedance_t tx_impd; 99 | const driver_impedance_t rx_impd; 100 | struct 101 | { 102 | uint8_t sel : 3; 103 | uint8_t val_t : 1; 104 | uint8_t val_c : 1; 105 | } override; 106 | } driver_cfg_t; 107 | 108 | #endif /* _DRIVER_TABLE_H_ */ 109 | -------------------------------------------------------------------------------- /include/table/gearbox/rx_table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _GEARBOX_RX_TABLE_H_ 7 | #define _GEARBOX_RX_TABLE_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief Receive (RX) Gearbox Configuration Structure 14 | * 15 | * @details Structure for storing Receive Gearbox configuration. 16 | * 17 | * data_mode Data Mode Configuration. 18 | * fifo_mode FIFO Mode Configuration. 19 | * wck_mode WCK Mode Configuration. 20 | * pre_filter_sel Sets if preamble should be filtered in PHY. 21 | */ 22 | typedef struct rx_gb_cfg_t 23 | { 24 | const gb_data_mode_t data_mode; 25 | const gb_fifo_mode_t fifo_mode; 26 | const gb_wck_mode_t wck_mode; 27 | const uint8_t pre_filter_sel; 28 | } rx_gb_cfg_t; 29 | 30 | #endif /* _GEARBOX_RX_TABLE_H_ */ 31 | -------------------------------------------------------------------------------- /include/table/gearbox/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _GEARBOX_TABLE_H_ 7 | #define _GEARBOX_TABLE_H_ 8 | 9 | /** 10 | * @brief Gearbox Data Mode Enumerations 11 | */ 12 | typedef enum gb_data_mode_t 13 | { 14 | DGB_1TO1_HF, 15 | DGB_2TO1_HF, 16 | DGB_2TO1_IR, 17 | DGB_4TO1_LF, 18 | DGB_4TO1_HF, 19 | DGB_4TO1_IR, 20 | DGB_8TO1_LF, 21 | DGB_8TO1_HF 22 | } gb_data_mode_t; 23 | 24 | /** 25 | * @brief Gearbox Write Mode Enumerations 26 | */ 27 | typedef enum gb_write_mode_t 28 | { 29 | WGB_1TO1, 30 | WGB_2TO1, 31 | WGB_4TO1, 32 | WGB_8TO1, 33 | WGB_2TO2, 34 | WGB_4TO2, 35 | WGB_8TO2, 36 | WGB_4TO4, 37 | WGB_8TO4, 38 | WGB_8TO8, 39 | WGB_16TO8 40 | } gb_write_mode_t; 41 | 42 | /** 43 | * @brief Gearbox FIFO Mode Enumerations 44 | */ 45 | typedef enum gb_fifo_mode_t 46 | { 47 | FGB_1TO1, 48 | FGB_1TO2, 49 | FGB_1TO4, 50 | FGB_1TO8, 51 | FGB_2TO2, 52 | FGB_2TO4, 53 | FGB_2TO8, 54 | FGB_4TO4, 55 | FGB_4TO8, 56 | FGB_8TO8, 57 | FGB_8TO16 58 | } gb_fifo_mode_t; 59 | 60 | /** 61 | * @brief Gearbox WCK Mode Enumerations 62 | */ 63 | typedef enum gb_wck_mode_t 64 | { 65 | // TODO: What does 0 and 1 actually mean? 66 | GB_WCK_MODE_0, 67 | GB_WCK_MODE_1 68 | } gb_wck_mode_t; 69 | 70 | #endif /* _GEARBOX_TABLE_H_ */ 71 | -------------------------------------------------------------------------------- /include/table/gearbox/tx_table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _GEARBOX_TX_TABLE_H_ 7 | #define _GEARBOX_TX_TABLE_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief Transmit (TX) Gearbox Configuration Structure 14 | * 15 | * @details Structure for storing Transmit Gearbox configuration. 16 | * 17 | * data_mode Data Mode Configuration. 18 | * write_mode Write Mode Configuration. 19 | * ck2wck_ratio Ratio of WCK to CK. 20 | */ 21 | typedef struct tx_gb_cfg_t 22 | { 23 | const gb_data_mode_t data_mode; 24 | const gb_write_mode_t write_mode; 25 | const uint8_t ck2wck_ratio; 26 | } tx_gb_cfg_t; 27 | 28 | #endif /* _GEARBOX_TX_TABLE_H_ */ 29 | -------------------------------------------------------------------------------- /include/table/lpde/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _LPDE_TABLE_H_ 7 | #define _LPDE_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief LPDE Configuration Structure 13 | * 14 | * delay configured delay value. 15 | * gear Configured gear value. 16 | */ 17 | typedef union lpde_cfg_t 18 | { 19 | struct 20 | { 21 | uint32_t delay: 6; 22 | const uint32_t gear: 3; 23 | }; 24 | uint32_t val; 25 | } lpde_cfg_t; 26 | 27 | #endif /* _LPDE_TABLE_H_ */ 28 | -------------------------------------------------------------------------------- /include/table/pi/rx_table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PI_RX_TABLE_H_ 7 | #define _PI_RX_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief RX Phase Interpolator Configuration Frequency Structure 13 | * 14 | * @details Per frequency configuration data for RX PIs. 15 | * 16 | * rcs Configuration for RCS Phase Interpolator. 17 | * ren Configuration for REN Phase Interpolator. 18 | * rdqs Configuration for RDQS Phase Interpolator. 19 | */ 20 | typedef struct rx_pi_cfg_t 21 | { 22 | pi_cfg_t rcs; 23 | pi_cfg_t ren; 24 | pi_cfg_t rdqs; 25 | } rx_pi_cfg_t; 26 | 27 | #endif /* _PI_RX_TABLE_H_ */ 28 | -------------------------------------------------------------------------------- /include/table/pi/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PI_TABLE_H_ 7 | #define _PI_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief Phase Interpolator Configuration Structure 13 | * 14 | * code Configured code value. 15 | * gear Configured gear value. 16 | * xcpl Configured xcpl value. 17 | */ 18 | typedef union pi_cfg_t 19 | { 20 | struct 21 | { 22 | uint32_t code:6; 23 | const uint32_t gear:4; 24 | const uint32_t xcpl:1; 25 | }; 26 | uint32_t val; 27 | } pi_cfg_t; 28 | 29 | #endif /* _PI_TABLE_H_ */ 30 | -------------------------------------------------------------------------------- /include/table/pi/tx_table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PI_TX_TABLE_H_ 7 | #define _PI_TX_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief TX Phase Interpolator Configuration Frequency Structure 13 | * 14 | * @details Per frequency configuration data for TX PIs. 15 | * 16 | * odr Configuration for ODR Phase Interpolator. 17 | * qdr Configuration for QDR Phase Interpolator. 18 | * ddr Configuration for DDR Phase Interpolator. 19 | * rt Configuration for RT Phase Interpolator. 20 | * sdr Configuration for SDR delay match Phase Interpolator. 21 | * dfi Configuration for DFI delay match Phase Interpolator. 22 | */ 23 | typedef struct tx_pi_cfg_t 24 | { 25 | pi_cfg_t odr; 26 | pi_cfg_t qdr; 27 | pi_cfg_t ddr; 28 | pi_cfg_t rt; 29 | pi_cfg_t sdr; 30 | pi_cfg_t dfi; 31 | } tx_pi_cfg_t; 32 | 33 | #endif /* _PI_TX_TABLE_H_ */ 34 | -------------------------------------------------------------------------------- /include/table/pll/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PLL_TABLE_H_ 7 | #define _PLL_TABLE_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief VCO Indices 14 | * 15 | * @details Available VCO indices. 16 | * 17 | * MCU Low Power VCO that is reserved for MCU clock. 18 | * PHY_START Index of where PHY clock VCOs start. 19 | * PHY_1 First VCO available for PHY clock. 20 | * PHY_2 Second VCO available for PHY clock. 21 | * PHY_END Index of where PHY clock VCOs end. 22 | * VCO_NUM Total number of available VCOs in the design. 23 | */ 24 | typedef enum vco_index_t 25 | { 26 | VCO_INDEX_MCU, 27 | VCO_INDEX_PHY_START, 28 | VCO_INDEX_PHY_1 = VCO_INDEX_PHY_START, 29 | VCO_INDEX_PHY_2, 30 | VCO_INDEX_PHY_END, 31 | VCO_INDEX_NUM = VCO_INDEX_PHY_END, 32 | } vco_index_t; 33 | 34 | /** 35 | * @brief PLL Frequency Configuration Structure 36 | * 37 | * @details PLL Frequency configuration structure used to store configuration 38 | * settings for a single frequency. 39 | * 40 | * vco_cfg Table of VCO configuration values for each VCO used to power PHY 41 | * clock. 42 | */ 43 | typedef struct pll_freq_cfg_t 44 | { 45 | vco_cfg_t vco_cfg[VCO_INDEX_PHY_END - VCO_INDEX_PHY_START]; 46 | } pll_freq_cfg_t; 47 | 48 | #endif /* _PLL_TABLE_H_ */ 49 | -------------------------------------------------------------------------------- /include/table/pmon/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _PMON_TABLE_H_ 7 | #define _PMON_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief Process Monitor Configuration Structure 13 | * 14 | * target Target count (target freq/refclk freq). 15 | * refclk_count number of refclks to sammple for. 16 | * init_wait number of refclks to wait before starting. 17 | */ 18 | typedef struct process_monitor_cfg_t 19 | { 20 | const uint32_t target; 21 | const uint16_t refclk_count; 22 | const uint8_t init_wait; 23 | } pmon_cfg_t; 24 | 25 | #endif /* _PMON_TABLE_H_ */ 26 | -------------------------------------------------------------------------------- /include/table/receiver/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _RECEIVER_TABLE_H_ 7 | #define _RECEIVER_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief Receiver T/C Side Enumerations 13 | * 14 | * T_SIDE Receiver T side index. 15 | * C_SIDE Receiver C side index. 16 | * TC_SIDE Max receiver T/C index. 17 | */ 18 | typedef enum receiver_tc_side_t 19 | { 20 | REC_T_SIDE, 21 | REC_C_SIDE, 22 | REC_TC_SIDE_NUM 23 | } receiver_tc_side_t; 24 | 25 | /** 26 | * @brief Receiver T/C Side Enumerations Mask 27 | * 28 | * T_SIDE_MASK Receiver T side mask. 29 | * C_SIDE_MASK Receiver C side mask. 30 | * BOTH_SIDE_MASK Max receiver T/C mask. 31 | */ 32 | typedef enum receiver_tc_side_mask_t 33 | { 34 | REC_T_SIDE_MASK = (0x1 << REC_T_SIDE), 35 | REC_C_SIDE_MASK = (0x1 << REC_C_SIDE), 36 | REC_BOTH_SIDE_MASK = (REC_T_SIDE_MASK | REC_C_SIDE_MASK) 37 | } receiver_tc_side_mask_t; 38 | 39 | /** 40 | * @brief Receiver P/N Side Enumerations 41 | * 42 | * P_SIDE Receiver P side index. 43 | * N_SIDE Receiver N side index. 44 | * PN_SIDE Max receiver P/N index. 45 | */ 46 | typedef enum receiver_pn_side_t 47 | { 48 | REC_P_SIDE, 49 | REC_N_SIDE, 50 | REC_PN_SIDE_NUM 51 | } receiver_pn_side_t; 52 | 53 | /** 54 | * @brief Receiver Mode Enumerations 55 | * 56 | * DIFF differential mode. 57 | * SE single-ended mode. 58 | */ 59 | typedef enum receiver_mode_t 60 | { 61 | REC_MODE_DIFF, 62 | REC_MODE_SE 63 | } receiver_mode_t; 64 | 65 | /** 66 | * @brief Receiver Path State 67 | * 68 | * AC AC path configuration. 69 | * DC DC path configuration. 70 | */ 71 | typedef enum receiver_path_state_t 72 | { 73 | REC_PATH_AC = 0, 74 | REC_PATH_DC = 1, 75 | } receiver_path_state_t; 76 | 77 | /** 78 | * @brief Receiver Frequency Configuration Structure 79 | * 80 | * @details Stores frequency specific configuration data. 81 | * 82 | * feedback_resistor Feeback resistor value. 83 | * mode Receive Mode. 84 | * path_state Path state. 85 | * rx_delay RX delay on reciever delay element. 86 | */ 87 | typedef struct receiver_freq_cfg_t 88 | { 89 | const uint8_t feedback_resistor; 90 | const receiver_mode_t mode; 91 | const receiver_path_state_t path_state; 92 | uint16_t rx_delay[REC_TC_SIDE_NUM]; 93 | } receiver_freq_cfg_t; 94 | 95 | /** 96 | * @brief Receiver Common Calibration Structure 97 | * 98 | * @details Stores frequency independent calibration data 99 | * 100 | * code Receiver calibration codes. 101 | */ 102 | typedef struct receiver_common_cfg_t 103 | { 104 | uint8_t code[REC_PN_SIDE_NUM][REC_TC_SIDE_NUM]; 105 | } receiver_common_cfg_t; 106 | 107 | #endif /* _RECEIVER_TABLE_H_ */ 108 | -------------------------------------------------------------------------------- /include/table/sensamp/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _SENSAMP_TABLE_H_ 7 | #define _SENSAMP_TABLE_H_ 8 | 9 | #include 10 | #include 11 | 12 | /** 13 | * @brief Sense Amp (Sensamp) Index Enumerations 14 | * 15 | * @details Enumeration to indicate valid Sensamp indices. 16 | * 17 | * @note 0 and 180 are indices used for DDR mode. 18 | * @note 90 and 270 are additional indices used for QDR mode. 19 | * 20 | */ 21 | typedef enum sensamp_index_t 22 | { 23 | SA_0_INDEX = 0, 24 | SA_180_INDEX = 1, 25 | SA_90_INDEX = 2, 26 | SA_270_INDEX = 3 27 | } sensamp_index_t; 28 | 29 | /** 30 | * @brief Sense Amp (Sensamp) DQBit Configuration Structure 31 | * 32 | * code calibration code for a Sensamp bit. 33 | */ 34 | typedef struct sensamp_dqbit_cfg_t { 35 | uint8_t code[WDDR_PHY_CFG]; 36 | } sensamp_dqbit_cfg_t; 37 | 38 | /** 39 | * @brief Sense Amp (Sensamp) Common Configuration Structure 40 | * 41 | * @details Calibration for entire DQ Byte that is common across all 42 | * frequencies. 43 | * 44 | * dq Array of DQBit cal codes for each DQ Slice. 45 | */ 46 | typedef struct sensamp_dqbyte_common_cfg_t { 47 | sensamp_dqbit_cfg_t dq[WDDR_PHY_DQ_SLICE_NUM]; 48 | } sensamp_dqbyte_common_cfg_t; 49 | 50 | #endif /* _SENSAMP_TABLE_H_ */ 51 | -------------------------------------------------------------------------------- /include/table/vco/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _VCO_TABLE_H_ 7 | #define _VCO_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief VCO Frequency Configuration Structure 13 | * 14 | * @details VCO Frequency configuration structure used to store configuration 15 | * settings for a single frequency. 16 | * 17 | * band band value of VCO. 18 | * fine fine band value of VCO. 19 | * prop_gain proportional gain value. 20 | * int_comp integer divider value. 21 | * post_div post divider setting. 22 | * fll_refclk_count refclk counter value. Used for calibration. 23 | * fll_range VCO range to consider locked. Used for calibration. 24 | * lock_count_threshold VCO threshold to pass to be considered locked. Used 25 | * for calibration. 26 | * fll_vco_count_target VCO count target. Used for calibration. 27 | */ 28 | typedef struct vco_cfg_t 29 | { 30 | uint8_t band; 31 | uint8_t fine; 32 | const uint8_t prop_gain; 33 | const uint8_t int_comp; 34 | const uint8_t post_div; 35 | const uint8_t fll_refclk_count; 36 | const uint8_t fll_range; 37 | const uint8_t lock_count_threshold; 38 | const uint16_t fll_vco_count_target; 39 | } vco_cfg_t; 40 | 41 | #endif /* _VCO_TABLE_H_ */ 42 | -------------------------------------------------------------------------------- /include/table/vref/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _VREF_TABLE_H_ 7 | #define _VREF_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief VREF Power Mode Enumeration 13 | * 14 | * VREF_POWER_MODE_0 Power mode 0 15 | * VREF_POWER_MODE_1 Power mode 1 16 | * VREF_POWER_MODE_2 Power mode 2 17 | * VREF_POWER_MODE_3 Power mode 3 18 | */ 19 | typedef enum vref_power_mode_t 20 | { 21 | VREF_POWER_MODE_0, 22 | VREF_POWER_MODE_1, 23 | VREF_POWER_MODE_2, 24 | VREF_POWER_MODE_3 25 | } vref_pwr_mode_t; 26 | 27 | /** 28 | * @brief VREF Configuration Structure 29 | * 30 | * pwr_mode Configured power mode. 31 | * code Calibrated code value. 32 | */ 33 | typedef struct vref_cfg_t 34 | { 35 | const vref_pwr_mode_t power_mode; 36 | uint16_t code; 37 | } vref_cfg_t; 38 | 39 | #endif /* _VREF_TABLE_H_ */ 40 | -------------------------------------------------------------------------------- /include/table/wddr/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _WDDR_TABLE_H_ 7 | #define _WDDR_TABLE_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include "table_defs.h" 15 | 16 | /** 17 | * @brief Wavious DDR Frequency Configuration Structure 18 | * 19 | * @details Stores all configuration data for all devices for a specific frequency. 20 | * 21 | * channel per-frequency configuration data for all channels. 22 | * dfi per-frequency configuration data for DFI. 23 | * dram per-frequency configuration data for DRAM. 24 | * pll per-frequency configuration data for PLL. 25 | * common per-frequency configuration data for common path. 26 | */ 27 | typedef struct wddr_freq_cfg_t 28 | { 29 | channel_freq_cfg_t channel[WDDR_PHY_CHANNEL_NUM]; 30 | dfi_freq_cfg_t dfi; 31 | dram_freq_cfg_t dram; 32 | pll_freq_cfg_t pll; 33 | common_path_freq_cfg_t common; 34 | } wddr_freq_cfg_t; 35 | 36 | /** 37 | * @brief Wavious DDR Common Configuration Structure 38 | * 39 | * @details Stores all configuration data for all devices that is common for all 40 | * frequencies. 41 | * 42 | * channel frequency independent configuration data for all channels. 43 | * common frequency independent configuration data for common path. 44 | */ 45 | typedef struct wddr_common_cfg_t 46 | { 47 | channel_common_cfg_t channel[WDDR_PHY_CHANNEL_NUM]; 48 | common_path_common_cfg_t common; 49 | } wddr_common_cfg_t; 50 | 51 | /** 52 | * @brief WDDR Configuration Structure 53 | * 54 | * @details Stores all frequency dependent and frequency independent 55 | * configuration data for all devices. 56 | * 57 | * freq Per-Frequency configuration table. 58 | * common Frequency independent configuration table. 59 | */ 60 | typedef struct wddr_cfg_t 61 | { 62 | wddr_freq_cfg_t freq[WDDR_PHY_FREQ_NUM]; 63 | wddr_common_cfg_t common; 64 | } wddr_cfg_t; 65 | 66 | /** 67 | * @brief WDDR Table Structure 68 | * 69 | * @details Table that stores all calibration and configuration data for 70 | * the entire WDDR device for all frequencies. 71 | * 72 | * cfg configuration table. 73 | * valid table of which frequencies are valid. 74 | */ 75 | typedef struct wddr_table_t 76 | { 77 | wddr_cfg_t cfg; 78 | uint8_t valid[WDDR_PHY_FREQ_NUM]; 79 | } wddr_table_t; 80 | 81 | #endif /* _WDDR_TABLE_H_ */ 82 | -------------------------------------------------------------------------------- /include/table/wddr/table_defs.h: -------------------------------------------------------------------------------- 1 | 2 | /** 3 | * Copyright (c) 2021 Wavious LLC. 4 | * 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | /**************************************************************************** 8 | ***************************************************************************** 9 | ** Tool used: cfg_table_creator.py 10 | ** Generated by: developer 11 | ** Date: 09/14/21 16:36:29 12 | ** Code version: 1.0 13 | ** Input file used: DDR_TABLES.xlsx 14 | ***************************************************************************** 15 | ****************************************************************************/ 16 | 17 | #ifndef _WDDR_TABLE_DEFS_H_ 18 | #define _WDDR_TABLE_DEFS_H_ 19 | 20 | #include "table_vals.h" 21 | 22 | #define WDDR_PHY_FREQ_NUM (4) 23 | #define WDDR_PHY_VALID_FREQ_NUM (4) 24 | #define FREQ_VALID (1) 25 | #define FREQ_INVALID (0) 26 | 27 | #define WDDR_FREQ_VALID_TABLE { \ 28 | FREQ_VALID, \ 29 | FREQ_VALID, \ 30 | FREQ_VALID, \ 31 | FREQ_VALID, \ 32 | } 33 | 34 | #define WDDR_TABLE_CFG(name) { \ 35 | .common = WDDR_TABLE_CFG__WDDR__COMMON(name), \ 36 | .freq[0] = WDDR_TABLE_CFG__WDDR__FREQID_0(name), \ 37 | .freq[1] = WDDR_TABLE_CFG__WDDR__FREQID_1(name), \ 38 | .freq[2] = WDDR_TABLE_CFG__WDDR__FREQID_2(name), \ 39 | .freq[3] = WDDR_TABLE_CFG__WDDR__FREQID_3(name), \ 40 | } 41 | 42 | #define WDDR_TABLE(name) { \ 43 | .cfg = WDDR_TABLE_CFG(name), \ 44 | .valid = WDDR_FREQ_VALID_TABLE, \ 45 | } 46 | 47 | #define DECLARE_WDDR_TABLE(name) \ 48 | wddr_table_t name = WDDR_TABLE(name) 49 | 50 | #endif /* _WDDR_TABLE_DEFS_H_ */ 51 | -------------------------------------------------------------------------------- /include/table/zqcal/table.h: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright (c) 2021 Wavious LLC. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | */ 6 | #ifndef _ZQCAL_TABLE_H_ 7 | #define _ZQCAL_TABLE_H_ 8 | 9 | #include 10 | 11 | /** 12 | * @brief ZQCAL P/N Side Enumerations 13 | * 14 | * P_SIDE ZQCAL P side index. 15 | * N_SIDE ZQCAL N side index. 16 | * PN_SIDE Max ZQCAL P/N index. 17 | */ 18 | typedef enum zqcal_pn_cal_t 19 | { 20 | ZQCAL_P_CAL, 21 | ZQCAL_N_CAL, 22 | ZQCAL_PN_CAL_NUM, 23 | } zqcal_pn_cal_t; 24 | 25 | /** 26 | * @brief ZQCAL VOH Mode Enumeration 27 | * 28 | * ZQCAL_VOH_0P5 VOH set to 0.5. 29 | * ZQCAL_VOH_0P6 VOH set to 0.6. 30 | */ 31 | typedef enum zqcal_voh_t 32 | { 33 | ZQCAL_VOH_0P5, 34 | ZQCAL_VOH_0P6, 35 | ZQCAL_VOH_NUM 36 | } zqcal_voh_t; 37 | 38 | /** 39 | * @brief ZQCAL Configuration Structure 40 | * 41 | * code calibrated PCAL / NCAL code for each VOH setting. 42 | */ 43 | typedef struct zqcal_cfg_t 44 | { 45 | uint8_t code[ZQCAL_VOH_NUM][ZQCAL_PN_CAL_NUM]; 46 | } zqcal_cfg_t; 47 | 48 | #endif /* _ZQCAL_TABLE_H_ */ 49 | --------------------------------------------------------------------------------