├── README.md ├── RTL ├── RA1SH.v ├── ahb_slave_if.v ├── sram_bist.v ├── sram_bist_8kx8.v ├── sram_core.v └── sramc_top.v └── TB └── tb_sramc_top.sv /README.md: -------------------------------------------------------------------------------- 1 | # Sram-controller-design-based-on-AHB-bus 2 | ### 基于 AHB 的 sram 设计框架图显示如下: 3 | 4 | ![ahb_sramc_control](https://user-images.githubusercontent.com/71707557/185911793-8c65b49e-e37d-4d1d-b745-6e69bc872b13.png) 5 | 6 | ### AHB总线传输协议之没有等待状态的单个读写操作: 7 | 8 | ![没有等待状态的单个传输](https://user-images.githubusercontent.com/71707557/185935469-070d6c22-97d3-4248-958d-b88476e8994c.jpg) 9 | 10 | ### AHB总线传输协议之有等待状态的单个读写操作: 11 | 12 | ![插入等待状态的单个读写操作](https://user-images.githubusercontent.com/71707557/185935507-1498f930-3243-45ff-b998-250515906bb2.png) 13 | 14 | ### AHB总线传输协议之连续读写操作: 15 | 16 | ![连续读写操作](https://user-images.githubusercontent.com/71707557/185935545-0242f83b-411b-4eb6-9ab1-2d4265828629.png) 17 | 18 | ### hsize控制读写数据位宽与数据深度(默认位宽为32bit，深度为2^14) 19 | 20 | ![绘图5](https://user-images.githubusercontent.com/71707557/182754272-dd9540d8-3b8e-4967-a1ff-0342555d659a.png) 21 | 22 | ### 当hsize为2'b00时，数据位宽为8bit，数据深度为2^16 23 | 24 | ![fbc7243cd8f6d3286070628d774b1c8](https://user-images.githubusercontent.com/71707557/182756040-11988dca-7215-4767-9a53-8653e4ba6a65.png) 25 | 26 | ### 当hsize为2'b01时，数据位宽为16bit，数据深度为2^15 27 | 28 | ![979e27f5082deef4e8b00e63921ec6f](https://user-images.githubusercontent.com/71707557/182756083-7677d5d5-4924-4a9b-aad2-4096af8ff2ab.png) 29 | 30 | ### 当hsize为2'b10时，数据位宽为32bit，数据深度为2^14 31 | 32 | ![cdca3ff32af45260c13a686fb47f368](https://user-images.githubusercontent.com/71707557/182756109-daa0d467-e2a6-4313-9f7f-42238b6ffb14.png) 33 | -------------------------------------------------------------------------------- /RTL/RA1SH.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbbbbbb123/Sram-controller-design-based-on-AHB-bus/ea8a09f473d1f85a64f3d5dd616be02bee37631a/RTL/RA1SH.v -------------------------------------------------------------------------------- /RTL/ahb_slave_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbbbbbb123/Sram-controller-design-based-on-AHB-bus/ea8a09f473d1f85a64f3d5dd616be02bee37631a/RTL/ahb_slave_if.v -------------------------------------------------------------------------------- /RTL/sram_bist.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbbbbbb123/Sram-controller-design-based-on-AHB-bus/ea8a09f473d1f85a64f3d5dd616be02bee37631a/RTL/sram_bist.v -------------------------------------------------------------------------------- /RTL/sram_bist_8kx8.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbbbbbb123/Sram-controller-design-based-on-AHB-bus/ea8a09f473d1f85a64f3d5dd616be02bee37631a/RTL/sram_bist_8kx8.v -------------------------------------------------------------------------------- /RTL/sram_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbbbbbb123/Sram-controller-design-based-on-AHB-bus/ea8a09f473d1f85a64f3d5dd616be02bee37631a/RTL/sram_core.v -------------------------------------------------------------------------------- /RTL/sramc_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbbbbbb123/Sram-controller-design-based-on-AHB-bus/ea8a09f473d1f85a64f3d5dd616be02bee37631a/RTL/sramc_top.v -------------------------------------------------------------------------------- /TB/tb_sramc_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbbbbbb123/Sram-controller-design-based-on-AHB-bus/ea8a09f473d1f85a64f3d5dd616be02bee37631a/TB/tb_sramc_top.sv --------------------------------------------------------------------------------