├── .gitignore ├── .gitmodules ├── README.md ├── cv2PYNQ_vivado ├── .gitignore ├── cv2PYNQ.tcl ├── cv2PYNQ_vivado.ip_user_files │ ├── README.txt │ ├── bd │ │ └── design_1 │ │ │ ├── ip │ │ │ ├── design_1_auto_cc_21 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_cc_21.v │ │ │ ├── design_1_auto_cc_22 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_cc_22.v │ │ │ ├── design_1_auto_cc_23 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_cc_23.v │ │ │ ├── design_1_auto_cc_24 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_cc_24.v │ │ │ ├── design_1_auto_pc_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_pc_0.v │ │ │ ├── design_1_auto_pc_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_pc_1.v │ │ │ ├── design_1_auto_pc_2 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_pc_2.v │ │ │ ├── design_1_auto_us_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_us_0.v │ │ │ ├── design_1_auto_us_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_us_1.v │ │ │ ├── design_1_auto_us_2 │ │ │ │ └── sim │ │ │ │ │ └── design_1_auto_us_2.v │ │ │ ├── design_1_axi_dma_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_axi_dma_0_0.vhd │ │ │ ├── design_1_axi_dynclk_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_axi_dynclk_0.vhd │ │ │ ├── design_1_axi_gpio_hdmiin_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_axi_gpio_hdmiin_0.vhd │ │ │ ├── design_1_axi_intc_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_axi_intc_0_0.vhd │ │ │ ├── design_1_axi_vdma_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_axi_vdma_0.vhd │ │ │ ├── design_1_axis_register_slice_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_axis_register_slice_0_0.v │ │ │ ├── design_1_axis_register_slice_0_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_axis_register_slice_0_1.v │ │ │ ├── design_1_color_convert_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_color_convert_0.v │ │ │ ├── design_1_color_convert_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_color_convert_1.v │ │ │ ├── design_1_color_swap_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_color_swap_0_0.v │ │ │ ├── design_1_color_swap_0_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_color_swap_0_1.v │ │ │ ├── design_1_dvi2rgb_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_dvi2rgb_0_0.vhd │ │ │ ├── design_1_filter2D_hls_5_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_filter2D_hls_5_0_0.v │ │ │ ├── design_1_hdmi_out_hpd_video_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_hdmi_out_hpd_video_0.vhd │ │ │ ├── design_1_m00_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m00_regslice_0.v │ │ │ ├── design_1_m00_regslice_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m00_regslice_1.v │ │ │ ├── design_1_m01_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m01_regslice_0.v │ │ │ ├── design_1_m02_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m02_regslice_0.v │ │ │ ├── design_1_m03_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m03_regslice_0.v │ │ │ ├── design_1_m04_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m04_regslice_0.v │ │ │ ├── design_1_m05_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m05_regslice_0.v │ │ │ ├── design_1_m06_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m06_regslice_0.v │ │ │ ├── design_1_m07_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m07_regslice_0.v │ │ │ ├── design_1_m08_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m08_regslice_0.v │ │ │ ├── design_1_m09_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_m09_regslice_0.v │ │ │ ├── design_1_pixel_pack_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_pixel_pack_0.v │ │ │ ├── design_1_pixel_unpack_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_pixel_unpack_0.v │ │ │ ├── design_1_proc_sys_reset_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_proc_sys_reset_0_0.vhd │ │ │ ├── design_1_proc_sys_reset_0_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_proc_sys_reset_0_1.vhd │ │ │ ├── design_1_proc_sys_reset_pixelclk_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_proc_sys_reset_pixelclk_0.vhd │ │ │ ├── design_1_processing_system7_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_processing_system7_0_0.v │ │ │ ├── design_1_rgb2dvi_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_rgb2dvi_0_0.vhd │ │ │ ├── design_1_s00_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_s00_regslice_0.v │ │ │ ├── design_1_s00_regslice_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_s00_regslice_1.v │ │ │ ├── design_1_s01_regslice_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_s01_regslice_0.v │ │ │ ├── design_1_v_axi4s_vid_out_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_v_axi4s_vid_out_0_0.v │ │ │ ├── design_1_v_vid_in_axi4s_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_v_vid_in_axi4s_0_0.v │ │ │ ├── design_1_vtc_in_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_vtc_in_0.vhd │ │ │ ├── design_1_vtc_out_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_vtc_out_0.vhd │ │ │ ├── design_1_xbar_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xbar_0.v │ │ │ ├── design_1_xbar_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xbar_1.v │ │ │ ├── design_1_xbar_2 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xbar_2.v │ │ │ ├── design_1_xbar_3 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xbar_3.v │ │ │ ├── design_1_xbar_4 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xbar_4.v │ │ │ ├── design_1_xbar_5 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xbar_5.v │ │ │ ├── design_1_xbar_6 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xbar_6.v │ │ │ ├── design_1_xlconcat_0_0 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xlconcat_0_0.v │ │ │ ├── design_1_xlconcat_0_1 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xlconcat_0_1.v │ │ │ ├── design_1_xlconcat_0_2 │ │ │ │ └── sim │ │ │ │ │ └── design_1_xlconcat_0_2.v │ │ │ └── design_1_xlconstant_0_0 │ │ │ │ └── sim │ │ │ │ └── design_1_xlconstant_0_0.v │ │ │ ├── ipshared │ │ │ └── fac8 │ │ │ │ └── color_swap.v │ │ │ └── sim │ │ │ └── design_1.v │ ├── ipstatic │ │ ├── axi_clock_converter_v2_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ ├── axi_clock_converter_v2_1_axic_sample_cycle_ratio.v │ │ │ │ └── axi_clock_converter_v2_1_axic_sync_clock_converter.v │ │ ├── axi_crossbar_v2_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ ├── axi_crossbar_v2_1_addr_arbiter.v │ │ │ │ ├── axi_crossbar_v2_1_addr_arbiter_sasd.v │ │ │ │ ├── axi_crossbar_v2_1_addr_decoder.v │ │ │ │ ├── axi_crossbar_v2_1_arbiter_resp.v │ │ │ │ ├── axi_crossbar_v2_1_crossbar.v │ │ │ │ ├── axi_crossbar_v2_1_crossbar_sasd.v │ │ │ │ ├── axi_crossbar_v2_1_decerr_slave.v │ │ │ │ ├── axi_crossbar_v2_1_si_transactor.v │ │ │ │ ├── axi_crossbar_v2_1_splitter.v │ │ │ │ ├── axi_crossbar_v2_1_wdata_mux.v │ │ │ │ └── axi_crossbar_v2_1_wdata_router.v │ │ ├── axi_data_fifo_v2_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ ├── axi_data_fifo_v2_1_axic_fifo.v │ │ │ │ ├── axi_data_fifo_v2_1_axic_reg_srl_fifo.v │ │ │ │ ├── axi_data_fifo_v2_1_axic_srl_fifo.v │ │ │ │ ├── axi_data_fifo_v2_1_fifo_gen.v │ │ │ │ └── axi_data_fifo_v2_1_ndeep_srl.v │ │ ├── axi_datamover_v5_1 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ ├── axi_datamover_addr_cntl.vhd │ │ │ │ ├── axi_datamover_afifo_autord.vhd │ │ │ │ ├── axi_datamover_cmd_status.vhd │ │ │ │ ├── axi_datamover_dre_mux2_1_x_n.vhd │ │ │ │ ├── axi_datamover_dre_mux4_1_x_n.vhd │ │ │ │ ├── axi_datamover_dre_mux8_1_x_n.vhd │ │ │ │ ├── axi_datamover_fifo.vhd │ │ │ │ ├── axi_datamover_ibttcc.vhd │ │ │ │ ├── axi_datamover_indet_btt.vhd │ │ │ │ ├── axi_datamover_mm2s_basic_wrap.vhd │ │ │ │ ├── axi_datamover_mm2s_dre.vhd │ │ │ │ ├── axi_datamover_mm2s_full_wrap.vhd │ │ │ │ ├── axi_datamover_mm2s_omit_wrap.vhd │ │ │ │ ├── axi_datamover_ms_strb_set.vhd │ │ │ │ ├── axi_datamover_mssai_skid_buf.vhd │ │ │ │ ├── axi_datamover_pcc.vhd │ │ │ │ ├── axi_datamover_rd_sf.vhd │ │ │ │ ├── axi_datamover_rd_status_cntl.vhd │ │ │ │ ├── axi_datamover_rddata_cntl.vhd │ │ │ │ ├── axi_datamover_rdmux.vhd │ │ │ │ ├── axi_datamover_reset.vhd │ │ │ │ ├── axi_datamover_s2mm_basic_wrap.vhd │ │ │ │ ├── axi_datamover_s2mm_dre.vhd │ │ │ │ ├── axi_datamover_s2mm_full_wrap.vhd │ │ │ │ ├── axi_datamover_s2mm_omit_wrap.vhd │ │ │ │ ├── axi_datamover_s2mm_realign.vhd │ │ │ │ ├── axi_datamover_s2mm_scatter.vhd │ │ │ │ ├── axi_datamover_scc.vhd │ │ │ │ ├── axi_datamover_sfifo_autord.vhd │ │ │ │ ├── axi_datamover_skid2mm_buf.vhd │ │ │ │ ├── axi_datamover_skid_buf.vhd │ │ │ │ ├── axi_datamover_slice.vhd │ │ │ │ ├── axi_datamover_stbs_set.vhd │ │ │ │ ├── axi_datamover_stbs_set_nodre.vhd │ │ │ │ ├── axi_datamover_strb_gen2.vhd │ │ │ │ ├── axi_datamover_wr_demux.vhd │ │ │ │ ├── axi_datamover_wr_sf.vhd │ │ │ │ ├── axi_datamover_wr_status_cntl.vhd │ │ │ │ └── axi_datamover_wrdata_cntl.vhd │ │ ├── axi_dma_v7_1 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ ├── axi_dma_afifo_autord.vhd │ │ │ │ ├── axi_dma_cmd_split.vhd │ │ │ │ ├── axi_dma_lite_if.vhd │ │ │ │ ├── axi_dma_mm2s_cmdsts_if.vhd │ │ │ │ ├── axi_dma_mm2s_cntrl_strm.vhd │ │ │ │ ├── axi_dma_mm2s_mngr.vhd │ │ │ │ ├── axi_dma_mm2s_sg_if.vhd │ │ │ │ ├── axi_dma_mm2s_sm.vhd │ │ │ │ ├── axi_dma_mm2s_sts_mngr.vhd │ │ │ │ ├── axi_dma_pkg.vhd │ │ │ │ ├── axi_dma_reg_module.vhd │ │ │ │ ├── axi_dma_register.vhd │ │ │ │ ├── axi_dma_register_s2mm.vhd │ │ │ │ ├── axi_dma_reset.vhd │ │ │ │ ├── axi_dma_rst_module.vhd │ │ │ │ ├── axi_dma_s2mm.vhd │ │ │ │ ├── axi_dma_s2mm_cmdsts_if.vhd │ │ │ │ ├── axi_dma_s2mm_mngr.vhd │ │ │ │ ├── axi_dma_s2mm_sg_if.vhd │ │ │ │ ├── axi_dma_s2mm_sm.vhd │ │ │ │ ├── axi_dma_s2mm_sts_mngr.vhd │ │ │ │ ├── axi_dma_s2mm_sts_strm.vhd │ │ │ │ ├── axi_dma_skid_buf.vhd │ │ │ │ ├── axi_dma_smple_sm.vhd │ │ │ │ └── axi_dma_sofeof_gen.vhd │ │ ├── axi_dwidth_converter_v2_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ ├── axi_dwidth_converter_v2_1_a_downsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_a_upsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_axi4lite_downsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_axi4lite_upsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_axi_downsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_axi_upsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_b_downsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_r_downsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_r_upsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_r_upsizer_pktfifo.v │ │ │ │ ├── axi_dwidth_converter_v2_1_w_downsizer.v │ │ │ │ ├── axi_dwidth_converter_v2_1_w_upsizer.v │ │ │ │ └── axi_dwidth_converter_v2_1_w_upsizer_pktfifo.v │ │ ├── axi_infrastructure_v1_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ ├── axi_infrastructure_v1_1_axi2vector.v │ │ │ │ └── axi_infrastructure_v1_1_axic_srl_fifo.v │ │ ├── axi_intc_v4_1 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ ├── double_synchronizer.vhd │ │ │ │ ├── intc_core.vhd │ │ │ │ ├── pulse_synchronizer.vhd │ │ │ │ └── shared_ram_ivar.vhd │ │ ├── axi_lite_ipif_v3_0 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ ├── address_decoder.vhd │ │ │ │ ├── ipif_pkg.vhd │ │ │ │ ├── pselect_f.vhd │ │ │ │ └── slave_attachment.vhd │ │ ├── axi_protocol_converter_v2_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ ├── axi_protocol_converter_v2_1_a_axi3_conv.v │ │ │ │ ├── axi_protocol_converter_v2_1_axi3_conv.v │ │ │ │ ├── axi_protocol_converter_v2_1_axilite_conv.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_ar_channel.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_aw_channel.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_b_channel.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_cmd_translator.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_incr_cmd.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_r_channel.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_simple_fifo.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v │ │ │ │ ├── axi_protocol_converter_v2_1_b2s_wrap_cmd.v │ │ │ │ ├── axi_protocol_converter_v2_1_b_downsizer.v │ │ │ │ ├── axi_protocol_converter_v2_1_decerr_slave.v │ │ │ │ ├── axi_protocol_converter_v2_1_r_axi3_conv.v │ │ │ │ └── axi_protocol_converter_v2_1_w_axi3_conv.v │ │ ├── axi_register_slice_v2_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ └── axi_register_slice_v2_1_axic_register_slice.v │ │ ├── axi_sg_v4_1 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ ├── axi_sg_addr_cntl.vhd │ │ │ │ ├── axi_sg_afifo_autord.vhd │ │ │ │ ├── axi_sg_cmd_status.vhd │ │ │ │ ├── axi_sg_cntrl_strm.vhd │ │ │ │ ├── axi_sg_datamover.vhd │ │ │ │ ├── axi_sg_fifo.vhd │ │ │ │ ├── axi_sg_ftch_cmdsts_if.vhd │ │ │ │ ├── axi_sg_ftch_mngr.vhd │ │ │ │ ├── axi_sg_ftch_noqueue.vhd │ │ │ │ ├── axi_sg_ftch_pntr.vhd │ │ │ │ ├── axi_sg_ftch_q_mngr.vhd │ │ │ │ ├── axi_sg_ftch_queue.vhd │ │ │ │ ├── axi_sg_ftch_sm.vhd │ │ │ │ ├── axi_sg_intrpt.vhd │ │ │ │ ├── axi_sg_mm2s_basic_wrap.vhd │ │ │ │ ├── axi_sg_pkg.vhd │ │ │ │ ├── axi_sg_rd_status_cntl.vhd │ │ │ │ ├── axi_sg_rddata_cntl.vhd │ │ │ │ ├── axi_sg_rdmux.vhd │ │ │ │ ├── axi_sg_reset.vhd │ │ │ │ ├── axi_sg_s2mm_basic_wrap.vhd │ │ │ │ ├── axi_sg_scc.vhd │ │ │ │ ├── axi_sg_scc_wr.vhd │ │ │ │ ├── axi_sg_sfifo_autord.vhd │ │ │ │ ├── axi_sg_skid2mm_buf.vhd │ │ │ │ ├── axi_sg_skid_buf.vhd │ │ │ │ ├── axi_sg_updt_cmdsts_if.vhd │ │ │ │ ├── axi_sg_updt_mngr.vhd │ │ │ │ ├── axi_sg_updt_noqueue.vhd │ │ │ │ ├── axi_sg_updt_q_mngr.vhd │ │ │ │ ├── axi_sg_updt_queue.vhd │ │ │ │ ├── axi_sg_updt_sm.vhd │ │ │ │ ├── axi_sg_wr_demux.vhd │ │ │ │ ├── axi_sg_wr_status_cntl.vhd │ │ │ │ └── axi_sg_wrdata_cntl.vhd │ │ ├── blk_mem_gen_v8_3 │ │ │ └── hdl │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ ├── fifo_generator_v13_1 │ │ │ ├── hdl │ │ │ │ ├── fifo_generator_v13_1.vhd │ │ │ │ ├── fifo_generator_v13_1_rfs.vhd │ │ │ │ └── fifo_generator_v13_1_vhsyn_rfs.vhd │ │ │ └── simulation │ │ │ │ └── fifo_generator_vlog_beh.v │ │ ├── generic_baseblocks_v2_1 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ ├── generic_baseblocks_v2_1_carry.v │ │ │ │ ├── generic_baseblocks_v2_1_carry_and.v │ │ │ │ ├── generic_baseblocks_v2_1_carry_latch_and.v │ │ │ │ ├── generic_baseblocks_v2_1_carry_latch_or.v │ │ │ │ ├── generic_baseblocks_v2_1_carry_or.v │ │ │ │ ├── generic_baseblocks_v2_1_command_fifo.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator_mask.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator_mask_static.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator_sel.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator_sel_mask.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator_sel_mask_static.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator_sel_static.v │ │ │ │ ├── generic_baseblocks_v2_1_comparator_static.v │ │ │ │ ├── generic_baseblocks_v2_1_mux.v │ │ │ │ └── generic_baseblocks_v2_1_mux_enc.v │ │ ├── image_filter_bw_v1_0 │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ └── image_filter_bw.v │ │ ├── lib_fifo_v1_0 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ └── async_fifo_fg.vhd │ │ ├── lib_srl_fifo_v1_0 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ ├── cntr_incr_decr_addn_f.vhd │ │ │ │ ├── dynshreg_f.vhd │ │ │ │ └── srl_fifo_rbu_f.vhd │ │ ├── proc_sys_reset_v5_0 │ │ │ └── hdl │ │ │ │ └── src │ │ │ │ └── vhdl │ │ │ │ ├── lpf.vhd │ │ │ │ ├── sequence_psr.vhd │ │ │ │ └── upcnt_n.vhd │ │ ├── processing_system7_bfm_v2_0 │ │ │ └── hdl │ │ │ │ ├── processing_system7_bfm_v2_0_5_apis.v │ │ │ │ ├── processing_system7_bfm_v2_0_5_axi_acp.v │ │ │ │ ├── processing_system7_bfm_v2_0_5_axi_gp.v │ │ │ │ ├── processing_system7_bfm_v2_0_5_axi_hp.v │ │ │ │ ├── processing_system7_bfm_v2_0_5_local_params.v │ │ │ │ ├── processing_system7_bfm_v2_0_5_reg_init.v │ │ │ │ ├── processing_system7_bfm_v2_0_5_reg_params.v │ │ │ │ ├── processing_system7_bfm_v2_0_5_unused_ports.v │ │ │ │ ├── processing_system7_bfm_v2_0_afi_slave.v │ │ │ │ ├── processing_system7_bfm_v2_0_arb_hp0_1.v │ │ │ │ ├── processing_system7_bfm_v2_0_arb_hp2_3.v │ │ │ │ ├── processing_system7_bfm_v2_0_arb_rd.v │ │ │ │ ├── processing_system7_bfm_v2_0_arb_rd_4.v │ │ │ │ ├── processing_system7_bfm_v2_0_arb_wr.v │ │ │ │ ├── processing_system7_bfm_v2_0_arb_wr_4.v │ │ │ │ ├── processing_system7_bfm_v2_0_axi_master.v │ │ │ │ ├── processing_system7_bfm_v2_0_axi_slave.v │ │ │ │ ├── processing_system7_bfm_v2_0_ddrc.v │ │ │ │ ├── processing_system7_bfm_v2_0_fmsw_gp.v │ │ │ │ ├── processing_system7_bfm_v2_0_gen_clock.v │ │ │ │ ├── processing_system7_bfm_v2_0_gen_reset.v │ │ │ │ ├── processing_system7_bfm_v2_0_interconnect_model.v │ │ │ │ ├── processing_system7_bfm_v2_0_intr_rd_mem.v │ │ │ │ ├── processing_system7_bfm_v2_0_intr_wr_mem.v │ │ │ │ ├── processing_system7_bfm_v2_0_ocm_mem.v │ │ │ │ ├── processing_system7_bfm_v2_0_ocmc.v │ │ │ │ ├── processing_system7_bfm_v2_0_reg_map.v │ │ │ │ ├── processing_system7_bfm_v2_0_regc.v │ │ │ │ ├── processing_system7_bfm_v2_0_sparse_mem.v │ │ │ │ └── processing_system7_bfm_v2_0_ssw_hp.v │ │ └── stream_math_stream_v1_0 │ │ │ └── hdl │ │ │ └── verilog │ │ │ ├── FIFO_stream_math_stream_channels_channel.v │ │ │ ├── FIFO_stream_math_stream_channels_channel5.v │ │ │ ├── FIFO_stream_math_stream_cols_cast_channel.v │ │ │ ├── FIFO_stream_math_stream_cols_channel.v │ │ │ ├── FIFO_stream_math_stream_g_img_data_stream_0_V.v │ │ │ ├── FIFO_stream_math_stream_newret.v │ │ │ ├── FIFO_stream_math_stream_newret1.v │ │ │ ├── FIFO_stream_math_stream_newret3.v │ │ │ ├── FIFO_stream_math_stream_rows_cast_channel.v │ │ │ ├── FIFO_stream_math_stream_rows_channel.v │ │ │ ├── FIFO_stream_math_stream_rows_channel33.v │ │ │ ├── stream_math_stream.v │ │ │ ├── stream_math_stream_Block_proc.v │ │ │ ├── stream_math_stream_CONTROL_BUS_s_axi.v │ │ │ ├── stream_math_stream_Loop_1_proc.v │ │ │ ├── stream_math_stream_Loop_2_proc1.v │ │ │ ├── stream_math_stream_mul_11ns_32s_32_3.v │ │ │ └── stream_math_stream_stream_math_stream_entry25.v │ └── mem_init_files │ │ ├── ps7_init.h │ │ ├── ps7_init.tcl │ │ └── ps7_init_gpl.h ├── cv2PYNQ_vivado.xpr ├── cv2PYNQ_vivado_def_val.txt ├── cv2PYNQ_vivado_dump.txt └── ip_upgrade.log ├── doc ├── PYNQ-OpenCV_xohw18-155.pdf ├── block_design.PNG └── image_filter_block_design.PNG ├── hw ├── cv2pynq03.bit └── cv2pynq03.tcl └── ip ├── HLS ├── canny │ ├── .apc │ │ └── autopilot.apfmapping │ ├── .cproject │ ├── .project │ ├── .settings │ │ ├── canny.Debug.launch │ │ ├── canny.Release.launch │ │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── canny_edge.cpp │ ├── canny_edge.h │ ├── canny_edge_test.cpp │ ├── lena_gray.bmp │ ├── solution1 │ │ ├── directives.tcl │ │ ├── impl │ │ │ ├── ip │ │ │ │ ├── autoimpl.log │ │ │ │ ├── auxiliary.xml │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── canny_edge_info.xml │ │ │ │ ├── component.xml │ │ │ │ ├── constraints │ │ │ │ │ ├── canny_edge.xdc │ │ │ │ │ └── canny_edge_ooc.xdc │ │ │ │ ├── doc │ │ │ │ │ └── ReleaseNotes.txt │ │ │ │ ├── drivers │ │ │ │ │ └── canny_edge_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── canny_edge.mdd │ │ │ │ │ │ └── canny_edge.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xcanny_edge.c │ │ │ │ │ │ ├── xcanny_edge.h │ │ │ │ │ │ ├── xcanny_edge_hw.h │ │ │ │ │ │ ├── xcanny_edge_linux.c │ │ │ │ │ │ └── xcanny_edge_sinit.c │ │ │ │ ├── example │ │ │ │ │ ├── ipi_example.bat │ │ │ │ │ └── ipi_example.tcl │ │ │ │ ├── hdl │ │ │ │ │ ├── verilog │ │ │ │ │ │ ├── Block_Mat_exit29635_s.v │ │ │ │ │ │ ├── Duplicate_canny.v │ │ │ │ │ │ ├── Filter2D_canny.v │ │ │ │ │ │ ├── Filter2D_k_buf_0_cud.v │ │ │ │ │ │ ├── Loop_1_proc_canny.v │ │ │ │ │ │ ├── Loop_2_proc_canny.v │ │ │ │ │ │ ├── Sobel_1_canny.v │ │ │ │ │ │ ├── Sobel_canny.v │ │ │ │ │ │ ├── canny_edge.v │ │ │ │ │ │ ├── canny_edge_CONTROL_BUS_s_axi.v │ │ │ │ │ │ ├── canny_edge_mac_mug8j.v │ │ │ │ │ │ ├── canny_edge_mac_muhbi.v │ │ │ │ │ │ ├── canny_edge_mac_muibs.v │ │ │ │ │ │ ├── canny_edge_mac_mujbC.v │ │ │ │ │ │ ├── canny_edge_mac_mukbM.v │ │ │ │ │ │ ├── canny_edge_mac_mulbW.v │ │ │ │ │ │ ├── canny_edge_mul_mubkb.v │ │ │ │ │ │ ├── canny_edge_mul_muqcK.v │ │ │ │ │ │ ├── canny_edge_mux_32fYi.v │ │ │ │ │ │ ├── fifo_w16_d1_A.v │ │ │ │ │ │ ├── fifo_w20_d2_A.v │ │ │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ │ │ ├── fifo_w9_d7_A.v │ │ │ │ │ │ ├── gradient_decompositi.v │ │ │ │ │ │ ├── hysteresis.v │ │ │ │ │ │ ├── nonmax_suppressiomb6.v │ │ │ │ │ │ └── nonmax_suppression.v │ │ │ │ │ └── vhdl │ │ │ │ │ │ ├── Block_Mat_exit29635_s.vhd │ │ │ │ │ │ ├── Duplicate.vhd │ │ │ │ │ │ ├── Filter2D.vhd │ │ │ │ │ │ ├── Filter2D_k_buf_0_cud.vhd │ │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ │ │ ├── Sobel.vhd │ │ │ │ │ │ ├── Sobel_1.vhd │ │ │ │ │ │ ├── canny_edge.vhd │ │ │ │ │ │ ├── canny_edge_CONTROL_BUS_s_axi.vhd │ │ │ │ │ │ ├── canny_edge_mac_mug8j.vhd │ │ │ │ │ │ ├── canny_edge_mac_muhbi.vhd │ │ │ │ │ │ ├── canny_edge_mac_muibs.vhd │ │ │ │ │ │ ├── canny_edge_mac_mujbC.vhd │ │ │ │ │ │ ├── canny_edge_mac_mukbM.vhd │ │ │ │ │ │ ├── canny_edge_mac_mulbW.vhd │ │ │ │ │ │ ├── canny_edge_mul_mubkb.vhd │ │ │ │ │ │ ├── canny_edge_mul_muqcK.vhd │ │ │ │ │ │ ├── canny_edge_mux_32fYi.vhd │ │ │ │ │ │ ├── fifo_w16_d1_A.vhd │ │ │ │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ │ │ ├── fifo_w9_d7_A.vhd │ │ │ │ │ │ ├── gradient_decompositi.vhd │ │ │ │ │ │ ├── hysteresis.vhd │ │ │ │ │ │ ├── nonmax_suppressiomb6.vhd │ │ │ │ │ │ └── nonmax_suppression.vhd │ │ │ │ ├── misc │ │ │ │ │ └── logo.png │ │ │ │ ├── pack.bat │ │ │ │ ├── run_ippack.tcl │ │ │ │ ├── vivado.jou │ │ │ │ ├── vivado.log │ │ │ │ ├── xgui │ │ │ │ │ └── canny_edge_v1_0.tcl │ │ │ │ └── xilinx_com_hls_canny_edge_1_0.zip │ │ │ ├── misc │ │ │ │ ├── drivers │ │ │ │ │ └── canny_edge_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── canny_edge.mdd │ │ │ │ │ │ └── canny_edge.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xcanny_edge.c │ │ │ │ │ │ ├── xcanny_edge.h │ │ │ │ │ │ ├── xcanny_edge_hw.h │ │ │ │ │ │ ├── xcanny_edge_linux.c │ │ │ │ │ │ └── xcanny_edge_sinit.c │ │ │ │ └── logo.png │ │ │ ├── report │ │ │ │ └── verilog │ │ │ │ │ ├── canny_edge_export.rpt │ │ │ │ │ └── canny_edge_export.xml │ │ │ ├── verilog │ │ │ │ ├── Block_Mat_exit29635_s.v │ │ │ │ ├── Duplicate_canny.v │ │ │ │ ├── Filter2D_canny.v │ │ │ │ ├── Filter2D_k_buf_0_cud.v │ │ │ │ ├── Loop_1_proc_canny.v │ │ │ │ ├── Loop_2_proc_canny.v │ │ │ │ ├── Sobel_1_canny.v │ │ │ │ ├── Sobel_canny.v │ │ │ │ ├── autoimpl.log │ │ │ │ ├── canny_edge.result.rb │ │ │ │ ├── canny_edge.v │ │ │ │ ├── canny_edge.xdc │ │ │ │ ├── canny_edge_CONTROL_BUS_s_axi.v │ │ │ │ ├── canny_edge_mac_mug8j.v │ │ │ │ ├── canny_edge_mac_muhbi.v │ │ │ │ ├── canny_edge_mac_muibs.v │ │ │ │ ├── canny_edge_mac_mujbC.v │ │ │ │ ├── canny_edge_mac_mukbM.v │ │ │ │ ├── canny_edge_mac_mulbW.v │ │ │ │ ├── canny_edge_mul_mubkb.v │ │ │ │ ├── canny_edge_mul_muqcK.v │ │ │ │ ├── canny_edge_mux_32fYi.v │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w16_d1_A.v │ │ │ │ ├── fifo_w20_d2_A.v │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ ├── fifo_w9_d7_A.v │ │ │ │ ├── gradient_decompositi.v │ │ │ │ ├── hysteresis.v │ │ │ │ ├── impl.bat │ │ │ │ ├── nonmax_suppressiomb6.v │ │ │ │ ├── nonmax_suppression.v │ │ │ │ ├── project.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ └── synthesis.wdf │ │ │ │ ├── project.hw │ │ │ │ │ └── project.lpr │ │ │ │ ├── project.runs │ │ │ │ │ ├── .jobs │ │ │ │ │ │ └── vrs_config_1.xml │ │ │ │ │ └── synth_1 │ │ │ │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── canny_edge.dcp │ │ │ │ │ │ ├── canny_edge.tcl │ │ │ │ │ │ ├── canny_edge.vds │ │ │ │ │ │ ├── canny_edge_utilization_synth.pb │ │ │ │ │ │ ├── canny_edge_utilization_synth.rpt │ │ │ │ │ │ ├── fsm_encoding.os │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ ├── project.xpr │ │ │ │ ├── report │ │ │ │ │ ├── canny_edge_timing_synth.rpt │ │ │ │ │ └── canny_edge_utilization_synth.rpt │ │ │ │ ├── run_vivado.tcl │ │ │ │ ├── settings.tcl │ │ │ │ ├── vivado.jou │ │ │ │ └── vivado.log │ │ │ └── vhdl │ │ │ │ ├── Block_Mat_exit29635_s.vhd │ │ │ │ ├── Duplicate.vhd │ │ │ │ ├── Filter2D.vhd │ │ │ │ ├── Filter2D_k_buf_0_cud.vhd │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ ├── Sobel.vhd │ │ │ │ ├── Sobel_1.vhd │ │ │ │ ├── canny_edge.vhd │ │ │ │ ├── canny_edge_CONTROL_BUS_s_axi.vhd │ │ │ │ ├── canny_edge_mac_mug8j.vhd │ │ │ │ ├── canny_edge_mac_muhbi.vhd │ │ │ │ ├── canny_edge_mac_muibs.vhd │ │ │ │ ├── canny_edge_mac_mujbC.vhd │ │ │ │ ├── canny_edge_mac_mukbM.vhd │ │ │ │ ├── canny_edge_mac_mulbW.vhd │ │ │ │ ├── canny_edge_mul_mubkb.vhd │ │ │ │ ├── canny_edge_mul_muqcK.vhd │ │ │ │ ├── canny_edge_mux_32fYi.vhd │ │ │ │ ├── fifo_w16_d1_A.vhd │ │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ ├── fifo_w9_d7_A.vhd │ │ │ │ ├── gradient_decompositi.vhd │ │ │ │ ├── hysteresis.vhd │ │ │ │ ├── nonmax_suppressiomb6.vhd │ │ │ │ └── nonmax_suppression.vhd │ │ ├── script.tcl │ │ ├── solution1.aps │ │ ├── solution1.directive │ │ ├── solution1.log │ │ └── solution1_data.json │ └── vivado_hls.app ├── dilate │ ├── .apc │ │ └── autopilot.apfmapping │ ├── .cproject │ ├── .project │ ├── .settings │ │ ├── dilate.Debug.launch │ │ ├── dilate.Release.launch │ │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── dilate_hls.cpp │ ├── dilate_hls.h │ ├── dilate_hls_test.cpp │ ├── lena_gray.bmp │ ├── solution1 │ │ ├── directives.tcl │ │ ├── impl │ │ │ ├── ip │ │ │ │ ├── autoimpl.log │ │ │ │ ├── auxiliary.xml │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── constraints │ │ │ │ │ ├── dilate_hls.xdc │ │ │ │ │ └── dilate_hls_ooc.xdc │ │ │ │ ├── dilate_hls_info.xml │ │ │ │ ├── doc │ │ │ │ │ └── ReleaseNotes.txt │ │ │ │ ├── drivers │ │ │ │ │ └── dilate_hls_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── dilate_hls.mdd │ │ │ │ │ │ └── dilate_hls.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xdilate_hls.c │ │ │ │ │ │ ├── xdilate_hls.h │ │ │ │ │ │ ├── xdilate_hls_hw.h │ │ │ │ │ │ ├── xdilate_hls_linux.c │ │ │ │ │ │ └── xdilate_hls_sinit.c │ │ │ │ ├── example │ │ │ │ │ ├── ipi_example.bat │ │ │ │ │ └── ipi_example.tcl │ │ │ │ ├── hdl │ │ │ │ │ ├── verilog │ │ │ │ │ │ ├── Block_Mat_exit406734_dilate.v │ │ │ │ │ │ ├── Block_arrayctor_loop.v │ │ │ │ │ │ ├── Loop_1_proc_dilate.v │ │ │ │ │ │ ├── Loop_3_proc_dilate.v │ │ │ │ │ │ ├── Loop_loop_height_dEe.v │ │ │ │ │ │ ├── Loop_loop_height_pro_dilate.v │ │ │ │ │ │ ├── dilate_hls.v │ │ │ │ │ │ ├── dilate_hls_CONTROL_BUS_s_axi.v │ │ │ │ │ │ ├── dilate_hls_mul_31hbi.v │ │ │ │ │ │ ├── dilate_hls_mul_32bkb.v │ │ │ │ │ │ ├── dilate_hls_mul_32cud.v │ │ │ │ │ │ ├── dilate_hls_mux_32g8j.v │ │ │ │ │ │ ├── fifo_w11_d1_A.v │ │ │ │ │ │ ├── fifo_w11_d2_A.v │ │ │ │ │ │ ├── fifo_w1_d2_A.v │ │ │ │ │ │ ├── fifo_w31_d3_A.v │ │ │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ │ │ └── fifo_w8_d1_A.v │ │ │ │ │ └── vhdl │ │ │ │ │ │ ├── Block_Mat_exit406734.vhd │ │ │ │ │ │ ├── Block_arrayctor_loop.vhd │ │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ │ ├── Loop_3_proc.vhd │ │ │ │ │ │ ├── Loop_loop_height_dEe.vhd │ │ │ │ │ │ ├── Loop_loop_height_pro.vhd │ │ │ │ │ │ ├── dilate_hls.vhd │ │ │ │ │ │ ├── dilate_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ │ │ ├── dilate_hls_mul_31hbi.vhd │ │ │ │ │ │ ├── dilate_hls_mul_32bkb.vhd │ │ │ │ │ │ ├── dilate_hls_mul_32cud.vhd │ │ │ │ │ │ ├── dilate_hls_mux_32g8j.vhd │ │ │ │ │ │ ├── fifo_w11_d1_A.vhd │ │ │ │ │ │ ├── fifo_w11_d2_A.vhd │ │ │ │ │ │ ├── fifo_w1_d2_A.vhd │ │ │ │ │ │ ├── fifo_w31_d3_A.vhd │ │ │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ │ │ └── fifo_w8_d1_A.vhd │ │ │ │ ├── misc │ │ │ │ │ └── logo.png │ │ │ │ ├── pack.bat │ │ │ │ ├── run_ippack.tcl │ │ │ │ ├── vivado.jou │ │ │ │ ├── vivado.log │ │ │ │ ├── xgui │ │ │ │ │ └── dilate_hls_v1_0.tcl │ │ │ │ └── xilinx_com_hls_dilate_hls_1_0.zip │ │ │ ├── misc │ │ │ │ ├── drivers │ │ │ │ │ └── dilate_hls_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── dilate_hls.mdd │ │ │ │ │ │ └── dilate_hls.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xdilate_hls.c │ │ │ │ │ │ ├── xdilate_hls.h │ │ │ │ │ │ ├── xdilate_hls_hw.h │ │ │ │ │ │ ├── xdilate_hls_linux.c │ │ │ │ │ │ └── xdilate_hls_sinit.c │ │ │ │ └── logo.png │ │ │ ├── report │ │ │ │ └── verilog │ │ │ │ │ ├── dilate_hls_export.rpt │ │ │ │ │ └── dilate_hls_export.xml │ │ │ ├── verilog │ │ │ │ ├── Block_Mat_exit406734_dilate.v │ │ │ │ ├── Block_arrayctor_loop.v │ │ │ │ ├── Loop_1_proc_dilate.v │ │ │ │ ├── Loop_3_proc_dilate.v │ │ │ │ ├── Loop_loop_height_dEe.v │ │ │ │ ├── Loop_loop_height_pro_dilate.v │ │ │ │ ├── autoimpl.log │ │ │ │ ├── dilate_hls.result.rb │ │ │ │ ├── dilate_hls.v │ │ │ │ ├── dilate_hls.xdc │ │ │ │ ├── dilate_hls_CONTROL_BUS_s_axi.v │ │ │ │ ├── dilate_hls_mul_31hbi.v │ │ │ │ ├── dilate_hls_mul_32bkb.v │ │ │ │ ├── dilate_hls_mul_32cud.v │ │ │ │ ├── dilate_hls_mux_32g8j.v │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w11_d1_A.v │ │ │ │ ├── fifo_w11_d2_A.v │ │ │ │ ├── fifo_w1_d2_A.v │ │ │ │ ├── fifo_w31_d3_A.v │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ ├── impl.bat │ │ │ │ ├── project.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ ├── synthesis.wdf │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── project.hw │ │ │ │ │ └── project.lpr │ │ │ │ ├── project.runs │ │ │ │ │ ├── .jobs │ │ │ │ │ │ ├── vrs_config_1.xml │ │ │ │ │ │ └── vrs_config_2.xml │ │ │ │ │ ├── impl_1 │ │ │ │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ │ │ │ ├── .init_design.begin.rst │ │ │ │ │ │ ├── .init_design.end.rst │ │ │ │ │ │ ├── .opt_design.begin.rst │ │ │ │ │ │ ├── .opt_design.end.rst │ │ │ │ │ │ ├── .phys_opt_design.begin.rst │ │ │ │ │ │ ├── .phys_opt_design.end.rst │ │ │ │ │ │ ├── .place_design.begin.rst │ │ │ │ │ │ ├── .place_design.end.rst │ │ │ │ │ │ ├── .route_design.begin.rst │ │ │ │ │ │ ├── .route_design.end.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── dilate_hls.dcp │ │ │ │ │ │ ├── dilate_hls.tcl │ │ │ │ │ │ ├── dilate_hls.vdi │ │ │ │ │ │ ├── dilate_hls_clock_utilization_routed.rpt │ │ │ │ │ │ ├── dilate_hls_control_sets_placed.rpt │ │ │ │ │ │ ├── dilate_hls_drc_opted.pb │ │ │ │ │ │ ├── dilate_hls_drc_opted.rpt │ │ │ │ │ │ ├── dilate_hls_drc_opted.rpx │ │ │ │ │ │ ├── dilate_hls_drc_routed.pb │ │ │ │ │ │ ├── dilate_hls_drc_routed.rpt │ │ │ │ │ │ ├── dilate_hls_drc_routed.rpx │ │ │ │ │ │ ├── dilate_hls_io_placed.rpt │ │ │ │ │ │ ├── dilate_hls_methodology_drc_routed.pb │ │ │ │ │ │ ├── dilate_hls_methodology_drc_routed.rpt │ │ │ │ │ │ ├── dilate_hls_methodology_drc_routed.rpx │ │ │ │ │ │ ├── dilate_hls_opt.dcp │ │ │ │ │ │ ├── dilate_hls_physopt.dcp │ │ │ │ │ │ ├── dilate_hls_placed.dcp │ │ │ │ │ │ ├── dilate_hls_power_routed.rpt │ │ │ │ │ │ ├── dilate_hls_power_routed.rpx │ │ │ │ │ │ ├── dilate_hls_power_summary_routed.pb │ │ │ │ │ │ ├── dilate_hls_route_status.pb │ │ │ │ │ │ ├── dilate_hls_route_status.rpt │ │ │ │ │ │ ├── dilate_hls_routed.dcp │ │ │ │ │ │ ├── dilate_hls_timing_summary_routed.rpt │ │ │ │ │ │ ├── dilate_hls_timing_summary_routed.rpx │ │ │ │ │ │ ├── dilate_hls_utilization_placed.pb │ │ │ │ │ │ ├── dilate_hls_utilization_placed.rpt │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── init_design.pb │ │ │ │ │ │ ├── opt_design.pb │ │ │ │ │ │ ├── phys_opt_design.pb │ │ │ │ │ │ ├── place_design.pb │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── route_design.pb │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ │ └── synth_1 │ │ │ │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── dilate_hls.dcp │ │ │ │ │ │ ├── dilate_hls.tcl │ │ │ │ │ │ ├── dilate_hls.vds │ │ │ │ │ │ ├── dilate_hls_utilization_synth.pb │ │ │ │ │ │ ├── dilate_hls_utilization_synth.rpt │ │ │ │ │ │ ├── fsm_encoding.os │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ ├── project.xpr │ │ │ │ ├── report │ │ │ │ │ ├── dilate_hls_timing_routed.rpt │ │ │ │ │ ├── dilate_hls_timing_synth.rpt │ │ │ │ │ ├── dilate_hls_utilization_routed.rpt │ │ │ │ │ └── dilate_hls_utilization_synth.rpt │ │ │ │ ├── run_vivado.tcl │ │ │ │ ├── settings.tcl │ │ │ │ ├── vivado.jou │ │ │ │ └── vivado.log │ │ │ └── vhdl │ │ │ │ ├── Block_Mat_exit406734.vhd │ │ │ │ ├── Block_arrayctor_loop.vhd │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ ├── Loop_3_proc.vhd │ │ │ │ ├── Loop_loop_height_dEe.vhd │ │ │ │ ├── Loop_loop_height_pro.vhd │ │ │ │ ├── dilate_hls.vhd │ │ │ │ ├── dilate_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ ├── dilate_hls_mul_31hbi.vhd │ │ │ │ ├── dilate_hls_mul_32bkb.vhd │ │ │ │ ├── dilate_hls_mul_32cud.vhd │ │ │ │ ├── dilate_hls_mux_32g8j.vhd │ │ │ │ ├── fifo_w11_d1_A.vhd │ │ │ │ ├── fifo_w11_d2_A.vhd │ │ │ │ ├── fifo_w1_d2_A.vhd │ │ │ │ ├── fifo_w31_d3_A.vhd │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ └── fifo_w8_d1_A.vhd │ │ ├── script.tcl │ │ ├── solution1.aps │ │ ├── solution1.directive │ │ ├── solution1.log │ │ └── solution1_data.json │ └── vivado_hls.app ├── erode │ ├── .apc │ │ └── autopilot.apfmapping │ ├── .cproject │ ├── .project │ ├── .settings │ │ ├── erode.Debug.launch │ │ ├── erode.Release.launch │ │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── Morphology.png │ ├── erode_hls.cpp │ ├── erode_hls.h │ ├── erode_hls_test.cpp │ ├── lena_gray.bmp │ ├── solution1 │ │ ├── .temp11.log │ │ ├── directives.tcl │ │ ├── impl │ │ │ ├── ip │ │ │ │ ├── autoimpl.log │ │ │ │ ├── auxiliary.xml │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── constraints │ │ │ │ │ ├── erode_hls.xdc │ │ │ │ │ └── erode_hls_ooc.xdc │ │ │ │ ├── doc │ │ │ │ │ └── ReleaseNotes.txt │ │ │ │ ├── drivers │ │ │ │ │ └── erode_hls_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── erode_hls.mdd │ │ │ │ │ │ └── erode_hls.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xerode_hls.c │ │ │ │ │ │ ├── xerode_hls.h │ │ │ │ │ │ ├── xerode_hls_hw.h │ │ │ │ │ │ ├── xerode_hls_linux.c │ │ │ │ │ │ └── xerode_hls_sinit.c │ │ │ │ ├── erode_hls_info.xml │ │ │ │ ├── example │ │ │ │ │ ├── ipi_example.bat │ │ │ │ │ └── ipi_example.tcl │ │ │ │ ├── hdl │ │ │ │ │ ├── verilog │ │ │ │ │ │ ├── Block_Mat_exit406734_erode.v │ │ │ │ │ │ ├── Block_arrayctor_loop.v │ │ │ │ │ │ ├── Loop_1_proc_erode.v │ │ │ │ │ │ ├── Loop_3_proc_erode.v │ │ │ │ │ │ ├── Loop_loop_height_dEe.v │ │ │ │ │ │ ├── Loop_loop_height_pro_erode.v │ │ │ │ │ │ ├── erode_hls.v │ │ │ │ │ │ ├── erode_hls_CONTROL_BUS_s_axi.v │ │ │ │ │ │ ├── erode_hls_mul_31nhbi.v │ │ │ │ │ │ ├── erode_hls_mul_32sbkb.v │ │ │ │ │ │ ├── erode_hls_mul_32scud.v │ │ │ │ │ │ ├── erode_hls_mux_32_g8j.v │ │ │ │ │ │ ├── fifo_w11_d1_A.v │ │ │ │ │ │ ├── fifo_w11_d2_A.v │ │ │ │ │ │ ├── fifo_w1_d2_A.v │ │ │ │ │ │ ├── fifo_w31_d3_A.v │ │ │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ │ │ └── fifo_w8_d1_A.v │ │ │ │ │ └── vhdl │ │ │ │ │ │ ├── Block_Mat_exit406734.vhd │ │ │ │ │ │ ├── Block_arrayctor_loop.vhd │ │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ │ ├── Loop_3_proc.vhd │ │ │ │ │ │ ├── Loop_loop_height_dEe.vhd │ │ │ │ │ │ ├── Loop_loop_height_pro.vhd │ │ │ │ │ │ ├── erode_hls.vhd │ │ │ │ │ │ ├── erode_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ │ │ ├── erode_hls_mul_31nhbi.vhd │ │ │ │ │ │ ├── erode_hls_mul_32sbkb.vhd │ │ │ │ │ │ ├── erode_hls_mul_32scud.vhd │ │ │ │ │ │ ├── erode_hls_mux_32_g8j.vhd │ │ │ │ │ │ ├── fifo_w11_d1_A.vhd │ │ │ │ │ │ ├── fifo_w11_d2_A.vhd │ │ │ │ │ │ ├── fifo_w1_d2_A.vhd │ │ │ │ │ │ ├── fifo_w31_d3_A.vhd │ │ │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ │ │ └── fifo_w8_d1_A.vhd │ │ │ │ ├── misc │ │ │ │ │ └── logo.png │ │ │ │ ├── pack.bat │ │ │ │ ├── run_ippack.tcl │ │ │ │ ├── vivado.jou │ │ │ │ ├── vivado.log │ │ │ │ ├── xgui │ │ │ │ │ └── erode_hls_v1_0.tcl │ │ │ │ └── xilinx_com_hls_erode_hls_1_0.zip │ │ │ ├── misc │ │ │ │ ├── drivers │ │ │ │ │ └── erode_hls_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── erode_hls.mdd │ │ │ │ │ │ └── erode_hls.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xerode_hls.c │ │ │ │ │ │ ├── xerode_hls.h │ │ │ │ │ │ ├── xerode_hls_hw.h │ │ │ │ │ │ ├── xerode_hls_linux.c │ │ │ │ │ │ └── xerode_hls_sinit.c │ │ │ │ └── logo.png │ │ │ ├── report │ │ │ │ └── verilog │ │ │ │ │ ├── erode_hls_export.rpt │ │ │ │ │ └── erode_hls_export.xml │ │ │ ├── verilog │ │ │ │ ├── Block_Mat_exit406734_erode.v │ │ │ │ ├── Block_arrayctor_loop.v │ │ │ │ ├── Loop_1_proc_erode.v │ │ │ │ ├── Loop_3_proc_erode.v │ │ │ │ ├── Loop_loop_height_dEe.v │ │ │ │ ├── Loop_loop_height_pro_erode.v │ │ │ │ ├── autoimpl.log │ │ │ │ ├── erode_hls.result.rb │ │ │ │ ├── erode_hls.v │ │ │ │ ├── erode_hls.xdc │ │ │ │ ├── erode_hls_CONTROL_BUS_s_axi.v │ │ │ │ ├── erode_hls_mul_31nhbi.v │ │ │ │ ├── erode_hls_mul_32sbkb.v │ │ │ │ ├── erode_hls_mul_32scud.v │ │ │ │ ├── erode_hls_mux_32_g8j.v │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w11_d1_A.v │ │ │ │ ├── fifo_w11_d2_A.v │ │ │ │ ├── fifo_w1_d2_A.v │ │ │ │ ├── fifo_w31_d3_A.v │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ ├── impl.bat │ │ │ │ ├── project.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ ├── synthesis.wdf │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── project.hw │ │ │ │ │ └── project.lpr │ │ │ │ ├── project.runs │ │ │ │ │ ├── .jobs │ │ │ │ │ │ ├── vrs_config_1.xml │ │ │ │ │ │ └── vrs_config_2.xml │ │ │ │ │ ├── impl_1 │ │ │ │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ │ │ │ ├── .init_design.begin.rst │ │ │ │ │ │ ├── .init_design.end.rst │ │ │ │ │ │ ├── .opt_design.begin.rst │ │ │ │ │ │ ├── .opt_design.end.rst │ │ │ │ │ │ ├── .phys_opt_design.begin.rst │ │ │ │ │ │ ├── .phys_opt_design.end.rst │ │ │ │ │ │ ├── .place_design.begin.rst │ │ │ │ │ │ ├── .place_design.end.rst │ │ │ │ │ │ ├── .route_design.begin.rst │ │ │ │ │ │ ├── .route_design.end.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── erode_hls.dcp │ │ │ │ │ │ ├── erode_hls.tcl │ │ │ │ │ │ ├── erode_hls.vdi │ │ │ │ │ │ ├── erode_hls_clock_utilization_routed.rpt │ │ │ │ │ │ ├── erode_hls_control_sets_placed.rpt │ │ │ │ │ │ ├── erode_hls_drc_opted.pb │ │ │ │ │ │ ├── erode_hls_drc_opted.rpt │ │ │ │ │ │ ├── erode_hls_drc_opted.rpx │ │ │ │ │ │ ├── erode_hls_drc_routed.pb │ │ │ │ │ │ ├── erode_hls_drc_routed.rpt │ │ │ │ │ │ ├── erode_hls_drc_routed.rpx │ │ │ │ │ │ ├── erode_hls_io_placed.rpt │ │ │ │ │ │ ├── erode_hls_methodology_drc_routed.pb │ │ │ │ │ │ ├── erode_hls_methodology_drc_routed.rpt │ │ │ │ │ │ ├── erode_hls_methodology_drc_routed.rpx │ │ │ │ │ │ ├── erode_hls_opt.dcp │ │ │ │ │ │ ├── erode_hls_physopt.dcp │ │ │ │ │ │ ├── erode_hls_placed.dcp │ │ │ │ │ │ ├── erode_hls_power_routed.rpt │ │ │ │ │ │ ├── erode_hls_power_routed.rpx │ │ │ │ │ │ ├── erode_hls_power_summary_routed.pb │ │ │ │ │ │ ├── erode_hls_route_status.pb │ │ │ │ │ │ ├── erode_hls_route_status.rpt │ │ │ │ │ │ ├── erode_hls_routed.dcp │ │ │ │ │ │ ├── erode_hls_timing_summary_routed.rpt │ │ │ │ │ │ ├── erode_hls_timing_summary_routed.rpx │ │ │ │ │ │ ├── erode_hls_utilization_placed.pb │ │ │ │ │ │ ├── erode_hls_utilization_placed.rpt │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── init_design.pb │ │ │ │ │ │ ├── opt_design.pb │ │ │ │ │ │ ├── phys_opt_design.pb │ │ │ │ │ │ ├── place_design.pb │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── route_design.pb │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ │ └── synth_1 │ │ │ │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── erode_hls.dcp │ │ │ │ │ │ ├── erode_hls.tcl │ │ │ │ │ │ ├── erode_hls.vds │ │ │ │ │ │ ├── erode_hls_utilization_synth.pb │ │ │ │ │ │ ├── erode_hls_utilization_synth.rpt │ │ │ │ │ │ ├── fsm_encoding.os │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ ├── project.xpr │ │ │ │ ├── report │ │ │ │ │ ├── erode_hls_timing_routed.rpt │ │ │ │ │ ├── erode_hls_timing_synth.rpt │ │ │ │ │ ├── erode_hls_utilization_routed.rpt │ │ │ │ │ └── erode_hls_utilization_synth.rpt │ │ │ │ ├── run_vivado.tcl │ │ │ │ ├── settings.tcl │ │ │ │ ├── vivado.jou │ │ │ │ └── vivado.log │ │ │ └── vhdl │ │ │ │ ├── Block_Mat_exit406734.vhd │ │ │ │ ├── Block_arrayctor_loop.vhd │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ ├── Loop_3_proc.vhd │ │ │ │ ├── Loop_loop_height_dEe.vhd │ │ │ │ ├── Loop_loop_height_pro.vhd │ │ │ │ ├── erode_hls.vhd │ │ │ │ ├── erode_hls.xdc │ │ │ │ ├── erode_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ ├── erode_hls_mul_31nhbi.vhd │ │ │ │ ├── erode_hls_mul_32sbkb.vhd │ │ │ │ ├── erode_hls_mul_32scud.vhd │ │ │ │ ├── erode_hls_mux_32_g8j.vhd │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w11_d1_A.vhd │ │ │ │ ├── fifo_w11_d2_A.vhd │ │ │ │ ├── fifo_w1_d2_A.vhd │ │ │ │ ├── fifo_w31_d3_A.vhd │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ ├── impl.bat │ │ │ │ ├── project.cache │ │ │ │ └── wt │ │ │ │ │ └── project.wpc │ │ │ │ ├── project.hw │ │ │ │ └── project.lpr │ │ │ │ ├── project.xpr │ │ │ │ ├── run_vivado.tcl │ │ │ │ └── settings.tcl │ │ ├── script.tcl │ │ ├── solution1.aps │ │ ├── solution1.directive │ │ ├── solution1.log │ │ └── solution1_data.json │ └── vivado_hls.app ├── filter2D │ ├── .apc │ │ └── autopilot.apfmapping │ ├── .cproject │ ├── .project │ ├── .settings │ │ ├── filter2D.Debug.launch │ │ ├── filter2D.Release.launch │ │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── filter2D_hls.cpp │ ├── filter2D_hls.h │ ├── filter2D_hls_test.cpp │ ├── lena_gray.bmp │ ├── solution1 │ │ ├── directives.tcl │ │ ├── impl │ │ │ ├── ip │ │ │ │ ├── autoimpl.log │ │ │ │ ├── auxiliary.xml │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── constraints │ │ │ │ │ ├── filter2D_hls.xdc │ │ │ │ │ └── filter2D_hls_ooc.xdc │ │ │ │ ├── doc │ │ │ │ │ └── ReleaseNotes.txt │ │ │ │ ├── drivers │ │ │ │ │ └── filter2D_hls_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── filter2D_hls.mdd │ │ │ │ │ │ └── filter2D_hls.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xfilter2d_hls.c │ │ │ │ │ │ ├── xfilter2d_hls.h │ │ │ │ │ │ ├── xfilter2d_hls_hw.h │ │ │ │ │ │ ├── xfilter2d_hls_linux.c │ │ │ │ │ │ └── xfilter2d_hls_sinit.c │ │ │ │ ├── example │ │ │ │ │ ├── ipi_example.bat │ │ │ │ │ └── ipi_example.tcl │ │ │ │ ├── filter2D_hls_info.xml │ │ │ │ ├── hdl │ │ │ │ │ ├── verilog │ │ │ │ │ │ ├── Block_Mat_exit38794_s.v │ │ │ │ │ │ ├── Block_proc_filter2D.v │ │ │ │ │ │ ├── Filter2D_filter2D.v │ │ │ │ │ │ ├── Filter2D_k_buf_0_dEe.v │ │ │ │ │ │ ├── Loop_1_proc_filter2D.v │ │ │ │ │ │ ├── Loop_2_proc_filter2D.v │ │ │ │ │ │ ├── fifo_w31_d3_A.v │ │ │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ │ │ ├── fifo_w8_d2_A.v │ │ │ │ │ │ ├── filter2D_hls.v │ │ │ │ │ │ ├── filter2D_hls_CONTROL_BUS_s_axi.v │ │ │ │ │ │ ├── filter2D_hls_mac_hbi.v │ │ │ │ │ │ ├── filter2D_hls_mac_ibs.v │ │ │ │ │ │ ├── filter2D_hls_mul_bkb.v │ │ │ │ │ │ ├── filter2D_hls_mul_cud.v │ │ │ │ │ │ ├── filter2D_hls_mul_jbC.v │ │ │ │ │ │ └── filter2D_hls_mux_g8j.v │ │ │ │ │ └── vhdl │ │ │ │ │ │ ├── Block_Mat_exit38794_s.vhd │ │ │ │ │ │ ├── Block_proc.vhd │ │ │ │ │ │ ├── Filter2D.vhd │ │ │ │ │ │ ├── Filter2D_k_buf_0_dEe.vhd │ │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ │ │ ├── fifo_w31_d3_A.vhd │ │ │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ │ │ ├── fifo_w8_d2_A.vhd │ │ │ │ │ │ ├── filter2D_hls.vhd │ │ │ │ │ │ ├── filter2D_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ │ │ ├── filter2D_hls_mac_hbi.vhd │ │ │ │ │ │ ├── filter2D_hls_mac_ibs.vhd │ │ │ │ │ │ ├── filter2D_hls_mul_bkb.vhd │ │ │ │ │ │ ├── filter2D_hls_mul_cud.vhd │ │ │ │ │ │ ├── filter2D_hls_mul_jbC.vhd │ │ │ │ │ │ └── filter2D_hls_mux_g8j.vhd │ │ │ │ ├── misc │ │ │ │ │ └── logo.png │ │ │ │ ├── pack.bat │ │ │ │ ├── run_ippack.tcl │ │ │ │ ├── vivado.jou │ │ │ │ ├── vivado.log │ │ │ │ ├── xgui │ │ │ │ │ └── filter2D_hls_v1_0.tcl │ │ │ │ └── xilinx_com_hls_filter2D_hls_1_0.zip │ │ │ ├── misc │ │ │ │ ├── drivers │ │ │ │ │ └── filter2D_hls_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── filter2D_hls.mdd │ │ │ │ │ │ └── filter2D_hls.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xfilter2d_hls.c │ │ │ │ │ │ ├── xfilter2d_hls.h │ │ │ │ │ │ ├── xfilter2d_hls_hw.h │ │ │ │ │ │ ├── xfilter2d_hls_linux.c │ │ │ │ │ │ └── xfilter2d_hls_sinit.c │ │ │ │ └── logo.png │ │ │ ├── report │ │ │ │ └── verilog │ │ │ │ │ ├── filter2D_hls_export.rpt │ │ │ │ │ └── filter2D_hls_export.xml │ │ │ ├── verilog │ │ │ │ ├── Block_Mat_exit38794_s.v │ │ │ │ ├── Block_proc_filter2D.v │ │ │ │ ├── Filter2D_filter2D.v │ │ │ │ ├── Filter2D_k_buf_0_dEe.v │ │ │ │ ├── Loop_1_proc_filter2D.v │ │ │ │ ├── Loop_2_proc_filter2D.v │ │ │ │ ├── autoimpl.log │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w31_d3_A.v │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ ├── fifo_w8_d2_A.v │ │ │ │ ├── filter2D_hls.result.rb │ │ │ │ ├── filter2D_hls.v │ │ │ │ ├── filter2D_hls.xdc │ │ │ │ ├── filter2D_hls_CONTROL_BUS_s_axi.v │ │ │ │ ├── filter2D_hls_mac_hbi.v │ │ │ │ ├── filter2D_hls_mac_ibs.v │ │ │ │ ├── filter2D_hls_mul_bkb.v │ │ │ │ ├── filter2D_hls_mul_cud.v │ │ │ │ ├── filter2D_hls_mul_jbC.v │ │ │ │ ├── filter2D_hls_mux_g8j.v │ │ │ │ ├── impl.bat │ │ │ │ ├── project.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ ├── synthesis.wdf │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── project.hw │ │ │ │ │ └── project.lpr │ │ │ │ ├── project.runs │ │ │ │ │ ├── .jobs │ │ │ │ │ │ ├── vrs_config_1.xml │ │ │ │ │ │ └── vrs_config_2.xml │ │ │ │ │ ├── impl_1 │ │ │ │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ │ │ │ ├── .init_design.begin.rst │ │ │ │ │ │ ├── .init_design.end.rst │ │ │ │ │ │ ├── .opt_design.begin.rst │ │ │ │ │ │ ├── .opt_design.end.rst │ │ │ │ │ │ ├── .phys_opt_design.begin.rst │ │ │ │ │ │ ├── .phys_opt_design.end.rst │ │ │ │ │ │ ├── .place_design.begin.rst │ │ │ │ │ │ ├── .place_design.end.rst │ │ │ │ │ │ ├── .route_design.begin.rst │ │ │ │ │ │ ├── .route_design.end.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── filter2D_hls.dcp │ │ │ │ │ │ ├── filter2D_hls.tcl │ │ │ │ │ │ ├── filter2D_hls.vdi │ │ │ │ │ │ ├── filter2D_hls_clock_utilization_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_control_sets_placed.rpt │ │ │ │ │ │ ├── filter2D_hls_drc_opted.pb │ │ │ │ │ │ ├── filter2D_hls_drc_opted.rpt │ │ │ │ │ │ ├── filter2D_hls_drc_opted.rpx │ │ │ │ │ │ ├── filter2D_hls_drc_routed.pb │ │ │ │ │ │ ├── filter2D_hls_drc_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_drc_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_io_placed.rpt │ │ │ │ │ │ ├── filter2D_hls_methodology_drc_routed.pb │ │ │ │ │ │ ├── filter2D_hls_methodology_drc_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_methodology_drc_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_opt.dcp │ │ │ │ │ │ ├── filter2D_hls_physopt.dcp │ │ │ │ │ │ ├── filter2D_hls_placed.dcp │ │ │ │ │ │ ├── filter2D_hls_power_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_power_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_power_summary_routed.pb │ │ │ │ │ │ ├── filter2D_hls_route_status.pb │ │ │ │ │ │ ├── filter2D_hls_route_status.rpt │ │ │ │ │ │ ├── filter2D_hls_routed.dcp │ │ │ │ │ │ ├── filter2D_hls_timing_summary_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_timing_summary_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_utilization_placed.pb │ │ │ │ │ │ ├── filter2D_hls_utilization_placed.rpt │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── init_design.pb │ │ │ │ │ │ ├── opt_design.pb │ │ │ │ │ │ ├── phys_opt_design.pb │ │ │ │ │ │ ├── place_design.pb │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── route_design.pb │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ │ └── synth_1 │ │ │ │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── filter2D_hls.dcp │ │ │ │ │ │ ├── filter2D_hls.tcl │ │ │ │ │ │ ├── filter2D_hls.vds │ │ │ │ │ │ ├── filter2D_hls_utilization_synth.pb │ │ │ │ │ │ ├── filter2D_hls_utilization_synth.rpt │ │ │ │ │ │ ├── fsm_encoding.os │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ ├── project.xpr │ │ │ │ ├── report │ │ │ │ │ ├── filter2D_hls_timing_routed.rpt │ │ │ │ │ ├── filter2D_hls_timing_synth.rpt │ │ │ │ │ ├── filter2D_hls_utilization_routed.rpt │ │ │ │ │ └── filter2D_hls_utilization_synth.rpt │ │ │ │ ├── run_vivado.tcl │ │ │ │ ├── settings.tcl │ │ │ │ ├── vivado.jou │ │ │ │ └── vivado.log │ │ │ └── vhdl │ │ │ │ ├── Block_Mat_exit38794_s.vhd │ │ │ │ ├── Block_proc.vhd │ │ │ │ ├── Filter2D.vhd │ │ │ │ ├── Filter2D_k_buf_0_dEe.vhd │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w31_d3_A.vhd │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ ├── fifo_w8_d2_A.vhd │ │ │ │ ├── filter2D_hls.vhd │ │ │ │ ├── filter2D_hls.xdc │ │ │ │ ├── filter2D_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ ├── filter2D_hls_mac_hbi.vhd │ │ │ │ ├── filter2D_hls_mac_ibs.vhd │ │ │ │ ├── filter2D_hls_mul_bkb.vhd │ │ │ │ ├── filter2D_hls_mul_cud.vhd │ │ │ │ ├── filter2D_hls_mul_jbC.vhd │ │ │ │ ├── filter2D_hls_mux_g8j.vhd │ │ │ │ ├── impl.bat │ │ │ │ ├── project.cache │ │ │ │ └── wt │ │ │ │ │ └── project.wpc │ │ │ │ ├── project.hw │ │ │ │ └── project.lpr │ │ │ │ ├── project.xpr │ │ │ │ ├── run_vivado.tcl │ │ │ │ └── settings.tcl │ │ ├── script.tcl │ │ ├── solution1.aps │ │ ├── solution1.directive │ │ ├── solution1.log │ │ └── solution1_data.json │ └── vivado_hls.app ├── filter2D_5 │ ├── .apc │ │ └── autopilot.apfmapping │ ├── .cproject │ ├── .project │ ├── .settings │ │ ├── filter2D_5.Debug.launch │ │ ├── filter2D_5.Release.launch │ │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── filter2D_hls_5.cpp │ ├── filter2D_hls_5.h │ ├── filter2D_hls_5_test.cpp │ ├── lena_gray.bmp │ ├── solution1 │ │ ├── directives.tcl │ │ ├── impl │ │ │ ├── ip │ │ │ │ ├── autoimpl.log │ │ │ │ ├── auxiliary.xml │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── constraints │ │ │ │ │ ├── filter2D_hls_5.xdc │ │ │ │ │ └── filter2D_hls_5_ooc.xdc │ │ │ │ ├── doc │ │ │ │ │ └── ReleaseNotes.txt │ │ │ │ ├── drivers │ │ │ │ │ └── filter2D_hls_5_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── filter2D_hls_5.mdd │ │ │ │ │ │ └── filter2D_hls_5.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xfilter2d_hls_5.c │ │ │ │ │ │ ├── xfilter2d_hls_5.h │ │ │ │ │ │ ├── xfilter2d_hls_5_hw.h │ │ │ │ │ │ ├── xfilter2d_hls_5_linux.c │ │ │ │ │ │ └── xfilter2d_hls_5_sinit.c │ │ │ │ ├── example │ │ │ │ │ ├── ipi_example.bat │ │ │ │ │ └── ipi_example.tcl │ │ │ │ ├── filter2D_hls_5_info.xml │ │ │ │ ├── hdl │ │ │ │ │ ├── verilog │ │ │ │ │ │ ├── Block_Mat_exit212359.v │ │ │ │ │ │ ├── Block_proc.v │ │ │ │ │ │ ├── Filter2D.v │ │ │ │ │ │ ├── Filter2D_k_buf_0_cud.v │ │ │ │ │ │ ├── Loop_1_proc.v │ │ │ │ │ │ ├── Loop_2_proc.v │ │ │ │ │ │ ├── fifo_w20_d2_A.v │ │ │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ │ │ ├── fifo_w8_d2_A.v │ │ │ │ │ │ ├── fifo_w9_d3_A.v │ │ │ │ │ │ ├── filter2D_hls_5.v │ │ │ │ │ │ ├── filter2D_hls_5_CONTROL_BUS_s_axi.v │ │ │ │ │ │ ├── filter2D_hls_5_maibs.v │ │ │ │ │ │ ├── filter2D_hls_5_majbC.v │ │ │ │ │ │ ├── filter2D_hls_5_makbM.v │ │ │ │ │ │ ├── filter2D_hls_5_mubkb.v │ │ │ │ │ │ ├── filter2D_hls_5_muhbi.v │ │ │ │ │ │ └── filter2D_hls_5_mulbW.v │ │ │ │ │ └── vhdl │ │ │ │ │ │ ├── Block_Mat_exit212359.vhd │ │ │ │ │ │ ├── Block_proc.vhd │ │ │ │ │ │ ├── Filter2D.vhd │ │ │ │ │ │ ├── Filter2D_k_buf_0_cud.vhd │ │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ │ │ ├── fifo_w8_d2_A.vhd │ │ │ │ │ │ ├── fifo_w9_d3_A.vhd │ │ │ │ │ │ ├── filter2D_hls_5.vhd │ │ │ │ │ │ ├── filter2D_hls_5_CONTROL_BUS_s_axi.vhd │ │ │ │ │ │ ├── filter2D_hls_5_maibs.vhd │ │ │ │ │ │ ├── filter2D_hls_5_majbC.vhd │ │ │ │ │ │ ├── filter2D_hls_5_makbM.vhd │ │ │ │ │ │ ├── filter2D_hls_5_mubkb.vhd │ │ │ │ │ │ ├── filter2D_hls_5_muhbi.vhd │ │ │ │ │ │ └── filter2D_hls_5_mulbW.vhd │ │ │ │ ├── misc │ │ │ │ │ └── logo.png │ │ │ │ ├── pack.bat │ │ │ │ ├── run_ippack.tcl │ │ │ │ ├── vivado.jou │ │ │ │ ├── vivado.log │ │ │ │ ├── xgui │ │ │ │ │ └── filter2D_hls_5_v1_0.tcl │ │ │ │ └── xilinx_com_hls_filter2D_hls_5_1_0.zip │ │ │ ├── misc │ │ │ │ ├── drivers │ │ │ │ │ └── filter2D_hls_5_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── filter2D_hls_5.mdd │ │ │ │ │ │ └── filter2D_hls_5.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xfilter2d_hls_5.c │ │ │ │ │ │ ├── xfilter2d_hls_5.h │ │ │ │ │ │ ├── xfilter2d_hls_5_hw.h │ │ │ │ │ │ ├── xfilter2d_hls_5_linux.c │ │ │ │ │ │ └── xfilter2d_hls_5_sinit.c │ │ │ │ └── logo.png │ │ │ ├── report │ │ │ │ └── verilog │ │ │ │ │ ├── filter2D_hls_5_export.rpt │ │ │ │ │ └── filter2D_hls_5_export.xml │ │ │ ├── verilog │ │ │ │ ├── Block_Mat_exit212359.v │ │ │ │ ├── Block_proc.v │ │ │ │ ├── Filter2D.v │ │ │ │ ├── Filter2D_k_buf_0_cud.v │ │ │ │ ├── Loop_1_proc.v │ │ │ │ ├── Loop_2_proc.v │ │ │ │ ├── autoimpl.log │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w20_d2_A.v │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ ├── fifo_w8_d2_A.v │ │ │ │ ├── fifo_w9_d3_A.v │ │ │ │ ├── filter2D_hls_5.result.rb │ │ │ │ ├── filter2D_hls_5.v │ │ │ │ ├── filter2D_hls_5.xdc │ │ │ │ ├── filter2D_hls_5_CONTROL_BUS_s_axi.v │ │ │ │ ├── filter2D_hls_5_maibs.v │ │ │ │ ├── filter2D_hls_5_majbC.v │ │ │ │ ├── filter2D_hls_5_makbM.v │ │ │ │ ├── filter2D_hls_5_mubkb.v │ │ │ │ ├── filter2D_hls_5_muhbi.v │ │ │ │ ├── filter2D_hls_5_mulbW.v │ │ │ │ ├── impl.bat │ │ │ │ ├── project.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ ├── synthesis.wdf │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── project.hw │ │ │ │ │ └── project.lpr │ │ │ │ ├── project.runs │ │ │ │ │ ├── .jobs │ │ │ │ │ │ ├── vrs_config_1.xml │ │ │ │ │ │ └── vrs_config_2.xml │ │ │ │ │ ├── impl_1 │ │ │ │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ │ │ │ ├── .init_design.begin.rst │ │ │ │ │ │ ├── .init_design.end.rst │ │ │ │ │ │ ├── .opt_design.begin.rst │ │ │ │ │ │ ├── .opt_design.end.rst │ │ │ │ │ │ ├── .phys_opt_design.begin.rst │ │ │ │ │ │ ├── .phys_opt_design.end.rst │ │ │ │ │ │ ├── .place_design.begin.rst │ │ │ │ │ │ ├── .place_design.end.rst │ │ │ │ │ │ ├── .route_design.begin.rst │ │ │ │ │ │ ├── .route_design.end.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── filter2D_hls_5.dcp │ │ │ │ │ │ ├── filter2D_hls_5.tcl │ │ │ │ │ │ ├── filter2D_hls_5.vdi │ │ │ │ │ │ ├── filter2D_hls_5_clock_utilization_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_5_control_sets_placed.rpt │ │ │ │ │ │ ├── filter2D_hls_5_drc_opted.pb │ │ │ │ │ │ ├── filter2D_hls_5_drc_opted.rpt │ │ │ │ │ │ ├── filter2D_hls_5_drc_opted.rpx │ │ │ │ │ │ ├── filter2D_hls_5_drc_routed.pb │ │ │ │ │ │ ├── filter2D_hls_5_drc_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_5_drc_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_5_io_placed.rpt │ │ │ │ │ │ ├── filter2D_hls_5_methodology_drc_routed.pb │ │ │ │ │ │ ├── filter2D_hls_5_methodology_drc_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_5_methodology_drc_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_5_opt.dcp │ │ │ │ │ │ ├── filter2D_hls_5_physopt.dcp │ │ │ │ │ │ ├── filter2D_hls_5_placed.dcp │ │ │ │ │ │ ├── filter2D_hls_5_power_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_5_power_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_5_power_summary_routed.pb │ │ │ │ │ │ ├── filter2D_hls_5_route_status.pb │ │ │ │ │ │ ├── filter2D_hls_5_route_status.rpt │ │ │ │ │ │ ├── filter2D_hls_5_routed.dcp │ │ │ │ │ │ ├── filter2D_hls_5_timing_summary_routed.rpt │ │ │ │ │ │ ├── filter2D_hls_5_timing_summary_routed.rpx │ │ │ │ │ │ ├── filter2D_hls_5_utilization_placed.pb │ │ │ │ │ │ ├── filter2D_hls_5_utilization_placed.rpt │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── init_design.pb │ │ │ │ │ │ ├── opt_design.pb │ │ │ │ │ │ ├── phys_opt_design.pb │ │ │ │ │ │ ├── place_design.pb │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── route_design.pb │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ │ └── synth_1 │ │ │ │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── filter2D_hls_5.dcp │ │ │ │ │ │ ├── filter2D_hls_5.tcl │ │ │ │ │ │ ├── filter2D_hls_5.vds │ │ │ │ │ │ ├── filter2D_hls_5_utilization_synth.pb │ │ │ │ │ │ ├── filter2D_hls_5_utilization_synth.rpt │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ ├── project.xpr │ │ │ │ ├── report │ │ │ │ │ ├── filter2D_hls_5_timing_routed.rpt │ │ │ │ │ ├── filter2D_hls_5_timing_synth.rpt │ │ │ │ │ ├── filter2D_hls_5_utilization_routed.rpt │ │ │ │ │ └── filter2D_hls_5_utilization_synth.rpt │ │ │ │ ├── run_vivado.tcl │ │ │ │ ├── settings.tcl │ │ │ │ ├── vivado.jou │ │ │ │ └── vivado.log │ │ │ └── vhdl │ │ │ │ ├── Block_Mat_exit212359.vhd │ │ │ │ ├── Block_proc.vhd │ │ │ │ ├── Filter2D.vhd │ │ │ │ ├── Filter2D_k_buf_0_cud.vhd │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ ├── fifo_w8_d2_A.vhd │ │ │ │ ├── fifo_w9_d3_A.vhd │ │ │ │ ├── filter2D_hls_5.vhd │ │ │ │ ├── filter2D_hls_5_CONTROL_BUS_s_axi.vhd │ │ │ │ ├── filter2D_hls_5_maibs.vhd │ │ │ │ ├── filter2D_hls_5_majbC.vhd │ │ │ │ ├── filter2D_hls_5_makbM.vhd │ │ │ │ ├── filter2D_hls_5_mubkb.vhd │ │ │ │ ├── filter2D_hls_5_muhbi.vhd │ │ │ │ └── filter2D_hls_5_mulbW.vhd │ │ ├── script.tcl │ │ ├── solution1.aps │ │ ├── solution1.directive │ │ ├── solution1.log │ │ └── solution1_data.json │ └── vivado_hls.app ├── filter2D_f │ ├── .apc │ │ └── autopilot.apfmapping │ ├── .cproject │ ├── .project │ ├── .settings │ │ ├── filter2D_f.Debug.launch │ │ ├── filter2D_f.Release.launch │ │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── filter2D_f.cpp │ ├── filter2D_f.h │ ├── filter2D_f_test.cpp │ ├── lena_gray.bmp │ ├── solution1 │ │ ├── directives.tcl │ │ ├── impl │ │ │ ├── ip │ │ │ │ ├── autoimpl.log │ │ │ │ ├── auxiliary.xml │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── constraints │ │ │ │ │ ├── filter2D_f.xdc │ │ │ │ │ └── filter2D_f_ooc.xdc │ │ │ │ ├── doc │ │ │ │ │ └── ReleaseNotes.txt │ │ │ │ ├── drivers │ │ │ │ │ └── filter2D_f_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── filter2D_f.mdd │ │ │ │ │ │ └── filter2D_f.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xfilter2d_f.c │ │ │ │ │ │ ├── xfilter2d_f.h │ │ │ │ │ │ ├── xfilter2d_f_hw.h │ │ │ │ │ │ ├── xfilter2d_f_linux.c │ │ │ │ │ │ └── xfilter2d_f_sinit.c │ │ │ │ ├── example │ │ │ │ │ ├── ipi_example.bat │ │ │ │ │ └── ipi_example.tcl │ │ │ │ ├── filter2D_f_info.xml │ │ │ │ ├── hdl │ │ │ │ │ ├── verilog │ │ │ │ │ │ ├── Block_Mat_exit65294_s.v │ │ │ │ │ │ ├── Block_proc_filter2D_f.v │ │ │ │ │ │ ├── Filter2D_filter2D_f.v │ │ │ │ │ │ ├── Filter2D_k_buf_0_dEe.v │ │ │ │ │ │ ├── Loop_1_proc_filter2D_f.v │ │ │ │ │ │ ├── Loop_2_proc_filter2D_f.v │ │ │ │ │ │ ├── fifo_w25_d2_A.v │ │ │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ │ │ ├── fifo_w32_d3_A.v │ │ │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ │ │ ├── filter2D_f.v │ │ │ │ │ │ ├── filter2D_f_CONTROL_BUS_s_axi.v │ │ │ │ │ │ ├── filter2D_f_mac_muibs.v │ │ │ │ │ │ ├── filter2D_f_mac_mujbC.v │ │ │ │ │ │ ├── filter2D_f_mac_mukbM.v │ │ │ │ │ │ ├── filter2D_f_mac_mulbW.v │ │ │ │ │ │ ├── filter2D_f_mul_32bkb.v │ │ │ │ │ │ ├── filter2D_f_mul_32cud.v │ │ │ │ │ │ ├── filter2D_f_mul_32mb6.v │ │ │ │ │ │ ├── filter2D_f_mul_muhbi.v │ │ │ │ │ │ └── filter2D_f_mux_32g8j.v │ │ │ │ │ └── vhdl │ │ │ │ │ │ ├── Block_Mat_exit65294_s.vhd │ │ │ │ │ │ ├── Block_proc.vhd │ │ │ │ │ │ ├── Filter2D.vhd │ │ │ │ │ │ ├── Filter2D_k_buf_0_dEe.vhd │ │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ │ │ ├── fifo_w25_d2_A.vhd │ │ │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ │ │ ├── fifo_w32_d3_A.vhd │ │ │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ │ │ ├── filter2D_f.vhd │ │ │ │ │ │ ├── filter2D_f_CONTROL_BUS_s_axi.vhd │ │ │ │ │ │ ├── filter2D_f_mac_muibs.vhd │ │ │ │ │ │ ├── filter2D_f_mac_mujbC.vhd │ │ │ │ │ │ ├── filter2D_f_mac_mukbM.vhd │ │ │ │ │ │ ├── filter2D_f_mac_mulbW.vhd │ │ │ │ │ │ ├── filter2D_f_mul_32bkb.vhd │ │ │ │ │ │ ├── filter2D_f_mul_32cud.vhd │ │ │ │ │ │ ├── filter2D_f_mul_32mb6.vhd │ │ │ │ │ │ ├── filter2D_f_mul_muhbi.vhd │ │ │ │ │ │ └── filter2D_f_mux_32g8j.vhd │ │ │ │ ├── misc │ │ │ │ │ └── logo.png │ │ │ │ ├── pack.bat │ │ │ │ ├── run_ippack.tcl │ │ │ │ ├── vivado.jou │ │ │ │ ├── vivado.log │ │ │ │ ├── xgui │ │ │ │ │ └── filter2D_f_v1_0.tcl │ │ │ │ └── xilinx_com_hls_filter2D_f_1_0.zip │ │ │ ├── misc │ │ │ │ ├── drivers │ │ │ │ │ └── filter2D_f_v1_0 │ │ │ │ │ │ ├── data │ │ │ │ │ │ ├── filter2D_f.mdd │ │ │ │ │ │ └── filter2D_f.tcl │ │ │ │ │ │ └── src │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ ├── xfilter2d_f.c │ │ │ │ │ │ ├── xfilter2d_f.h │ │ │ │ │ │ ├── xfilter2d_f_hw.h │ │ │ │ │ │ ├── xfilter2d_f_linux.c │ │ │ │ │ │ └── xfilter2d_f_sinit.c │ │ │ │ └── logo.png │ │ │ ├── report │ │ │ │ └── verilog │ │ │ │ │ ├── filter2D_f_export.rpt │ │ │ │ │ └── filter2D_f_export.xml │ │ │ ├── verilog │ │ │ │ ├── Block_Mat_exit65294_s.v │ │ │ │ ├── Block_proc_filter2D_f.v │ │ │ │ ├── Filter2D_filter2D_f.v │ │ │ │ ├── Filter2D_k_buf_0_dEe.v │ │ │ │ ├── Loop_1_proc_filter2D_f.v │ │ │ │ ├── Loop_2_proc_filter2D_f.v │ │ │ │ ├── autoimpl.log │ │ │ │ ├── extraction.tcl │ │ │ │ ├── fifo_w25_d2_A.v │ │ │ │ ├── fifo_w32_d2_A.v │ │ │ │ ├── fifo_w32_d3_A.v │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ ├── filter2D_f.result.rb │ │ │ │ ├── filter2D_f.v │ │ │ │ ├── filter2D_f.xdc │ │ │ │ ├── filter2D_f_CONTROL_BUS_s_axi.v │ │ │ │ ├── filter2D_f_mac_muibs.v │ │ │ │ ├── filter2D_f_mac_mujbC.v │ │ │ │ ├── filter2D_f_mac_mukbM.v │ │ │ │ ├── filter2D_f_mac_mulbW.v │ │ │ │ ├── filter2D_f_mul_32bkb.v │ │ │ │ ├── filter2D_f_mul_32cud.v │ │ │ │ ├── filter2D_f_mul_32mb6.v │ │ │ │ ├── filter2D_f_mul_muhbi.v │ │ │ │ ├── filter2D_f_mux_32g8j.v │ │ │ │ ├── impl.bat │ │ │ │ ├── project.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ ├── synthesis.wdf │ │ │ │ │ │ └── webtalk_pa.xml │ │ │ │ ├── project.hw │ │ │ │ │ └── project.lpr │ │ │ │ ├── project.runs │ │ │ │ │ ├── .jobs │ │ │ │ │ │ ├── vrs_config_1.xml │ │ │ │ │ │ └── vrs_config_2.xml │ │ │ │ │ ├── impl_1 │ │ │ │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ │ │ │ ├── .init_design.begin.rst │ │ │ │ │ │ ├── .init_design.end.rst │ │ │ │ │ │ ├── .opt_design.begin.rst │ │ │ │ │ │ ├── .opt_design.end.rst │ │ │ │ │ │ ├── .phys_opt_design.begin.rst │ │ │ │ │ │ ├── .phys_opt_design.end.rst │ │ │ │ │ │ ├── .place_design.begin.rst │ │ │ │ │ │ ├── .place_design.end.rst │ │ │ │ │ │ ├── .route_design.begin.rst │ │ │ │ │ │ ├── .route_design.end.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── filter2D_f.dcp │ │ │ │ │ │ ├── filter2D_f.tcl │ │ │ │ │ │ ├── filter2D_f.vdi │ │ │ │ │ │ ├── filter2D_f_clock_utilization_routed.rpt │ │ │ │ │ │ ├── filter2D_f_control_sets_placed.rpt │ │ │ │ │ │ ├── filter2D_f_drc_opted.pb │ │ │ │ │ │ ├── filter2D_f_drc_opted.rpt │ │ │ │ │ │ ├── filter2D_f_drc_opted.rpx │ │ │ │ │ │ ├── filter2D_f_drc_routed.pb │ │ │ │ │ │ ├── filter2D_f_drc_routed.rpt │ │ │ │ │ │ ├── filter2D_f_drc_routed.rpx │ │ │ │ │ │ ├── filter2D_f_io_placed.rpt │ │ │ │ │ │ ├── filter2D_f_methodology_drc_routed.pb │ │ │ │ │ │ ├── filter2D_f_methodology_drc_routed.rpt │ │ │ │ │ │ ├── filter2D_f_methodology_drc_routed.rpx │ │ │ │ │ │ ├── filter2D_f_opt.dcp │ │ │ │ │ │ ├── filter2D_f_physopt.dcp │ │ │ │ │ │ ├── filter2D_f_placed.dcp │ │ │ │ │ │ ├── filter2D_f_power_routed.rpt │ │ │ │ │ │ ├── filter2D_f_power_routed.rpx │ │ │ │ │ │ ├── filter2D_f_power_summary_routed.pb │ │ │ │ │ │ ├── filter2D_f_route_status.pb │ │ │ │ │ │ ├── filter2D_f_route_status.rpt │ │ │ │ │ │ ├── filter2D_f_routed.dcp │ │ │ │ │ │ ├── filter2D_f_timing_summary_routed.rpt │ │ │ │ │ │ ├── filter2D_f_timing_summary_routed.rpx │ │ │ │ │ │ ├── filter2D_f_utilization_placed.pb │ │ │ │ │ │ ├── filter2D_f_utilization_placed.rpt │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── init_design.pb │ │ │ │ │ │ ├── opt_design.pb │ │ │ │ │ │ ├── phys_opt_design.pb │ │ │ │ │ │ ├── place_design.pb │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── route_design.pb │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ │ └── synth_1 │ │ │ │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ │ │ │ ├── .vivado.begin.rst │ │ │ │ │ │ ├── .vivado.end.rst │ │ │ │ │ │ ├── ISEWrap.js │ │ │ │ │ │ ├── ISEWrap.sh │ │ │ │ │ │ ├── filter2D_f.dcp │ │ │ │ │ │ ├── filter2D_f.tcl │ │ │ │ │ │ ├── filter2D_f.vds │ │ │ │ │ │ ├── filter2D_f_utilization_synth.pb │ │ │ │ │ │ ├── filter2D_f_utilization_synth.rpt │ │ │ │ │ │ ├── fsm_encoding.os │ │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ │ ├── htr.txt │ │ │ │ │ │ ├── project.wdf │ │ │ │ │ │ ├── rundef.js │ │ │ │ │ │ ├── runme.bat │ │ │ │ │ │ ├── runme.log │ │ │ │ │ │ ├── runme.sh │ │ │ │ │ │ ├── vivado.jou │ │ │ │ │ │ └── vivado.pb │ │ │ │ ├── project.xpr │ │ │ │ ├── report │ │ │ │ │ ├── filter2D_f_timing_routed.rpt │ │ │ │ │ ├── filter2D_f_timing_synth.rpt │ │ │ │ │ ├── filter2D_f_utilization_routed.rpt │ │ │ │ │ └── filter2D_f_utilization_synth.rpt │ │ │ │ ├── run_vivado.tcl │ │ │ │ ├── settings.tcl │ │ │ │ ├── vivado.jou │ │ │ │ └── vivado.log │ │ │ └── vhdl │ │ │ │ ├── Block_Mat_exit65294_s.vhd │ │ │ │ ├── Block_proc.vhd │ │ │ │ ├── Filter2D.vhd │ │ │ │ ├── Filter2D_k_buf_0_dEe.vhd │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ ├── fifo_w25_d2_A.vhd │ │ │ │ ├── fifo_w32_d2_A.vhd │ │ │ │ ├── fifo_w32_d3_A.vhd │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ ├── filter2D_f.vhd │ │ │ │ ├── filter2D_f_CONTROL_BUS_s_axi.vhd │ │ │ │ ├── filter2D_f_mac_muibs.vhd │ │ │ │ ├── filter2D_f_mac_mujbC.vhd │ │ │ │ ├── filter2D_f_mac_mukbM.vhd │ │ │ │ ├── filter2D_f_mac_mulbW.vhd │ │ │ │ ├── filter2D_f_mul_32bkb.vhd │ │ │ │ ├── filter2D_f_mul_32cud.vhd │ │ │ │ ├── filter2D_f_mul_32mb6.vhd │ │ │ │ ├── filter2D_f_mul_muhbi.vhd │ │ │ │ └── filter2D_f_mux_32g8j.vhd │ │ ├── script.tcl │ │ ├── solution1.aps │ │ ├── solution1.directive │ │ ├── solution1.log │ │ └── solution1_data.json │ └── vivado_hls.app ├── makeHLScodeUnique.py ├── move │ ├── .settings │ │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── lena_gray.bmp │ ├── move.h │ └── solution1 │ │ ├── directives.tcl │ │ ├── impl │ │ ├── ip │ │ │ ├── auxiliary.xml │ │ │ ├── bd │ │ │ │ └── bd.tcl │ │ │ ├── component.xml │ │ │ ├── constraints │ │ │ │ ├── move_hls.xdc │ │ │ │ └── move_hls_ooc.xdc │ │ │ ├── doc │ │ │ │ └── ReleaseNotes.txt │ │ │ ├── drivers │ │ │ │ └── move_hls_v1_0 │ │ │ │ │ ├── data │ │ │ │ │ └── move_hls.tcl │ │ │ │ │ └── src │ │ │ │ │ ├── xmove_hls.c │ │ │ │ │ ├── xmove_hls.h │ │ │ │ │ ├── xmove_hls_hw.h │ │ │ │ │ ├── xmove_hls_linux.c │ │ │ │ │ └── xmove_hls_sinit.c │ │ │ ├── example │ │ │ │ └── ipi_example.tcl │ │ │ ├── hdl │ │ │ │ ├── verilog │ │ │ │ │ ├── Block_Mat_exit16542_s.v │ │ │ │ │ ├── Loop_1_proc_move.v │ │ │ │ │ ├── Loop_2_proc18.v │ │ │ │ │ ├── Loop_3_proc_move.v │ │ │ │ │ ├── fifo_w20_d2_A.v │ │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ │ ├── fifo_w9_d3_A.v │ │ │ │ │ ├── move_hls.v │ │ │ │ │ ├── move_hls_CONTROL_BUS_s_axi.v │ │ │ │ │ ├── move_hls_mul_32s_cud.v │ │ │ │ │ ├── move_hls_mul_mul_bkb.v │ │ │ │ │ └── move_hls_mul_mul_dEe.v │ │ │ │ └── vhdl │ │ │ │ │ ├── Block_Mat_exit16542_s.vhd │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ ├── Loop_2_proc18.vhd │ │ │ │ │ ├── Loop_3_proc.vhd │ │ │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ │ ├── fifo_w9_d3_A.vhd │ │ │ │ │ ├── move_hls.vhd │ │ │ │ │ ├── move_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ │ ├── move_hls_mul_32s_cud.vhd │ │ │ │ │ ├── move_hls_mul_mul_bkb.vhd │ │ │ │ │ └── move_hls_mul_mul_dEe.vhd │ │ │ ├── move_hls_info.xml │ │ │ ├── run_ippack.tcl │ │ │ ├── vivado.jou │ │ │ └── xgui │ │ │ │ └── move_hls_v1_0.tcl │ │ ├── misc │ │ │ └── drivers │ │ │ │ └── move_hls_v1_0 │ │ │ │ ├── data │ │ │ │ └── move_hls.tcl │ │ │ │ └── src │ │ │ │ ├── xmove_hls.c │ │ │ │ ├── xmove_hls.h │ │ │ │ ├── xmove_hls_hw.h │ │ │ │ ├── xmove_hls_linux.c │ │ │ │ └── xmove_hls_sinit.c │ │ ├── report │ │ │ └── verilog │ │ │ │ ├── move_hls_export.rpt │ │ │ │ └── move_hls_export.xml │ │ ├── verilog │ │ │ ├── Block_Mat_exit16542_s.v │ │ │ ├── Loop_1_proc_move.v │ │ │ ├── Loop_2_proc18.v │ │ │ ├── Loop_3_proc_move.v │ │ │ ├── extraction.tcl │ │ │ ├── fifo_w20_d2_A.v │ │ │ ├── fifo_w8_d1_A.v │ │ │ ├── fifo_w9_d3_A.v │ │ │ ├── move_hls.v │ │ │ ├── move_hls.xdc │ │ │ ├── move_hls_CONTROL_BUS_s_axi.v │ │ │ ├── move_hls_mul_32s_cud.v │ │ │ ├── move_hls_mul_mul_bkb.v │ │ │ ├── move_hls_mul_mul_dEe.v │ │ │ ├── project.runs │ │ │ │ ├── .jobs │ │ │ │ │ └── vrs_config_1.xml │ │ │ │ └── synth_1 │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ ├── htr.txt │ │ │ │ │ ├── move_hls.dcp │ │ │ │ │ ├── move_hls.tcl │ │ │ │ │ ├── move_hls.vds │ │ │ │ │ ├── move_hls_utilization_synth.pb │ │ │ │ │ ├── move_hls_utilization_synth.rpt │ │ │ │ │ ├── vivado.jou │ │ │ │ │ └── vivado.pb │ │ │ ├── project.xpr │ │ │ ├── report │ │ │ │ ├── move_hls_timing_synth.rpt │ │ │ │ └── move_hls_utilization_synth.rpt │ │ │ ├── run_vivado.tcl │ │ │ ├── settings.tcl │ │ │ └── vivado.jou │ │ └── vhdl │ │ │ ├── Block_Mat_exit16542_s.vhd │ │ │ ├── Loop_1_proc.vhd │ │ │ ├── Loop_2_proc18.vhd │ │ │ ├── Loop_3_proc.vhd │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ ├── fifo_w9_d3_A.vhd │ │ │ ├── move_hls.vhd │ │ │ ├── move_hls_CONTROL_BUS_s_axi.vhd │ │ │ ├── move_hls_mul_32s_cud.vhd │ │ │ ├── move_hls_mul_mul_bkb.vhd │ │ │ └── move_hls_mul_mul_dEe.vhd │ │ └── script.tcl └── threshold │ ├── .settings │ └── language.settings.xml │ ├── .vivado_hls_log_all.xml │ ├── lena_gray.bmp │ ├── solution1 │ ├── directives.tcl │ ├── impl │ │ ├── ip │ │ │ ├── auxiliary.xml │ │ │ ├── bd │ │ │ │ └── bd.tcl │ │ │ ├── component.xml │ │ │ ├── constraints │ │ │ │ ├── threshold_hls.xdc │ │ │ │ └── threshold_hls_ooc.xdc │ │ │ ├── doc │ │ │ │ └── ReleaseNotes.txt │ │ │ ├── drivers │ │ │ │ └── threshold_hls_v1_0 │ │ │ │ │ ├── data │ │ │ │ │ └── threshold_hls.tcl │ │ │ │ │ └── src │ │ │ │ │ ├── xthreshold_hls.c │ │ │ │ │ ├── xthreshold_hls.h │ │ │ │ │ ├── xthreshold_hls_hw.h │ │ │ │ │ ├── xthreshold_hls_linux.c │ │ │ │ │ └── xthreshold_hls_sinit.c │ │ │ ├── example │ │ │ │ └── ipi_example.tcl │ │ │ ├── hdl │ │ │ │ ├── verilog │ │ │ │ │ ├── Block_Mat_exit16134_s.v │ │ │ │ │ ├── Loop_1_proc_threshold.v │ │ │ │ │ ├── Loop_2_proc_threshold.v │ │ │ │ │ ├── Threshold.v │ │ │ │ │ ├── fifo_w20_d2_A.v │ │ │ │ │ ├── fifo_w8_d1_A.v │ │ │ │ │ ├── fifo_w9_d3_A.v │ │ │ │ │ ├── threshold_hls.v │ │ │ │ │ ├── threshold_hls_CONTROL_BUS_s_axi.v │ │ │ │ │ ├── threshold_hls_mulbkb.v │ │ │ │ │ └── threshold_hls_mulcud.v │ │ │ │ └── vhdl │ │ │ │ │ ├── Block_Mat_exit16134_s.vhd │ │ │ │ │ ├── Loop_1_proc.vhd │ │ │ │ │ ├── Loop_2_proc.vhd │ │ │ │ │ ├── Threshold.vhd │ │ │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ │ │ ├── fifo_w9_d3_A.vhd │ │ │ │ │ ├── threshold_hls.vhd │ │ │ │ │ ├── threshold_hls_CONTROL_BUS_s_axi.vhd │ │ │ │ │ ├── threshold_hls_mulbkb.vhd │ │ │ │ │ └── threshold_hls_mulcud.vhd │ │ │ ├── run_ippack.tcl │ │ │ ├── threshold_hls_info.xml │ │ │ ├── vivado.jou │ │ │ └── xgui │ │ │ │ └── threshold_hls_v1_0.tcl │ │ ├── misc │ │ │ └── drivers │ │ │ │ └── threshold_hls_v1_0 │ │ │ │ ├── data │ │ │ │ └── threshold_hls.tcl │ │ │ │ └── src │ │ │ │ ├── xthreshold_hls.c │ │ │ │ ├── xthreshold_hls.h │ │ │ │ ├── xthreshold_hls_hw.h │ │ │ │ ├── xthreshold_hls_linux.c │ │ │ │ └── xthreshold_hls_sinit.c │ │ ├── report │ │ │ └── verilog │ │ │ │ ├── threshold_hls_export.rpt │ │ │ │ └── threshold_hls_export.xml │ │ ├── verilog │ │ │ ├── Block_Mat_exit16134_s.v │ │ │ ├── Loop_1_proc_threshold.v │ │ │ ├── Loop_2_proc_threshold.v │ │ │ ├── Threshold.v │ │ │ ├── extraction.tcl │ │ │ ├── fifo_w20_d2_A.v │ │ │ ├── fifo_w8_d1_A.v │ │ │ ├── fifo_w9_d3_A.v │ │ │ ├── project.runs │ │ │ │ ├── .jobs │ │ │ │ │ └── vrs_config_1.xml │ │ │ │ └── synth_1 │ │ │ │ │ ├── gen_run.xml │ │ │ │ │ ├── htr.txt │ │ │ │ │ ├── threshold_hls.dcp │ │ │ │ │ ├── threshold_hls.tcl │ │ │ │ │ ├── threshold_hls.vds │ │ │ │ │ ├── threshold_hls_utilization_synth.pb │ │ │ │ │ ├── threshold_hls_utilization_synth.rpt │ │ │ │ │ ├── vivado.jou │ │ │ │ │ └── vivado.pb │ │ │ ├── project.xpr │ │ │ ├── report │ │ │ │ ├── threshold_hls_timing_synth.rpt │ │ │ │ └── threshold_hls_utilization_synth.rpt │ │ │ ├── run_vivado.tcl │ │ │ ├── settings.tcl │ │ │ ├── threshold_hls.v │ │ │ ├── threshold_hls.xdc │ │ │ ├── threshold_hls_CONTROL_BUS_s_axi.v │ │ │ ├── threshold_hls_mulbkb.v │ │ │ ├── threshold_hls_mulcud.v │ │ │ └── vivado.jou │ │ └── vhdl │ │ │ ├── Block_Mat_exit16134_s.vhd │ │ │ ├── Loop_1_proc.vhd │ │ │ ├── Loop_2_proc.vhd │ │ │ ├── Threshold.vhd │ │ │ ├── fifo_w20_d2_A.vhd │ │ │ ├── fifo_w8_d1_A.vhd │ │ │ ├── fifo_w9_d3_A.vhd │ │ │ ├── threshold_hls.vhd │ │ │ ├── threshold_hls_CONTROL_BUS_s_axi.vhd │ │ │ ├── threshold_hls_mulbkb.vhd │ │ │ └── threshold_hls_mulcud.vhd │ └── script.tcl │ └── threshold.h └── PYNQ ├── ip ├── audio_codec_ctrl_v1.0 │ ├── component.xml │ ├── src │ │ ├── address_decoder.vhd │ │ ├── axi_lite_ipif.vhd │ │ ├── common_types.vhd │ │ ├── family_support.vhd │ │ ├── i2s_ctrl.vhd │ │ ├── iis_deser.vhd │ │ ├── iis_ser.vhd │ │ ├── pselect_f.vhd │ │ ├── slave_attachment.vhd │ │ └── user_logic.vhd │ └── xgui │ │ ├── audio_codec_ctrl_v1_0.tcl │ │ └── i2s_ctrl_v1_0.tcl ├── audio_direct_1.1 │ ├── bd │ │ └── bd.tcl │ ├── component.xml │ ├── drivers │ │ └── audio_direct_v1_0 │ │ │ ├── data │ │ │ ├── audio_direct.mdd │ │ │ └── audio_direct.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── audio_direct.c │ │ │ ├── audio_direct.h │ │ │ └── audio_direct_selftest.c │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── audio_direct_v1_1_tb.sv │ │ │ └── design.tcl │ │ └── debug_hw_design │ │ │ ├── audio_direct_v1_1_hw_test.tcl │ │ │ └── design.tcl │ ├── hdl │ │ └── audio_direct_v1_1.v │ ├── src │ │ ├── PdmDes.v │ │ ├── PdmSer.v │ │ ├── audio_direct.v │ │ ├── audio_direct_path.v │ │ ├── d_axi_pdm_v1_2_S_AXI.vhd │ │ ├── fifo_512.edif │ │ ├── pdm_des.vhd │ │ ├── pdm_rxtx.vhd │ │ └── pdm_ser.vhd │ └── xgui │ │ └── audio_direct_v1_1.tcl ├── axi_dynclk_v1_0 │ ├── component.xml │ ├── src │ │ ├── axi_dynclk.vhd │ │ ├── axi_dynclk_S00_AXI.vhd │ │ └── mmcme2_drp.v │ └── xgui │ │ └── axi_dynclk_v1_0.tcl ├── boolean_generator_1.1 │ ├── bd │ │ └── bd.tcl │ ├── component.xml │ ├── drivers │ │ └── boolean_generator_v1_0 │ │ │ ├── data │ │ │ ├── boolean_generator.mdd │ │ │ └── boolean_generator.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── boolean_generator.c │ │ │ ├── boolean_generator.h │ │ │ └── boolean_generator_selftest.c │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── boolean_generator_v1_1_tb.sv │ │ │ └── design.tcl │ │ └── debug_hw_design │ │ │ ├── boolean_generator_v1_1_hw_test.tcl │ │ │ └── design.tcl │ ├── hdl │ │ ├── boolean_generator_v1_1.v │ │ └── boolean_generator_v1_1_S_AXI.v │ ├── src │ │ ├── boolean_fsm.v │ │ ├── boolean_gr.v │ │ ├── boolean_input.v │ │ ├── boolean_lut.v │ │ └── input_mux.v │ └── xgui │ │ └── boolean_generator_v1_1.tcl ├── color_swap_1.0 │ ├── color_swap.v │ ├── component.xml │ └── xgui │ │ └── color_swap_v1_0.tcl ├── debouncer_1.1 │ ├── component.xml │ ├── debouncer.v │ ├── gui │ │ └── debouncer_v1_0.gtcl │ └── xgui │ │ └── debouncer_v1_1.tcl ├── dff_en_reset_vector_1.0 │ ├── component.xml │ ├── dff_en_reset_vector.v │ └── xgui │ │ └── dff_en_reset_vector_v1_0.tcl ├── dvi2rgb_v1_7 │ ├── component.xml │ ├── docs │ │ ├── 1024_edid.dat │ │ ├── 1080_edid.dat │ │ ├── 720p_edid.dat │ │ ├── 900p_edid.dat │ │ ├── dat2txt.cpp │ │ ├── dvi2rgb.pdf │ │ └── dvi2rgb_v1_7.docx │ ├── gui │ │ └── dvi2rgb_v1_0.gtcl │ ├── src │ │ ├── 1024_edid.data │ │ ├── 1080_edid.data │ │ ├── 720p_edid.data │ │ ├── 900p_edid.data │ │ ├── ChannelBond.vhd │ │ ├── DVI_Constants.vhd │ │ ├── EEPROM_8b.vhd │ │ ├── GlitchFilter.vhd │ │ ├── InputSERDES.vhd │ │ ├── PhaseAlign.vhd │ │ ├── ResyncToBUFG.vhd │ │ ├── SyncAsync.vhd │ │ ├── SyncAsyncReset.vhd │ │ ├── SyncBase.vhd │ │ ├── TMDS_Clocking.vhd │ │ ├── TMDS_Decoder.vhd │ │ ├── TWI_SlaveCtl.vhd │ │ ├── dvi2rgb.vhd │ │ ├── dvi2rgb.xdc │ │ └── dvi2rgb_ooc.xdc │ └── xgui │ │ ├── dvi2rgb_v1_3.tcl │ │ ├── dvi2rgb_v1_4.tcl │ │ ├── dvi2rgb_v1_5.tcl │ │ ├── dvi2rgb_v1_6.tcl │ │ └── dvi2rgb_v1_7.tcl ├── fsm_controller_1.1 │ ├── component.xml │ ├── fsm_controller.v │ ├── pulse_gen.v │ └── xgui │ │ └── fsm_controller_v1_0.tcl ├── fsm_io_switch_1.1 │ ├── bd │ │ └── bd.tcl │ ├── component.xml │ ├── drivers │ │ └── fsm_io_switch_v1_0 │ │ │ ├── data │ │ │ ├── fsm_io_switch.mdd │ │ │ └── fsm_io_switch.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── fsm_io_switch.c │ │ │ ├── fsm_io_switch.h │ │ │ └── fsm_io_switch_selftest.c │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── design.tcl │ │ │ └── fsm_io_switch_v1_1_tb.sv │ │ └── debug_hw_design │ │ │ ├── design.tcl │ │ │ └── fsm_io_switch_v1_1_hw_test.tcl │ ├── hdl │ │ ├── fsm_io_switch_v1_1.v │ │ └── fsm_io_switch_v1_1_S_AXI.v │ ├── src │ │ ├── input_mux.v │ │ ├── mux_2_to_1.v │ │ └── output_demux.v │ └── xgui │ │ └── fsm_io_switch_v1_1.tcl ├── gclk_generator_1.0 │ ├── bd │ │ └── bd.tcl │ ├── component.xml │ ├── drivers │ │ └── gclk_generator_v1_0 │ │ │ ├── data │ │ │ ├── gclk_generator.mdd │ │ │ └── gclk_generator.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── gclk_generator.c │ │ │ ├── gclk_generator.h │ │ │ └── gclk_generator_selftest.c │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── design.tcl │ │ │ └── gclk_generator_v1_0_tb.sv │ │ └── debug_hw_design │ │ │ ├── design.tcl │ │ │ └── gclk_generator_v1_0_hw_test.tcl │ ├── hdl │ │ ├── gclk_generator_v1_0.v │ │ └── gclk_generator_v1_0_S_AXI.v │ ├── src │ │ ├── counter.v │ │ └── pulse_gen.v │ └── xgui │ │ └── gclk_generator_v1_0.tcl ├── hls │ ├── .gitignore │ ├── build_ip.bat │ ├── build_ip.sh │ ├── color_convert │ │ ├── .apc │ │ │ └── autopilot.apfmapping │ │ ├── .cproject │ │ ├── .project │ │ ├── .settings │ │ │ ├── color_convert.Debug.launch │ │ │ ├── color_convert.Release.launch │ │ │ └── language.settings.xml │ │ ├── color_convert.cpp │ │ ├── color_convert_test.cpp │ │ └── script.tcl │ ├── pixel_pack │ │ ├── pixel_pack.cpp │ │ ├── pixel_pack_test.cpp │ │ └── script.tcl │ └── pixel_unpack │ │ ├── pixel_unpack.cpp │ │ ├── pixel_unpack_test.cpp │ │ └── script.tcl ├── if │ └── tmds_v1_0 │ │ ├── tmds.xml │ │ └── tmds_rtl.xml ├── interface_switch_1.1 │ ├── component.xml │ ├── interface_switch.v │ ├── mux_4_to_1.v │ └── xgui │ │ └── interface_switch_v1_0.tcl ├── io_switch_1.1 │ ├── bd │ │ └── bd.tcl │ ├── component.xml │ ├── drivers │ │ └── io_switch_v1_0 │ │ │ ├── data │ │ │ ├── io_switch.mdd │ │ │ └── io_switch.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── io_switch.c │ │ │ ├── io_switch.h │ │ │ ├── io_switch_selftest.c │ │ │ ├── xio_switch.c │ │ │ └── xio_switch.h │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── design.tcl │ │ │ └── io_switch_v1_1_tb.sv │ │ └── debug_hw_design │ │ │ ├── design.tcl │ │ │ └── io_switch_v1_1_hw_test.tcl │ ├── gui │ │ └── io_switch_v1_1.gtcl │ ├── hdl │ │ ├── io_switch_v1_1.v │ │ └── io_switch_v1_1_S_AXI.v │ ├── src │ │ ├── io_switch.v │ │ └── io_switch_bit.v │ └── xgui │ │ └── io_switch_v1_1.tcl ├── mux_vector_1.0 │ ├── component.xml │ ├── mux_vector.v │ └── xgui │ │ └── mux_vector_v1_0.tcl ├── pattern_controller_1.1 │ ├── component.xml │ ├── pattern_controller.v │ ├── pulse_gen.v │ └── xgui │ │ └── pattern_controller_v1_0.tcl ├── rgb2dvi_v1_2 │ ├── component.xml │ ├── docs │ │ └── rgb2dvi_v1_2.pdf │ ├── src │ │ ├── ClockGen.vhd │ │ ├── DVI_Constants.vhd │ │ ├── OutputSERDES.vhd │ │ ├── SyncAsync.vhd │ │ ├── SyncAsyncReset.vhd │ │ ├── TMDS_Encoder.vhd │ │ ├── rgb2dvi.vhd │ │ ├── rgb2dvi.xdc │ │ ├── rgb2dvi_clocks.xdc │ │ └── rgb2dvi_ooc.xdc │ └── xgui │ │ ├── rgb2dvi_v1_1.tcl │ │ └── rgb2dvi_v1_2.tcl └── trace_generator_controller_1.1 │ ├── component.xml │ ├── pulse_gen.v │ ├── trace_generator_controller.v │ └── xgui │ └── trace_generator_controller_v1_0.tcl └── pynq_video_subsystem ├── design_copy.bd ├── design_copy.bxml ├── howto.txt ├── ip ├── design_copy_axi_dynclk_0 │ ├── design_copy_axi_dynclk_0.xci │ └── design_copy_axi_dynclk_0.xml ├── design_copy_axi_gpio_hdmiin_0 │ ├── design_copy_axi_gpio_hdmiin_0.xci │ └── design_copy_axi_gpio_hdmiin_0.xml ├── design_copy_axi_interconnect_0_0 │ ├── design_copy_axi_interconnect_0_0.xci │ └── design_copy_axi_interconnect_0_0.xml ├── design_copy_axi_mem_intercon_0 │ ├── design_copy_axi_mem_intercon_0.xci │ └── design_copy_axi_mem_intercon_0.xml ├── design_copy_axi_vdma_0 │ ├── design_copy_axi_vdma_0.xci │ └── design_copy_axi_vdma_0.xml ├── design_copy_axis_register_slice_0_0 │ ├── design_copy_axis_register_slice_0_0.xci │ └── design_copy_axis_register_slice_0_0.xml ├── design_copy_axis_register_slice_0_1 │ ├── design_copy_axis_register_slice_0_1.xci │ └── design_copy_axis_register_slice_0_1.xml ├── design_copy_color_convert_0 │ ├── design_copy_color_convert_0.xci │ └── design_copy_color_convert_0.xml ├── design_copy_color_convert_1 │ ├── design_copy_color_convert_1.xci │ └── design_copy_color_convert_1.xml ├── design_copy_color_swap_0_0 │ ├── design_copy_color_swap_0_0.xci │ └── design_copy_color_swap_0_0.xml ├── design_copy_color_swap_0_1 │ ├── design_copy_color_swap_0_1.xci │ └── design_copy_color_swap_0_1.xml ├── design_copy_dvi2rgb_0_0 │ ├── design_copy_dvi2rgb_0_0.xci │ └── design_copy_dvi2rgb_0_0.xml ├── design_copy_hdmi_out_hpd_video_0 │ ├── design_copy_hdmi_out_hpd_video_0.xci │ └── design_copy_hdmi_out_hpd_video_0.xml ├── design_copy_m00_regslice_0 │ ├── design_copy_m00_regslice_0.xci │ └── design_copy_m00_regslice_0.xml ├── design_copy_m00_regslice_1 │ ├── design_copy_m00_regslice_1.xci │ └── design_copy_m00_regslice_1.xml ├── design_copy_m01_regslice_0 │ ├── design_copy_m01_regslice_0.xci │ └── design_copy_m01_regslice_0.xml ├── design_copy_m02_regslice_0 │ ├── design_copy_m02_regslice_0.xci │ └── design_copy_m02_regslice_0.xml ├── design_copy_m03_regslice_0 │ ├── design_copy_m03_regslice_0.xci │ └── design_copy_m03_regslice_0.xml ├── design_copy_m04_regslice_0 │ ├── design_copy_m04_regslice_0.xci │ └── design_copy_m04_regslice_0.xml ├── design_copy_m05_regslice_0 │ ├── design_copy_m05_regslice_0.xci │ └── design_copy_m05_regslice_0.xml ├── design_copy_m06_regslice_0 │ ├── design_copy_m06_regslice_0.xci │ └── design_copy_m06_regslice_0.xml ├── design_copy_m07_regslice_0 │ ├── design_copy_m07_regslice_0.xci │ └── design_copy_m07_regslice_0.xml ├── design_copy_m08_regslice_0 │ ├── design_copy_m08_regslice_0.xci │ └── design_copy_m08_regslice_0.xml ├── design_copy_m09_regslice_0 │ ├── design_copy_m09_regslice_0.xci │ └── design_copy_m09_regslice_0.xml ├── design_copy_pixel_pack_0 │ ├── design_copy_pixel_pack_0.xci │ └── design_copy_pixel_pack_0.xml ├── design_copy_pixel_unpack_0 │ ├── design_copy_pixel_unpack_0.xci │ └── design_copy_pixel_unpack_0.xml ├── design_copy_proc_sys_reset_pixelclk_0 │ ├── design_copy_proc_sys_reset_pixelclk_0.xci │ └── design_copy_proc_sys_reset_pixelclk_0.xml ├── design_copy_rgb2dvi_0_0 │ ├── design_copy_rgb2dvi_0_0.xci │ └── design_copy_rgb2dvi_0_0.xml ├── design_copy_s00_regslice_0 │ ├── design_copy_s00_regslice_0.xci │ └── design_copy_s00_regslice_0.xml ├── design_copy_s00_regslice_1 │ ├── design_copy_s00_regslice_1.xci │ └── design_copy_s00_regslice_1.xml ├── design_copy_s01_regslice_0 │ ├── design_copy_s01_regslice_0.xci │ └── design_copy_s01_regslice_0.xml ├── design_copy_v_axi4s_vid_out_0_0 │ ├── design_copy_v_axi4s_vid_out_0_0.xci │ └── design_copy_v_axi4s_vid_out_0_0.xml ├── design_copy_v_vid_in_axi4s_0_0 │ ├── design_copy_v_vid_in_axi4s_0_0.xci │ └── design_copy_v_vid_in_axi4s_0_0.xml ├── design_copy_vtc_in_0 │ ├── design_copy_vtc_in_0.xci │ └── design_copy_vtc_in_0.xml ├── design_copy_vtc_out_0 │ ├── design_copy_vtc_out_0.xci │ └── design_copy_vtc_out_0.xml ├── design_copy_xbar_0 │ ├── design_copy_xbar_0.xci │ └── design_copy_xbar_0.xml ├── design_copy_xbar_1 │ ├── design_copy_xbar_1.xci │ └── design_copy_xbar_1.xml └── design_copy_xlconcat_0_0 │ ├── design_copy_xlconcat_0_0.xci │ └── design_copy_xlconcat_0_0.xml └── ui └── bd_fc910af6.ui /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/.gitignore -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/.gitmodules -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/README.md -------------------------------------------------------------------------------- /cv2PYNQ_vivado/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/cv2PYNQ_vivado/.gitignore -------------------------------------------------------------------------------- /cv2PYNQ_vivado/cv2PYNQ.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/cv2PYNQ_vivado/cv2PYNQ.tcl -------------------------------------------------------------------------------- /cv2PYNQ_vivado/cv2PYNQ_vivado.ip_user_files/README.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/cv2PYNQ_vivado/cv2PYNQ_vivado.ip_user_files/README.txt -------------------------------------------------------------------------------- /cv2PYNQ_vivado/cv2PYNQ_vivado.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/cv2PYNQ_vivado/cv2PYNQ_vivado.xpr -------------------------------------------------------------------------------- /cv2PYNQ_vivado/cv2PYNQ_vivado_def_val.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/cv2PYNQ_vivado/cv2PYNQ_vivado_def_val.txt -------------------------------------------------------------------------------- /cv2PYNQ_vivado/cv2PYNQ_vivado_dump.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/cv2PYNQ_vivado/cv2PYNQ_vivado_dump.txt -------------------------------------------------------------------------------- /cv2PYNQ_vivado/ip_upgrade.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/cv2PYNQ_vivado/ip_upgrade.log -------------------------------------------------------------------------------- /doc/PYNQ-OpenCV_xohw18-155.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/doc/PYNQ-OpenCV_xohw18-155.pdf -------------------------------------------------------------------------------- /doc/block_design.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/doc/block_design.PNG -------------------------------------------------------------------------------- /doc/image_filter_block_design.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/doc/image_filter_block_design.PNG -------------------------------------------------------------------------------- /hw/cv2pynq03.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/hw/cv2pynq03.bit -------------------------------------------------------------------------------- /hw/cv2pynq03.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/hw/cv2pynq03.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/.apc/autopilot.apfmapping -------------------------------------------------------------------------------- /ip/HLS/canny/.cproject: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/.cproject -------------------------------------------------------------------------------- /ip/HLS/canny/.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/.project -------------------------------------------------------------------------------- /ip/HLS/canny/.settings/canny.Debug.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/.settings/canny.Debug.launch -------------------------------------------------------------------------------- /ip/HLS/canny/.settings/canny.Release.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/.settings/canny.Release.launch -------------------------------------------------------------------------------- /ip/HLS/canny/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/canny/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/canny/canny_edge.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/canny_edge.cpp -------------------------------------------------------------------------------- /ip/HLS/canny/canny_edge.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/canny_edge.h -------------------------------------------------------------------------------- /ip/HLS/canny/canny_edge_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/canny_edge_test.cpp -------------------------------------------------------------------------------- /ip/HLS/canny/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/canny_edge_info.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/canny_edge_info.xml -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/constraints/canny_edge.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/constraints/canny_edge.xdc -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/example/ipi_example.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/example/ipi_example.bat -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/example/ipi_example.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/example/ipi_example.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/Filter2D_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/Filter2D_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/Sobel_1_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/Sobel_1_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/Sobel_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/Sobel_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/canny_edge.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/canny_edge.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w16_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w16_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w20_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w20_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w9_d7_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/fifo_w9_d7_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/verilog/hysteresis.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/verilog/hysteresis.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Duplicate.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Duplicate.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Filter2D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Filter2D.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Loop_2_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Loop_2_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Sobel.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Sobel.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Sobel_1.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/Sobel_1.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/canny_edge.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/canny_edge.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w16_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w16_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w20_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w20_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w9_d7_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/fifo_w9_d7_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/hdl/vhdl/hysteresis.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/hdl/vhdl/hysteresis.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/pack.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/pack.bat -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/vivado.log -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/ip/xgui/canny_edge_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/ip/xgui/canny_edge_v1_0.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Block_Mat_exit29635_s.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Block_Mat_exit29635_s.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Duplicate_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Duplicate_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Filter2D_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Filter2D_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Filter2D_k_buf_0_cud.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Filter2D_k_buf_0_cud.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Loop_1_proc_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Loop_1_proc_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Loop_2_proc_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Loop_2_proc_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Sobel_1_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Sobel_1_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/Sobel_canny.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/Sobel_canny.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge.result.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge.result.rb -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge.xdc -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mug8j.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mug8j.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_muhbi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_muhbi.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_muibs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_muibs.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mujbC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mujbC.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mukbM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mukbM.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mulbW.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mac_mulbW.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mul_mubkb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mul_mubkb.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mul_muqcK.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mul_muqcK.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/canny_edge_mux_32fYi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/canny_edge_mux_32fYi.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/fifo_w16_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/fifo_w16_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/fifo_w20_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/fifo_w20_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/fifo_w9_d7_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/fifo_w9_d7_A.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/gradient_decompositi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/gradient_decompositi.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/hysteresis.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/hysteresis.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/impl.bat -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/nonmax_suppressiomb6.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/nonmax_suppressiomb6.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/nonmax_suppression.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/nonmax_suppression.v -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/project.hw/project.lpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/project.hw/project.lpr -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/verilog/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/verilog/vivado.log -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Block_Mat_exit29635_s.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Block_Mat_exit29635_s.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Duplicate.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Duplicate.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Filter2D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Filter2D.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Filter2D_k_buf_0_cud.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Filter2D_k_buf_0_cud.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Loop_2_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Loop_2_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Sobel.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Sobel.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/Sobel_1.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/Sobel_1.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mug8j.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mug8j.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_muhbi.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_muhbi.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_muibs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_muibs.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mujbC.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mujbC.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mukbM.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mukbM.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mulbW.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mac_mulbW.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mul_mubkb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mul_mubkb.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mul_muqcK.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mul_muqcK.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/canny_edge_mux_32fYi.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/canny_edge_mux_32fYi.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/fifo_w16_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/fifo_w16_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/fifo_w20_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/fifo_w20_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/fifo_w9_d7_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/fifo_w9_d7_A.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/gradient_decompositi.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/gradient_decompositi.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/hysteresis.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/hysteresis.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/nonmax_suppressiomb6.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/nonmax_suppressiomb6.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/impl/vhdl/nonmax_suppression.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/impl/vhdl/nonmax_suppression.vhd -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/solution1.aps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/solution1.aps -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/solution1.directive: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/solution1.directive -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/solution1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/solution1.log -------------------------------------------------------------------------------- /ip/HLS/canny/solution1/solution1_data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/solution1/solution1_data.json -------------------------------------------------------------------------------- /ip/HLS/canny/vivado_hls.app: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/canny/vivado_hls.app -------------------------------------------------------------------------------- /ip/HLS/dilate/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/.apc/autopilot.apfmapping -------------------------------------------------------------------------------- /ip/HLS/dilate/.cproject: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/.cproject -------------------------------------------------------------------------------- /ip/HLS/dilate/.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/.project -------------------------------------------------------------------------------- /ip/HLS/dilate/.settings/dilate.Debug.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/.settings/dilate.Debug.launch -------------------------------------------------------------------------------- /ip/HLS/dilate/.settings/dilate.Release.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/.settings/dilate.Release.launch -------------------------------------------------------------------------------- /ip/HLS/dilate/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/dilate/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/dilate/dilate_hls.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/dilate_hls.cpp -------------------------------------------------------------------------------- /ip/HLS/dilate/dilate_hls.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/dilate_hls.h -------------------------------------------------------------------------------- /ip/HLS/dilate/dilate_hls_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/dilate_hls_test.cpp -------------------------------------------------------------------------------- /ip/HLS/dilate/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/constraints/dilate_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/constraints/dilate_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/dilate_hls_info.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/dilate_hls_info.xml -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/example/ipi_example.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/example/ipi_example.bat -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/example/ipi_example.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/example/ipi_example.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/verilog/dilate_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/verilog/dilate_hls.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w11_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w11_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w11_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w11_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w1_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w1_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w31_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w31_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w32_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w32_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/Loop_3_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/Loop_3_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/dilate_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/dilate_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w11_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w11_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w11_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w11_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w1_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w1_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w31_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/hdl/vhdl/fifo_w31_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/pack.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/pack.bat -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/vivado.log -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/ip/xgui/dilate_hls_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/ip/xgui/dilate_hls_v1_0.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/dilate_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/dilate_hls.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/dilate_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/dilate_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/fifo_w11_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/fifo_w11_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/fifo_w11_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/fifo_w11_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/fifo_w1_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/fifo_w1_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/fifo_w31_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/fifo_w31_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/fifo_w32_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/fifo_w32_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/impl.bat -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/impl_1/.Vivado_Implementation.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/impl_1/.phys_opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/impl_1/.place_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/impl_1/.route_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/verilog/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/verilog/vivado.log -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/Loop_3_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/Loop_3_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/dilate_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/dilate_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/fifo_w11_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/fifo_w11_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/fifo_w11_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/fifo_w11_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/fifo_w1_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/fifo_w1_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/fifo_w31_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/fifo_w31_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/fifo_w32_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/fifo_w32_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/solution1.aps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/solution1.aps -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/solution1.directive: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/solution1.directive -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/solution1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/solution1.log -------------------------------------------------------------------------------- /ip/HLS/dilate/solution1/solution1_data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/solution1/solution1_data.json -------------------------------------------------------------------------------- /ip/HLS/dilate/vivado_hls.app: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/dilate/vivado_hls.app -------------------------------------------------------------------------------- /ip/HLS/erode/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/.apc/autopilot.apfmapping -------------------------------------------------------------------------------- /ip/HLS/erode/.cproject: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/.cproject -------------------------------------------------------------------------------- /ip/HLS/erode/.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/.project -------------------------------------------------------------------------------- /ip/HLS/erode/.settings/erode.Debug.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/.settings/erode.Debug.launch -------------------------------------------------------------------------------- /ip/HLS/erode/.settings/erode.Release.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/.settings/erode.Release.launch -------------------------------------------------------------------------------- /ip/HLS/erode/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/erode/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/erode/Morphology.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/Morphology.png -------------------------------------------------------------------------------- /ip/HLS/erode/erode_hls.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/erode_hls.cpp -------------------------------------------------------------------------------- /ip/HLS/erode/erode_hls.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/erode_hls.h -------------------------------------------------------------------------------- /ip/HLS/erode/erode_hls_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/erode_hls_test.cpp -------------------------------------------------------------------------------- /ip/HLS/erode/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/.temp11.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/.temp11.log -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/constraints/erode_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/constraints/erode_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/erode_hls_info.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/erode_hls_info.xml -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/example/ipi_example.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/example/ipi_example.bat -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/example/ipi_example.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/example/ipi_example.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/hdl/verilog/erode_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/hdl/verilog/erode_hls.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/hdl/vhdl/Loop_3_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/hdl/vhdl/Loop_3_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/hdl/vhdl/erode_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/hdl/vhdl/erode_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/hdl/vhdl/fifo_w1_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/hdl/vhdl/fifo_w1_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/hdl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/hdl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/pack.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/pack.bat -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/vivado.log -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/ip/xgui/erode_hls_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/ip/xgui/erode_hls_v1_0.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/Loop_1_proc_erode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/Loop_1_proc_erode.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/Loop_3_proc_erode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/Loop_3_proc_erode.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/erode_hls.result.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/erode_hls.result.rb -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/erode_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/erode_hls.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/erode_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/erode_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/fifo_w11_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/fifo_w11_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/fifo_w11_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/fifo_w11_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/fifo_w1_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/fifo_w1_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/fifo_w31_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/fifo_w31_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/fifo_w32_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/fifo_w32_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/impl.bat -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/impl_1/.Vivado_Implementation.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/impl_1/.phys_opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/impl_1/.place_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/impl_1/.route_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/verilog/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/verilog/vivado.log -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/Loop_3_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/Loop_3_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/erode_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/erode_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/erode_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/erode_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/fifo_w11_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/fifo_w11_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/fifo_w11_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/fifo_w11_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/fifo_w1_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/fifo_w1_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/fifo_w31_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/fifo_w31_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/fifo_w32_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/fifo_w32_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/impl.bat -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/project.hw/project.lpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/project.hw/project.lpr -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/project.xpr -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/impl/vhdl/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/impl/vhdl/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/solution1.aps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/solution1.aps -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/solution1.directive: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/solution1.directive -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/solution1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/solution1.log -------------------------------------------------------------------------------- /ip/HLS/erode/solution1/solution1_data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/solution1/solution1_data.json -------------------------------------------------------------------------------- /ip/HLS/erode/vivado_hls.app: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/erode/vivado_hls.app -------------------------------------------------------------------------------- /ip/HLS/filter2D/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/.apc/autopilot.apfmapping -------------------------------------------------------------------------------- /ip/HLS/filter2D/.cproject: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/.cproject -------------------------------------------------------------------------------- /ip/HLS/filter2D/.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/.project -------------------------------------------------------------------------------- /ip/HLS/filter2D/.settings/filter2D.Debug.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/.settings/filter2D.Debug.launch -------------------------------------------------------------------------------- /ip/HLS/filter2D/.settings/filter2D.Release.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/.settings/filter2D.Release.launch -------------------------------------------------------------------------------- /ip/HLS/filter2D/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D/filter2D_hls.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/filter2D_hls.cpp -------------------------------------------------------------------------------- /ip/HLS/filter2D/filter2D_hls.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/filter2D_hls.h -------------------------------------------------------------------------------- /ip/HLS/filter2D/filter2D_hls_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/filter2D_hls_test.cpp -------------------------------------------------------------------------------- /ip/HLS/filter2D/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/filter2D_hls_info.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/filter2D_hls_info.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/hdl/vhdl/Filter2D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/hdl/vhdl/Filter2D.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/pack.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/pack.bat -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/ip/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/ip/vivado.log -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/fifo_w31_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/fifo_w31_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/fifo_w32_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/fifo_w32_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/fifo_w8_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/fifo_w8_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/filter2D_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/filter2D_hls.v -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/filter2D_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/filter2D_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/impl.bat -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/impl_1/.Vivado_Implementation.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/impl_1/.phys_opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/impl_1/.place_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/impl_1/.route_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/verilog/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/verilog/vivado.log -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/Block_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/Block_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/Filter2D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/Filter2D.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/Loop_2_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/Loop_2_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/fifo_w31_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/fifo_w31_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/fifo_w32_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/fifo_w32_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/fifo_w8_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/fifo_w8_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/filter2D_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/filter2D_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/filter2D_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/filter2D_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/impl.bat -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/project.xpr -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/impl/vhdl/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/impl/vhdl/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/solution1.aps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/solution1.aps -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/solution1.directive: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/solution1.directive -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/solution1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/solution1.log -------------------------------------------------------------------------------- /ip/HLS/filter2D/solution1/solution1_data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/solution1/solution1_data.json -------------------------------------------------------------------------------- /ip/HLS/filter2D/vivado_hls.app: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D/vivado_hls.app -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/.apc/autopilot.apfmapping -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/.cproject: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/.cproject -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/.project -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/.settings/filter2D_5.Debug.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/.settings/filter2D_5.Debug.launch -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/.settings/filter2D_5.Release.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/.settings/filter2D_5.Release.launch -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/filter2D_hls_5.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/filter2D_hls_5.cpp -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/filter2D_hls_5.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/filter2D_hls_5.h -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/filter2D_hls_5_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/filter2D_hls_5_test.cpp -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/pack.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/pack.bat -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/ip/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/ip/vivado.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/Block_proc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/Block_proc.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/Filter2D.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/Filter2D.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/Loop_1_proc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/Loop_1_proc.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/Loop_2_proc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/Loop_2_proc.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w20_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w20_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w8_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w8_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w9_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/fifo_w9_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/impl.bat -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/impl_1/.Vivado_Implementation.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/impl_1/.phys_opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/impl_1/.place_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/impl_1/.route_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/verilog/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/verilog/vivado.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/Block_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/Block_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/Filter2D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/Filter2D.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/Loop_2_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/Loop_2_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w20_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w20_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w8_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w8_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w9_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/fifo_w9_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/impl/vhdl/filter2D_hls_5.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/impl/vhdl/filter2D_hls_5.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/solution1.aps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/solution1.aps -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/solution1.directive: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/solution1.directive -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/solution1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/solution1.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/solution1/solution1_data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/solution1/solution1_data.json -------------------------------------------------------------------------------- /ip/HLS/filter2D_5/vivado_hls.app: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_5/vivado_hls.app -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/.apc/autopilot.apfmapping -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/.cproject: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/.cproject -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/.project -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/.settings/filter2D_f.Debug.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/.settings/filter2D_f.Debug.launch -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/.settings/filter2D_f.Release.launch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/.settings/filter2D_f.Release.launch -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/filter2D_f.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/filter2D_f.cpp -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/filter2D_f.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/filter2D_f.h -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/filter2D_f_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/filter2D_f_test.cpp -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/filter2D_f_info.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/filter2D_f_info.xml -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/pack.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/pack.bat -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/ip/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/ip/vivado.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/misc/logo.png -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/autoimpl.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/autoimpl.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w25_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w25_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w32_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w32_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w32_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w32_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/filter2D_f.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/filter2D_f.v -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/filter2D_f.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/filter2D_f.xdc -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/impl.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/impl.bat -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/impl_1/.Vivado_Implementation.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/impl_1/.phys_opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/impl_1/.place_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/impl_1/.route_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/verilog/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/verilog/vivado.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/Block_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/Block_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/Filter2D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/Filter2D.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/Loop_2_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/Loop_2_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w25_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w25_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w32_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w32_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w32_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w32_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/impl/vhdl/filter2D_f.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/impl/vhdl/filter2D_f.vhd -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/solution1.aps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/solution1.aps -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/solution1.directive: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/solution1.directive -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/solution1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/solution1.log -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/solution1/solution1_data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/solution1/solution1_data.json -------------------------------------------------------------------------------- /ip/HLS/filter2D_f/vivado_hls.app: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/filter2D_f/vivado_hls.app -------------------------------------------------------------------------------- /ip/HLS/makeHLScodeUnique.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/makeHLScodeUnique.py -------------------------------------------------------------------------------- /ip/HLS/move/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/move/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/move/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/move/move.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/move.h -------------------------------------------------------------------------------- /ip/HLS/move/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/constraints/move_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/constraints/move_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/example/ipi_example.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/example/ipi_example.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/verilog/fifo_w9_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/verilog/fifo_w9_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/verilog/move_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/verilog/move_hls.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/vhdl/Loop_2_proc18.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/vhdl/Loop_2_proc18.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/vhdl/Loop_3_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/vhdl/Loop_3_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/vhdl/fifo_w20_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/vhdl/fifo_w20_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/vhdl/fifo_w9_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/vhdl/fifo_w9_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/hdl/vhdl/move_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/hdl/vhdl/move_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/move_hls_info.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/move_hls_info.xml -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/ip/xgui/move_hls_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/ip/xgui/move_hls_v1_0.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/Loop_1_proc_move.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/Loop_1_proc_move.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/Loop_2_proc18.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/Loop_2_proc18.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/Loop_3_proc_move.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/Loop_3_proc_move.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/fifo_w20_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/fifo_w20_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/fifo_w9_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/fifo_w9_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/move_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/move_hls.v -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/move_hls.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/move_hls.xdc -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/Loop_2_proc18.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/Loop_2_proc18.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/Loop_3_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/Loop_3_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/fifo_w20_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/fifo_w20_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/fifo_w9_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/fifo_w9_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/move_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/move_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/move_hls_mul_32s_cud.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/move_hls_mul_32s_cud.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/move_hls_mul_mul_bkb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/move_hls_mul_mul_bkb.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/impl/vhdl/move_hls_mul_mul_dEe.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/impl/vhdl/move_hls_mul_mul_dEe.vhd -------------------------------------------------------------------------------- /ip/HLS/move/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/move/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/.settings/language.settings.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/.settings/language.settings.xml -------------------------------------------------------------------------------- /ip/HLS/threshold/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/.vivado_hls_log_all.xml -------------------------------------------------------------------------------- /ip/HLS/threshold/lena_gray.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/lena_gray.bmp -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/directives.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/directives.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/ip/auxiliary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/ip/auxiliary.xml -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/ip/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/ip/bd/bd.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/ip/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/ip/component.xml -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/ip/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/ip/doc/ReleaseNotes.txt -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/ip/run_ippack.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/ip/run_ippack.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/ip/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/ip/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/Threshold.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/Threshold.v -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/extraction.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/extraction.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/fifo_w20_d2_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/fifo_w20_d2_A.v -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/fifo_w8_d1_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/fifo_w8_d1_A.v -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/fifo_w9_d3_A.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/fifo_w9_d3_A.v -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/project.xpr -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/run_vivado.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/run_vivado.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/settings.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/settings.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/threshold_hls.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/threshold_hls.v -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/verilog/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/verilog/vivado.jou -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/vhdl/Loop_1_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/vhdl/Loop_1_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/vhdl/Loop_2_proc.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/vhdl/Loop_2_proc.vhd -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/vhdl/Threshold.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/vhdl/Threshold.vhd -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/vhdl/fifo_w20_d2_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/vhdl/fifo_w20_d2_A.vhd -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/vhdl/fifo_w8_d1_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/vhdl/fifo_w8_d1_A.vhd -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/vhdl/fifo_w9_d3_A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/vhdl/fifo_w9_d3_A.vhd -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/impl/vhdl/threshold_hls.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/impl/vhdl/threshold_hls.vhd -------------------------------------------------------------------------------- /ip/HLS/threshold/solution1/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/solution1/script.tcl -------------------------------------------------------------------------------- /ip/HLS/threshold/threshold.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/HLS/threshold/threshold.h -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/address_decoder.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/address_decoder.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/axi_lite_ipif.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/axi_lite_ipif.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/common_types.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/common_types.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/family_support.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/family_support.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/i2s_ctrl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/i2s_ctrl.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/iis_deser.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/iis_deser.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/iis_ser.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/iis_ser.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/pselect_f.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/pselect_f.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/user_logic.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/src/user_logic.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_codec_ctrl_v1.0/xgui/i2s_ctrl_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_codec_ctrl_v1.0/xgui/i2s_ctrl_v1_0.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/bd/bd.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/hdl/audio_direct_v1_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/hdl/audio_direct_v1_1.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/PdmDes.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/PdmDes.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/PdmSer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/PdmSer.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/audio_direct.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/audio_direct.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/audio_direct_path.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/audio_direct_path.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/d_axi_pdm_v1_2_S_AXI.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/d_axi_pdm_v1_2_S_AXI.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/fifo_512.edif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/fifo_512.edif -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/pdm_des.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/pdm_des.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/pdm_rxtx.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/pdm_rxtx.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/src/pdm_ser.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/src/pdm_ser.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/audio_direct_1.1/xgui/audio_direct_v1_1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/audio_direct_1.1/xgui/audio_direct_v1_1.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/axi_dynclk_v1_0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/axi_dynclk_v1_0/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/axi_dynclk_v1_0/src/axi_dynclk.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/axi_dynclk_v1_0/src/axi_dynclk.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/axi_dynclk_v1_0/src/axi_dynclk_S00_AXI.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/axi_dynclk_v1_0/src/axi_dynclk_S00_AXI.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/axi_dynclk_v1_0/src/mmcme2_drp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/axi_dynclk_v1_0/src/mmcme2_drp.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/axi_dynclk_v1_0/xgui/axi_dynclk_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/axi_dynclk_v1_0/xgui/axi_dynclk_v1_0.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/boolean_generator_1.1/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/boolean_generator_1.1/bd/bd.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/boolean_generator_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/boolean_generator_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/boolean_generator_1.1/src/boolean_fsm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/boolean_generator_1.1/src/boolean_fsm.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/boolean_generator_1.1/src/boolean_gr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/boolean_generator_1.1/src/boolean_gr.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/boolean_generator_1.1/src/boolean_input.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/boolean_generator_1.1/src/boolean_input.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/boolean_generator_1.1/src/boolean_lut.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/boolean_generator_1.1/src/boolean_lut.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/boolean_generator_1.1/src/input_mux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/boolean_generator_1.1/src/input_mux.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/color_swap_1.0/color_swap.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/color_swap_1.0/color_swap.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/color_swap_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/color_swap_1.0/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/color_swap_1.0/xgui/color_swap_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/color_swap_1.0/xgui/color_swap_v1_0.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/debouncer_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/debouncer_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/debouncer_1.1/debouncer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/debouncer_1.1/debouncer.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/debouncer_1.1/gui/debouncer_v1_0.gtcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/debouncer_1.1/gui/debouncer_v1_0.gtcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/debouncer_1.1/xgui/debouncer_v1_1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/debouncer_1.1/xgui/debouncer_v1_1.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/dff_en_reset_vector_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dff_en_reset_vector_1.0/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/dff_en_reset_vector_1.0/dff_en_reset_vector.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dff_en_reset_vector_1.0/dff_en_reset_vector.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/docs/1024_edid.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/docs/1024_edid.dat -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/docs/1080_edid.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/docs/1080_edid.dat -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/docs/720p_edid.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/docs/720p_edid.dat -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/docs/900p_edid.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/docs/900p_edid.dat -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/docs/dat2txt.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/docs/dat2txt.cpp -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/docs/dvi2rgb.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/docs/dvi2rgb.pdf -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/docs/dvi2rgb_v1_7.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/docs/dvi2rgb_v1_7.docx -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/gui/dvi2rgb_v1_0.gtcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/gui/dvi2rgb_v1_0.gtcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/1024_edid.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/1024_edid.data -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/1080_edid.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/1080_edid.data -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/720p_edid.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/720p_edid.data -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/900p_edid.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/900p_edid.data -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/ChannelBond.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/ChannelBond.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/DVI_Constants.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/DVI_Constants.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/EEPROM_8b.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/EEPROM_8b.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/GlitchFilter.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/GlitchFilter.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/InputSERDES.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/InputSERDES.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/PhaseAlign.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/PhaseAlign.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/ResyncToBUFG.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/ResyncToBUFG.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/SyncAsync.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/SyncAsync.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/SyncAsyncReset.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/SyncAsyncReset.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/SyncBase.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/SyncBase.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/TMDS_Clocking.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/TMDS_Clocking.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/TMDS_Decoder.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/TMDS_Decoder.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/TWI_SlaveCtl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/TWI_SlaveCtl.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/dvi2rgb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/dvi2rgb.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/dvi2rgb.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/dvi2rgb.xdc -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/src/dvi2rgb_ooc.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/src/dvi2rgb_ooc.xdc -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_3.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_3.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_4.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_4.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_5.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_5.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_6.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_6.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_7.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/dvi2rgb_v1_7/xgui/dvi2rgb_v1_7.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_controller_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_controller_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_controller_1.1/fsm_controller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_controller_1.1/fsm_controller.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_controller_1.1/pulse_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_controller_1.1/pulse_gen.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_io_switch_1.1/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_io_switch_1.1/bd/bd.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_io_switch_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_io_switch_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_io_switch_1.1/hdl/fsm_io_switch_v1_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_io_switch_1.1/hdl/fsm_io_switch_v1_1.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_io_switch_1.1/src/input_mux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_io_switch_1.1/src/input_mux.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_io_switch_1.1/src/mux_2_to_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_io_switch_1.1/src/mux_2_to_1.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_io_switch_1.1/src/output_demux.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_io_switch_1.1/src/output_demux.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/fsm_io_switch_1.1/xgui/fsm_io_switch_v1_1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/fsm_io_switch_1.1/xgui/fsm_io_switch_v1_1.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/gclk_generator_1.0/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/gclk_generator_1.0/bd/bd.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/gclk_generator_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/gclk_generator_1.0/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/gclk_generator_1.0/hdl/gclk_generator_v1_0.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/gclk_generator_1.0/hdl/gclk_generator_v1_0.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/gclk_generator_1.0/src/counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/gclk_generator_1.0/src/counter.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/gclk_generator_1.0/src/pulse_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/gclk_generator_1.0/src/pulse_gen.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/.gitignore: -------------------------------------------------------------------------------- 1 | */solution1 2 | */vivado_hls.app 3 | -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/build_ip.bat: -------------------------------------------------------------------------------- 1 | for /D %%f in ( * ) do vivado_hls -f %%f\script.tcl 2 | -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/build_ip.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | for f in */script.tcl 4 | do 5 | vivado_hls -f $f 6 | done 7 | -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/color_convert/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/color_convert/.apc/autopilot.apfmapping -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/color_convert/.cproject: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/color_convert/.cproject -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/color_convert/.project: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/color_convert/.project -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/color_convert/color_convert.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/color_convert/color_convert.cpp -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/color_convert/color_convert_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/color_convert/color_convert_test.cpp -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/color_convert/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/color_convert/script.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/pixel_pack/pixel_pack.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/pixel_pack/pixel_pack.cpp -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/pixel_pack/pixel_pack_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/pixel_pack/pixel_pack_test.cpp -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/pixel_pack/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/pixel_pack/script.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/pixel_unpack/pixel_unpack.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/pixel_unpack/pixel_unpack.cpp -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/pixel_unpack/pixel_unpack_test.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/pixel_unpack/pixel_unpack_test.cpp -------------------------------------------------------------------------------- /ip/PYNQ/ip/hls/pixel_unpack/script.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/hls/pixel_unpack/script.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/if/tmds_v1_0/tmds.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/if/tmds_v1_0/tmds.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/if/tmds_v1_0/tmds_rtl.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/if/tmds_v1_0/tmds_rtl.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/interface_switch_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/interface_switch_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/interface_switch_1.1/interface_switch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/interface_switch_1.1/interface_switch.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/interface_switch_1.1/mux_4_to_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/interface_switch_1.1/mux_4_to_1.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/bd/bd.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/gui/io_switch_v1_1.gtcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/gui/io_switch_v1_1.gtcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/hdl/io_switch_v1_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/hdl/io_switch_v1_1.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/hdl/io_switch_v1_1_S_AXI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/hdl/io_switch_v1_1_S_AXI.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/src/io_switch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/src/io_switch.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/src/io_switch_bit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/src/io_switch_bit.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/io_switch_1.1/xgui/io_switch_v1_1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/io_switch_1.1/xgui/io_switch_v1_1.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/mux_vector_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/mux_vector_1.0/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/mux_vector_1.0/mux_vector.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/mux_vector_1.0/mux_vector.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/mux_vector_1.0/xgui/mux_vector_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/mux_vector_1.0/xgui/mux_vector_v1_0.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/pattern_controller_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/pattern_controller_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/pattern_controller_1.1/pattern_controller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/pattern_controller_1.1/pattern_controller.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/pattern_controller_1.1/pulse_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/pattern_controller_1.1/pulse_gen.v -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/docs/rgb2dvi_v1_2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/docs/rgb2dvi_v1_2.pdf -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/ClockGen.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/ClockGen.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/DVI_Constants.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/DVI_Constants.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/OutputSERDES.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/OutputSERDES.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/SyncAsync.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/SyncAsync.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/SyncAsyncReset.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/SyncAsyncReset.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/TMDS_Encoder.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/TMDS_Encoder.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi.vhd -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi.xdc -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi_ooc.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/src/rgb2dvi_ooc.xdc -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/xgui/rgb2dvi_v1_1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/xgui/rgb2dvi_v1_1.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/rgb2dvi_v1_2/xgui/rgb2dvi_v1_2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/rgb2dvi_v1_2/xgui/rgb2dvi_v1_2.tcl -------------------------------------------------------------------------------- /ip/PYNQ/ip/trace_generator_controller_1.1/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/trace_generator_controller_1.1/component.xml -------------------------------------------------------------------------------- /ip/PYNQ/ip/trace_generator_controller_1.1/pulse_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/ip/trace_generator_controller_1.1/pulse_gen.v -------------------------------------------------------------------------------- /ip/PYNQ/pynq_video_subsystem/design_copy.bd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/pynq_video_subsystem/design_copy.bd -------------------------------------------------------------------------------- /ip/PYNQ/pynq_video_subsystem/design_copy.bxml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/pynq_video_subsystem/design_copy.bxml -------------------------------------------------------------------------------- /ip/PYNQ/pynq_video_subsystem/howto.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/pynq_video_subsystem/howto.txt -------------------------------------------------------------------------------- /ip/PYNQ/pynq_video_subsystem/ui/bd_fc910af6.ui: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2PYNQ-The-project-behind-the-library/HEAD/ip/PYNQ/pynq_video_subsystem/ui/bd_fc910af6.ui --------------------------------------------------------------------------------