├── MANIFEST.in ├── cv2pynq ├── bitstreams │ ├── cv2pynq03.bit │ └── cv2pynq03.tcl ├── __init__.py └── cv2pynq.py ├── .gitignore ├── LICENSE ├── setup.py ├── README.md └── notebooks └── cv2PYNQ - Get Started.ipynb /MANIFEST.in: -------------------------------------------------------------------------------- 1 | recursive-include cv2pynq/bitstreams * 2 | -------------------------------------------------------------------------------- /cv2pynq/bitstreams/cv2pynq03.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wbrueckner/cv2pynq/HEAD/cv2pynq/bitstreams/cv2pynq03.bit -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled python modules. 2 | *.pyc 3 | 4 | # Setuptools distribution folder. 5 | /dist/ 6 | 7 | # Python egg metadata, regenerated from source files by setuptools. 8 | /*.egg-info -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Wolfgang Brückner 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | from setuptools import setup 2 | import os 3 | import shutil 4 | import cv2pynq 5 | 6 | if 'BOARD' not in os.environ or os.environ['BOARD'] != 'Pynq-Z1': 7 | print("Only supported on a Pynq Z1 Board") 8 | exit(1) 9 | 10 | # Notebook copy 11 | WORK_DIR = os.path.dirname(os.path.realpath(__file__)) 12 | src_nb = WORK_DIR + '/notebooks' 13 | dst_nb_dir = '/home/xilinx/jupyter_notebooks/cv2PYNQ' 14 | if os.path.exists(dst_nb_dir): 15 | shutil.rmtree(dst_nb_dir) 16 | shutil.copytree(src_nb, dst_nb_dir) 17 | 18 | setup(name='cv2pynq', 19 | version=cv2pynq.__version__, 20 | description='Accelerates OpenCV image filter functions on Zynq', 21 | keywords='pynq opencv image filter zynq', 22 | url='http://github.com/wbrueckner/cv2pynq', 23 | author='Wolfgang Brueckner', 24 | author_email='wolfgang.brueckner@fau.de', 25 | license='MIT', 26 | packages=['cv2pynq'], 27 | include_package_data = True, 28 | package_data = { 29 | '' : ['*.bit','*.tcl','*.py','*.so'], 30 | }, 31 | install_requires=[ 32 | 'pynq','numpy','cffi' 33 | ], 34 | dependency_links=['http://github.com/xilinx/PYNQ'], 35 | zip_safe=False) -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # cv2PYNQ 2 | This Python package accelerates [OpenCV](https://opencv.org/) image filtering functions for the [PYNQ](http://www.pynq.io/) platform. 3 | The library implements a specific set of popular image filters and feature detection algorithms. 4 | The calculation of time-consuming tasks is implemented in the Programmable Logic (PL) of the ZYNQ chip. 5 | cv2PYNQ also includes the Video-Subsystem of the [base](https://github.com/Xilinx/PYNQ) project of PYNQ. 6 | Therefore, the HDMI In and Out interfaces can be used in your application. 7 | The library calculates every filter for gray-channel images with 1080p within 16 ms if the input and output buffers 8 | are located in the contiguous memory of the chip. 9 | 10 | ## Get Started 11 | Install by typing: 12 | ``` 13 | git clone https://github.com/wbrueckner/cv2pynq.git 14 | cd cv2pynq/ 15 | pip3.6 install -e . 16 | ``` 17 | into the terminal on your Pynq-Z1 board. 18 | The library comes with a [jupyter notebook](https://github.com/wbrueckner/cv2pynq/blob/master/notebooks/cv2PYNQ%20-%20Get%20Started.ipynb) to demonstrate its usage and capabilities. 19 | You find the notebook in the cv2PYNQ folder of your home tree after installation. 20 | 21 | Link to YouTube Video: 22 | https://www.youtube.com/watch?v=nRxe-NqvOl8 23 | 24 | Currently accelerated functions: 25 | - Sobel: 3x3; 5x5 26 | - Scharr 27 | - Laplacian: ksize = 1; 3; 5 28 | - blur: ksize = 3 29 | - GaussinBlur: ksize = 3 30 | - erode: ksize = 3 31 | - dilate: ksize = 3 32 | - Canny 33 | 34 | ## Contribute to cv2PYNQ 35 | 36 | Read the instructions in [cv2PYNQ - The project behind the library](https://github.com/wbrueckner/cv2PYNQ-The-project-behind-the-library). 37 | -------------------------------------------------------------------------------- /cv2pynq/__init__.py: -------------------------------------------------------------------------------- 1 | import cv2 2 | from cv2 import * 3 | import numpy as np 4 | from .cv2pynq import * 5 | from pynq.lib.video import * 6 | 7 | __version__ = 0.3 8 | 9 | c = cv2pynq() 10 | video = c.ol.video #cv2pynq uses the pynq video library and the Pynq-Z1 video subsystem 11 | 12 | def Sobel(src, ddepth, dx, dy, dst=None, ksize=3, scale=1, delta=0, borderType=cv2.BORDER_DEFAULT): 13 | """dst = cv.Sobel( src, ddepth, dx, dy[, dst[, ksize[, scale[, delta[, borderType]]]]] ) 14 | Executes the Sobel operator on hardware if input parameters fit to hardware constraints. 15 | Otherwise the OpenCV Sobel function is called.""" 16 | if (ksize == 3 or ksize == 5) and (scale == 1) and (delta == 0) and (borderType == cv2.BORDER_DEFAULT) : 17 | if (src.dtype == np.uint8) and (src.ndim == 2) : 18 | if (src.shape[0] <= cv2pynq.MAX_HEIGHT) and (src.shape[0] > 0) and (src.shape[1] <= cv2pynq.MAX_WIDTH) and (src.shape[1] > 0) : 19 | if ((ddepth == -1) and (dx == 1) and (dy == 0)) or ((ddepth == -1) and (dx == 0) and (dy == 1)) : 20 | return c.Sobel(src, ddepth, dx, dy, dst, ksize) 21 | return cv2.Sobel(src, ddepth, dx, dy, dst, ksize, scale, delta, borderType) 22 | 23 | def Scharr(src, ddepth, dx, dy, dst=None, scale=1, delta=0, borderType=cv2.BORDER_DEFAULT): 24 | """dst = cv.Scharr( src, ddepth, dx, dy[, dst[, scale[, delta[, borderType]]]] ) 25 | Executes the Scharr operator on hardware if input parameters fit to hardware constraints. 26 | Otherwise the OpenCV Scharr function is called.""" 27 | if (scale == 1) and (delta == 0) and (borderType == cv2.BORDER_DEFAULT) : 28 | if (src.dtype == np.uint8) and (src.ndim == 2) : 29 | if (src.shape[0] <= cv2pynq.MAX_HEIGHT) and (src.shape[0] > 0) and (src.shape[1] <= cv2pynq.MAX_WIDTH) and (src.shape[1] > 0) : 30 | if ((ddepth == -1) and (dx == 1) and (dy == 0)) or ((ddepth == -1) and (dx == 0) and (dy == 1)) : 31 | return c.Scharr(src, ddepth, dx, dy, dst) 32 | return cv2.Scharr(src, ddepth, dx, dy, dst, scale, delta, borderType) 33 | 34 | def Laplacian(src, ddepth, dst=None, ksize=1, scale=1, delta=0, borderType=cv2.BORDER_DEFAULT): 35 | """dst = cv.Laplacian( src, ddepth[, dst[, ksize[, scale[, delta[, borderType]]]]] ) 36 | Executes the Laplacian operator on hardware if input parameters fit to hardware constraints. 37 | Otherwise the OpenCV Laplacian function is called.""" 38 | if (ksize == 1 or ksize ==3 or ksize == 5) and (scale == 1) and (delta == 0) and (borderType == cv2.BORDER_DEFAULT) : 39 | if (src.dtype == np.uint8) and (src.ndim == 2) : 40 | if (src.shape[0] <= cv2pynq.MAX_HEIGHT) and (src.shape[0] > 0) and (src.shape[1] <= cv2pynq.MAX_WIDTH) and (src.shape[1] > 0) : 41 | if (ddepth == -1) : 42 | return c.Laplacian(src, ddepth, dst, ksize) 43 | return cv2.Laplacian(src, ddepth, dst, ksize, scale, delta, borderType) 44 | 45 | def blur(src, ksize, dst=None, anchor=(-1,-1), borderType=cv2.BORDER_DEFAULT): 46 | """dst = cv.blur( src, ksize[, dst[, anchor[, borderType]]]) 47 | Smooths an image using the kernel on hardware if input parameters fit to hardware constraints. 48 | Otherwise the OpenCV blur function is called.""" 49 | if (ksize == (3,3)) and (anchor == (-1,-1)) and (borderType == cv2.BORDER_DEFAULT) : 50 | if (src.dtype == np.uint8) and (src.ndim == 2) : 51 | return c.blur(src, ksize, dst) 52 | return cv2.blur(src,ksize,dst,anchor,borderType) 53 | 54 | def GaussianBlur(src, ksize, sigmaX, dst=None, sigmaY=0, borderType=cv2.BORDER_DEFAULT): 55 | """dst = cv.GaussianBlur( src, ksize, sigmaX[, dst[, sigmaY[, borderType]]]) 56 | Smooths an image using a Gaussian kernel on hardware if input parameters fit to hardware constraints. 57 | Otherwise the OpenCV GaussianBlur function is called.""" 58 | if (ksize == (3,3)) and (borderType == cv2.BORDER_DEFAULT) : 59 | if (src.dtype == np.uint8) and (src.ndim == 2) : 60 | return c.GaussianBlur(src, ksize, sigmaX, sigmaY, dst) 61 | return cv2.GaussianBlur(src,ksize,dst,anchor,borderType) 62 | 63 | def erode(src, kernel, dst=None, anchor=(-1,-1), iterations=1, borderType=cv2.BORDER_CONSTANT, borderValue=None): 64 | """dst = cv.erode( src, kernel[, dst[, anchor[, iterations[, borderType[, borderValue]]]]]) 65 | Erodes an image by using a specific structuring element on hardware if input parameters fit to hardware constraints. 66 | Otherwise the OpenCV erode function is called.""" 67 | if (kernel.shape[0] == 3) and (kernel.shape[1] == 3) and (anchor == (-1,-1)) and (borderType == cv2.BORDER_CONSTANT) and (borderValue is None): 68 | if (src.dtype == np.uint8) and (src.ndim == 2) : 69 | if (src.shape[0] <= cv2pynq.MAX_HEIGHT) and (src.shape[0] > 0) and (src.shape[1] <= cv2pynq.MAX_WIDTH) and (src.shape[1] > 0) : 70 | if np.array_equal(kernel,cv2.getStructuringElement(cv2.MORPH_RECT,(3,3))): 71 | return c.erode(src, kernel, dst, iterations, 0) # mode = 0 72 | elif np.array_equal(kernel,cv2.getStructuringElement(cv2.MORPH_CROSS,(3,3))): 73 | return c.erode(src, kernel, dst, iterations, 1) # mode = 1 74 | return cv2.erode(src,kernel, dst, anchor, iterations, borderType, borderValue) 75 | 76 | def dilate(src, kernel, dst=None, anchor=(-1,-1), iterations=1, borderType=cv2.BORDER_CONSTANT, borderValue=None): 77 | """dst = cv.dilate( src, kernel[, dst[, anchor[, iterations[, borderType[, borderValue]]]]]) 78 | Dilates an image by using a specific structuring element on hardware if input parameters fit to hardware constraints. 79 | Otherwise the OpenCV dilate function is called.""" 80 | if (kernel.shape[0] == 3) and (kernel.shape[1] == 3) and (anchor == (-1,-1)) and (borderType == cv2.BORDER_CONSTANT) and (borderValue is None): 81 | if (src.dtype == np.uint8) and (src.ndim == 2) : 82 | if (src.shape[0] <= cv2pynq.MAX_HEIGHT) and (src.shape[0] > 0) and (src.shape[1] <= cv2pynq.MAX_WIDTH) and (src.shape[1] > 0) : 83 | if np.array_equal(kernel,cv2.getStructuringElement(cv2.MORPH_RECT,(3,3))): 84 | return c.dilate(src, kernel, dst, iterations, 0) # mode = 0 85 | elif np.array_equal(kernel,cv2.getStructuringElement(cv2.MORPH_CROSS,(3,3))): 86 | return c.dilate(src, kernel, dst, iterations, 1) # mode = 1 87 | return cv2.dilate(src,kernel, dst, anchor, iterations, borderType, borderValue) 88 | 89 | def Canny(image, threshold1, threshold2, edges=None, apertureSize=3, L2gradient=False): 90 | """ edges = cv.Canny(image, threshold1, threshold2[, edges[, apertureSize[, L2gradient]]]) 91 | Finds edges in an image by using the Canny algorithm on hardware if the input parameter fit to the hardware constraints. 92 | Caution: results of the hardware implementation may differ to OpenCV Canny output. 93 | Otherwise the OpenCV Canny function is called.""" 94 | if (apertureSize == 3) and (L2gradient == False) : 95 | if (image.dtype == np.uint8) and (image.ndim == 2) : 96 | if (image.shape[0] <= cv2pynq.MAX_HEIGHT) and (image.shape[0] > 0) and (image.shape[1] <= cv2pynq.MAX_WIDTH) and (image.shape[1] > 0) : 97 | return c.Canny(image, threshold1, threshold2, edges) 98 | return cv2.Canny(image, threshold1, threshold2, edges, apertureSize, L2gradient) 99 | 100 | '''def cornerHarris(src, blockSize, ksize, k, dst=None, borderType=cv2.BORDER_DEFAULT): 101 | """dst = cv.cornerHarris( src, blockSize, ksize, k[, dst[, borderType]]) 102 | Executes the Harris corner detector operation on hardware if input parameters fit to hardware constraints. 103 | Otherwise the OpenCV cornerHarris function is called.""" 104 | if (ksize == 3) and (blockSize == 2) and (borderType == cv2.BORDER_DEFAULT) : 105 | if (src.dtype == np.uint8) and (src.ndim == 2) : 106 | if (src.shape[0] <= cv2pynq.MAX_HEIGHT) and (src.shape[0] > 0) and (src.shape[1] <= cv2pynq.MAX_WIDTH) and (src.shape[1] > 0) : 107 | return c.cornerHarris(src, k, dst) 108 | return cv2.cornerHarris(src, blockSize, ksize, k, dst, borderType) 109 | ''' 110 | 111 | 112 | def close(): 113 | '''this function should be called after using the cv2pynq library. 114 | It cleans up the internal state and frees the used CMA-buffers. 115 | ''' 116 | c.close() -------------------------------------------------------------------------------- /notebooks/cv2PYNQ - Get Started.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": {}, 6 | "source": [ 7 | "# cv2PYNQ: Get Started" 8 | ] 9 | }, 10 | { 11 | "cell_type": "markdown", 12 | "metadata": {}, 13 | "source": [ 14 | "This jupyter notebook serves as a quick start guide of the cv2PYNQ library. \n", 15 | "It demonstrates its capabilities as well as the limitations and what to pay attention to. \n", 16 | "This notebook was created based on [this](https://github.com/Xilinx/PYNQ-ComputerVision/tree/master/notebooks/computer_vision) template." 17 | ] 18 | }, 19 | { 20 | "cell_type": "markdown", 21 | "metadata": {}, 22 | "source": [ 23 | "## Include cv2PYNQ\n", 24 | "\n" 25 | ] 26 | }, 27 | { 28 | "cell_type": "code", 29 | "execution_count": 1, 30 | "metadata": {}, 31 | "outputs": [ 32 | { 33 | "data": { 34 | "application/javascript": [ 35 | "\n", 36 | "require(['notebook/js/codecell'], function(codecell) {\n", 37 | " codecell.CodeCell.options_default.highlight_modes[\n", 38 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 39 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 40 | " Jupyter.notebook.get_cells().map(function(cell){\n", 41 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 42 | " });\n", 43 | "});\n" 44 | ] 45 | }, 46 | "metadata": {}, 47 | "output_type": "display_data" 48 | } 49 | ], 50 | "source": [ 51 | "import cv2pynq as cv2" 52 | ] 53 | }, 54 | { 55 | "cell_type": "markdown", 56 | "metadata": {}, 57 | "source": [ 58 | "## The video subsystem with HDMI \n", 59 | "The library uses the video subsystem from the base PYNQ design.\n", 60 | "If you want to learn all about its capabilities, use the notebooks \n", 61 | "https://github.com/Xilinx/PYNQ/tree/master/boards/Pynq-Z1/base/notebooks/video\n", 62 | "provided by Xilinx as an introduction. \n", 63 | "You can access the video subsystem simply with *cv2.video* \n", 64 | "It contains the HDMI-in and HDMI-out interfaces. \n", 65 | "CAUTION: hdmi_in.start() will take some time and will fail if no incoming video signal is detected.\n" 66 | ] 67 | }, 68 | { 69 | "cell_type": "code", 70 | "execution_count": 2, 71 | "metadata": {}, 72 | "outputs": [ 73 | { 74 | "name": "stdout", 75 | "output_type": "stream", 76 | "text": [ 77 | "VideoMode: width=1920 height=1080 bpp=8\n" 78 | ] 79 | } 80 | ], 81 | "source": [ 82 | "hdmi_in = cv2.video.hdmi_in\n", 83 | "hdmi_out = cv2.video.hdmi_out\n", 84 | "\n", 85 | "hdmi_in.configure(cv2.PIXEL_GRAY)\n", 86 | "hdmi_out.configure(hdmi_in.mode)\n", 87 | "\n", 88 | "hdmi_in.start()\n", 89 | "hdmi_out.start()\n", 90 | "\n", 91 | "print(hdmi_in.mode)" 92 | ] 93 | }, 94 | { 95 | "cell_type": "markdown", 96 | "metadata": {}, 97 | "source": [ 98 | "## Run the original OpenCV Sobel 5x5 " 99 | ] 100 | }, 101 | { 102 | "cell_type": "code", 103 | "execution_count": 3, 104 | "metadata": {}, 105 | "outputs": [ 106 | { 107 | "name": "stdout", 108 | "output_type": "stream", 109 | "text": [ 110 | "Frames per second using OpenCV: 2.7751992189247194\n" 111 | ] 112 | } 113 | ], 114 | "source": [ 115 | "import cv2 as openCV\n", 116 | "import time\n", 117 | "\n", 118 | "iterations = 10\n", 119 | "\n", 120 | "start = time.time()\n", 121 | "for i in range(iterations):\n", 122 | " inframe = hdmi_in.readframe()\n", 123 | " outframe = hdmi_out.newframe()\n", 124 | " openCV.Sobel(inframe,-1,1,0,ksize=5,dst=outframe)\n", 125 | " inframe.freebuffer()\n", 126 | " hdmi_out.writeframe(outframe)\n", 127 | "end = time.time()\n", 128 | "print(\"Frames per second using OpenCV: \" + str(iterations / (end - start)))" 129 | ] 130 | }, 131 | { 132 | "cell_type": "markdown", 133 | "metadata": {}, 134 | "source": [ 135 | "## Run the cv2PYNQ Sobel 5x5 in the Programmable Logic\n" 136 | ] 137 | }, 138 | { 139 | "cell_type": "code", 140 | "execution_count": 4, 141 | "metadata": {}, 142 | "outputs": [ 143 | { 144 | "name": "stdout", 145 | "output_type": "stream", 146 | "text": [ 147 | "Frames per second using cv2PYNQ: 59.75132486181549\n" 148 | ] 149 | } 150 | ], 151 | "source": [ 152 | "import time\n", 153 | "\n", 154 | "iterations = 10\n", 155 | "\n", 156 | "start = time.time()\n", 157 | "for i in range(iterations):\n", 158 | " inframe = hdmi_in.readframe()\n", 159 | " outframe = hdmi_out.newframe()\n", 160 | " cv2.Sobel(inframe,-1,1,0,ksize=5,dst=outframe)\n", 161 | " inframe.freebuffer()\n", 162 | " hdmi_out.writeframe(outframe)\n", 163 | "end = time.time()\n", 164 | "print(\"Frames per second using cv2PYNQ: \" + str(iterations / (end - start)))" 165 | ] 166 | }, 167 | { 168 | "cell_type": "markdown", 169 | "metadata": {}, 170 | "source": [ 171 | "## cv2PYNQ and continous memory\n", 172 | "\n", 173 | "The video subsystem returns images as [contiguous memory arrays](https://pynq.readthedocs.io/en/latest/pynq_libraries/xlnk.html). \n", 174 | "This allows the cv2PYNQ library to stream the data directly through the hardware. \n", 175 | "If the image is a normal numpy ndarray and no destination is given, the library must execute two copy functions. \n", 176 | "This results in a perspicuous drop of the framerate but is still faster than the software version." 177 | ] 178 | }, 179 | { 180 | "cell_type": "code", 181 | "execution_count": 5, 182 | "metadata": { 183 | "scrolled": true 184 | }, 185 | "outputs": [ 186 | { 187 | "name": "stdout", 188 | "output_type": "stream", 189 | "text": [ 190 | "Frames per second using cv2PYNQ without CMA: 16.418144610118855\n" 191 | ] 192 | } 193 | ], 194 | "source": [ 195 | "import numpy as np\n", 196 | "\n", 197 | "image = np.ndarray(shape=(1080,1920),dtype=np.uint8) \n", 198 | "\n", 199 | "iterations = 10\n", 200 | "\n", 201 | "start = time.time()\n", 202 | "for i in range(iterations):\n", 203 | " sobel = cv2.Sobel(image,-1,1,0,ksize=5)\n", 204 | "end = time.time()\n", 205 | "print(\"Frames per second using cv2PYNQ without CMA: \" + str(iterations / (end - start)))" 206 | ] 207 | }, 208 | { 209 | "cell_type": "markdown", 210 | "metadata": {}, 211 | "source": [ 212 | "The solution to this problem is allocating contiguous memory arrays and use them as images. \n", 213 | "Don't forget to free them after use." 214 | ] 215 | }, 216 | { 217 | "cell_type": "code", 218 | "execution_count": 6, 219 | "metadata": {}, 220 | "outputs": [ 221 | { 222 | "name": "stdout", 223 | "output_type": "stream", 224 | "text": [ 225 | "Frames per second using cv2PYNQ with CMA: 65.67885150201688\n" 226 | ] 227 | } 228 | ], 229 | "source": [ 230 | "from pynq import Xlnk\n", 231 | "xlnk = Xlnk()\n", 232 | "\n", 233 | "image_buffer = xlnk.cma_array(shape=(1080,1920), dtype=np.uint8)\n", 234 | "return_buffer = xlnk.cma_array(shape=(1080,1920), dtype=np.uint8)\n", 235 | "\n", 236 | "iterations = 10\n", 237 | "\n", 238 | "start = time.time()\n", 239 | "for i in range(iterations):\n", 240 | " cv2.Sobel(image_buffer,-1,1,0,ksize=5,dst=return_buffer)\n", 241 | "end = time.time()\n", 242 | "print(\"Frames per second using cv2PYNQ with CMA: \" + str(iterations / (end - start)))\n", 243 | "\n", 244 | "image_buffer.close()\n", 245 | "return_buffer.close()" 246 | ] 247 | }, 248 | { 249 | "cell_type": "markdown", 250 | "metadata": {}, 251 | "source": [ 252 | "## Clean up HDMI drivers\n", 253 | "\n", 254 | "NOTE: This is needed to reset the HDMI drivers in a clean state. If this is not run, subsequent executions of this notebook may show visual artifacts on the HDMI out (usually a shifted output image)" 255 | ] 256 | }, 257 | { 258 | "cell_type": "code", 259 | "execution_count": 7, 260 | "metadata": {}, 261 | "outputs": [], 262 | "source": [ 263 | "hdmi_out.close()\n", 264 | "hdmi_in.close()" 265 | ] 266 | }, 267 | { 268 | "cell_type": "markdown", 269 | "metadata": {}, 270 | "source": [ 271 | "## Clean up cv2PYNQ\n", 272 | "NOTE: This cleanup is needed because the library allocates contiguous memory and must free it. Otherwise, it may allocate all the available contiguous memory after including it a few times. The only solution is a reboot of the device, therefore do the cleanup ;) " 273 | ] 274 | }, 275 | { 276 | "cell_type": "code", 277 | "execution_count": 8, 278 | "metadata": {}, 279 | "outputs": [], 280 | "source": [ 281 | "cv2.close()" 282 | ] 283 | } 284 | ], 285 | "metadata": { 286 | "kernelspec": { 287 | "display_name": "Python 3", 288 | "language": "python", 289 | "name": "python3" 290 | }, 291 | "language_info": { 292 | "codemirror_mode": { 293 | "name": "ipython", 294 | "version": 3 295 | }, 296 | "file_extension": ".py", 297 | "mimetype": "text/x-python", 298 | "name": "python", 299 | "nbconvert_exporter": "python", 300 | "pygments_lexer": "ipython3", 301 | "version": "3.6.0" 302 | } 303 | }, 304 | "nbformat": 4, 305 | "nbformat_minor": 2 306 | } 307 | -------------------------------------------------------------------------------- /cv2pynq/cv2pynq.py: -------------------------------------------------------------------------------- 1 | import os 2 | import numpy as np 3 | from pynq import Overlay, PL, MMIO 4 | from pynq import DefaultIP, DefaultHierarchy 5 | from pynq import Xlnk 6 | from pynq.xlnk import ContiguousArray 7 | from pynq.lib import DMA 8 | from cffi import FFI 9 | import cv2 10 | 11 | CV2PYNQ_ROOT_DIR = os.path.dirname(os.path.realpath(__file__)) 12 | CV2PYNQ_BIT_DIR = os.path.join(CV2PYNQ_ROOT_DIR, 'bitstreams') 13 | 14 | class cv2pynq(): 15 | MAX_WIDTH = 1920 16 | MAX_HEIGHT = 1080 17 | def __init__(self, load_overlay=True): 18 | self.bitstream_name = None 19 | self.bitstream_name = "cv2pynq03.bit" 20 | self.bitstream_path = os.path.join(CV2PYNQ_BIT_DIR, self.bitstream_name) 21 | self.ol = Overlay(self.bitstream_path) 22 | self.ol.download() 23 | self.ol.reset() 24 | self.xlnk = Xlnk() 25 | self.partitions = 10 #split the cma into partitions for pipelined transfer 26 | self.cmaPartitionLen = self.MAX_HEIGHT*self.MAX_WIDTH/self.partitions 27 | self.listOfcma = [self.xlnk.cma_array(shape=(int(self.MAX_HEIGHT/self.partitions),self.MAX_WIDTH), dtype=np.uint8) for i in range(self.partitions)] 28 | self.img_filters = self.ol.image_filters 29 | self.dmaOut = self.img_filters.axi_dma_0.sendchannel 30 | self.dmaIn = self.img_filters.axi_dma_0.recvchannel 31 | self.dmaOut.stop() 32 | self.dmaIn.stop() 33 | self.dmaIn.start() 34 | self.dmaOut.start() 35 | self.filter2DType = -1 # filter types: SobelX=0, SobelY=1, ScharrX=2, ScharrY=3, Laplacian1=4, Laplacian3=5 36 | self.filter2D_5Type = -1 # filter types: SobelX=0, SobelY=1, Laplacian5=4 37 | self.filter2DfType = -1 # filter types: blur=0, GaussianBlur=1 38 | self.ffi = FFI() 39 | self.f2D = self.img_filters.filter2D_hls_0 40 | self.f2D.reset() 41 | self.f2D_5 = self.img_filters.filter2D_hls_5_0 42 | self.f2D_5.reset() 43 | self.f2D_f = self.img_filters.filter2D_f_0 44 | self.f2D_f.reset() 45 | self.erodeIP = self.img_filters.erode_hls_0 46 | self.erodeIP.reset() 47 | self.dilateIP = self.img_filters.dilate_hls_0 48 | self.dilateIP.reset() 49 | self.cmaBuffer_0 = self.xlnk.cma_array(shape=(self.MAX_HEIGHT,self.MAX_WIDTH), dtype=np.uint8) 50 | self.cmaBuffer0 = self.cmaBuffer_0.view(self.ContiguousArrayCv2pynq) 51 | self.cmaBuffer0.init(self.cmaBuffer_0) 52 | self.cmaBuffer_1 = self.xlnk.cma_array(shape=(self.MAX_HEIGHT,self.MAX_WIDTH), dtype=np.uint8) 53 | self.cmaBuffer1 = self.cmaBuffer_1.view(self.ContiguousArrayCv2pynq) 54 | self.cmaBuffer1.init(self.cmaBuffer_1) 55 | self.cmaBuffer_2 = self.xlnk.cma_array(shape=(self.MAX_HEIGHT*4,self.MAX_WIDTH), dtype=np.uint8) # *4 for CornerHarris return 56 | self.cmaBuffer2 = self.cmaBuffer_2.view(self.ContiguousArrayCv2pynq) 57 | self.cmaBuffer2.init(self.cmaBuffer_2) 58 | self.CannyIP = self.img_filters.canny_edge_0 59 | self.CannyIP.reset() 60 | #self.cornerHarrisIP = self.img_filters.CornerHarris_hls_0 61 | #self.cornerHarrisIP.reset() 62 | 63 | def close(self): 64 | #self.dmaOut.stop() 65 | #self.dmaIn.stop() 66 | self.cmaBuffer_0.close() 67 | self.cmaBuffer_1.close() 68 | self.cmaBuffer_2.close() 69 | for cma in self.listOfcma: 70 | cma.close() 71 | 72 | def Sobel(self,src, ddepth, dx, dy, dst, ksize): 73 | if(ksize == 3): 74 | self.f2D.rows = src.shape[0] 75 | self.f2D.columns = src.shape[1] 76 | self.f2D.channels = 1 77 | if (dx == 1) and (dy == 0) : 78 | if self.filter2DType != 0 : 79 | self.filter2DType = 0 80 | self.f2D.r1 = 0x000100ff #[-1 0 1] 81 | self.f2D.r2 = 0x000200fe #[-2 0 2] 82 | self.f2D.r3 = 0x000100ff #[-1 0 1] 83 | elif (dx == 0) and (dy == 1) : 84 | if self.filter2DType != 1 : 85 | self.filter2DType = 1 86 | self.f2D.r1 = 0x00fffeff #[-1 -2 -1] 87 | self.f2D.r2 = 0x00000000 #[ 0 0 0] 88 | self.f2D.r3 = 0x00010201 #[ 1 2 1] 89 | else: 90 | raise RuntimeError("Incorrect dx dy configuration") 91 | self.img_filters.select_filter(1) 92 | self.f2D.start() 93 | return self.filter2D(src, dst) 94 | else: #ksize == 5 95 | self.f2D_5.rows = src.shape[0] 96 | self.f2D_5.columns = src.shape[1] 97 | if (dx == 1) and (dy == 0) : 98 | if self.filter2D_5Type != 0 : 99 | self.filter2D_5Type = 0 100 | self.f2D_5.par_V = bytes([ \ 101 | #-1, -2, 0, 2, 1, 102 | 0xff, 0xfe, 0x00, 0x02, 0x01, \ 103 | #-4, -8, 0, 8, 4, 104 | 0xfc, 0xf8, 0x00, 0x08, 0x04, \ 105 | #-6, -12, 0, 12, 6, 106 | 0xfa, 0xf4, 0x00, 0x0c, 0x06, \ 107 | #-4, -8, 0, 8, 4, 108 | 0xfc, 0xf8, 0x00, 0x08, 0x04, \ 109 | #-1, -2, 0, 2, 1, 110 | 0xff, 0xfe, 0x00, 0x02, 0x01, \ 111 | 0,0,0]) #fill up to allign with 4 112 | elif (dx == 0) and (dy == 1) : 113 | if self.filter2D_5Type != 1 : 114 | self.filter2D_5Type = 1 115 | self.f2D_5.par_V = bytes([ \ 116 | #-1, -4, -6, -4, -1, 117 | 0xff, 0xfc, 0xfa, 0xfc, 0xff, \ 118 | #-2, -8, -12, -8, -2, 119 | 0xfe, 0xf8, 0xf4, 0xf8, 0xfe, \ 120 | # 0, 0, 0, 0, 0, 121 | 0x00, 0x00, 0x00, 0x00, 0x00, \ 122 | # 2, 8, 12, 8, 2, 123 | 0x02, 0x08, 0x0c, 0x08, 0x02, \ 124 | # 1, 4, 6, 4, 1, 125 | 0x01, 0x04, 0x06, 0x04, 0x01, \ 126 | 0,0,0]) #fill up to allign with 4 127 | else: 128 | raise RuntimeError("Incorrect dx dy configuration") 129 | self.img_filters.select_filter(5) 130 | self.f2D_5.start() 131 | return self.filter2D(src, dst) 132 | 133 | def Scharr(self,src, ddepth, dx, dy, dst): 134 | self.f2D.rows = src.shape[0] 135 | self.f2D.columns = src.shape[1] 136 | self.f2D.channels = 1 137 | if (dx == 1) and (dy == 0) : 138 | if self.filter2DType != 2 : 139 | self.filter2DType = 2 140 | self.f2D.r1 = 0x000300fd #[-3 0 3] 141 | self.f2D.r2 = 0x000a00f6 #[-10 0 10] 142 | self.f2D.r3 = 0x000300fd #[-3 0 3] 143 | elif (dx == 0) and (dy == 1) : 144 | if self.filter2DType != 3 : 145 | self.filter2DType = 3 146 | self.f2D.r1 = 0x00fdf6fd #[-3 -10 -3] 147 | self.f2D.r2 = 0x00000000 #[ 0 0 0] 148 | self.f2D.r3 = 0x00030a03 #[ 3 10 3] 149 | else: 150 | raise RuntimeError("Incorrect dx dy configuration") 151 | self.img_filters.select_filter(1) 152 | self.f2D.start() 153 | return self.filter2D(src, dst) 154 | 155 | def Laplacian(self,src, ddepth, dst, ksize): 156 | if ksize == 5: 157 | self.f2D_5.rows = src.shape[0] 158 | self.f2D_5.columns = src.shape[1] 159 | if self.filter2D_5Type != 4 : 160 | self.filter2D_5Type = 4 # "Laplacian_5" 161 | self.f2D_5.par_V = bytes([ \ 162 | #2, 4, 4, 4, 2, 163 | 0x02, 0x04, 0x04, 0x04, 0x02, \ 164 | #4, 0, -8, 0, 4, 165 | 0x04, 0x00, 0xf8, 0x00, 0x04, \ 166 | #4, -8, -24, -8, 4, 167 | 0x04, 0xf8, 0xe8, 0xf8, 0x04, \ 168 | #4, 0, -8, 0, 4, 169 | 0x04, 0x00, 0xf8, 0x00, 0x04, \ 170 | #2, 4, 4, 4, 2, 171 | 0x02, 0x04, 0x04, 0x04, 0x02, \ 172 | 0,0,0]) #fill up to allign with 4 173 | self.img_filters.select_filter(5) 174 | self.f2D_5.start() 175 | return self.filter2D(src, dst) 176 | else: #ksize 1 or 3 177 | self.f2D.rows = src.shape[0] 178 | self.f2D.columns = src.shape[1] 179 | self.f2D.channels = 1 180 | if ksize == 1: 181 | if (self.filter2DType != 4) : 182 | self.filter2DType = 4 # "Laplacian_1" 183 | self.f2D.r1 = 0x00000100 #[ 0 1 0] 184 | self.f2D.r2 = 0x0001fc01 #[ 1 -4 1] 185 | self.f2D.r3 = 0x00000100 #[ 0 1 0] 186 | elif ksize == 3: 187 | if (self.filter2DType != 5) : 188 | self.filter2DType = 5 # "Laplacian_3" 189 | self.f2D.r1 = 0x00020002 #[ 2 0 2] 190 | self.f2D.r2 = 0x0000f800 #[ 0 -8 0] 191 | self.f2D.r3 = 0x00020002 #[ 2 0 2] 192 | self.img_filters.select_filter(1) 193 | self.f2D.start() 194 | return self.filter2D(src, dst) 195 | 196 | def blur(self,src, ksize, dst): 197 | self.f2D_f.rows = src.shape[0] 198 | self.f2D_f.columns = src.shape[1] 199 | if (self.filter2DfType != 0) : 200 | self.filter2DfType = 0 #blur 201 | mean = self.floatToFixed(1/9, cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 202 | self.f2D_f.r11 = mean 203 | self.f2D_f.r12 = mean 204 | self.f2D_f.r13 = mean 205 | self.f2D_f.r21 = mean 206 | self.f2D_f.r22 = mean 207 | self.f2D_f.r23 = mean 208 | self.f2D_f.r31 = mean 209 | self.f2D_f.r32 = mean 210 | self.f2D_f.r33 = mean 211 | self.img_filters.select_filter(2) 212 | self.f2D_f.start() 213 | return self.filter2D(src, dst) 214 | 215 | def GaussianBlur(self, src, ksize, sigmaX, sigmaY, dst): 216 | self.f2D_f.rows = src.shape[0] 217 | self.f2D_f.columns = src.shape[1] 218 | if (self.filter2DfType != 1) : 219 | self.filter2DfType = 1 #GaussianBlur 220 | if(sigmaX <= 0): 221 | sigmaX = 0.3*((ksize[0]-1)*0.5 - 1) + 0.8 222 | if(sigmaY <= 0): 223 | sigmaY = sigmaX 224 | kX = cv2.getGaussianKernel(3,sigmaX,ktype=cv2.CV_32F) #kernel X 225 | kY = cv2.getGaussianKernel(3,sigmaY,ktype=cv2.CV_32F) #kernel Y 226 | self.f2D_f.r11 = self.floatToFixed(kY[0]*kX[0], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 227 | self.f2D_f.r12 = self.floatToFixed(kY[0]*kX[1], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 228 | self.f2D_f.r13 = self.floatToFixed(kY[0]*kX[2], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 229 | self.f2D_f.r21 = self.floatToFixed(kY[1]*kX[0], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 230 | self.f2D_f.r22 = self.floatToFixed(kY[1]*kX[1], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 231 | self.f2D_f.r23 = self.floatToFixed(kY[1]*kX[2], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 232 | self.f2D_f.r31 = self.floatToFixed(kY[2]*kX[0], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 233 | self.f2D_f.r32 = self.floatToFixed(kY[2]*kX[1], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 234 | self.f2D_f.r33 = self.floatToFixed(kY[2]*kX[2], cv2pynqDriverFilter2D_f.K_FP_W, cv2pynqDriverFilter2D_f.K_FP_F) 235 | self.img_filters.select_filter(2) 236 | self.f2D_f.start() 237 | return self.filter2D(src, dst) 238 | 239 | def erode(self, src, kernel, dst, iterations, mode): 240 | self.img_filters.select_filter(3) 241 | return self.erodeDilateKernel(src, kernel, dst, iterations, mode, self.erodeIP) 242 | 243 | def dilate(self, src, kernel, dst, iterations, mode): 244 | self.img_filters.select_filter(4) 245 | return self.erodeDilateKernel(src, kernel, dst, iterations, mode, self.dilateIP) 246 | 247 | def Canny(self, src, threshold1, threshold2, dst): 248 | self.img_filters.select_filter(0) 249 | self.CannyIP.rows = src.shape[0] 250 | self.CannyIP.columns = src.shape[1] 251 | self.CannyIP.threshold1 = threshold1 252 | self.CannyIP.threshold2 = threshold2 253 | self.CannyIP.start() 254 | if hasattr(src, 'physical_address') and hasattr(dst, 'physical_address'): 255 | self.dmaIn.transfer(dst) 256 | self.dmaOut.transfer(src) 257 | self.dmaIn.wait() 258 | return dst 259 | 260 | self.cmaBuffer1.nbytes = src.nbytes 261 | self.dmaIn.transfer(self.cmaBuffer1) 262 | if hasattr(src, 'physical_address') : 263 | self.dmaOut.transfer(src) 264 | else: 265 | self.cmaBuffer0.nbytes = src.nbytes 266 | self.copyNto(self.cmaBuffer0,src,src.nbytes) 267 | self.dmaOut.transfer(self.cmaBuffer0) 268 | self.dmaIn.wait() 269 | ret = np.ndarray(src.shape,src.dtype) 270 | self.copyNto(ret,self.cmaBuffer1,ret.nbytes) 271 | return ret 272 | 273 | def filter2D(self, src, dst): 274 | if dst is None : 275 | self.cmaBuffer1.nbytes = src.nbytes 276 | elif hasattr(src, 'physical_address') and hasattr(dst, 'physical_address') : 277 | self.dmaIn.transfer(dst) 278 | self.dmaOut.transfer(src) 279 | self.dmaIn.wait() 280 | return dst 281 | if hasattr(src, 'physical_address') : 282 | self.dmaIn.transfer(self.cmaBuffer1) 283 | self.dmaOut.transfer(src) 284 | self.dmaIn.wait() 285 | else:#pipeline the copy to contiguous memory and filter calculation in hardware 286 | if src.nbytes < 184800: #440x420 287 | self.partitions = 1 288 | elif src.nbytes < 180000: #600x300 289 | self.partitions = 2 290 | elif src.nbytes < 231200: #680x340 291 | self.partitions = 4 292 | else : 293 | self.partitions = 8 294 | self.cmaBuffer1.nbytes = src.nbytes 295 | self.dmaIn.transfer(self.cmaBuffer1) 296 | chunks_len = int(src.nbytes / (self.partitions)) 297 | self.cmaBuffer0.nbytes = chunks_len 298 | self.cmaBuffer2.nbytes = chunks_len 299 | self.copyNto(src,self.cmaBuffer0,chunks_len) 300 | for i in range(1,self.partitions): 301 | if i % 2 == 1: 302 | while not self.dmaOut.idle and not self.dmaOut._first_transfer: 303 | pass 304 | self.dmaOut.transfer(self.cmaBuffer0) 305 | self.copyNtoOff(src ,self.cmaBuffer2,chunks_len, i*chunks_len, 0) 306 | else: 307 | while not self.dmaOut.idle and not self.dmaOut._first_transfer: 308 | pass 309 | self.dmaOut.transfer(self.cmaBuffer2) 310 | self.copyNtoOff(src ,self.cmaBuffer0,chunks_len, i*chunks_len, 0) 311 | while not self.dmaOut.idle and not self.dmaOut._first_transfer: 312 | pass 313 | self.dmaOut.transfer(self.cmaBuffer2) 314 | rest = src.nbytes % self.partitions 315 | if rest != 0: #cleanup any remaining data and send it to HW 316 | self.copyNtoOff(src ,self.cmaBuffer0,chunks_len, self.partitions*chunks_len, 0) 317 | while not self.dmaOut.idle and not self.dmaOut._first_transfer: 318 | pass 319 | self.dmaOut.transfer(self.cmaBuffer0) 320 | self.dmaIn.wait() 321 | ret = np.ndarray(src.shape,src.dtype) 322 | self.copyNto(ret,self.cmaBuffer1,ret.nbytes) 323 | return ret 324 | 325 | def floatToFixed(self, f, total_bits, fract_bits): 326 | """convert float f to a signed fixed point with #total_bits and #frac_bits after the point""" 327 | fix = int((abs(f) * (1 << fract_bits))) 328 | if(f < 0): 329 | fix += 1 << total_bits-1 330 | return fix 331 | 332 | def erodeDilateKernel(self, src, kernel, dst, iterations, mode, filter): 333 | filter.mode = mode 334 | filter.rows = src.shape[0] 335 | filter.columns = src.shape[1] 336 | if hasattr(src, 'physical_address') and hasattr(dst, 'physical_address') : 337 | filter.start() 338 | if iterations > 1: 339 | self.dmaIn.transfer(self.cmaBuffer1) 340 | else: 341 | self.dmaIn.transfer(dst) 342 | self.dmaOut.transfer(src) 343 | self.dmaIn.wait() 344 | self.cmaBuffer2.nbytes = src.nbytes #buffer = self.xlnk.cma_array(src.shape, dtype=np.uint8) 345 | for i in range(2, iterations+1): 346 | filter.start() 347 | if i % 2 == 0: 348 | self.dmaIn.transfer(self.cmaBuffer2) 349 | if i != iterations: #avoid copy after last iteration 350 | self.dmaOut.transfer(self.cmaBuffer1) 351 | else: 352 | self.dmaOut.transfer(dst) 353 | else: 354 | self.dmaIn.transfer(self.cmaBuffer1) 355 | if i != iterations: 356 | self.dmaOut.transfer(self.cmaBuffer2) 357 | else: 358 | self.dmaOut.transfer(dst) 359 | self.dmaIn.wait() 360 | return dst 361 | self.cmaBuffer0.nbytes = src.nbytes 362 | self.cmaBuffer1.nbytes = src.nbytes 363 | filter.start() 364 | self.dmaIn.transfer(self.cmaBuffer1) 365 | if hasattr(src, 'physical_address') : 366 | self.dmaOut.transfer(src) 367 | else: 368 | self.copyNto(self.cmaBuffer0,src,src.nbytes) #np.copyto(srcBuffer,src) 369 | self.dmaOut.transfer(self.cmaBuffer0) 370 | self.dmaIn.wait() 371 | self.cmaBuffer2.nbytes = src.nbytes #buffer = self.xlnk.cma_array(src.shape, dtype=np.uint8) 372 | for i in range(2, iterations+1): 373 | filter.start() 374 | if i % 2 == 0: 375 | self.dmaIn.transfer(self.cmaBuffer2) 376 | self.dmaOut.transfer(self.cmaBuffer1) 377 | else: 378 | self.dmaIn.transfer(self.cmaBuffer1) 379 | self.dmaOut.transfer(self.cmaBuffer2) 380 | self.dmaIn.wait() 381 | ret = np.ndarray(src.shape,src.dtype) 382 | if iterations % 2 == 1: 383 | self.copyNto(ret,self.cmaBuffer1,ret.nbytes) 384 | else: 385 | self.copyNto(ret,self.cmaBuffer2,ret.nbytes) 386 | return ret 387 | 388 | '''def cornerHarris(self, src, k, dst): 389 | self.img_filters.select_filter(5) 390 | self.cornerHarrisIP.rows = src.shape[0] 391 | self.cornerHarrisIP.columns = src.shape[1] 392 | self.cornerHarrisIP.start() 393 | if hasattr(src, 'physical_address') and hasattr(dst, 'physical_address') and (dst.nbytes == src.nbytes*4): 394 | self.dmaIn.transfer(dst) 395 | self.dmaOut.transfer(src) 396 | self.dmaIn.wait() 397 | return dst 398 | 399 | self.cmaBuffer2.nbytes = src.nbytes*4 400 | self.dmaIn.transfer(self.cmaBuffer2) 401 | if hasattr(src, 'physical_address') : 402 | self.dmaOut.transfer(src) 403 | else: 404 | self.cmaBuffer0.nbytes = src.nbytes 405 | self.copyNto(self.cmaBuffer0,src,src.nbytes) 406 | self.dmaOut.transfer(self.cmaBuffer0) 407 | self.dmaIn.wait() 408 | ret = np.ndarray(src.shape,np.float32) 409 | self.copyNto(ret,self.cmaBuffer2,ret.nbytes) 410 | return ret''' 411 | 412 | def copyNto(self,dst,src,N): 413 | dstPtr = self.ffi.cast("uint8_t *", self.ffi.from_buffer(dst)) 414 | srcPtr = self.ffi.cast("uint8_t *", self.ffi.from_buffer(src)) 415 | self.ffi.memmove(dstPtr, srcPtr, N) 416 | 417 | def copyNtoOff(self,dst,src,N,dstOffset,srcOffset): 418 | dstPtr = self.ffi.cast("uint8_t *", self.ffi.from_buffer(dst)) 419 | srcPtr = self.ffi.cast("uint8_t *", self.ffi.from_buffer(src)) 420 | dstPtr += dstOffset 421 | srcPtr += srcOffset 422 | self.ffi.memmove(dstPtr, srcPtr, N) 423 | 424 | class ContiguousArrayCv2pynq(ContiguousArray): 425 | def init(self,cmaArray): 426 | self._nbytes = cmaArray.nbytes 427 | self.physical_address = cmaArray.physical_address 428 | self.cacheable = cmaArray.cacheable 429 | # overwrite access to nbytes with own function 430 | @property 431 | def nbytes(self): 432 | return self._nbytes 433 | 434 | @nbytes.setter 435 | def nbytes(self, value): 436 | self._nbytes = value 437 | 438 | 439 | class cv2pynqDiverImageFilters(DefaultHierarchy): 440 | def __init__(self, description): 441 | super().__init__(description) 442 | self.intc1 = MMIO(0x43C10000, 0x10000)#get axis_interconnect_1 443 | self.intc2 = MMIO(0x43C20000, 0x10000)#get axis_interconnect_2 444 | self.filter = 1 445 | self.intc1.write(0x40 + 0*4, 0x80000000)#disable master0 446 | self.intc1.write(0x40 + 1*4, 0x00000000)#select slave0 for master1 447 | self.intc1.write(0x40 + 2*4, 0x80000000)#disable master2 448 | self.intc1.write(0x40 + 3*4, 0x80000000)#disable master3 449 | self.intc1.write(0x40 + 4*4, 0x80000000)#disable master4 450 | self.intc1.write(0x40 + 5*4, 0x80000000)#disable master5 451 | self.intc2.write(0x40, self.filter)#select slave# for master0 452 | self.intc1.write(0x00, 0x2)#reset interconnect 1 453 | self.intc2.write(0x00, 0x2)#reset interconnect 2 454 | 455 | @staticmethod 456 | def checkhierarchy(description): 457 | if 'axi_dma_0' in description['ip'] \ 458 | and 'axis_interconnect_1' in description['ip'] \ 459 | and 'axis_interconnect_2' in description['ip'] \ 460 | and 'canny_edge_0' in description['ip'] \ 461 | and 'filter2D_hls_0' in description['ip'] \ 462 | and 'filter2D_f_0' in description['ip'] \ 463 | and 'erode_hls_0' in description['ip'] \ 464 | and 'dilate_hls_0' in description['ip'] \ 465 | and 'filter2D_hls_5_0' in description['ip']: 466 | return True 467 | return False 468 | 469 | def select_filter(self, filter): 470 | if not self.filter == filter: 471 | self.intc1.write(0x40 + self.filter*4, 0x80000000)#disable old master 472 | self.intc1.write(0x40 + filter*4, 0x00000000)#select slave0 for new master 473 | self.intc2.write(0x40, filter)#select new slave for master0 474 | self.intc1.write(0x00, 0x2)#reset interconnect 1 475 | self.intc2.write(0x00, 0x2)#reset interconnect 2 476 | self.filter = filter 477 | 478 | 479 | class cv2pynqDriverFilter2D(DefaultIP): 480 | def __init__(self, description): 481 | super().__init__(description=description) 482 | self.reset() 483 | 484 | bindto = ['xilinx.com:hls:filter2D_hls:1.0'] 485 | 486 | def start(self): 487 | self.write(0x00, 0x01) 488 | 489 | def auto_restart(self): 490 | self.write(0x00, 0x81) 491 | 492 | def reset(self): 493 | self.rows_value = -1 494 | self.rows = 0 495 | self.columns_value = -1 496 | self.columns = 0 497 | self.channels_value = -1 498 | self.channels = 1 499 | self.mode_value = -1 500 | self.mode = 0 501 | self.r1_value = -1 502 | self.r1 = 0 503 | self.r2_value = -1 504 | self.r2 = 0 505 | self.r3_value = -1 506 | self.r3 = 0 507 | 508 | @property 509 | def rows(self): 510 | return self.read(0x14) 511 | @rows.setter 512 | def rows(self, value): 513 | if not self.rows_value == value: 514 | self.write(0x14, value) 515 | self.rows_value = value 516 | 517 | @property 518 | def columns(self): 519 | return self.read(0x1c) 520 | @columns.setter 521 | def columns(self, value): 522 | if not self.columns_value == value: 523 | self.write(0x1c, value) 524 | self.columns_value = value 525 | 526 | @property 527 | def channels(self): 528 | return self.read(0x24) 529 | @channels.setter 530 | def channels(self, value): 531 | if not self.channels_value == value: 532 | self.write(0x24, value) 533 | self.channels_value = value 534 | 535 | @property 536 | def mode(self): 537 | return self.read(0x2c) 538 | @mode.setter 539 | def mode(self, value): 540 | if not self.mode_value == value: 541 | self.write(0x2c, value) 542 | self.mode_value = value 543 | 544 | @property 545 | def r1(self): 546 | return self.read(0x34) 547 | @r1.setter 548 | def r1(self, value): 549 | if not self.r1_value == value: 550 | self.write(0x34, value) 551 | self.mode_value = value 552 | 553 | @property 554 | def r2(self): 555 | return self.read(0x3c) 556 | @r2.setter 557 | def r2(self, value): 558 | if not self.r2_value == value: 559 | self.write(0x3c, value) 560 | self.mode_value = value 561 | 562 | @property 563 | def r3(self): 564 | return self.read(0x44) 565 | @r3.setter 566 | def r3(self, value): 567 | if not self.r3_value == value: 568 | self.write(0x44, value) 569 | self.mode_value = value 570 | 571 | class cv2pynqDriverFilter2D_5(DefaultIP): 572 | def __init__(self, description): 573 | super().__init__(description=description) 574 | self.reset() 575 | 576 | bindto = ['xilinx.com:hls:filter2D_hls_5:1.0'] 577 | 578 | def start(self): 579 | self.write(0x00, 0x01) 580 | 581 | def auto_restart(self): 582 | self.write(0x00, 0x81) 583 | 584 | def reset(self): 585 | self.rows_value = -1 586 | self.rows = 0 587 | self.columns_value = -1 588 | self.columns = 0 589 | self.par_V_value = bytes([0,0,0,0]) 590 | self.par_V = 0 591 | 592 | @property 593 | def rows(self): 594 | return self.read(0x14) 595 | @rows.setter 596 | def rows(self, value): 597 | if not self.rows_value == value: 598 | self.write(0x14, value) 599 | self.rows_value = value 600 | 601 | @property 602 | def columns(self): 603 | return self.read(0x1c) 604 | @columns.setter 605 | def columns(self, value): 606 | if not self.columns_value == value: 607 | self.write(0x1c, value) 608 | self.columns_value = value 609 | 610 | @property 611 | def par_V(self): 612 | return self.read(0x40) 613 | @par_V.setter 614 | def par_V(self, value): 615 | if not self.par_V_value == value: 616 | self.write(0x40, value) 617 | self.par_V_value = value 618 | 619 | class cv2pynqDriverFilter2D_f(DefaultIP): 620 | def __init__(self, description): 621 | super().__init__(description=description) 622 | self.reset() 623 | 624 | bindto = ['xilinx.com:hls:filter2D_f:1.0'] 625 | K_FP_W = 25 #kernel fixed point: length in bits 626 | K_FP_F = 23 #kernel fixed point: The number of bits used to represent the number of bits behind the decimal point 627 | def start(self): 628 | self.write(0x00, 0x01) 629 | 630 | def auto_restart(self): 631 | self.write(0x00, 0x81) 632 | 633 | def reset(self): 634 | self.rows_value = -1 635 | self.rows = 0 636 | self.columns_value = -1 637 | self.columns = 0 638 | self.channels_value = -1 639 | self.channels = 1 640 | self.mode_value = -1 641 | self.mode = 0 642 | self.r11_value = -1 643 | self.r11 = 0 644 | self.r12_value = -1 645 | self.r12 = 0 646 | self.r13_value = -1 647 | self.r13 = 0 648 | self.r21_value = -1 649 | self.r21 = 0 650 | self.r22_value = -1 651 | self.r22 = 0 652 | self.r23_value = -1 653 | self.r23 = 0 654 | self.r31_value = -1 655 | self.r31 = 0 656 | self.r32_value = -1 657 | self.r32 = 0 658 | self.r33_value = -1 659 | self.r33 = 0 660 | 661 | @property 662 | def rows(self): 663 | return self.read(0x14) 664 | @rows.setter 665 | def rows(self, value): 666 | if not self.rows_value == value: 667 | self.write(0x14, value) 668 | self.rows_value = value 669 | 670 | @property 671 | def columns(self): 672 | return self.read(0x1c) 673 | @columns.setter 674 | def columns(self, value): 675 | if not self.columns_value == value: 676 | self.write(0x1c, value) 677 | self.columns_value = value 678 | 679 | @property 680 | def channels(self): 681 | return self.read(0x24) 682 | @channels.setter 683 | def channels(self, value): 684 | if not self.channels_value == value: 685 | self.write(0x24, value) 686 | self.channels_value = value 687 | 688 | @property 689 | def mode(self): 690 | return self.read(0x2c) 691 | @mode.setter 692 | def mode(self, value): 693 | if not self.mode_value == value: 694 | self.write(0x2c, value) 695 | self.mode_value = value 696 | 697 | @property 698 | def r11(self): 699 | return self.read(0x34) 700 | @r11.setter 701 | def r11(self, value): 702 | if not self.r11_value == value: 703 | self.write(0x34, value) 704 | self.mode_value = value 705 | 706 | @property 707 | def r12(self): 708 | return self.read(0x3c) 709 | @r12.setter 710 | def r12(self, value): 711 | if not self.r12_value == value: 712 | self.write(0x3c, value) 713 | self.mode_value = value 714 | 715 | @property 716 | def r13(self): 717 | return self.read(0x44) 718 | @r13.setter 719 | def r13(self, value): 720 | if not self.r13_value == value: 721 | self.write(0x44, value) 722 | self.mode_value = value 723 | 724 | @property 725 | def r21(self): 726 | return self.read(0x4c) 727 | @r21.setter 728 | def r21(self, value): 729 | if not self.r21_value == value: 730 | self.write(0x4c, value) 731 | self.mode_value = value 732 | 733 | @property 734 | def r22(self): 735 | return self.read(0x54) 736 | @r22.setter 737 | def r22(self, value): 738 | if not self.r22_value == value: 739 | self.write(0x54, value) 740 | self.mode_value = value 741 | 742 | @property 743 | def r23(self): 744 | return self.read(0x5c) 745 | @r23.setter 746 | def r23(self, value): 747 | if not self.r23_value == value: 748 | self.write(0x5c, value) 749 | self.mode_value = value 750 | 751 | @property 752 | def r31(self): 753 | return self.read(0x64) 754 | @r31.setter 755 | def r31(self, value): 756 | if not self.r31_value == value: 757 | self.write(0x64, value) 758 | self.mode_value = value 759 | 760 | @property 761 | def r32(self): 762 | return self.read(0x6c) 763 | @r32.setter 764 | def r32(self, value): 765 | if not self.r32_value == value: 766 | self.write(0x6c, value) 767 | self.mode_value = value 768 | 769 | @property 770 | def r33(self): 771 | return self.read(0x74) 772 | @r33.setter 773 | def r33(self, value): 774 | if not self.r33_value == value: 775 | self.write(0x74, value) 776 | self.mode_value = value 777 | 778 | class cv2pynqDriverCanny(DefaultIP): 779 | def __init__(self, description): 780 | super().__init__(description=description) 781 | self.reset() 782 | 783 | bindto = ['xilinx.com:hls:canny_edge:1.0'] 784 | 785 | def start(self): 786 | self.write(0x00, 0x01) 787 | 788 | def auto_restart(self): 789 | self.write(0x00, 0x81) 790 | 791 | def reset(self): 792 | self.rows_value = -1 793 | self.rows = 0 794 | self.columns_value = -1 795 | self.columns = 0 796 | self.threshold1_value = -1 797 | self.threshold1 = 0 798 | self.threshold2_value = -1 799 | self.threshold2 = 0 800 | 801 | @property 802 | def rows(self): 803 | return self.read(0x14) 804 | @rows.setter 805 | def rows(self, value): 806 | if not self.rows_value == value: 807 | self.write(0x14, value) 808 | self.rows_value = value 809 | 810 | @property 811 | def columns(self): 812 | return self.read(0x1c) 813 | @columns.setter 814 | def columns(self, value): 815 | if not self.columns_value == value: 816 | self.write(0x1c, value) 817 | self.columns_value = value 818 | 819 | @property 820 | def threshold1(self): 821 | return self.read(0x24) 822 | @threshold1.setter 823 | def threshold1(self, value): 824 | if not self.threshold1_value == value: 825 | self.write(0x24, value) 826 | self.threshold1_value = value 827 | 828 | @property 829 | def threshold2(self): 830 | return self.read(0x2c) 831 | @threshold2.setter 832 | def threshold2(self, value): 833 | if not self.threshold2_value == value: 834 | self.write(0x2c, value) 835 | self.threshold2_value = value 836 | 837 | class cv2pynqDriverErode(DefaultIP): 838 | def __init__(self, description): 839 | super().__init__(description=description) 840 | self.reset() 841 | 842 | bindto = ['xilinx.com:hls:erode_hls:1.0'] 843 | 844 | def start(self): 845 | self.write(0x00, 0x01) 846 | 847 | def reset(self): 848 | self.rows_value = -1 849 | self.rows = 0 850 | self.columns_value = -1 851 | self.columns = 0 852 | self.channels_value = -1 853 | self.channels = 1 854 | self.mode_value = -1 855 | self.mode = 0 856 | 857 | @property 858 | def rows(self): 859 | return self.read(0x14) 860 | @rows.setter 861 | def rows(self, value): 862 | if not self.rows_value == value: 863 | self.write(0x14, value) 864 | self.rows_value = value 865 | 866 | @property 867 | def columns(self): 868 | return self.read(0x1c) 869 | @columns.setter 870 | def columns(self, value): 871 | if not self.columns_value == value: 872 | self.write(0x1c, value) 873 | self.columns_value = value 874 | 875 | @property 876 | def channels(self): 877 | return self.read(0x24) 878 | @channels.setter 879 | def channels(self, value): 880 | if not self.channels_value == value: 881 | self.write(0x24, value) 882 | self.channels_value = value 883 | 884 | @property 885 | def mode(self): 886 | return self.read(0x2c) 887 | @mode.setter 888 | def mode(self, value): 889 | if not self.mode_value == value: 890 | self.write(0x2c, value) 891 | self.mode_value = value 892 | 893 | class cv2pynqDriverDilate(DefaultIP): 894 | def __init__(self, description): 895 | super().__init__(description=description) 896 | self.reset() 897 | 898 | bindto = ['xilinx.com:hls:dilate_hls:1.0'] 899 | 900 | def start(self): 901 | self.write(0x00, 0x01) 902 | 903 | def reset(self): 904 | self.rows_value = -1 905 | self.rows = 0 906 | self.columns_value = -1 907 | self.columns = 0 908 | self.channels_value = -1 909 | self.channels = 1 910 | self.mode_value = -1 911 | self.mode = 0 912 | 913 | @property 914 | def rows(self): 915 | return self.read(0x14) 916 | @rows.setter 917 | def rows(self, value): 918 | if not self.rows_value == value: 919 | self.write(0x14, value) 920 | self.rows_value = value 921 | 922 | @property 923 | def columns(self): 924 | return self.read(0x1c) 925 | @columns.setter 926 | def columns(self, value): 927 | if not self.columns_value == value: 928 | self.write(0x1c, value) 929 | self.columns_value = value 930 | 931 | @property 932 | def channels(self): 933 | return self.read(0x24) 934 | @channels.setter 935 | def channels(self, value): 936 | if not self.channels_value == value: 937 | self.write(0x24, value) 938 | self.channels_value = value 939 | 940 | @property 941 | def mode(self): 942 | return self.read(0x2c) 943 | @mode.setter 944 | def mode(self, value): 945 | if not self.mode_value == value: 946 | self.write(0x2c, value) 947 | self.mode_value = value 948 | 949 | class cv2pynqDriverCornerHarris(DefaultIP): 950 | def __init__(self, description): 951 | super().__init__(description=description) 952 | self.reset() 953 | bindto = ['xilinx.com:hls:CornerHarris_hls:1.0'] 954 | 955 | def start(self): 956 | self.write(0x00, 0x01) 957 | 958 | def reset(self): 959 | self.rows_value = -1 960 | self.rows = 0 961 | self.columns_value = -1 962 | self.columns = 0 963 | self.k_value_check = np.ndarray(1,np.float32) 964 | self.k_value = np.ndarray(1,np.float32) 965 | self.k_value[0] = -1 966 | self.k = 0 967 | 968 | 969 | @property 970 | def rows(self): 971 | return self.read(0x14) 972 | @rows.setter 973 | def rows(self, value): 974 | if not self.rows_value == value: 975 | self.write(0x14, value) 976 | self.rows_value = value 977 | 978 | @property 979 | def columns(self): 980 | return self.read(0x1c) 981 | @columns.setter 982 | def columns(self, value): 983 | if not self.columns_value == value: 984 | self.write(0x1c, value) 985 | self.columns_value = value 986 | 987 | @property 988 | def k(self): 989 | return self.read(0x34) 990 | @k.setter 991 | def k(self, value): 992 | self.k_value_check[0] = value 993 | if not self.k_value[0] == self.k_value_check[0]: 994 | self.k_value[0] = self.k_value_check[0] 995 | self.write(0x34, int(self.k_value[0].view(dtype=np.int32))) -------------------------------------------------------------------------------- /cv2pynq/bitstreams/cv2pynq03.tcl: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # This is a generated script based on design: design_1 4 | # 5 | # Though there are limitations about the generated script, 6 | # the main purpose of this utility is to make learning 7 | # IP Integrator Tcl commands easier. 8 | ################################################################ 9 | 10 | namespace eval _tcl { 11 | proc get_script_folder {} { 12 | set script_path [file normalize [info script]] 13 | set script_folder [file dirname $script_path] 14 | return $script_folder 15 | } 16 | } 17 | variable script_folder 18 | set script_folder [_tcl::get_script_folder] 19 | 20 | ################################################################ 21 | # Check if script is running in correct Vivado version. 22 | ################################################################ 23 | set scripts_vivado_version 2017.4 24 | set current_vivado_version [version -short] 25 | 26 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 27 | puts "" 28 | catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} 29 | 30 | return 1 31 | } 32 | 33 | ################################################################ 34 | # START 35 | ################################################################ 36 | 37 | # To test this script, run the following commands from Vivado Tcl console: 38 | # source design_1_script.tcl 39 | 40 | # If there is no project opened, this script will create a 41 | # project, but make sure you do not have an existing project 42 | # <./myproj/project_1.xpr> in the current working folder. 43 | 44 | set list_projs [get_projects -quiet] 45 | if { $list_projs eq "" } { 46 | create_project project_1 myproj -part xc7z020clg400-1 47 | set_property BOARD_PART www.digilentinc.com:pynq-z1:part0:1.0 [current_project] 48 | } 49 | 50 | 51 | # CHANGE DESIGN NAME HERE 52 | variable design_name 53 | set design_name design_1 54 | 55 | # If you do not already have an existing IP Integrator design open, 56 | # you can create a design using the following command: 57 | # create_bd_design $design_name 58 | 59 | # Creating design if needed 60 | set errMsg "" 61 | set nRet 0 62 | 63 | set cur_design [current_bd_design -quiet] 64 | set list_cells [get_bd_cells -quiet] 65 | 66 | if { ${design_name} eq "" } { 67 | # USE CASES: 68 | # 1) Design_name not set 69 | 70 | set errMsg "Please set the variable to a non-empty value." 71 | set nRet 1 72 | 73 | } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { 74 | # USE CASES: 75 | # 2): Current design opened AND is empty AND names same. 76 | # 3): Current design opened AND is empty AND names diff; design_name NOT in project. 77 | # 4): Current design opened AND is empty AND names diff; design_name exists in project. 78 | 79 | if { $cur_design ne $design_name } { 80 | common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." 81 | set design_name [get_property NAME $cur_design] 82 | } 83 | common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." 84 | 85 | } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { 86 | # USE CASES: 87 | # 5) Current design opened AND has components AND same names. 88 | 89 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 90 | set nRet 1 91 | } elseif { [get_files -quiet ${design_name}.bd] ne "" } { 92 | # USE CASES: 93 | # 6) Current opened design, has components, but diff names, design_name exists in project. 94 | # 7) No opened design, design_name exists in project. 95 | 96 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 97 | set nRet 2 98 | 99 | } else { 100 | # USE CASES: 101 | # 8) No opened design, design_name not in project. 102 | # 9) Current opened design, has components, but diff names, design_name not in project. 103 | 104 | common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." 105 | 106 | create_bd_design $design_name 107 | 108 | common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." 109 | current_bd_design $design_name 110 | 111 | } 112 | 113 | common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." 114 | 115 | if { $nRet != 0 } { 116 | catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} 117 | return $nRet 118 | } 119 | 120 | set bCheckIPsPassed 1 121 | ################################################################## 122 | # CHECK IPs 123 | ################################################################## 124 | set bCheckIPs 1 125 | if { $bCheckIPs == 1 } { 126 | set list_check_ips "\ 127 | xilinx.com:ip:axi_intc:4.1\ 128 | xilinx.com:ip:proc_sys_reset:5.0\ 129 | xilinx.com:ip:processing_system7:5.5\ 130 | xilinx.com:ip:xlconcat:2.1\ 131 | xilinx.com:ip:axi_dma:7.1\ 132 | xilinx.com:hls:canny_edge:1.0\ 133 | xilinx.com:hls:dilate_hls:1.0\ 134 | xilinx.com:hls:erode_hls:1.0\ 135 | xilinx.com:hls:filter2D_f:1.0\ 136 | xilinx.com:hls:filter2D_hls:1.0\ 137 | xilinx.com:hls:filter2D_hls_5:1.0\ 138 | xilinx.com:ip:xlconstant:1.1\ 139 | xilinx.com:ip:axi_vdma:6.3\ 140 | xilinx.com:ip:axis_register_slice:1.1\ 141 | xilinx.com:hls:color_convert:1.0\ 142 | xilinx.com:hls:pixel_pack:1.0\ 143 | xilinx.com:hls:pixel_unpack:1.0\ 144 | xilinx.com:ip:axi_gpio:2.0\ 145 | xilinx:user:color_swap:1.0\ 146 | digilentinc.com:ip:dvi2rgb:1.7\ 147 | xilinx.com:ip:v_vid_in_axi4s:4.0\ 148 | xilinx.com:ip:v_tc:6.1\ 149 | digilentinc.com:ip:axi_dynclk:1.0\ 150 | digilentinc.com:ip:rgb2dvi:1.2\ 151 | xilinx.com:ip:v_axi4s_vid_out:4.0\ 152 | " 153 | 154 | set list_ips_missing "" 155 | common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." 156 | 157 | foreach ip_vlnv $list_check_ips { 158 | set ip_obj [get_ipdefs -all $ip_vlnv] 159 | if { $ip_obj eq "" } { 160 | lappend list_ips_missing $ip_vlnv 161 | } 162 | } 163 | 164 | if { $list_ips_missing ne "" } { 165 | catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } 166 | set bCheckIPsPassed 0 167 | } 168 | 169 | } 170 | 171 | if { $bCheckIPsPassed != 1 } { 172 | common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." 173 | return 3 174 | } 175 | 176 | ################################################################## 177 | # DESIGN PROCs 178 | ################################################################## 179 | 180 | 181 | # Hierarchical cell: frontend 182 | proc create_hier_cell_frontend_1 { parentCell nameHier } { 183 | 184 | variable script_folder 185 | 186 | if { $parentCell eq "" || $nameHier eq "" } { 187 | catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_frontend_1() - Empty argument(s)!"} 188 | return 189 | } 190 | 191 | # Get object for parentCell 192 | set parentObj [get_bd_cells $parentCell] 193 | if { $parentObj == "" } { 194 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 195 | return 196 | } 197 | 198 | # Make sure parentObj is hier blk 199 | set parentType [get_property TYPE $parentObj] 200 | if { $parentType ne "hier" } { 201 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 202 | return 203 | } 204 | 205 | # Save current instance; Restore later 206 | set oldCurInst [current_bd_instance .] 207 | 208 | # Set parent object as current 209 | current_bd_instance $parentObj 210 | 211 | # Create cell and set as current instance 212 | set hier_obj [create_bd_cell -type hier $nameHier] 213 | current_bd_instance $hier_obj 214 | 215 | # Create interface pins 216 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXILite 217 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXILite 218 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S04_AXILite 219 | create_bd_intf_pin -mode Master -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS_out 220 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 video_in 221 | 222 | # Create pins 223 | create_bd_pin -dir I -type clk clk_100M 224 | create_bd_pin -dir I -type clk clk_142M 225 | create_bd_pin -dir O -from 0 -to 0 hdmi_out_hpd 226 | create_bd_pin -dir O -type intr hdmi_out_hpd_irq 227 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk100M 228 | create_bd_pin -dir O -type intr vtc_out_irq 229 | 230 | # Create instance: axi_dynclk, and set properties 231 | set axi_dynclk [ create_bd_cell -type ip -vlnv digilentinc.com:ip:axi_dynclk:1.0 axi_dynclk ] 232 | 233 | set_property -dict [ list \ 234 | CONFIG.SUPPORTS_NARROW_BURST {0} \ 235 | CONFIG.NUM_READ_OUTSTANDING {1} \ 236 | CONFIG.NUM_WRITE_OUTSTANDING {1} \ 237 | CONFIG.MAX_BURST_LENGTH {1} \ 238 | ] [get_bd_intf_pins /video/hdmi_out/frontend/axi_dynclk/s00_axi] 239 | 240 | # Create instance: color_swap_0, and set properties 241 | set color_swap_0 [ create_bd_cell -type ip -vlnv xilinx:user:color_swap:1.0 color_swap_0 ] 242 | 243 | # Create instance: hdmi_out_hpd_video, and set properties 244 | set hdmi_out_hpd_video [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 hdmi_out_hpd_video ] 245 | set_property -dict [ list \ 246 | CONFIG.C_ALL_OUTPUTS {1} \ 247 | CONFIG.C_GPIO_WIDTH {1} \ 248 | CONFIG.C_INTERRUPT_PRESENT {1} \ 249 | ] $hdmi_out_hpd_video 250 | 251 | # Create instance: rgb2dvi_0, and set properties 252 | set rgb2dvi_0 [ create_bd_cell -type ip -vlnv digilentinc.com:ip:rgb2dvi:1.2 rgb2dvi_0 ] 253 | set_property -dict [ list \ 254 | CONFIG.kClkRange {2} \ 255 | CONFIG.kGenerateSerialClk {false} \ 256 | CONFIG.kRstActiveHigh {false} \ 257 | ] $rgb2dvi_0 258 | 259 | # Create instance: v_axi4s_vid_out_0, and set properties 260 | set v_axi4s_vid_out_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_axi4s_vid_out:4.0 v_axi4s_vid_out_0 ] 261 | set_property -dict [ list \ 262 | CONFIG.C_ADDR_WIDTH {11} \ 263 | CONFIG.C_HAS_ASYNC_CLK {1} \ 264 | CONFIG.C_HYSTERESIS_LEVEL {1024} \ 265 | CONFIG.C_VTG_MASTER_SLAVE {1} \ 266 | ] $v_axi4s_vid_out_0 267 | 268 | # Create instance: vtc_out, and set properties 269 | set vtc_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_tc:6.1 vtc_out ] 270 | set_property -dict [ list \ 271 | CONFIG.enable_detection {false} \ 272 | ] $vtc_out 273 | 274 | # Create interface connections 275 | connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins TMDS_out] [get_bd_intf_pins rgb2dvi_0/TMDS] 276 | connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S02_AXILite] [get_bd_intf_pins vtc_out/ctrl] 277 | connect_bd_intf_net -intf_net color_swap_0_pixel_output [get_bd_intf_pins color_swap_0/pixel_output] [get_bd_intf_pins rgb2dvi_0/RGB] 278 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M06_AXI [get_bd_intf_pins S00_AXILite] [get_bd_intf_pins hdmi_out_hpd_video/S_AXI] 279 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M08_AXI [get_bd_intf_pins S04_AXILite] [get_bd_intf_pins axi_dynclk/s00_axi] 280 | connect_bd_intf_net -intf_net v_axi4s_vid_out_0_vid_io_out [get_bd_intf_pins color_swap_0/pixel_input] [get_bd_intf_pins v_axi4s_vid_out_0/vid_io_out] 281 | connect_bd_intf_net -intf_net v_tc_0_vtiming_out [get_bd_intf_pins v_axi4s_vid_out_0/vtiming_in] [get_bd_intf_pins vtc_out/vtiming_out] 282 | connect_bd_intf_net -intf_net video_in_1 [get_bd_intf_pins video_in] [get_bd_intf_pins v_axi4s_vid_out_0/video_in] 283 | 284 | # Create port connections 285 | connect_bd_net -net Net [get_bd_pins clk_100M] [get_bd_pins axi_dynclk/REF_CLK_I] [get_bd_pins axi_dynclk/s00_axi_aclk] [get_bd_pins hdmi_out_hpd_video/s_axi_aclk] [get_bd_pins vtc_out/s_axi_aclk] 286 | connect_bd_net -net Net1 [get_bd_pins periph_resetn_clk100M] [get_bd_pins axi_dynclk/s00_axi_aresetn] [get_bd_pins hdmi_out_hpd_video/s_axi_aresetn] [get_bd_pins vtc_out/s_axi_aresetn] 287 | connect_bd_net -net aclk_1 [get_bd_pins clk_142M] [get_bd_pins v_axi4s_vid_out_0/aclk] 288 | connect_bd_net -net axi_dynclk_0_LOCKED_O [get_bd_pins axi_dynclk/LOCKED_O] [get_bd_pins rgb2dvi_0/aRst_n] 289 | connect_bd_net -net axi_dynclk_0_PXL_CLK_5X_O [get_bd_pins axi_dynclk/PXL_CLK_5X_O] [get_bd_pins rgb2dvi_0/SerialClk] 290 | connect_bd_net -net axi_dynclk_0_PXL_CLK_O [get_bd_pins axi_dynclk/PXL_CLK_O] [get_bd_pins rgb2dvi_0/PixelClk] [get_bd_pins v_axi4s_vid_out_0/vid_io_out_clk] [get_bd_pins vtc_out/clk] 291 | connect_bd_net -net hdmi_out_hpd_video_gpio_io_o [get_bd_pins hdmi_out_hpd] [get_bd_pins hdmi_out_hpd_video/gpio_io_o] 292 | connect_bd_net -net hdmi_out_hpd_video_ip2intc_irpt [get_bd_pins hdmi_out_hpd_irq] [get_bd_pins hdmi_out_hpd_video/ip2intc_irpt] 293 | connect_bd_net -net v_tc_0_irq [get_bd_pins vtc_out_irq] [get_bd_pins vtc_out/irq] 294 | 295 | # Restore current instance 296 | current_bd_instance $oldCurInst 297 | } 298 | 299 | # Hierarchical cell: frontend 300 | proc create_hier_cell_frontend { parentCell nameHier } { 301 | 302 | variable script_folder 303 | 304 | if { $parentCell eq "" || $nameHier eq "" } { 305 | catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_frontend() - Empty argument(s)!"} 306 | return 307 | } 308 | 309 | # Get object for parentCell 310 | set parentObj [get_bd_cells $parentCell] 311 | if { $parentObj == "" } { 312 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 313 | return 314 | } 315 | 316 | # Make sure parentObj is hier blk 317 | set parentType [get_property TYPE $parentObj] 318 | if { $parentType ne "hier" } { 319 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 320 | return 321 | } 322 | 323 | # Save current instance; Restore later 324 | set oldCurInst [current_bd_instance .] 325 | 326 | # Set parent object as current 327 | current_bd_instance $parentObj 328 | 329 | # Create cell and set as current instance 330 | set hier_obj [create_bd_cell -type hier $nameHier] 331 | current_bd_instance $hier_obj 332 | 333 | # Create interface pins 334 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 DDC 335 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXILite 336 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXILite 337 | create_bd_intf_pin -mode Slave -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS_in 338 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 video_out 339 | 340 | # Create pins 341 | create_bd_pin -dir O -type clk PixelClk 342 | create_bd_pin -dir O aPixelClkLckd 343 | create_bd_pin -dir I -type clk clk_100M 344 | create_bd_pin -dir I -type clk clk_142M 345 | create_bd_pin -dir I -type clk clk_200M 346 | create_bd_pin -dir O -from 0 -to 0 hdmi_in_hpd 347 | create_bd_pin -dir O -type intr hdmi_in_hpd_irq 348 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk100M 349 | create_bd_pin -dir I -from 0 -to 0 -type rst resetn 350 | create_bd_pin -dir I -from 0 -to 0 -type rst vid_io_in_reset 351 | create_bd_pin -dir O -type intr vtc_in_irq 352 | 353 | # Create instance: axi_gpio_hdmiin, and set properties 354 | set axi_gpio_hdmiin [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_hdmiin ] 355 | set_property -dict [ list \ 356 | CONFIG.C_ALL_INPUTS_2 {1} \ 357 | CONFIG.C_ALL_OUTPUTS {1} \ 358 | CONFIG.C_GPIO2_WIDTH {1} \ 359 | CONFIG.C_GPIO_WIDTH {1} \ 360 | CONFIG.C_INTERRUPT_PRESENT {1} \ 361 | CONFIG.C_IS_DUAL {1} \ 362 | ] $axi_gpio_hdmiin 363 | 364 | # Create instance: color_swap_0, and set properties 365 | set color_swap_0 [ create_bd_cell -type ip -vlnv xilinx:user:color_swap:1.0 color_swap_0 ] 366 | set_property -dict [ list \ 367 | CONFIG.input_format {rbg} \ 368 | CONFIG.output_format {rgb} \ 369 | ] $color_swap_0 370 | 371 | # Create instance: dvi2rgb_0, and set properties 372 | set dvi2rgb_0 [ create_bd_cell -type ip -vlnv digilentinc.com:ip:dvi2rgb:1.7 dvi2rgb_0 ] 373 | set_property -dict [ list \ 374 | CONFIG.kAddBUFG {false} \ 375 | CONFIG.kClkRange {1} \ 376 | CONFIG.kEdidFileName {720p_edid.data} \ 377 | CONFIG.kRstActiveHigh {false} \ 378 | ] $dvi2rgb_0 379 | 380 | # Create instance: v_vid_in_axi4s_0, and set properties 381 | set v_vid_in_axi4s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_vid_in_axi4s:4.0 v_vid_in_axi4s_0 ] 382 | set_property -dict [ list \ 383 | CONFIG.C_ADDR_WIDTH {12} \ 384 | CONFIG.C_HAS_ASYNC_CLK {1} \ 385 | ] $v_vid_in_axi4s_0 386 | 387 | # Create instance: vtc_in, and set properties 388 | set vtc_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_tc:6.1 vtc_in ] 389 | set_property -dict [ list \ 390 | CONFIG.HAS_INTC_IF {true} \ 391 | CONFIG.enable_generation {false} \ 392 | CONFIG.horizontal_blank_detection {false} \ 393 | CONFIG.max_lines_per_frame {2048} \ 394 | CONFIG.vertical_blank_detection {false} \ 395 | ] $vtc_in 396 | 397 | # Create interface connections 398 | connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins DDC] [get_bd_intf_pins dvi2rgb_0/DDC] 399 | connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins TMDS_in] [get_bd_intf_pins dvi2rgb_0/TMDS] 400 | connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins S02_AXILite] [get_bd_intf_pins vtc_in/ctrl] 401 | connect_bd_intf_net -intf_net color_swap_0_pixel_output [get_bd_intf_pins color_swap_0/pixel_output] [get_bd_intf_pins v_vid_in_axi4s_0/vid_io_in] 402 | connect_bd_intf_net -intf_net dvi2rgb_0_RGB [get_bd_intf_pins color_swap_0/pixel_input] [get_bd_intf_pins dvi2rgb_0/RGB] 403 | connect_bd_intf_net -intf_net hdmi_in_video_out [get_bd_intf_pins video_out] [get_bd_intf_pins v_vid_in_axi4s_0/video_out] 404 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M07_AXI [get_bd_intf_pins S00_AXILite] [get_bd_intf_pins axi_gpio_hdmiin/S_AXI] 405 | connect_bd_intf_net -intf_net v_vid_in_axi4s_0_vtiming_out [get_bd_intf_pins v_vid_in_axi4s_0/vtiming_out] [get_bd_intf_pins vtc_in/vtiming_in] 406 | 407 | # Create port connections 408 | connect_bd_net -net Net [get_bd_pins clk_100M] [get_bd_pins axi_gpio_hdmiin/s_axi_aclk] [get_bd_pins vtc_in/s_axi_aclk] 409 | connect_bd_net -net Net1 [get_bd_pins periph_resetn_clk100M] [get_bd_pins axi_gpio_hdmiin/s_axi_aresetn] [get_bd_pins dvi2rgb_0/aRst_n] [get_bd_pins vtc_in/s_axi_aresetn] 410 | connect_bd_net -net RefClk_1 [get_bd_pins clk_200M] [get_bd_pins dvi2rgb_0/RefClk] 411 | connect_bd_net -net aclk_1 [get_bd_pins clk_142M] [get_bd_pins v_vid_in_axi4s_0/aclk] 412 | connect_bd_net -net axi_gpio_video_gpio_io_o [get_bd_pins hdmi_in_hpd] [get_bd_pins axi_gpio_hdmiin/gpio_io_o] 413 | connect_bd_net -net axi_gpio_video_ip2intc_irpt [get_bd_pins hdmi_in_hpd_irq] [get_bd_pins axi_gpio_hdmiin/ip2intc_irpt] 414 | connect_bd_net -net dvi2rgb_0_PixelClk1 [get_bd_pins PixelClk] [get_bd_pins dvi2rgb_0/PixelClk] [get_bd_pins v_vid_in_axi4s_0/vid_io_in_clk] [get_bd_pins vtc_in/clk] 415 | connect_bd_net -net dvi2rgb_0_aPixelClkLckd [get_bd_pins aPixelClkLckd] [get_bd_pins axi_gpio_hdmiin/gpio2_io_i] [get_bd_pins dvi2rgb_0/aPixelClkLckd] 416 | connect_bd_net -net resetn_1 [get_bd_pins resetn] [get_bd_pins vtc_in/resetn] 417 | connect_bd_net -net v_tc_1_irq [get_bd_pins vtc_in_irq] [get_bd_pins vtc_in/irq] 418 | connect_bd_net -net vid_io_in_reset_1 [get_bd_pins vid_io_in_reset] [get_bd_pins v_vid_in_axi4s_0/vid_io_in_reset] 419 | 420 | # Restore current instance 421 | current_bd_instance $oldCurInst 422 | } 423 | 424 | # Hierarchical cell: hdmi_out 425 | proc create_hier_cell_hdmi_out { parentCell nameHier } { 426 | 427 | variable script_folder 428 | 429 | if { $parentCell eq "" || $nameHier eq "" } { 430 | catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_hdmi_out() - Empty argument(s)!"} 431 | return 432 | } 433 | 434 | # Get object for parentCell 435 | set parentObj [get_bd_cells $parentCell] 436 | if { $parentObj == "" } { 437 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 438 | return 439 | } 440 | 441 | # Make sure parentObj is hier blk 442 | set parentType [get_property TYPE $parentObj] 443 | if { $parentType ne "hier" } { 444 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 445 | return 446 | } 447 | 448 | # Save current instance; Restore later 449 | set oldCurInst [current_bd_instance .] 450 | 451 | # Set parent object as current 452 | current_bd_instance $parentObj 453 | 454 | # Create cell and set as current instance 455 | set hier_obj [create_bd_cell -type hier $nameHier] 456 | current_bd_instance $hier_obj 457 | 458 | # Create interface pins 459 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXILite 460 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXILite 461 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXILite 462 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S03_AXILite 463 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S04_AXILite 464 | create_bd_intf_pin -mode Master -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS_out 465 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 in_stream 466 | 467 | # Create pins 468 | create_bd_pin -dir I -type clk clk_100M 469 | create_bd_pin -dir I -type clk clk_142M 470 | create_bd_pin -dir O -from 0 -to 0 hdmi_out_hpd 471 | create_bd_pin -dir O -type intr hdmi_out_hpd_irq 472 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk100M 473 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk142M 474 | create_bd_pin -dir O -type intr vtc_out_irq 475 | 476 | # Create instance: axis_register_slice_0, and set properties 477 | set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] 478 | 479 | # Create instance: color_convert, and set properties 480 | set color_convert [ create_bd_cell -type ip -vlnv xilinx.com:hls:color_convert:1.0 color_convert ] 481 | 482 | # Create instance: frontend 483 | create_hier_cell_frontend_1 $hier_obj frontend 484 | 485 | # Create instance: pixel_unpack, and set properties 486 | set pixel_unpack [ create_bd_cell -type ip -vlnv xilinx.com:hls:pixel_unpack:1.0 pixel_unpack ] 487 | 488 | # Create interface connections 489 | connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins TMDS_out] [get_bd_intf_pins frontend/TMDS_out] 490 | connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S02_AXILite] [get_bd_intf_pins frontend/S02_AXILite] 491 | connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins S03_AXILite] [get_bd_intf_pins color_convert/s_axi_AXILiteS] 492 | connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins S01_AXILite] [get_bd_intf_pins pixel_unpack/s_axi_AXILiteS] 493 | connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_register_slice_0/M_AXIS] [get_bd_intf_pins color_convert/stream_in_24] 494 | connect_bd_intf_net -intf_net color_convert_stream_out_24 [get_bd_intf_pins color_convert/stream_out_24] [get_bd_intf_pins frontend/video_in] 495 | connect_bd_intf_net -intf_net in_stream_1 [get_bd_intf_pins in_stream] [get_bd_intf_pins pixel_unpack/stream_in_32] 496 | connect_bd_intf_net -intf_net pixel_unpack_stream_out_24 [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins pixel_unpack/stream_out_24] 497 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M06_AXI [get_bd_intf_pins S00_AXILite] [get_bd_intf_pins frontend/S00_AXILite] 498 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M08_AXI [get_bd_intf_pins S04_AXILite] [get_bd_intf_pins frontend/S04_AXILite] 499 | 500 | # Create port connections 501 | connect_bd_net -net Net [get_bd_pins clk_100M] [get_bd_pins frontend/clk_100M] 502 | connect_bd_net -net Net1 [get_bd_pins periph_resetn_clk100M] [get_bd_pins frontend/periph_resetn_clk100M] 503 | connect_bd_net -net aclk_1 [get_bd_pins clk_142M] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins color_convert/ap_clk] [get_bd_pins color_convert/control] [get_bd_pins frontend/clk_142M] [get_bd_pins pixel_unpack/ap_clk] [get_bd_pins pixel_unpack/control] 504 | connect_bd_net -net hdmi_out_hpd_video_gpio_io_o [get_bd_pins hdmi_out_hpd] [get_bd_pins frontend/hdmi_out_hpd] 505 | connect_bd_net -net hdmi_out_hpd_video_ip2intc_irpt [get_bd_pins hdmi_out_hpd_irq] [get_bd_pins frontend/hdmi_out_hpd_irq] 506 | connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins periph_resetn_clk142M] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins color_convert/ap_rst_n] [get_bd_pins color_convert/ap_rst_n_control] [get_bd_pins pixel_unpack/ap_rst_n] [get_bd_pins pixel_unpack/ap_rst_n_control] 507 | connect_bd_net -net v_tc_0_irq [get_bd_pins vtc_out_irq] [get_bd_pins frontend/vtc_out_irq] 508 | 509 | # Restore current instance 510 | current_bd_instance $oldCurInst 511 | } 512 | 513 | # Hierarchical cell: hdmi_in 514 | proc create_hier_cell_hdmi_in { parentCell nameHier } { 515 | 516 | variable script_folder 517 | 518 | if { $parentCell eq "" || $nameHier eq "" } { 519 | catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_hdmi_in() - Empty argument(s)!"} 520 | return 521 | } 522 | 523 | # Get object for parentCell 524 | set parentObj [get_bd_cells $parentCell] 525 | if { $parentObj == "" } { 526 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 527 | return 528 | } 529 | 530 | # Make sure parentObj is hier blk 531 | set parentType [get_property TYPE $parentObj] 532 | if { $parentType ne "hier" } { 533 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 534 | return 535 | } 536 | 537 | # Save current instance; Restore later 538 | set oldCurInst [current_bd_instance .] 539 | 540 | # Set parent object as current 541 | current_bd_instance $parentObj 542 | 543 | # Create cell and set as current instance 544 | set hier_obj [create_bd_cell -type hier $nameHier] 545 | current_bd_instance $hier_obj 546 | 547 | # Create interface pins 548 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 DDC 549 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXILite 550 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXILite 551 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S02_AXILite 552 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S03_AXILite 553 | create_bd_intf_pin -mode Slave -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS_in 554 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 out_stream 555 | 556 | # Create pins 557 | create_bd_pin -dir O -type clk PixelClk 558 | create_bd_pin -dir O aPixelClkLckd 559 | create_bd_pin -dir I -type clk clk_100M 560 | create_bd_pin -dir I -type clk clk_142M 561 | create_bd_pin -dir I -type clk clk_200M 562 | create_bd_pin -dir O -from 0 -to 0 hdmi_in_hpd 563 | create_bd_pin -dir O -type intr hdmi_in_hpd_irq 564 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk100M 565 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk142M 566 | create_bd_pin -dir I -from 0 -to 0 -type rst resetn 567 | create_bd_pin -dir I -from 0 -to 0 -type rst vid_io_in_reset 568 | create_bd_pin -dir O -type intr vtc_in_irq 569 | 570 | # Create instance: axis_register_slice_0, and set properties 571 | set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ] 572 | 573 | # Create instance: color_convert, and set properties 574 | set color_convert [ create_bd_cell -type ip -vlnv xilinx.com:hls:color_convert:1.0 color_convert ] 575 | 576 | # Create instance: frontend 577 | create_hier_cell_frontend $hier_obj frontend 578 | 579 | # Create instance: pixel_pack, and set properties 580 | set pixel_pack [ create_bd_cell -type ip -vlnv xilinx.com:hls:pixel_pack:1.0 pixel_pack ] 581 | 582 | # Create interface connections 583 | connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins S02_AXILite] [get_bd_intf_pins frontend/S02_AXILite] 584 | connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins S03_AXILite] [get_bd_intf_pins pixel_pack/s_axi_AXILiteS] 585 | connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins S01_AXILite] [get_bd_intf_pins color_convert/s_axi_AXILiteS] 586 | connect_bd_intf_net -intf_net TMDS_1 [get_bd_intf_pins TMDS_in] [get_bd_intf_pins frontend/TMDS_in] 587 | connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_register_slice_0/M_AXIS] [get_bd_intf_pins pixel_pack/stream_in_24] 588 | connect_bd_intf_net -intf_net color_convert_stream_out_24 [get_bd_intf_pins axis_register_slice_0/S_AXIS] [get_bd_intf_pins color_convert/stream_out_24] 589 | connect_bd_intf_net -intf_net frontend_DDC [get_bd_intf_pins DDC] [get_bd_intf_pins frontend/DDC] 590 | connect_bd_intf_net -intf_net frontend_video_out [get_bd_intf_pins color_convert/stream_in_24] [get_bd_intf_pins frontend/video_out] 591 | connect_bd_intf_net -intf_net pixel_pack_stream_out_32 [get_bd_intf_pins out_stream] [get_bd_intf_pins pixel_pack/stream_out_32] 592 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M07_AXI [get_bd_intf_pins S00_AXILite] [get_bd_intf_pins frontend/S00_AXILite] 593 | 594 | # Create port connections 595 | connect_bd_net -net Net [get_bd_pins clk_100M] [get_bd_pins frontend/clk_100M] 596 | connect_bd_net -net Net1 [get_bd_pins periph_resetn_clk100M] [get_bd_pins frontend/periph_resetn_clk100M] 597 | connect_bd_net -net RefClk_1 [get_bd_pins clk_200M] [get_bd_pins frontend/clk_200M] 598 | connect_bd_net -net aclk_1 [get_bd_pins clk_142M] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins color_convert/ap_clk] [get_bd_pins color_convert/control] [get_bd_pins frontend/clk_142M] [get_bd_pins pixel_pack/ap_clk] [get_bd_pins pixel_pack/control] 599 | connect_bd_net -net axi_gpio_video_gpio_io_o [get_bd_pins hdmi_in_hpd] [get_bd_pins frontend/hdmi_in_hpd] 600 | connect_bd_net -net axi_gpio_video_ip2intc_irpt [get_bd_pins hdmi_in_hpd_irq] [get_bd_pins frontend/hdmi_in_hpd_irq] 601 | connect_bd_net -net dvi2rgb_0_PixelClk [get_bd_pins PixelClk] [get_bd_pins frontend/PixelClk] 602 | connect_bd_net -net dvi2rgb_0_aPixelClkLckd [get_bd_pins aPixelClkLckd] [get_bd_pins frontend/aPixelClkLckd] 603 | connect_bd_net -net resetn_1 [get_bd_pins resetn] [get_bd_pins frontend/resetn] 604 | connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins periph_resetn_clk142M] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins color_convert/ap_rst_n] [get_bd_pins color_convert/ap_rst_n_control] [get_bd_pins pixel_pack/ap_rst_n] [get_bd_pins pixel_pack/ap_rst_n_control] 605 | connect_bd_net -net v_tc_1_irq [get_bd_pins vtc_in_irq] [get_bd_pins frontend/vtc_in_irq] 606 | connect_bd_net -net vid_io_in_reset_1 [get_bd_pins vid_io_in_reset] [get_bd_pins frontend/vid_io_in_reset] 607 | 608 | # Restore current instance 609 | current_bd_instance $oldCurInst 610 | } 611 | 612 | # Hierarchical cell: video 613 | proc create_hier_cell_video { parentCell nameHier } { 614 | 615 | variable script_folder 616 | 617 | if { $parentCell eq "" || $nameHier eq "" } { 618 | catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video() - Empty argument(s)!"} 619 | return 620 | } 621 | 622 | # Get object for parentCell 623 | set parentObj [get_bd_cells $parentCell] 624 | if { $parentObj == "" } { 625 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 626 | return 627 | } 628 | 629 | # Make sure parentObj is hier blk 630 | set parentType [get_property TYPE $parentObj] 631 | if { $parentType ne "hier" } { 632 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 633 | return 634 | } 635 | 636 | # Save current instance; Restore later 637 | set oldCurInst [current_bd_instance .] 638 | 639 | # Set parent object as current 640 | current_bd_instance $parentObj 641 | 642 | # Create cell and set as current instance 643 | set hier_obj [create_bd_cell -type hier $nameHier] 644 | current_bd_instance $hier_obj 645 | 646 | # Create interface pins 647 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 DDC 648 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI 649 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI 650 | create_bd_intf_pin -mode Slave -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS_in 651 | create_bd_intf_pin -mode Master -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS_out 652 | 653 | # Create pins 654 | create_bd_pin -dir I -type clk clk_100M 655 | create_bd_pin -dir I clk_142M 656 | create_bd_pin -dir I -type clk clk_200M 657 | create_bd_pin -dir O -from 0 -to 0 hdmi_in_hpd 658 | create_bd_pin -dir O -from 0 -to 0 hdmi_out_hpd 659 | create_bd_pin -dir I -from 0 -to 0 -type rst ic_resetn_clk100M 660 | create_bd_pin -dir I -from 0 -to 0 -type rst ic_resetn_clk142M 661 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk100M 662 | create_bd_pin -dir I -from 0 -to 0 -type rst periph_resetn_clk142M 663 | create_bd_pin -dir I -type rst system_resetn 664 | create_bd_pin -dir O -from 5 -to 0 video_irq 665 | 666 | # Create instance: axi_interconnect_0, and set properties 667 | set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] 668 | set_property -dict [ list \ 669 | CONFIG.M00_HAS_REGSLICE {1} \ 670 | CONFIG.M01_HAS_REGSLICE {1} \ 671 | CONFIG.M02_HAS_REGSLICE {1} \ 672 | CONFIG.M03_HAS_REGSLICE {1} \ 673 | CONFIG.M04_HAS_REGSLICE {1} \ 674 | CONFIG.M05_HAS_REGSLICE {1} \ 675 | CONFIG.M06_HAS_REGSLICE {1} \ 676 | CONFIG.M07_HAS_REGSLICE {1} \ 677 | CONFIG.M08_HAS_REGSLICE {1} \ 678 | CONFIG.M09_HAS_REGSLICE {1} \ 679 | CONFIG.NUM_MI {10} \ 680 | CONFIG.S00_HAS_REGSLICE {1} \ 681 | ] $axi_interconnect_0 682 | 683 | # Create instance: axi_mem_intercon, and set properties 684 | set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] 685 | set_property -dict [ list \ 686 | CONFIG.M00_HAS_REGSLICE {1} \ 687 | CONFIG.NUM_MI {1} \ 688 | CONFIG.NUM_SI {2} \ 689 | CONFIG.S00_HAS_REGSLICE {1} \ 690 | CONFIG.S01_HAS_REGSLICE {1} \ 691 | ] $axi_mem_intercon 692 | 693 | # Create instance: axi_vdma, and set properties 694 | set axi_vdma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma ] 695 | set_property -dict [ list \ 696 | CONFIG.c_m_axi_mm2s_data_width {32} \ 697 | CONFIG.c_m_axis_mm2s_tdata_width {32} \ 698 | CONFIG.c_mm2s_genlock_mode {1} \ 699 | CONFIG.c_mm2s_linebuffer_depth {512} \ 700 | CONFIG.c_mm2s_max_burst_length {32} \ 701 | CONFIG.c_num_fstores {4} \ 702 | CONFIG.c_s2mm_genlock_mode {0} \ 703 | CONFIG.c_s2mm_linebuffer_depth {4096} \ 704 | CONFIG.c_s2mm_max_burst_length {32} \ 705 | ] $axi_vdma 706 | 707 | # Create instance: hdmi_in 708 | create_hier_cell_hdmi_in $hier_obj hdmi_in 709 | 710 | # Create instance: hdmi_out 711 | create_hier_cell_hdmi_out $hier_obj hdmi_out 712 | 713 | # Create instance: proc_sys_reset_pixelclk, and set properties 714 | set proc_sys_reset_pixelclk [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_pixelclk ] 715 | 716 | # Create instance: xlconcat_0, and set properties 717 | set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] 718 | set_property -dict [ list \ 719 | CONFIG.NUM_PORTS {6} \ 720 | ] $xlconcat_0 721 | 722 | # Create interface connections 723 | connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins TMDS_out] [get_bd_intf_pins hdmi_out/TMDS_out] 724 | connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_interconnect_0/S00_AXI] 725 | connect_bd_intf_net -intf_net TMDS_1 [get_bd_intf_pins TMDS_in] [get_bd_intf_pins hdmi_in/TMDS_in] 726 | connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins axi_vdma/S_AXI_LITE] 727 | connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins hdmi_out/S01_AXILite] 728 | connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins hdmi_out/S03_AXILite] 729 | connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins hdmi_out/S04_AXILite] 730 | connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins hdmi_out/S02_AXILite] 731 | connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_interconnect_0/M05_AXI] [get_bd_intf_pins hdmi_out/S00_AXILite] 732 | connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_interconnect_0/M06_AXI] [get_bd_intf_pins hdmi_in/S01_AXILite] 733 | connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins axi_interconnect_0/M07_AXI] [get_bd_intf_pins hdmi_in/S03_AXILite] 734 | connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins hdmi_in/S00_AXILite] 735 | connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_pins axi_interconnect_0/M09_AXI] [get_bd_intf_pins hdmi_in/S02_AXILite] 736 | connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins M_AXI] [get_bd_intf_pins axi_mem_intercon/M00_AXI] 737 | connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma/M_AXIS_MM2S] [get_bd_intf_pins hdmi_out/in_stream] 738 | connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_MM2S [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins axi_vdma/M_AXI_MM2S] 739 | connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_S2MM [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins axi_vdma/M_AXI_S2MM] 740 | connect_bd_intf_net -intf_net frontend_DDC [get_bd_intf_pins DDC] [get_bd_intf_pins hdmi_in/DDC] 741 | connect_bd_intf_net -intf_net in_pixelformat_M00_AXIS [get_bd_intf_pins axi_vdma/S_AXIS_S2MM] [get_bd_intf_pins hdmi_in/out_stream] 742 | 743 | # Create port connections 744 | connect_bd_net -net ARESETN_1 [get_bd_pins ic_resetn_clk100M] [get_bd_pins axi_interconnect_0/ARESETN] 745 | connect_bd_net -net Net [get_bd_pins clk_100M] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_vdma/s_axi_lite_aclk] [get_bd_pins hdmi_in/clk_100M] [get_bd_pins hdmi_out/clk_100M] 746 | connect_bd_net -net Net1 [get_bd_pins periph_resetn_clk100M] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_vdma/axi_resetn] [get_bd_pins hdmi_in/periph_resetn_clk100M] [get_bd_pins hdmi_out/periph_resetn_clk100M] 747 | connect_bd_net -net RefClk_1 [get_bd_pins clk_200M] [get_bd_pins hdmi_in/clk_200M] 748 | connect_bd_net -net aclk_1 [get_bd_pins clk_142M] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_vdma/m_axi_mm2s_aclk] [get_bd_pins axi_vdma/m_axi_s2mm_aclk] [get_bd_pins axi_vdma/m_axis_mm2s_aclk] [get_bd_pins axi_vdma/s_axis_s2mm_aclk] [get_bd_pins hdmi_in/clk_142M] [get_bd_pins hdmi_out/clk_142M] 749 | connect_bd_net -net axi_gpio_video_gpio_io_o [get_bd_pins hdmi_in_hpd] [get_bd_pins hdmi_in/hdmi_in_hpd] 750 | connect_bd_net -net axi_gpio_video_ip2intc_irpt [get_bd_pins hdmi_in/hdmi_in_hpd_irq] [get_bd_pins xlconcat_0/In4] 751 | connect_bd_net -net axi_vdma_0_mm2s_introut [get_bd_pins axi_vdma/mm2s_introut] [get_bd_pins xlconcat_0/In1] 752 | connect_bd_net -net axi_vdma_0_s2mm_introut [get_bd_pins axi_vdma/s2mm_introut] [get_bd_pins xlconcat_0/In0] 753 | connect_bd_net -net ext_reset_in_1 [get_bd_pins system_resetn] [get_bd_pins proc_sys_reset_pixelclk/ext_reset_in] 754 | connect_bd_net -net hdmi_in_PixelClk [get_bd_pins hdmi_in/PixelClk] [get_bd_pins proc_sys_reset_pixelclk/slowest_sync_clk] 755 | connect_bd_net -net hdmi_in_aPixelClkLckd [get_bd_pins hdmi_in/aPixelClkLckd] [get_bd_pins proc_sys_reset_pixelclk/aux_reset_in] 756 | connect_bd_net -net hdmi_out_hpd_video_gpio_io_o [get_bd_pins hdmi_out_hpd] [get_bd_pins hdmi_out/hdmi_out_hpd] 757 | connect_bd_net -net hdmi_out_hpd_video_ip2intc_irpt [get_bd_pins hdmi_out/hdmi_out_hpd_irq] [get_bd_pins xlconcat_0/In5] 758 | connect_bd_net -net proc_sys_reset_pixelclk_peripheral_aresetn [get_bd_pins hdmi_in/resetn] [get_bd_pins proc_sys_reset_pixelclk/peripheral_aresetn] 759 | connect_bd_net -net proc_sys_reset_pixelclk_peripheral_reset [get_bd_pins hdmi_in/vid_io_in_reset] [get_bd_pins proc_sys_reset_pixelclk/peripheral_reset] 760 | connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ic_resetn_clk142M] [get_bd_pins axi_mem_intercon/ARESETN] 761 | connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins periph_resetn_clk142M] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins hdmi_in/periph_resetn_clk142M] [get_bd_pins hdmi_out/periph_resetn_clk142M] 762 | connect_bd_net -net v_tc_0_irq [get_bd_pins hdmi_out/vtc_out_irq] [get_bd_pins xlconcat_0/In2] 763 | connect_bd_net -net v_tc_1_irq [get_bd_pins hdmi_in/vtc_in_irq] [get_bd_pins xlconcat_0/In3] 764 | connect_bd_net -net xlconcat_0_dout [get_bd_pins video_irq] [get_bd_pins xlconcat_0/dout] 765 | 766 | # Restore current instance 767 | current_bd_instance $oldCurInst 768 | } 769 | 770 | # Hierarchical cell: image_filters 771 | proc create_hier_cell_image_filters { parentCell nameHier } { 772 | 773 | variable script_folder 774 | 775 | if { $parentCell eq "" || $nameHier eq "" } { 776 | catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_image_filters() - Empty argument(s)!"} 777 | return 778 | } 779 | 780 | # Get object for parentCell 781 | set parentObj [get_bd_cells $parentCell] 782 | if { $parentObj == "" } { 783 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 784 | return 785 | } 786 | 787 | # Make sure parentObj is hier blk 788 | set parentType [get_property TYPE $parentObj] 789 | if { $parentType ne "hier" } { 790 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 791 | return 792 | } 793 | 794 | # Save current instance; Restore later 795 | set oldCurInst [current_bd_instance .] 796 | 797 | # Set parent object as current 798 | current_bd_instance $parentObj 799 | 800 | # Create cell and set as current instance 801 | set hier_obj [create_bd_cell -type hier $nameHier] 802 | current_bd_instance $hier_obj 803 | 804 | # Create interface pins 805 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S 806 | create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM 807 | create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_CTRL 808 | 809 | # Create pins 810 | create_bd_pin -dir I -type clk clk_100M 811 | create_bd_pin -dir I -type rst clk_100M_aresetn 812 | create_bd_pin -dir I -type clk clk_142M 813 | create_bd_pin -dir I -type rst clk_142M_aresetn 814 | create_bd_pin -dir O -from 1 -to 0 dout 815 | 816 | # Create instance: axi_dma_0, and set properties 817 | set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] 818 | set_property -dict [ list \ 819 | CONFIG.c_include_sg {0} \ 820 | CONFIG.c_mm2s_burst_size {256} \ 821 | CONFIG.c_s2mm_burst_size {256} \ 822 | CONFIG.c_sg_include_stscntrl_strm {0} \ 823 | CONFIG.c_sg_length_width {23} \ 824 | ] $axi_dma_0 825 | 826 | # Create instance: axi_interconnect_2, and set properties 827 | set axi_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2 ] 828 | set_property -dict [ list \ 829 | CONFIG.NUM_MI {9} \ 830 | ] $axi_interconnect_2 831 | 832 | # Create instance: axis_interconnect_1, and set properties 833 | set axis_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_1 ] 834 | set_property -dict [ list \ 835 | CONFIG.ARB_ON_TLAST {0} \ 836 | CONFIG.NUM_MI {6} \ 837 | CONFIG.ROUTING_MODE {1} \ 838 | ] $axis_interconnect_1 839 | 840 | # Create instance: axis_interconnect_2, and set properties 841 | set axis_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_2 ] 842 | set_property -dict [ list \ 843 | CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ 844 | CONFIG.NUM_MI {1} \ 845 | CONFIG.NUM_SI {6} \ 846 | CONFIG.ROUTING_MODE {1} \ 847 | ] $axis_interconnect_2 848 | 849 | # Create instance: canny_edge_0, and set properties 850 | set canny_edge_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:canny_edge:1.0 canny_edge_0 ] 851 | 852 | # Create instance: dilate_hls_0, and set properties 853 | set dilate_hls_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:dilate_hls:1.0 dilate_hls_0 ] 854 | 855 | # Create instance: erode_hls_0, and set properties 856 | set erode_hls_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:erode_hls:1.0 erode_hls_0 ] 857 | 858 | # Create instance: filter2D_f_0, and set properties 859 | set filter2D_f_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:filter2D_f:1.0 filter2D_f_0 ] 860 | 861 | # Create instance: filter2D_hls_0, and set properties 862 | set filter2D_hls_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:filter2D_hls:1.0 filter2D_hls_0 ] 863 | 864 | # Create instance: filter2D_hls_5_0, and set properties 865 | set filter2D_hls_5_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:filter2D_hls_5:1.0 filter2D_hls_5_0 ] 866 | 867 | # Create instance: xlconcat_0, and set properties 868 | set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] 869 | 870 | # Create instance: xlconstant_0, and set properties 871 | set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] 872 | set_property -dict [ list \ 873 | CONFIG.CONST_VAL {0} \ 874 | CONFIG.CONST_WIDTH {1} \ 875 | ] $xlconstant_0 876 | 877 | # Create interface connections 878 | connect_bd_intf_net -intf_net S00_AXIS_2 [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_interconnect_1/S00_AXIS] 879 | connect_bd_intf_net -intf_net S02_AXIS_1 [get_bd_intf_pins axis_interconnect_2/S02_AXIS] [get_bd_intf_pins filter2D_f_0/out_stream] 880 | connect_bd_intf_net -intf_net S_AXI_CTRL_1 [get_bd_intf_pins S_AXI_CTRL] [get_bd_intf_pins axi_interconnect_2/S00_AXI] 881 | connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] 882 | connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] 883 | connect_bd_intf_net -intf_net axi_interconnect_2_M00_AXI [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins axis_interconnect_1/S_AXI_CTRL] 884 | connect_bd_intf_net -intf_net axi_interconnect_2_M01_AXI [get_bd_intf_pins axi_interconnect_2/M01_AXI] [get_bd_intf_pins axis_interconnect_2/S_AXI_CTRL] 885 | connect_bd_intf_net -intf_net axi_interconnect_2_M02_AXI [get_bd_intf_pins axi_interconnect_2/M02_AXI] [get_bd_intf_pins canny_edge_0/s_axi_CONTROL_BUS] 886 | connect_bd_intf_net -intf_net axi_interconnect_2_M03_AXI [get_bd_intf_pins axi_interconnect_2/M03_AXI] [get_bd_intf_pins filter2D_hls_0/s_axi_CONTROL_BUS] 887 | connect_bd_intf_net -intf_net axi_interconnect_2_M04_AXI [get_bd_intf_pins axi_interconnect_2/M04_AXI] [get_bd_intf_pins filter2D_f_0/s_axi_CONTROL_BUS] 888 | connect_bd_intf_net -intf_net axi_interconnect_2_M05_AXI [get_bd_intf_pins axi_interconnect_2/M05_AXI] [get_bd_intf_pins erode_hls_0/s_axi_CONTROL_BUS] 889 | connect_bd_intf_net -intf_net axi_interconnect_2_M06_AXI [get_bd_intf_pins axi_interconnect_2/M06_AXI] [get_bd_intf_pins dilate_hls_0/s_axi_CONTROL_BUS] 890 | connect_bd_intf_net -intf_net axi_interconnect_2_M07_AXI [get_bd_intf_pins axi_interconnect_2/M07_AXI] [get_bd_intf_pins filter2D_hls_5_0/s_axi_CONTROL_BUS] 891 | connect_bd_intf_net -intf_net axi_interconnect_2_M08_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins axi_interconnect_2/M08_AXI] 892 | connect_bd_intf_net -intf_net axis_interconnect_1_M00_AXIS [get_bd_intf_pins axis_interconnect_1/M00_AXIS] [get_bd_intf_pins canny_edge_0/in_stream] 893 | connect_bd_intf_net -intf_net axis_interconnect_1_M01_AXIS [get_bd_intf_pins axis_interconnect_1/M01_AXIS] [get_bd_intf_pins filter2D_hls_0/in_stream] 894 | connect_bd_intf_net -intf_net axis_interconnect_1_M02_AXIS [get_bd_intf_pins axis_interconnect_1/M02_AXIS] [get_bd_intf_pins filter2D_f_0/in_stream] 895 | connect_bd_intf_net -intf_net axis_interconnect_1_M03_AXIS [get_bd_intf_pins axis_interconnect_1/M03_AXIS] [get_bd_intf_pins erode_hls_0/in_stream] 896 | connect_bd_intf_net -intf_net axis_interconnect_1_M04_AXIS [get_bd_intf_pins axis_interconnect_1/M04_AXIS] [get_bd_intf_pins dilate_hls_0/in_stream] 897 | connect_bd_intf_net -intf_net axis_interconnect_1_M05_AXIS [get_bd_intf_pins axis_interconnect_1/M05_AXIS] [get_bd_intf_pins filter2D_hls_5_0/in_stream] 898 | connect_bd_intf_net -intf_net axis_interconnect_2_M00_AXIS [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_interconnect_2/M00_AXIS] 899 | connect_bd_intf_net -intf_net canny_edge_0_out_stream [get_bd_intf_pins axis_interconnect_2/S00_AXIS] [get_bd_intf_pins canny_edge_0/out_stream] 900 | connect_bd_intf_net -intf_net dilate_hls_0_out_stream [get_bd_intf_pins axis_interconnect_2/S04_AXIS] [get_bd_intf_pins dilate_hls_0/out_stream] 901 | connect_bd_intf_net -intf_net erode_hls_0_out_stream [get_bd_intf_pins axis_interconnect_2/S03_AXIS] [get_bd_intf_pins erode_hls_0/out_stream] 902 | connect_bd_intf_net -intf_net filter2D_hls_0_out_stream [get_bd_intf_pins axis_interconnect_2/S01_AXIS] [get_bd_intf_pins filter2D_hls_0/out_stream] 903 | connect_bd_intf_net -intf_net filter2D_hls_5_0_out_stream [get_bd_intf_pins axis_interconnect_2/S05_AXIS] [get_bd_intf_pins filter2D_hls_5_0/out_stream] 904 | 905 | # Create port connections 906 | connect_bd_net -net ap_clk1_1 [get_bd_pins clk_142M] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_interconnect_2/M02_ACLK] [get_bd_pins axi_interconnect_2/M03_ACLK] [get_bd_pins axi_interconnect_2/M04_ACLK] [get_bd_pins axi_interconnect_2/M05_ACLK] [get_bd_pins axi_interconnect_2/M06_ACLK] [get_bd_pins axi_interconnect_2/M07_ACLK] [get_bd_pins axi_interconnect_2/M08_ACLK] [get_bd_pins axis_interconnect_1/M00_AXIS_ACLK] [get_bd_pins axis_interconnect_1/M01_AXIS_ACLK] [get_bd_pins axis_interconnect_1/M02_AXIS_ACLK] [get_bd_pins axis_interconnect_1/M03_AXIS_ACLK] [get_bd_pins axis_interconnect_1/M04_AXIS_ACLK] [get_bd_pins axis_interconnect_1/M05_AXIS_ACLK] [get_bd_pins axis_interconnect_1/S00_AXIS_ACLK] [get_bd_pins axis_interconnect_2/M00_AXIS_ACLK] [get_bd_pins axis_interconnect_2/S00_AXIS_ACLK] [get_bd_pins axis_interconnect_2/S01_AXIS_ACLK] [get_bd_pins axis_interconnect_2/S02_AXIS_ACLK] [get_bd_pins axis_interconnect_2/S03_AXIS_ACLK] [get_bd_pins axis_interconnect_2/S04_AXIS_ACLK] [get_bd_pins axis_interconnect_2/S05_AXIS_ACLK] [get_bd_pins canny_edge_0/AXI_LITE_clk] [get_bd_pins canny_edge_0/ap_clk] [get_bd_pins dilate_hls_0/AXI_LITE_clk] [get_bd_pins dilate_hls_0/ap_clk] [get_bd_pins erode_hls_0/AXI_LITE_clk] [get_bd_pins erode_hls_0/ap_clk] [get_bd_pins filter2D_f_0/AXI_LITE_clk] [get_bd_pins filter2D_f_0/ap_clk] [get_bd_pins filter2D_hls_0/AXI_LITE_clk] [get_bd_pins filter2D_hls_0/ap_clk] [get_bd_pins filter2D_hls_5_0/AXI_LITE_clk] [get_bd_pins filter2D_hls_5_0/ap_clk] 907 | connect_bd_net -net ap_rst_n1_1 [get_bd_pins clk_142M_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_interconnect_2/M02_ARESETN] [get_bd_pins axi_interconnect_2/M03_ARESETN] [get_bd_pins axi_interconnect_2/M04_ARESETN] [get_bd_pins axi_interconnect_2/M05_ARESETN] [get_bd_pins axi_interconnect_2/M06_ARESETN] [get_bd_pins axi_interconnect_2/M07_ARESETN] [get_bd_pins axi_interconnect_2/M08_ARESETN] [get_bd_pins axis_interconnect_1/M00_AXIS_ARESETN] [get_bd_pins axis_interconnect_1/M01_AXIS_ARESETN] [get_bd_pins axis_interconnect_1/M02_AXIS_ARESETN] [get_bd_pins axis_interconnect_1/M03_AXIS_ARESETN] [get_bd_pins axis_interconnect_1/M04_AXIS_ARESETN] [get_bd_pins axis_interconnect_1/M05_AXIS_ARESETN] [get_bd_pins axis_interconnect_1/S00_AXIS_ARESETN] [get_bd_pins axis_interconnect_2/M00_AXIS_ARESETN] [get_bd_pins axis_interconnect_2/S00_AXIS_ARESETN] [get_bd_pins axis_interconnect_2/S01_AXIS_ARESETN] [get_bd_pins axis_interconnect_2/S02_AXIS_ARESETN] [get_bd_pins axis_interconnect_2/S03_AXIS_ARESETN] [get_bd_pins axis_interconnect_2/S04_AXIS_ARESETN] [get_bd_pins axis_interconnect_2/S05_AXIS_ARESETN] [get_bd_pins canny_edge_0/ap_rst_n] [get_bd_pins canny_edge_0/ap_rst_n_AXI_LITE_clk] [get_bd_pins dilate_hls_0/ap_rst_n] [get_bd_pins dilate_hls_0/ap_rst_n_AXI_LITE_clk] [get_bd_pins erode_hls_0/ap_rst_n] [get_bd_pins erode_hls_0/ap_rst_n_AXI_LITE_clk] [get_bd_pins filter2D_f_0/ap_rst_n] [get_bd_pins filter2D_f_0/ap_rst_n_AXI_LITE_clk] [get_bd_pins filter2D_hls_0/ap_rst_n] [get_bd_pins filter2D_hls_0/ap_rst_n_AXI_LITE_clk] [get_bd_pins filter2D_hls_5_0/ap_rst_n] [get_bd_pins filter2D_hls_5_0/ap_rst_n_AXI_LITE_clk] 908 | connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0] 909 | connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1] 910 | connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins clk_100M_aresetn] [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins axi_interconnect_2/M01_ARESETN] [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins axis_interconnect_1/ARESETN] [get_bd_pins axis_interconnect_1/S_AXI_CTRL_ARESETN] [get_bd_pins axis_interconnect_2/ARESETN] [get_bd_pins axis_interconnect_2/S_AXI_CTRL_ARESETN] 911 | connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins clk_100M] [get_bd_pins axi_interconnect_2/ACLK] [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_interconnect_2/M01_ACLK] [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins axis_interconnect_1/ACLK] [get_bd_pins axis_interconnect_1/S_AXI_CTRL_ACLK] [get_bd_pins axis_interconnect_2/ACLK] [get_bd_pins axis_interconnect_2/S_AXI_CTRL_ACLK] 912 | connect_bd_net -net xlconcat_0_dout [get_bd_pins dout] [get_bd_pins xlconcat_0/dout] 913 | connect_bd_net -net xlconstant_0_dout [get_bd_pins axis_interconnect_2/S00_ARB_REQ_SUPPRESS] [get_bd_pins axis_interconnect_2/S01_ARB_REQ_SUPPRESS] [get_bd_pins axis_interconnect_2/S02_ARB_REQ_SUPPRESS] [get_bd_pins axis_interconnect_2/S03_ARB_REQ_SUPPRESS] [get_bd_pins axis_interconnect_2/S04_ARB_REQ_SUPPRESS] [get_bd_pins axis_interconnect_2/S05_ARB_REQ_SUPPRESS] [get_bd_pins xlconstant_0/dout] 914 | 915 | # Restore current instance 916 | current_bd_instance $oldCurInst 917 | } 918 | 919 | 920 | # Procedure to create entire design; Provide argument to make 921 | # procedure reusable. If parentCell is "", will use root. 922 | proc create_root_design { parentCell } { 923 | 924 | variable script_folder 925 | variable design_name 926 | 927 | if { $parentCell eq "" } { 928 | set parentCell [get_bd_cells /] 929 | } 930 | 931 | # Get object for parentCell 932 | set parentObj [get_bd_cells $parentCell] 933 | if { $parentObj == "" } { 934 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 935 | return 936 | } 937 | 938 | # Make sure parentObj is hier blk 939 | set parentType [get_property TYPE $parentObj] 940 | if { $parentType ne "hier" } { 941 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 942 | return 943 | } 944 | 945 | # Save current instance; Restore later 946 | set oldCurInst [current_bd_instance .] 947 | 948 | # Set parent object as current 949 | current_bd_instance $parentObj 950 | 951 | 952 | # Create interface ports 953 | set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] 954 | set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] 955 | set hdmi_in [ create_bd_intf_port -mode Slave -vlnv digilentinc.com:interface:tmds_rtl:1.0 hdmi_in ] 956 | set hdmi_in_ddc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 hdmi_in_ddc ] 957 | set hdmi_out [ create_bd_intf_port -mode Master -vlnv digilentinc.com:interface:tmds_rtl:1.0 hdmi_out ] 958 | set hdmi_out_ddc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 hdmi_out_ddc ] 959 | 960 | # Create ports 961 | set hdmi_in_hpd [ create_bd_port -dir O -from 0 -to 0 hdmi_in_hpd ] 962 | set hdmi_out_hpd [ create_bd_port -dir O -from 0 -to 0 hdmi_out_hpd ] 963 | 964 | # Create instance: axi_intc_0, and set properties 965 | set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] 966 | 967 | # Create instance: axi_interconnect_0, and set properties 968 | set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] 969 | set_property -dict [ list \ 970 | CONFIG.NUM_MI {4} \ 971 | CONFIG.SYNCHRONIZATION_STAGES {2} \ 972 | ] $axi_interconnect_0 973 | 974 | # Create instance: axi_interconnect_1, and set properties 975 | set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] 976 | set_property -dict [ list \ 977 | CONFIG.NUM_MI {1} \ 978 | CONFIG.NUM_SI {3} \ 979 | CONFIG.SYNCHRONIZATION_STAGES {2} \ 980 | ] $axi_interconnect_1 981 | 982 | # Create instance: image_filters 983 | create_hier_cell_image_filters [current_bd_instance .] image_filters 984 | 985 | # Create instance: proc_sys_reset_fclk0, and set properties 986 | set proc_sys_reset_fclk0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_fclk0 ] 987 | 988 | # Create instance: proc_sys_reset_fclk1, and set properties 989 | set proc_sys_reset_fclk1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_fclk1 ] 990 | 991 | # Create instance: processing_system7_0, and set properties 992 | set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] 993 | set_property -dict [ list \ 994 | CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ 995 | CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ 996 | CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ 997 | CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ 998 | CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ 999 | CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ 1000 | CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ 1001 | CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ 1002 | CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {142.857132} \ 1003 | CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {200.000000} \ 1004 | CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {100.000000} \ 1005 | CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ 1006 | CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ 1007 | CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ 1008 | CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ 1009 | CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ 1010 | CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ 1011 | CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ 1012 | CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 1013 | CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 1014 | CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 1015 | CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 1016 | CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 1017 | CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 1018 | CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ 1019 | CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ 1020 | CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ 1021 | CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ 1022 | CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ 1023 | CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ 1024 | CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ 1025 | CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ 1026 | CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ 1027 | CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \ 1028 | CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ 1029 | CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ 1030 | CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ 1031 | CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ 1032 | CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ 1033 | CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \ 1034 | CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ 1035 | CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ 1036 | CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ 1037 | CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ 1038 | CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ 1039 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ 1040 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ 1041 | CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ 1042 | CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ 1043 | CONFIG.PCW_CLK0_FREQ {100000000} \ 1044 | CONFIG.PCW_CLK1_FREQ {142857132} \ 1045 | CONFIG.PCW_CLK2_FREQ {200000000} \ 1046 | CONFIG.PCW_CLK3_FREQ {100000000} \ 1047 | CONFIG.PCW_CORE0_FIQ_INTR {0} \ 1048 | CONFIG.PCW_CORE0_IRQ_INTR {0} \ 1049 | CONFIG.PCW_CORE1_FIQ_INTR {0} \ 1050 | CONFIG.PCW_CORE1_IRQ_INTR {0} \ 1051 | CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ 1052 | CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ 1053 | CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ 1054 | CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ 1055 | CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ 1056 | CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ 1057 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ 1058 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ 1059 | CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ 1060 | CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ 1061 | CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ 1062 | CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ 1063 | CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ 1064 | CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ 1065 | CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ 1066 | CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ 1067 | CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ 1068 | CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ 1069 | CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ 1070 | CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ 1071 | CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ 1072 | CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ 1073 | CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ 1074 | CONFIG.PCW_DM_WIDTH {4} \ 1075 | CONFIG.PCW_DQS_WIDTH {4} \ 1076 | CONFIG.PCW_DQ_WIDTH {32} \ 1077 | CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ 1078 | CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ 1079 | CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ 1080 | CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ 1081 | CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ 1082 | CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ 1083 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ 1084 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ 1085 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ 1086 | CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ 1087 | CONFIG.PCW_ENET0_RESET_ENABLE {1} \ 1088 | CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ 1089 | CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ 1090 | CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ 1091 | CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ 1092 | CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ 1093 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ 1094 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ 1095 | CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ 1096 | CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ 1097 | CONFIG.PCW_ENET1_RESET_ENABLE {0} \ 1098 | CONFIG.PCW_ENET_RESET_ENABLE {1} \ 1099 | CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ 1100 | CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ 1101 | CONFIG.PCW_EN_4K_TIMER {0} \ 1102 | CONFIG.PCW_EN_CAN0 {0} \ 1103 | CONFIG.PCW_EN_CAN1 {0} \ 1104 | CONFIG.PCW_EN_CLK0_PORT {1} \ 1105 | CONFIG.PCW_EN_CLK1_PORT {1} \ 1106 | CONFIG.PCW_EN_CLK2_PORT {1} \ 1107 | CONFIG.PCW_EN_CLK3_PORT {1} \ 1108 | CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ 1109 | CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ 1110 | CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ 1111 | CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ 1112 | CONFIG.PCW_EN_DDR {1} \ 1113 | CONFIG.PCW_EN_EMIO_CAN0 {0} \ 1114 | CONFIG.PCW_EN_EMIO_CAN1 {0} \ 1115 | CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ 1116 | CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ 1117 | CONFIG.PCW_EN_EMIO_ENET0 {0} \ 1118 | CONFIG.PCW_EN_EMIO_ENET1 {0} \ 1119 | CONFIG.PCW_EN_EMIO_GPIO {0} \ 1120 | CONFIG.PCW_EN_EMIO_I2C0 {1} \ 1121 | CONFIG.PCW_EN_EMIO_I2C1 {0} \ 1122 | CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ 1123 | CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ 1124 | CONFIG.PCW_EN_EMIO_PJTAG {0} \ 1125 | CONFIG.PCW_EN_EMIO_SDIO0 {0} \ 1126 | CONFIG.PCW_EN_EMIO_SDIO1 {0} \ 1127 | CONFIG.PCW_EN_EMIO_SPI0 {0} \ 1128 | CONFIG.PCW_EN_EMIO_SPI1 {0} \ 1129 | CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ 1130 | CONFIG.PCW_EN_EMIO_TRACE {0} \ 1131 | CONFIG.PCW_EN_EMIO_TTC0 {0} \ 1132 | CONFIG.PCW_EN_EMIO_TTC1 {0} \ 1133 | CONFIG.PCW_EN_EMIO_UART0 {0} \ 1134 | CONFIG.PCW_EN_EMIO_UART1 {0} \ 1135 | CONFIG.PCW_EN_EMIO_WDT {0} \ 1136 | CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ 1137 | CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ 1138 | CONFIG.PCW_EN_ENET0 {1} \ 1139 | CONFIG.PCW_EN_ENET1 {0} \ 1140 | CONFIG.PCW_EN_GPIO {1} \ 1141 | CONFIG.PCW_EN_I2C0 {1} \ 1142 | CONFIG.PCW_EN_I2C1 {0} \ 1143 | CONFIG.PCW_EN_MODEM_UART0 {0} \ 1144 | CONFIG.PCW_EN_MODEM_UART1 {0} \ 1145 | CONFIG.PCW_EN_PJTAG {0} \ 1146 | CONFIG.PCW_EN_PTP_ENET0 {0} \ 1147 | CONFIG.PCW_EN_PTP_ENET1 {0} \ 1148 | CONFIG.PCW_EN_QSPI {1} \ 1149 | CONFIG.PCW_EN_RST0_PORT {1} \ 1150 | CONFIG.PCW_EN_RST1_PORT {0} \ 1151 | CONFIG.PCW_EN_RST2_PORT {0} \ 1152 | CONFIG.PCW_EN_RST3_PORT {0} \ 1153 | CONFIG.PCW_EN_SDIO0 {1} \ 1154 | CONFIG.PCW_EN_SDIO1 {0} \ 1155 | CONFIG.PCW_EN_SMC {0} \ 1156 | CONFIG.PCW_EN_SPI0 {0} \ 1157 | CONFIG.PCW_EN_SPI1 {0} \ 1158 | CONFIG.PCW_EN_TRACE {0} \ 1159 | CONFIG.PCW_EN_TTC0 {0} \ 1160 | CONFIG.PCW_EN_TTC1 {0} \ 1161 | CONFIG.PCW_EN_UART0 {1} \ 1162 | CONFIG.PCW_EN_UART1 {0} \ 1163 | CONFIG.PCW_EN_USB0 {1} \ 1164 | CONFIG.PCW_EN_USB1 {0} \ 1165 | CONFIG.PCW_EN_WDT {0} \ 1166 | CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ 1167 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ 1168 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ 1169 | CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ 1170 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {7} \ 1171 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ 1172 | CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ 1173 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {5} \ 1174 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ 1175 | CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ 1176 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \ 1177 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \ 1178 | CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ 1179 | CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ 1180 | CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ 1181 | CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ 1182 | CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ 1183 | CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {142} \ 1184 | CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200} \ 1185 | CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {100} \ 1186 | CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ 1187 | CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ 1188 | CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ 1189 | CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \ 1190 | CONFIG.PCW_FTM_CTI_IN0 {} \ 1192 | CONFIG.PCW_FTM_CTI_IN2 {} \ 1194 | CONFIG.PCW_FTM_CTI_OUT0 {} \ 1196 | CONFIG.PCW_FTM_CTI_OUT2 {} \ 1198 | CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {0} \ 1199 | CONFIG.PCW_GP0_NUM_READ_THREADS {4} \ 1200 | CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \ 1201 | CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {0} \ 1202 | CONFIG.PCW_GP1_NUM_READ_THREADS {4} \ 1203 | CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \ 1204 | CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ 1205 | CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ 1206 | CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ 1207 | CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ 1208 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ 1209 | CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ 1210 | CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ 1211 | CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ 1212 | CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \ 1213 | CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \ 1214 | CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ 1215 | CONFIG.PCW_I2C0_I2C0_IO {EMIO} \ 1216 | CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ 1217 | CONFIG.PCW_I2C0_RESET_ENABLE {0} \ 1218 | CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ 1219 | CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \ 1220 | CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ 1221 | CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ 1222 | CONFIG.PCW_I2C1_RESET_ENABLE {0} \ 1223 | CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {108.333336} \ 1224 | CONFIG.PCW_I2C_RESET_ENABLE {0} \ 1225 | CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ 1226 | CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ 1227 | CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ 1228 | CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ 1229 | CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ 1230 | CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ 1231 | CONFIG.PCW_IRQ_F2P_INTR {1} \ 1232 | CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ 1233 | CONFIG.PCW_MIO_0_DIRECTION {inout} \ 1234 | CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ 1235 | CONFIG.PCW_MIO_0_PULLUP {enabled} \ 1236 | CONFIG.PCW_MIO_0_SLEW {slow} \ 1237 | CONFIG.PCW_MIO_10_DIRECTION {inout} \ 1238 | CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ 1239 | CONFIG.PCW_MIO_10_PULLUP {enabled} \ 1240 | CONFIG.PCW_MIO_10_SLEW {slow} \ 1241 | CONFIG.PCW_MIO_11_DIRECTION {inout} \ 1242 | CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ 1243 | CONFIG.PCW_MIO_11_PULLUP {enabled} \ 1244 | CONFIG.PCW_MIO_11_SLEW {slow} \ 1245 | CONFIG.PCW_MIO_12_DIRECTION {inout} \ 1246 | CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ 1247 | CONFIG.PCW_MIO_12_PULLUP {enabled} \ 1248 | CONFIG.PCW_MIO_12_SLEW {slow} \ 1249 | CONFIG.PCW_MIO_13_DIRECTION {inout} \ 1250 | CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ 1251 | CONFIG.PCW_MIO_13_PULLUP {enabled} \ 1252 | CONFIG.PCW_MIO_13_SLEW {slow} \ 1253 | CONFIG.PCW_MIO_14_DIRECTION {in} \ 1254 | CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ 1255 | CONFIG.PCW_MIO_14_PULLUP {enabled} \ 1256 | CONFIG.PCW_MIO_14_SLEW {slow} \ 1257 | CONFIG.PCW_MIO_15_DIRECTION {out} \ 1258 | CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ 1259 | CONFIG.PCW_MIO_15_PULLUP {enabled} \ 1260 | CONFIG.PCW_MIO_15_SLEW {slow} \ 1261 | CONFIG.PCW_MIO_16_DIRECTION {out} \ 1262 | CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ 1263 | CONFIG.PCW_MIO_16_PULLUP {enabled} \ 1264 | CONFIG.PCW_MIO_16_SLEW {slow} \ 1265 | CONFIG.PCW_MIO_17_DIRECTION {out} \ 1266 | CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ 1267 | CONFIG.PCW_MIO_17_PULLUP {enabled} \ 1268 | CONFIG.PCW_MIO_17_SLEW {slow} \ 1269 | CONFIG.PCW_MIO_18_DIRECTION {out} \ 1270 | CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ 1271 | CONFIG.PCW_MIO_18_PULLUP {enabled} \ 1272 | CONFIG.PCW_MIO_18_SLEW {slow} \ 1273 | CONFIG.PCW_MIO_19_DIRECTION {out} \ 1274 | CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ 1275 | CONFIG.PCW_MIO_19_PULLUP {enabled} \ 1276 | CONFIG.PCW_MIO_19_SLEW {slow} \ 1277 | CONFIG.PCW_MIO_1_DIRECTION {out} \ 1278 | CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ 1279 | CONFIG.PCW_MIO_1_PULLUP {enabled} \ 1280 | CONFIG.PCW_MIO_1_SLEW {slow} \ 1281 | CONFIG.PCW_MIO_20_DIRECTION {out} \ 1282 | CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ 1283 | CONFIG.PCW_MIO_20_PULLUP {enabled} \ 1284 | CONFIG.PCW_MIO_20_SLEW {slow} \ 1285 | CONFIG.PCW_MIO_21_DIRECTION {out} \ 1286 | CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ 1287 | CONFIG.PCW_MIO_21_PULLUP {enabled} \ 1288 | CONFIG.PCW_MIO_21_SLEW {slow} \ 1289 | CONFIG.PCW_MIO_22_DIRECTION {in} \ 1290 | CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ 1291 | CONFIG.PCW_MIO_22_PULLUP {enabled} \ 1292 | CONFIG.PCW_MIO_22_SLEW {slow} \ 1293 | CONFIG.PCW_MIO_23_DIRECTION {in} \ 1294 | CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ 1295 | CONFIG.PCW_MIO_23_PULLUP {enabled} \ 1296 | CONFIG.PCW_MIO_23_SLEW {slow} \ 1297 | CONFIG.PCW_MIO_24_DIRECTION {in} \ 1298 | CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ 1299 | CONFIG.PCW_MIO_24_PULLUP {enabled} \ 1300 | CONFIG.PCW_MIO_24_SLEW {slow} \ 1301 | CONFIG.PCW_MIO_25_DIRECTION {in} \ 1302 | CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ 1303 | CONFIG.PCW_MIO_25_PULLUP {enabled} \ 1304 | CONFIG.PCW_MIO_25_SLEW {slow} \ 1305 | CONFIG.PCW_MIO_26_DIRECTION {in} \ 1306 | CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ 1307 | CONFIG.PCW_MIO_26_PULLUP {enabled} \ 1308 | CONFIG.PCW_MIO_26_SLEW {slow} \ 1309 | CONFIG.PCW_MIO_27_DIRECTION {in} \ 1310 | CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ 1311 | CONFIG.PCW_MIO_27_PULLUP {enabled} \ 1312 | CONFIG.PCW_MIO_27_SLEW {slow} \ 1313 | CONFIG.PCW_MIO_28_DIRECTION {inout} \ 1314 | CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ 1315 | CONFIG.PCW_MIO_28_PULLUP {enabled} \ 1316 | CONFIG.PCW_MIO_28_SLEW {slow} \ 1317 | CONFIG.PCW_MIO_29_DIRECTION {in} \ 1318 | CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ 1319 | CONFIG.PCW_MIO_29_PULLUP {enabled} \ 1320 | CONFIG.PCW_MIO_29_SLEW {slow} \ 1321 | CONFIG.PCW_MIO_2_DIRECTION {inout} \ 1322 | CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ 1323 | CONFIG.PCW_MIO_2_PULLUP {disabled} \ 1324 | CONFIG.PCW_MIO_2_SLEW {slow} \ 1325 | CONFIG.PCW_MIO_30_DIRECTION {out} \ 1326 | CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ 1327 | CONFIG.PCW_MIO_30_PULLUP {enabled} \ 1328 | CONFIG.PCW_MIO_30_SLEW {slow} \ 1329 | CONFIG.PCW_MIO_31_DIRECTION {in} \ 1330 | CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ 1331 | CONFIG.PCW_MIO_31_PULLUP {enabled} \ 1332 | CONFIG.PCW_MIO_31_SLEW {slow} \ 1333 | CONFIG.PCW_MIO_32_DIRECTION {inout} \ 1334 | CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ 1335 | CONFIG.PCW_MIO_32_PULLUP {enabled} \ 1336 | CONFIG.PCW_MIO_32_SLEW {slow} \ 1337 | CONFIG.PCW_MIO_33_DIRECTION {inout} \ 1338 | CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ 1339 | CONFIG.PCW_MIO_33_PULLUP {enabled} \ 1340 | CONFIG.PCW_MIO_33_SLEW {slow} \ 1341 | CONFIG.PCW_MIO_34_DIRECTION {inout} \ 1342 | CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ 1343 | CONFIG.PCW_MIO_34_PULLUP {enabled} \ 1344 | CONFIG.PCW_MIO_34_SLEW {slow} \ 1345 | CONFIG.PCW_MIO_35_DIRECTION {inout} \ 1346 | CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ 1347 | CONFIG.PCW_MIO_35_PULLUP {enabled} \ 1348 | CONFIG.PCW_MIO_35_SLEW {slow} \ 1349 | CONFIG.PCW_MIO_36_DIRECTION {in} \ 1350 | CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ 1351 | CONFIG.PCW_MIO_36_PULLUP {enabled} \ 1352 | CONFIG.PCW_MIO_36_SLEW {slow} \ 1353 | CONFIG.PCW_MIO_37_DIRECTION {inout} \ 1354 | CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ 1355 | CONFIG.PCW_MIO_37_PULLUP {enabled} \ 1356 | CONFIG.PCW_MIO_37_SLEW {slow} \ 1357 | CONFIG.PCW_MIO_38_DIRECTION {inout} \ 1358 | CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ 1359 | CONFIG.PCW_MIO_38_PULLUP {enabled} \ 1360 | CONFIG.PCW_MIO_38_SLEW {slow} \ 1361 | CONFIG.PCW_MIO_39_DIRECTION {inout} \ 1362 | CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ 1363 | CONFIG.PCW_MIO_39_PULLUP {enabled} \ 1364 | CONFIG.PCW_MIO_39_SLEW {slow} \ 1365 | CONFIG.PCW_MIO_3_DIRECTION {inout} \ 1366 | CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ 1367 | CONFIG.PCW_MIO_3_PULLUP {disabled} \ 1368 | CONFIG.PCW_MIO_3_SLEW {slow} \ 1369 | CONFIG.PCW_MIO_40_DIRECTION {inout} \ 1370 | CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ 1371 | CONFIG.PCW_MIO_40_PULLUP {enabled} \ 1372 | CONFIG.PCW_MIO_40_SLEW {slow} \ 1373 | CONFIG.PCW_MIO_41_DIRECTION {inout} \ 1374 | CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ 1375 | CONFIG.PCW_MIO_41_PULLUP {enabled} \ 1376 | CONFIG.PCW_MIO_41_SLEW {slow} \ 1377 | CONFIG.PCW_MIO_42_DIRECTION {inout} \ 1378 | CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ 1379 | CONFIG.PCW_MIO_42_PULLUP {enabled} \ 1380 | CONFIG.PCW_MIO_42_SLEW {slow} \ 1381 | CONFIG.PCW_MIO_43_DIRECTION {inout} \ 1382 | CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ 1383 | CONFIG.PCW_MIO_43_PULLUP {enabled} \ 1384 | CONFIG.PCW_MIO_43_SLEW {slow} \ 1385 | CONFIG.PCW_MIO_44_DIRECTION {inout} \ 1386 | CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ 1387 | CONFIG.PCW_MIO_44_PULLUP {enabled} \ 1388 | CONFIG.PCW_MIO_44_SLEW {slow} \ 1389 | CONFIG.PCW_MIO_45_DIRECTION {inout} \ 1390 | CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ 1391 | CONFIG.PCW_MIO_45_PULLUP {enabled} \ 1392 | CONFIG.PCW_MIO_45_SLEW {slow} \ 1393 | CONFIG.PCW_MIO_46_DIRECTION {out} \ 1394 | CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ 1395 | CONFIG.PCW_MIO_46_PULLUP {enabled} \ 1396 | CONFIG.PCW_MIO_46_SLEW {slow} \ 1397 | CONFIG.PCW_MIO_47_DIRECTION {in} \ 1398 | CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ 1399 | CONFIG.PCW_MIO_47_PULLUP {enabled} \ 1400 | CONFIG.PCW_MIO_47_SLEW {slow} \ 1401 | CONFIG.PCW_MIO_48_DIRECTION {inout} \ 1402 | CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ 1403 | CONFIG.PCW_MIO_48_PULLUP {enabled} \ 1404 | CONFIG.PCW_MIO_48_SLEW {slow} \ 1405 | CONFIG.PCW_MIO_49_DIRECTION {inout} \ 1406 | CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ 1407 | CONFIG.PCW_MIO_49_PULLUP {enabled} \ 1408 | CONFIG.PCW_MIO_49_SLEW {slow} \ 1409 | CONFIG.PCW_MIO_4_DIRECTION {inout} \ 1410 | CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ 1411 | CONFIG.PCW_MIO_4_PULLUP {disabled} \ 1412 | CONFIG.PCW_MIO_4_SLEW {slow} \ 1413 | CONFIG.PCW_MIO_50_DIRECTION {inout} \ 1414 | CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ 1415 | CONFIG.PCW_MIO_50_PULLUP {enabled} \ 1416 | CONFIG.PCW_MIO_50_SLEW {slow} \ 1417 | CONFIG.PCW_MIO_51_DIRECTION {inout} \ 1418 | CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ 1419 | CONFIG.PCW_MIO_51_PULLUP {enabled} \ 1420 | CONFIG.PCW_MIO_51_SLEW {slow} \ 1421 | CONFIG.PCW_MIO_52_DIRECTION {out} \ 1422 | CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ 1423 | CONFIG.PCW_MIO_52_PULLUP {enabled} \ 1424 | CONFIG.PCW_MIO_52_SLEW {slow} \ 1425 | CONFIG.PCW_MIO_53_DIRECTION {inout} \ 1426 | CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ 1427 | CONFIG.PCW_MIO_53_PULLUP {enabled} \ 1428 | CONFIG.PCW_MIO_53_SLEW {slow} \ 1429 | CONFIG.PCW_MIO_5_DIRECTION {inout} \ 1430 | CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ 1431 | CONFIG.PCW_MIO_5_PULLUP {disabled} \ 1432 | CONFIG.PCW_MIO_5_SLEW {slow} \ 1433 | CONFIG.PCW_MIO_6_DIRECTION {out} \ 1434 | CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ 1435 | CONFIG.PCW_MIO_6_PULLUP {disabled} \ 1436 | CONFIG.PCW_MIO_6_SLEW {slow} \ 1437 | CONFIG.PCW_MIO_7_DIRECTION {out} \ 1438 | CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ 1439 | CONFIG.PCW_MIO_7_PULLUP {disabled} \ 1440 | CONFIG.PCW_MIO_7_SLEW {slow} \ 1441 | CONFIG.PCW_MIO_8_DIRECTION {out} \ 1442 | CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ 1443 | CONFIG.PCW_MIO_8_PULLUP {disabled} \ 1444 | CONFIG.PCW_MIO_8_SLEW {slow} \ 1445 | CONFIG.PCW_MIO_9_DIRECTION {out} \ 1446 | CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ 1447 | CONFIG.PCW_MIO_9_PULLUP {enabled} \ 1448 | CONFIG.PCW_MIO_9_SLEW {slow} \ 1449 | CONFIG.PCW_MIO_PRIMITIVE {54} \ 1450 | CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ 1451 | CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ 1452 | CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ 1453 | CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ 1454 | CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ 1455 | CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ 1456 | CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ 1457 | CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ 1458 | CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ 1459 | CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ 1460 | CONFIG.PCW_NAND_CYCLES_T_AR {1} \ 1461 | CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ 1462 | CONFIG.PCW_NAND_CYCLES_T_RC {11} \ 1463 | CONFIG.PCW_NAND_CYCLES_T_REA {1} \ 1464 | CONFIG.PCW_NAND_CYCLES_T_RR {1} \ 1465 | CONFIG.PCW_NAND_CYCLES_T_WC {11} \ 1466 | CONFIG.PCW_NAND_CYCLES_T_WP {1} \ 1467 | CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ 1468 | CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ 1469 | CONFIG.PCW_NOR_CS0_T_CEOE {1} \ 1470 | CONFIG.PCW_NOR_CS0_T_PC {1} \ 1471 | CONFIG.PCW_NOR_CS0_T_RC {11} \ 1472 | CONFIG.PCW_NOR_CS0_T_TR {1} \ 1473 | CONFIG.PCW_NOR_CS0_T_WC {11} \ 1474 | CONFIG.PCW_NOR_CS0_T_WP {1} \ 1475 | CONFIG.PCW_NOR_CS0_WE_TIME {0} \ 1476 | CONFIG.PCW_NOR_CS1_T_CEOE {1} \ 1477 | CONFIG.PCW_NOR_CS1_T_PC {1} \ 1478 | CONFIG.PCW_NOR_CS1_T_RC {11} \ 1479 | CONFIG.PCW_NOR_CS1_T_TR {1} \ 1480 | CONFIG.PCW_NOR_CS1_T_WC {11} \ 1481 | CONFIG.PCW_NOR_CS1_T_WP {1} \ 1482 | CONFIG.PCW_NOR_CS1_WE_TIME {0} \ 1483 | CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ 1484 | CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ 1485 | CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ 1486 | CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ 1487 | CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ 1488 | CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ 1489 | CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ 1490 | CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ 1491 | CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ 1492 | CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ 1493 | CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ 1494 | CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ 1495 | CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ 1496 | CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ 1497 | CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ 1498 | CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ 1499 | CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ 1500 | CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ 1501 | CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ 1502 | CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ 1503 | CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ 1504 | CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ 1505 | CONFIG.PCW_P2F_CAN0_INTR {0} \ 1506 | CONFIG.PCW_P2F_CAN1_INTR {0} \ 1507 | CONFIG.PCW_P2F_CTI_INTR {0} \ 1508 | CONFIG.PCW_P2F_DMAC0_INTR {0} \ 1509 | CONFIG.PCW_P2F_DMAC1_INTR {0} \ 1510 | CONFIG.PCW_P2F_DMAC2_INTR {0} \ 1511 | CONFIG.PCW_P2F_DMAC3_INTR {0} \ 1512 | CONFIG.PCW_P2F_DMAC4_INTR {0} \ 1513 | CONFIG.PCW_P2F_DMAC5_INTR {0} \ 1514 | CONFIG.PCW_P2F_DMAC6_INTR {0} \ 1515 | CONFIG.PCW_P2F_DMAC7_INTR {0} \ 1516 | CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ 1517 | CONFIG.PCW_P2F_ENET0_INTR {0} \ 1518 | CONFIG.PCW_P2F_ENET1_INTR {0} \ 1519 | CONFIG.PCW_P2F_GPIO_INTR {0} \ 1520 | CONFIG.PCW_P2F_I2C0_INTR {0} \ 1521 | CONFIG.PCW_P2F_I2C1_INTR {0} \ 1522 | CONFIG.PCW_P2F_QSPI_INTR {0} \ 1523 | CONFIG.PCW_P2F_SDIO0_INTR {0} \ 1524 | CONFIG.PCW_P2F_SDIO1_INTR {0} \ 1525 | CONFIG.PCW_P2F_SMC_INTR {0} \ 1526 | CONFIG.PCW_P2F_SPI0_INTR {0} \ 1527 | CONFIG.PCW_P2F_SPI1_INTR {0} \ 1528 | CONFIG.PCW_P2F_UART0_INTR {0} \ 1529 | CONFIG.PCW_P2F_UART1_INTR {0} \ 1530 | CONFIG.PCW_P2F_USB0_INTR {0} \ 1531 | CONFIG.PCW_P2F_USB1_INTR {0} \ 1532 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ 1533 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ 1534 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ 1535 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ 1536 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ 1537 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ 1538 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 1539 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 1540 | CONFIG.PCW_PACKAGE_NAME {clg400} \ 1541 | CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ 1542 | CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ 1543 | CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ 1544 | CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ 1545 | CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ 1546 | CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ 1547 | CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ 1548 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ 1549 | CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ 1550 | CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ 1551 | CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ 1552 | CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ 1553 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ 1554 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ 1555 | CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ 1556 | CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ 1557 | CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ 1558 | CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ 1559 | CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ 1560 | CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ 1561 | CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ 1562 | CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ 1563 | CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ 1564 | CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ 1565 | CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ 1566 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ 1567 | CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ 1568 | CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ 1569 | CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ 1570 | CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ 1571 | CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ 1572 | CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ 1573 | CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ 1574 | CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ 1575 | CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ 1576 | CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ 1577 | CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ 1578 | CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ 1579 | CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ 1580 | CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ 1581 | CONFIG.PCW_SMC_CYCLE_T0 {NA} \ 1582 | CONFIG.PCW_SMC_CYCLE_T1 {NA} \ 1583 | CONFIG.PCW_SMC_CYCLE_T2 {NA} \ 1584 | CONFIG.PCW_SMC_CYCLE_T3 {NA} \ 1585 | CONFIG.PCW_SMC_CYCLE_T4 {NA} \ 1586 | CONFIG.PCW_SMC_CYCLE_T5 {NA} \ 1587 | CONFIG.PCW_SMC_CYCLE_T6 {NA} \ 1588 | CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ 1589 | CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ 1590 | CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ 1591 | CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ 1592 | CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ 1593 | CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ 1594 | CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ 1595 | CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ 1596 | CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ 1597 | CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ 1598 | CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ 1599 | CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ 1600 | CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ 1601 | CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ 1602 | CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ 1603 | CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ 1604 | CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ 1605 | CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ 1606 | CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ 1607 | CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ 1608 | CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ 1609 | CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ 1610 | CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ 1611 | CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ 1612 | CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ 1613 | CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ 1614 | CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ 1615 | CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ 1616 | CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ 1617 | CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ 1618 | CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ 1619 | CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ 1620 | CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ 1621 | CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ 1622 | CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ 1623 | CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ 1624 | CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ 1625 | CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ 1626 | CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \ 1627 | CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ 1628 | CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \ 1629 | CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ 1630 | CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \ 1631 | CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ 1632 | CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ 1633 | CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ 1634 | CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ 1635 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 1636 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ 1637 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 1638 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 1639 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ 1640 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 1641 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 1642 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ 1643 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 1644 | CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ 1645 | CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \ 1646 | CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ 1647 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 1648 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ 1649 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 1650 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 1651 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ 1652 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 1653 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 1654 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ 1655 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 1656 | CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ 1657 | CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ 1658 | CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ 1659 | CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ 1660 | CONFIG.PCW_UART0_BAUD_RATE {115200} \ 1661 | CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ 1662 | CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ 1663 | CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ 1664 | CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ 1665 | CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ 1666 | CONFIG.PCW_UART1_BAUD_RATE {115200} \ 1667 | CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ 1668 | CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ 1669 | CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ 1670 | CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ 1671 | CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ 1672 | CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ 1673 | CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ 1674 | CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ 1675 | CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ 1676 | CONFIG.PCW_UIPARAM_DDR_AL {0} \ 1677 | CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ 1678 | CONFIG.PCW_UIPARAM_DDR_BL {8} \ 1679 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ 1680 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ 1681 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ 1682 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ 1683 | CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ 1684 | CONFIG.PCW_UIPARAM_DDR_CL {7} \ 1685 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ 1686 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ 1687 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ 1688 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ 1689 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ 1690 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ 1691 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ 1692 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ 1693 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ 1694 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ 1695 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ 1696 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ 1697 | CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ 1698 | CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ 1699 | CONFIG.PCW_UIPARAM_DDR_CWL {6} \ 1700 | CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ 1701 | CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ 1702 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ 1703 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ 1704 | CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ 1705 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ 1706 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ 1707 | CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ 1708 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ 1709 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ 1710 | CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ 1711 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ 1712 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ 1713 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ 1714 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ 1715 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 1716 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 1717 | CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ 1718 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ 1719 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ 1720 | CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ 1721 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ 1722 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ 1723 | CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ 1724 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ 1725 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ 1726 | CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ 1727 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ 1728 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ 1729 | CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ 1730 | CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ 1731 | CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ 1732 | CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ 1733 | CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ 1734 | CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ 1735 | CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ 1736 | CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ 1737 | CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ 1738 | CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ 1739 | CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ 1740 | CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ 1741 | CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ 1742 | CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ 1743 | CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ 1744 | CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ 1745 | CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ 1746 | CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ 1747 | CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ 1748 | CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ 1749 | CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ 1750 | CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ 1751 | CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ 1752 | CONFIG.PCW_USB0_RESET_ENABLE {1} \ 1753 | CONFIG.PCW_USB0_RESET_IO {MIO 46} \ 1754 | CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ 1755 | CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ 1756 | CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ 1757 | CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ 1758 | CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ 1759 | CONFIG.PCW_USB1_RESET_ENABLE {0} \ 1760 | CONFIG.PCW_USB_RESET_ENABLE {1} \ 1761 | CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ 1762 | CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ 1763 | CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ 1764 | CONFIG.PCW_USE_AXI_NONSECURE {0} \ 1765 | CONFIG.PCW_USE_CORESIGHT {0} \ 1766 | CONFIG.PCW_USE_CROSS_TRIGGER {0} \ 1767 | CONFIG.PCW_USE_CR_FABRIC {1} \ 1768 | CONFIG.PCW_USE_DDR_BYPASS {0} \ 1769 | CONFIG.PCW_USE_DEBUG {0} \ 1770 | CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ 1771 | CONFIG.PCW_USE_DMA0 {0} \ 1772 | CONFIG.PCW_USE_DMA1 {0} \ 1773 | CONFIG.PCW_USE_DMA2 {0} \ 1774 | CONFIG.PCW_USE_DMA3 {0} \ 1775 | CONFIG.PCW_USE_EXPANDED_IOP {0} \ 1776 | CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ 1777 | CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ 1778 | CONFIG.PCW_USE_HIGH_OCM {0} \ 1779 | CONFIG.PCW_USE_M_AXI_GP0 {1} \ 1780 | CONFIG.PCW_USE_M_AXI_GP1 {0} \ 1781 | CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ 1782 | CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ 1783 | CONFIG.PCW_USE_S_AXI_ACP {0} \ 1784 | CONFIG.PCW_USE_S_AXI_GP0 {0} \ 1785 | CONFIG.PCW_USE_S_AXI_GP1 {0} \ 1786 | CONFIG.PCW_USE_S_AXI_HP0 {1} \ 1787 | CONFIG.PCW_USE_S_AXI_HP1 {0} \ 1788 | CONFIG.PCW_USE_S_AXI_HP2 {1} \ 1789 | CONFIG.PCW_USE_S_AXI_HP3 {0} \ 1790 | CONFIG.PCW_USE_TRACE {0} \ 1791 | CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ 1792 | CONFIG.PCW_VALUE_SILVERSION {3} \ 1793 | CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ 1794 | CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ 1795 | CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ 1796 | CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ 1797 | ] $processing_system7_0 1798 | 1799 | # Create instance: video 1800 | create_hier_cell_video [current_bd_instance .] video 1801 | 1802 | # Create instance: xlconcat_0, and set properties 1803 | set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] 1804 | set_property -dict [ list \ 1805 | CONFIG.IN0_WIDTH {6} \ 1806 | CONFIG.IN1_WIDTH {2} \ 1807 | ] $xlconcat_0 1808 | 1809 | # Create interface connections 1810 | connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins video/S_AXI] 1811 | connect_bd_intf_net -intf_net S_AXI_CTRL_1 [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins image_filters/S_AXI_CTRL] 1812 | connect_bd_intf_net -intf_net TMDS_in_0_1 [get_bd_intf_ports hdmi_in] [get_bd_intf_pins video/TMDS_in] 1813 | connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_interconnect_1/S01_AXI] [get_bd_intf_pins image_filters/M_AXI_MM2S] 1814 | connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_interconnect_1/S02_AXI] [get_bd_intf_pins image_filters/M_AXI_S2MM] 1815 | connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins axi_interconnect_0/M01_AXI] 1816 | connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] 1817 | connect_bd_intf_net -intf_net dvi2rgb_0_DDC [get_bd_intf_ports hdmi_in_ddc] [get_bd_intf_pins video/DDC] 1818 | connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] 1819 | connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] 1820 | connect_bd_intf_net -intf_net processing_system7_0_IIC_0 [get_bd_intf_ports hdmi_out_ddc] [get_bd_intf_pins processing_system7_0/IIC_0] 1821 | connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] 1822 | connect_bd_intf_net -intf_net video_M_AXI [get_bd_intf_pins processing_system7_0/S_AXI_HP2] [get_bd_intf_pins video/M_AXI] 1823 | connect_bd_intf_net -intf_net video_TMDS1 [get_bd_intf_ports hdmi_out] [get_bd_intf_pins video/TMDS_out] 1824 | 1825 | # Create port connections 1826 | connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins processing_system7_0/IRQ_F2P] 1827 | connect_bd_net -net image_filters_dout [get_bd_pins image_filters/dout] [get_bd_pins xlconcat_0/In1] 1828 | connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_fclk0/interconnect_aresetn] [get_bd_pins video/ic_resetn_clk100M] 1829 | connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins image_filters/clk_100M_aresetn] [get_bd_pins proc_sys_reset_fclk0/peripheral_aresetn] [get_bd_pins video/periph_resetn_clk100M] 1830 | connect_bd_net -net proc_sys_reset_fclk1_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins axi_interconnect_1/S01_ARESETN] [get_bd_pins axi_interconnect_1/S02_ARESETN] [get_bd_pins proc_sys_reset_fclk1/interconnect_aresetn] [get_bd_pins video/ic_resetn_clk142M] 1831 | connect_bd_net -net proc_sys_reset_fclk1_peripheral_aresetn [get_bd_pins image_filters/clk_142M_aresetn] [get_bd_pins proc_sys_reset_fclk1/peripheral_aresetn] [get_bd_pins video/periph_resetn_clk142M] 1832 | connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins image_filters/clk_100M] [get_bd_pins proc_sys_reset_fclk0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins video/clk_100M] 1833 | connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins axi_interconnect_1/S01_ACLK] [get_bd_pins axi_interconnect_1/S02_ACLK] [get_bd_pins image_filters/clk_142M] [get_bd_pins proc_sys_reset_fclk1/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins video/clk_142M] 1834 | connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_pins processing_system7_0/FCLK_CLK2] [get_bd_pins video/clk_200M] 1835 | connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_fclk0/ext_reset_in] [get_bd_pins proc_sys_reset_fclk1/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins video/system_resetn] 1836 | connect_bd_net -net video_hdmi_in_hpd [get_bd_ports hdmi_in_hpd] [get_bd_pins video/hdmi_in_hpd] 1837 | connect_bd_net -net video_hdmi_out_hpd [get_bd_ports hdmi_out_hpd] [get_bd_pins video/hdmi_out_hpd] 1838 | connect_bd_net -net video_video_irq [get_bd_pins video/video_irq] [get_bd_pins xlconcat_0/In0] 1839 | connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout] 1840 | 1841 | # Create address segments 1842 | create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg 1843 | create_bd_addr_seg -range 0x00010000 -offset 0x43C90000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_out/frontend/axi_dynclk/s00_axi/reg0] SEG_axi_dynclk_reg0 1844 | create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_in/frontend/axi_gpio_hdmiin/S_AXI/Reg] SEG_axi_gpio_hdmiin_Reg 1845 | create_bd_addr_seg -range 0x00010000 -offset 0x41800000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] SEG_axi_intc_0_Reg 1846 | create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/axi_vdma/S_AXI_LITE/Reg] SEG_axi_vdma_Reg 1847 | create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/canny_edge_0/s_axi_CONTROL_BUS/Reg] SEG_canny_edge_0_Reg 1848 | create_bd_addr_seg -range 0x00010000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_in/color_convert/s_axi_AXILiteS/Reg] SEG_color_convert_Reg 1849 | create_bd_addr_seg -range 0x00010000 -offset 0x43C80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_out/color_convert/s_axi_AXILiteS/Reg] SEG_color_convert_Reg8 1850 | create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/dilate_hls_0/s_axi_CONTROL_BUS/Reg] SEG_dilate_hls_0_Reg 1851 | create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/erode_hls_0/s_axi_CONTROL_BUS/Reg] SEG_erode_hls_0_Reg 1852 | create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/filter2D_f_0/s_axi_CONTROL_BUS/Reg] SEG_filter2D_f_0_Reg 1853 | create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/filter2D_hls_0/s_axi_CONTROL_BUS/Reg] SEG_filter2D_hls_0_Reg 1854 | create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/filter2D_hls_5_0/s_axi_CONTROL_BUS/Reg] SEG_filter2D_hls_5_0_Reg 1855 | create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_out/frontend/hdmi_out_hpd_video/S_AXI/Reg] SEG_hdmi_out_hpd_video_Reg 1856 | create_bd_addr_seg -range 0x00010000 -offset 0x43C70000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_in/pixel_pack/s_axi_AXILiteS/Reg] SEG_pixel_pack_Reg 1857 | create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_out/pixel_unpack/s_axi_AXILiteS/Reg] SEG_pixel_unpack_Reg 1858 | create_bd_addr_seg -range 0x00010000 -offset 0x43C60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_in/frontend/vtc_in/ctrl/Reg] SEG_vtc_in_Reg 1859 | create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video/hdmi_out/frontend/vtc_out/ctrl/Reg] SEG_vtc_out_Reg 1860 | create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/axis_interconnect_2/xbar/S_AXI_CTRL/Reg] SEG_xbar_Reg 1861 | create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs image_filters/axis_interconnect_1/xbar/S_AXI_CTRL/Reg] SEG_xbar_Reg1 1862 | create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces image_filters/axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM 1863 | create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces image_filters/axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM 1864 | create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces video/axi_vdma/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM 1865 | create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces video/axi_vdma/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM 1866 | 1867 | 1868 | # Restore current instance 1869 | current_bd_instance $oldCurInst 1870 | 1871 | save_bd_design 1872 | } 1873 | # End of create_root_design() 1874 | 1875 | 1876 | ################################################################## 1877 | # MAIN FLOW 1878 | ################################################################## 1879 | 1880 | create_root_design "" 1881 | 1882 | 1883 | --------------------------------------------------------------------------------