├── .gitignore ├── README.md ├── ipcore ├── drm_fifo24to24 │ ├── .last_generated │ ├── .settings │ ├── drm_fifo24to24.idf │ ├── drm_fifo24to24.v │ ├── drm_fifo24to24_prefetch.v │ ├── drm_fifo24to24_tb.v │ ├── drm_fifo24to24_tmpl.v │ ├── drm_fifo24to24_tmpl.vhdl │ └── rtl │ │ ├── ipml_fifo_ctrl_v1_3.v │ │ ├── ipml_fifo_v1_6_drm_fifo24to24.v │ │ ├── ipml_prefetch_fifo_v1_6_drm_fifo24to24.v │ │ ├── ipml_reg_fifo_v1_0.v │ │ └── ipml_sdpram_v1_6_drm_fifo24to24.v ├── frame_2_pcie_buf │ ├── .last_generated │ ├── .settings │ ├── frame_2_pcie_buf.idf │ ├── frame_2_pcie_buf.v │ ├── frame_2_pcie_buf_tb.v │ ├── frame_2_pcie_buf_tmpl.v │ ├── frame_2_pcie_buf_tmpl.vhdl │ ├── init_param_bin_exmp.dat │ ├── init_param_hex_exmp.dat │ └── rtl │ │ ├── frame_2_pcie_buf_init_param.v │ │ └── ipml_sdpram_v1_6_frame_2_pcie_buf.v ├── frame_2_pcie_fifo │ ├── .last_generated │ ├── .settings │ ├── frame_2_pcie_fifo.idf │ ├── frame_2_pcie_fifo.v │ ├── frame_2_pcie_fifo_prefetch.v │ ├── frame_2_pcie_fifo_tb.v │ ├── frame_2_pcie_fifo_tmpl.v │ ├── frame_2_pcie_fifo_tmpl.vhdl │ └── rtl │ │ ├── ipml_fifo_ctrl_v1_3.v │ │ ├── ipml_fifo_v1_6_frame_2_pcie_fifo.v │ │ ├── ipml_prefetch_fifo_v1_6_frame_2_pcie_fifo.v │ │ ├── ipml_reg_fifo_v1_0.v │ │ └── ipml_sdpram_v1_6_frame_2_pcie_fifo.v ├── gen_en_fifo │ ├── .last_generated │ ├── .settings │ ├── gen_en_fifo.idf │ ├── gen_en_fifo.v │ ├── gen_en_fifo_prefetch.v │ ├── gen_en_fifo_tb.v │ ├── gen_en_fifo_tmpl.v │ ├── gen_en_fifo_tmpl.vhdl │ └── rtl │ │ ├── ipml_fifo_ctrl_v1_3.v │ │ ├── ipml_fifo_v1_6_gen_en_fifo.v │ │ ├── ipml_prefetch_fifo_v1_6_gen_en_fifo.v │ │ ├── ipml_reg_fifo_v1_0.v │ │ └── ipml_sdpram_v1_6_gen_en_fifo.v ├── icmp_rx_ram_8_256 │ ├── .last_generated │ ├── .settings │ ├── icmp_rx_ram_8_256.idf │ ├── icmp_rx_ram_8_256.v │ ├── icmp_rx_ram_8_256_tb.v │ ├── icmp_rx_ram_8_256_tmpl.v │ ├── icmp_rx_ram_8_256_tmpl.vhdl │ ├── init_param_bin_exmp.dat │ ├── init_param_hex_exmp.dat │ └── rtl │ │ ├── icmp_rx_ram_8_256_init_param.v │ │ └── ipml_sdpram_v1_6_icmp_rx_ram_8_256.v ├── ip_ddr3 │ ├── .last_generated │ ├── .settings │ ├── example_design │ │ ├── bench │ │ │ ├── ddr3_tb │ │ │ │ └── ddr_test_top_tb.v │ │ │ └── mem │ │ │ │ ├── ddr3.v │ │ │ │ └── ddr3_parameters.vh │ │ └── rtl │ │ │ ├── axi_bist_top_v1_0.v │ │ │ ├── prbs15_64bit_v1_0.v │ │ │ ├── prbs31_128bit_v1_0.v │ │ │ ├── test_ddr.v │ │ │ ├── test_main_ctrl_v1_0.v │ │ │ ├── test_rd_ctrl_v1_0.v │ │ │ ├── test_wr_ctrl_v1_0.v │ │ │ ├── uart_ctrl_32bit │ │ │ ├── ipsxb_clk_gen_32bit.v │ │ │ ├── ipsxb_cmd_parser_32bit.v │ │ │ ├── ipsxb_seu_rs232_intf.v │ │ │ ├── ipsxb_seu_uart_rx.v │ │ │ ├── ipsxb_seu_uart_tx.v │ │ │ ├── ipsxb_uart_ctrl_32bit.v │ │ │ ├── ipsxb_uart_ctrl_top_32bit.v │ │ │ └── ipsxb_ver_ctrl_32bit.v │ │ │ └── uart_rd_lock.v │ ├── generate.log │ ├── ip_ddr3.idf │ ├── ip_ddr3.v │ ├── ip_ddr3_ddrphy_top.v │ ├── ip_ddr3_tmpl.v │ ├── ip_ddr3_tmpl.vhdl │ ├── pnr │ │ ├── ddr_test.fdc │ │ ├── ip_ddr3.pds │ │ └── ip_ddr3.rcf │ ├── readme.txt │ ├── rtl │ │ ├── ddrphy │ │ │ ├── ipsxb_ddrphy_calib_mux_v1_3.vp │ │ │ ├── ipsxb_ddrphy_calib_top_v1_3.vp │ │ │ ├── ipsxb_ddrphy_control_path_adj_v1_0.vp │ │ │ ├── ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3.vp │ │ │ ├── ipsxb_ddrphy_data_slice_v1_4.vp │ │ │ ├── ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp │ │ │ ├── ipsxb_ddrphy_dfi_v1_4.vp │ │ │ ├── ipsxb_ddrphy_dll_update_ctrl_v1_0.vp │ │ │ ├── ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp │ │ │ ├── ipsxb_ddrphy_dqs_rddata_align_v1_3.vp │ │ │ ├── ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp │ │ │ ├── ipsxb_ddrphy_drift_ctrl_v1_3.vp │ │ │ ├── ipsxb_ddrphy_gate_update_ctrl_v1_3.vp │ │ │ ├── ipsxb_ddrphy_gatecal_v1_3.vp │ │ │ ├── ipsxb_ddrphy_info_v1_0.vp │ │ │ ├── ipsxb_ddrphy_init_v1_0.vp │ │ │ ├── ipsxb_ddrphy_main_ctrl_v1_3.vp │ │ │ ├── ipsxb_ddrphy_rdcal_v1_2.vp │ │ │ ├── ipsxb_ddrphy_reset_ctrl_v1_4.vp │ │ │ ├── ipsxb_ddrphy_rst_debounce_v1_0.vp │ │ │ ├── ipsxb_ddrphy_slice_rddata_align_v1_0.vp │ │ │ ├── ipsxb_ddrphy_slice_top_v1_4.v │ │ │ ├── ipsxb_ddrphy_training_ctrl_v1_0.vp │ │ │ ├── ipsxb_ddrphy_upcal_v1_4.vp │ │ │ ├── ipsxb_ddrphy_wdata_path_adj_v1_0.vp │ │ │ └── ipsxb_ddrphy_wrlvl_v1_0.vp │ │ ├── ipsxb_rst_sync_v1_1.v │ │ ├── mcdq_ctrl │ │ │ ├── distributed_fifo │ │ │ │ ├── ipsxb_distributed_fifo_v1_0.v │ │ │ │ └── rtl │ │ │ │ │ ├── ipsxb_distributed_fifo_ctr_v1_0.v │ │ │ │ │ ├── ipsxb_distributed_fifo_v1_0_distributed_fifo_v1_0.v │ │ │ │ │ └── ipsxb_distributed_sdpram_v1_0_distributed_fifo_v1_0.v │ │ │ ├── ipsxb_mcdq_apb_cross_v1_2.vp │ │ │ ├── ipsxb_mcdq_calib_delay_v1_2.vp │ │ │ ├── ipsxb_mcdq_cfg_apb_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_bm_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_rowaddr_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_sm_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_top_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_back_ctrl_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_buf_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_out_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_top_v1_2.vp │ │ │ ├── ipsxb_mcdq_dfi_v1_2.vp │ │ │ ├── ipsxb_mcdq_lp_v1_2.vp │ │ │ ├── ipsxb_mcdq_mrs_v1_2.vp │ │ │ ├── ipsxb_mcdq_prefetch_fifo_v1_2.vp │ │ │ ├── ipsxb_mcdq_rdatapath_v1_2.vp │ │ │ ├── ipsxb_mcdq_reg_fifo2_v1_2.vp │ │ │ ├── ipsxb_mcdq_ui_axi_v1_2.vp │ │ │ ├── ipsxb_mcdq_wdatapath_v1_2.vp │ │ │ ├── ipsxb_mcdq_wdp_align_v1_2.vp │ │ │ ├── ipsxb_mcdq_wdp_dcp_v1_2.vp │ │ │ ├── ipsxb_mcdq_wrapper_v1_2a.vp │ │ │ └── syn_mod │ │ │ │ ├── ipsxb_mcdq_com_timing_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_tfaw_timing_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_tfaw_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_act2wr_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_act_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_pre_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_rd_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_ref_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_wr_pass_v1_2.vp │ │ │ │ └── ipsxb_mcdq_trc_timing_v1_2.vp │ │ └── pll │ │ │ └── ipsxb_ddrphy_pll_v1_0.v │ ├── sim │ │ ├── modelsim │ │ │ ├── sim.tcl │ │ │ └── sim_file_list.f │ │ └── vcs │ │ │ ├── makefile │ │ │ └── sim_file_list.f │ └── sim_lib │ │ └── rtl │ │ ├── ddrphy │ │ ├── ipsxb_ddrphy_calib_mux_v1_3.vp │ │ ├── ipsxb_ddrphy_calib_top_v1_3.vp │ │ ├── ipsxb_ddrphy_control_path_adj_v1_0.vp │ │ ├── ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3.vp │ │ ├── ipsxb_ddrphy_data_slice_v1_4.vp │ │ ├── ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp │ │ ├── ipsxb_ddrphy_dfi_v1_4.vp │ │ ├── ipsxb_ddrphy_dll_update_ctrl_v1_0.vp │ │ ├── ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp │ │ ├── ipsxb_ddrphy_dqs_rddata_align_v1_3.vp │ │ ├── ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp │ │ ├── ipsxb_ddrphy_drift_ctrl_v1_3.vp │ │ ├── ipsxb_ddrphy_gate_update_ctrl_v1_3.vp │ │ ├── ipsxb_ddrphy_gatecal_v1_3.vp │ │ ├── ipsxb_ddrphy_info_v1_0.vp │ │ ├── ipsxb_ddrphy_init_v1_0.vp │ │ ├── ipsxb_ddrphy_main_ctrl_v1_3.vp │ │ ├── ipsxb_ddrphy_rdcal_v1_2.vp │ │ ├── ipsxb_ddrphy_reset_ctrl_v1_4.vp │ │ ├── ipsxb_ddrphy_rst_debounce_v1_0.vp │ │ ├── ipsxb_ddrphy_slice_rddata_align_v1_0.vp │ │ ├── ipsxb_ddrphy_training_ctrl_v1_0.vp │ │ ├── ipsxb_ddrphy_upcal_v1_4.vp │ │ ├── ipsxb_ddrphy_wdata_path_adj_v1_0.vp │ │ └── ipsxb_ddrphy_wrlvl_v1_0.vp │ │ └── mcdq_ctrl │ │ ├── distributed_fifo │ │ ├── ipsxb_distributed_fifo_v1_0.v │ │ └── rtl │ │ │ ├── ipsxb_distributed_fifo_ctr_v1_0.v │ │ │ ├── ipsxb_distributed_fifo_v1_0_distributed_fifo_v1_0.v │ │ │ └── ipsxb_distributed_sdpram_v1_0_distributed_fifo_v1_0.v │ │ ├── ipsxb_mcdq_apb_cross_v1_2.vp │ │ ├── ipsxb_mcdq_calib_delay_v1_2.vp │ │ ├── ipsxb_mcdq_cfg_apb_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_bm_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_rowaddr_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_sm_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_top_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_back_ctrl_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_buf_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_out_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_top_v1_2.vp │ │ ├── ipsxb_mcdq_dfi_v1_2.vp │ │ ├── ipsxb_mcdq_lp_v1_2.vp │ │ ├── ipsxb_mcdq_mrs_v1_2.vp │ │ ├── ipsxb_mcdq_prefetch_fifo_v1_2.vp │ │ ├── ipsxb_mcdq_rdatapath_v1_2.vp │ │ ├── ipsxb_mcdq_reg_fifo2_v1_2.vp │ │ ├── ipsxb_mcdq_ui_axi_v1_2.vp │ │ ├── ipsxb_mcdq_wdatapath_v1_2.vp │ │ ├── ipsxb_mcdq_wdp_align_v1_2.vp │ │ ├── ipsxb_mcdq_wdp_dcp_v1_2.vp │ │ ├── ipsxb_mcdq_wrapper_v1_2a.vp │ │ └── syn_mod │ │ ├── ipsxb_mcdq_com_timing_v1_2.vp │ │ ├── ipsxb_mcdq_tfaw_timing_v1_2.vp │ │ ├── ipsxb_mcdq_tfaw_v1_2.vp │ │ ├── ipsxb_mcdq_timing_act2wr_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_act_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_pre_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_rd_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_ref_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_wr_pass_v1_2.vp │ │ └── ipsxb_mcdq_trc_timing_v1_2.vp ├── ip_pcie │ ├── .last_generated │ ├── .settings │ ├── example_design │ │ ├── bench │ │ │ ├── ipsl_pcie_wrap_v1_3_sim.v │ │ │ ├── pango_pcie_top.v │ │ │ ├── pango_pcie_top_sim.v │ │ │ └── pango_pcie_top_tb.v │ │ └── rtl │ │ │ ├── ipsl_expd_apb_mux.v │ │ │ ├── ipsl_pcie_cfg_ctrl │ │ │ └── rtl │ │ │ │ ├── ipsl_pcie_cfg_ctrl.v │ │ │ │ ├── ipsl_pcie_cfg_ctrl_apb.v │ │ │ │ └── ipsl_pcie_cfg_trans.v │ │ │ ├── ipsl_pcie_dma_ctrl │ │ │ ├── fifo │ │ │ │ ├── ipm_distributed_sdpram_v1_2_distributed_fifo.v │ │ │ │ ├── pgs_pciex4_fifo_ctrl.v │ │ │ │ └── pgs_pciex4_fifo_v1_2.v │ │ │ ├── ipm_distributed_sdpram_v1_2.v │ │ │ ├── ipsl_pcie_dma.v │ │ │ ├── ipsl_pcie_dma_controller.v │ │ │ ├── ipsl_pcie_dma_cpld_tx_ctrl.v │ │ │ ├── ipsl_pcie_dma_mrd_tx_ctrl.v │ │ │ ├── ipsl_pcie_dma_mwr_tx_ctrl.v │ │ │ ├── ipsl_pcie_dma_ram │ │ │ │ ├── ipsl_pcie_dma_ram.v │ │ │ │ └── rtl │ │ │ │ │ ├── ipml_sdpram_v1_5_ipsl_pcie_dma_ram.v │ │ │ │ │ └── ipsl_pcie_dma_ram_init_param.v │ │ │ ├── ipsl_pcie_dma_rd_ctrl.v │ │ │ ├── ipsl_pcie_dma_rx_cpld_wr_ctrl.v │ │ │ ├── ipsl_pcie_dma_rx_mwr_wr_ctrl.v │ │ │ ├── ipsl_pcie_dma_rx_top.v │ │ │ ├── ipsl_pcie_dma_tlp_rcv.v │ │ │ ├── ipsl_pcie_dma_tlp_tx_mux.v │ │ │ ├── ipsl_pcie_dma_tx_cpld_rd_ctrl.v │ │ │ ├── ipsl_pcie_dma_tx_mwr_rd_ctrl.v │ │ │ ├── ipsl_pcie_dma_tx_top.v │ │ │ ├── ipsl_pcie_dma_wr_ctrl.v │ │ │ ├── ipsl_pcie_reg.v │ │ │ └── pgs_pciex4_prefetch_fifo_v1_2.v │ │ │ └── uart2apb_32bit │ │ │ ├── fifo │ │ │ ├── pgm_distributed_fifo_ctr_v1_0.v │ │ │ ├── pgm_distributed_fifo_v1_1.v │ │ │ ├── pgm_distributed_sdpram_v1_1.v │ │ │ └── pgr_prefetch_fifo.v │ │ │ ├── pgr_apb_ctr_32bit.v │ │ │ ├── pgr_apb_mif_32bit.v │ │ │ ├── pgr_clk_gen_32bit.v │ │ │ ├── pgr_cmd_parser_32bit.v │ │ │ ├── pgr_fifo_top_32bit.v │ │ │ ├── pgr_uart2apb_top_32bit.v │ │ │ ├── pgr_uart_rx_32bit.v │ │ │ ├── pgr_uart_top_32bit.v │ │ │ ├── pgr_uart_tx_32bit.v │ │ │ └── rstn_sync_32bit.v │ ├── generate.log │ ├── ip_pcie.idf │ ├── ip_pcie.v │ ├── ip_pcie_tmpl.v │ ├── ip_pcie_tmpl.vhdl │ ├── pnr │ │ ├── core_only │ │ │ ├── ip_pcie.fdc │ │ │ └── ip_pcie.pds │ │ └── example_design │ │ │ ├── pango_pcie_top.fdc │ │ │ └── pango_pcie_top.pds │ ├── readme.txt │ ├── rtl │ │ ├── ipml_pcie_hsst │ │ │ ├── ipml_pcie_hsst_x1_top.v │ │ │ ├── ipml_pcie_hsst_x2_top.v │ │ │ ├── ipml_pcie_hsst_x4_top.v │ │ │ └── rtl │ │ │ │ ├── ipml_hsst_rst │ │ │ │ ├── ipml_hsst_fifo_clr_v1_0.v │ │ │ │ ├── ipml_hsst_lane_powerup_v1_0.v │ │ │ │ ├── ipml_hsst_pll_rst_fsm_v1_0.v │ │ │ │ ├── ipml_hsst_rst_debounce_v1_0.v │ │ │ │ ├── ipml_hsst_rst_pll_v1_0.v │ │ │ │ ├── ipml_hsst_rst_rx_v1_1.v │ │ │ │ ├── ipml_hsst_rst_sync_v1_0.v │ │ │ │ ├── ipml_hsst_rst_tx_v1_0.v │ │ │ │ ├── ipml_hsst_rst_v1_1.v │ │ │ │ ├── ipml_hsst_rst_wtchdg_v1_0.v │ │ │ │ ├── ipml_hsst_rxlane_rst_fsm_v1_1.v │ │ │ │ └── ipml_hsst_txlane_rst_fsm_v1_0.v │ │ │ │ ├── ipml_pcie_hsst_x1_wrapper_v1_3e.v │ │ │ │ ├── ipml_pcie_hsst_x2_wrapper_v1_3e.v │ │ │ │ └── ipml_pcie_hsst_x4_wrapper_v1_3e.v │ │ ├── ipsl_pcie_apb2dbi_v1_0.v │ │ ├── ipsl_pcie_apb_cross_v1_0.v │ │ ├── ipsl_pcie_apb_mux_v1_1.v │ │ ├── ipsl_pcie_cfg_init_v1_3.v │ │ ├── ipsl_pcie_ext_ram │ │ │ ├── ipsl_pcie_ext_rcvd_ram │ │ │ │ ├── ipsl_pcie_ext_rcvd_ram.v │ │ │ │ └── rtl │ │ │ │ │ ├── ipml_sdpram_v1_5_ipsl_pcie_ext_rcvd_ram.v │ │ │ │ │ └── ipsl_pcie_ext_rcvd_ram_init_param.v │ │ │ ├── ipsl_pcie_ext_rcvh_ram │ │ │ │ ├── ipsl_pcie_ext_rcvh_ram.v │ │ │ │ └── rtl │ │ │ │ │ ├── ipml_sdpram_v1_5_ipsl_pcie_ext_rcvh_ram.v │ │ │ │ │ └── ipsl_pcie_ext_rcvh_ram_init_param.v │ │ │ └── ipsl_pcie_retryd_ram │ │ │ │ ├── ipsl_pcie_retryd_ram.v │ │ │ │ └── rtl │ │ │ │ ├── ipml_spram_v1_4_ipsl_pcie_retryd_ram.v │ │ │ │ └── ipsl_pcie_retryd_ram_init_param.v │ │ ├── ipsl_pcie_hard_ctrl_v1_3.v │ │ ├── ipsl_pcie_pipe │ │ │ ├── hsst_rst_cross_sync_v1_0.v │ │ │ ├── hsst_rst_debounce_v1_0.v │ │ │ ├── hsst_rst_wtchdg_v1_0.v │ │ │ ├── hsstl_phy_mac_rdata_proc.v │ │ │ ├── hsstl_rst4mcrsw_rx_init_v1_0.v │ │ │ ├── hsstl_rst4mcrsw_rx_rst_fsm_v1_0.v │ │ │ ├── hsstl_rst4mcrsw_rx_rst_initfsm_v1_0.v │ │ │ ├── hsstl_rst4mcrsw_rx_v1_0.v │ │ │ ├── hsstl_rst4mcrsw_tx_rst_fsm_v1_1.v │ │ │ ├── hsstl_rst4mcrsw_tx_v1_0.v │ │ │ └── hsstl_rst4mcrsw_v1_0.v │ │ ├── ipsl_pcie_seio_intf_v1_0.v │ │ ├── ipsl_pcie_soft_phy_v1_2a.v │ │ ├── ipsl_pcie_sync_v1_0.v │ │ └── ipsl_pcie_top_v1_3.v │ └── sim │ │ └── modelsim │ │ ├── DWC_pcie_ctl_cc_constants.svh │ │ ├── include │ │ ├── DWC_pcie_ctl_all_defs.svh │ │ ├── adm_defs.svh │ │ ├── cap_port_cfg.svh │ │ ├── cxpl_defs.svh │ │ ├── pcie_defs.svh │ │ ├── pipe_defines.svh │ │ ├── port_cfg.svh │ │ └── radm_defs.svh │ │ ├── ipsl_pcie_dma_ram_init_param.v │ │ ├── ipsl_pcie_ext_rcvd_ram_init_param.v │ │ ├── ipsl_pcie_ext_rcvh_ram_init_param.v │ │ ├── ipsl_pcie_retryd_ram_init_param.v │ │ ├── pango_pcie_top_filelist.f │ │ ├── pango_pcie_top_sim.do │ │ ├── pango_pcie_top_wave.do │ │ ├── power_management │ │ └── DWC_pcie_pm_pkg.svh │ │ └── sim.bat ├── ip_pll │ ├── .last_generated │ ├── .settings │ ├── generate.log │ ├── ip_pll.idf │ ├── ip_pll.v │ ├── ip_pll_tb.v │ ├── ip_pll_tmpl.v │ └── ip_pll_tmpl.vhdl ├── pcie_rd_fram_buf │ ├── .last_generated │ ├── .settings │ ├── generate.log │ ├── init_param_bin_exmp.dat │ ├── init_param_hex_exmp.dat │ ├── pcie_rd_fram_buf.idf │ ├── pcie_rd_fram_buf.v │ ├── pcie_rd_fram_buf_tb.v │ ├── pcie_rd_fram_buf_tmpl.v │ ├── pcie_rd_fram_buf_tmpl.vhdl │ └── rtl │ │ ├── ipml_sdpram_v1_6_pcie_rd_fram_buf.v │ │ └── pcie_rd_fram_buf_init_param.v ├── rd_fram_buf │ ├── .last_generated │ ├── .settings │ ├── init_param_bin_exmp.dat │ ├── init_param_hex_exmp.dat │ ├── rd_fram_buf.idf │ ├── rd_fram_buf.v │ ├── rd_fram_buf_tb.v │ ├── rd_fram_buf_tmpl.v │ ├── rd_fram_buf_tmpl.vhdl │ └── rtl │ │ ├── ipml_sdpram_v1_6_rd_fram_buf.v │ │ └── rd_fram_buf_init_param.v ├── sync_fifo │ ├── .last_generated │ ├── .settings │ ├── rtl │ │ ├── ipml_fifo_ctrl_v1_3.v │ │ ├── ipml_fifo_v1_6_sync_fifo.v │ │ ├── ipml_prefetch_fifo_v1_6_sync_fifo.v │ │ ├── ipml_reg_fifo_v1_0.v │ │ └── ipml_sdpram_v1_6_sync_fifo.v │ ├── sync_fifo.idf │ ├── sync_fifo.v │ ├── sync_fifo_prefetch.v │ ├── sync_fifo_tb.v │ ├── sync_fifo_tmpl.v │ └── sync_fifo_tmpl.vhdl ├── ttt │ ├── .settings │ └── ttt.idf ├── udp_shift_register │ ├── .last_generated │ ├── .settings │ ├── rtl │ │ ├── ipm_distributed_sdpram_v1_2_udp_shift_register.v │ │ └── ipm_distributed_shiftregister_v1_3_udp_shift_register.v │ ├── udp_shift_register.idf │ ├── udp_shift_register.v │ ├── udp_shift_register_tb.v │ ├── udp_shift_register_tmpl.v │ └── udp_shift_register_tmpl.vhdl ├── video_fifo │ ├── .last_generated │ ├── .settings │ ├── rtl │ │ ├── ipml_fifo_ctrl_v1_3.v │ │ ├── ipml_fifo_v1_6_video_fifo.v │ │ ├── ipml_prefetch_fifo_v1_6_video_fifo.v │ │ ├── ipml_reg_fifo_v1_0.v │ │ └── ipml_sdpram_v1_6_video_fifo.v │ ├── video_fifo.idf │ ├── video_fifo.v │ ├── video_fifo_prefetch.v │ ├── video_fifo_tb.v │ ├── video_fifo_tmpl.v │ └── video_fifo_tmpl.vhdl └── wr_fram_buf │ ├── .last_generated │ ├── .settings │ ├── generate.log │ ├── init_param_bin_exmp.dat │ ├── init_param_hex_exmp.dat │ ├── rtl │ ├── ipml_sdpram_v1_6_wr_fram_buf.v │ └── wr_fram_buf_init_param.v │ ├── wr_fram_buf.idf │ ├── wr_fram_buf.v │ ├── wr_fram_buf_tb.v │ ├── wr_fram_buf_tmpl.v │ └── wr_fram_buf_tmpl.vhdl ├── pango_hdmi_pcie_ai_acc.pds └── source ├── TOP.v ├── delay.v ├── last.fdc ├── pcie_trans.v ├── rtl ├── DDR3_50H │ ├── .last_generated │ ├── .settings │ ├── DDR3_50H.idf │ ├── DDR3_50H.v │ ├── DDR3_50H_ddrphy_top.v │ ├── DDR3_50H_tmpl.v │ ├── DDR3_50H_tmpl.vhdl │ ├── example_design │ │ ├── bench │ │ │ ├── ddr3_tb │ │ │ │ └── ddr_test_top_tb.v │ │ │ └── mem │ │ │ │ ├── ddr3.v │ │ │ │ └── ddr3_parameters.vh │ │ └── rtl │ │ │ ├── axi_bist_top_v1_0.v │ │ │ ├── prbs15_64bit_v1_0.v │ │ │ ├── prbs31_128bit_v1_0.v │ │ │ ├── test_ddr.v │ │ │ ├── test_main_ctrl_v1_0.v │ │ │ ├── test_rd_ctrl_v1_0.v │ │ │ ├── test_wr_ctrl_v1_0.v │ │ │ ├── uart_ctrl_32bit │ │ │ ├── ipsxb_clk_gen_32bit.v │ │ │ ├── ipsxb_cmd_parser_32bit.v │ │ │ ├── ipsxb_seu_rs232_intf.v │ │ │ ├── ipsxb_seu_uart_rx.v │ │ │ ├── ipsxb_seu_uart_tx.v │ │ │ ├── ipsxb_uart_ctrl_32bit.v │ │ │ ├── ipsxb_uart_ctrl_top_32bit.v │ │ │ └── ipsxb_ver_ctrl_32bit.v │ │ │ └── uart_rd_lock.v │ ├── pnr │ │ ├── DDR3_50H.backup_1.pds │ │ ├── DDR3_50H.pds │ │ ├── DDR3_50H.rcf │ │ └── ddr_test.fdc │ ├── readme.txt │ ├── rtl │ │ ├── ddrphy │ │ │ ├── ipsxb_ddrphy_calib_mux_v1_3.vp │ │ │ ├── ipsxb_ddrphy_calib_top_v1_3.vp │ │ │ ├── ipsxb_ddrphy_control_path_adj_v1_0.vp │ │ │ ├── ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3.vp │ │ │ ├── ipsxb_ddrphy_data_slice_v1_4.vp │ │ │ ├── ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp │ │ │ ├── ipsxb_ddrphy_dfi_v1_4.vp │ │ │ ├── ipsxb_ddrphy_dll_update_ctrl_v1_0.vp │ │ │ ├── ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp │ │ │ ├── ipsxb_ddrphy_dqs_rddata_align_v1_3.vp │ │ │ ├── ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp │ │ │ ├── ipsxb_ddrphy_drift_ctrl_v1_3.vp │ │ │ ├── ipsxb_ddrphy_gate_update_ctrl_v1_3.vp │ │ │ ├── ipsxb_ddrphy_gatecal_v1_3.vp │ │ │ ├── ipsxb_ddrphy_info_v1_0.vp │ │ │ ├── ipsxb_ddrphy_init_v1_0.vp │ │ │ ├── ipsxb_ddrphy_main_ctrl_v1_3.vp │ │ │ ├── ipsxb_ddrphy_rdcal_v1_2.vp │ │ │ ├── ipsxb_ddrphy_reset_ctrl_v1_4.vp │ │ │ ├── ipsxb_ddrphy_rst_debounce_v1_0.vp │ │ │ ├── ipsxb_ddrphy_slice_rddata_align_v1_0.vp │ │ │ ├── ipsxb_ddrphy_slice_top_v1_4.v │ │ │ ├── ipsxb_ddrphy_training_ctrl_v1_0.vp │ │ │ ├── ipsxb_ddrphy_upcal_v1_4.vp │ │ │ ├── ipsxb_ddrphy_wdata_path_adj_v1_0.vp │ │ │ └── ipsxb_ddrphy_wrlvl_v1_0.vp │ │ ├── ipsxb_rst_sync_v1_1.v │ │ ├── mcdq_ctrl │ │ │ ├── distributed_fifo │ │ │ │ ├── ipsxb_distributed_fifo_v1_0.v │ │ │ │ └── rtl │ │ │ │ │ ├── ipsxb_distributed_fifo_ctr_v1_0.v │ │ │ │ │ ├── ipsxb_distributed_fifo_v1_0_distributed_fifo_v1_0.v │ │ │ │ │ └── ipsxb_distributed_sdpram_v1_0_distributed_fifo_v1_0.v │ │ │ ├── ipsxb_mcdq_apb_cross_v1_2.vp │ │ │ ├── ipsxb_mcdq_calib_delay_v1_2.vp │ │ │ ├── ipsxb_mcdq_cfg_apb_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_bm_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_rowaddr_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_sm_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcd_top_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_back_ctrl_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_buf_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_out_v1_2.vp │ │ │ ├── ipsxb_mcdq_dcp_top_v1_2.vp │ │ │ ├── ipsxb_mcdq_dfi_v1_2.vp │ │ │ ├── ipsxb_mcdq_lp_v1_2.vp │ │ │ ├── ipsxb_mcdq_mrs_v1_2.vp │ │ │ ├── ipsxb_mcdq_prefetch_fifo_v1_2.vp │ │ │ ├── ipsxb_mcdq_rdatapath_v1_2.vp │ │ │ ├── ipsxb_mcdq_reg_fifo2_v1_2.vp │ │ │ ├── ipsxb_mcdq_ui_axi_v1_2.vp │ │ │ ├── ipsxb_mcdq_wdatapath_v1_2.vp │ │ │ ├── ipsxb_mcdq_wdp_align_v1_2.vp │ │ │ ├── ipsxb_mcdq_wdp_dcp_v1_2.vp │ │ │ ├── ipsxb_mcdq_wrapper_v1_2a.vp │ │ │ └── syn_mod │ │ │ │ ├── ipsxb_mcdq_com_timing_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_tfaw_timing_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_tfaw_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_act2wr_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_act_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_pre_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_rd_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_ref_pass_v1_2.vp │ │ │ │ ├── ipsxb_mcdq_timing_wr_pass_v1_2.vp │ │ │ │ └── ipsxb_mcdq_trc_timing_v1_2.vp │ │ └── pll │ │ │ └── ipsxb_ddrphy_pll_v1_0.v │ ├── sim │ │ ├── modelsim │ │ │ ├── image_L.txt │ │ │ ├── modelsim.ini │ │ │ ├── sim.tcl │ │ │ ├── sim_file_list.f │ │ │ ├── sim_path.bak │ │ │ ├── sim_top.bak.v │ │ │ ├── sim_wave.bak │ │ │ ├── transcript │ │ │ ├── vish_stacktrace.vstf │ │ │ ├── vsim.wlf │ │ │ ├── vsim_stacktrace.vstf │ │ │ ├── wave.do │ │ │ ├── wave_def.do │ │ │ ├── wlft537awv │ │ │ └── work │ │ │ │ ├── _info │ │ │ │ ├── _lib.qdb │ │ │ │ ├── _lib1_0.qdb │ │ │ │ ├── _lib1_0.qpg │ │ │ │ ├── _lib1_0.qtl │ │ │ │ └── _vmake │ │ └── vcs │ │ │ ├── makefile │ │ │ └── sim_file_list.f │ └── sim_lib │ │ └── rtl │ │ ├── ddrphy │ │ ├── ipsxb_ddrphy_calib_mux_v1_3.vp │ │ ├── ipsxb_ddrphy_calib_top_v1_3.vp │ │ ├── ipsxb_ddrphy_control_path_adj_v1_0.vp │ │ ├── ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3.vp │ │ ├── ipsxb_ddrphy_data_slice_v1_4.vp │ │ ├── ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp │ │ ├── ipsxb_ddrphy_dfi_v1_4.vp │ │ ├── ipsxb_ddrphy_dll_update_ctrl_v1_0.vp │ │ ├── ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp │ │ ├── ipsxb_ddrphy_dqs_rddata_align_v1_3.vp │ │ ├── ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp │ │ ├── ipsxb_ddrphy_drift_ctrl_v1_3.vp │ │ ├── ipsxb_ddrphy_gate_update_ctrl_v1_3.vp │ │ ├── ipsxb_ddrphy_gatecal_v1_3.vp │ │ ├── ipsxb_ddrphy_info_v1_0.vp │ │ ├── ipsxb_ddrphy_init_v1_0.vp │ │ ├── ipsxb_ddrphy_main_ctrl_v1_3.vp │ │ ├── ipsxb_ddrphy_rdcal_v1_2.vp │ │ ├── ipsxb_ddrphy_reset_ctrl_v1_4.vp │ │ ├── ipsxb_ddrphy_rst_debounce_v1_0.vp │ │ ├── ipsxb_ddrphy_slice_rddata_align_v1_0.vp │ │ ├── ipsxb_ddrphy_training_ctrl_v1_0.vp │ │ ├── ipsxb_ddrphy_upcal_v1_4.vp │ │ ├── ipsxb_ddrphy_wdata_path_adj_v1_0.vp │ │ └── ipsxb_ddrphy_wrlvl_v1_0.vp │ │ └── mcdq_ctrl │ │ ├── distributed_fifo │ │ ├── ipsxb_distributed_fifo_v1_0.v │ │ └── rtl │ │ │ ├── ipsxb_distributed_fifo_ctr_v1_0.v │ │ │ ├── ipsxb_distributed_fifo_v1_0_distributed_fifo_v1_0.v │ │ │ └── ipsxb_distributed_sdpram_v1_0_distributed_fifo_v1_0.v │ │ ├── ipsxb_mcdq_apb_cross_v1_2.vp │ │ ├── ipsxb_mcdq_calib_delay_v1_2.vp │ │ ├── ipsxb_mcdq_cfg_apb_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_bm_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_rowaddr_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_sm_v1_2.vp │ │ ├── ipsxb_mcdq_dcd_top_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_back_ctrl_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_buf_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_out_v1_2.vp │ │ ├── ipsxb_mcdq_dcp_top_v1_2.vp │ │ ├── ipsxb_mcdq_dfi_v1_2.vp │ │ ├── ipsxb_mcdq_lp_v1_2.vp │ │ ├── ipsxb_mcdq_mrs_v1_2.vp │ │ ├── ipsxb_mcdq_prefetch_fifo_v1_2.vp │ │ ├── ipsxb_mcdq_rdatapath_v1_2.vp │ │ ├── ipsxb_mcdq_reg_fifo2_v1_2.vp │ │ ├── ipsxb_mcdq_ui_axi_v1_2.vp │ │ ├── ipsxb_mcdq_wdatapath_v1_2.vp │ │ ├── ipsxb_mcdq_wdp_align_v1_2.vp │ │ ├── ipsxb_mcdq_wdp_dcp_v1_2.vp │ │ ├── ipsxb_mcdq_wrapper_v1_2a.vp │ │ └── syn_mod │ │ ├── ipsxb_mcdq_com_timing_v1_2.vp │ │ ├── ipsxb_mcdq_tfaw_timing_v1_2.vp │ │ ├── ipsxb_mcdq_tfaw_v1_2.vp │ │ ├── ipsxb_mcdq_timing_act2wr_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_act_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_pre_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_rd_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_ref_pass_v1_2.vp │ │ ├── ipsxb_mcdq_timing_wr_pass_v1_2.vp │ │ └── ipsxb_mcdq_trc_timing_v1_2.vp ├── btn_deb_fix.v ├── cmos_8_16bit.v ├── eth_src │ ├── arp_cache.v │ ├── arp_mac_top.v │ ├── arp_rx.v │ ├── arp_tx.v │ ├── check_sum.vh │ ├── crc32_gen.v │ ├── eth_test_top.v │ ├── gen_pix.v │ ├── gmii2rgmii.v │ ├── icmp.v │ ├── ip_layer.v │ ├── ip_rx.v │ ├── ip_tx.v │ ├── ip_tx_mode.v │ ├── mac_layer.v │ ├── mac_rx.v │ ├── mac_tx.v │ ├── mac_tx_mode.v │ ├── rgmii_interface.v │ ├── test_top │ │ ├── eth_udp_test.v │ │ ├── mac_arp_test.v │ │ └── rgmii_test.v │ ├── udp_ip_mac_top.v │ ├── udp_layer.v │ ├── udp_rx.v │ ├── udp_rx_bac.v │ ├── udp_tx.v │ └── xdc │ │ └── ethenet_test.xdc ├── fram_buf.v ├── frame_start_ctrl.v ├── i2c_com.v ├── iic_dri.v ├── ms7200_ctl.v ├── ms7210_ctl.v ├── ms72xx_ctl.v ├── pcie │ ├── fifo │ │ ├── ipm_distributed_sdpram_v1_2_distributed_fifo.v │ │ ├── pgs_pciex4_fifo_ctrl.v │ │ └── pgs_pciex4_fifo_v1_2.v │ ├── ipm_distributed_sdpram_v1_2.v │ ├── ipsl_pcie_dma.v │ ├── ipsl_pcie_dma_controller.v │ ├── ipsl_pcie_dma_cpld_tx_ctrl.v │ ├── ipsl_pcie_dma_mrd_tx_ctrl.v │ ├── ipsl_pcie_dma_mwr_tx_ctrl.v │ ├── ipsl_pcie_dma_ram │ │ ├── ipsl_pcie_dma_ram.v │ │ └── rtl │ │ │ ├── ipml_sdpram_v1_5_ipsl_pcie_dma_ram.v │ │ │ └── ipsl_pcie_dma_ram_init_param.v │ ├── ipsl_pcie_dma_rd_ctrl.v │ ├── ipsl_pcie_dma_rx_cpld_wr_ctrl.v │ ├── ipsl_pcie_dma_rx_mwr_wr_ctrl.v │ ├── ipsl_pcie_dma_rx_top.v │ ├── ipsl_pcie_dma_tlp_rcv.v │ ├── ipsl_pcie_dma_tlp_tx_mux.v │ ├── ipsl_pcie_dma_tx_cpld_rd_ctrl.v │ ├── ipsl_pcie_dma_tx_mwr_rd_ctrl.v │ ├── ipsl_pcie_dma_tx_top.v │ ├── ipsl_pcie_dma_wr_ctrl.v │ ├── ipsl_pcie_reg.v │ └── pgs_pciex4_prefetch_fifo_v1_2.v ├── pcie_rd_buf.v ├── pcie_wr_buf.v ├── pll │ ├── .last_generated │ ├── .settings │ ├── pll.idf │ ├── pll.v │ ├── pll_tb.v │ ├── pll_tmpl.v │ └── pll_tmpl.vhdl ├── power_on_delay.v ├── rd_buf.v ├── rd_ctrl.v ├── reg_config.v ├── scaler │ ├── DP_ram.vp │ ├── buff_ctrl.vp │ ├── mult_18x18_logos │ │ ├── mult_18x18_logos.idf │ │ ├── mult_18x18_logos.v │ │ └── rtl │ │ │ └── ipml_mult_v1_2_mult_18x18_logos.v │ ├── mult_18x18_logos2 │ │ ├── mult_18x18_logos2.idf │ │ ├── mult_18x18_logos2.v │ │ └── rtl │ │ │ ├── ipm2l_apm_data_pipeline │ │ │ ├── ipm2l_apm_data_pipeline.v │ │ │ ├── ipm2l_apm_distributed_sdpram.v │ │ │ └── ipm2l_apm_distributed_shiftregister.v │ │ │ └── ipm2l_mult_v1_2_mult_18x18_logos2.v │ ├── mult_9x9_logos │ │ ├── mult_9x9_logos.idf │ │ ├── mult_9x9_logos.v │ │ └── rtl │ │ │ └── ipml_mult_v1_2_mult_9x9_logos.v │ ├── mult_9x9_logos2 │ │ ├── mult_9x9_logos2.idf │ │ ├── mult_9x9_logos2.v │ │ └── rtl │ │ │ ├── ipm2l_apm_data_pipeline │ │ │ ├── ipm2l_apm_data_pipeline.v │ │ │ ├── ipm2l_apm_distributed_sdpram.v │ │ │ └── ipm2l_apm_distributed_shiftregister.v │ │ │ └── ipm2l_mult_v1_2_mult_9x9_logos2.v │ └── scaler_bilinear.vp ├── src_timing_detect.v ├── sync_vg.v ├── wr_buf.v ├── wr_cmd_trans.v ├── wr_ctrl.v └── wr_rd_ctrl_top.v ├── scaler.v ├── test.v ├── test_scaler.v ├── testt.v └── wr_scale_buf.v /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wdxm657/fpga_practice/HEAD/.gitignore -------------------------------------------------------------------------------- /README.md: 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