├── NOTICE
├── README.rst
├── RX610
└── GNURX
│ └── cpu_a.s
├── RL78
└── GNURL78
│ └── cpu_c.c
├── RX
└── GNURX
│ └── cpu_a.s
├── Cache
├── ARM
│ ├── armv5_generic_l1
│ │ ├── cpu_cache_armv5_generic_l1.c
│ │ └── IAR
│ │ │ └── cpu_cache_armv5_generic_l1_a.s
│ ├── armv7_generic_l1
│ │ ├── cpu_cache_armv7_generic_l1.c
│ │ ├── IAR
│ │ │ └── cpu_cache_armv7_generic_l1_a.s
│ │ ├── GNU
│ │ │ └── cpu_cache_armv7_generic_l1_a.S
│ │ └── ARM
│ │ │ └── cpu_cache_armv7_generic_l1_a.s
│ └── armv7_generic_l1_l2c310_l2
│ │ ├── cpu_cache_armv7_generic_l1_l2c310_l2.c
│ │ ├── IAR
│ │ └── cpu_cache_armv7_generic_l1_l2c310_l2_a.s
│ │ └── GNU
│ │ └── cpu_cache_armv7_generic_l1_l2c310_l2_a.S
└── NXP
│ └── powerpc_e200z4204n3
│ └── cpu_cache_powerpc_e200z4204n3.c
├── NiosII
└── GNU
│ └── cpu_c.c
├── MC9S08
├── Paged
│ └── Codewarrior
│ │ └── cpu_a.s
└── NonPaged
│ └── Codewarrior
│ └── cpu_a.s
├── MC9S12
└── Codewarrior
│ ├── cpu_a.s
│ └── NonPaged
│ └── cpu_a.s
├── MC9S12X
└── Codewarrior
│ └── cpu_a.s
├── MicroBlaze
└── GNU
│ └── cpu_c.c
├── FR
└── Softune
│ └── cpu_a.asm
├── AVR
├── ATxmega128
│ ├── GNU
│ │ └── cpu_a.s
│ └── IAR
│ │ └── cpu_a.s90
├── ATmega128
│ └── IAR
│ │ └── cpu_a.s90
└── ATmega256
│ └── IAR
│ └── cpu_a.s90
├── MCF5272
└── GNU
│ └── cpu_a.s
├── LatticeMico32
└── GNU
│ └── cpu_a.s
├── ColdFire
└── Generic
│ ├── IAR
│ ├── cpu_c.c
│ └── cpu_a.asm
│ ├── Codewarrior
│ └── cpu_c.c
│ └── CW_For_Microcontrollers
│ └── cpu_c.c
├── M14K
└── CodeSourcery
│ └── cpu_a.s
├── MSP430X
├── IAR
│ └── cpu_a.s43
└── CCS
│ └── cpu_a.s43
├── Blackfin
└── VDSP++
│ └── cpu_a.asm
├── MPC57xx-VLE
└── GNU
│ └── cpu_a.S
├── R32C
├── IAR
│ └── cpu_a.s53
└── HEW
│ └── cpu_a.a30
├── M16C
├── IAR
│ └── cpu_a.s34
└── HEW
│ └── cpu_a.a30
├── M32C
├── IAR
│ └── cpu_a.s48
└── HEW
│ └── cpu_a.a30
├── cpu_cache.h
├── RISC-V
└── GCC
│ └── cpu_a.S
├── V850ES
├── PM+
│ └── cpu_a.s
├── CubeSuite
│ └── cpu_a.s
└── IAR
│ └── cpu_a.s85
├── V850E2M
├── IAR
│ └── cpu_a.s85
└── CubeSuite+
│ └── cpu_a.asm
└── V850E2S
└── IAR
└── cpu_a.s85
/NOTICE:
--------------------------------------------------------------------------------
1 | ATTENTION ALL USERS OF THIS REPOSITORY:
2 |
3 | The original work found in this repository is provided by Silicon Labs under the
4 | Apache License, Version 2.0.
5 |
6 | Any third party may contribute derivative works to the original work in which
7 | modifications are clearly identified as being licensed under:
8 |
9 | (1) the Apache License, Version 2.0 or a compatible open source license; or
10 | (2) under a proprietary license with a copy of such license deposited.
11 |
12 | All posted derivative works must clearly identify which license choice has been
13 | elected.
14 |
15 | No such posted derivative works will be considered to be a “Contribution” under
16 | the Apache License, Version 2.0.
17 |
18 | SILICON LABS MAKES NO WARRANTY WITH RESPECT TO ALL POSTED THIRD PARTY CONTENT
19 | AND DISCLAIMS ALL OTHER WARRANTIES OR LIABILITIES, INCLUDING ALL WARRANTIES OF
20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, OWNERSHIP,
21 | NON-INFRINGEMENT, AND NON-MISAPPROPRIATION.
22 |
23 | In the event a derivative work is desired to be submitted to Silicon Labs as a
24 | “Contribution” under the Apache License, Version 2.0, a “Contributor” must give
25 | written email notice to micrium@weston-embedded.com. Unless an email response in
26 | the affirmative to accept the derivative work as a “Contribution”, such email
27 | submission should be considered to have not been incorporated into the original
28 | work.
29 |
--------------------------------------------------------------------------------
/README.rst:
--------------------------------------------------------------------------------
1 | .. raw:: html
2 |
3 |
4 |
5 | 
6 |
7 |
8 |
9 | µC/OS is a full-featured embedded operating system originally developed by Micriµm™. In addition to the two highly popular kernels, µC/OS features support for TCP/IP, USB-Device, USB-Host, and Modbus, as well as a robust File System.
10 |
11 | Since its founding in 1999 as a private company, Micriµm and its team of engineers have offered world-class embedded software components for the most critical and demanding real-time applications. Recognized as having some of the cleanest code in the industry, with easy-to-understand documentation, the Micrium real-time kernels, and software components have successfully been deployed in thousands of products worldwide across a broad range of industries. Micrium’s µC/OS-II™ kernel has been certified for use in safety-critical applications and remains a respected favorite in the medical, aerospace, and industrial markets. µC/OS continues to be the RTOS of choice for engineers requiring the most reliable and trusted solution for their mission-critical applications.
12 |
13 | ----------
14 |
15 | .. raw:: HTML
16 |
17 |
18 |
19 | 
20 |
21 |
22 |
23 | Founded by a team of former Micrium employees, Weston Embedded Solutions is the official custodian for the µC/OS RTOS and Stacks software repository to ensure it remains the trusted choice for embedded engineers around the world.
24 |
25 | ----------
26 |
27 | Product Documentation and Release Notes
28 | ***************
29 | https://micrium.atlassian.net/
30 |
31 | Technical Support
32 | *****************
33 | https://weston-embedded.com/micrium-support
34 |
35 | Example Projects
36 | *********
37 | https://weston-embedded.com/micrium-examples
38 |
39 | Commercial Licensing Option
40 | *********
41 | https://weston-embedded.com/products/cesium
42 |
43 | Who to Contact
44 | *********
45 | https://weston-embedded.com/company/contact
46 |
--------------------------------------------------------------------------------
/RX610/GNURX/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; Renesas RX610 Specific code
20 | ; GNU RX C Compiler
21 | ;
22 | ; Filename : cpu_a.s
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; PUBLIC FUNCTIONS
29 | ;********************************************************************************************************
30 |
31 | .global _set_ipl
32 | .global _get_ipl
33 |
34 | .text
35 |
36 |
37 | ;********************************************************************************************************
38 | ; set_ipl() & get_ipl()
39 | ;
40 | ; Description: Set or retrieve interrupt priority level.
41 | ;********************************************************************************************************
42 |
43 | _set_ipl:
44 | PUSH R2
45 | MVFC PSW, R2
46 | AND #-0F000001H, R2
47 | SHLL #24, R1
48 | OR R1, R2
49 | MVTC R2, PSW
50 | POP R2
51 | RTS
52 |
53 | _get_ipl:
54 | MVFC PSW, R1
55 | SHLR #24, R1
56 | AND #15, R1
57 | RTS
58 |
59 |
60 | .END
61 |
--------------------------------------------------------------------------------
/RL78/GNURL78/cpu_c.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /********************************************************************************************************
18 | *
19 | * CPU PORT FILE
20 | *
21 | * Renesas RL78 Specific code
22 | * GNU RL78 C Compiler
23 | *
24 | * Filename : cpu_c.c
25 | * Version : V1.32.01
26 | *********************************************************************************************************
27 | */
28 |
29 | #include
30 |
31 |
32 | /********************************************************************************************************
33 | * set_interrupt_state & get_interrupt_state
34 | *
35 | * Description: Set or retrieve interrupt priority level.
36 | * KPIT GNU Work around for set and get interrupt states
37 | *********************************************************************************************************
38 | */
39 |
40 | void __set_interrupt_state(CPU_INT08U cpu_sr){
41 | if (cpu_sr)
42 | asm("EI");
43 | else
44 | asm("DI");
45 | }
46 |
47 | CPU_INT08U __get_interrupt_state(void){
48 |
49 | CPU_INT08U cpu_sr;
50 |
51 |
52 | asm(" MOV A, PSW"); /* Get Process Status Word Register PSW value */
53 | asm(" SHR A, 7"); /* Save only the Interrupt Enabled (IE) Bit */
54 | asm(" MOV %0, A" : "=r"(cpu_sr)); /* Save IE bit value into cpu_sr */ //__asm
55 |
56 | return(cpu_sr);
57 | }
58 |
--------------------------------------------------------------------------------
/RX/GNURX/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; Renesas RX Specific code
20 | ; GNU RX C Compiler
21 | ;
22 | ; Filename : cpu_a.s
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; PUBLIC FUNCTIONS
29 | ;********************************************************************************************************
30 |
31 | .global _set_ipl
32 | .global _get_ipl
33 | .global _set_intb
34 |
35 | .text
36 |
37 |
38 | ;********************************************************************************************************
39 | ; set_ipl() & get_ipl()
40 | ;
41 | ; Description: Set or retrieve interrupt priority level.
42 | ;********************************************************************************************************
43 |
44 | _set_ipl:
45 | PUSH R2
46 | MVFC PSW, R2
47 | AND #-0F000001H, R2
48 | SHLL #24, R1
49 | OR R1, R2
50 | MVTC R2, PSW
51 | POP R2
52 | RTS
53 |
54 |
55 | _get_ipl:
56 | MVFC PSW, R1
57 | SHLR #24, R1
58 | AND #15, R1
59 | RTS
60 |
61 |
62 | ;********************************************************************************************************
63 | ; set_intb()
64 | ;
65 | ; Description: Set the interrupt base register
66 | ;********************************************************************************************************
67 |
68 | _set_intb:
69 | PUSH R2
70 | mvtc R1, intb
71 | POP R2
72 | RTS
73 |
74 |
75 | .END
76 |
--------------------------------------------------------------------------------
/Cache/ARM/armv5_generic_l1/cpu_cache_armv5_generic_l1.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU CACHE IMPLEMENTATION
21 | * ARMv5 Generic L1 Cache
22 | *
23 | * Filename : cpu_cache_armv5_generic_l1.c
24 | * Version : V1.32.01
25 | *********************************************************************************************************
26 | */
27 |
28 |
29 | /*
30 | *********************************************************************************************************
31 | * INCLUDE FILES
32 | *********************************************************************************************************
33 | */
34 | #include
35 | #include "../../../cpu_cache.h"
36 | #include
37 |
38 |
39 | #ifdef __cplusplus
40 | extern "C" {
41 | #endif
42 |
43 | /*
44 | *********************************************************************************************************
45 | * EXTERNAL DECLARATIONS
46 | *********************************************************************************************************
47 | */
48 |
49 | /*
50 | *********************************************************************************************************
51 | * LOCAL GLOBAL VARIABLES
52 | *********************************************************************************************************
53 | */
54 |
55 | CPU_INT32U CPU_Cache_Linesize; /* Cache line size. */
56 |
57 |
58 | /*
59 | *********************************************************************************************************
60 | * CPU_CacheMGMTInit()
61 | *
62 | * Description : Initialize cpu cache module.
63 | *
64 | * Argument(s) : none.
65 | *
66 | * Return(s) : none.
67 | *
68 | * Note(s) : none.
69 | *********************************************************************************************************
70 | */
71 |
72 | void CPU_Cache_Init(void)
73 | {
74 | CPU_Cache_Linesize = 32u;
75 | }
76 |
77 | #ifdef __cplusplus
78 | }
79 | #endif
80 |
--------------------------------------------------------------------------------
/NiosII/GNU/cpu_c.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * Nios II
23 | * GNU C Compiler
24 | *
25 | * Filename : cpu_c.c
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 | /*
31 | *********************************************************************************************************
32 | * INCLUDE FILES
33 | *********************************************************************************************************
34 | */
35 |
36 | #define MICRIUM_SOURCE
37 | #include
38 | #include
39 |
40 | #ifdef __cplusplus
41 | extern "C" {
42 | #endif
43 |
44 |
45 | /*
46 | *********************************************************************************************************
47 | * CPU_SR_Save()
48 | *
49 | * Description : This function disables interrupts for critical sections of code.
50 | *
51 | * Argument(s) : none.
52 | *
53 | * Return(s) : The CPU's status register, so that interrupts can later be returned to their original
54 | * state.
55 | *
56 | * Note(s) : none.
57 | *********************************************************************************************************
58 | */
59 |
60 | CPU_SR CPU_SR_Save (void)
61 | {
62 | return (alt_irq_disable_all());
63 | }
64 |
65 |
66 | /*
67 | *********************************************************************************************************
68 | * CPU_SR_Restore()
69 | *
70 | * Description : Restores interrupts after critical sections of code.
71 | *
72 | * Argument(s) : cpu_sr The interrupt status that will be restored.
73 | *
74 | * Return(s) : none.
75 | *
76 | * Note(s) : none.
77 | *********************************************************************************************************
78 | */
79 |
80 | void CPU_SR_Restore (CPU_SR cpu_sr)
81 | {
82 | alt_irq_enable_all(cpu_sr);
83 | }
84 |
85 | #ifdef __cplusplus
86 | }
87 | #endif
88 |
--------------------------------------------------------------------------------
/Cache/ARM/armv7_generic_l1/cpu_cache_armv7_generic_l1.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU CACHE IMPLEMENTATION
21 | * ARMv7 Generic L1 Cache
22 | *
23 | * Filename : cpu_cache_armv7_generic_l1.c
24 | * Version : V1.32.01
25 | *********************************************************************************************************
26 | */
27 |
28 |
29 | /*
30 | *********************************************************************************************************
31 | * INCLUDE FILES
32 | *********************************************************************************************************
33 | */
34 | #include
35 | #include "../../../cpu_cache.h"
36 | #include
37 |
38 |
39 | #ifdef __cplusplus
40 | extern "C" {
41 | #endif
42 |
43 | /*
44 | *********************************************************************************************************
45 | * EXTERNAL DECLARATIONS
46 | *********************************************************************************************************
47 | */
48 |
49 | CPU_INT32U CPU_DCache_LineSizeGet(void);
50 |
51 |
52 | /*
53 | *********************************************************************************************************
54 | * LOCAL GLOBAL VARIABLES
55 | *********************************************************************************************************
56 | */
57 |
58 | CPU_INT32U CPU_Cache_Linesize; /* Cache line size. */
59 |
60 |
61 | /*
62 | *********************************************************************************************************
63 | * CPU_CacheMGMTInit()
64 | *
65 | * Description : Initialize cpu cache module.
66 | *
67 | * Argument(s) : none.
68 | *
69 | * Return(s) : none.
70 | *
71 | * Note(s) : none.
72 | *********************************************************************************************************
73 | */
74 |
75 | void CPU_Cache_Init(void)
76 | {
77 | CPU_Cache_Linesize = CPU_DCache_LineSizeGet();
78 | }
79 |
80 | #ifdef __cplusplus
81 | }
82 | #endif
83 |
--------------------------------------------------------------------------------
/Cache/NXP/powerpc_e200z4204n3/cpu_cache_powerpc_e200z4204n3.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU CACHE IMPLEMENTATION
21 | * PowerPC e200z4204n3
22 | * L1 Cache
23 | *
24 | * Filename : cpu_cache_powerpc_e200z4204n3.c
25 | * Version : V1.32.01
26 | *********************************************************************************************************
27 | */
28 |
29 |
30 | /*
31 | *********************************************************************************************************
32 | * INCLUDE FILES
33 | *********************************************************************************************************
34 | */
35 | #include
36 | #include "../../../cpu_cache.h"
37 | #include
38 |
39 |
40 | #ifdef __cplusplus
41 | extern "C" {
42 | #endif
43 |
44 | /*
45 | *********************************************************************************************************
46 | * EXTERNAL DECLARATIONS
47 | *********************************************************************************************************
48 | */
49 |
50 | CPU_INT32U CPU_DCache_LineSizeGet(void);
51 |
52 |
53 | /*
54 | *********************************************************************************************************
55 | * LOCAL GLOBAL VARIABLES
56 | *********************************************************************************************************
57 | */
58 |
59 | CPU_INT32U CPU_Cache_Linesize; /* Cache line size. */
60 |
61 |
62 | /*
63 | *********************************************************************************************************
64 | * CPU_CacheMGMTInit()
65 | *
66 | * Description : Initialize cpu cache module.
67 | *
68 | * Argument(s) : none.
69 | *
70 | * Return(s) : none.
71 | *
72 | * Note(s) : none.
73 | *********************************************************************************************************
74 | */
75 |
76 | void CPU_Cache_Init(void)
77 | {
78 | CPU_Cache_Linesize = CPU_DCache_LineSizeGet();
79 | }
80 |
81 | #ifdef __cplusplus
82 | }
83 | #endif
84 |
--------------------------------------------------------------------------------
/MC9S08/Paged/Codewarrior/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 |
16 | ;********************************************************************************************************
17 | ;
18 | ; CPU PORT FILE
19 | ;
20 | ; Freescale MC9S08
21 | ; Codewarrior
22 | ; Paged
23 | ;
24 | ; Filename : cpu_a.s
25 | ; Version : V1.32.01
26 | ;********************************************************************************************************
27 |
28 |
29 | ;********************************************************************************************************
30 | ; PUBLIC FUNCTIONS
31 | ;********************************************************************************************************
32 |
33 | xdef CPU_SR_Save
34 | xdef CPU_SR_Restore
35 |
36 | ;********************************************************************************************************
37 | ; EQUATES
38 | ;********************************************************************************************************
39 |
40 |
41 | ;********************************************************************************************************
42 | ; SAVE THE CCR AND DISABLE INTERRUPTS
43 | ; &
44 | ; RESTORE CCR
45 | ;
46 | ; Description : These function implements OS_CRITICAL_METHOD #3
47 | ;
48 | ; Arguments : The function prototypes for the two functions are:
49 | ; 1) OS_CPU_SR OSCPUSaveSR(void)
50 | ; where OS_CPU_SR is the contents of the CCR register prior to disabling
51 | ; interrupts.
52 | ; 2) void OSCPURestoreSR(OS_CPU_SR os_cpu_sr);
53 | ; 'os_cpu_sr' the the value of the CCR to restore.
54 | ;
55 | ; Note(s) : 1) It's assumed that the compiler uses the A register to pass a single 8-bit argument
56 | ; to and from an assembly language function.
57 | ;********************************************************************************************************
58 |
59 | CPU_SR_Save:
60 | tpa ; Transfer the CCR to A.
61 | sei ; Disable interrupts
62 | rtc ; Return to caller with A containing the previous CCR
63 |
64 | CPU_SR_Restore:
65 | tap ; Restore the CCR from the function argument stored in A
66 | rtc
67 |
--------------------------------------------------------------------------------
/MC9S08/NonPaged/Codewarrior/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 |
16 | ;********************************************************************************************************
17 | ;
18 | ; CPU PORT FILE
19 | ;
20 | ; Freescale MC9S08
21 | ; Codewarrior
22 | ; Non Paged
23 | ;
24 | ; Filename : cpu_a.s
25 | ; Version : V1.32.01
26 | ;********************************************************************************************************
27 |
28 |
29 | ;********************************************************************************************************
30 | ; PUBLIC FUNCTIONS
31 | ;********************************************************************************************************
32 |
33 | xdef CPU_SR_Save
34 | xdef CPU_SR_Restore
35 |
36 | ;********************************************************************************************************
37 | ; EQUATES
38 | ;********************************************************************************************************
39 |
40 |
41 | ;********************************************************************************************************
42 | ; SAVE THE CCR AND DISABLE INTERRUPTS
43 | ; &
44 | ; RESTORE CCR
45 | ;
46 | ; Description : These function implements OS_CRITICAL_METHOD #3
47 | ;
48 | ; Arguments : The function prototypes for the two functions are:
49 | ; 1) OS_CPU_SR OSCPUSaveSR(void)
50 | ; where OS_CPU_SR is the contents of the CCR register prior to disabling
51 | ; interrupts.
52 | ; 2) void OSCPURestoreSR(OS_CPU_SR os_cpu_sr);
53 | ; 'os_cpu_sr' the the value of the CCR to restore.
54 | ;
55 | ; Note(s) : 1) It's assumed that the compiler uses the A register to pass a single 8-bit argument
56 | ; to and from an assembly language function.
57 | ;********************************************************************************************************
58 |
59 | CPU_SR_Save:
60 | tpa ; Transfer the CCR to A.
61 | sei ; Disable interrupts
62 | rts ; Return to caller with A containing the previous CCR
63 |
64 | CPU_SR_Restore:
65 | tap ; Restore the CCR from the function argument stored in A
66 | rts
67 |
--------------------------------------------------------------------------------
/Cache/ARM/armv7_generic_l1_l2c310_l2/cpu_cache_armv7_generic_l1_l2c310_l2.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU CACHE IMPLEMENTATION
21 | * Generic ARMv7 L1 Cache and External L2C310 L2 Cache Controller
22 | *
23 | * Filename : cpu_cache_armv7_generic_l1_l2c310_l2.c
24 | * Version : V1.32.01
25 | *********************************************************************************************************
26 | */
27 |
28 |
29 | /*
30 | *********************************************************************************************************
31 | * INCLUDE FILES
32 | *********************************************************************************************************
33 | */
34 | #include
35 | #include "../../../cpu_cache.h"
36 | #include
37 |
38 | #ifndef CPU_CACHE_CFG_L2C310_BASE_ADDR
39 | #error "CPU_CFG.H, Missing CPU_CACHE_CFG_L2C310_BASE_ADDR: Base address of L2C310 Level 2 cache controller"
40 | #endif
41 |
42 |
43 | #ifdef __cplusplus
44 | extern "C" {
45 | #endif
46 |
47 | /*
48 | *********************************************************************************************************
49 | * EXTERNAL DECLARATIONS
50 | *********************************************************************************************************
51 | */
52 |
53 | CPU_INT32U CPU_DCache_LineSizeGet (void);
54 |
55 |
56 | /*
57 | *********************************************************************************************************
58 | * LOCAL GLOBAL VARIABLES
59 | *********************************************************************************************************
60 | */
61 |
62 | CPU_INT32U CPU_Cache_Linesize; /* Cache line size. */
63 | CPU_INT32U CPU_Cache_PL310BaseAddr; /* PL310 L2 cache controller base addr. */
64 |
65 |
66 | /*
67 | *********************************************************************************************************
68 | * CPU_CacheMGMTInit()
69 | *
70 | * Description : Initialize cpu cache module.
71 | *
72 | * Argument(s) : none.
73 | *
74 | * Return(s) : none.
75 | *
76 | * Note(s) : none.
77 | *********************************************************************************************************
78 | */
79 |
80 | void CPU_Cache_Init(void)
81 | {
82 | CPU_Cache_Linesize = CPU_DCache_LineSizeGet();
83 | CPU_Cache_PL310BaseAddr = CPU_CACHE_CFG_L2C310_BASE_ADDR;
84 | }
85 |
86 | #ifdef __cplusplus
87 | }
88 | #endif
89 |
--------------------------------------------------------------------------------
/MC9S12/Codewarrior/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 |
16 | ;********************************************************************************************************
17 | ;
18 | ; CPU PORT FILE
19 | ;
20 | ; Freescale MC9S12
21 | ; Codewarrior
22 | ;
23 | ; Filename : cpu_a.s
24 | ; Version : V1.32.01
25 | ;********************************************************************************************************
26 |
27 |
28 | ;********************************************************************************************************
29 | ; PUBLIC FUNCTIONS
30 | ;********************************************************************************************************
31 |
32 | xdef CPU_SR_Save
33 | xdef CPU_SR_Restore
34 |
35 |
36 | ;********************************************************************************************************
37 | ; EQUATES
38 | ;********************************************************************************************************
39 |
40 |
41 | ;********************************************************************************************************
42 | ; SAVE THE CCR AND DISABLE INTERRUPTS
43 | ; &
44 | ; RESTORE CCR
45 | ;
46 | ; Description : These function implements OS_CRITICAL_METHOD #3
47 | ;
48 | ; Arguments : The function prototypes for the two functions are:
49 | ; 1) CPU_SR CPU_SR_Save(void);
50 | ; where CPU_SR is the contents of the CCR register prior to disabling
51 | ; interrupts.
52 | ; 2) void CPU_SR_Restore(CPU_SR cpu_sr);
53 | ; 'cpu_sr' the the value of the CCR to restore.
54 | ;
55 | ; Note(s) : 1) It's assumed that the compiler uses the D register to pass a single 16-bit argument
56 | ; to and from an assembly language function.
57 | ;********************************************************************************************************
58 |
59 | CPU_SR_Save:
60 | tfr ccr,b ; It's assumed that 8-bit return value is in register B
61 | sei ; Disable interrupts
62 | rtc ; Return to caller with D containing the previous CCR
63 |
64 | CPU_SR_Restore:
65 | tfr b,ccr ; B contains the CCR value to restore, move to CCR
66 | rtc
67 |
68 |
69 | ;********************************************************************************************************
70 | ; CPU ASSEMBLY PORT FILE END
71 | ;********************************************************************************************************
72 |
--------------------------------------------------------------------------------
/MC9S12X/Codewarrior/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 |
16 | ;********************************************************************************************************
17 | ;
18 | ; CPU PORT FILE
19 | ;
20 | ; Freescale MC9S12X
21 | ; Codewarrior Compiler
22 | ;
23 | ; Filename : cpu_a.s
24 | ; Version : V1.32.01
25 | ;********************************************************************************************************
26 |
27 |
28 | ;********************************************************************************************************
29 | ; PUBLIC FUNCTIONS
30 | ;********************************************************************************************************
31 |
32 | xdef CPU_SR_Save
33 | xdef CPU_SR_Restore
34 |
35 |
36 | ;********************************************************************************************************
37 | ; EQUATES
38 | ;********************************************************************************************************
39 |
40 |
41 | ;********************************************************************************************************
42 | ; SAVE THE CCR AND DISABLE INTERRUPTS
43 | ; &
44 | ; RESTORE CCR
45 | ;
46 | ; Description : These function implements OS_CRITICAL_METHOD #3
47 | ;
48 | ; Arguments : The function prototypes for the two functions are:
49 | ; 1) CPU_SR CPU_SR_Save(void);
50 | ; where CPU_SR is the contents of the CCR register prior to disabling
51 | ; interrupts.
52 | ; 2) void CPU_SR_Restore(CPU_SR cpu_sr);
53 | ; 'cpu_sr' the the value of the CCR to restore.
54 | ;
55 | ; Note(s) : 1) It's assumed that the compiler uses the D register to pass a single 16-bit argument
56 | ; to and from an assembly language function.
57 | ;********************************************************************************************************
58 |
59 | CPU_SR_Save:
60 | tfr ccrw,d ; It's assumed that 16-bit return value is in register D
61 | sei ; Disable interrupts
62 | rtc ; Return to caller with D containing the previous CCR
63 |
64 | CPU_SR_Restore:
65 | tfr d,ccrw ; D contains the CCR word value to restore, move D to CCR
66 | rtc
67 |
68 |
69 | ;********************************************************************************************************
70 | ; CPU ASSEMBLY PORT FILE END
71 | ;********************************************************************************************************
72 |
--------------------------------------------------------------------------------
/MC9S12/Codewarrior/NonPaged/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 |
16 | ;********************************************************************************************************
17 | ;
18 | ; CPU PORT FILE
19 | ;
20 | ; Freescale MC9S12
21 | ; Codewarrior
22 | ; Non Paged
23 | ;
24 | ; Filename : cpu_a.s
25 | ; Version : V1.32.01
26 | ;********************************************************************************************************
27 |
28 | NON_BANKED: section
29 |
30 | ;********************************************************************************************************
31 | ; PUBLIC FUNCTIONS
32 | ;********************************************************************************************************
33 |
34 | xdef CPU_SR_Save
35 | xdef CPU_SR_Restore
36 |
37 |
38 | ;********************************************************************************************************
39 | ; EQUATES
40 | ;********************************************************************************************************
41 |
42 |
43 | ;********************************************************************************************************
44 | ; SAVE THE CCR AND DISABLE INTERRUPTS
45 | ; &
46 | ; RESTORE CCR
47 | ;
48 | ; Description : These function implements OS_CRITICAL_METHOD #3
49 | ;
50 | ; Arguments : The function prototypes for the two functions are:
51 | ; 1) CPU_SR CPU_SR_Save(void);
52 | ; where CPU_SR is the contents of the CCR register prior to disabling
53 | ; interrupts.
54 | ; 2) void CPU_SR_Restore(CPU_SR cpu_sr);
55 | ; 'cpu_sr' the the value of the CCR to restore.
56 | ;
57 | ; Note(s) : 1) It's assumed that the compiler uses the D register to pass a single 16-bit argument
58 | ; to and from an assembly language function.
59 | ;********************************************************************************************************
60 |
61 | CPU_SR_Save:
62 | tfr ccr,b ; It's assumed that 8-bit return value is in register B
63 | sei ; Disable interrupts
64 | rts ; Return to caller with D containing the previous CCR
65 |
66 | CPU_SR_Restore:
67 | tfr b,ccr ; B contains the CCR value to restore, move to CCR
68 | rts
69 |
70 |
71 | ;********************************************************************************************************
72 | ; CPU ASSEMBLY PORT FILE END
73 | ;********************************************************************************************************
74 |
--------------------------------------------------------------------------------
/MicroBlaze/GNU/cpu_c.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * Microblaze
23 | * GNU
24 | *
25 | * Filename : cpu_c.c
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 | /*
31 | *********************************************************************************************************
32 | * INCLUDE FILES
33 | *********************************************************************************************************
34 | */
35 |
36 | #define MICRIUM_SOURCE
37 | #include
38 | #include
39 | #include
40 |
41 | #ifdef __cplusplus
42 | extern "C" {
43 | #endif
44 |
45 |
46 | /*
47 | *********************************************************************************************************
48 | * LOCAL VARIABLES
49 | *********************************************************************************************************
50 | */
51 |
52 | /*
53 | *********************************************************************************************************
54 | * CPU_FlushDCache()
55 | *
56 | * Description : Flush a specific range in the cache memory
57 | *
58 | * Argument(s) : addr the start address of the memory area to flush
59 | * len the size of the memory area to flush
60 | *
61 | * Return(s) : none.
62 | *
63 | * Note(s) : The function uses microblaze_flush_dcache_range() which is part of Xilinx libraries
64 | *********************************************************************************************************
65 | */
66 |
67 | void CPU_CacheDataFlush (void *addr,
68 | CPU_INT32U len)
69 | {
70 | microblaze_flush_dcache_range((CPU_INT32S)addr, len);
71 | }
72 |
73 | /*
74 | *********************************************************************************************************
75 | * CPU_InvalidateDCache()
76 | *
77 | * Description : Invalide a specific range in the cache memory
78 | *
79 | * Argument(s) : addr the start address of the memory area to invalidate
80 | * len the size of the memory area to invalidate
81 | *
82 | * Return(s) : none.
83 | *
84 | * Note(s) : The function uses microblaze_invalidate_dcache_range() which is part of Xilinx libraries
85 | *********************************************************************************************************
86 | */
87 |
88 | void CPU_CacheDataInvalidate (void *addr,
89 | CPU_INT32U len)
90 | {
91 | microblaze_invalidate_dcache_range((CPU_INT32S)addr, len);
92 | }
93 |
94 | #ifdef __cplusplus
95 | }
96 | #endif
97 |
--------------------------------------------------------------------------------
/FR/Softune/cpu_a.asm:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; Fujitsu FR
20 | ; Softune Compiler
21 | ;
22 | ; Filename : cpu_a.asm
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 | .PROGRAM CPU_A
27 |
28 |
29 | ;********************************************************************************************************
30 | ; PUBLIC FUNCTIONS
31 | ;********************************************************************************************************
32 |
33 | .EXPORT _CPU_SR_Save
34 | .EXPORT _CPU_SR_Restore
35 |
36 | .section CODE, code, align=4
37 |
38 |
39 | ;********************************************************************************************************
40 | ; CRITICAL SECTION FUNCTIONS
41 | ;
42 | ; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
43 | ; would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
44 | ; disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
45 | ; into the CPU's status register.
46 | ;
47 | ; Prototypes : CPU_SR CPU_SR_Save (void);
48 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
49 | ;
50 | ; Note(s) : (1) These functions are used in general like this :
51 | ;
52 | ; void Task (void *p_arg)
53 | ; {
54 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
55 | ; :
56 | ; :
57 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
58 | ; :
59 | ; :
60 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
61 | ; :
62 | ; }
63 | ;********************************************************************************************************
64 |
65 |
66 | _CPU_SR_Save:
67 | MOV PS, R4 ; Save state of PS
68 | ANDCCR #0xEF ; Disable interrupts
69 | RET
70 |
71 | _CPU_SR_Restore:
72 | MOV R4, PS ; Restore state of PS
73 | RET
74 |
75 |
76 | ;********************************************************************************************************
77 | ; CPU ASSEMBLY PORT FILE END
78 | ;********************************************************************************************************
79 |
80 | .END
81 |
--------------------------------------------------------------------------------
/AVR/ATxmega128/GNU/cpu_a.s:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * Atmel ATxmega128
23 | * GNU C Compiler
24 | *
25 | * Filename : cpu_a.s
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * ASM HEADER
34 | *********************************************************************************************************
35 | */
36 |
37 | .text
38 |
39 |
40 | /*
41 | *********************************************************************************************************
42 | * DEFINES
43 | *********************************************************************************************************
44 | */
45 |
46 | .equ SREG, 0x3F /* Status Register */
47 |
48 |
49 | /*
50 | *********************************************************************************************************
51 | * PUBLIC DECLARATIONS
52 | *********************************************************************************************************
53 | */
54 |
55 | .global CPU_SR_Save
56 | .global CPU_SR_Restore
57 |
58 |
59 | /*
60 | *********************************************************************************************************
61 | * DISABLE/ENABLE INTERRUPTS USING OS_CRITICAL_METHOD #3
62 | *
63 | * Description : These functions are used to disable and enable interrupts using OS_CRITICAL_METHOD #3.
64 | *
65 | * CPU_SR CPU_SR_Save (void)
66 | * Get current value of SREG
67 | * Disable interrupts
68 | * Return original value of SREG
69 | *
70 | * void CPU_SR_Restore (OS_CPU_SR cpu_sr)
71 | * Set SREG to cpu_sr
72 | * Return
73 | *********************************************************************************************************
74 | */
75 |
76 | CPU_SR_Save:
77 | IN R16,SREG /* Get current state of interrupts disable flag */
78 | CLI /* Disable interrupts */
79 | RET /* Return original SREG value in R16 */
80 |
81 |
82 | CPU_SR_Restore:
83 | OUT SREG,R16 /* Restore SREG */
84 | RET /* Return */
85 |
--------------------------------------------------------------------------------
/MCF5272/GNU/cpu_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 |
16 | ;********************************************************************************************************
17 | ;
18 | ; CPU PORT FILE
19 | ;
20 | ; MCF5272
21 | ; GNU C Compiler
22 | ;
23 | ; Filename : cpu_a.s
24 | ; Version : V1.32.01
25 | ;********************************************************************************************************
26 |
27 |
28 | ;********************************************************************************************************
29 | ; PUBLIC DECLARATIONS
30 | ;********************************************************************************************************
31 |
32 | .global CPU_SR_Save
33 | .global CPU_SR_Restore
34 |
35 |
36 | ;********************************************************************************************************
37 | ; CPU_SR_Save() for OS_CRITICAL_METHOD #3
38 | ;
39 | ; Description : This functions implements the OS_CRITICAL_METHOD #3 function to preserve the state of the
40 | ; interrupt disable flag in order to be able to restore it later.
41 | ;
42 | ; Arguments : none
43 | ;
44 | ; Returns : It is assumed that the return value is placed in the D0 register as expected by the
45 | ; compiler.
46 | ;********************************************************************************************************
47 |
48 | .text
49 |
50 | CPU_SR_Save:
51 | MOVE %SR,%D0 /* Copy SR into D0 */
52 | MOVE.L %D0,-(%A7) /* Save D0 */
53 | ORI.L #0x0700,%D0 /* Disable interrupts */
54 | MOVE %D0,%SR
55 | MOVE.L (%A7)+,%D0 /* Restore original state of SR */
56 | RTS
57 |
58 | ;********************************************************************************************************
59 | ; CPU_SR_Restore() for OS_CRITICAL_METHOD #3
60 | ;
61 | ; Description : This functions implements the OS_CRITICAL_METHOD #function to restore the state of the
62 | ; interrupt flag.
63 | ;
64 | ; Arguments : cpu_sr is the contents of the SR to restore. It is assumed that this 'argument' is
65 | ; passed in the D0 register of the CPU by the compiler.
66 | ;
67 | ; Returns : None
68 | ;********************************************************************************************************
69 |
70 | CPU_SR_Restore:
71 | MOVE %D0,%SR
72 | RTS
73 |
74 |
75 | ;********************************************************************************************************
76 | ; CPU ASSEMBLY PORT FILE END
77 | ;********************************************************************************************************
78 |
79 | END
80 |
--------------------------------------------------------------------------------
/AVR/ATmega128/IAR/cpu_a.s90:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * Atmel ATmega128
23 | * IAR C Compiler
24 | *
25 | * Filename : cpu_a.s90
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * ASM HEADER
34 | *********************************************************************************************************
35 | */
36 |
37 | MODULE CPU_A
38 |
39 | RSEG CODE:CODE:NOROOT(1)
40 |
41 |
42 | /*
43 | *********************************************************************************************************
44 | * DEFINES
45 | *********************************************************************************************************
46 | */
47 |
48 | SREG EQU 0x3F /* Status Register */
49 |
50 |
51 | /*
52 | *********************************************************************************************************
53 | * PUBLIC DECLARATIONS
54 | *********************************************************************************************************
55 | */
56 |
57 | PUBLIC CPU_SR_Save
58 | PUBLIC CPU_SR_Restore
59 |
60 |
61 | /*
62 | *********************************************************************************************************
63 | * DISABLE/ENABLE INTERRUPTS USING OS_CRITICAL_METHOD #3
64 | *
65 | * Description : These functions are used to disable and enable interrupts using OS_CRITICAL_METHOD #3.
66 | *
67 | * CPU_SR CPU_SR_Save (void)
68 | * Get current value of SREG
69 | * Disable interrupts
70 | * Return original value of SREG
71 | *
72 | * void CPU_SR_Restore (OS_CPU_SR cpu_sr)
73 | * Set SREG to cpu_sr
74 | * Return
75 | *********************************************************************************************************
76 | */
77 |
78 | CPU_SR_Save:
79 | IN R16,SREG /* Get current state of interrupts disable flag */
80 | CLI /* Disable interrupts */
81 | RET /* Return original SREG value in R16 */
82 |
83 |
84 | CPU_SR_Restore:
85 | OUT SREG,R16 /* Restore SREG */
86 | RET /* Return */
87 |
88 | END
89 |
--------------------------------------------------------------------------------
/AVR/ATmega256/IAR/cpu_a.s90:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * Atmel ATmega256
23 | * IAR C Compiler
24 | *
25 | * Filename : cpu_a.s90
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * ASM HEADER
34 | *********************************************************************************************************
35 | */
36 |
37 | MODULE CPU_A
38 |
39 | RSEG FARCODE:CODE:NOROOT(1)
40 |
41 |
42 | /*
43 | *********************************************************************************************************
44 | * DEFINES
45 | *********************************************************************************************************
46 | */
47 |
48 | SREG EQU 0x3F /* Status Register */
49 |
50 |
51 | /*
52 | *********************************************************************************************************
53 | * PUBLIC DECLARATIONS
54 | *********************************************************************************************************
55 | */
56 |
57 | PUBLIC CPU_SR_Save
58 | PUBLIC CPU_SR_Restore
59 |
60 |
61 | /*
62 | *********************************************************************************************************
63 | * DISABLE/ENABLE INTERRUPTS USING OS_CRITICAL_METHOD #3
64 | *
65 | * Description : These functions are used to disable and enable interrupts using OS_CRITICAL_METHOD #3.
66 | *
67 | * CPU_SR CPU_SR_Save (void)
68 | * Get current value of SREG
69 | * Disable interrupts
70 | * Return original value of SREG
71 | *
72 | * void CPU_SR_Restore (OS_CPU_SR cpu_sr)
73 | * Set SREG to cpu_sr
74 | * Return
75 | *********************************************************************************************************
76 | */
77 |
78 | CPU_SR_Save:
79 | IN R16,SREG /* Get current state of interrupts disable flag */
80 | CLI /* Disable interrupts */
81 | RET /* Return original SREG value in R16 */
82 |
83 |
84 | CPU_SR_Restore:
85 | OUT SREG,R16 /* Restore SREG */
86 | RET /* Return */
87 |
88 | END
89 |
--------------------------------------------------------------------------------
/LatticeMico32/GNU/cpu_a.s:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * LatticeMico32
23 | * GNU C/C++ Compiler
24 | *
25 | * Filename : cpu_a.s
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * PUBLIC FUNCTIONS
34 | *********************************************************************************************************
35 | */
36 |
37 | .global CPU_SR_Save
38 | .global CPU_SR_Restore
39 |
40 | /*
41 | *********************************************************************************************************
42 | * CODE GENERATION DIRECTIVES
43 | *********************************************************************************************************
44 | */
45 |
46 | .text
47 |
48 | /*
49 | *********************************************************************************************************
50 | * SAVE/RESTORE CPU STATUS REGISTER
51 | *
52 | * Description : Save/Restore the state of CPU interrupts, if possible.
53 | *
54 | * (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
55 | * stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
56 | * allocated in all functions that need to disable interrupts). The previous interrupt
57 | * status state is restored by copying 'cpu_sr' into the CPU's status register.
58 | *
59 | *
60 | * Prototypes : CPU_SR CPU_SR_Save (void);
61 | * void CPU_SR_Restore(CPU_SR cpu_sr);
62 | *
63 | * Note(s) : (2) These functions are used in general like this :
64 | *
65 | * void Task (void *p_arg)
66 | * {
67 | * CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
68 | * :
69 | * :
70 | * CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
71 | * :
72 | * :
73 | * CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
74 | * :
75 | * }
76 | *********************************************************************************************************
77 | */
78 |
79 | CPU_SR_Save:
80 | rcsr r1, ie
81 | wcsr ie, r0
82 | ret
83 |
84 |
85 | CPU_SR_Restore:
86 | wcsr ie, r1
87 | ret
88 |
89 |
90 | /*
91 | *********************************************************************************************************
92 | * CPU ASSEMBLY PORT FILE END
93 | *********************************************************************************************************
94 | */
95 |
--------------------------------------------------------------------------------
/ColdFire/Generic/IAR/cpu_c.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * ColdFire
23 | * IAR C Compiler
24 | *
25 | * Filename : cpu_c.c
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * INCLUDE FILES
34 | *********************************************************************************************************
35 | */
36 |
37 | #define MICRIUM_SOURCE
38 | #include
39 | #include
40 |
41 | #ifdef __cplusplus
42 | extern "C" {
43 | #endif
44 |
45 |
46 | /*
47 | *********************************************************************************************************
48 | * LOCAL VARIABLES
49 | *********************************************************************************************************
50 | */
51 |
52 | CPU_INT32U CPU_VBR_Ptr;
53 |
54 |
55 | /*
56 | *********************************************************************************************************
57 | * CPU_VectGet()
58 | * GET ISR VECTOR
59 | *
60 | * Description : This function is called to get the address of the exception handler specified by 'vect'.
61 | *
62 | * Argument(s) : vect Vector number to retrieve handler.
63 | *
64 | * Return(s) : none.
65 | *
66 | * Note(s) : (1) Interrupts are disabled during this call.
67 | *********************************************************************************************************
68 | */
69 |
70 | void *CPU_VectGet (CPU_INT16U vect)
71 | {
72 | CPU_ADDR addr;
73 | CPU_SR_ALLOC();
74 |
75 |
76 | CPU_CRITICAL_ENTER();
77 | addr = *(CPU_ADDR *)(CPU_VBR_Ptr + (CPU_INT16U)vect * 4);
78 | CPU_CRITICAL_EXIT();
79 |
80 | return ((void *)addr);
81 | }
82 |
83 |
84 | /*
85 | *********************************************************************************************************
86 | * CPU_VectSet()
87 | * SET ISR VECTOR
88 | *
89 | * Description : This function is called to set the contents of an exception vector. The function assumes
90 | * that the VBR (Vector Base Register) is set to 0x00000000.
91 | *
92 | * Argument(s) : vect is the vector number.
93 | *
94 | * addr is the address of the ISR handler.
95 | *
96 | * Return(s) : none.
97 | *
98 | * Note(s) : (1) Interrupts are disabled during this call.
99 | *********************************************************************************************************
100 | */
101 |
102 | void CPU_VectSet (CPU_INT16U vect, void (*vect_addr)(void))
103 | {
104 | CPU_ADDR *pvect;
105 | CPU_SR_ALLOC();
106 |
107 |
108 | CPU_CRITICAL_ENTER();
109 | pvect = (CPU_ADDR *)(CPU_VBR_Ptr + (CPU_INT16U)vect * 4);
110 | *pvect = (CPU_ADDR ) vect_addr;
111 | CPU_CRITICAL_EXIT();
112 | }
113 |
114 | #ifdef __cplusplus
115 | }
116 | #endif
117 |
--------------------------------------------------------------------------------
/ColdFire/Generic/Codewarrior/cpu_c.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * ColdFire
23 | * Codewarrior
24 | *
25 | * Filename : cpu_c.c
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * INCLUDE FILES
34 | *********************************************************************************************************
35 | */
36 |
37 | #define MICRIUM_SOURCE
38 | #include
39 | #include
40 |
41 | #ifdef __cplusplus
42 | extern "C" {
43 | #endif
44 |
45 |
46 | /*
47 | *********************************************************************************************************
48 | * LOCAL VARIABLES
49 | *********************************************************************************************************
50 | */
51 |
52 | CPU_INT32U CPU_VBR_Ptr;
53 |
54 |
55 | /*
56 | *********************************************************************************************************
57 | * CPU_VectGet()
58 | * GET ISR VECTOR
59 | *
60 | * Description : This function is called to get the address of the exception handler specified by 'vect'.
61 | *
62 | * Argument(s) : vect Vector number to retrieve handler.
63 | *
64 | * Return(s) : none.
65 | *
66 | * Note(s) : (1) Interrupts are disabled during this call.
67 | *********************************************************************************************************
68 | */
69 |
70 | void *CPU_VectGet (CPU_INT16U vect)
71 | {
72 | CPU_ADDR addr;
73 | CPU_SR_ALLOC();
74 |
75 |
76 | CPU_CRITICAL_ENTER();
77 | addr = *(CPU_ADDR *)(CPU_VBR_Ptr + (CPU_INT16U)vect * 4);
78 | CPU_CRITICAL_EXIT();
79 |
80 | return ((void *)addr);
81 | }
82 |
83 |
84 | /*
85 | *********************************************************************************************************
86 | * CPU_VectSet()
87 | * SET ISR VECTOR
88 | *
89 | * Description : This function is called to set the contents of an exception vector. The function assumes
90 | * that the VBR (Vector Base Register) is set to 0x00000000.
91 | *
92 | * Argument(s) : vect is the vector number.
93 | *
94 | * addr is the address of the ISR handler.
95 | *
96 | * Return(s) : none.
97 | *
98 | * Note(s) : (1) Interrupts are disabled during this call.
99 | *********************************************************************************************************
100 | */
101 |
102 | void CPU_VectSet (CPU_INT16U vect, void (*vect_addr)(void))
103 | {
104 | CPU_ADDR *pvect;
105 | CPU_SR_ALLOC();
106 |
107 |
108 | CPU_CRITICAL_ENTER();
109 | pvect = (CPU_ADDR *)(CPU_VBR_Ptr + (CPU_INT16U)vect * 4);
110 | *pvect = (CPU_ADDR ) vect_addr;
111 | CPU_CRITICAL_EXIT();
112 | }
113 |
114 | #ifdef __cplusplus
115 | }
116 | #endif
117 |
--------------------------------------------------------------------------------
/ColdFire/Generic/CW_For_Microcontrollers/cpu_c.c:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * ColdFire
23 | * CW for Microcontrollers
24 | *
25 | * Filename : cpu_c.c
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * INCLUDE FILES
34 | *********************************************************************************************************
35 | */
36 |
37 | #define MICRIUM_SOURCE
38 | #include
39 | #include
40 |
41 | #ifdef __cplusplus
42 | extern "C" {
43 | #endif
44 |
45 |
46 | /*
47 | *********************************************************************************************************
48 | * LOCAL VARIABLES
49 | *********************************************************************************************************
50 | */
51 |
52 | CPU_INT32U CPU_VBR_Ptr;
53 |
54 |
55 | /*
56 | *********************************************************************************************************
57 | * CPU_VectGet()
58 | * GET ISR VECTOR
59 | *
60 | * Description : This function is called to get the address of the exception handler specified by 'vect'.
61 | *
62 | * Argument(s) : vect Vector number to retrieve handler.
63 | *
64 | * Return(s) : none.
65 | *
66 | * Note(s) : (1) Interrupts are disabled during this call.
67 | *********************************************************************************************************
68 | */
69 |
70 | void *CPU_VectGet (CPU_INT16U vect)
71 | {
72 | CPU_ADDR addr;
73 | CPU_SR_ALLOC();
74 |
75 |
76 | CPU_CRITICAL_ENTER();
77 | addr = *(CPU_ADDR *)(CPU_VBR_Ptr + (CPU_INT16U)vect * 4);
78 | CPU_CRITICAL_EXIT();
79 |
80 | return ((void *)addr);
81 | }
82 |
83 |
84 | /*
85 | *********************************************************************************************************
86 | * CPU_VectSet()
87 | * SET ISR VECTOR
88 | *
89 | * Description : This function is called to set the contents of an exception vector. The function assumes
90 | * that the VBR (Vector Base Register) is set to 0x00000000.
91 | *
92 | * Argument(s) : vect is the vector number.
93 | *
94 | * addr is the address of the ISR handler.
95 | *
96 | * Return(s) : none.
97 | *
98 | * Note(s) : (1) Interrupts are disabled during this call.
99 | *********************************************************************************************************
100 | */
101 |
102 | void CPU_VectSet (CPU_INT16U vect, void (*vect_addr)(void))
103 | {
104 | CPU_ADDR *pvect;
105 | CPU_SR_ALLOC();
106 |
107 |
108 | CPU_CRITICAL_ENTER();
109 | pvect = (CPU_ADDR *)(CPU_VBR_Ptr + (CPU_INT16U)vect * 4);
110 | *pvect = (CPU_ADDR ) vect_addr;
111 | CPU_CRITICAL_EXIT();
112 | }
113 |
114 | #ifdef __cplusplus
115 | }
116 | #endif
117 |
--------------------------------------------------------------------------------
/M14K/CodeSourcery/cpu_a.s:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * MIPS14k
23 | * MicroMips
24 | *
25 | * Filename : cpu_a.s
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 | #define _ASMLANGUAGE
31 |
32 | /*
33 | *********************************************************************************************************
34 | * PUBLIC FUNCTIONS
35 | *********************************************************************************************************
36 | */
37 |
38 | .globl CPU_SR_Save
39 | .globl CPU_SR_Restore
40 |
41 | /*
42 | *********************************************************************************************************
43 | * EQUATES
44 | *********************************************************************************************************
45 | */
46 |
47 | .text
48 |
49 |
50 | /*
51 | *********************************************************************************************************
52 | * DISABLE INTERRUPTS
53 | * CPU_SR CPU_SR_Save(void);
54 | *
55 | * Description: This function saves the state of the Status register and then disables interrupts via this
56 | * register. This objective is accomplished with a single instruction, di. The di
57 | * instruction's operand, $2, is the general purpose register to which the Status register's
58 | * value is saved. This value can be read by C functions that call OS_CPU_SR_Save().
59 | *
60 | * Arguments : None
61 | *
62 | * Returns : The previous state of the Status register
63 | *********************************************************************************************************
64 | */
65 |
66 | .ent CPU_SR_Save
67 | CPU_SR_Save:
68 |
69 | jr $31
70 | di $2 /* Disable interrupts, and move the old value of the... */
71 | /* ...Status register into v0 ($2) */
72 | .end CPU_SR_Save
73 |
74 |
75 | /*
76 | *********************************************************************************************************
77 | * ENABLE INTERRUPTS
78 | * void CPU_SR_Restore(CPU_SR sr);
79 | *
80 | * Description: This function must be used in tandem with CPU_SR_Save(). Calling CPU_SR_Restore()
81 | * causes the value returned by CPU_SR_Save() to be placed in the Status register.
82 | *
83 | * Arguments : The value to be placed in the Status register
84 | *
85 | * Returns : None
86 | *********************************************************************************************************
87 | */
88 |
89 | .ent CPU_SR_Restore
90 | CPU_SR_Restore:
91 |
92 | jr $31
93 | mtc0 $4, $12, 0 /* Restore the status register to its previous state */
94 |
95 | .end CPU_SR_Restore
96 |
97 |
98 | /*
99 | *********************************************************************************************************
100 | * CPU ASSEMBLY PORT FILE END
101 | *********************************************************************************************************
102 | */
103 |
--------------------------------------------------------------------------------
/MSP430X/IAR/cpu_a.s43:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; TI MSP430X
20 | ; MSP430x5xx
21 | ;
22 | ; Filename : cpu_a.s43
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; PUBLIC FUNCTIONS
29 | ;********************************************************************************************************
30 |
31 | PUBLIC CPU_SR_Save
32 | PUBLIC CPU_SR_Restore
33 |
34 |
35 | ;********************************************************************************************************
36 | ; EQUATES
37 | ;********************************************************************************************************
38 |
39 |
40 | ;********************************************************************************************************
41 | ; CODE GENERATION DIRECTIVES
42 | ;********************************************************************************************************
43 |
44 | RSEG CODE ; Program code
45 |
46 |
47 | ;********************************************************************************************************
48 | ; SAVE/RESTORE CPU STATUS REGISTER
49 | ;
50 | ; Description : Save/Restore the state of CPU interrupts, if possible.
51 | ;
52 | ; (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
53 | ; stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
54 | ; allocated in all functions that need to disable interrupts). The previous interrupt
55 | ; status state is restored by copying 'cpu_sr' into the CPU's status register.
56 | ;
57 | ;
58 | ; Prototypes : CPU_SR CPU_SR_Save (void);
59 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
60 | ;
61 | ; Note(s) : (1) These functions are used in general like this :
62 | ;
63 | ; void Task (void *p_arg)
64 | ; {
65 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
66 | ; :
67 | ; :
68 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
69 | ; :
70 | ; :
71 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
72 | ; :
73 | ; }
74 | ;
75 | ; (2) R12 is assumed to hold the argument passed to CPU_SR_Save() & also the value returned
76 | ; by CPU_SR_Restore().
77 | ;********************************************************************************************************
78 |
79 | CPU_SR_Save
80 | MOV.W SR, R12
81 | DINT
82 | RETA
83 |
84 |
85 | CPU_SR_Restore
86 | MOV.W R12, SR
87 | RETA
88 |
89 |
90 | ;********************************************************************************************************
91 | ; CPU ASSEMBLY PORT FILE END
92 | ;********************************************************************************************************
93 |
94 | END
95 |
--------------------------------------------------------------------------------
/Cache/ARM/armv5_generic_l1/IAR/cpu_cache_armv5_generic_l1_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU CACHE IMPLEMENTATION
18 | ; ARMv5 L1 Cache
19 | ; IAR C Compiler
20 | ;
21 | ; Filename : cpu_cache_armv5_generic_l1_a.s
22 | ; Version : V1.32.01
23 | ;********************************************************************************************************
24 |
25 | ;********************************************************************************************************
26 | ; MACROS AND DEFINIITIONS
27 | ;********************************************************************************************************
28 |
29 | PRESERVE8
30 |
31 | RSEG CODE:CODE:NOROOT(2)
32 | CODE32
33 |
34 |
35 | ;********************************************************************************************************
36 | ; CPU_DCache_LineSizeGet()
37 | ;
38 | ; Description : Returns the cache line size.
39 | ;
40 | ; Prototypes : void CPU_DCache_LineSizeGet (void)
41 | ;
42 | ; Argument(s) : none.
43 | ;********************************************************************************************************
44 |
45 | EXPORT CPU_DCache_LineSizeGet
46 |
47 | CPU_DCache_LineSizeGet
48 |
49 | MRC p15, 0, r0, c0, c0, 1
50 | AND r0, r0, #0xF0000
51 | LSR r0, r0, #16
52 | MOV r1, #1
53 | LSL r1, r1, r0
54 | LSL r0, r1, #2
55 |
56 |
57 | BX lr
58 |
59 |
60 | ;********************************************************************************************************
61 | ; INVALIDATE DATA CACHE RANGE
62 | ;
63 | ; Description : Invalidate a range of data cache by MVA.
64 | ;
65 | ; Prototypes : void CPU_DCache_RangeInv (void *p_mem,
66 | ; CPU_SIZE_T range);
67 | ;
68 | ; Argument(s) : p_mem Start address of the region to invalidate.
69 | ;
70 | ; range Size of the region to invalidate in bytes.
71 | ;
72 | ; Note(s) : none.
73 | ;********************************************************************************************************
74 |
75 | EXPORT CPU_DCache_RangeInv
76 |
77 | CPU_DCache_RangeInv
78 | CMP r1, #0
79 | BEQ CPU_DCache_RangeInv_END
80 |
81 | ADD r1, r1, r0
82 | BIC r0, r0, #31
83 |
84 | CPU_DCache_RangeInvL1:
85 | MCR p15,0, r0, c7, c6, 1
86 | ADD r0, r0, #32
87 | CMP r0, r1
88 | BLT CPU_DCache_RangeInvL1
89 | BX LR
90 |
91 | CPU_DCache_RangeInv_END
92 | BX LR
93 |
94 |
95 | ;********************************************************************************************************
96 | ; FLUSH DATA CACHE RANGE
97 | ;
98 | ; Description : Flush (clean) a range of data cache by MVA.
99 | ;
100 | ; Prototypes : void CPU_DCache_RangeFlush (void *p_mem,
101 | ; CPU_SIZE_T range);
102 | ;
103 | ; Argument(s) : p_mem Start address of the region to flush.
104 | ;
105 | ; range Size of the region to invalidate in bytes.
106 | ;
107 | ; Note(s) : none.
108 | ;********************************************************************************************************
109 |
110 | EXPORT CPU_DCache_RangeFlush
111 |
112 | CPU_DCache_RangeFlush
113 | CMP r1, #0
114 | BEQ CPU_DCache_RangeFlush_END
115 |
116 | ADD r1, r1, r0
117 | BIC r0, r0, #31
118 |
119 | CPU_DCache_RangeFlushL1:
120 | MCR p15, 0, r0, c7, c14, 1
121 | ADD r0, r0, #32
122 | CMP r0, r1
123 | BLT CPU_DCache_RangeFlushL1
124 |
125 | CPU_DCache_RangeFlush_END
126 | BX LR
127 |
128 | END
129 |
--------------------------------------------------------------------------------
/MSP430X/CCS/cpu_a.s43:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; TI MSP430X
20 | ; MSP430x5xx
21 | ;
22 | ; Filename : cpu_a.s43
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; PUBLIC FUNCTIONS
29 | ;********************************************************************************************************
30 |
31 | .global CPU_SR_Save
32 | .global CPU_SR_Restore
33 |
34 |
35 | ;********************************************************************************************************
36 | ; EQUATES
37 | ;********************************************************************************************************
38 |
39 |
40 | ;********************************************************************************************************
41 | ; CODE GENERATION DIRECTIVES
42 | ;********************************************************************************************************
43 |
44 | .text ; Program code
45 |
46 |
47 | ;********************************************************************************************************
48 | ; SAVE/RESTORE CPU STATUS REGISTER
49 | ;
50 | ; Description : Save/Restore the state of CPU interrupts, if possible.
51 | ;
52 | ; (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
53 | ; stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
54 | ; allocated in all functions that need to disable interrupts). The previous interrupt
55 | ; status state is restored by copying 'cpu_sr' into the CPU's status register.
56 | ;
57 | ;
58 | ; Prototypes : CPU_SR CPU_SR_Save (void);
59 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
60 | ;
61 | ; Note(s) : (1) These functions are used in general like this :
62 | ;
63 | ; void Task (void *p_arg)
64 | ; {
65 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
66 | ; :
67 | ; :
68 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
69 | ; :
70 | ; :
71 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
72 | ; :
73 | ; }
74 | ;
75 | ; (2) R12 is assumed to hold the argument passed to CPU_SR_Save() & also the value returned
76 | ; by CPU_SR_Restore().
77 | ;********************************************************************************************************
78 |
79 | .asmfunc
80 | CPU_SR_Save:
81 | MOV.W SR, R12
82 | DINT
83 | NOP
84 | RETA
85 | .endasmfunc
86 |
87 | .asmfunc
88 | CPU_SR_Restore:
89 | MOV.W R12, SR
90 | NOP
91 | RETA
92 | .endasmfunc
93 |
94 |
95 | ;********************************************************************************************************
96 | ; CPU ASSEMBLY PORT FILE END
97 | ;********************************************************************************************************
98 |
99 | .end
100 |
--------------------------------------------------------------------------------
/Blackfin/VDSP++/cpu_a.asm:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * Blackfin
23 | * VisualDSP++
24 | *
25 | * Filename : cpu_a.asm
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 | /*
31 | *********************************************************************************************************
32 | * PUBLIC FUNCTIONS
33 | *********************************************************************************************************
34 | */
35 |
36 | .global _CPU_SR_Save
37 | .global _CPU_SR_Restore
38 |
39 |
40 | /*
41 | *********************************************************************************************************
42 | * EQUATES
43 | *********************************************************************************************************
44 | */
45 |
46 |
47 | /*
48 | *********************************************************************************************************
49 | * CODE GENERATION DIRECTIVES
50 | *********************************************************************************************************
51 | */
52 |
53 |
54 | /*
55 | *********************************************************************************************************
56 | * EXTERNAL VARIABLES
57 | *********************************************************************************************************
58 | */
59 |
60 | .section program;
61 |
62 |
63 | /*
64 | *********************************************************************************************************
65 | * SAVE/RESTORE CPU STATUS REGISTER
66 | *
67 | * Description : Save/Restore the state of CPU interrupts, if possible.
68 | *
69 | * (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
70 | * stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
71 | * allocated in all functions that need to disable interrupts). The previous interrupt
72 | * status state is restored by copying 'cpu_sr' into the CPU's status register.
73 | *
74 | *
75 | * Prototypes : CPU_SR CPU_SR_Save (void);
76 | * void CPU_SR_Restore(CPU_SR cpu_sr);
77 | *
78 | * Note(s) : (1) These functions are used in general like this :
79 | *
80 | * void Task (void *p_arg)
81 | * {
82 | * CPU_SR_ALLOC(); Allocate storage for CPU status register
83 | * :
84 | * :
85 | * CPU_CRITICAL_ENTER(); cpu_sr = CPU_SR_Save();
86 | * :
87 | * :
88 | * CPU_CRITICAL_EXIT(); CPU_SR_Restore(cpu_sr);
89 | * :
90 | * }
91 | **********************************************************************************************************
92 | */
93 |
94 | _CPU_SR_Save:
95 |
96 | CLI R0;
97 |
98 | _CPU_SR_Save.end:
99 | RTS;
100 |
101 | _CPU_SR_Restore:
102 |
103 | STI R0;
104 |
105 | _CPU_SR_Restore.end:
106 | RTS;
107 |
108 |
109 | /*
110 | *********************************************************************************************************
111 | * CPU ASSEMBLY PORT FILE END
112 | *********************************************************************************************************
113 | */
114 |
--------------------------------------------------------------------------------
/MPC57xx-VLE/GNU/cpu_a.S:
--------------------------------------------------------------------------------
1 | #********************************************************************************************************
2 | #* uC/CPU
3 | #* CPU CONFIGURATION & PORT LAYER
4 | #*
5 | #* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | #*
7 | #* SPDX-License-Identifier: APACHE-2.0
8 | #*
9 | #* This software is subject to an open source license and is distributed by
10 | #* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | #* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | #*
13 | #********************************************************************************************************
14 |
15 | #********************************************************************************************************
16 | #*
17 | #* CPU PORT FILE
18 | #*
19 | #* NXP MPC57xx-VLE
20 | #*
21 | #* Filename : cpu_a.s
22 | #* Version : V1.32.01
23 | #********************************************************************************************************
24 |
25 |
26 | #********************************************************************************************************
27 | #* ASM HEADER
28 | #********************************************************************************************************
29 |
30 | .text
31 |
32 | #********************************************************************************************************
33 | # PUBLIC DECLARATIONS
34 | #********************************************************************************************************
35 |
36 | .global CPU_SR_Save
37 | .global CPU_SR_Restore
38 | .global CPU_SR_Rd
39 | .global CPU_IntDis
40 | .global CPU_IntEn
41 |
42 |
43 | #********************************************************************************************************
44 | #* CRITICAL SECTION FUNCTIONS
45 | #*
46 | #* Description : These functions are used to enter and exit critical sections using Critical Method #3.
47 | #*
48 | #* CPU_SR CPU_SR_Save (void)
49 | #* Get current global interrupt mask bit value from MSR
50 | #* Disable interrupts
51 | #* Return global interrupt mask bit
52 | #*
53 | #* void CPU_SR_Restore (CPU_SR cpu_sr)
54 | #* Set global interrupt mask bit on MSR according to parameter cpu_sr
55 | #* Return
56 | #*
57 | #* Argument(s) : cpu_sr global interrupt mask status.
58 | #********************************************************************************************************
59 |
60 | CPU_SR_Save:
61 | mfmsr r3
62 | wrteei 0
63 | se_blr
64 |
65 | CPU_SR_Restore:
66 | wrtee r3
67 | se_blr
68 |
69 |
70 | #********************************************************************************************************
71 | #* READ STATUS REGISTER FUNCTION
72 | #*
73 | #* Description : This function is used to retrieve the status register value.
74 | #*
75 | #* CPU_SR CPU_SR_Rd (void)
76 | #* Get current MSR value
77 | #* Return
78 | #********************************************************************************************************
79 |
80 | CPU_SR_Rd:
81 | mfmsr r3
82 | se_blr
83 |
84 |
85 | #********************************************************************************************************
86 | #* DISABLE/ENABLE INTERRUPTS
87 | #*
88 | #* Description : Disable/Enable interrupts by setting or clearing the global interrupt mask in the cpu
89 | #* status register.
90 | #*
91 | #* void CPU_IntDis (void)
92 | #* Set global interrupt mask bit on MSR
93 | #* Return
94 | #*
95 | #* void CPU_IntEn (void)
96 | #* Clear global interrupt mask bit on MSR
97 | #* Return
98 | #********************************************************************************************************
99 |
100 | CPU_IntDis:
101 | wrteei 0
102 | se_blr
103 |
104 |
105 | CPU_IntEn:
106 | wrteei 1
107 | se_blr
108 |
109 |
110 | #********************************************************************************************************
111 | #* CPU ASSEMBLY PORT FILE END
112 | #********************************************************************************************************
113 | .end
114 |
--------------------------------------------------------------------------------
/Cache/ARM/armv7_generic_l1/IAR/cpu_cache_armv7_generic_l1_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU CACHE IMPLEMENTATION
18 | ; ARMv7 Generic L1 Cache
19 | ; IAR EWARM Compiler
20 | ;
21 | ; Filename : cpu_cache_armv7_generic_l1_a.s
22 | ; Version : V1.32.01
23 | ;********************************************************************************************************
24 |
25 | ;********************************************************************************************************
26 | ; MACROS AND DEFINIITIONS
27 | ;********************************************************************************************************
28 |
29 | IMPORT CPU_Cache_Linesize
30 |
31 |
32 | PRESERVE8
33 |
34 | RSEG CODE:CODE:NOROOT(2)
35 | CODE32
36 |
37 |
38 | ;********************************************************************************************************
39 | ; CPU_DCache_LineSizeGet()
40 | ;
41 | ; Description : Returns the cache line size.
42 | ;
43 | ; Prototypes : void CPU_DCache_LineSizeGet (void)
44 | ;
45 | ; Argument(s) : none.
46 | ;********************************************************************************************************
47 |
48 | EXPORT CPU_DCache_LineSizeGet
49 |
50 | CPU_DCache_LineSizeGet
51 |
52 | MRC p15, 0, r0, c0, c0, 1
53 | AND r0, r0, #0xF0000
54 | LSR r0, r0, #16
55 | MOV r1, #1
56 | LSL r1, r1, r0
57 | LSL r0, r1, #2
58 |
59 |
60 | BX lr
61 |
62 |
63 | ;********************************************************************************************************
64 | ; INVALIDATE DATA CACHE RANGE
65 | ;
66 | ; Description : Invalidate a range of data cache by MVA.
67 | ;
68 | ; Prototypes : void CPU_DCache_RangeInv (void *p_mem,
69 | ; CPU_SIZE_T range);
70 | ;
71 | ; Argument(s) : p_mem Start address of the region to invalidate.
72 | ;
73 | ; range Size of the region to invalidate in bytes.
74 | ;
75 | ; Note(s) : none.
76 | ;********************************************************************************************************
77 |
78 | EXPORT CPU_DCache_RangeInv
79 |
80 | CPU_DCache_RangeInv
81 | CMP r1, #0
82 | BEQ CPU_DCache_RangeInv_END
83 |
84 | DSB
85 | MOV32 r2, CPU_Cache_Linesize
86 | LDR r2, [r2]
87 | SUB r3, r2, #1
88 | ADD r1, r1, r0
89 | BIC r0, r0, r3
90 |
91 | CPU_DCache_RangeInvL1
92 | MCR p15,0, r0, c7, c6, 1
93 | ADD r0, r0, r2
94 | CMP r0, r1
95 | BLT CPU_DCache_RangeInvL1
96 | DSB
97 |
98 | CPU_DCache_RangeInv_END
99 | BX LR
100 |
101 |
102 | ;********************************************************************************************************
103 | ; FLUSH DATA CACHE RANGE
104 | ;
105 | ; Description : Flush (clean) a range of data cache by MVA.
106 | ;
107 | ; Prototypes : void CPU_DCache_RangeFlush (void *p_mem,
108 | ; CPU_SIZE_T range);
109 | ;
110 | ; Argument(s) : p_mem Start address of the region to flush.
111 | ;
112 | ; range Size of the region to invalidate in bytes.
113 | ;
114 | ; Note(s) : none.
115 | ;********************************************************************************************************
116 |
117 | EXPORT CPU_DCache_RangeFlush
118 |
119 | CPU_DCache_RangeFlush
120 | CMP r1, #0
121 | BEQ CPU_DCache_RangeFlush_END
122 |
123 | DSB
124 | MOV32 r2, CPU_Cache_Linesize
125 | LDR r2, [r2]
126 | SUB r3, r2, #1
127 | ADD r1, r1, r0
128 | BIC r0, r0, r3
129 |
130 | CPU_DCache_RangeFlushL1
131 | MCR p15, 0, r0, c7, c10, 1
132 | ADD r0, r0, r2
133 | CMP r0, r1
134 | BLT CPU_DCache_RangeFlushL1
135 | DSB
136 |
137 | CPU_DCache_RangeFlush_END
138 | BX LR
139 |
140 | END
141 |
--------------------------------------------------------------------------------
/R32C/IAR/cpu_a.s53:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; R32C
20 | ; IAR C Compiler
21 | ;
22 | ; Filename : cpu_a.s53
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; EQUATES
29 | ;********************************************************************************************************
30 |
31 |
32 | ;********************************************************************************************************
33 | ; CODE GENERATION DIRECTIVES
34 | ;********************************************************************************************************
35 |
36 |
37 | ;********************************************************************************************************
38 | ; PUBLIC FUNCTIONS
39 | ;********************************************************************************************************
40 |
41 | PUBLIC CPU_IntDis ; Public functions
42 | PUBLIC CPU_IntEn
43 | PUBLIC CPU_SR_Save
44 | PUBLIC CPU_SR_Restore
45 |
46 | ;*********************************************************************************************************
47 | ; DISABLE and ENABLE INTERRUPTS
48 | ;
49 | ; Description : Disable/Enable interrupts.
50 | ;
51 | ; Prototypes : void CPU_IntDis(void);
52 | ; void CPU_IntEn (void);
53 | ;*********************************************************************************************************
54 |
55 | CPU_IntDis:
56 | FCLR I
57 | RTS
58 |
59 | CPU_IntEn:
60 | FSET I
61 | RTS
62 |
63 | ;*********************************************************************************************************
64 | ; CRITICAL SECTION FUNCTIONS
65 | ;
66 | ; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
67 | ; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
68 | ; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
69 | ; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
70 | ;
71 | ; Prototypes : CPU_SR CPU_SR_Save (void);
72 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
73 | ;
74 | ; Note(s) : (1) These functions are used in general like this :
75 | ;
76 | ; void Task (void *p_arg)
77 | ; {
78 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
79 | ; :
80 | ; :
81 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
82 | ; :
83 | ; :
84 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
85 | ; :
86 | ; }
87 | ;*********************************************************************************************************
88 |
89 | CPU_SR_Save:
90 | STC FLG, R2R0
91 | FCLR I
92 | RTS
93 |
94 | CPU_SR_Restore:
95 | LDC R2R0, FLG
96 | RTS
97 |
98 | ;********************************************************************************************************
99 | ; CPU ASSEMBLY PORT FILE END
100 | ;********************************************************************************************************
101 |
102 | END
103 |
--------------------------------------------------------------------------------
/M16C/IAR/cpu_a.s34:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; M16C
20 | ; IAR C Compiler
21 | ;
22 | ; Filename : cpu_a.s34
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; PUBLIC FUNCTIONS
29 | ;********************************************************************************************************
30 |
31 | PUBLIC CPU_IntDis
32 | PUBLIC CPU_IntEn
33 |
34 | PUBLIC CPU_SR_Save
35 | PUBLIC CPU_SR_Restore
36 |
37 |
38 | ;********************************************************************************************************
39 | ; EQUATES
40 | ;********************************************************************************************************
41 |
42 |
43 | ;********************************************************************************************************
44 | ; CODE GENERATION DIRECTIVES
45 | ;********************************************************************************************************
46 |
47 | RSEG CODE:CODE:NOROOT(2)
48 |
49 |
50 | ;*********************************************************************************************************
51 | ; DISABLE and ENABLE INTERRUPTS
52 | ;
53 | ; Description : Disable/Enable interrupts.
54 | ;
55 | ; Prototypes : void CPU_IntDis(void);
56 | ; void CPU_IntEn (void);
57 | ;*********************************************************************************************************
58 |
59 | CPU_IntDis
60 | FCLR I
61 | RTS
62 |
63 |
64 | CPU_IntEn
65 | FSET I
66 | RTS
67 |
68 |
69 | ;*********************************************************************************************************
70 | ; CRITICAL SECTION FUNCTIONS
71 | ;
72 | ; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
73 | ; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
74 | ; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
75 | ; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
76 | ;
77 | ; Prototypes : CPU_SR CPU_SR_Save (void);
78 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
79 | ;
80 | ; Note(s) : (1) These functions are used in general like this :
81 | ;
82 | ; void Task (void *p_arg)
83 | ; {
84 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
85 | ; :
86 | ; :
87 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
88 | ; :
89 | ; :
90 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
91 | ; :
92 | ; }
93 | ;*********************************************************************************************************
94 |
95 | CPU_SR_Save
96 | STC FLG, R0
97 | FCLR I
98 | RTS
99 |
100 |
101 | CPU_SR_Restore
102 | LDC R0, FLG
103 | RTS
104 |
105 |
106 | ;********************************************************************************************************
107 | ; CPU ASSEMBLY PORT FILE END
108 | ;********************************************************************************************************
109 |
110 | END
111 |
--------------------------------------------------------------------------------
/M32C/IAR/cpu_a.s48:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; M32C
20 | ; IAR C Compiler
21 | ;
22 | ; Filename : cpu_a.s48
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; PUBLIC FUNCTIONS
29 | ;********************************************************************************************************
30 |
31 | PUBLIC CPU_IntDis
32 | PUBLIC CPU_IntEn
33 |
34 | PUBLIC CPU_SR_Save
35 | PUBLIC CPU_SR_Restore
36 |
37 |
38 | ;********************************************************************************************************
39 | ; EQUATES
40 | ;********************************************************************************************************
41 |
42 |
43 | ;********************************************************************************************************
44 | ; CODE GENERATION DIRECTIVES
45 | ;********************************************************************************************************
46 |
47 | RSEG CODE:CODE:NOROOT(2)
48 |
49 |
50 | ;*********************************************************************************************************
51 | ; DISABLE and ENABLE INTERRUPTS
52 | ;
53 | ; Description : Disable/Enable interrupts.
54 | ;
55 | ; Prototypes : void CPU_IntDis(void);
56 | ; void CPU_IntEn (void);
57 | ;*********************************************************************************************************
58 |
59 | CPU_IntDis
60 | FCLR I
61 | RTS
62 |
63 |
64 | CPU_IntEn
65 | FSET I
66 | RTS
67 |
68 |
69 | ;*********************************************************************************************************
70 | ; CRITICAL SECTION FUNCTIONS
71 | ;
72 | ; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
73 | ; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
74 | ; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
75 | ; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
76 | ;
77 | ; Prototypes : CPU_SR CPU_SR_Save (void);
78 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
79 | ;
80 | ; Note(s) : (1) These functions are used in general like this :
81 | ;
82 | ; void Task (void *p_arg)
83 | ; {
84 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
85 | ; :
86 | ; :
87 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
88 | ; :
89 | ; :
90 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
91 | ; :
92 | ; }
93 | ;*********************************************************************************************************
94 |
95 | CPU_SR_Save
96 | STC FLG, R0
97 | FCLR I
98 | RTS
99 |
100 |
101 | CPU_SR_Restore
102 | LDC R0, FLG
103 | RTS
104 |
105 |
106 | ;********************************************************************************************************
107 | ; CPU ASSEMBLY PORT FILE END
108 | ;********************************************************************************************************
109 |
110 | END
111 |
--------------------------------------------------------------------------------
/M16C/HEW/cpu_a.a30:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; M16C
20 | ; Renesas HEW w/NC30 C Compiler
21 | ;
22 | ; Filename : cpu_a.a30
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; EQUATES
29 | ;********************************************************************************************************
30 |
31 |
32 | ;********************************************************************************************************
33 | ; CODE GENERATION DIRECTIVES
34 | ;********************************************************************************************************
35 |
36 |
37 | ;********************************************************************************************************
38 | ; PUBLIC FUNCTIONS
39 | ;********************************************************************************************************
40 |
41 |
42 | ;*********************************************************************************************************
43 | ; DISABLE and ENABLE INTERRUPTS
44 | ;
45 | ; Description : Disable/Enable interrupts.
46 | ;
47 | ; Prototypes : void CPU_IntDis(void);
48 | ; void CPU_IntEn (void);
49 | ;*********************************************************************************************************
50 |
51 | .SECTION program
52 | .GLB _CPU_IntDis
53 | _CPU_IntDis:
54 | FCLR I
55 | RTS
56 |
57 |
58 | .SECTION program
59 | .GLB _CPU_IntEn
60 | _CPU_IntEn:
61 | FSET I
62 | RTS
63 |
64 |
65 | ;*********************************************************************************************************
66 | ; CRITICAL SECTION FUNCTIONS
67 | ;
68 | ; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
69 | ; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
70 | ; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
71 | ; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
72 | ;
73 | ; Prototypes : CPU_SR CPU_SR_Save (void);
74 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
75 | ;
76 | ; Note(s) : (1) These functions are used in general like this :
77 | ;
78 | ; void Task (void *p_arg)
79 | ; {
80 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
81 | ; :
82 | ; :
83 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
84 | ; :
85 | ; :
86 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
87 | ; :
88 | ; }
89 | ;*********************************************************************************************************
90 |
91 | .SECTION program
92 | .GLB _CPU_SR_Save
93 | _CPU_SR_Save:
94 | STC FLG, R0
95 | FCLR I
96 | RTS
97 |
98 |
99 | .SECTION program
100 | .GLB _CPU_SR_Restore
101 |
102 | _CPU_SR_Restore:
103 | LDC R0, FLG
104 | RTS
105 |
106 |
107 | ;********************************************************************************************************
108 | ; CPU ASSEMBLY PORT FILE END
109 | ;********************************************************************************************************
110 |
111 | .END
112 |
--------------------------------------------------------------------------------
/M32C/HEW/cpu_a.a30:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; M32C
20 | ; Renesas HEW w/NC30 C Compiler
21 | ;
22 | ; Filename : cpu_a.a30
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; EQUATES
29 | ;********************************************************************************************************
30 |
31 |
32 | ;********************************************************************************************************
33 | ; CODE GENERATION DIRECTIVES
34 | ;********************************************************************************************************
35 |
36 |
37 | ;********************************************************************************************************
38 | ; PUBLIC FUNCTIONS
39 | ;********************************************************************************************************
40 |
41 |
42 | ;*********************************************************************************************************
43 | ; DISABLE and ENABLE INTERRUPTS
44 | ;
45 | ; Description : Disable/Enable interrupts.
46 | ;
47 | ; Prototypes : void CPU_IntDis(void);
48 | ; void CPU_IntEn (void);
49 | ;*********************************************************************************************************
50 |
51 | .SECTION program
52 | .GLB _CPU_IntDis
53 | _CPU_IntDis:
54 | FCLR I
55 | RTS
56 |
57 |
58 | .SECTION program
59 | .GLB _CPU_IntEn
60 | _CPU_IntEn:
61 | FSET I
62 | RTS
63 |
64 |
65 | ;*********************************************************************************************************
66 | ; CRITICAL SECTION FUNCTIONS
67 | ;
68 | ; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
69 | ; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
70 | ; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
71 | ; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
72 | ;
73 | ; Prototypes : CPU_SR CPU_SR_Save (void);
74 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
75 | ;
76 | ; Note(s) : (1) These functions are used in general like this :
77 | ;
78 | ; void Task (void *p_arg)
79 | ; {
80 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
81 | ; :
82 | ; :
83 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
84 | ; :
85 | ; :
86 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
87 | ; :
88 | ; }
89 | ;*********************************************************************************************************
90 |
91 | .SECTION program
92 | .GLB _CPU_SR_Save
93 | _CPU_SR_Save:
94 | STC FLG, R0
95 | FCLR I
96 | RTS
97 |
98 |
99 | .SECTION program
100 | .GLB _CPU_SR_Restore
101 |
102 | _CPU_SR_Restore:
103 | LDC R0, FLG
104 | RTS
105 |
106 |
107 | ;********************************************************************************************************
108 | ; CPU ASSEMBLY PORT FILE END
109 | ;********************************************************************************************************
110 |
111 | .END
112 |
--------------------------------------------------------------------------------
/R32C/HEW/cpu_a.a30:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; R32C
20 | ; Renesas HEW w/NC30 C Compiler
21 | ;
22 | ; Filename : cpu_a.a30
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 | ;********************************************************************************************************
28 | ; EQUATES
29 | ;********************************************************************************************************
30 |
31 |
32 | ;********************************************************************************************************
33 | ; CODE GENERATION DIRECTIVES
34 | ;********************************************************************************************************
35 |
36 |
37 | ;********************************************************************************************************
38 | ; PUBLIC FUNCTIONS
39 | ;********************************************************************************************************
40 |
41 |
42 | ;*********************************************************************************************************
43 | ; DISABLE and ENABLE INTERRUPTS
44 | ;
45 | ; Description : Disable/Enable interrupts.
46 | ;
47 | ; Prototypes : void CPU_IntDis(void);
48 | ; void CPU_IntEn (void);
49 | ;*********************************************************************************************************
50 |
51 | .SECTION program
52 | .GLB _CPU_IntDis
53 | _CPU_IntDis:
54 | FCLR I
55 | RTS
56 |
57 |
58 | .SECTION program
59 | .GLB _CPU_IntEn
60 | _CPU_IntEn:
61 | FSET I
62 | RTS
63 |
64 |
65 | ;*********************************************************************************************************
66 | ; CRITICAL SECTION FUNCTIONS
67 | ;
68 | ; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
69 | ; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
70 | ; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
71 | ; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
72 | ;
73 | ; Prototypes : CPU_SR CPU_SR_Save (void);
74 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
75 | ;
76 | ; Note(s) : (1) These functions are used in general like this :
77 | ;
78 | ; void Task (void *p_arg)
79 | ; {
80 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
81 | ; :
82 | ; :
83 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
84 | ; :
85 | ; :
86 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
87 | ; :
88 | ; }
89 | ;*********************************************************************************************************
90 |
91 | .SECTION program
92 | .GLB _CPU_SR_Save
93 | _CPU_SR_Save:
94 | STC FLG, R2R0
95 | FCLR I
96 | RTS
97 |
98 |
99 | .SECTION program
100 | .GLB _CPU_SR_Restore
101 |
102 | _CPU_SR_Restore:
103 | LDC R2R0, FLG
104 | RTS
105 |
106 |
107 | ;********************************************************************************************************
108 | ; CPU ASSEMBLY PORT FILE END
109 | ;********************************************************************************************************
110 |
111 | .END
112 |
--------------------------------------------------------------------------------
/Cache/ARM/armv7_generic_l1/GNU/cpu_cache_armv7_generic_l1_a.S:
--------------------------------------------------------------------------------
1 | @********************************************************************************************************
2 | @ uC/CPU
3 | @ CPU CONFIGURATION & PORT LAYER
4 | @
5 | @ Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | @
7 | @ SPDX-License-Identifier: APACHE-2.0
8 | @
9 | @ This software is subject to an open source license and is distributed by
10 | @ Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | @ Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | @
13 | @********************************************************************************************************
14 |
15 | @********************************************************************************************************
16 | @
17 | @ CPU CACHE IMPLEMENTATION
18 | @ ARMv7 Generic L1 Cache
19 | @ GNU C Compiler
20 | @
21 | @ Filename : cpu_cache_armv7_generic_l1_a.S
22 | @ Version : V1.32.01
23 | @********************************************************************************************************
24 |
25 | @********************************************************************************************************
26 | @ MACROS AND DEFINIITIONS
27 | @********************************************************************************************************
28 |
29 |
30 | .code 32
31 |
32 |
33 | .equ CPU_CACHE_L2C_REG7_CACHE_SYNC, 0x730
34 | .equ CPU_CACHE_L2C_REG7_CACHE_INV_PA, 0x770
35 | .equ CPU_CACHE_L2C_REG7_CACHE_INV_WAY, 0x77C
36 | .equ CPU_CACHE_L2C_REG7_CACHE_CLEAN_PA, 0x7B0
37 |
38 |
39 | @********************************************************************************************************
40 | @ CPU_DCache_LineSizeGet()
41 | @
42 | @ Description : Returns the cache line size.
43 | @
44 | @ Prototypes : void CPU_DCache_LineSizeGet (void)
45 | @
46 | @ Argument(s) : none.
47 | @********************************************************************************************************
48 |
49 | .global CPU_DCache_LineSizeGet
50 |
51 | CPU_DCache_LineSizeGet:
52 |
53 | MRC p15, 0, r0, c0, c0, 1
54 | AND r0, r0, #0xF0000
55 | LSR r0, r0, #16
56 | MOV r1, #1
57 | LSL r1, r1, r0
58 | LSL r0, r1, #2
59 |
60 | BX lr
61 |
62 |
63 | @********************************************************************************************************
64 | @ INVALIDATE DATA CACHE RANGE
65 | @
66 | @ Description : Invalidate a range of data cache by MVA.
67 | @
68 | @ Prototypes : void CPU_DCache_RangeInv (void *p_mem,
69 | @ CPU_SIZE_T range);
70 | @
71 | @ Argument(s) : p_mem Start address of the region to invalidate.
72 | @
73 | @ range Size of the region to invalidate in bytes.
74 | @
75 | @ Note(s) : none.
76 | @********************************************************************************************************
77 |
78 | .global CPU_DCache_RangeInv
79 |
80 | CPU_DCache_RangeInv:
81 | CMP r1, #0
82 | BEQ CPU_DCache_RangeInv_END
83 |
84 | DSB
85 | MOVW r2, #:lower16:CPU_Cache_Linesize
86 | MOVT r2, #:upper16:CPU_Cache_Linesize
87 | LDR r2, [r2]
88 | SUB r3, r2, #1
89 | ADD r1, r1, r0
90 | BIC r0, r0, r3
91 |
92 | CPU_DCache_RangeInvL1:
93 | MCR p15,0, r0, c7, c6, 1
94 | ADD r0, r0, r2
95 | CMP r0, r1
96 | BLT CPU_DCache_RangeInvL1
97 | DSB
98 |
99 | CPU_DCache_RangeInv_END:
100 | BX LR
101 |
102 |
103 | @********************************************************************************************************
104 | @ FLUSH DATA CACHE RANGE
105 | @
106 | @ Description : Flush (clean) a range of data cache by MVA.
107 | @
108 | @ Prototypes : void CPU_DCache_RangeFlush (void *p_mem,
109 | @ CPU_SIZE_T range)@
110 | @
111 | @ Argument(s) : p_mem Start address of the region to flush.
112 | @
113 | @ range Size of the region to invalidate in bytes.
114 | @
115 | @ Note(s) : none.
116 | @********************************************************************************************************
117 |
118 | .global CPU_DCache_RangeFlush
119 |
120 | CPU_DCache_RangeFlush:
121 | CMP r1, #0
122 | BEQ CPU_DCache_RangeFlush_END
123 |
124 | DSB
125 | MOVW r2, #:lower16:CPU_Cache_Linesize
126 | MOVT r2, #:upper16:CPU_Cache_Linesize
127 | LDR r2, [r2]
128 | SUB r3, r2, #1
129 | ADD r1, r1, r0
130 | BIC r0, r0, r3
131 |
132 | CPU_DCache_RangeFlushL1:
133 | MCR p15, 0, r0, c7, c10, 1
134 | ADD r0, r0, r2
135 | CMP r0, r1
136 | BLT CPU_DCache_RangeFlushL1
137 | DSB
138 |
139 | CPU_DCache_RangeFlush_END:
140 | BX LR
141 |
--------------------------------------------------------------------------------
/AVR/ATxmega128/IAR/cpu_a.s90:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CPU PORT FILE
21 | *
22 | * Atmel Xmega128
23 | * IAR C Compiler
24 | *
25 | * Filename : cpu_a.s90
26 | * Version : V1.32.01
27 | *********************************************************************************************************
28 | */
29 |
30 |
31 | /*
32 | *********************************************************************************************************
33 | * ASM HEADER
34 | *********************************************************************************************************
35 | */
36 |
37 | MODULE CPU_A
38 |
39 | RSEG FARCODE:CODE:NOROOT(1)
40 |
41 |
42 | /*
43 | *********************************************************************************************************
44 | * DEFINES
45 | *********************************************************************************************************
46 | */
47 |
48 | SREG EQU 0x3F /* Status Register */
49 |
50 |
51 | /*
52 | *********************************************************************************************************
53 | * PUBLIC DECLARATIONS
54 | *********************************************************************************************************
55 | */
56 |
57 | PUBLIC CPU_SR_Save
58 | PUBLIC CPU_SR_Restore
59 | PUBLIC CPU_IntDis
60 |
61 |
62 | /*
63 | *********************************************************************************************************
64 | * DISABLE/ENABLE INTERRUPTS USING OS_CRITICAL_METHOD #3
65 | *
66 | * Description : These functions are used to disable and enable interrupts using OS_CRITICAL_METHOD #3.
67 | *
68 | * CPU_SR CPU_SR_Save (void)
69 | * Get current value of SREG
70 | * Disable interrupts
71 | * Return original value of SREG
72 | *
73 | * void CPU_SR_Restore (OS_CPU_SR cpu_sr)
74 | * Set SREG to cpu_sr
75 | * Return
76 | *********************************************************************************************************
77 | */
78 |
79 | CPU_SR_Save:
80 | IN R16,SREG /* Get current state of interrupts disable flag */
81 | CLI /* Disable interrupts */
82 | RET /* Return original SREG value in R16 */
83 |
84 |
85 | CPU_SR_Restore:
86 | OUT SREG,R16 /* Restore SREG */
87 | RET /* Return */
88 |
89 |
90 | /*
91 | *********************************************************************************************************
92 | * DISABLE INTERRUPTS
93 | *
94 | * Description : This function is used to disable interrupts.
95 | *
96 | * void CPU_IntDis (void)
97 | * Disable interrupts
98 | * Return
99 | *********************************************************************************************************
100 | */
101 |
102 | CPU_IntDis:
103 | CLI /* Disable interrupts */
104 | RET /* Return */
105 |
106 |
107 | /*
108 | *********************************************************************************************************
109 | * CPU ASSEMBLY PORT FILE END
110 | *********************************************************************************************************
111 | */
112 |
113 | END
114 |
--------------------------------------------------------------------------------
/Cache/ARM/armv7_generic_l1/ARM/cpu_cache_armv7_generic_l1_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU CACHE IMPLEMENTATION
18 | ; ARMv7 Generic L1 Cache
19 | ; ARM C Compiler
20 | ;
21 | ; Filename : cpu_cache_armv7_generic_l1_a.s
22 | ; Version : V1.32.01
23 | ;********************************************************************************************************
24 |
25 | ;********************************************************************************************************
26 | ; MACROS AND DEFINIITIONS
27 | ;********************************************************************************************************
28 |
29 | PRESERVE8
30 |
31 | AREA BSP_Cache,CODE,READONLY
32 |
33 | ENTRY
34 |
35 |
36 | CPU_CACHE_L2C_REG7_CACHE_SYNC EQU 0x730
37 | CPU_CACHE_L2C_REG7_CACHE_INV_PA EQU 0x770
38 | CPU_CACHE_L2C_REG7_CACHE_INV_WAY EQU 0x77C
39 | CPU_CACHE_L2C_REG7_CACHE_CLEAN_PA EQU 0x7B0
40 |
41 |
42 | IMPORT CPU_Cache_Linesize
43 |
44 |
45 | ;********************************************************************************************************
46 | ; CPU_DCache_LineSizeGet()
47 | ;
48 | ; Description : Returns the cache line size.
49 | ;
50 | ; Prototypes : void CPU_DCache_LineSizeGet (void)
51 | ;
52 | ; Argument(s) : none.
53 | ;********************************************************************************************************
54 |
55 | EXPORT CPU_DCache_LineSizeGet
56 |
57 | CPU_DCache_LineSizeGet FUNCTION
58 |
59 | MRC p15, 0, r0, c0, c0, 1
60 | AND r0, r0, #0xF0000
61 | LSR r0, r0, #16
62 | MOV r1, #1
63 | LSL r1, r1, r0
64 | LSL r0, r1, #2
65 |
66 | BX lr
67 |
68 | ENDFUNC
69 |
70 |
71 | ;********************************************************************************************************
72 | ; INVALIDATE DATA CACHE RANGE
73 | ;
74 | ; Description : Invalidate a range of data cache by MVA.
75 | ;
76 | ; Prototypes : void CPU_DCache_RangeInv (void *p_mem,
77 | ; CPU_SIZE_T range);
78 | ;
79 | ; Argument(s) : p_mem Start address of the region to invalidate.
80 | ;
81 | ; range Size of the region to invalidate in bytes.
82 | ;
83 | ; Note(s) : none.
84 | ;********************************************************************************************************
85 |
86 | EXPORT CPU_DCache_RangeInv
87 |
88 | CPU_DCache_RangeInv FUNCTION
89 | CMP r1, #0
90 | BEQ CPU_DCache_RangeInv_END
91 |
92 | DSB
93 | MOV32 r2, CPU_Cache_Linesize
94 | LDR r2, [r2]
95 | SUB r3, r2, #1
96 | ADD r1, r1, r0
97 | BIC r0, r0, r3
98 |
99 | CPU_DCache_RangeInvL1
100 | MCR p15,0, r0, c7, c6, 1
101 | ADD r0, r0, r2
102 | CMP r0, r1
103 | BLT CPU_DCache_RangeInvL1
104 | DSB
105 |
106 | CPU_DCache_RangeInv_END
107 | BX LR
108 |
109 | ENDFUNC
110 |
111 |
112 | ;********************************************************************************************************
113 | ; FLUSH DATA CACHE RANGE
114 | ;
115 | ; Description : Flush (clean) a range of data cache by MVA.
116 | ;
117 | ; Prototypes : void CPU_DCache_RangeFlush (void *p_mem,
118 | ; CPU_SIZE_T range);
119 | ;
120 | ; Argument(s) : p_mem Start address of the region to flush.
121 | ;
122 | ; range Size of the region to invalidate in bytes.
123 | ;
124 | ; Note(s) : none.
125 | ;********************************************************************************************************
126 |
127 | EXPORT CPU_DCache_RangeFlush
128 |
129 | CPU_DCache_RangeFlush FUNCTION
130 | CMP r1, #0
131 | BEQ CPU_DCache_RangeFlush_END
132 |
133 | DSB
134 | MOV32 r2, CPU_Cache_Linesize
135 | LDR r2, [r2]
136 | SUB r3, r2, #1
137 | ADD r1, r1, r0
138 | BIC r0, r0, r3
139 |
140 | CPU_DCache_RangeFlushL1
141 | MCR p15, 0, r0, c7, c10, 1
142 | ADD r0, r0, r2
143 | CMP r0, r1
144 | BLT CPU_DCache_RangeFlushL1
145 | DSB
146 |
147 | CPU_DCache_RangeFlush_END
148 | BX LR
149 |
150 | ENDFUNC
151 |
152 |
153 | END
154 |
--------------------------------------------------------------------------------
/cpu_cache.h:
--------------------------------------------------------------------------------
1 | /*
2 | *********************************************************************************************************
3 | * uC/CPU
4 | * CPU CONFIGURATION & PORT LAYER
5 | *
6 | * Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | *
8 | * SPDX-License-Identifier: APACHE-2.0
9 | *
10 | * This software is subject to an open source license and is distributed by
11 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | *
14 | *********************************************************************************************************
15 | */
16 |
17 | /*
18 | *********************************************************************************************************
19 | *
20 | * CACHE CPU MODULE
21 | *
22 | * Filename : cpu_cache.h
23 | * Version : V1.32.01
24 | *********************************************************************************************************
25 | */
26 |
27 |
28 | /*
29 | *********************************************************************************************************
30 | * MODULE
31 | *
32 | * Note(s) : (1) This cache CPU header file is protected from multiple pre-processor inclusion through use of
33 | * the cache CPU module present pre-processor macro definition.
34 | *********************************************************************************************************
35 | */
36 |
37 | #ifndef CPU_CACHE_MODULE_PRESENT /* See Note #1. */
38 | #define CPU_CACHE_MODULE_PRESENT
39 |
40 |
41 | /*
42 | *********************************************************************************************************
43 | * EXTERNS
44 | *********************************************************************************************************
45 | */
46 |
47 | #ifdef CPU_CACHE_MODULE
48 | #define CPU_CACHE_EXT
49 | #else
50 | #define CPU_CACHE_EXT extern
51 | #endif
52 |
53 |
54 | /*
55 | *********************************************************************************************************
56 | * INCLUDE FILES
57 | *********************************************************************************************************
58 | */
59 |
60 | #include
61 | #include
62 | #include
63 |
64 |
65 | /*
66 | *********************************************************************************************************
67 | * CACHE CONFIGURATION
68 | *********************************************************************************************************
69 | */
70 |
71 | #ifndef CPU_CFG_CACHE_MGMT_EN
72 | #define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
73 | #endif
74 |
75 |
76 | /*
77 | *********************************************************************************************************
78 | * CACHE OPERATIONS DEFINES
79 | *********************************************************************************************************
80 | */
81 |
82 | #if (CPU_CFG_CACHE_MGMT_EN == DEF_ENABLED)
83 | #ifndef CPU_DCACHE_RANGE_FLUSH
84 | #define CPU_DCACHE_RANGE_FLUSH(addr_start, len) CPU_DCache_RangeFlush(addr_start, len)
85 | #endif /* CPU_DCACHE_RANGE_FLUSH */
86 | #else
87 | #define CPU_DCACHE_RANGE_FLUSH(addr_start, len)
88 | #endif /* CPU_CFG_CACHE_MGMT_EN) */
89 |
90 |
91 | #if (CPU_CFG_CACHE_MGMT_EN == DEF_ENABLED)
92 | #ifndef CPU_DCACHE_RANGE_INV
93 | #define CPU_DCACHE_RANGE_INV(addr_start, len) CPU_DCache_RangeInv(addr_start, len)
94 | #endif /* CPU_DCACHE_RANGE_INV */
95 | #else
96 | #define CPU_DCACHE_RANGE_INV(addr_start, len)
97 | #endif /* CPU_CFG_CACHE_MGMT_EN) */
98 |
99 |
100 | /*
101 | *********************************************************************************************************
102 | * FUNCTION PROTOTYPES
103 | *********************************************************************************************************
104 | */
105 |
106 | #if (CPU_CFG_CACHE_MGMT_EN == DEF_ENABLED)
107 |
108 | #ifdef __cplusplus
109 | extern "C" {
110 | #endif
111 |
112 | void CPU_Cache_Init (void);
113 |
114 | void CPU_DCache_RangeFlush(void *addr_start,
115 | CPU_ADDR len);
116 |
117 | void CPU_DCache_RangeInv (void *addr_start,
118 | CPU_ADDR len);
119 |
120 | #ifdef __cplusplus
121 | }
122 | #endif
123 |
124 | #endif /* CPU_CFG_CACHE_MGMT_EN */
125 |
126 |
127 | /*
128 | *********************************************************************************************************
129 | * MODULE END
130 | *
131 | * Note(s) : (1) See 'cpu_core.h MODULE'.
132 | *********************************************************************************************************
133 | */
134 |
135 | #endif /* End of CPU core module include. */
136 |
--------------------------------------------------------------------------------
/ColdFire/Generic/IAR/cpu_a.asm:
--------------------------------------------------------------------------------
1 | /*
2 | ;********************************************************************************************************
3 | ; uC/CPU
4 | ; CPU CONFIGURATION & PORT LAYER
5 | ;
6 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
7 | ;
8 | ; SPDX-License-Identifier: APACHE-2.0
9 | ;
10 | ; This software is subject to an open source license and is distributed by
11 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
12 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
13 | ;
14 | ;********************************************************************************************************
15 | */
16 |
17 | /*
18 | ;********************************************************************************************************
19 | ;
20 | ; CPU PORT FILE
21 | ;
22 | ; ColdFire
23 | ; IAR C Compiler
24 | ;
25 | ; Filename : cpu_a.asm
26 | ; Version : V1.32.01
27 | ;********************************************************************************************************
28 | */
29 |
30 | /*
31 | ;********************************************************************************************************
32 | ; PUBLIC DECLARATIONS
33 | ;********************************************************************************************************
34 | */
35 |
36 | PUBLIC CPU_VectInit
37 |
38 | PUBLIC CPU_SR_Save
39 | PUBLIC CPU_SR_Restore
40 |
41 | /*
42 | ;********************************************************************************************************
43 | ; EXTERNAL DECLARATIONS
44 | ;********************************************************************************************************
45 | */
46 |
47 | EXTERN CPU_VBR_Ptr
48 |
49 | RSEG CODE:CODE:NOROOT(2) /* Align to power 2, 4 bytes. */
50 |
51 | /*
52 | ;********************************************************************************************************
53 | ; VECTOR BASE REGISTER INITIALIZATION
54 | ;
55 | ; Description : This function is called to set the Vector Base Register to the value specified in
56 | ; the function argument.
57 | ;
58 | ; Argument(s) : VBR Desired vector base address.
59 | ;
60 | ; Return(s) : none.
61 | ;
62 | ; Note(s) : (1) 'CPU_VBR_Ptr' keeps the current vector base address.
63 | ;
64 | ; (2) 'VBR' parameter is assumed to be passed on D0 by the compiler.
65 | ;********************************************************************************************************
66 | */
67 |
68 | CPU_VectInit:
69 | MOVE.L D0, (CPU_VBR_Ptr) /* Save 'vbr' into CPU_VBR_Ptr */
70 | MOVEC D0, VBR
71 | RTS
72 |
73 |
74 | /*
75 | ;********************************************************************************************************
76 | ; CPU_SR_Save() for OS_CRITICAL_METHOD #3
77 | ;
78 | ; Description : This functions implements the OS_CRITICAL_METHOD #3 function to preserve the state of the
79 | ; interrupt disable flag in order to be able to restore it later.
80 | ;
81 | ; Argument(s) : none.
82 | ;
83 | ; Return(s) : It is assumed that the return value is placed in the D0 register as expected by the
84 | ; compiler.
85 | ;
86 | ; Note(s) : none.
87 | ;********************************************************************************************************
88 | */
89 |
90 | CPU_SR_Save:
91 | MOVE.W SR, D0 /* Copy SR into D0 */
92 | MOVE.W D0, D1
93 | ORI.L #0x0700, D1 /* Disable interrupts */
94 | MOVE.W D1, SR /* Restore SR state with interrupts disabled */
95 | RTS
96 |
97 |
98 | /*
99 | ;********************************************************************************************************
100 | ; CPU_SR_Restore() for OS_CRITICAL_METHOD #3
101 | ;
102 | ; Description : This functions implements the OS_CRITICAL_METHOD #function to restore the state of the
103 | ; interrupt flag.
104 | ;
105 | ; Argument(s) : cpu_sr Contents of the SR to restore. It is assumed that 'cpu_sr' is passed in D0.
106 | ;
107 | ; Return(s) : none.
108 | ;
109 | ; Note(s) : none.
110 | ;********************************************************************************************************
111 | */
112 |
113 | CPU_SR_Restore:
114 | MOVE.W D0, SR /* Restore SR previous state */
115 | RTS
116 |
117 |
118 | /*
119 | ;********************************************************************************************************
120 | ; CPU ASSEMBLY PORT FILE END
121 | ;********************************************************************************************************
122 | */
123 |
124 | END
125 |
--------------------------------------------------------------------------------
/RISC-V/GCC/cpu_a.S:
--------------------------------------------------------------------------------
1 | #********************************************************************************************************
2 | # uC/CPU
3 | # CPU CONFIGURATION & PORT LAYER
4 | #
5 | # Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | #
7 | # SPDX-License-Identifier: APACHE-2.0
8 | #
9 | # This software is subject to an open source license and is distributed by
10 | # Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | # Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | #
13 | #********************************************************************************************************
14 |
15 | #********************************************************************************************************
16 | #
17 | # CPU PORT FILE
18 | #
19 | # RISC-V
20 | # GNU C Compiler
21 | #
22 | # Filename : cpu_a.S
23 | # Version : V1.32.01
24 | #********************************************************************************************************
25 |
26 |
27 | #********************************************************************************************************
28 | # PUBLIC FUNCTIONS
29 | #********************************************************************************************************
30 |
31 | .global CPU_SR_Save
32 | .global CPU_SR_Restore
33 |
34 | .global CPU_IntDis
35 | .global CPU_IntEn
36 |
37 |
38 | #********************************************************************************************************
39 | # EQUATES
40 | #********************************************************************************************************
41 |
42 | .equ CPU_MSTATUS_MIE, 0x08
43 |
44 |
45 | #********************************************************************************************************
46 | # CODE GENERATION DIRECTIVES
47 | #********************************************************************************************************
48 |
49 | .section .text
50 |
51 |
52 | #********************************************************************************************************
53 | # DISABLE/ENABLE INTERRUPTS
54 | #
55 | # Description : Disable/Enable interrupts.
56 | #
57 | # (1) (a) For CPU_CRITICAL_METHOD_INT_DIS_EN, interrupts are enabled/disabled WITHOUT saving
58 | # or restoring the state of the interrupt status.
59 | #
60 | #
61 | # Prototypes : void CPU_IntDis(void);
62 | # void CPU_IntEn (void);
63 | #********************************************************************************************************
64 |
65 | CPU_IntDis:
66 | # Disable global interupt
67 | li t0, CPU_MSTATUS_MIE
68 | csrrc zero, mstatus, t0
69 | ret
70 |
71 |
72 | CPU_IntEn:
73 | # Enable global interupt
74 | li t0, CPU_MSTATUS_MIE
75 | csrrs zero, mstatus, t0
76 | ret
77 |
78 |
79 |
80 | #********************************************************************************************************
81 | # CRITICAL SECTION FUNCTIONS
82 | #
83 | # Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
84 | # state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
85 | # are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
86 | # The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
87 | #
88 | # Prototypes : CPU_SR CPU_SR_Save (void);
89 | # void CPU_SR_Restore(CPU_SR cpu_sr);
90 | #
91 | # Note(s) : (1) These functions are used in general like this :
92 | #
93 | # void Task (void *p_arg)
94 | # {
95 | # CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
96 | # :
97 | # :
98 | # CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save()# */
99 | # :
100 | # :
101 | # CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr)# */
102 | # :
103 | # }
104 | #********************************************************************************************************
105 |
106 | CPU_SR_Save:
107 | # Save the Machine status register
108 | csrr a0, mstatus
109 | # Disable global interupt
110 | li t0, CPU_MSTATUS_MIE
111 | csrrc zero, mstatus, t0
112 | ret
113 |
114 |
115 | CPU_SR_Restore:
116 | # restore the Machine status register previous state
117 | csrw mstatus, a0
118 | ret
119 |
120 |
121 | #********************************************************************************************************
122 | # CPU ASSEMBLY PORT FILE END
123 | #********************************************************************************************************
124 |
--------------------------------------------------------------------------------
/V850ES/PM+/cpu_a.s:
--------------------------------------------------------------------------------
1 | #********************************************************************************************************
2 | #* uC/CPU
3 | #* CPU CONFIGURATION & PORT LAYER
4 | #*
5 | #* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | #*
7 | #* SPDX-License-Identifier: APACHE-2.0
8 | #*
9 | #* This software is subject to an open source license and is distributed by
10 | #* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | #* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | #*
13 | #********************************************************************************************************
14 |
15 | #********************************************************************************************************
16 | #
17 | # CPU PORT FILE
18 | #
19 | # V850ES
20 | # Renesas CA850
21 | #
22 | # Filename : cpu_a.s
23 | # Version : V1.32.01
24 | #********************************************************************************************************
25 |
26 |
27 |
28 | #********************************************************************************************************
29 | # PUBLIC FUNCTIONS
30 | #********************************************************************************************************
31 |
32 |
33 | .extern _CPU_SR_Save
34 | .extern _CPU_SR_Restore
35 | .extern _CPU_IntDis
36 | .extern _CPU_IntEn
37 | .extern _CPU_ECR_Rd
38 |
39 |
40 | #********************************************************************************************************
41 | # EQUATES
42 | #********************************************************************************************************
43 |
44 | .set ECR, 4
45 | .set PSW, 5
46 |
47 | #********************************************************************************************************
48 | # CODE GENERATION DIRECTIVES
49 | #********************************************************************************************************
50 |
51 | .text
52 | .align 4
53 |
54 | #********************************************************************************************************
55 | # SAVE/RESTORE CPU STATUS REGISTER
56 | #
57 | # Description : Save/Restore the state of CPU interrupts, if possible.
58 | #
59 | # (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
60 | # stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
61 | # allocated in all functions that need to disable interrupts). The previous interrupt
62 | # status state is restored by copying 'cpu_sr' into the CPU's status register.
63 | #
64 | #
65 | # Prototypes : CPU_SR CPU_SR_Save (void);
66 | # void CPU_SR_Restore(CPU_SR cpu_sr);
67 | #
68 | # Note(s) : (1) These functions are used in general like this :
69 | #
70 | # void Task (void *p_arg)
71 | # {
72 | # CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
73 | # :
74 | # :
75 | # CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
76 | # :
77 | # :
78 | # CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
79 | # :
80 | # }
81 | #********************************************************************************************************
82 |
83 | _CPU_SR_Save:
84 | stsr PSW, r10 -- Store PSW
85 | di
86 | jmp [lp]
87 |
88 | _CPU_SR_Restore:
89 | ldsr r6 , PSW
90 | jmp [lp]
91 |
92 | #********************************************************************************************************
93 | # DISABLE and ENABLE INTERRUPTS
94 | #
95 | # Description: Disable/Enable interrupts.
96 | #
97 | # Prototypes : void CPU_IntDis(void);
98 | # void CPU_IntEn (void);
99 | #********************************************************************************************************
100 |
101 | _CPU_IntDis:
102 | di
103 | jmp [lp]
104 |
105 | _CPU_IntEn:
106 | ei
107 | jmp [lp]
108 |
109 | #********************************************************************************************************
110 | # READS CPU EXCEPTION CAUSE REGISTER
111 | #
112 | # Description : Reads CPU exception code register(ECR), which identifies each interrupt source according to
113 | # its exception code.
114 | #
115 | # Prototypes : CPU_DATA CPU_ECR_Rd (void);
116 | #
117 | # Note(s) : None.
118 | #
119 | #********************************************************************************************************
120 |
121 | _CPU_ECR_Rd:
122 | stsr ECR, r10
123 | jmp [lp]
124 |
125 | #********************************************************************************************************
126 | # CPU ASSEMBLY PORT FILE END
127 | #********************************************************************************************************
128 |
--------------------------------------------------------------------------------
/V850E2M/IAR/cpu_a.s85:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; V850E2M
20 | ; IAR compiler for V850
21 | ;
22 | ; Filename : cpu_a.s85
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 |
28 | ;********************************************************************************************************
29 | ; PUBLIC FUNCTIONS
30 | ;********************************************************************************************************
31 |
32 | PUBLIC CPU_SR_Save
33 | PUBLIC CPU_SR_Restore
34 | PUBLIC CPU_IntDis
35 | PUBLIC CPU_IntEn
36 | PUBLIC CPU_EIIC_Rd
37 |
38 |
39 | ;********************************************************************************************************
40 | ; EQUATES
41 | ;********************************************************************************************************
42 |
43 | PSW EQU 5
44 | EIIC EQU 13
45 |
46 |
47 | ;********************************************************************************************************
48 | ; CODE GENERATION DIRECTIVES
49 | ;********************************************************************************************************
50 |
51 | RSEG CODE:CODE:NOROOT(2)
52 |
53 |
54 | ;********************************************************************************************************
55 | ; SAVE/RESTORE CPU STATUS REGISTER
56 | ;
57 | ; Description : Save/Restore the state of CPU interrupts, if possible.
58 | ;
59 | ; (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
60 | ; stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
61 | ; allocated in all functions that need to disable interrupts). The previous interrupt
62 | ; status state is restored by copying 'cpu_sr' into the CPU's status register.
63 | ;
64 | ;
65 | ; Prototypes : CPU_SR CPU_SR_Save (void);
66 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
67 | ;
68 | ; Note(s) : (1) These functions are used in general like this :
69 | ;
70 | ; void Task (void *p_arg)
71 | ; {
72 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
73 | ; :
74 | ; :
75 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
76 | ; :
77 | ; :
78 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
79 | ; :
80 | ; }
81 | ;********************************************************************************************************
82 |
83 | CPU_SR_Save:
84 | stsr PSW, r1 ; Store PSW
85 | di
86 | jmp [lp]
87 |
88 | CPU_SR_Restore:
89 | ldsr r1 , PSW
90 | jmp [lp]
91 |
92 | ;********************************************************************************************************
93 | ; DISABLE and ENABLE INTERRUPTS
94 | ;
95 | ; Description: Disable/Enable interrupts.
96 | ;
97 | ; Prototypes : void CPU_IntDis(void);
98 | ; void CPU_IntEn (void);
99 | ;********************************************************************************************************
100 |
101 | CPU_IntDis:
102 | di
103 | jmp [lp]
104 |
105 | CPU_IntEn:
106 | ei
107 | jmp [lp]
108 |
109 |
110 | ;********************************************************************************************************
111 | ; READS CPU EXCEPTION CAUSE REGISTER
112 | ;
113 | ; Description : Reads CPU EI level exception code register(EIIC), which retains the cause of any EI level
114 | ; exception that occurs.
115 | ;
116 | ; Prototypes : CPU_DATA CPU_EIIC_Rd (void);
117 | ;
118 | ; Note(s) : None.
119 | ;
120 | ;********************************************************************************************************
121 |
122 | CPU_EIIC_Rd:
123 | stsr EIIC, r1
124 | jmp [lp]
125 |
126 |
127 | ;********************************************************************************************************
128 | ; CPU ASSEMBLY PORT FILE END
129 | ;********************************************************************************************************
130 |
131 | END
132 |
--------------------------------------------------------------------------------
/V850ES/CubeSuite/cpu_a.s:
--------------------------------------------------------------------------------
1 | #********************************************************************************************************
2 | #* uC/CPU
3 | #* CPU CONFIGURATION & PORT LAYER
4 | #*
5 | #* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | #*
7 | #* SPDX-License-Identifier: APACHE-2.0
8 | #*
9 | #* This software is subject to an open source license and is distributed by
10 | #* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | #* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | #*
13 | #********************************************************************************************************
14 |
15 | #********************************************************************************************************
16 | #
17 | # CPU PORT FILE
18 | #
19 | # V850ES
20 | # Renesas CA850
21 | #
22 | # Filename : cpu_a.s
23 | # Version : V1.32.01
24 | #********************************************************************************************************
25 |
26 |
27 |
28 | #********************************************************************************************************
29 | # PUBLIC FUNCTIONS
30 | #********************************************************************************************************
31 |
32 |
33 | .extern _CPU_SR_Save
34 | .extern _CPU_SR_Restore
35 | .extern _CPU_IntDis
36 | .extern _CPU_IntEn
37 | .extern _CPU_ECR_Rd
38 |
39 |
40 | #********************************************************************************************************
41 | # EQUATES
42 | #********************************************************************************************************
43 |
44 | .set ECR, 4
45 | .set PSW, 5
46 |
47 | #********************************************************************************************************
48 | # CODE GENERATION DIRECTIVES
49 | #********************************************************************************************************
50 |
51 | .text
52 | .align 4
53 |
54 | #********************************************************************************************************
55 | # SAVE/RESTORE CPU STATUS REGISTER
56 | #
57 | # Description : Save/Restore the state of CPU interrupts, if possible.
58 | #
59 | # (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
60 | # stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
61 | # allocated in all functions that need to disable interrupts). The previous interrupt
62 | # status state is restored by copying 'cpu_sr' into the CPU's status register.
63 | #
64 | #
65 | # Prototypes : CPU_SR CPU_SR_Save (void);
66 | # void CPU_SR_Restore(CPU_SR cpu_sr);
67 | #
68 | # Note(s) : (1) These functions are used in general like this :
69 | #
70 | # void Task (void *p_arg)
71 | # {
72 | # CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
73 | # :
74 | # :
75 | # CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
76 | # :
77 | # :
78 | # CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
79 | # :
80 | # }
81 | #********************************************************************************************************
82 |
83 | _CPU_SR_Save:
84 | stsr PSW, r10 -- Store PSW
85 | di
86 | jmp [lp]
87 |
88 | _CPU_SR_Restore:
89 | ldsr r6 , PSW
90 | jmp [lp]
91 |
92 | #********************************************************************************************************
93 | # DISABLE and ENABLE INTERRUPTS
94 | #
95 | # Description: Disable/Enable interrupts.
96 | #
97 | # Prototypes : void CPU_IntDis(void);
98 | # void CPU_IntEn (void);
99 | #********************************************************************************************************
100 |
101 | _CPU_IntDis:
102 | di
103 | jmp [lp]
104 |
105 | _CPU_IntEn:
106 | ei
107 | jmp [lp]
108 |
109 | #********************************************************************************************************
110 | # READS CPU EXCEPTION CAUSE REGISTER
111 | #
112 | # Description : Reads CPU exception code register(ECR), which identifies each interrupt source according to
113 | # its exception code.
114 | #
115 | # Prototypes : CPU_DATA CPU_ECR_Rd (void);
116 | #
117 | # Note(s) : None.
118 | #
119 | #********************************************************************************************************
120 |
121 | _CPU_ECR_Rd:
122 | stsr ECR, r10
123 | jmp [lp]
124 |
125 | #********************************************************************************************************
126 | # CPU ASSEMBLY PORT FILE END
127 | #********************************************************************************************************
128 |
--------------------------------------------------------------------------------
/V850E2S/IAR/cpu_a.s85:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; V850E2S
20 | ; IAR compiler for V850
21 | ;
22 | ; Filename : cpu_a.s85
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 |
28 | ;********************************************************************************************************
29 | ; PUBLIC FUNCTIONS
30 | ;********************************************************************************************************
31 |
32 | PUBLIC CPU_SR_Save
33 | PUBLIC CPU_SR_Restore
34 | PUBLIC CPU_IntDis
35 | PUBLIC CPU_IntEn
36 | PUBLIC CPU_EIIC_Rd
37 |
38 |
39 | ;********************************************************************************************************
40 | ; EQUATES
41 | ;********************************************************************************************************
42 |
43 | PSW EQU 5
44 | EIIC EQU 13
45 |
46 |
47 | ;********************************************************************************************************
48 | ; CODE GENERATION DIRECTIVES
49 | ;********************************************************************************************************
50 |
51 | RSEG CODE:CODE:NOROOT(2)
52 |
53 |
54 | ;********************************************************************************************************
55 | ; SAVE/RESTORE CPU STATUS REGISTER
56 | ;
57 | ; Description : Save/Restore the state of CPU interrupts, if possible.
58 | ;
59 | ; (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
60 | ; stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
61 | ; allocated in all functions that need to disable interrupts). The previous interrupt
62 | ; status state is restored by copying 'cpu_sr' into the CPU's status register.
63 | ;
64 | ;
65 | ; Prototypes : CPU_SR CPU_SR_Save (void);
66 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
67 | ;
68 | ; Note(s) : (1) These functions are used in general like this :
69 | ;
70 | ; void Task (void *p_arg)
71 | ; {
72 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
73 | ; :
74 | ; :
75 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
76 | ; :
77 | ; :
78 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
79 | ; :
80 | ; }
81 | ;********************************************************************************************************
82 |
83 | CPU_SR_Save:
84 | stsr PSW, r1 ; Store PSW
85 | di
86 | jmp [lp]
87 |
88 | CPU_SR_Restore:
89 | ldsr r1 , PSW
90 | jmp [lp]
91 |
92 |
93 | ;********************************************************************************************************
94 | ; DISABLE and ENABLE INTERRUPTS
95 | ;
96 | ; Description: Disable/Enable interrupts.
97 | ;
98 | ; Prototypes : void CPU_IntDis(void);
99 | ; void CPU_IntEn (void);
100 | ;********************************************************************************************************
101 |
102 | CPU_IntDis:
103 | di
104 | jmp [lp]
105 |
106 | CPU_IntEn:
107 | ei
108 | jmp [lp]
109 |
110 |
111 | ;********************************************************************************************************
112 | ; READS CPU EXCEPTION CAUSE REGISTER
113 | ;
114 | ; Description : Reads CPU EI level exception code register(EIIC), which retains the cause of any EI level
115 | ; exception that occurs.
116 | ;
117 | ; Prototypes : CPU_DATA CPU_EIIC_Rd (void);
118 | ;
119 | ; Note(s) : None.
120 | ;
121 | ;********************************************************************************************************
122 |
123 | CPU_EIIC_Rd:
124 | stsr EIIC, r1
125 | jmp [lp]
126 |
127 |
128 | ;********************************************************************************************************
129 | ; CPU ASSEMBLY PORT FILE END
130 | ;********************************************************************************************************
131 |
132 | END
133 |
--------------------------------------------------------------------------------
/V850ES/IAR/cpu_a.s85:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; V850ES
20 | ; IAR compiler for V850
21 | ;
22 | ; Filename : cpu_a.s85
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 |
28 | ;********************************************************************************************************
29 | ; PUBLIC FUNCTIONS
30 | ;********************************************************************************************************
31 |
32 |
33 | PUBLIC CPU_SR_Save
34 | PUBLIC CPU_SR_Restore
35 | PUBLIC CPU_IntDis
36 | PUBLIC CPU_IntEn
37 | PUBLIC CPU_ECR_Rd
38 |
39 |
40 | ;********************************************************************************************************
41 | ; EQUATES
42 | ;********************************************************************************************************
43 |
44 | ECR EQU 4
45 | PSW EQU 5
46 |
47 |
48 | ;********************************************************************************************************
49 | ; CODE GENERATION DIRECTIVES
50 | ;********************************************************************************************************
51 |
52 | RSEG CODE:CODE:NOROOT(2)
53 |
54 |
55 | ;********************************************************************************************************
56 | ; SAVE/RESTORE CPU STATUS REGISTER
57 | ;
58 | ; Description : Save/Restore the state of CPU interrupts, if possible.
59 | ;
60 | ; (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
61 | ; stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
62 | ; allocated in all functions that need to disable interrupts). The previous interrupt
63 | ; status state is restored by copying 'cpu_sr' into the CPU's status register.
64 | ;
65 | ;
66 | ; Prototypes : CPU_SR CPU_SR_Save (void);
67 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
68 | ;
69 | ; Note(s) : (1) These functions are used in general like this :
70 | ;
71 | ; void Task (void *p_arg)
72 | ; {
73 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
74 | ; :
75 | ; :
76 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
77 | ; :
78 | ; :
79 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
80 | ; :
81 | ; }
82 | ;********************************************************************************************************
83 |
84 | CPU_SR_Save:
85 | stsr PSW, r1 ; Store PSW
86 | di
87 | jmp [lp]
88 |
89 | CPU_SR_Restore:
90 | ldsr r1 , PSW
91 | jmp [lp]
92 |
93 |
94 | ;********************************************************************************************************
95 | ; DISABLE and ENABLE INTERRUPTS
96 | ;
97 | ; Description: Disable/Enable interrupts.
98 | ;
99 | ; Prototypes : void CPU_IntDis(void);
100 | ; void CPU_IntEn (void);
101 | ;********************************************************************************************************
102 |
103 | CPU_IntDis:
104 | di
105 | jmp [lp]
106 |
107 | CPU_IntEn:
108 | ei
109 | jmp [lp]
110 |
111 |
112 | ;********************************************************************************************************
113 | ; READS CPU EXCEPTION CAUSE REGISTER
114 | ;
115 | ; Description : Reads CPU EI level exception code register(EIIC), which retains the cause of any EI level
116 | ; exception that occurs.
117 | ;
118 | ; Prototypes : CPU_DATA CPU_EIIC_Read (void);
119 | ;
120 | ; Note(s) : None.
121 | ;
122 | ;********************************************************************************************************
123 |
124 | CPU_ECR_Rd:
125 | stsr ECR, r1
126 | jmp [lp]
127 |
128 |
129 | ;********************************************************************************************************
130 | ; CPU ASSEMBLY PORT FILE END
131 | ;********************************************************************************************************
132 |
133 | END
134 |
--------------------------------------------------------------------------------
/V850E2M/CubeSuite+/cpu_a.asm:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU PORT FILE
18 | ;
19 | ; V850E2M
20 | ; Renesas CX Compiler
21 | ;
22 | ; Filename : cpu_a.asm
23 | ; Version : V1.32.01
24 | ;********************************************************************************************************
25 |
26 |
27 |
28 | ;********************************************************************************************************
29 | ; PUBLIC FUNCTIONS
30 | ;********************************************************************************************************
31 |
32 | .extern _CPU_SR_Save
33 | .extern _CPU_SR_Restore
34 | .extern _CPU_IntDis
35 | .extern _CPU_IntEn
36 | .extern _CPU_EIIC_Rd
37 |
38 |
39 | ;********************************************************************************************************
40 | ; EQUATES
41 | ;********************************************************************************************************
42 |
43 | PSW .set 5
44 | EIIC .set 13
45 |
46 |
47 | ;********************************************************************************************************
48 | ; CODE GENERATION DIRECTIVES
49 | ;********************************************************************************************************
50 |
51 | .cseg text
52 | .align 4
53 |
54 |
55 | ;********************************************************************************************************
56 | ; SAVE/RESTORE CPU STATUS REGISTER
57 | ;
58 | ; Description : Save/Restore the state of CPU interrupts, if possible.
59 | ;
60 | ; (1) (c) For CPU_CRITICAL_METHOD_STATUS_LOCAL, the state of the interrupt status flag is
61 | ; stored in the local variable 'cpu_sr' & interrupts are then disabled ('cpu_sr' is
62 | ; allocated in all functions that need to disable interrupts). The previous interrupt
63 | ; status state is restored by copying 'cpu_sr' into the CPU's status register.
64 | ;
65 | ;
66 | ; Prototypes : CPU_SR CPU_SR_Save (void);
67 | ; void CPU_SR_Restore(CPU_SR cpu_sr);
68 | ;
69 | ; Note(s) : (1) These functions are used in general like this :
70 | ;
71 | ; void Task (void *p_arg)
72 | ; {
73 | ; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
74 | ; :
75 | ; :
76 | ; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
77 | ; :
78 | ; :
79 | ; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
80 | ; :
81 | ; }
82 | ;********************************************************************************************************
83 |
84 | _CPU_SR_Save:
85 | stsr PSW, r10 ; Store PSW
86 | di
87 | jmp [lp]
88 |
89 | _CPU_SR_Restore:
90 | ldsr r6 , PSW
91 | jmp [lp]
92 |
93 |
94 | ;********************************************************************************************************
95 | ; DISABLE and ENABLE INTERRUPTS
96 | ;
97 | ; Description: Disable/Enable interrupts.
98 | ;
99 | ; Prototypes : void CPU_IntDis(void);
100 | ; void CPU_IntEn (void);
101 | ;********************************************************************************************************
102 |
103 | _CPU_IntDis:
104 | di
105 | jmp [lp]
106 |
107 | _CPU_IntEn:
108 | ei
109 | jmp [lp]
110 |
111 |
112 | ;********************************************************************************************************
113 | ; READS CPU EXCEPTION CAUSE REGISTER
114 | ;
115 | ; Description : Reads CPU EI level exception code register(EIIC), which retains the cause of any EI level
116 | ; exception that occurs.
117 | ;
118 | ; Prototypes : CPU_DATA CPU_EIIC_Rd (void);
119 | ;
120 | ; Note(s) : None.
121 | ;
122 | ;********************************************************************************************************
123 |
124 | _CPU_EIIC_Rd:
125 | stsr EIIC, r10
126 | jmp [lp]
127 |
128 |
129 | ;********************************************************************************************************
130 | ; CPU ASSEMBLY PORT FILE END
131 | ;********************************************************************************************************
132 |
--------------------------------------------------------------------------------
/Cache/ARM/armv7_generic_l1_l2c310_l2/IAR/cpu_cache_armv7_generic_l1_l2c310_l2_a.s:
--------------------------------------------------------------------------------
1 | ;********************************************************************************************************
2 | ; uC/CPU
3 | ; CPU CONFIGURATION & PORT LAYER
4 | ;
5 | ; Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | ;
7 | ; SPDX-License-Identifier: APACHE-2.0
8 | ;
9 | ; This software is subject to an open source license and is distributed by
10 | ; Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | ; Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | ;
13 | ;********************************************************************************************************
14 |
15 | ;********************************************************************************************************
16 | ;
17 | ; CPU CACHE IMPLEMENTATION
18 | ; Generic ARMv7 L1 Cache and External L2C310 L2 Cache Controller
19 | ; IAR EWARM Compiler
20 | ;
21 | ; Filename : cpu_cache_armv7_generic_l1_l2c310_l2_a.s
22 | ; Version : V1.32.01
23 | ;********************************************************************************************************
24 |
25 |
26 | ;********************************************************************************************************
27 | ; MACROS AND DEFINIITIONS
28 | ;********************************************************************************************************
29 |
30 |
31 | CPU_CACHE_L2C_REG7_CACHE_SYNC EQU 0x730
32 | CPU_CACHE_L2C_REG7_CACHE_INV_PA EQU 0x770
33 | CPU_CACHE_L2C_REG7_CACHE_INV_WAY EQU 0x77C
34 | CPU_CACHE_L2C_REG7_CACHE_CLEAN_PA EQU 0x7B0
35 |
36 |
37 | IMPORT CPU_Cache_Linesize
38 | IMPORT CPU_Cache_PL310BaseAddr
39 |
40 |
41 | PRESERVE8
42 |
43 | RSEG CODE:CODE:NOROOT(2)
44 | CODE32
45 |
46 |
47 | ;********************************************************************************************************
48 | ; CPU_DCache_LineSizeGet()
49 | ;
50 | ; Description : Returns the cache line size.
51 | ;
52 | ; Prototypes : void CPU_DCache_LineSizeGet (void)
53 | ;
54 | ; Argument(s) : none.
55 | ;********************************************************************************************************
56 |
57 | EXPORT CPU_DCache_LineSizeGet
58 |
59 | CPU_DCache_LineSizeGet
60 |
61 | MRC p15, 0, r0, c0, c0, 1
62 | AND r0, r0, #0xF0000
63 | LSR r0, r0, #16
64 | MOV r1, #1
65 | LSL r1, r1, r0
66 | LSL r0, r1, #2
67 |
68 |
69 | BX lr
70 |
71 |
72 | ;********************************************************************************************************
73 | ; INVALIDATE DATA CACHE RANGE
74 | ;
75 | ; Description : Invalidate a range of data cache by MVA.
76 | ;
77 | ; Prototypes : void CPU_DCache_RangeInv (void *p_mem,
78 | ; CPU_SIZE_T range);
79 | ;
80 | ; Argument(s) : p_mem Start address of the region to invalidate.
81 | ;
82 | ; range Size of the region to invalidate in bytes.
83 | ;
84 | ; Note(s) : none.
85 | ;********************************************************************************************************
86 |
87 | EXPORT CPU_DCache_RangeInv
88 |
89 | CPU_DCache_RangeInv
90 | CMP r1, #0
91 | BEQ CPU_DCache_RangeInv_END
92 |
93 | DSB
94 | ADD r1, r1, r0
95 | MOV32 r12, CPU_Cache_Linesize
96 | LDR r12, [r12]
97 | SUB r2, r12, #1
98 | BIC r0, r0, r2
99 | MOV r3, r0
100 |
101 | MOV32 r2, CPU_Cache_PL310BaseAddr
102 | LDR r2, [r2]
103 | CPU_DCache_RangeInvL2
104 | STR r3, [r2, #CPU_CACHE_L2C_REG7_CACHE_INV_PA]
105 | ADD r3, r3, r12
106 | CMP r3, r1
107 | BLT CPU_DCache_RangeInvL2
108 | DSB
109 |
110 | CPU_DCache_RangeInvL1
111 | MCR p15,0, r0, c7, c6, 1
112 | ADD r0, r0, r12
113 | CMP r0, r1
114 | BLT CPU_DCache_RangeInvL1
115 | DSB
116 |
117 | CPU_DCache_RangeInv_END
118 | BX LR
119 |
120 |
121 | ;********************************************************************************************************
122 | ; FLUSH DATA CACHE RANGE
123 | ;
124 | ; Description : Flush (clean) a range of data cache by MVA.
125 | ;
126 | ; Prototypes : void CPU_DCache_RangeFlush (void *p_mem,
127 | ; CPU_SIZE_T range);
128 | ;
129 | ; Argument(s) : p_mem Start address of the region to flush.
130 | ;
131 | ; range Size of the region to invalidate in bytes.
132 | ;
133 | ; Note(s) : none.
134 | ;********************************************************************************************************
135 |
136 | EXPORT CPU_DCache_RangeFlush
137 |
138 | CPU_DCache_RangeFlush
139 | CMP r1, #0
140 | BEQ CPU_DCache_RangeFlush_END
141 |
142 | DSB
143 | ADD r1, r1, r0
144 | MOV32 r12, CPU_Cache_Linesize
145 | LDR r12, [r12]
146 | SUB r2, r12, #1
147 | BIC r0, r0, r2
148 |
149 | MOV r3, r0
150 | CPU_DCache_RangeFlushL1
151 | MCR p15, 0, r3, c7, c14, 1
152 | ADD r3, r3, r12
153 | CMP r3, r1
154 | BLT CPU_DCache_RangeFlushL1
155 | DSB
156 |
157 | MOV32 r2, CPU_Cache_PL310BaseAddr
158 | LDR r2, [r2]
159 | CPU_DCache_RangeFlushL2
160 | STR r0, [r2, #CPU_CACHE_L2C_REG7_CACHE_CLEAN_PA]
161 | ADD r0, r0, r12
162 | CMP r0, r1
163 | BLT CPU_DCache_RangeFlushL2
164 | DSB
165 |
166 | CPU_DCache_RangeFlush_END
167 | BX LR
168 |
169 | END
170 |
--------------------------------------------------------------------------------
/Cache/ARM/armv7_generic_l1_l2c310_l2/GNU/cpu_cache_armv7_generic_l1_l2c310_l2_a.S:
--------------------------------------------------------------------------------
1 | @********************************************************************************************************
2 | @ uC/CPU
3 | @ CPU CONFIGURATION & PORT LAYER
4 | @
5 | @ Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
6 | @
7 | @ SPDX-License-Identifier: APACHE-2.0
8 | @
9 | @ This software is subject to an open source license and is distributed by
10 | @ Silicon Laboratories Inc. pursuant to the terms of the Apache License,
11 | @ Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
12 | @
13 | @********************************************************************************************************
14 |
15 | @********************************************************************************************************
16 | @
17 | @ CPU CACHE IMPLEMENTATION
18 | @ Generic ARMv7 L1 Cache and External L2C310 L2 Cache Controller
19 | @ GNU C Compiler
20 | @
21 | @ Filename : cpu_cache_armv7_generic_l1_l2c310_l2_a.S
22 | @ Version : V1.32.01
23 | @********************************************************************************************************
24 |
25 | @********************************************************************************************************
26 | @ MACROS AND DEFINIITIONS
27 | @********************************************************************************************************
28 |
29 |
30 | .code 32
31 |
32 |
33 | .equ CPU_CACHE_L2C_REG7_CACHE_SYNC, 0x730
34 | .equ CPU_CACHE_L2C_REG7_CACHE_INV_PA, 0x770
35 | .equ CPU_CACHE_L2C_REG7_CACHE_INV_WAY, 0x77C
36 | .equ CPU_CACHE_L2C_REG7_CACHE_CLEAN_PA, 0x7B0
37 |
38 |
39 | @********************************************************************************************************
40 | @ CPU_DCache_LineSizeGet()
41 | @
42 | @ Description : Returns the cache line size.
43 | @
44 | @ Prototypes : void CPU_DCache_LineSizeGet (void)
45 | @
46 | @ Argument(s) : none.
47 | @********************************************************************************************************
48 |
49 | .global CPU_DCache_LineSizeGet
50 |
51 | CPU_DCache_LineSizeGet:
52 |
53 | MRC p15, 0, r0, c0, c0, 1
54 | AND r0, r0, #0xF0000
55 | LSR r0, r0, #16
56 | MOV r1, #1
57 | LSL r1, r1, r0
58 | LSL r0, r1, #2
59 |
60 | BX lr
61 |
62 |
63 | @********************************************************************************************************
64 | @ INVALIDATE DATA CACHE RANGE
65 | @
66 | @ Description : Invalidate a range of data cache by MVA.
67 | @
68 | @ Prototypes : void CPU_DCache_RangeInv (void *p_mem,
69 | @ CPU_SIZE_T range)@
70 | @
71 | @ Argument(s) : p_mem Start address of the region to invalidate.
72 | @
73 | @ range Size of the region to invalidate in bytes.
74 | @
75 | @ Note(s) : none.
76 | @********************************************************************************************************
77 |
78 | .global CPU_DCache_RangeInv
79 |
80 | CPU_DCache_RangeInv:
81 | CMP r1, #0
82 | BEQ CPU_DCache_RangeInv_END
83 |
84 | DSB
85 | ADD r1, r1, r0
86 | MOVW R12, #:lower16:CPU_Cache_Linesize
87 | MOVT R12, #:upper16:CPU_Cache_Linesize
88 | LDR r12, [r12]
89 | SUB r2, r12, #1
90 | BIC r0, r0, r2
91 | MOV r3, r0
92 |
93 | MOVW r2, #:lower16:CPU_Cache_PL310BaseAddr
94 | MOVT r2, #:upper16:CPU_Cache_PL310BaseAddr
95 | LDR r2, [r2]
96 | CPU_DCache_RangeInvL2:
97 | STR r3, [r2, #CPU_CACHE_L2C_REG7_CACHE_INV_PA]
98 | ADD r3, r3, r12
99 | CMP r3, r1
100 | BLT CPU_DCache_RangeInvL2
101 | DSB
102 |
103 | CPU_DCache_RangeInvL1:
104 | MCR p15,0, r0, c7, c6, 1
105 | ADD r0, r0, r12
106 | CMP r0, r1
107 | BLT CPU_DCache_RangeInvL1
108 | DSB
109 |
110 | CPU_DCache_RangeInv_END:
111 | BX LR
112 |
113 |
114 | @********************************************************************************************************
115 | @ FLUSH DATA CACHE RANGE
116 | @
117 | @ Description : Flush (clean) a range of data cache by MVA.
118 | @
119 | @ Prototypes : void CPU_DCache_RangeFlush (void *p_mem,
120 | @ CPU_SIZE_T range)@
121 | @
122 | @ Argument(s) : p_mem Start address of the region to flush.
123 | @
124 | @ range Size of the region to invalidate in bytes.
125 | @
126 | @ Note(s) : none.
127 | @********************************************************************************************************
128 |
129 | .global CPU_DCache_RangeFlush
130 |
131 | CPU_DCache_RangeFlush:
132 | CMP r1, #0
133 | BEQ CPU_DCache_RangeFlush_END
134 |
135 | DSB
136 | ADD r1, r1, r0
137 | MOVW R12, #:lower16:CPU_Cache_Linesize
138 | MOVT R12, #:upper16:CPU_Cache_Linesize
139 | LDR r12, [r12]
140 | SUB r2, r12, #1
141 | BIC r0, r0, r2
142 |
143 | MOV r3, r0
144 | CPU_DCache_RangeFlushL1:
145 | MCR p15, 0, r3, c7, c14, 1
146 | ADD r3, r3, r12
147 | CMP r3, r1
148 | BLT CPU_DCache_RangeFlushL1
149 | DSB
150 |
151 | MOVW r2, #:lower16:CPU_Cache_PL310BaseAddr
152 | MOVT r2, #:upper16:CPU_Cache_PL310BaseAddr
153 | LDR r2, [r2]
154 | CPU_DCache_RangeFlushL2:
155 | STR r0, [r2, #CPU_CACHE_L2C_REG7_CACHE_CLEAN_PA]
156 | ADD r0, r0, r12
157 | CMP r0, r1
158 | BLT CPU_DCache_RangeFlushL2
159 | DSB
160 |
161 | CPU_DCache_RangeFlush_END:
162 | BX LR
163 |
--------------------------------------------------------------------------------