├── .gitattributes ├── .gitignore ├── CMakeLists.txt ├── LICENSE ├── README.md ├── images └── current.png └── src ├── bus.cpp ├── bus.hpp ├── cdrom ├── cdrom_core.cpp └── cdrom_core.hpp ├── cpu ├── cpu_code.cpp ├── cpu_core.cpp ├── cpu_core.hpp ├── decoder.cpp └── disassembler.cpp ├── dma ├── dma_core.cpp └── dma_core.hpp ├── gpu ├── gpu_core.cpp ├── gpu_core.hpp ├── gpu_draw.cpp ├── gpu_draw_gouraud.cpp ├── gpu_draw_texture.cpp ├── gpu_gp0.cpp └── gpu_gp1.cpp ├── input ├── input.cpp └── input.hpp ├── memory ├── vram.cpp └── vram.hpp ├── psxact.cpp ├── renderer.cpp ├── renderer.hpp ├── spu ├── spu_core.cpp └── spu_core.hpp ├── timer ├── timer_core.cpp └── timer_core.hpp └── utility.hpp /.gitattributes: -------------------------------------------------------------------------------- 1 | # Automatically normalize line endings 2 | * text=auto 3 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | bin/ 2 | cmake-build-*/ 3 | .idea/ 4 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.0) 2 | project(psxact) 3 | 4 | find_package(SDL2 REQUIRED) 5 | 6 | set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11") 7 | 8 | set(SOURCE_FILES 9 | src/cdrom/cdrom_core.cpp 10 | src/cdrom/cdrom_core.hpp 11 | src/cpu/cpu_code.cpp 12 | src/cpu/cpu_core.cpp 13 | src/cpu/cpu_core.hpp 14 | src/cpu/decoder.cpp 15 | src/cpu/disassembler.cpp 16 | src/dma/dma_core.cpp 17 | src/dma/dma_core.hpp 18 | src/gpu/gpu_gp0.cpp 19 | src/gpu/gpu_gp1.cpp 20 | src/gpu/gpu_core.cpp 21 | src/gpu/gpu_core.hpp 22 | src/gpu/gpu_draw.cpp 23 | src/gpu/gpu_draw_gouraud.cpp 24 | src/gpu/gpu_draw_texture.cpp 25 | src/input/input.cpp 26 | src/input/input.hpp 27 | src/memory/vram.cpp 28 | src/memory/vram.hpp 29 | src/spu/spu_core.cpp 30 | src/spu/spu_core.hpp 31 | src/timer/timer_core.cpp 32 | src/timer/timer_core.hpp 33 | src/bus.cpp 34 | src/bus.hpp 35 | src/psxact.cpp 36 | src/renderer.cpp 37 | src/renderer.hpp 38 | src/utility.hpp) 39 | 40 | add_executable(psxact ${SOURCE_FILES}) 41 | 42 | target_link_libraries(psxact ${SDL2_LIBRARY}) 43 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | {one line to give the program's name and a brief idea of what it does.} 635 | Copyright (C) {year} {name of author} 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | {project} Copyright (C) {year} {fullname} 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # PSXACT 2 | 3 | This project aims to emulate the PlayStation™ 1 console in an accurate 4 | fashion. No hacks or proprietary software will be used to accomplish this goal. 5 | 6 | This emulator is designed to work "out of the box", no plug-in hell required! 7 | 8 | ## Current Status 9 | 10 | Currently, the emulator can get through the BIOS, but hasn't booted any 11 | commercial games yet. A software rasterizer is used to attempt pixel accurate 12 | graphical output, the results are quite nice! 13 | 14 | ![Current status](images/current.png) 15 | 16 | ## Usage 17 | 18 | The emulator requires a BIOS file, which can be dumped from a physical console. 19 | 20 | Once you have a BIOS file, PSXACT can be invoked via command line, using the 21 | following simple interface: 22 | 23 | ``` 24 | $ psxact 25 | ``` 26 | 27 | ## Building 28 | 29 | This project uses CMake for builds, and requires SDL2. 30 | 31 | I personally use the `FindSDL2.cmake` script available 32 | [here](https://github.com/tcbrindle/sdl2-cmake-scripts). 33 | 34 | ## Contributing 35 | 36 | If you'd like to contribute, please create a fork and issue pull requests! I am 37 | very open to newcomers, and will need all the help I can get to make the best 38 | PS1 emulator available. 39 | 40 | However, do try and follow the syntax used by the project when contributing, I 41 | **will** rewrite any code to make it match the project style before accepting. 42 | -------------------------------------------------------------------------------- /images/current.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whaison/psxact/4405d7a06915e7bfaabdce32d86cec416196ba1b/images/current.png -------------------------------------------------------------------------------- /src/bus.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include "bus.hpp" 5 | #include "cdrom/cdrom_core.hpp" 6 | #include "cpu/cpu_core.hpp" 7 | #include "dma/dma_core.hpp" 8 | #include "gpu/gpu_core.hpp" 9 | #include "input/input.hpp" 10 | #include "spu/spu_core.hpp" 11 | #include "timer/timer_core.hpp" 12 | #include "utility.hpp" 13 | 14 | utility::memory_t<19> bios; 15 | utility::memory_t<21> wram; 16 | utility::memory_t<10> dmem; 17 | 18 | void bus::initialize(const std::string &bios_file_name, const std::string &game_file_name) { 19 | memset(bios.b, 0, size_t(bios.size)); 20 | memset(wram.b, 0, size_t(wram.size)); 21 | memset(dmem.b, 0, size_t(dmem.size)); 22 | 23 | utility::read_all_bytes(bios_file_name.c_str(), bios); 24 | } 25 | 26 | void bus::irq(int interrupt) { 27 | cpu::state.i_stat |= (1 << interrupt); 28 | } 29 | 30 | uint32_t bus::read(int width, uint32_t address) { 31 | if (utility::between<0x00000000, 0x007fffff>(address)) { 32 | switch (width) { 33 | case BYTE: return utility::read_byte(wram, address); 34 | case HALF: return utility::read_half(wram, address); 35 | case WORD: return utility::read_word(wram, address); 36 | } 37 | } 38 | 39 | if (utility::between<0x1fc00000, 0x1fc7ffff>(address)) { 40 | switch (width) { 41 | case BYTE: return utility::read_byte(bios, address); 42 | case HALF: return utility::read_half(bios, address); 43 | case WORD: return utility::read_word(bios, address); 44 | } 45 | } 46 | 47 | if (utility::between<0x1f800000, 0x1f8003ff>(address)) { 48 | switch (width) { 49 | case BYTE: return utility::read_byte(dmem, address); 50 | case HALF: return utility::read_half(dmem, address); 51 | case WORD: return utility::read_word(dmem, address); 52 | } 53 | } 54 | 55 | if (utility::between<0x1f801040, 0x1f80104f>(address)) { 56 | return input::bus_read(width, address); 57 | } 58 | 59 | if (utility::between<0x1f801070, 0x1f801077>(address)) { 60 | return cpu::bus_read(width, address); 61 | } 62 | 63 | if (utility::between<0x1f801080, 0x1f8010ff>(address)) { 64 | return dma::bus_read(width, address); 65 | } 66 | 67 | if (utility::between<0x1f801100, 0x1f80110f>(address) || 68 | utility::between<0x1f801110, 0x1f80111f>(address) || 69 | utility::between<0x1f801120, 0x1f80112f>(address)) { 70 | return timer::bus_read(width, address); 71 | } 72 | 73 | if (utility::between<0x1f801800, 0x1f801803>(address)) { 74 | return cdrom::bus_read(width, address); 75 | } 76 | 77 | if (utility::between<0x1f801810, 0x1f801817>(address)) { 78 | return gpu::bus_read(width, address); 79 | } 80 | 81 | if (utility::between<0x1f801c00, 0x1f801fff>(address)) { 82 | return spu::bus_read(width, address); 83 | } 84 | 85 | if (utility::between<0x1f000000, 0x1f7fffff>(address) || // expansion region 1 86 | utility::between<0x1f802000, 0x1f802fff>(address) || // expansion region 2 87 | utility::between<0x1fa00000, 0x1fbfffff>(address)) { // expansion region 3 88 | return 0; 89 | } 90 | 91 | if (address == 0xfffe0130) { 92 | return 0; 93 | } 94 | 95 | printf("bus::read(%d, 0x%08x)\n", width, address); 96 | throw std::exception(); 97 | } 98 | 99 | void bus::write(int width, uint32_t address, uint32_t data) { 100 | if (utility::between<0x00000000, 0x007fffff>(address)) { 101 | switch (width) { 102 | case BYTE: return utility::write_byte(wram, address, data); 103 | case HALF: return utility::write_half(wram, address, data); 104 | case WORD: return utility::write_word(wram, address, data); 105 | } 106 | } 107 | 108 | if (utility::between<0x1fc00000, 0x1fc7ffff>(address)) { 109 | printf("bios write: $%08x <- $%08x\n", address, data); 110 | return; 111 | } 112 | 113 | if (utility::between<0x1f800000, 0x1f8003ff>(address)) { 114 | switch (width) { 115 | case BYTE: return utility::write_byte(dmem, address, data); 116 | case HALF: return utility::write_half(dmem, address, data); 117 | case WORD: return utility::write_word(dmem, address, data); 118 | } 119 | } 120 | 121 | if (utility::between<0x1f801040, 0x1f80104f>(address)) { 122 | return input::bus_write(width, address, data); 123 | } 124 | 125 | if (utility::between<0x1f801070, 0x1f801077>(address)) { 126 | return cpu::bus_write(width, address, data); 127 | } 128 | 129 | if (utility::between<0x1f801080, 0x1f8010ff>(address)) { 130 | return dma::bus_write(width, address, data); 131 | } 132 | 133 | if (utility::between<0x1f801100, 0x1f80110f>(address) || 134 | utility::between<0x1f801110, 0x1f80111f>(address) || 135 | utility::between<0x1f801120, 0x1f80112f>(address)) { 136 | return timer::bus_write(width, address, data); 137 | } 138 | 139 | if (utility::between<0x1f801800, 0x1f801803>(address)) { 140 | return cdrom::bus_write(width, address, data); 141 | } 142 | 143 | if (utility::between<0x1f801810, 0x1f801817>(address)) { 144 | return gpu::bus_write(width, address, data); 145 | } 146 | 147 | if (utility::between<0x1f801c00, 0x1f801fff>(address)) { 148 | return spu::bus_write(width, address, data); 149 | } 150 | 151 | if (utility::between<0x1f000000, 0x1f7fffff>(address) || // expansion region 1 bus_write 152 | utility::between<0x1f802000, 0x1f802fff>(address) || // expansion region 2 bus_write 153 | utility::between<0x1fa00000, 0x1fbfffff>(address)) { // expansion region 3 bus_write 154 | return; 155 | } 156 | 157 | switch (address) { 158 | case 0x1f801000: assert(data == 0x1f000000); return; 159 | case 0x1f801004: assert(data == 0x1f802000); return; 160 | case 0x1f801008: assert(data == 0x0013243f); return; 161 | case 0x1f80100c: assert(data == 0x00003022); return; 162 | case 0x1f801010: assert(data == 0x0013243f); return; 163 | case 0x1f801014: assert(data == 0x200931e1); return; 164 | case 0x1f801018: assert(data == 0x00020843); return; 165 | case 0x1f80101c: assert(data == 0x00070777); return; 166 | case 0x1f801020: assert(data == 0x00031125); return; 167 | 168 | case 0x1f801060: assert(data == 0x00000b88); return; 169 | } 170 | 171 | if (address == 0xfffe0130) { 172 | return; 173 | } 174 | 175 | printf("bus::write(%d, 0x%08x, 0x%08x)\n", width, address, data); 176 | throw std::exception(); 177 | } 178 | -------------------------------------------------------------------------------- /src/bus.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_BUS_HPP 2 | #define PSXACT_BUS_HPP 3 | 4 | #include 5 | #include 6 | 7 | enum bus_width_t { 8 | BYTE, 9 | HALF, 10 | WORD 11 | }; 12 | 13 | namespace bus { 14 | void initialize(const std::string &bios_file_name, const std::string &game_file_name); 15 | 16 | void irq(int interrupt); 17 | 18 | uint32_t read(int width, uint32_t address); 19 | 20 | void write(int width, uint32_t address, uint32_t data); 21 | } 22 | 23 | #endif //PSXACT_BUS_HPP 24 | -------------------------------------------------------------------------------- /src/cdrom/cdrom_core.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include "cdrom_core.hpp" 3 | #include "../bus.hpp" 4 | 5 | cdrom::state_t cdrom::state; 6 | 7 | static uint8_t get_arg() { 8 | auto parameter = cdrom::state.args_fifo.front(); 9 | cdrom::state.args_fifo.pop_front(); 10 | 11 | return parameter; 12 | } 13 | 14 | static void set_arg(uint8_t data) { 15 | cdrom::state.args_fifo.push_back(data); 16 | } 17 | 18 | static uint8_t get_resp() { 19 | auto response = cdrom::state.resp_fifo.front(); 20 | cdrom::state.resp_fifo.pop_front(); 21 | 22 | return response; 23 | } 24 | 25 | static void set_resp(uint8_t data) { 26 | cdrom::state.resp_fifo.push_back(data); 27 | } 28 | 29 | static uint8_t get_data() { 30 | auto data = cdrom::state.data_fifo.front(); 31 | cdrom::state.data_fifo.pop_front(); 32 | 33 | return data; 34 | } 35 | 36 | static void set_data(uint8_t data) { 37 | cdrom::state.data_fifo.push_back(data); 38 | } 39 | 40 | uint32_t cdrom::bus_read(int width, uint32_t address) { 41 | assert(width == BYTE); 42 | 43 | switch (address - 0x1f801800) { 44 | case 0: { // status register 45 | uint32_t result = state.index; 46 | 47 | if (state.args_fifo.size() == 0) { result |= 1 << 3; } 48 | if (state.args_fifo.size() != 16) { result |= 1 << 4; } 49 | if (state.resp_fifo.size() != 0) { result |= 1 << 5; } 50 | if (state.data_fifo.size() != 0) { result |= 1 << 6; } 51 | 52 | return result; 53 | } 54 | 55 | case 1: return get_resp(); 56 | case 2: return get_data(); 57 | case 3: 58 | switch (state.index & 1) { 59 | default: return state.interrupt_enable; // interrupt enable register 60 | case 1: return state.interrupt_request; // interrupt flag register 61 | } 62 | } 63 | 64 | return 0; 65 | } 66 | 67 | void cdrom::bus_write(int width, uint32_t address, uint32_t data) { 68 | assert(width == BYTE); 69 | 70 | switch (address - 0x1f801800) { 71 | case 0: 72 | state.index = data & 3; 73 | return; 74 | 75 | case 1: 76 | switch (state.index) { 77 | case 0: // command register 78 | state.command = uint8_t(data); 79 | state.has_command = true; 80 | break; 81 | 82 | case 1: break; // sound map data out 83 | case 2: break; // sound map coding info 84 | case 3: break; // audio volume for cd-right to spu-right 85 | } 86 | break; 87 | 88 | case 2: 89 | switch (state.index) { 90 | case 0: // parameter fifo 91 | set_arg(uint8_t(data)); 92 | break; 93 | 94 | case 1: // interrupt enable register 95 | state.interrupt_enable = data; 96 | break; 97 | 98 | case 2: break; // audio volume for cd-right to spu-left 99 | case 3: break; // audio volume for cd-right to spu-left 100 | } 101 | break; 102 | 103 | case 3: 104 | switch (state.index) { 105 | case 0: break; // request register 106 | 107 | case 1: // interrupt flag register 108 | state.interrupt_request &= ~data; 109 | break; 110 | 111 | case 2: break; // audio volume for cd-left to spu-right 112 | case 3: break; // apply volume changes 113 | } 114 | break; 115 | } 116 | } 117 | 118 | static void (*second_response)() = nullptr; 119 | 120 | static void command_get_stat() { 121 | set_resp(0x02); 122 | 123 | cdrom::state.interrupt_request = 3; 124 | bus::irq(2); 125 | } 126 | 127 | static void command_test() { 128 | switch (get_arg()) { 129 | case 0x20: 130 | set_resp(0x99); 131 | set_resp(0x02); 132 | set_resp(0x01); 133 | set_resp(0xc3); 134 | 135 | cdrom::state.interrupt_request = 3; 136 | bus::irq(2); 137 | break; 138 | } 139 | } 140 | 141 | static void command_get_id_no_disk() { 142 | set_resp(0x08); 143 | set_resp(0x40); 144 | 145 | set_resp(0x00); 146 | set_resp(0x00); 147 | 148 | set_resp(0x00); 149 | set_resp(0x00); 150 | set_resp(0x00); 151 | set_resp(0x00); 152 | 153 | cdrom::state.interrupt_request = 5; 154 | bus::irq(2); 155 | } 156 | 157 | static void command_get_id() { 158 | set_resp(0x02); 159 | 160 | cdrom::state.interrupt_request = 3; 161 | bus::irq(2); 162 | 163 | second_response = &command_get_id_no_disk; 164 | } 165 | 166 | void cdrom::run() { 167 | if (second_response) { 168 | second_response(); 169 | second_response = nullptr; 170 | } 171 | 172 | if (state.has_command) { 173 | state.has_command = false; 174 | 175 | switch (state.command) { 176 | case 0x01: 177 | return command_get_stat(); 178 | 179 | case 0x19: 180 | return command_test(); 181 | 182 | case 0x1a: 183 | return command_get_id(); 184 | 185 | default: 186 | printf("cd-rom command: $%02x\n", state.command); 187 | break; 188 | } 189 | } 190 | } 191 | -------------------------------------------------------------------------------- /src/cdrom/cdrom_core.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_CDROM_CORE_HPP 2 | #define PSXACT_CDROM_CORE_HPP 3 | 4 | #include 5 | #include 6 | 7 | namespace cdrom { 8 | struct state_t { 9 | uint32_t interrupt_enable; 10 | uint32_t interrupt_request; 11 | uint32_t index; 12 | uint32_t command; 13 | bool has_command; 14 | 15 | std::deque args_fifo; 16 | std::deque resp_fifo; 17 | std::deque data_fifo; 18 | }; 19 | 20 | extern state_t state; 21 | 22 | uint32_t bus_read(int width, uint32_t address); 23 | 24 | void bus_write(int width, uint32_t address, uint32_t data); 25 | 26 | void run(); 27 | } 28 | 29 | #endif //PSXACT_CDROM_CORE_HPP 30 | -------------------------------------------------------------------------------- /src/cpu/cpu_code.cpp: -------------------------------------------------------------------------------- 1 | #include "cpu_core.hpp" 2 | #include "../bus.hpp" 3 | #include "../utility.hpp" 4 | 5 | // --========-- 6 | // Decoding 7 | // --========-- 8 | 9 | static inline uint32_t overflow(uint32_t x, uint32_t y, uint32_t z) { 10 | return (~(x ^ y) & (x ^ z) & 0x80000000); 11 | } 12 | 13 | template 14 | static inline uint32_t get_register(uint32_t index) { 15 | if (!forwarded && cpu::state.is_load_delay_slot && cpu::state.load_index == index) { 16 | return cpu::state.load_value; 17 | } else { 18 | return cpu::state.regs.gp[index]; 19 | } 20 | } 21 | 22 | static inline void set_rd(uint32_t value) { 23 | cpu::state.regs.gp[cpu::decoder::rd()] = value; 24 | cpu::state.regs.gp[0] = 0; 25 | } 26 | 27 | template 28 | static inline void set_rt(uint32_t value) { 29 | auto t = cpu::decoder::rt(); 30 | 31 | if (load) { 32 | if (cpu::state.is_load_delay_slot && cpu::state.load_index == t) { 33 | cpu::state.regs.gp[t] = cpu::state.load_value; 34 | } 35 | 36 | cpu::state.is_load = true; 37 | cpu::state.load_index = t; 38 | cpu::state.load_value = cpu::state.regs.gp[t]; 39 | } 40 | 41 | cpu::state.regs.gp[t] = value; 42 | cpu::state.regs.gp[0] = 0; 43 | } 44 | 45 | template 46 | static inline uint32_t rt() { 47 | return get_register(cpu::decoder::rt()); 48 | } 49 | 50 | static inline uint32_t rs() { 51 | return get_register(cpu::decoder::rs()); 52 | } 53 | 54 | // --============-- 55 | // Instructions 56 | // --============-- 57 | 58 | void cpu::op_add() { 59 | auto x = rs(); 60 | auto y = rt(); 61 | auto z = x + y; 62 | 63 | if (overflow(x, y, z)) { 64 | enter_exception(0xc); 65 | } else { 66 | set_rd(z); 67 | } 68 | } 69 | 70 | void cpu::op_addi() { 71 | auto x = rs(); 72 | auto y = decoder::iconst(); 73 | auto z = x + y; 74 | 75 | if (overflow(x, y, z)) { 76 | enter_exception(0xc); 77 | } else { 78 | set_rt(z); 79 | } 80 | } 81 | 82 | void cpu::op_addiu() { 83 | set_rt(rs() + decoder::iconst()); 84 | } 85 | 86 | void cpu::op_addu() { 87 | set_rd(rs() + rt()); 88 | } 89 | 90 | void cpu::op_and() { 91 | set_rd(rs() & rt()); 92 | } 93 | 94 | void cpu::op_andi() { 95 | set_rt(rs() & decoder::uconst()); 96 | } 97 | 98 | void cpu::op_beq() { 99 | if (rs() == rt()) { 100 | state.regs.next_pc = state.regs.pc + (decoder::iconst() << 2); 101 | state.is_branch = true; 102 | } 103 | } 104 | 105 | void cpu::op_bgtz() { 106 | if (int32_t(rs()) > 0) { 107 | state.regs.next_pc = state.regs.pc + (decoder::iconst() << 2); 108 | state.is_branch = true; 109 | } 110 | } 111 | 112 | void cpu::op_blez() { 113 | if (int32_t(rs()) <= 0) { 114 | state.regs.next_pc = state.regs.pc + (decoder::iconst() << 2); 115 | state.is_branch = true; 116 | } 117 | } 118 | 119 | void cpu::op_bne() { 120 | if (rs() != rt()) { 121 | state.regs.next_pc = state.regs.pc + (decoder::iconst() << 2); 122 | state.is_branch = true; 123 | } 124 | } 125 | 126 | void cpu::op_break() { 127 | enter_exception(0x09); 128 | } 129 | 130 | void cpu::op_bxx() { 131 | // bgez rs,$nnnn 132 | // bgezal rs,$nnnn 133 | // bltz rs,$nnnn 134 | // bltzal rs,$nnnn 135 | bool condition = (state.code & (1 << 16)) 136 | ? int32_t(rs()) >= 0 137 | : int32_t(rs()) < 0; 138 | 139 | if ((state.code & 0x1e0000) == 0x100000) { 140 | state.regs.gp[31] = state.regs.next_pc; 141 | } 142 | 143 | if (condition) { 144 | state.regs.next_pc = state.regs.pc + (decoder::iconst() << 2); 145 | state.is_branch = true; 146 | } 147 | } 148 | 149 | void cpu::op_cop0() { 150 | switch ((cpu::state.code >> 21) & 31) { 151 | default: op_und(); return; 152 | 153 | case 0x00: set_rt(state.cop0.regs[decoder::rd()]); return; // mfc0 rt,rd 154 | case 0x04: state.cop0.regs[decoder::rd()] = rt(); return; // mtc0 rt,rd 155 | 156 | case 0x10: 157 | switch (cpu::state.code & 63) { 158 | default: op_und(); return; 159 | 160 | case 0x10: leave_exception(); return; // rfe 161 | } 162 | } 163 | } 164 | 165 | void cpu::op_cop1() { 166 | enter_exception(0xb); 167 | } 168 | 169 | void cpu::op_cop2() { 170 | if (state.code & (1 << 25)) { 171 | printf("cop2 $%08x\n", state.code); 172 | } else { 173 | switch (decoder::rs()) { 174 | case 0: /*printf("mfc2 r%02d, r%02d\n", decoder::rt(), decoder::rd());*/ break; 175 | case 2: /*printf("cfc2 r%02d, r%02d\n", decoder::rt(), decoder::rd());*/ break; 176 | case 4: /*printf("mtc2 r%02d, r%02d\n", decoder::rt(), decoder::rd());*/ break; 177 | case 6: /*printf("ctc2 r%02d, r%02d\n", decoder::rt(), decoder::rd());*/ break; 178 | 179 | default: 180 | printf("unimplemented cop2\n"); 181 | throw "unimplemented cop2\n"; 182 | } 183 | } 184 | } 185 | 186 | void cpu::op_cop3() { 187 | enter_exception(0xb); 188 | } 189 | 190 | void cpu::op_div() { 191 | auto dividend = int32_t(rs()); 192 | auto divisor = int32_t(rt()); 193 | 194 | if (dividend == 0x80000000 && divisor == 0xffffffff) { 195 | state.regs.lo = 0x80000000; 196 | state.regs.hi = 0; 197 | } else if (dividend >= 0 && divisor == 0) { 198 | state.regs.lo = uint32_t(0xffffffff); 199 | state.regs.hi = uint32_t(dividend); 200 | } else if (dividend <= 0 && divisor == 0) { 201 | state.regs.lo = uint32_t(0x00000001); 202 | state.regs.hi = uint32_t(dividend); 203 | } else { 204 | state.regs.lo = uint32_t(dividend / divisor); 205 | state.regs.hi = uint32_t(dividend % divisor); 206 | } 207 | } 208 | 209 | void cpu::op_divu() { 210 | auto dividend = rs(); 211 | auto divisor = rt(); 212 | 213 | if (divisor) { 214 | state.regs.lo = dividend / divisor; 215 | state.regs.hi = dividend % divisor; 216 | } else { 217 | state.regs.lo = 0xffffffff; 218 | state.regs.hi = dividend; 219 | } 220 | } 221 | 222 | void cpu::op_j() { 223 | state.regs.next_pc = (state.regs.pc & 0xf0000000) | ((state.code << 2) & 0x0ffffffc); 224 | state.is_branch = true; 225 | } 226 | 227 | void cpu::op_jal() { 228 | state.regs.gp[31] = state.regs.next_pc; 229 | state.regs.next_pc = (state.regs.pc & 0xf0000000) | ((state.code << 2) & 0x0ffffffc); 230 | state.is_branch = true; 231 | } 232 | 233 | void cpu::op_jalr() { 234 | auto ra = state.regs.next_pc; 235 | 236 | state.regs.next_pc = rs(); 237 | set_rd(ra); 238 | 239 | state.is_branch = true; 240 | } 241 | 242 | void cpu::op_jr() { 243 | state.regs.next_pc = rs(); 244 | state.is_branch = true; 245 | } 246 | 247 | void cpu::op_lb() { 248 | auto address = rs() + decoder::iconst(); 249 | auto data = read_data(BYTE, address); 250 | data = utility::sclip<8>(data); 251 | 252 | set_rt<1>(data); 253 | } 254 | 255 | void cpu::op_lbu() { 256 | auto address = rs() + decoder::iconst(); 257 | auto data = read_data(BYTE, address); 258 | 259 | set_rt<1>(data); 260 | } 261 | 262 | void cpu::op_lh() { 263 | auto address = rs() + decoder::iconst(); 264 | if (address & 1) { 265 | enter_exception(0x4); 266 | } else { 267 | auto data = read_data(HALF, address); 268 | data = utility::sclip<16>(data); 269 | 270 | set_rt<1>(data); 271 | } 272 | } 273 | 274 | void cpu::op_lhu() { 275 | auto address = rs() + decoder::iconst(); 276 | if (address & 1) { 277 | enter_exception(0x4); 278 | } else { 279 | auto data = read_data(HALF, address); 280 | 281 | set_rt<1>(data); 282 | } 283 | } 284 | 285 | void cpu::op_lui() { 286 | set_rt(decoder::uconst() << 16); 287 | } 288 | 289 | void cpu::op_lw() { 290 | auto address = rs() + decoder::iconst(); 291 | if (address & 3) { 292 | enter_exception(0x4); 293 | } else { 294 | auto data = read_data(WORD, address); 295 | 296 | set_rt<1>(data); 297 | } 298 | } 299 | 300 | void cpu::op_lwc0() { 301 | throw "unimplemented lwc0\n"; 302 | } 303 | 304 | void cpu::op_lwc1() { 305 | throw "unimplemented lwc1\n"; 306 | } 307 | 308 | void cpu::op_lwc2() { 309 | throw "unimplemented lwc2\n"; 310 | } 311 | 312 | void cpu::op_lwc3() { 313 | throw "unimplemented lwc3\n"; 314 | } 315 | 316 | void cpu::op_lwl() { 317 | auto address = rs() + decoder::iconst(); 318 | auto data = read_data(WORD, address & ~3); 319 | 320 | switch (address & 3) { 321 | default: data = (data << 24) | (rt<1>() & 0x00ffffff); break; 322 | case 1: data = (data << 16) | (rt<1>() & 0x0000ffff); break; 323 | case 2: data = (data << 8) | (rt<1>() & 0x000000ff); break; 324 | case 3: data = (data << 0) | (rt<1>() & 0x00000000); break; 325 | } 326 | 327 | set_rt<1>(data); 328 | } 329 | 330 | void cpu::op_lwr() { 331 | auto address = rs() + decoder::iconst(); 332 | auto data = read_data(WORD, address & ~3); 333 | 334 | switch (address & 3) { 335 | default: data = (data >> 0) | (rt<1>() & 0x00000000); break; 336 | case 1: data = (data >> 8) | (rt<1>() & 0xff000000); break; 337 | case 2: data = (data >> 16) | (rt<1>() & 0xffff0000); break; 338 | case 3: data = (data >> 24) | (rt<1>() & 0xffffff00); break; 339 | } 340 | 341 | set_rt<1>(data); 342 | } 343 | 344 | void cpu::op_mfhi() { 345 | set_rd(state.regs.hi); 346 | } 347 | 348 | void cpu::op_mflo() { 349 | set_rd(state.regs.lo); 350 | } 351 | 352 | void cpu::op_mthi() { 353 | state.regs.hi = rs(); 354 | } 355 | 356 | void cpu::op_mtlo() { 357 | state.regs.lo = rs(); 358 | } 359 | 360 | void cpu::op_mult() { 361 | auto s = int32_t(rs()); 362 | auto t = int32_t(rt()); 363 | 364 | int64_t result = int64_t(s) * int64_t(t); 365 | state.regs.lo = uint32_t(result >> 0); 366 | state.regs.hi = uint32_t(result >> 32); 367 | } 368 | 369 | void cpu::op_multu() { 370 | auto s = rs(); 371 | auto t = rt(); 372 | 373 | uint64_t result = uint64_t(s) * uint64_t(t); 374 | state.regs.lo = uint32_t(result >> 0); 375 | state.regs.hi = uint32_t(result >> 32); 376 | } 377 | 378 | void cpu::op_nor() { 379 | set_rd(~(rs() | rt())); 380 | } 381 | 382 | void cpu::op_or() { 383 | set_rd(rs() | rt()); 384 | } 385 | 386 | void cpu::op_ori() { 387 | set_rt(rs() | decoder::uconst()); 388 | } 389 | 390 | void cpu::op_sb() { 391 | auto address = rs() + decoder::iconst(); 392 | auto data = rt(); 393 | 394 | write_data(BYTE, address, data); 395 | } 396 | 397 | void cpu::op_sh() { 398 | auto address = rs() + decoder::iconst(); 399 | if (address & 1) { 400 | enter_exception(0x5); 401 | } else { 402 | auto data = rt(); 403 | 404 | write_data(HALF, address, data); 405 | } 406 | } 407 | 408 | void cpu::op_sll() { 409 | set_rd(rt() << decoder::sa()); 410 | } 411 | 412 | void cpu::op_sllv() { 413 | set_rd(rt() << rs()); 414 | } 415 | 416 | void cpu::op_slt() { 417 | set_rd(int32_t(rs()) < int32_t(rt()) ? 1 : 0); 418 | } 419 | 420 | void cpu::op_slti() { 421 | set_rt(int32_t(rs()) < int32_t(decoder::iconst()) ? 1 : 0); 422 | } 423 | 424 | void cpu::op_sltiu() { 425 | set_rt(rs() < decoder::iconst() ? 1 : 0); 426 | } 427 | 428 | void cpu::op_sltu() { 429 | set_rd(rs() < rt() ? 1 : 0); 430 | } 431 | 432 | void cpu::op_sra() { 433 | set_rd(int32_t(rt()) >> decoder::sa()); 434 | } 435 | 436 | void cpu::op_srav() { 437 | set_rd(int32_t(rt()) >> rs()); 438 | } 439 | 440 | void cpu::op_srl() { 441 | set_rd(rt() >> decoder::sa()); 442 | } 443 | 444 | void cpu::op_srlv() { 445 | set_rd(rt() >> rs()); 446 | } 447 | 448 | void cpu::op_sub() { 449 | auto x = rs(); 450 | auto y = rt(); 451 | auto z = x - y; 452 | 453 | if (overflow(x, ~y, z)) { 454 | enter_exception(0xc); 455 | } else { 456 | set_rd(z); 457 | } 458 | } 459 | 460 | void cpu::op_subu() { 461 | set_rd(rs() - rt()); 462 | } 463 | 464 | void cpu::op_sw() { 465 | auto address = rs() + decoder::iconst(); 466 | if (address & 3) { 467 | enter_exception(0x5); 468 | } else { 469 | auto data = rt(); 470 | 471 | write_data(WORD, address, data); 472 | } 473 | } 474 | 475 | void cpu::op_swc0() { 476 | throw "unimplemented swc0\n"; 477 | } 478 | 479 | void cpu::op_swc1() { 480 | throw "unimplemented swc1\n"; 481 | } 482 | 483 | void cpu::op_swc2() { 484 | throw "unimplemented swc2\n"; 485 | } 486 | 487 | void cpu::op_swc3() { 488 | throw "unimplemented swc3\n"; 489 | } 490 | 491 | void cpu::op_swl() { 492 | auto address = rs() + decoder::iconst(); 493 | auto data = read_data(WORD, address & ~3); 494 | 495 | switch (address & 3) { 496 | default: data = (data & 0xffffff00) | (rt() >> 24); break; 497 | case 1: data = (data & 0xffff0000) | (rt() >> 16); break; 498 | case 2: data = (data & 0xff000000) | (rt() >> 8); break; 499 | case 3: data = (data & 0x00000000) | (rt() >> 0); break; 500 | } 501 | 502 | write_data(WORD, address & ~3, data); 503 | } 504 | 505 | void cpu::op_swr() { 506 | auto address = rs() + decoder::iconst(); 507 | auto data = read_data(WORD, address & ~3); 508 | 509 | switch (address & 3) { 510 | default: data = (data & 0x00000000) | (rt() << 0); break; 511 | case 1: data = (data & 0x000000ff) | (rt() << 8); break; 512 | case 2: data = (data & 0x0000ffff) | (rt() << 16); break; 513 | case 3: data = (data & 0x00ffffff) | (rt() << 24); break; 514 | } 515 | 516 | write_data(WORD, address & ~3, data); 517 | } 518 | 519 | void cpu::op_syscall() { 520 | enter_exception(0x08); 521 | } 522 | 523 | void cpu::op_xor() { 524 | set_rd(rs() ^ rt()); 525 | } 526 | 527 | void cpu::op_xori() { 528 | set_rt(rs() ^ decoder::uconst()); 529 | } 530 | 531 | void cpu::op_und() { 532 | cpu::enter_exception(0xa); 533 | } 534 | -------------------------------------------------------------------------------- /src/cpu/cpu_core.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include "cpu_core.hpp" 3 | #include "../bus.hpp" 4 | 5 | cpu::state_t cpu::state; 6 | 7 | cpu::opcode cpu::op_table[64] = { 8 | nullptr, op_bxx, op_j, op_jal, op_beq, op_bne, op_blez, op_bgtz, 9 | op_addi, op_addiu, op_slti, op_sltiu, op_andi, op_ori, op_xori, op_lui, 10 | op_cop0, op_cop1, op_cop2, op_cop3, op_und, op_und, op_und, op_und, 11 | op_und, op_und, op_und, op_und, op_und, op_und, op_und, op_und, 12 | op_lb, op_lh, op_lwl, op_lw, op_lbu, op_lhu, op_lwr, op_und, 13 | op_sb, op_sh, op_swl, op_sw, op_und, op_und, op_swr, op_und, 14 | op_lwc0, op_lwc1, op_lwc2, op_lwc3, op_und, op_und, op_und, op_und, 15 | op_swc0, op_swc1, op_swc2, op_swc3, op_und, op_und, op_und, op_und 16 | }; 17 | 18 | cpu::opcode cpu::op_table_special[64] = { 19 | op_sll, op_und, op_srl, op_sra, op_sllv, op_und, op_srlv, op_srav, 20 | op_jr, op_jalr, op_und, op_und, op_syscall, op_break, op_und, op_und, 21 | op_mfhi, op_mthi, op_mflo, op_mtlo, op_und, op_und, op_und, op_und, 22 | op_mult, op_multu, op_div, op_divu, op_und, op_und, op_und, op_und, 23 | op_add, op_addu, op_sub, op_subu, op_and, op_or, op_xor, op_nor, 24 | op_und, op_und, op_slt, op_sltu, op_und, op_und, op_und, op_und, 25 | op_und, op_und, op_und, op_und, op_und, op_und, op_und, op_und, 26 | op_und, op_und, op_und, op_und, op_und, op_und, op_und, op_und 27 | }; 28 | 29 | void cpu::initialize() { 30 | state.regs.gp[0] = 0; 31 | state.regs.pc = 0xbfc00000; 32 | state.regs.next_pc = state.regs.pc + 4; 33 | } 34 | 35 | void cpu::tick() { 36 | cpu::read_code(); 37 | 38 | state.is_branch_delay_slot = state.is_branch; 39 | state.is_branch = false; 40 | 41 | state.is_load_delay_slot = state.is_load; 42 | state.is_load = false; 43 | 44 | if (state.i_stat & state.i_mask) { 45 | state.cop0.regs[13] |= (1 << 10); 46 | } else { 47 | state.cop0.regs[13] &= ~(1 << 10); 48 | } 49 | 50 | auto iec = (state.cop0.regs[12] & 1) != 0; 51 | auto irq = (state.cop0.regs[12] & state.cop0.regs[13] & 0xff00) != 0; 52 | 53 | if (iec && irq) { 54 | enter_exception(0x0); 55 | } else { 56 | auto code = (cpu::state.code >> 26) & 63; 57 | if (code) 58 | op_table[code](); 59 | else 60 | op_table_special[(cpu::state.code >> 0) & 63](); 61 | } 62 | } 63 | 64 | void cpu::enter_exception(uint32_t code) { 65 | uint32_t status = state.cop0.regs[12]; 66 | status = (status & ~0x3f) | ((status << 2) & 0x3f); 67 | 68 | uint32_t cause = state.cop0.regs[13]; 69 | cause = (cause & ~0x7f) | ((code << 2) & 0x7f); 70 | 71 | uint32_t epc; 72 | 73 | if (state.is_branch_delay_slot) { 74 | epc = state.regs.this_pc - 4; 75 | cause |= 0x80000000; 76 | } else { 77 | epc = state.regs.this_pc; 78 | cause &= ~0x80000000; 79 | } 80 | 81 | state.cop0.regs[12] = status; 82 | state.cop0.regs[13] = cause; 83 | state.cop0.regs[14] = epc; 84 | 85 | state.regs.pc = (status & (1 << 22)) 86 | ? 0xbfc00180 87 | : 0x80000080; 88 | 89 | state.regs.next_pc = state.regs.pc + 4; 90 | } 91 | 92 | void cpu::leave_exception() { 93 | uint32_t sr = state.cop0.regs[12]; 94 | sr = (sr & ~0xf) | ((sr >> 2) & 0xf); 95 | 96 | state.cop0.regs[12] = sr; 97 | } 98 | 99 | static uint32_t segments[8] = { 100 | 0x7fffffff, // kuseg ($0000_0000 - $7fff_ffff) 101 | 0x7fffffff, // 102 | 0x7fffffff, // 103 | 0x7fffffff, // 104 | 0x1fffffff, // kseg0 ($8000_0000 - $9fff_ffff) 105 | 0x1fffffff, // kseg1 ($a000_0000 - $bfff_ffff) 106 | 0xffffffff, // kseg2 ($c000_0000 - $ffff_ffff) 107 | 0xffffffff // 108 | }; 109 | 110 | static inline uint32_t map_address(uint32_t address) { 111 | return address & segments[address >> 29]; 112 | } 113 | 114 | void cpu::read_code() { 115 | if (state.regs.pc & 3) { 116 | enter_exception(0x4); 117 | } 118 | 119 | state.regs.this_pc = state.regs.pc; 120 | state.regs.pc = state.regs.next_pc; 121 | state.regs.next_pc += 4; 122 | 123 | // todo: read i-cache 124 | 125 | state.code = bus::read(WORD, map_address(state.regs.this_pc)); 126 | } 127 | 128 | uint32_t cpu::read_data(int width, uint32_t address) { 129 | if (state.cop0.regs[12] & (1 << 16)) { 130 | return 0; // isc=1 131 | } 132 | 133 | // todo: read d-cache? 134 | 135 | return bus::read(width, map_address(address)); 136 | } 137 | 138 | void cpu::write_data(int width, uint32_t address, uint32_t data) { 139 | if (state.cop0.regs[12] & (1 << 16)) { 140 | return; // isc=1 141 | } 142 | 143 | // todo: write d-cache? 144 | 145 | return bus::write(width, map_address(address), data); 146 | } 147 | 148 | uint32_t cpu::bus_read(int width, uint32_t address) { 149 | printf("cpu::bus_read(%d, 0x%08x)\n", width, address); 150 | 151 | switch (address) { 152 | case 0x1f801070: 153 | return state.i_stat; 154 | 155 | case 0x1f801074: 156 | return state.i_mask; 157 | } 158 | } 159 | 160 | void cpu::bus_write(int width, uint32_t address, uint32_t data) { 161 | printf("cpu::bus_write(%d, 0x%08x, 0x%08x)\n", width, address, data); 162 | 163 | switch (address) { 164 | case 0x1f801070: 165 | state.i_stat = state.i_stat & data; 166 | break; 167 | 168 | case 0x1f801074: 169 | state.i_mask = data & 0x7ff; 170 | break; 171 | } 172 | } 173 | -------------------------------------------------------------------------------- /src/cpu/cpu_core.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_CPU_CORE_HPP 2 | #define PSXACT_CPU_CORE_HPP 3 | 4 | #include 5 | 6 | namespace cpu { 7 | typedef void (*opcode)(); 8 | 9 | extern opcode op_table[64]; 10 | extern opcode op_table_special[64]; 11 | 12 | struct state_t { 13 | struct { 14 | uint32_t regs[16]; 15 | } cop0; 16 | 17 | struct { 18 | uint32_t gp[32]; 19 | uint32_t lo; 20 | uint32_t hi; 21 | uint32_t pc; 22 | uint32_t this_pc; 23 | uint32_t next_pc; 24 | } regs; 25 | 26 | uint32_t code; 27 | 28 | bool is_branch; 29 | bool is_branch_delay_slot; 30 | 31 | bool is_load; 32 | bool is_load_delay_slot; 33 | uint32_t load_index; 34 | uint32_t load_value; 35 | 36 | uint32_t i_stat; 37 | uint32_t i_mask; 38 | }; 39 | 40 | extern state_t state; 41 | 42 | void initialize(); 43 | 44 | void disassemble(); 45 | 46 | void tick(); 47 | 48 | void enter_exception(uint32_t code); 49 | 50 | void leave_exception(); 51 | 52 | void read_code(); 53 | 54 | uint32_t read_data(int width, uint32_t address); 55 | 56 | void write_data(int width, uint32_t address, uint32_t data); 57 | 58 | uint32_t bus_read(int width, uint32_t address); 59 | 60 | void bus_write(int width, uint32_t address, uint32_t data); 61 | 62 | // --============-- 63 | // Instructions 64 | // --============-- 65 | 66 | void op_add(); 67 | void op_addi(); 68 | void op_addiu(); 69 | void op_addu(); 70 | void op_and(); 71 | void op_andi(); 72 | void op_beq(); 73 | void op_bgtz(); 74 | void op_blez(); 75 | void op_bne(); 76 | void op_break(); 77 | void op_bxx(); 78 | void op_cop0(); 79 | void op_cop1(); 80 | void op_cop2(); 81 | void op_cop3(); 82 | void op_div(); 83 | void op_divu(); 84 | void op_j(); 85 | void op_jal(); 86 | void op_jalr(); 87 | void op_jr(); 88 | void op_lb(); 89 | void op_lbu(); 90 | void op_lh(); 91 | void op_lhu(); 92 | void op_lui(); 93 | void op_lw(); 94 | void op_lwc0(); 95 | void op_lwc1(); 96 | void op_lwc2(); 97 | void op_lwc3(); 98 | void op_lwl(); 99 | void op_lwr(); 100 | void op_mfhi(); 101 | void op_mflo(); 102 | void op_mthi(); 103 | void op_mtlo(); 104 | void op_mult(); 105 | void op_multu(); 106 | void op_nor(); 107 | void op_or(); 108 | void op_ori(); 109 | void op_sb(); 110 | void op_sh(); 111 | void op_sll(); 112 | void op_sllv(); 113 | void op_slt(); 114 | void op_slti(); 115 | void op_sltiu(); 116 | void op_sltu(); 117 | void op_sra(); 118 | void op_srav(); 119 | void op_srl(); 120 | void op_srlv(); 121 | void op_sub(); 122 | void op_subu(); 123 | void op_sw(); 124 | void op_swc0(); 125 | void op_swc1(); 126 | void op_swc2(); 127 | void op_swc3(); 128 | void op_swl(); 129 | void op_swr(); 130 | void op_syscall(); 131 | void op_xor(); 132 | void op_xori(); 133 | 134 | // undefined instruction 135 | void op_und(); 136 | 137 | namespace decoder { 138 | uint32_t iconst(); 139 | uint32_t uconst(); 140 | uint32_t sa(); 141 | uint32_t rd(); 142 | uint32_t rt(); 143 | uint32_t rs(); 144 | } 145 | } 146 | 147 | #endif //PSXACT_CPU_CORE_HPP 148 | -------------------------------------------------------------------------------- /src/cpu/decoder.cpp: -------------------------------------------------------------------------------- 1 | #include "cpu_core.hpp" 2 | #include "../utility.hpp" 3 | 4 | uint32_t cpu::decoder::iconst() { 5 | return utility::sclip<16>(cpu::state.code); 6 | } 7 | 8 | uint32_t cpu::decoder::uconst() { 9 | return utility::uclip<16>(cpu::state.code); 10 | } 11 | 12 | uint32_t cpu::decoder::sa() { 13 | return (cpu::state.code >> 6) & 31; 14 | } 15 | 16 | uint32_t cpu::decoder::rd() { 17 | return (cpu::state.code >> 11) & 31; 18 | } 19 | 20 | uint32_t cpu::decoder::rt() { 21 | return (cpu::state.code >> 16) & 31; 22 | } 23 | 24 | uint32_t cpu::decoder::rs() { 25 | return (cpu::state.code >> 21) & 31; 26 | } 27 | -------------------------------------------------------------------------------- /src/cpu/disassembler.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include "cpu_core.hpp" 3 | 4 | void disassemble_special() { 5 | switch (cpu::state.code & 0x3f) { 6 | case 0x00: printf("sll r%02d, r%02d, #%d\n", cpu::decoder::rd(), cpu::decoder::rt(), cpu::decoder::sa()); break; 7 | 8 | case 0x02: printf("srl r%02d, r%02d, #%d\n", cpu::decoder::rd(), cpu::decoder::rt(), cpu::decoder::sa()); break; 9 | case 0x03: printf("sra r%02d, r%02d, #%d\n", cpu::decoder::rd(), cpu::decoder::rt(), cpu::decoder::sa()); break; 10 | case 0x04: printf("sllv r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rt(), cpu::decoder::rs()); break; 11 | 12 | case 0x06: printf("srlv r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rt(), cpu::decoder::rs()); break; 13 | case 0x07: printf("srav r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rt(), cpu::decoder::rs()); break; 14 | case 0x08: printf("jr r%02d\n", cpu::decoder::rs()); break; 15 | case 0x09: printf("jalr r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs()); break; 16 | 17 | case 0x0c: printf("syscall\n"); break; 18 | case 0x0d: printf("break\n"); break; 19 | 20 | case 0x10: printf("mfhi r%02d\n", cpu::decoder::rs()); break; 21 | case 0x11: printf("mthi r%02d\n", cpu::decoder::rs()); break; 22 | case 0x12: printf("mflo r%02d\n", cpu::decoder::rs()); break; 23 | case 0x13: printf("mtlo r%02d\n", cpu::decoder::rs()); break; 24 | 25 | case 0x18: printf("mult r%02d, r%02d\n", cpu::decoder::rs(), cpu::decoder::rt()); break; 26 | case 0x19: printf("multu r%02d, r%02d\n", cpu::decoder::rs(), cpu::decoder::rt()); break; 27 | case 0x1a: printf("div r%02d, r%02d\n", cpu::decoder::rs(), cpu::decoder::rt()); break; 28 | case 0x1b: printf("divu r%02d, r%02d\n", cpu::decoder::rs(), cpu::decoder::rt()); break; 29 | 30 | case 0x20: printf("add r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 31 | case 0x21: printf("addu r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 32 | case 0x22: printf("sub r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 33 | case 0x23: printf("subu r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 34 | case 0x24: printf("and r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 35 | case 0x25: printf("or r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 36 | case 0x26: printf("xor r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 37 | case 0x27: printf("nor r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 38 | 39 | case 0x2a: printf("slt r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 40 | case 0x2b: printf("sltu r%02d, r%02d, r%02d\n", cpu::decoder::rd(), cpu::decoder::rs(), cpu::decoder::rt()); break; 41 | 42 | default: 43 | printf("unknown (0x%08x)\n", cpu::state.code); 44 | break; 45 | } 46 | } 47 | 48 | void disassemble_reg_imm() { 49 | auto pc = cpu::state.regs.this_pc; 50 | 51 | switch (cpu::decoder::rt()) { 52 | case 0x00: printf("bltz r%02d, #0x%08x\n", cpu::decoder::rs(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 53 | case 0x01: printf("bgez r%02d, #0x%08x\n", cpu::decoder::rs(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 54 | 55 | case 0x10: printf("bltzal r%02d, #0x%08x\n", cpu::decoder::rs(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 56 | case 0x11: printf("bgezal r%02d, #0x%08x\n", cpu::decoder::rs(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 57 | 58 | default: 59 | printf("unknown (0x%08x)\n", cpu::state.code); 60 | break; 61 | } 62 | } 63 | 64 | void cpu::disassemble() { 65 | auto pc = state.regs.this_pc; 66 | 67 | printf("0x%08x | ", pc); 68 | 69 | switch ((cpu::state.code >> 26) & 0x3f) { 70 | case 0x00: return disassemble_special(); 71 | case 0x01: return disassemble_reg_imm(); 72 | 73 | case 0x02: printf("j 0x%08x\n", (pc & ~0x0fffffff) | ((cpu::state.code << 2) & 0x0fffffff)); break; 74 | case 0x03: printf("jal 0x%08x\n", (pc & ~0x0fffffff) | ((cpu::state.code << 2) & 0x0fffffff)); break; 75 | 76 | case 0x04: printf("beq r%02d, r%02d, #0x%08x\n", cpu::decoder::rs(), cpu::decoder::rt(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 77 | case 0x05: printf("bne r%02d, r%02d, #0x%08x\n", cpu::decoder::rs(), cpu::decoder::rt(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 78 | case 0x06: printf("blez r%02d, #0x%08x\n", cpu::decoder::rs(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 79 | case 0x07: printf("bgtz r%02d, #0x%08x\n", cpu::decoder::rs(), pc + 4 + (cpu::decoder::iconst() << 2)); break; 80 | 81 | case 0x08: printf("addi r%02d, r%02d, #0x%08x\n", cpu::decoder::rt(), cpu::decoder::rs(), cpu::decoder::iconst()); break; 82 | case 0x09: printf("addiu r%02d, r%02d, #0x%08x\n", cpu::decoder::rt(), cpu::decoder::rs(), cpu::decoder::iconst()); break; 83 | case 0x0a: printf("slti r%02d, r%02d, #0x%08x\n", cpu::decoder::rt(), cpu::decoder::rs(), cpu::decoder::iconst()); break; 84 | case 0x0b: printf("sltiu r%02d, r%02d, #0x%08x\n", cpu::decoder::rt(), cpu::decoder::rs(), cpu::decoder::iconst()); break; 85 | case 0x0c: printf("andi r%02d, r%02d, #0x%04x\n", cpu::decoder::rt(), cpu::decoder::rs(), cpu::decoder::uconst()); break; 86 | case 0x0d: printf("ori r%02d, r%02d, #0x%04x\n", cpu::decoder::rt(), cpu::decoder::rs(), cpu::decoder::uconst()); break; 87 | case 0x0e: printf("xori r%02d, r%02d, #0x%04x\n", cpu::decoder::rt(), cpu::decoder::rs(), cpu::decoder::uconst()); break; 88 | case 0x0f: printf("lui r%02d, #0x%04x\n", cpu::decoder::rt(), cpu::decoder::uconst()); break; 89 | 90 | case 0x10: 91 | case 0x11: 92 | case 0x12: 93 | case 0x13: { 94 | auto co = (cpu::state.code >> 26) & 3; 95 | 96 | switch (cpu::decoder::rs()) { 97 | case 0x00: printf("mfc%d r%02d, r%02d\n", co, cpu::decoder::rt(), cpu::decoder::rd()); break; 98 | case 0x04: printf("mtc%d r%02d, r%02d\n", co, cpu::decoder::rt(), cpu::decoder::rd()); break; 99 | 100 | case 0x10: 101 | switch ((cpu::state.code >> 0) & 0x3f) { 102 | case 0x10: printf("rfe\n"); break; 103 | 104 | default: 105 | printf("unknown (0x%08x)\n", cpu::state.code); 106 | break; 107 | } 108 | break; 109 | 110 | default: 111 | printf("unknown (0x%08x)\n", cpu::state.code); 112 | break; 113 | } 114 | 115 | break; 116 | } 117 | 118 | case 0x20: printf("lb r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 119 | case 0x21: printf("lh r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 120 | case 0x22: printf("lwl r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 121 | case 0x23: printf("lw r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 122 | case 0x24: printf("lbu r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 123 | case 0x25: printf("lhu r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 124 | case 0x26: printf("lwr r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 125 | 126 | case 0x28: printf("sb r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 127 | case 0x29: printf("sh r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 128 | case 0x2a: printf("swl r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 129 | case 0x2b: printf("sw r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 130 | 131 | case 0x2e: printf("swr r%02d, #%08x(r%02d)\n", cpu::decoder::rt(), cpu::decoder::iconst(), cpu::decoder::rs()); break; 132 | 133 | default: 134 | printf("unknown (0x%08x)\n", cpu::state.code); 135 | break; 136 | } 137 | } 138 | -------------------------------------------------------------------------------- /src/dma/dma_core.cpp: -------------------------------------------------------------------------------- 1 | #include "dma_core.hpp" 2 | #include "../bus.hpp" 3 | #include "../gpu/gpu_core.hpp" 4 | 5 | static dma::state_t state; 6 | 7 | static void update_irq_active_flag() { 8 | auto forced = ((state.dicr >> 15) & 1) != 0; 9 | auto master = ((state.dicr >> 23) & 1) != 0; 10 | auto signal = ((state.dicr >> 16) & (state.dicr >> 24) & 0x7f) != 0; 11 | auto active = forced || (master && signal); 12 | 13 | if (active) { 14 | if (!(state.dicr & 0x80000000)) { 15 | bus::irq(3); 16 | } 17 | 18 | state.dicr |= 0x80000000; 19 | } else { 20 | state.dicr &= ~0x80000000; 21 | } 22 | } 23 | 24 | static uint32_t get_channel_index(uint32_t address) { 25 | return (address >> 4) & 7; 26 | } 27 | 28 | static uint32_t get_register_index(uint32_t address) { 29 | return (address >> 2) & 3; 30 | } 31 | 32 | uint32_t dma::bus_read(int width, uint32_t address) { 33 | auto channel = get_channel_index(address); 34 | if (channel == 7) { 35 | switch (get_register_index(address)) { 36 | case 0: return state.dpcr; 37 | case 1: return state.dicr; 38 | case 2: return 0x7ffac68b; 39 | case 3: return 0x00fffff7; 40 | } 41 | } 42 | else { 43 | switch (get_register_index(address)) { 44 | case 0: return state.channels[channel].address; 45 | case 1: return state.channels[channel].counter; 46 | case 2: return state.channels[channel].control; 47 | } 48 | } 49 | 50 | return 0; 51 | } 52 | 53 | void dma::bus_write(int width, uint32_t address, uint32_t data) { 54 | auto channel = get_channel_index(address); 55 | if (channel == 7) { 56 | switch (get_register_index(address)) { 57 | case 0: state.dpcr = data; break; 58 | 59 | case 1: 60 | state.dicr &= ( 0xff000000); 61 | state.dicr |= (data & 0x00ff803f); 62 | state.dicr &= ~(data & 0x7f000000); 63 | update_irq_active_flag(); 64 | break; 65 | 66 | case 2: break; 67 | case 3: break; 68 | } 69 | } 70 | else { 71 | switch (get_register_index(address)) { 72 | case 0: state.channels[channel].address = data & 0x00ffffff; break; 73 | case 1: state.channels[channel].counter = data & 0xffffffff; break; 74 | case 2: state.channels[channel].control = data & 0x71770703; break; 75 | } 76 | } 77 | 78 | dma::main(); 79 | } 80 | 81 | void dma::main() { 82 | if (state.dpcr & 0x08000000) { run_channel(6); } 83 | if (state.dpcr & 0x00800000) { run_channel(5); } 84 | if (state.dpcr & 0x00080000) { run_channel(4); } 85 | if (state.dpcr & 0x00008000) { run_channel(3); } 86 | if (state.dpcr & 0x00000800) { run_channel(2); } 87 | if (state.dpcr & 0x00000080) { run_channel(1); } 88 | if (state.dpcr & 0x00000008) { run_channel(0); } 89 | } 90 | 91 | static void run_channel_2_data_read() { 92 | auto address = state.channels[2].address; 93 | auto bs = (state.channels[2].counter >> 0) & 0xffff; 94 | auto ba = (state.channels[2].counter >> 16) & 0xffff; 95 | 96 | bs = bs ? bs : 0x10000; 97 | ba = ba ? ba : 0x10000; 98 | 99 | for (int a = 0; a < ba; a++) { 100 | for (int s = 0; s < bs; s++) { 101 | bus::write(WORD, address, gpu::data()); 102 | address += 4; 103 | } 104 | } 105 | 106 | state.channels[2].control &= ~0x01000000; 107 | 108 | dma::irq_channel(2); 109 | } 110 | 111 | static void run_channel_2_data_write() { 112 | auto address = state.channels[2].address; 113 | auto bs = (state.channels[2].counter >> 0) & 0xffff; 114 | auto ba = (state.channels[2].counter >> 16) & 0xffff; 115 | 116 | bs = bs ? bs : 0x10000; 117 | ba = ba ? ba : 0x10000; 118 | 119 | for (int a = 0; a < ba; a++) { 120 | for (int s = 0; s < bs; s++) { 121 | gpu::gp0(bus::read(WORD, address)); 122 | address += 4; 123 | } 124 | } 125 | 126 | state.channels[2].control &= ~0x01000000; 127 | 128 | dma::irq_channel(2); 129 | } 130 | 131 | static void run_channel_2_list() { 132 | auto address = state.channels[2].address; 133 | 134 | while (address != 0xffffff) { 135 | auto value = bus::read(WORD, address); 136 | address += 4; 137 | 138 | auto count = value >> 24; 139 | 140 | for (auto index = 0; index < count; index++) { 141 | gpu::gp0(bus::read(WORD, address)); 142 | address += 4; 143 | } 144 | 145 | address = value & 0xffffff; 146 | } 147 | 148 | state.channels[2].control &= ~0x01000000; 149 | 150 | dma::irq_channel(2); 151 | } 152 | 153 | static void run_channel_6() { 154 | auto address = state.channels[6].address; 155 | auto counter = state.channels[6].counter & 0xffff; 156 | 157 | counter = counter ? counter : 0x10000; 158 | 159 | for (int i = 1; i < counter; i++) { 160 | bus::write(WORD, address, address - 4); 161 | address -= 4; 162 | } 163 | 164 | bus::write(WORD, address, 0x00ffffff); 165 | 166 | state.channels[6].control &= ~0x11000000; 167 | 168 | dma::irq_channel(6); 169 | } 170 | 171 | void dma::run_channel(int n) { 172 | if (n == 2) { 173 | if (state.channels[2].control == 0x01000200) { return run_channel_2_data_read(); } 174 | if (state.channels[2].control == 0x01000201) { return run_channel_2_data_write(); } 175 | if (state.channels[2].control == 0x01000401) { return run_channel_2_list(); } 176 | } 177 | 178 | if (n == 6 && state.channels[6].control == 0x11000002) { return run_channel_6(); } 179 | } 180 | 181 | void dma::irq_channel(int n) { 182 | int flag = 1 << (n + 24); 183 | int mask = 1 << (n + 16); 184 | 185 | if (state.dicr & mask) { 186 | state.dicr |= flag; 187 | } 188 | 189 | update_irq_active_flag(); 190 | } 191 | -------------------------------------------------------------------------------- /src/dma/dma_core.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_DMA_CORE_HPP 2 | #define PSXACT_DMA_CORE_HPP 3 | 4 | #include 5 | 6 | namespace dma { 7 | struct state_t { 8 | uint32_t dpcr = 0x07654321; 9 | uint32_t dicr = 0x00000000; 10 | 11 | struct { 12 | uint32_t address; 13 | uint32_t counter; 14 | uint32_t control; 15 | } channels[7]; 16 | }; 17 | 18 | uint32_t bus_read(int width, uint32_t address); 19 | 20 | void bus_write(int width, uint32_t address, uint32_t data); 21 | 22 | void main(); 23 | 24 | void irq_channel(int n); 25 | 26 | void run_channel(int n); 27 | } 28 | 29 | #endif //PSXACT_DMA_CORE_HPP 30 | -------------------------------------------------------------------------------- /src/gpu/gpu_core.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include "gpu_core.hpp" 3 | #include "../bus.hpp" 4 | #include "../memory/vram.hpp" 5 | 6 | gpu::state_t gpu::state; 7 | 8 | uint32_t gpu::data() { 9 | if (gpu::state.gpu_to_cpu_transfer.run.active) { 10 | auto lower = vram_transfer(); 11 | auto upper = vram_transfer(); 12 | 13 | return (upper << 16) | lower; 14 | } 15 | 16 | return 0; 17 | } 18 | 19 | uint32_t gpu::stat() { 20 | // 19 Vertical Resolution (0=240, 1=480, when Bit22=1) ;GP1(08h).2 21 | // 26 Ready to receive Cmd Word (0=No, 1=Ready) ;GP0(...) ;via GP0 22 | // 27 Ready to send VRAM to CPU (0=No, 1=Ready) ;GP0(C0h) ;via GPUREAD 23 | // 28 Ready to receive DMA Block (0=No, 1=Ready) ;GP0(...) ;via GP0 24 | 25 | return (gpu::state.status & ~0x00080000) | 0x1c002000; 26 | } 27 | 28 | uint32_t gpu::bus_read(int width, uint32_t address) { 29 | assert(width == WORD); 30 | 31 | switch (address) { 32 | case 0x1f801810: return data(); 33 | case 0x1f801814: return stat(); 34 | } 35 | } 36 | 37 | void gpu::bus_write(int width, uint32_t address, uint32_t data) { 38 | assert(width == WORD); 39 | 40 | switch (address) { 41 | case 0x1f801810: 42 | return gp0(data); 43 | 44 | case 0x1f801814: 45 | return gp1(data); 46 | } 47 | } 48 | 49 | uint16_t gpu::vram_transfer() { 50 | auto &transfer = gpu::state.gpu_to_cpu_transfer; 51 | if (!transfer.run.active) { 52 | return 0; 53 | } 54 | 55 | auto data = vram::read(transfer.reg.x + transfer.run.x, 56 | transfer.reg.y + transfer.run.y); 57 | 58 | transfer.run.x++; 59 | 60 | if (transfer.run.x == transfer.reg.w) { 61 | transfer.run.x = 0; 62 | transfer.run.y++; 63 | 64 | if (transfer.run.y == transfer.reg.h) { 65 | transfer.run.y = 0; 66 | transfer.run.active = false; 67 | } 68 | } 69 | 70 | return data; 71 | } 72 | 73 | void gpu::vram_transfer(uint16_t data) { 74 | auto &transfer = gpu::state.cpu_to_gpu_transfer; 75 | if (!transfer.run.active) { 76 | return; 77 | } 78 | 79 | vram::write(transfer.reg.x + transfer.run.x, 80 | transfer.reg.y + transfer.run.y, uint16_t(data)); 81 | 82 | transfer.run.x++; 83 | 84 | if (transfer.run.x == transfer.reg.w) { 85 | transfer.run.x = 0; 86 | transfer.run.y++; 87 | 88 | if (transfer.run.y == transfer.reg.h) { 89 | transfer.run.y = 0; 90 | transfer.run.active = false; 91 | } 92 | } 93 | } 94 | -------------------------------------------------------------------------------- /src/gpu/gpu_core.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_GPU_CORE_HPP 2 | #define PSXACT_GPU_CORE_HPP 3 | 4 | #include 5 | #include 6 | #include "../utility.hpp" 7 | 8 | namespace gpu { 9 | struct state_t { 10 | uint32_t status = 0x14802000; 11 | uint32_t texture_window_mask_x; 12 | uint32_t texture_window_mask_y; 13 | uint32_t texture_window_offset_x; 14 | uint32_t texture_window_offset_y; 15 | uint32_t drawing_area_x1; 16 | uint32_t drawing_area_y1; 17 | uint32_t drawing_area_x2; 18 | uint32_t drawing_area_y2; 19 | uint32_t x_offset; 20 | uint32_t y_offset; 21 | uint32_t display_area_x; 22 | uint32_t display_area_y; 23 | uint32_t display_area_x1; 24 | uint32_t display_area_y1; 25 | uint32_t display_area_x2; 26 | uint32_t display_area_y2; 27 | bool textured_rectangle_x_flip; 28 | bool textured_rectangle_y_flip; 29 | 30 | struct { 31 | uint32_t buffer[16]; 32 | int wr; 33 | int rd; 34 | } fifo; 35 | 36 | struct { 37 | struct { 38 | int x; 39 | int y; 40 | int w; 41 | int h; 42 | } reg; 43 | 44 | struct { 45 | bool active; 46 | int x; 47 | int y; 48 | } run; 49 | } cpu_to_gpu_transfer; 50 | 51 | struct { 52 | struct { 53 | int x; 54 | int y; 55 | int w; 56 | int h; 57 | } reg; 58 | 59 | struct { 60 | bool active; 61 | int x; 62 | int y; 63 | } run; 64 | } gpu_to_cpu_transfer; 65 | }; 66 | 67 | extern state_t state; 68 | 69 | uint32_t bus_read(int width, uint32_t address); 70 | 71 | void bus_write(int width, uint32_t address, uint32_t data); 72 | 73 | uint32_t data(); 74 | 75 | uint32_t stat(); 76 | 77 | void gp0(uint32_t data); 78 | 79 | void gp1(uint32_t data); 80 | 81 | void vram_transfer(uint16_t data); 82 | 83 | uint16_t vram_transfer(); 84 | 85 | struct color_t { 86 | int r; 87 | int g; 88 | int b; 89 | }; 90 | 91 | struct point_t { 92 | int x; 93 | int y; 94 | }; 95 | 96 | void draw_point(int x, int y, int r, int g, int b); 97 | 98 | namespace gouraud { 99 | struct pixel_t { 100 | point_t point; 101 | color_t color; 102 | }; 103 | 104 | template 105 | struct polygon_t { 106 | pixel_t v[size]; 107 | }; 108 | 109 | void draw_poly3(const gpu::gouraud::polygon_t<3> &p); 110 | 111 | void draw_poly4(const gpu::gouraud::polygon_t<4> &p); 112 | } 113 | 114 | namespace texture { 115 | struct pixel_t { 116 | point_t point; 117 | color_t color; 118 | int u; 119 | int v; 120 | }; 121 | 122 | template 123 | struct polygon_t { 124 | pixel_t v[size]; 125 | int clut_x; 126 | int clut_y; 127 | int base_u; 128 | int base_v; 129 | int depth; 130 | }; 131 | 132 | void draw_poly3(const polygon_t<3> &p); 133 | 134 | void draw_poly4(const polygon_t<4> &p); 135 | } 136 | } 137 | 138 | #endif //PSXACT_GPU_CORE_HPP 139 | -------------------------------------------------------------------------------- /src/gpu/gpu_draw.cpp: -------------------------------------------------------------------------------- 1 | #include "gpu_core.hpp" 2 | #include "../memory/vram.hpp" 3 | 4 | template 5 | int clip(int value) { 6 | if (value <= min) return min; 7 | if (value >= max) return max; 8 | return value; 9 | }; 10 | 11 | static int dither_lut[4][4] = { 12 | { -4, 0, -3, 1 }, 13 | { 2, -2, 3, -1 }, 14 | { -3, 1, -4, 0 }, 15 | { 3, -1, 2, -2 } 16 | }; 17 | 18 | void gpu::draw_point(int x, int y, int r, int g, int b) { 19 | if (x < state.drawing_area_x1 || x > state.drawing_area_x2) return; 20 | if (y < state.drawing_area_y1 || y > state.drawing_area_y2) return; 21 | 22 | auto dither = dither_lut[y & 3][x & 3]; 23 | 24 | r = clip<0, 255>(r + dither); 25 | g = clip<0, 255>(g + dither); 26 | b = clip<0, 255>(b + dither); 27 | 28 | auto color = 29 | (((r >> 3) & 0x1f) << 0) | 30 | (((g >> 3) & 0x1f) << 5) | 31 | (((b >> 3) & 0x1f) << 10); 32 | 33 | vram::write(x, y, uint16_t(color)); 34 | } 35 | -------------------------------------------------------------------------------- /src/gpu/gpu_draw_gouraud.cpp: -------------------------------------------------------------------------------- 1 | #include "gpu_core.hpp" 2 | 3 | void fill_gouraud(const gpu::gouraud::pixel_t &v0, const int &w0, 4 | const gpu::gouraud::pixel_t &v1, const int &w1, 5 | const gpu::gouraud::pixel_t &v2, const int &w2, int x, int y) { 6 | int area = w0 + w1 + w2; 7 | 8 | int r = ((v0.color.r * w0) + (v1.color.r * w1) + (v2.color.r * w2)) / area; 9 | int g = ((v0.color.g * w0) + (v1.color.g * w1) + (v2.color.g * w2)) / area; 10 | int b = ((v0.color.b * w0) + (v1.color.b * w1) + (v2.color.b * w2)) / area; 11 | 12 | gpu::draw_point(x, y, r, g, b); 13 | } 14 | 15 | static int min3(int a, int b, int c) { 16 | if (a <= b && a <= c) return a; 17 | if (b <= a && b <= c) return b; 18 | return c; 19 | } 20 | 21 | static int max3(int a, int b, int c) { 22 | if (a >= b && a >= c) return a; 23 | if (b >= a && b >= c) return b; 24 | return c; 25 | } 26 | 27 | static int edge(const gpu::point_t& a, const gpu::point_t& b, const gpu::point_t& c) { 28 | return ((b.x - a.x) * (c.y - a.y)) - ((b.y - a.y) * (c.x - a.x)); 29 | } 30 | 31 | static bool is_top_left(const gpu::point_t &a, const gpu::point_t &b) { 32 | return (b.y == a.y && b.x > a.x) || b.y < a.y; 33 | } 34 | 35 | static void fill_poly3_gouraud(const gpu::gouraud::pixel_t &v0, const gpu::gouraud::pixel_t &v1, const gpu::gouraud::pixel_t &v2) { 36 | int min_x = min3(v0.point.x, v1.point.x, v2.point.x); 37 | int min_y = min3(v0.point.y, v1.point.y, v2.point.y); 38 | int max_x = max3(v0.point.x, v1.point.x, v2.point.x); 39 | int max_y = max3(v0.point.y, v1.point.y, v2.point.y); 40 | 41 | bool is_top_left_12 = is_top_left(v1.point, v2.point); 42 | bool is_top_left_20 = is_top_left(v2.point, v0.point); 43 | bool is_top_left_01 = is_top_left(v0.point, v1.point); 44 | 45 | int x01 = v0.point.y - v1.point.y, y01 = v1.point.x - v0.point.x; 46 | int x12 = v1.point.y - v2.point.y, y12 = v2.point.x - v1.point.x; 47 | int x20 = v2.point.y - v0.point.y, y20 = v0.point.x - v2.point.x; 48 | 49 | gpu::point_t p = { min_x, min_y }; 50 | 51 | int w0_row = edge(v1.point, v2.point, p); 52 | int w1_row = edge(v2.point, v0.point, p); 53 | int w2_row = edge(v0.point, v1.point, p); 54 | 55 | for (p.y = min_y; p.y <= max_y; p.y++) { 56 | int w0 = w0_row; 57 | w0_row += y12; 58 | 59 | int w1 = w1_row; 60 | w1_row += y20; 61 | 62 | int w2 = w2_row; 63 | w2_row += y01; 64 | 65 | for (p.x = min_x; p.x <= max_x; p.x++) { 66 | bool draw = 67 | (w0 > 0 || (w0 == 0 && is_top_left_12)) && 68 | (w1 > 0 || (w1 == 0 && is_top_left_20)) && 69 | (w2 > 0 || (w2 == 0 && is_top_left_01)); 70 | 71 | if (draw) { 72 | fill_gouraud(v0, w0, v1, w1, v2, w2, p.x, p.y); 73 | } 74 | 75 | w0 += x12; 76 | w1 += x20; 77 | w2 += x01; 78 | } 79 | } 80 | } 81 | 82 | static inline int double_area(const gpu::point_t &v0, const gpu::point_t &v1, const gpu::point_t &v2) { 83 | auto e0 = (v1.x - v0.x) * (v1.y + v0.y); 84 | auto e1 = (v2.x - v1.x) * (v2.y + v1.y); 85 | auto e2 = (v0.x - v2.x) * (v0.y + v2.y); 86 | 87 | return e0 + e1 + e2; 88 | } 89 | 90 | void gpu::gouraud::draw_poly3(const polygon_t<3> &p) { 91 | const auto &p0 = p.v[0]; 92 | const auto &p1 = p.v[1]; 93 | const auto &p2 = p.v[2]; 94 | 95 | if (double_area(p0.point, p1.point, p2.point) < 0) { 96 | fill_poly3_gouraud(p0, p1, p2); 97 | } else { 98 | fill_poly3_gouraud(p0, p2, p1); 99 | } 100 | } 101 | 102 | void gpu::gouraud::draw_poly4(const polygon_t<4> &p) { 103 | auto &v0 = p.v[0]; 104 | auto &v1 = p.v[1]; 105 | auto &v2 = p.v[2]; 106 | auto &v3 = p.v[3]; 107 | 108 | draw_poly3({ v0, v1, v2 }); 109 | draw_poly3({ v1, v2, v3 }); 110 | } 111 | -------------------------------------------------------------------------------- /src/gpu/gpu_draw_texture.cpp: -------------------------------------------------------------------------------- 1 | #include "gpu_core.hpp" 2 | #include "../memory/vram.hpp" 3 | 4 | void fill_texture_4bpp(const gpu::texture::polygon_t<3> &p, 5 | const int &w0, 6 | const int &w1, 7 | const int &w2, int x, int y) { 8 | int area = w0 + w1 + w2; 9 | 10 | int u = ((p.v[0].u * w0) + (p.v[1].u * w1) + (p.v[2].u * w2)) / area; 11 | int v = ((p.v[0].v * w0) + (p.v[1].v * w1) + (p.v[2].v * w2)) / area; 12 | 13 | auto texel = vram::read(p.base_u + (u / 4), p.base_v + v); 14 | int index = 0; 15 | 16 | switch (u & 3) { 17 | case 0: index = (texel >> 0) & 0xf; break; 18 | case 1: index = (texel >> 4) & 0xf; break; 19 | case 2: index = (texel >> 8) & 0xf; break; 20 | case 3: index = (texel >> 12) & 0xf; break; 21 | } 22 | 23 | auto color = vram::read(p.clut_x + index, p.clut_y); 24 | if (color == 0) { 25 | return; 26 | } 27 | 28 | vram::write(x, y, color); 29 | } 30 | 31 | void fill_texture_15bpp(const gpu::texture::polygon_t<3> &p, 32 | const int &w0, 33 | const int &w1, 34 | const int &w2, int x, int y) { 35 | int area = w0 + w1 + w2; 36 | 37 | int u = ((p.v[0].u * w0) + (p.v[1].u * w1) + (p.v[2].u * w2)) / area; 38 | int v = ((p.v[0].v * w0) + (p.v[1].v * w1) + (p.v[2].v * w2)) / area; 39 | 40 | auto color = vram::read(p.base_u + u, p.base_v + v); 41 | if (color) { 42 | vram::write(x, y, color); 43 | } 44 | } 45 | 46 | static int min3(int a, int b, int c) { 47 | if (a <= b && a <= c) return a; 48 | if (b <= a && b <= c) return b; 49 | return c; 50 | } 51 | 52 | static int max3(int a, int b, int c) { 53 | if (a >= b && a >= c) return a; 54 | if (b >= a && b >= c) return b; 55 | return c; 56 | } 57 | 58 | static int edge(const gpu::point_t& a, const gpu::point_t& b, const gpu::point_t& c) { 59 | return ((b.x - a.x) * (c.y - a.y)) - ((b.y - a.y) * (c.x - a.x)); 60 | } 61 | 62 | static bool is_top_left(const gpu::point_t &a, const gpu::point_t &b) { 63 | return (b.y == a.y && b.x > a.x) || b.y < a.y; 64 | } 65 | 66 | static void fill_poly3_texture(const gpu::texture::polygon_t<3> &t) { 67 | int min_x = min3(t.v[0].point.x, t.v[1].point.x, t.v[2].point.x); 68 | int min_y = min3(t.v[0].point.y, t.v[1].point.y, t.v[2].point.y); 69 | int max_x = max3(t.v[0].point.x, t.v[1].point.x, t.v[2].point.x); 70 | int max_y = max3(t.v[0].point.y, t.v[1].point.y, t.v[2].point.y); 71 | 72 | bool is_top_left_12 = is_top_left(t.v[1].point, t.v[2].point); 73 | bool is_top_left_20 = is_top_left(t.v[2].point, t.v[0].point); 74 | bool is_top_left_01 = is_top_left(t.v[0].point, t.v[1].point); 75 | 76 | int x01 = t.v[0].point.y - t.v[1].point.y, y01 = t.v[1].point.x - t.v[0].point.x; 77 | int x12 = t.v[1].point.y - t.v[2].point.y, y12 = t.v[2].point.x - t.v[1].point.x; 78 | int x20 = t.v[2].point.y - t.v[0].point.y, y20 = t.v[0].point.x - t.v[2].point.x; 79 | 80 | gpu::point_t p = { min_x, min_y }; 81 | 82 | int w0_row = edge(t.v[1].point, t.v[2].point, p); 83 | int w1_row = edge(t.v[2].point, t.v[0].point, p); 84 | int w2_row = edge(t.v[0].point, t.v[1].point, p); 85 | 86 | for (p.y = min_y; p.y <= max_y; p.y++) { 87 | int w0 = w0_row; 88 | int w1 = w1_row; 89 | int w2 = w2_row; 90 | 91 | for (p.x = min_x; p.x <= max_x; p.x++) { 92 | bool draw = 93 | (w0 > 0 || (w0 == 0 && is_top_left_12)) && 94 | (w1 > 0 || (w1 == 0 && is_top_left_20)) && 95 | (w2 > 0 || (w2 == 0 && is_top_left_01)); 96 | 97 | if (draw) { 98 | switch (t.depth) { 99 | case 0: fill_texture_4bpp (t, w0, w1, w2, p.x, p.y); break; 100 | case 2: fill_texture_15bpp(t, w0, w1, w2, p.x, p.y); break; 101 | case 3: fill_texture_15bpp(t, w0, w1, w2, p.x, p.y); break; 102 | } 103 | } 104 | 105 | w0 += x12; 106 | w1 += x20; 107 | w2 += x01; 108 | } 109 | 110 | w0_row += y12; 111 | w1_row += y20; 112 | w2_row += y01; 113 | } 114 | } 115 | 116 | static inline int double_area(const gpu::point_t &v0, const gpu::point_t &v1, const gpu::point_t &v2) { 117 | auto e0 = (v1.x - v0.x) * (v1.y + v0.y); 118 | auto e1 = (v2.x - v1.x) * (v2.y + v1.y); 119 | auto e2 = (v0.x - v2.x) * (v0.y + v2.y); 120 | 121 | return e0 + e1 + e2; 122 | } 123 | 124 | void gpu::texture::draw_poly3(const gpu::texture::polygon_t<3> &p) { 125 | auto &v0 = p.v[0]; 126 | auto &v1 = p.v[1]; 127 | auto &v2 = p.v[2]; 128 | 129 | if (double_area(v0.point, v1.point, v2.point) < 0) { 130 | fill_poly3_texture({v0, v1, v2, p.clut_x, p.clut_y, p.base_u, p.base_v, p.depth}); 131 | } else { 132 | fill_poly3_texture({v0, v2, v1, p.clut_x, p.clut_y, p.base_u, p.base_v, p.depth}); 133 | } 134 | } 135 | 136 | void gpu::texture::draw_poly4(const gpu::texture::polygon_t<4> &p) { 137 | auto &v0 = p.v[0]; 138 | auto &v1 = p.v[1]; 139 | auto &v2 = p.v[2]; 140 | auto &v3 = p.v[3]; 141 | 142 | gpu::texture::draw_poly3({v0, v1, v2, p.clut_x, p.clut_y, p.base_u, p.base_v, p.depth}); 143 | gpu::texture::draw_poly3({v1, v2, v3, p.clut_x, p.clut_y, p.base_u, p.base_v, p.depth}); 144 | } 145 | -------------------------------------------------------------------------------- /src/gpu/gpu_gp0.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include "gpu_core.hpp" 3 | #include "../memory/vram.hpp" 4 | 5 | static int command_size[256] = { 6 | 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $00 7 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $10 8 | 1, 1, 1, 1, 1, 1, 1, 1, 5, 1, 1, 1, 9, 9, 1, 1, // $20 9 | 6, 1, 1, 1, 1, 1, 1, 1, 8, 1, 1, 1, 1, 1, 1, 1, // $30 10 | 11 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $40 12 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $50 13 | 1, 1, 1, 1, 1, 4, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, // $60 14 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $70 15 | 16 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $80 17 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $90 18 | 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $a0 19 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $b0 20 | 21 | 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $c0 22 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $d0 23 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $e0 24 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // $f0 25 | }; 26 | 27 | static gpu::point_t gp0_to_point(uint32_t point) { 28 | gpu::point_t result; 29 | result.x = utility::sclip<11>(point); 30 | result.y = utility::sclip<11>(point >> 16); 31 | 32 | return result; 33 | } 34 | 35 | static gpu::color_t gp0_to_color(uint32_t color) { 36 | gpu::color_t result; 37 | result.r = (color >> 0) & 0xff; 38 | result.g = (color >> 8) & 0xff; 39 | result.b = (color >> 16) & 0xff; 40 | 41 | return result; 42 | } 43 | 44 | static gpu::gouraud::pixel_t gp0_to_gouraud_pixel(uint32_t point, uint32_t color) { 45 | gpu::gouraud::pixel_t p; 46 | p.point = gp0_to_point(point); 47 | p.color = gp0_to_color(color); 48 | 49 | return p; 50 | } 51 | 52 | static gpu::texture::pixel_t gp0_to_texture_pixel(uint32_t point, uint32_t color, uint32_t coord) { 53 | gpu::texture::pixel_t p; 54 | p.point = gp0_to_point(point); 55 | p.color = gp0_to_color(color); 56 | 57 | p.u = (coord >> 0) & 0xff; 58 | p.v = (coord >> 8) & 0xff; 59 | 60 | return p; 61 | } 62 | 63 | void gpu::gp0(uint32_t data) { 64 | if (state.cpu_to_gpu_transfer.run.active) { 65 | auto lower = uint16_t(data >> 0); 66 | auto upper = uint16_t(data >> 16); 67 | 68 | vram_transfer(lower); 69 | vram_transfer(upper); 70 | return; 71 | } 72 | 73 | state.fifo.buffer[state.fifo.wr] = data; 74 | state.fifo.wr = (state.fifo.wr + 1) & 0xf; 75 | 76 | auto command = state.fifo.buffer[0] >> 24; 77 | 78 | if (state.fifo.wr == command_size[command]) { 79 | state.fifo.wr = 0; 80 | 81 | switch (command) { 82 | case 0x00: break; // nop 83 | case 0x01: break; // clear texture cache 84 | 85 | case 0x02: { // fill rectangle 86 | auto color = gp0_to_color(state.fifo.buffer[0]); 87 | auto point1 = gp0_to_point(state.fifo.buffer[1]); 88 | auto point2 = gp0_to_point(state.fifo.buffer[2]); 89 | 90 | point1.x = (point1.x + 0x0) & ~0xf; 91 | point2.x = (point2.x + 0xf) & ~0xf; 92 | 93 | for (int y = 0; y < point2.y; y++) { 94 | for (int x = 0; x < point2.x; x++) { 95 | gpu::draw_point(point1.x + x, 96 | point1.y + y, 97 | color.r, 98 | color.g, 99 | color.b); 100 | } 101 | } 102 | 103 | break; 104 | } 105 | 106 | case 0x28: { // monochrome quad, opaque 107 | auto color = state.fifo.buffer[0]; 108 | auto point1 = state.fifo.buffer[1]; 109 | auto point2 = state.fifo.buffer[2]; 110 | auto point3 = state.fifo.buffer[3]; 111 | auto point4 = state.fifo.buffer[4]; 112 | 113 | auto v0 = gp0_to_gouraud_pixel(point1, color); 114 | auto v1 = gp0_to_gouraud_pixel(point2, color); 115 | auto v2 = gp0_to_gouraud_pixel(point3, color); 116 | auto v3 = gp0_to_gouraud_pixel(point4, color); 117 | 118 | gpu::gouraud::draw_poly4({v0, v1, v2, v3}); 119 | break; 120 | } 121 | 122 | case 0x2c: 123 | case 0x2d: { // textured quad, opaque 124 | auto color = state.fifo.buffer[0]; 125 | auto point1 = state.fifo.buffer[1]; 126 | auto coord1 = state.fifo.buffer[2]; 127 | auto point2 = state.fifo.buffer[3]; 128 | auto coord2 = state.fifo.buffer[4]; 129 | auto point3 = state.fifo.buffer[5]; 130 | auto coord3 = state.fifo.buffer[6]; 131 | auto point4 = state.fifo.buffer[7]; 132 | auto coord4 = state.fifo.buffer[8]; 133 | 134 | gpu::texture::polygon_t<4> p; 135 | 136 | p.v[0] = gp0_to_texture_pixel(point1, color, coord1); 137 | p.v[1] = gp0_to_texture_pixel(point2, color, coord2); 138 | p.v[2] = gp0_to_texture_pixel(point3, color, coord3); 139 | p.v[3] = gp0_to_texture_pixel(point4, color, coord4); 140 | p.clut_x = ((coord1 >> 16) & 0x03f) * 16; 141 | p.clut_y = ((coord1 >> 22) & 0x1ff) * 1; 142 | p.base_u = ((coord2 >> 16) & 0x00f) * 64; 143 | p.base_v = ((coord2 >> 20) & 0x001) * 256; 144 | p.depth = ((coord2 >> 23) & 0x003); 145 | 146 | gpu::texture::draw_poly4(p); 147 | break; 148 | } 149 | 150 | case 0x30: { // shaded triangle, opaque 151 | auto color1 = state.fifo.buffer[0]; 152 | auto point1 = state.fifo.buffer[1]; 153 | auto color2 = state.fifo.buffer[2]; 154 | auto point2 = state.fifo.buffer[3]; 155 | auto color3 = state.fifo.buffer[4]; 156 | auto point3 = state.fifo.buffer[5]; 157 | 158 | auto v0 = gp0_to_gouraud_pixel(point1, color1); 159 | auto v1 = gp0_to_gouraud_pixel(point2, color2); 160 | auto v2 = gp0_to_gouraud_pixel(point3, color3); 161 | 162 | gpu::gouraud::draw_poly3({v0, v1, v2}); 163 | break; 164 | } 165 | 166 | case 0x38: { // shaded quad, opaque 167 | auto color1 = state.fifo.buffer[0]; 168 | auto point1 = state.fifo.buffer[1]; 169 | auto color2 = state.fifo.buffer[2]; 170 | auto point2 = state.fifo.buffer[3]; 171 | auto color3 = state.fifo.buffer[4]; 172 | auto point3 = state.fifo.buffer[5]; 173 | auto color4 = state.fifo.buffer[6]; 174 | auto point4 = state.fifo.buffer[7]; 175 | 176 | auto v0 = gp0_to_gouraud_pixel(point1, color1); 177 | auto v1 = gp0_to_gouraud_pixel(point2, color2); 178 | auto v2 = gp0_to_gouraud_pixel(point3, color3); 179 | auto v3 = gp0_to_gouraud_pixel(point4, color4); 180 | 181 | gpu::gouraud::draw_poly4({v0, v1, v2, v3}); 182 | break; 183 | } 184 | 185 | case 0x65: { 186 | //auto color = gp0_to_color(state.fifo.buffer[0]); 187 | auto point1 = gp0_to_point(state.fifo.buffer[1]); 188 | auto coord = state.fifo.buffer[2]; 189 | auto point2 = gp0_to_point(state.fifo.buffer[3]); 190 | 191 | assert((state.status & 0x180) == 0); 192 | 193 | auto base_u = ((state.status >> 0) & 0xf) * 64; 194 | auto base_v = ((state.status >> 4) & 0x1) * 256; 195 | 196 | auto clut_x = ((coord >> 16) & 0x03f) * 16; 197 | auto clut_y = ((coord >> 22) & 0x1ff); 198 | 199 | for (int y = 0; y < point2.y; y++) { 200 | for (int x = 0; x < point2.x; x++) { 201 | auto texel = vram::read(base_u + (x / 4), 202 | base_v + y); 203 | 204 | int index = 0; 205 | 206 | switch (x & 3) { 207 | case 0: index = (texel >> 0) & 0xf; break; 208 | case 1: index = (texel >> 4) & 0xf; break; 209 | case 2: index = (texel >> 8) & 0xf; break; 210 | case 3: index = (texel >> 12) & 0xf; break; 211 | } 212 | 213 | auto color = vram::read(clut_x + index, 214 | clut_y); 215 | 216 | vram::write(point1.x + x, 217 | point1.y + y, 218 | color); 219 | } 220 | } 221 | 222 | break; 223 | } 224 | 225 | case 0x68: { 226 | auto color = gp0_to_color(state.fifo.buffer[0]); 227 | auto point = gp0_to_point(state.fifo.buffer[1]); 228 | 229 | gpu::draw_point(point.x, 230 | point.y, 231 | color.r, 232 | color.g, 233 | color.b); 234 | break; 235 | } 236 | 237 | case 0xa0: { 238 | auto &transfer = state.cpu_to_gpu_transfer; 239 | transfer.reg.x = state.fifo.buffer[1] & 0xffff; 240 | transfer.reg.y = state.fifo.buffer[1] >> 16; 241 | transfer.reg.w = state.fifo.buffer[2] & 0xffff; 242 | transfer.reg.h = state.fifo.buffer[2] >> 16; 243 | 244 | transfer.run.x = 0; 245 | transfer.run.y = 0; 246 | transfer.run.active = true; 247 | break; 248 | } 249 | 250 | case 0xc0: { 251 | auto &transfer = state.gpu_to_cpu_transfer; 252 | transfer.reg.x = state.fifo.buffer[1] & 0xffff; 253 | transfer.reg.y = state.fifo.buffer[1] >> 16; 254 | transfer.reg.w = state.fifo.buffer[2] & 0xffff; 255 | transfer.reg.h = state.fifo.buffer[2] >> 16; 256 | 257 | transfer.run.x = 0; 258 | transfer.run.y = 0; 259 | transfer.run.active = true; 260 | break; 261 | } 262 | 263 | case 0xe1: 264 | state.status &= ~0x87ff; 265 | state.status |= (state.fifo.buffer[0] << 0) & 0x7ff; 266 | state.status |= (state.fifo.buffer[0] << 4) & 0x8000; 267 | 268 | state.textured_rectangle_x_flip = ((state.fifo.buffer[0] >> 12) & 1) != 0; 269 | state.textured_rectangle_y_flip = ((state.fifo.buffer[0] >> 13) & 1) != 0; 270 | break; 271 | 272 | case 0xe2: 273 | state.texture_window_mask_x = utility::uclip<5>(state.fifo.buffer[0] >> 0); 274 | state.texture_window_mask_y = utility::uclip<5>(state.fifo.buffer[0] >> 5); 275 | state.texture_window_offset_x = utility::uclip<5>(state.fifo.buffer[0] >> 10); 276 | state.texture_window_offset_y = utility::uclip<5>(state.fifo.buffer[0] >> 15); 277 | break; 278 | 279 | case 0xe3: 280 | state.drawing_area_x1 = utility::uclip<10>(state.fifo.buffer[0] >> 0); 281 | state.drawing_area_y1 = utility::uclip<10>(state.fifo.buffer[0] >> 10); 282 | break; 283 | 284 | case 0xe4: 285 | state.drawing_area_x2 = utility::uclip<10>(state.fifo.buffer[0] >> 0); 286 | state.drawing_area_y2 = utility::uclip<10>(state.fifo.buffer[0] >> 10); 287 | break; 288 | 289 | case 0xe5: 290 | state.x_offset = utility::sclip<11>(state.fifo.buffer[0] >> 0); 291 | state.y_offset = utility::sclip<11>(state.fifo.buffer[0] >> 11); 292 | break; 293 | 294 | case 0xe6: 295 | state.status &= ~0x1800; 296 | state.status |= (state.fifo.buffer[0] << 11) & 0x1800; 297 | break; 298 | 299 | default: 300 | printf("unhandled gp0 command: 0x%08x\n", state.fifo.buffer[0]); 301 | break; 302 | } 303 | } 304 | } 305 | -------------------------------------------------------------------------------- /src/gpu/gpu_gp1.cpp: -------------------------------------------------------------------------------- 1 | #include "gpu_core.hpp" 2 | 3 | void gpu::gp1(uint32_t data) { 4 | switch ((data >> 24) & 0x3f) { 5 | case 0x00: 6 | state.status = 0x14802000; 7 | state.textured_rectangle_x_flip = 0; 8 | state.textured_rectangle_y_flip = 0; 9 | break; 10 | 11 | case 0x01: 12 | state.fifo.wr = 0; 13 | state.fifo.rd = 0; 14 | break; 15 | 16 | case 0x02: 17 | state.status &= ~0x01000000; 18 | break; 19 | 20 | case 0x03: 21 | state.status &= ~0x00800000; 22 | state.status |= (data << 23) & 0x00800000; 23 | break; 24 | 25 | case 0x04: 26 | state.status &= ~0x60000000; 27 | state.status |= (data << 29) & 0x60000000; 28 | break; 29 | 30 | case 0x05: 31 | state.display_area_x = utility::uclip<10>(data >> 0); 32 | state.display_area_y = utility::uclip< 9>(data >> 10); 33 | break; 34 | 35 | case 0x06: 36 | state.display_area_x1 = utility::uclip<12>(data >> 0); 37 | state.display_area_x2 = utility::uclip<12>(data >> 12); 38 | break; 39 | 40 | case 0x07: 41 | state.display_area_y1 = utility::uclip<10>(data >> 0); 42 | state.display_area_y2 = utility::uclip<10>(data >> 10); 43 | break; 44 | 45 | case 0x08: 46 | state.status &= ~0x7f4000; 47 | state.status |= (data << 17) & 0x7e0000; 48 | state.status |= (data << 10) & 0x10000; 49 | state.status |= (data << 7) & 0x4000; 50 | break; 51 | 52 | default: 53 | printf("unhandled gp1 command: 0x%08x\n", data); 54 | break; 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /src/input/input.cpp: -------------------------------------------------------------------------------- 1 | #include "input.hpp" 2 | 3 | static input::state_t state; 4 | 5 | uint32_t input::bus_read(int width, uint32_t address) { 6 | switch (address) { 7 | case 0x1f801040: 8 | state.status &= ~(1 << 1); 9 | return 0xffffffff; 10 | 11 | case 0x1f801044: 12 | return state.status | (1 << 0) | (1 << 2); 13 | } 14 | 15 | return 0; 16 | } 17 | 18 | void input::bus_write(int width, uint32_t address, uint32_t data) { 19 | switch (address) { 20 | case 0x1f801040: 21 | state.status |= (1 << 1); 22 | break; 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /src/input/input.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_INPUT_HPP 2 | #define PSXACT_INPUT_HPP 3 | 4 | #include 5 | 6 | namespace input { 7 | struct state_t { 8 | uint32_t status; 9 | }; 10 | 11 | uint32_t bus_read(int width, uint32_t address); 12 | 13 | void bus_write(int width, uint32_t address, uint32_t data); 14 | } 15 | 16 | #endif //PSXACT_INPUT_HPP 17 | -------------------------------------------------------------------------------- /src/memory/vram.cpp: -------------------------------------------------------------------------------- 1 | #include "vram.hpp" 2 | #include "../utility.hpp" 3 | 4 | static utility::memory_t<20> buffer; 5 | 6 | uint16_t* vram::get_pointer() { 7 | return &buffer.h[0]; 8 | } 9 | 10 | uint16_t vram::read(int x, int y) { 11 | return buffer.h[(y * 1024) + x]; 12 | } 13 | 14 | void vram::write(int x, int y, uint16_t data) { 15 | if (x < 0 || x > 0x400) return; 16 | if (y < 0 || y > 0x200) return; 17 | 18 | buffer.h[(y * 1024) + x] = data; 19 | } 20 | -------------------------------------------------------------------------------- /src/memory/vram.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_VRAM_HPP 2 | #define PSXACT_VRAM_HPP 3 | 4 | #include 5 | 6 | namespace vram { 7 | uint16_t *get_pointer(); 8 | 9 | uint16_t read(int x, int y); 10 | 11 | void write(int x, int y, uint16_t data); 12 | } 13 | 14 | #endif //PSXACT_VRAM_HPP 15 | -------------------------------------------------------------------------------- /src/psxact.cpp: -------------------------------------------------------------------------------- 1 | #include "bus.hpp" 2 | #include "cdrom/cdrom_core.hpp" 3 | #include "cpu/cpu_core.hpp" 4 | #include "gpu/gpu_core.hpp" 5 | #include "renderer.hpp" 6 | #include "timer/timer_core.hpp" 7 | 8 | int main(int argc, char *argv[]) { 9 | if (argc != 3) { 10 | return -1; 11 | } 12 | 13 | std::string bios_file_name(argv[1]); 14 | std::string game_file_name(argv[2]); 15 | 16 | cpu::initialize(); 17 | bus::initialize(bios_file_name, game_file_name); 18 | 19 | renderer::initialize(); 20 | 21 | while (renderer::render()) { 22 | for (int i = 0; i < 10; i++) { 23 | for (int i = 0; i < 33868800 / 60 / 10; i++) { 24 | cpu::tick(); 25 | timer::tick_timer_2(); 26 | } 27 | 28 | cdrom::run(); 29 | } 30 | 31 | bus::irq(0); 32 | } 33 | 34 | renderer::destroy(); 35 | 36 | return 0; 37 | } 38 | -------------------------------------------------------------------------------- /src/renderer.cpp: -------------------------------------------------------------------------------- 1 | #include "renderer.hpp" 2 | #include "memory/vram.hpp" 3 | 4 | SDL_Window *window; 5 | SDL_Surface *surface; 6 | SDL_Event event; 7 | 8 | void renderer::destroy() { 9 | SDL_DestroyWindow(window); 10 | } 11 | 12 | void renderer::initialize() { 13 | SDL_Init(SDL_INIT_VIDEO); 14 | 15 | window = SDL_CreateWindow("psxact", 16 | SDL_WINDOWPOS_CENTERED, 17 | SDL_WINDOWPOS_CENTERED, 1024, 512, 0); 18 | 19 | surface = SDL_GetWindowSurface(window); 20 | } 21 | 22 | uint32_t color_16_to_24(uint32_t color) { 23 | auto r = ((color << 3) & 0xf8); 24 | auto g = ((color >> 2) & 0xf8); 25 | auto b = ((color >> 7) & 0xf8); 26 | 27 | return (0xff << 24) | (r << 16) | (g << 8) | (b << 0); 28 | } 29 | 30 | bool renderer::render() { 31 | SDL_LockSurface(surface); 32 | 33 | auto pixels = (uint32_t *)surface->pixels; 34 | auto colors = vram::get_pointer(); 35 | 36 | for (uint32_t i = 0; i < 1024 * 512; i++) { 37 | *pixels++ = color_16_to_24( colors[i] ); 38 | } 39 | 40 | SDL_UnlockSurface(surface); 41 | SDL_UpdateWindowSurface(window); 42 | 43 | return !SDL_PollEvent(&event) || event.type != SDL_QUIT; 44 | } 45 | -------------------------------------------------------------------------------- /src/renderer.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_RENDERER_HPP 2 | #define PSXACT_RENDERER_HPP 3 | 4 | #include 5 | 6 | namespace renderer { 7 | void destroy(); 8 | 9 | void initialize(); 10 | 11 | bool render(); 12 | } 13 | 14 | #endif //PSXACT_RENDERER_HPP 15 | -------------------------------------------------------------------------------- /src/spu/spu_core.cpp: -------------------------------------------------------------------------------- 1 | #include "spu_core.hpp" 2 | 3 | uint32_t spu::bus_read(int width, uint32_t address) { 4 | return 0; 5 | } 6 | 7 | void spu::bus_write(int width, uint32_t address, uint32_t data) { 8 | } 9 | -------------------------------------------------------------------------------- /src/spu/spu_core.hpp: -------------------------------------------------------------------------------- 1 | #ifndef __SPU_CORE_HPP__ 2 | #define __SPU_CORE_HPP__ 3 | 4 | #include 5 | 6 | namespace spu { 7 | uint32_t bus_read(int width, uint32_t address); 8 | 9 | void bus_write(int width, uint32_t address, uint32_t data); 10 | } 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /src/timer/timer_core.cpp: -------------------------------------------------------------------------------- 1 | #include "timer_core.hpp" 2 | #include "../bus.hpp" 3 | 4 | static timer::state_t timers[3]; 5 | 6 | uint32_t timer::bus_read(int width, uint32_t address) { 7 | int n = (address >> 4) & 3; 8 | 9 | switch ((address & 0xf) / 4) { 10 | case 0: return timers[n].counter; 11 | case 1: return timers[n].control; 12 | case 2: return timers[n].compare; 13 | } 14 | 15 | return 0; 16 | } 17 | 18 | void timer::bus_write(int width, uint32_t address, uint32_t data) { 19 | int n = (address >> 4) & 3; 20 | 21 | switch ((address & 0xf) / 4) { 22 | case 0: 23 | timers[n].counter = uint16_t(data); 24 | break; 25 | 26 | case 1: 27 | timers[n].control = uint16_t(data | 0x400); 28 | timers[n].counter = 0; 29 | break; 30 | 31 | case 2: 32 | timers[n].compare = uint16_t(data); 33 | break; 34 | } 35 | } 36 | 37 | void timer::tick_timer_2() { 38 | // system clock/8 39 | timers[2].divider++; 40 | 41 | if (timers[2].divider == 8) { 42 | timers[2].divider = 0; 43 | timers[2].counter++; 44 | 45 | if (timers[2].counter == timers[2].compare) { 46 | timers[2].control |= 0x800; 47 | 48 | if (timers[2].control & 0x0008) { 49 | timers[2].counter = 0; 50 | } 51 | 52 | if (timers[2].control & 0x0010) { 53 | timers[2].control &= ~0x0400; 54 | bus::irq(6); 55 | } 56 | } 57 | } 58 | } 59 | -------------------------------------------------------------------------------- /src/timer/timer_core.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_TIMER_CORE_HPP 2 | #define PSXACT_TIMER_CORE_HPP 3 | 4 | #include 5 | 6 | namespace timer { 7 | struct state_t { 8 | uint16_t counter; 9 | uint16_t control; 10 | uint16_t compare; 11 | int divider; 12 | }; 13 | 14 | uint32_t bus_read(int width, uint32_t address); 15 | 16 | void bus_write(int width, uint32_t address, uint32_t data); 17 | 18 | void run_timer_0(); 19 | 20 | void run_timer_1(); 21 | 22 | void tick_timer_2(); 23 | } 24 | 25 | #endif //PSXACT_TIMER_CORE_HPP 26 | -------------------------------------------------------------------------------- /src/utility.hpp: -------------------------------------------------------------------------------- 1 | #ifndef PSXACT_UTILITY_HPP 2 | #define PSXACT_UTILITY_HPP 3 | 4 | #include 5 | #include 6 | 7 | namespace utility { 8 | template 9 | struct memory_t { 10 | static constexpr int mask = (1 << bits) - 1; 11 | static constexpr int size = (1 << bits); 12 | 13 | union { 14 | uint8_t b[size]; 15 | uint16_t h[size / 2]; 16 | uint32_t w[size / 4]; 17 | }; 18 | }; 19 | 20 | template 21 | void read_all_bytes(const char *filename, memory_t &memory) { 22 | if (FILE* file = fopen(filename, "rb+")) { 23 | fread(memory.b, 1, memory.size, file); 24 | fclose(file); 25 | } 26 | } 27 | 28 | template 29 | uint32_t read_byte(const memory_t &memory, uint32_t address) { 30 | return memory.b[(address & memory.mask) / 1]; 31 | } 32 | 33 | template 34 | uint32_t read_half(const memory_t &memory, uint32_t address) { 35 | return memory.h[(address & memory.mask) / 2]; 36 | } 37 | 38 | template 39 | uint32_t read_word(const memory_t &memory, uint32_t address) { 40 | return memory.w[(address & memory.mask) / 4]; 41 | } 42 | 43 | template 44 | void write_byte(memory_t &memory, uint32_t address, uint32_t data) { 45 | memory.b[(address & memory.mask) / 1] = uint8_t(data); 46 | } 47 | 48 | template 49 | void write_half(memory_t &memory, uint32_t address, uint32_t data) { 50 | memory.h[(address & memory.mask) / 2] = uint16_t(data); 51 | } 52 | 53 | template 54 | void write_word(memory_t &memory, uint32_t address, uint32_t data) { 55 | memory.w[(address & memory.mask) / 4] = data; 56 | } 57 | 58 | template 59 | inline uint32_t sclip(uint32_t value) { 60 | enum { mask = (1 << bits) - 1 }; 61 | enum { sign = 1 << (bits - 1) }; 62 | 63 | return ((value & mask) ^ sign) - sign; 64 | } 65 | 66 | template 67 | inline uint32_t uclip(uint32_t value) { 68 | enum { mask = (1 << bits) - 1 }; 69 | enum { sign = 0 }; 70 | 71 | return ((value & mask) ^ sign) - sign; 72 | } 73 | 74 | template 75 | inline bool between(unsigned value) { 76 | return (value & ~(min ^ max)) == min; 77 | } 78 | 79 | template 80 | constexpr unsigned kib() { 81 | return 1024 * value; 82 | } 83 | 84 | template 85 | constexpr unsigned mib() { 86 | return 1024 * kib(); 87 | } 88 | } 89 | 90 | #endif //PSXACT_UTILITY_HPP 91 | --------------------------------------------------------------------------------