├── Default.wcfg
├── LICENSE
├── bfcpu2.gise
├── bfcpu2.xise
├── irom.h
└── verilog
    ├── BrainfuckCore.v
    ├── Common.tf
    ├── Constants.v
    ├── Counter.v
    ├── DRAM.v
    ├── IROM.v
    ├── Stack.v
    ├── StageExecute.v
    ├── StageIDecode.v
    ├── StageIFetch.v
    ├── StageModify.v
    ├── StageTemplate.v
    ├── StageWriteback.v
    └── UART.v


/Default.wcfg:
--------------------------------------------------------------------------------
  1 | <?xml version="1.0" encoding="UTF-8"?>
  2 | <wave_config>
  3 |    <wave_state>
  4 |    </wave_state>
  5 |    <db_ref_list>
  6 |       <db_ref path="/home/whitequark/xilinx/bfcpu2/BrainfuckCoreTest_isim_beh.wdb" id="1" type="auto">
  7 |          <top_modules>
  8 |             <top_module name="BrainfuckCoreTest" />
  9 |             <top_module name="glbl" />
 10 |          </top_modules>
 11 |       </db_ref>
 12 |    </db_ref_list>
 13 |    <WVObjectSize size="29" />
 14 |    <wvobject fp_name="/BrainfuckCoreTest/uut/clk" type="logic" db_ref_id="1">
 15 |       <obj_property name="ElementShortName">clk</obj_property>
 16 |       <obj_property name="ObjectShortName">clk</obj_property>
 17 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 18 |       <obj_property name="CustomSignalColor">#ffff00</obj_property>
 19 |    </wvobject>
 20 |    <wvobject fp_name="/BrainfuckCoreTest/uut/reset" type="logic" db_ref_id="1">
 21 |       <obj_property name="ElementShortName">reset</obj_property>
 22 |       <obj_property name="ObjectShortName">reset</obj_property>
 23 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 24 |       <obj_property name="CustomSignalColor">#808080</obj_property>
 25 |    </wvobject>
 26 |    <wvobject fp_name="/BrainfuckCoreTest/uut/pc_ce" type="logic" db_ref_id="1">
 27 |       <obj_property name="ElementShortName">pc_ce</obj_property>
 28 |       <obj_property name="ObjectShortName">pc_ce</obj_property>
 29 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 30 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
 31 |    </wvobject>
 32 |    <wvobject fp_name="/BrainfuckCoreTest/uut/pc" type="array" db_ref_id="1">
 33 |       <obj_property name="ElementShortName">pc[11:0]</obj_property>
 34 |       <obj_property name="ObjectShortName">pc[11:0]</obj_property>
 35 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 36 |       <obj_property name="CustomSignalColor">#ffa500</obj_property>
 37 |    </wvobject>
 38 |    <wvobject fp_name="/BrainfuckCoreTest/ice" type="logic" db_ref_id="1">
 39 |       <obj_property name="ElementShortName">ice</obj_property>
 40 |       <obj_property name="ObjectShortName">ice</obj_property>
 41 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 42 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
 43 |    </wvobject>
 44 |    <wvobject fp_name="/BrainfuckCoreTest/ia" type="array" db_ref_id="1">
 45 |       <obj_property name="ElementShortName">ia[11:0]</obj_property>
 46 |       <obj_property name="ObjectShortName">ia[11:0]</obj_property>
 47 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 48 |       <obj_property name="CustomSignalColor">#ffff00</obj_property>
 49 |    </wvobject>
 50 |    <wvobject fp_name="/BrainfuckCoreTest/id" type="array" db_ref_id="1">
 51 |       <obj_property name="ElementShortName">id[7:0]</obj_property>
 52 |       <obj_property name="ObjectShortName">id[7:0]</obj_property>
 53 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 54 |       <obj_property name="CustomSignalColor">#ff00ff</obj_property>
 55 |    </wvobject>
 56 |    <wvobject fp_name="/BrainfuckCoreTest/uut/idecode_opcode" type="array" db_ref_id="1">
 57 |       <obj_property name="ElementShortName">idecode_opcode[7:0]</obj_property>
 58 |       <obj_property name="ObjectShortName">idecode_opcode[7:0]</obj_property>
 59 |       <obj_property name="Radix">ASCIIRADIX</obj_property>
 60 |    </wvobject>
 61 |    <wvobject fp_name="/BrainfuckCoreTest/uut/execute_operation" type="array" db_ref_id="1">
 62 |       <obj_property name="ElementShortName">execute_operation[7:0]</obj_property>
 63 |       <obj_property name="ObjectShortName">execute_operation[7:0]</obj_property>
 64 |    </wvobject>
 65 |    <wvobject fp_name="/BrainfuckCoreTest/uut/writeback_operation" type="array" db_ref_id="1">
 66 |       <obj_property name="ElementShortName">writeback_operation[7:0]</obj_property>
 67 |       <obj_property name="ObjectShortName">writeback_operation[7:0]</obj_property>
 68 |    </wvobject>
 69 |    <wvobject fp_name="/BrainfuckCoreTest/uut/execute/do_mem_fetch" type="logic" db_ref_id="1">
 70 |       <obj_property name="ElementShortName">do_mem_fetch</obj_property>
 71 |       <obj_property name="ObjectShortName">do_mem_fetch</obj_property>
 72 |    </wvobject>
 73 |    <wvobject fp_name="/BrainfuckCoreTest/uut/execute/do_reg_forward" type="logic" db_ref_id="1">
 74 |       <obj_property name="ElementShortName">do_reg_forward</obj_property>
 75 |       <obj_property name="ObjectShortName">do_reg_forward</obj_property>
 76 |    </wvobject>
 77 |    <wvobject fp_name="/BrainfuckCoreTest/uut/execute_a" type="array" db_ref_id="1">
 78 |       <obj_property name="ElementShortName">execute_a[7:0]</obj_property>
 79 |       <obj_property name="ObjectShortName">execute_a[7:0]</obj_property>
 80 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 81 |       <obj_property name="CustomSignalColor">#ffa500</obj_property>
 82 |    </wvobject>
 83 |    <wvobject fp_name="/BrainfuckCoreTest/uut/dp" type="array" db_ref_id="1">
 84 |       <obj_property name="ElementShortName">dp[11:0]</obj_property>
 85 |       <obj_property name="ObjectShortName">dp[11:0]</obj_property>
 86 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 87 |       <obj_property name="CustomSignalColor">#ffa500</obj_property>
 88 |    </wvobject>
 89 |    <wvobject fp_name="/BrainfuckCoreTest/uut/drce" type="logic" db_ref_id="1">
 90 |       <obj_property name="ElementShortName">drce</obj_property>
 91 |       <obj_property name="ObjectShortName">drce</obj_property>
 92 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 93 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
 94 |    </wvobject>
 95 |    <wvobject fp_name="/BrainfuckCoreTest/uut/dra" type="array" db_ref_id="1">
 96 |       <obj_property name="ElementShortName">dra[11:0]</obj_property>
 97 |       <obj_property name="ObjectShortName">dra[11:0]</obj_property>
 98 |       <obj_property name="UseCustomSignalColor">true</obj_property>
 99 |       <obj_property name="CustomSignalColor">#ffff00</obj_property>
100 |    </wvobject>
101 |    <wvobject fp_name="/BrainfuckCoreTest/drd" type="array" db_ref_id="1">
102 |       <obj_property name="ElementShortName">drd[7:0]</obj_property>
103 |       <obj_property name="ObjectShortName">drd[7:0]</obj_property>
104 |       <obj_property name="UseCustomSignalColor">true</obj_property>
105 |       <obj_property name="CustomSignalColor">#ff00ff</obj_property>
106 |    </wvobject>
107 |    <wvobject fp_name="/BrainfuckCoreTest/uut/dwce" type="logic" db_ref_id="1">
108 |       <obj_property name="ElementShortName">dwce</obj_property>
109 |       <obj_property name="ObjectShortName">dwce</obj_property>
110 |       <obj_property name="UseCustomSignalColor">true</obj_property>
111 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
112 |    </wvobject>
113 |    <wvobject fp_name="/BrainfuckCoreTest/uut/dwa" type="array" db_ref_id="1">
114 |       <obj_property name="ElementShortName">dwa[11:0]</obj_property>
115 |       <obj_property name="ObjectShortName">dwa[11:0]</obj_property>
116 |       <obj_property name="UseCustomSignalColor">true</obj_property>
117 |       <obj_property name="CustomSignalColor">#ffff00</obj_property>
118 |    </wvobject>
119 |    <wvobject fp_name="/BrainfuckCoreTest/dwq" type="array" db_ref_id="1">
120 |       <obj_property name="ElementShortName">dwq[7:0]</obj_property>
121 |       <obj_property name="ObjectShortName">dwq[7:0]</obj_property>
122 |       <obj_property name="UseCustomSignalColor">true</obj_property>
123 |       <obj_property name="CustomSignalColor">#ff00ff</obj_property>
124 |    </wvobject>
125 |    <wvobject fp_name="/BrainfuckCoreTest/cwre" type="logic" db_ref_id="1">
126 |       <obj_property name="ElementShortName">cwre</obj_property>
127 |       <obj_property name="ObjectShortName">cwre</obj_property>
128 |       <obj_property name="UseCustomSignalColor">true</obj_property>
129 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
130 |    </wvobject>
131 |    <wvobject fp_name="/BrainfuckCoreTest/cbsy" type="logic" db_ref_id="1">
132 |       <obj_property name="ElementShortName">cbsy</obj_property>
133 |       <obj_property name="ObjectShortName">cbsy</obj_property>
134 |       <obj_property name="UseCustomSignalColor">true</obj_property>
135 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
136 |    </wvobject>
137 |    <wvobject fp_name="/BrainfuckCoreTest/cq" type="array" db_ref_id="1">
138 |       <obj_property name="DisplayName">label</obj_property>
139 |       <obj_property name="ElementShortName">cq[7:0]</obj_property>
140 |       <obj_property name="ObjectShortName">cq[7:0]</obj_property>
141 |       <obj_property name="UseCustomSignalColor">true</obj_property>
142 |       <obj_property name="CustomSignalColor">#ff00ff</obj_property>
143 |       <obj_property name="label">cq[7:0]</obj_property>
144 |    </wvobject>
145 |    <wvobject fp_name="/BrainfuckCoreTest/crda" type="logic" db_ref_id="1">
146 |       <obj_property name="ElementShortName">crda</obj_property>
147 |       <obj_property name="ObjectShortName">crda</obj_property>
148 |       <obj_property name="UseCustomSignalColor">true</obj_property>
149 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
150 |    </wvobject>
151 |    <wvobject fp_name="/BrainfuckCoreTest/cack" type="logic" db_ref_id="1">
152 |       <obj_property name="ElementShortName">cack</obj_property>
153 |       <obj_property name="ObjectShortName">cack</obj_property>
154 |       <obj_property name="UseCustomSignalColor">true</obj_property>
155 |       <obj_property name="CustomSignalColor">#00ffff</obj_property>
156 |    </wvobject>
157 |    <wvobject fp_name="/BrainfuckCoreTest/cd" type="array" db_ref_id="1">
158 |       <obj_property name="ElementShortName">cd[7:0]</obj_property>
159 |       <obj_property name="ObjectShortName">cd[7:0]</obj_property>
160 |       <obj_property name="UseCustomSignalColor">true</obj_property>
161 |       <obj_property name="CustomSignalColor">#ff00ff</obj_property>
162 |    </wvobject>
163 |    <wvobject fp_name="/BrainfuckCoreTest/uut/idecode_ack" type="logic" db_ref_id="1">
164 |       <obj_property name="ElementShortName">idecode_ack</obj_property>
165 |       <obj_property name="ObjectShortName">idecode_ack</obj_property>
166 |    </wvobject>
167 |    <wvobject fp_name="/BrainfuckCoreTest/uut/execute_ack" type="logic" db_ref_id="1">
168 |       <obj_property name="ElementShortName">execute_ack</obj_property>
169 |       <obj_property name="ObjectShortName">execute_ack</obj_property>
170 |    </wvobject>
171 |    <wvobject fp_name="/BrainfuckCoreTest/uut/writeback_ack" type="logic" db_ref_id="1">
172 |       <obj_property name="ElementShortName">writeback_ack</obj_property>
173 |       <obj_property name="ObjectShortName">writeback_ack</obj_property>
174 |    </wvobject>
175 | </wave_config>
176 | 


--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
 1 | Copyright (C) 2011, 2012  Peter Zotov <whitequark@whitequark.org>
 2 | 
 3 | Permission is hereby granted, free of charge, to any person obtaining a copy of
 4 | this software and associated documentation files (the "Software"), to deal in
 5 | the Software without restriction, including without limitation the rights to
 6 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
 7 | of the Software, and to permit persons to whom the Software is furnished to do
 8 | so, subject to the following conditions:
 9 | 
10 | The above copyright notice and this permission notice shall be included in all
11 | copies or substantial portions of the Software.
12 | 
13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
19 | SOFTWARE.
20 | 


--------------------------------------------------------------------------------
/bfcpu2.gise:
--------------------------------------------------------------------------------
 1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
 2 | <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 3 | 
 4 |   <!--                                                          -->
 5 | 
 6 |   <!--             For tool use only. Do not edit.              -->
 7 | 
 8 |   <!--                                                          -->
 9 | 
10 |   <!-- ProjectNavigator created generated project file.         -->
11 | 
12 |   <!-- For use in tracking generated file and other information -->
13 | 
14 |   <!-- allowing preservation of process status.                 -->
15 | 
16 |   <!--                                                          -->
17 | 
18 |   <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
19 | 
20 |   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
21 | 
22 |   <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="bfcpu2.xise"/>
23 | 
24 |   <files xmlns="http://www.xilinx.com/XMLSchema">
25 |     <file xil_pn:fileType="FILE_NCD" xil_pn:name="BrainfuckCore_guide.ncd" xil_pn:origination="imported"/>
26 |   </files>
27 | 
28 |   <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
29 | 
30 | </generated_project>
31 | 


--------------------------------------------------------------------------------
/bfcpu2.xise:
--------------------------------------------------------------------------------
  1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2 | <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
  3 | 
  4 |   <header>
  5 |     <!-- ISE source project file created by Project Navigator.             -->
  6 |     <!--                                                                   -->
  7 |     <!-- This file contains project source information including a list of -->
  8 |     <!-- project source files, project and process properties.  This file, -->
  9 |     <!-- along with the project source files, is sufficient to open and    -->
 10 |     <!-- implement in ISE Project Navigator.                               -->
 11 |     <!--                                                                   -->
 12 |     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
 13 |   </header>
 14 | 
 15 |   <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
 16 | 
 17 |   <files>
 18 |     <file xil_pn:name="verilog/Stack.v" xil_pn:type="FILE_VERILOG">
 19 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
 20 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 21 |     </file>
 22 |     <file xil_pn:name="verilog/Counter.v" xil_pn:type="FILE_VERILOG">
 23 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
 24 |       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
 25 |     </file>
 26 |     <file xil_pn:name="verilog/StageIFetch.v" xil_pn:type="FILE_VERILOG">
 27 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
 28 |       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
 29 |     </file>
 30 |     <file xil_pn:name="verilog/IROM.v" xil_pn:type="FILE_VERILOG">
 31 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
 32 |       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
 33 |     </file>
 34 |     <file xil_pn:name="verilog/StageIDecode.v" xil_pn:type="FILE_VERILOG">
 35 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
 36 |       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
 37 |     </file>
 38 |     <file xil_pn:name="verilog/BrainfuckCore.v" xil_pn:type="FILE_VERILOG">
 39 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
 40 |       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
 41 |     </file>
 42 |     <file xil_pn:name="verilog/StageExecute.v" xil_pn:type="FILE_VERILOG">
 43 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
 44 |       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
 45 |     </file>
 46 |     <file xil_pn:name="verilog/DRAM.v" xil_pn:type="FILE_VERILOG">
 47 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
 48 |       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
 49 |     </file>
 50 |     <file xil_pn:name="verilog/StageModify.v" xil_pn:type="FILE_VERILOG">
 51 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
 52 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 53 |     </file>
 54 |     <file xil_pn:name="verilog/StageWriteback.v" xil_pn:type="FILE_VERILOG">
 55 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
 56 |       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
 57 |     </file>
 58 |     <file xil_pn:name="verilog/UART.v" xil_pn:type="FILE_VERILOG">
 59 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
 60 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 61 |     </file>
 62 |     <file xil_pn:name="verilog/StageWriteback.v" xil_pn:type="FILE_VERILOG">
 63 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
 64 |       <association xil_pn:name="Implementation" xil_pn:seqID="252"/>
 65 |     </file>
 66 |   </files>
 67 | 
 68 |   <properties>
 69 |     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
 70 |     <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
 71 |     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
 72 |     <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
 73 |     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
 74 |     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
 75 |     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
 76 |     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
 77 |     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
 78 |     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
 79 |     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
 80 |     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
 81 |     <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
 82 |     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
 83 |     <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
 84 |     <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
 85 |     <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
 86 |     <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
 87 |     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
 88 |     <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
 89 |     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
 90 |     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
 91 |     <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
 92 |     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
 93 |     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
 94 |     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
 95 |     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
 96 |     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 97 |     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 98 |     <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
 99 |     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
100 |     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
101 |     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
102 |     <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
103 |     <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
104 |     <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
105 |     <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
106 |     <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
107 |     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
108 |     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
109 |     <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Default.wcfg" xil_pn:valueState="non-default"/>
110 |     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
111 |     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
112 |     <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
113 |     <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
114 |     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
115 |     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
116 |     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
117 |     <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
118 |     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
119 |     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
120 |     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
121 |     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
122 |     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
123 |     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
124 |     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
125 |     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
126 |     <property xil_pn:name="Evaluation Development Board" xil_pn:value="" xil_pn:valueState="non-default"/>
127 |     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
128 |     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
129 |     <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
130 |     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
131 |     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
132 |     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
133 |     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
134 |     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
135 |     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
136 |     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
137 |     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
138 |     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
139 |     <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
140 |     <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
141 |     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
142 |     <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
143 |     <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
144 |     <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
145 |     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
146 |     <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
147 |     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
148 |     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
149 |     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
150 |     <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
151 |     <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
152 |     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
153 |     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
154 |     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
155 |     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
156 |     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
157 |     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
158 |     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
159 |     <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
160 |     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
161 |     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
162 |     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
163 |     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
164 |     <property xil_pn:name="Implementation Top" xil_pn:value="Module|BrainfuckCore" xil_pn:valueState="non-default"/>
165 |     <property xil_pn:name="Implementation Top File" xil_pn:value="verilog/BrainfuckCore.v" xil_pn:valueState="non-default"/>
166 |     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/BrainfuckCoreTest/uut" xil_pn:valueState="non-default"/>
167 |     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
168 |     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
169 |     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
170 |     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
171 |     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
172 |     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
173 |     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
174 |     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
175 |     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
176 |     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
177 |     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
178 |     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
179 |     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
180 |     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
181 |     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
182 |     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
183 |     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
184 |     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
185 |     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
186 |     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
187 |     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
188 |     <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
189 |     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
190 |     <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
191 |     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
192 |     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
193 |     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
194 |     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
195 |     <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
196 |     <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
197 |     <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
198 |     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
199 |     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
200 |     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
201 |     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
202 |     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
203 |     <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
204 |     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
205 |     <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
206 |     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
207 |     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
208 |     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
209 |     <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
210 |     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
211 |     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
212 |     <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
213 |     <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
214 |     <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
215 |     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
216 |     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
217 |     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
218 |     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
219 |     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
220 |     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
221 |     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
222 |     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
223 |     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="-use_new_parser yes" xil_pn:valueState="non-default"/>
224 |     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
225 |     <property xil_pn:name="Output File Name" xil_pn:value="BrainfuckCore" xil_pn:valueState="default"/>
226 |     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
227 |     <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
228 |     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
229 |     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
230 |     <property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
231 |     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
232 |     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
233 |     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
234 |     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
235 |     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
236 |     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
237 |     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
238 |     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="BrainfuckCore_map.v" xil_pn:valueState="default"/>
239 |     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="BrainfuckCore_timesim.v" xil_pn:valueState="default"/>
240 |     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="BrainfuckCore_synthesis.v" xil_pn:valueState="default"/>
241 |     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="BrainfuckCore_translate.v" xil_pn:valueState="default"/>
242 |     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
243 |     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
244 |     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
245 |     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
246 |     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
247 |     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
248 |     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
249 |     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
250 |     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
251 |     <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
252 |     <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
253 |     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
254 |     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
255 |     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
256 |     <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
257 |     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
258 |     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
259 |     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
260 |     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
261 |     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
262 |     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
263 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
264 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
265 |     <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
266 |     <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
267 |     <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
268 |     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
269 |     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
270 |     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
271 |     <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
272 |     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
273 |     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
274 |     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
275 |     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
276 |     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
277 |     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
278 |     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
279 |     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
280 |     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
281 |     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
282 |     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
283 |     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/BrainfuckCoreTest/uut/execute" xil_pn:valueState="non-default"/>
284 |     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.StageExecute" xil_pn:valueState="non-default"/>
285 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
286 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
287 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work." xil_pn:valueState="non-default"/>
288 |     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
289 |     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
290 |     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
291 |     <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
292 |     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="500 ns" xil_pn:valueState="non-default"/>
293 |     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
294 |     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
295 |     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
296 |     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
297 |     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
298 |     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
299 |     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
300 |     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.StageExecute" xil_pn:valueState="default"/>
301 |     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
302 |     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
303 |     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work." xil_pn:valueState="default"/>
304 |     <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
305 |     <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
306 |     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
307 |     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
308 |     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
309 |     <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
310 |     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
311 |     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
312 |     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
313 |     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
314 |     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
315 |     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
316 |     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
317 |     <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
318 |     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
319 |     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
320 |     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
321 |     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
322 |     <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
323 |     <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
324 |     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
325 |     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
326 |     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
327 |     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
328 |     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
329 |     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
330 |     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
331 |     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
332 |     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
333 |     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
334 |     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
335 |     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
336 |     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
337 |     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
338 |     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
339 |     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
340 |     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
341 |     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
342 |     <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
343 |     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
344 |     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
345 |     <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
346 |     <!--                                                                                  -->
347 |     <!-- The following properties are for internal use only. These should not be modified.-->
348 |     <!--                                                                                  -->
349 |     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|BrainfuckCoreTest" xil_pn:valueState="non-default"/>
350 |     <property xil_pn:name="PROP_DesignName" xil_pn:value="bfcpu2" xil_pn:valueState="non-default"/>
351 |     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
352 |     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
353 |     <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
354 |     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
355 |     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
356 |     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
357 |     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Module|" xil_pn:valueState="non-default"/>
358 |     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
359 |     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-12-14T22:30:22" xil_pn:valueState="non-default"/>
360 |     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="024B5103C4FF89308A7C19828A9597AE" xil_pn:valueState="non-default"/>
361 |     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
362 |     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
363 |   </properties>
364 | 
365 |   <bindings/>
366 | 
367 |   <libraries/>
368 | 
369 |   <autoManagedFiles>
370 |     <!-- The following files are identified by `include statements in verilog -->
371 |     <!-- source files and are automatically managed by Project Navigator.     -->
372 |     <!--                                                                      -->
373 |     <!-- Do not hand-edit this section, as it will be overwritten when the    -->
374 |     <!-- project is analyzed based on files automatically identified as       -->
375 |     <!-- include files.                                                       -->
376 |     <file xil_pn:name="verilog/Constants.v" xil_pn:type="FILE_VERILOG"/>
377 |     <file xil_pn:name="verilog/Common.tf" xil_pn:type="FILE_VERILOG"/>
378 |   </autoManagedFiles>
379 | 
380 | </project>
381 | 


--------------------------------------------------------------------------------
/irom.h:
--------------------------------------------------------------------------------
1 | @00000000
2 | 2b 2b 2b 2b 2b 5b 2d 5d
3 | 


--------------------------------------------------------------------------------
/verilog/BrainfuckCore.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | `include "Common.tf"
  3 | `include "Constants.v"
  4 | 
  5 | module BrainfuckCore(
  6 | 	clk,
  7 | 	reset,
  8 | 
  9 | 	/* IROM interface */
 10 | 	ice,
 11 | 	ia,
 12 | 	id,
 13 | 
 14 | 	/* DRAM read port */
 15 | 	drce,
 16 | 	dra,
 17 | 	drd,
 18 | 
 19 | 	/* DRAM write port */
 20 | 	dwce,
 21 | 	dwa,
 22 | 	dwq,
 23 | 
 24 | 	/* EXT read port */
 25 | 	cd,
 26 | 	crda,
 27 | 	cack,
 28 | 
 29 | 	/* EXT write port */
 30 | 	cq,
 31 | 	cwre,
 32 | 	cbsy
 33 | );
 34 | 
 35 | 	parameter IA_WIDTH = 12;
 36 | 	parameter ID_WIDTH = 8;
 37 | 	parameter DA_WIDTH = 12;
 38 | 	parameter DD_WIDTH = 8;
 39 | 
 40 | 	input clk;
 41 | 	input reset;
 42 | 
 43 | 	wire [IA_WIDTH - 1:0] pc;
 44 | 	wire pc_ce;
 45 | 
 46 | 	Counter #(
 47 | 		.WIDTH(IA_WIDTH)
 48 | 	) reg_pc (
 49 | 		.clk(clk),
 50 | 		.reset(reset),
 51 | 		.ce(pc_ce),
 52 | 		.q(pc),
 53 | 		.d(12'b0),
 54 | 		.load(1'b0),
 55 | 		.down(1'b0)
 56 | 	);
 57 | 
 58 | 	wire [DA_WIDTH - 1:0] dp;
 59 | 	wire dp_ce, dp_down;
 60 | 
 61 | 	Counter #(
 62 | 		.WIDTH(DA_WIDTH)
 63 | 	) reg_dp (
 64 | 		.clk(clk),
 65 | 		.reset(reset),
 66 | 		.ce(dp_ce),
 67 | 		.q(dp),
 68 | 		.d(12'b0),
 69 | 		.load(1'b0),
 70 | 		.down(dp_down)
 71 | 	);
 72 | 
 73 | 	output ice;
 74 | 	output [IA_WIDTH - 1:0] ia;
 75 | 	input  [ID_WIDTH - 1:0] id;
 76 | 
 77 | 	output drce, dwce;
 78 | 	output [DA_WIDTH - 1:0] dra;
 79 | 	output [DA_WIDTH - 1:0] dwa;
 80 | 	input  [DD_WIDTH - 1:0] drd;
 81 | 	output [DD_WIDTH - 1:0] dwq;
 82 | 
 83 | 	input  [7:0] cd;
 84 | 	input        crda;
 85 | 	output       cack;
 86 | 
 87 | 	output [7:0] cq;
 88 | 	output       cwre;
 89 | 	input        cbsy;
 90 | 
 91 | 	wire [ID_WIDTH - 1:0] idecode_opcode;
 92 | 	wire                  idecode_ack;
 93 | 
 94 | 	wire [`OPCODE_MSB:0]  execute_operation;
 95 | 	wire                  execute_ack;
 96 | 	wire [DD_WIDTH - 1:0] execute_a;
 97 | 
 98 | 	wire [`OPCODE_MSB:0]  writeback_operation;
 99 | 	wire                  writeback_ack;
100 | 	wire [DA_WIDTH - 1:0] writeback_dp;
101 | 
102 | 	/*
103 | 	 * Fetch instruction, taking memory delays into
104 | 	 * account.
105 | 	 * This stage prefetches one instruction.
106 | 	 */
107 | 	StageIFetch #(
108 | 		.A_WIDTH(IA_WIDTH),
109 | 		.D_WIDTH(ID_WIDTH)
110 | 	) ifetch (
111 | 		.clk(clk),
112 | 		.reset(reset),
113 | 
114 | 		/* PC register value, to get instruction address */
115 | 		.pc(pc),
116 | 
117 | 		/* Has ifetch got an instruction last cycle? */
118 | 		.step_pc(pc_ce),
119 | 
120 | 		/* IROM interface */
121 | 		.ice(ice),
122 | 		.ia(ia),
123 | 		.id(id),
124 | 
125 | 		.opcode(idecode_opcode),
126 | 		.ack_in(idecode_ack)
127 | 	);
128 | 
129 | 	/*
130 | 	 * Decode instruction. IDecode has fixed 8 bit width.
131 | 	 */
132 | 	StageIDecode idecode (
133 | 		.clk(clk),
134 | 		.reset(reset),
135 | 
136 | 		.opcode_in(idecode_opcode),
137 | 		.ack(idecode_ack),
138 | 
139 | 		.operation(execute_operation),
140 | 		.ack_in(execute_ack)
141 | 	);
142 | 
143 | 	/*
144 | 	 * Execute the instruction.
145 | 	 * This stage prefetches one datum and maintains cache consistency
146 | 	 * on data pointer updates.
147 | 	 */
148 | 	StageExecute #(
149 | 		.A_WIDTH(DA_WIDTH),
150 | 		.D_WIDTH(DD_WIDTH)
151 | 	) execute (
152 | 		.clk(clk),
153 | 		.reset(reset),
154 | 
155 | 		/* DP register value, to get a datum */
156 | 		.dp(dp),
157 | 
158 | 		/* DP register increment and decrement control lines */
159 | 		.dp_ce(dp_ce),
160 | 		.dp_down(dp_down),
161 | 
162 | 		/* DP register cache, to avoid WAW(mem,dp) hazard */
163 | 		.dp_cache(writeback_dp),
164 | 
165 | 		/* DRAM read port interface */
166 | 		.dce(drce),
167 | 		.da(dra),
168 | 		.dd(drd),
169 | 
170 | 		/* EXT read port interface */
171 | 		.cd(cd),
172 | 		.crda(crda),
173 | 		.cack(cack),
174 | 
175 | 		/* Accumulator output */
176 | 		.a(execute_a),
177 | 
178 | 		.operation_in(execute_operation),
179 | 		.ack(execute_ack),
180 | 
181 | 		.operation(writeback_operation),
182 | 		.ack_in(writeback_ack)
183 | 	);
184 | 
185 | 	/*
186 | 	 * Write accumulator back to DRAM or to I/O module.
187 | 	 */
188 | 	StageWriteback #(
189 | 		.A_WIDTH(DA_WIDTH),
190 | 		.D_WIDTH(DD_WIDTH)
191 | 	) writeback (
192 | 		.clk(clk),
193 | 		.reset(reset),
194 | 
195 | 		/* DP register value, to write a datum */
196 | 		.dp(writeback_dp),
197 | 
198 | 		/* DRAM write port interface */
199 | 		.dce(dwce),
200 | 		.da(dwa),
201 | 		.dq(dwq),
202 | 
203 | 		/* EXT write port interface */
204 | 		.cq(cq),
205 | 		.cwre(cwre),
206 | 		.cbsy(cbsy),
207 | 
208 | 		/* Accumulator input */
209 | 		.a_in(execute_a),
210 | 
211 | 		.operation_in(writeback_operation),
212 | 		.ack(writeback_ack),
213 | 
214 | 		/* The last stage has ACK always asserted. */
215 | 		.ack_in(1'b1)
216 | 	);
217 | endmodule
218 | 
219 | module BrainfuckCoreTest;
220 | 	reg clk;
221 | 	reg reset;
222 | 
223 | 	wire ce, drce, dwce;
224 | 	wire [11:0] ia;
225 | 	wire [11:0] dra;
226 | 	wire [11:0] dwa;
227 | 	wire [7:0] id;
228 | 	wire [7:0] drd;
229 | 	wire [7:0] dwq;
230 | 	wire cack, cwre;
231 | 	reg  crda, cbsy;
232 | 	reg  [7:0] cd;
233 | 	wire [7:0] cq;
234 | 
235 | 	BrainfuckCore uut (
236 | 		.clk(clk),
237 | 		.reset(reset),
238 | 
239 | 		.ice(ice),
240 | 		.ia(ia),
241 | 		.id(id),
242 | 
243 | 		.drce(drce),
244 | 		.dra(dra),
245 | 		.drd(drd),
246 | 
247 | 		.dwce(dwce),
248 | 		.dwa(dwa),
249 | 		.dwq(dwq),
250 | 
251 | 		.cd(cd),
252 | 		.crda(crda),
253 | 		.cack(cack),
254 | 
255 | 		.cq(cq),
256 | 		.cwre(cwre),
257 | 		.cbsy(cbsy)
258 | 	);
259 | 
260 | 	IROM irom (
261 | 		.clk(clk),
262 | 		.ce(ice),
263 | 		.a(ia),
264 | 		.q(id)
265 | 	);
266 | 
267 | 	DRAM dram (
268 | 		.clk(clk),
269 | 		.rce(drce),
270 | 		.ra(dra),
271 | 		.rq(drd),
272 | 		.wce(dwce),
273 | 		.wa(dwa),
274 | 		.wd(dwq)
275 | 	);
276 | 
277 | 	initial begin
278 | 		clk = 0;
279 | 		reset = 0;
280 | 		crda = 0;
281 | 
282 | 		`reset
283 | 
284 | 		#161; crda = 1; cd = 8'h42;
285 | 		#20; cd = 8'h43;
286 | 		#20; crda = 0; cd = 0;
287 | 	end
288 | 
289 | 	always begin
290 | 		`step
291 | 	end
292 | 
293 | 	reg [1:0] uart_wait = 2'b00;
294 | 	always @(posedge clk) begin
295 | 		if (cwre) begin
296 | 			$write("%c", cq);
297 | 			cbsy      <= 1'b1;
298 | 			uart_wait <= 2'b11;
299 | 		end else begin
300 | 			if (uart_wait)
301 | 				uart_wait <= uart_wait - 1;
302 | 			else
303 | 				cbsy   <= 1'b0;
304 | 		end
305 | 	end
306 | 
307 | endmodule
308 | 


--------------------------------------------------------------------------------
/verilog/Common.tf:
--------------------------------------------------------------------------------
1 | `define reset  reset = 1; `step `step reset = 0; #20;
2 | `define step	clk = 1; #10; clk = 0; #10;


--------------------------------------------------------------------------------
/verilog/Constants.v:
--------------------------------------------------------------------------------
 1 | `define OPCODE_MSB   7
 2 | 
 3 | `define OP_INCDP        0	// >
 4 | `define OP_DECDP        1	// <
 5 | `define OP_INC          2	// +
 6 | `define OP_DEC          3	// -
 7 | `define OP_OUT          4	// .
 8 | `define OP_IN           5	// ,
 9 | `define OP_LOOPBEGIN    6	// [
10 | `define OP_LOOPEND      7	// ]
11 | 


--------------------------------------------------------------------------------
/verilog/Counter.v:
--------------------------------------------------------------------------------
 1 | module Counter (
 2 |    clk,
 3 |    reset,
 4 |    ce,
 5 |    d,
 6 |    q,
 7 |    load,
 8 |    down
 9 | );
10 | 
11 | 	parameter WIDTH = 8;
12 | 
13 | 	input                    clk;
14 | 	input                    reset;
15 | 	input                    ce;
16 | 	input      [WIDTH - 1:0] d;
17 | 	output reg [WIDTH - 1:0] q;
18 | 	input                    load;
19 | 	input                    down;
20 | 
21 | 	always @(posedge clk) begin
22 | 		if (reset)
23 | 			q <= 0;
24 | 		else if (ce) begin
25 | 			if (load)
26 | 				q <= d;
27 | 			else if(down)
28 | 				q <= q - 1;
29 | 			else /* !load && !down */
30 | 				q <= q + 1;
31 | 		end
32 | 	end
33 | 
34 | endmodule
35 | 


--------------------------------------------------------------------------------
/verilog/DRAM.v:
--------------------------------------------------------------------------------
 1 | module DRAM (
 2 | 	clk,
 3 | 	rce,
 4 | 	ra,
 5 | 	rq,
 6 | 	wce,
 7 | 	wa,
 8 | 	wd
 9 | );
10 | 
11 | 	parameter D_WIDTH =  8;
12 | 	parameter A_WIDTH =  12;
13 | 	parameter A_DEPTH = (1 << A_WIDTH);
14 | 
15 | 	input  clk;
16 | 
17 | 	input                      rce;
18 | 	input      [A_WIDTH - 1:0] ra;
19 | 	output reg [D_WIDTH - 1:0] rq;
20 | 
21 | 	input                      wce;
22 | 	input      [A_WIDTH - 1:0] wa;
23 | 	input      [D_WIDTH - 1:0] wd;
24 | 
25 | 	reg        [D_WIDTH - 1:0] memory[0:A_DEPTH - 1];
26 | 
27 | 	always @(posedge clk) begin
28 | 		if (rce)
29 | 			rq <= memory[ra];
30 | 
31 | 		if (wce)
32 | 			memory[wa] <= wd;
33 | 	end
34 | 
35 | 	integer i;
36 | 	initial
37 | 	begin
38 | 		for(i = 0; i < A_DEPTH; i = i + 1)
39 | 			memory[i] = 0;
40 | 	end
41 | 
42 | endmodule
43 | 


--------------------------------------------------------------------------------
/verilog/IROM.v:
--------------------------------------------------------------------------------
 1 | module IROM (
 2 | 	clk,
 3 | 	ce,
 4 | 	a,
 5 | 	q
 6 | );
 7 | 
 8 | 	parameter D_WIDTH =  8;
 9 | 	parameter A_WIDTH =  12;
10 | 	parameter A_DEPTH = (1 << A_WIDTH);
11 | 
12 | 	input  clk;
13 | 	input  ce;
14 | 
15 | 	input      [A_WIDTH - 1:0] a;
16 | 	output reg [D_WIDTH - 1:0] q;
17 | 
18 | 	reg        [D_WIDTH - 1:0] memory[0:A_DEPTH - 1];
19 | 
20 | 	always @(posedge clk) begin
21 | 		if(ce)
22 | 			q <= memory[a];
23 | 	end
24 | 
25 | 	integer i;
26 | 	initial
27 | 	begin
28 | 		for(i = 0; i < A_DEPTH; i = i + 1)
29 | 			memory[i] = 0;
30 | 
31 | 		$readmemh("irom.h", memory);
32 | 	end
33 | 
34 | endmodule
35 | 


--------------------------------------------------------------------------------
/verilog/Stack.v:
--------------------------------------------------------------------------------
 1 | module Stack (
 2 | 	clk,
 3 | 	reset,
 4 | 	q,
 5 | 	d,
 6 | 	push,
 7 | 	pop,
 8 | );
 9 | 
10 | 	parameter WIDTH = 11;
11 | 	parameter DEPTH = 7;
12 | 
13 | 	input                    clk;
14 | 	input                    reset;
15 | 	input      [WIDTH - 1:0] d;
16 | 	output reg [WIDTH - 1:0] q;
17 | 	input                    push;
18 | 	input                    pop;
19 | 
20 | 	reg [DEPTH - 1:0] ptr;
21 | 	reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
22 | 
23 | 	always @(posedge clk) begin
24 | 		if (reset)
25 | 			ptr <= 0;
26 | 		else if (push)
27 | 			ptr <= ptr + 1;
28 | 		else if (pop)
29 | 			ptr <= ptr - 1;
30 | 	end
31 | 
32 | 	always @(posedge clk) begin
33 | 		if (push || pop) begin
34 | 			if(push)
35 | 				stack[ptr] <= q;
36 | 
37 | 			q <= stack[ptr - 1];
38 | 		end
39 | 	end
40 | 
41 | endmodule


--------------------------------------------------------------------------------
/verilog/StageExecute.v:
--------------------------------------------------------------------------------
  1 | `include "Constants.v"
  2 | 
  3 | module StageExecute (
  4 | 	clk,
  5 | 	reset,
  6 | 
  7 | 	dp,
  8 | 	dp_ce,
  9 | 	dp_down,
 10 | 
 11 | 	dp_cache,
 12 | 
 13 | 	dce,
 14 | 	da,
 15 | 	dd,
 16 | 
 17 | 	cd,
 18 | 	crda,
 19 | 	cack,
 20 | 
 21 | 	a,
 22 | 
 23 | 	operation_in,
 24 | 	ack_in,
 25 | 
 26 | 	operation,
 27 | 	ack
 28 | );
 29 | 
 30 | 	parameter A_WIDTH = 12;
 31 | 	parameter D_WIDTH = 8;
 32 | 
 33 | 	input clk;
 34 | 	input reset;
 35 | 
 36 | 	input      [A_WIDTH - 1:0] dp;
 37 | 	output                     dp_ce;
 38 | 	output                     dp_down;
 39 | 
 40 | 	output                     dce;
 41 | 	output     [A_WIDTH - 1:0] da;
 42 | 	input      [D_WIDTH - 1:0] dd;
 43 | 
 44 | 	input                [7:0] cd;
 45 | 	input                      crda;
 46 | 	output                     cack;
 47 | 
 48 | 	output reg [D_WIDTH - 1:0] a;
 49 | 
 50 | 	input      [`OPCODE_MSB:0] operation_in;
 51 | 	output     ack;
 52 | 
 53 | 	output reg [`OPCODE_MSB:0] operation;
 54 | 	input      ack_in;
 55 | 
 56 | 	reg prefetched;
 57 | 
 58 | 	/*
 59 | 	 * Data pointer manipulation
 60 | 	 */
 61 | 	assign dp_ce   = ack_in && (operation_in[`OP_INCDP] || operation_in[`OP_DECDP]);
 62 | 	assign dp_down = ack_in &&  operation_in[`OP_DECDP];
 63 | 
 64 | 	output reg [A_WIDTH - 1:0] dp_cache;
 65 | 
 66 | 	/*
 67 | 	 * RAW hazard handling: register forwarding
 68 | 	 */
 69 | 	wire dirty_datum;
 70 | 	assign dirty_datum = operation[`OP_INC] || operation[`OP_DEC] ||
 71 | 				operation[`OP_IN] ||
 72 | 				/* These do not make change the datum. It is an optimization: *
 73 | 				 * memfetch costs 2 cycles, and regforward only one.          */
 74 | 				operation[`OP_LOOPBEGIN] || operation[`OP_LOOPEND];
 75 | 
 76 | 	wire do_mem_fetch, do_reg_forward;
 77 | 
 78 | 	assign do_mem_fetch   = need_fetch_mem && !dirty_datum;
 79 | 	assign do_reg_forward = need_fetch_mem && dirty_datum;
 80 | 
 81 | 	/*
 82 | 	 * Reading from DRAM
 83 | 	 */
 84 | 	wire need_fetch_mem;
 85 | 	assign need_fetch_mem = (operation_in[`OP_INC] || operation_in[`OP_DEC] ||
 86 | 					operation_in[`OP_OUT] || operation_in[`OP_LOOPBEGIN] ||
 87 | 					operation_in[`OP_LOOPEND]);
 88 | 
 89 | 	assign da  = dp;
 90 | 	assign dce = do_mem_fetch;
 91 | 
 92 | 	wire   [D_WIDTH - 1:0] data_input;
 93 | 	assign                 data_input = do_reg_forward ? a : dd;
 94 | 
 95 | 	assign datum_ready = (do_mem_fetch && prefetched) || do_reg_forward;
 96 | 
 97 | 	/*
 98 | 	 * Reading from EXT
 99 | 	 */
100 | 	wire need_fetch_ext;
101 | 	assign need_fetch_ext = operation_in[`OP_IN];
102 | 
103 | 	assign cack = crda && need_fetch_ext;
104 | 
105 | 	/*
106 | 	 * Wait states
107 | 	 */
108 | 	wire ext_wait;
109 | 	assign ext_wait = (need_fetch_ext && !crda) || (do_mem_fetch && !prefetched);
110 | 
111 | 	/*
112 | 	 * ACKing the previous stage
113 | 	 */
114 | 	assign ack = ack_in && !ext_wait;
115 | 
116 | 	always @(posedge clk) begin
117 | 		if (reset)
118 | 			prefetched <= 0;
119 | 		else
120 | 			prefetched <= do_mem_fetch;
121 | 	end
122 | 
123 | 	always @(posedge clk) begin
124 | 		if (reset) begin
125 | 			operation  <= 0;
126 | 
127 | 			dp_cache   <= 0;
128 | 			a          <= 0;
129 | 		end else begin
130 | 			dp_cache   <= dp;
131 | 
132 | 			if (ack_in && ext_wait) begin
133 | 				operation <= 0; /* Bubble */
134 | 				a         <= 0;
135 | 			end else if(ack_in) begin
136 | 				operation <= operation_in;
137 | 
138 | 				if (datum_ready)
139 | 					if (operation_in[`OP_INC])
140 | 						a   <= data_input + 1;
141 | 					else if (operation_in[`OP_DEC])
142 | 						a   <= data_input - 1;
143 | 					else
144 | 						a   <= data_input;
145 | 				else if (need_fetch_ext && crda)
146 | 					a      <= cd;
147 | 				else
148 | 					a      <= 0;
149 | 			end
150 | 		end
151 | 	end
152 | 
153 | endmodule
154 | 


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/verilog/StageIDecode.v:
--------------------------------------------------------------------------------
 1 | `include "Constants.v"
 2 | 
 3 | module StageIDecode (
 4 | 	clk,
 5 | 	reset,
 6 | 
 7 | 	opcode_in,
 8 | 	ack,
 9 | 
10 | 	operation,
11 | 	ack_in
12 | );
13 | 
14 | 	input clk;
15 | 	input reset;
16 | 
17 | 	input                [7:0] opcode_in;
18 | 	output                     ack;
19 | 
20 | 	output reg [`OPCODE_MSB:0] operation;
21 | 	input                      ack_in;
22 | 
23 | 	assign ack = ack_in;
24 | 
25 | 	always @(posedge clk) begin
26 | 		if (reset) begin
27 | 			operation <= 0;
28 | 		end else begin
29 | 			if (ack_in) begin
30 | 				case (opcode_in)
31 | 					8'h3E:   operation <= 8'b0000_0001;
32 | 					8'h3C:   operation <= 8'b0000_0010;
33 | 					8'h2B:   operation <= 8'b0000_0100;
34 | 					8'h2D:   operation <= 8'b0000_1000;
35 | 					8'h2E:   operation <= 8'b0001_0000;
36 | 					8'h2C:   operation <= 8'b0010_0000;
37 | 					8'h5B:   operation <= 8'b0100_0000;
38 | 					8'h5D:   operation <= 8'b1000_0000;
39 | 
40 | 					default: operation <= 8'b0000_0000;
41 | 				endcase
42 | 			end
43 | 		end
44 | 	end
45 | 
46 | endmodule
47 | 


--------------------------------------------------------------------------------
/verilog/StageIFetch.v:
--------------------------------------------------------------------------------
 1 | module StageIFetch (
 2 | 	clk,
 3 | 	reset,
 4 | 
 5 | 	pc,
 6 | 
 7 | 	ice,
 8 | 	ia,
 9 | 	id,
10 | 
11 | 	step_pc,
12 | 
13 | 	opcode,
14 | 	ack_in
15 | );
16 | 
17 | 	parameter A_WIDTH = 12;
18 | 	parameter D_WIDTH = 8;
19 | 
20 | 	input clk;
21 | 	input reset;
22 | 
23 | 	input      [A_WIDTH - 1:0] pc;
24 | 
25 | 	output                     ice;
26 | 	output     [A_WIDTH - 1:0] ia;
27 | 	input      [D_WIDTH - 1:0] id;
28 | 
29 | 	output                     step_pc;
30 | 
31 | 	output reg [D_WIDTH - 1:0] opcode;
32 | 
33 | 	input                      ack_in;
34 | 
35 | 	assign ia  = pc;
36 | 	assign ice = !reset && ack_in;
37 | 
38 | 	/*
39 | 	 * step_pc=1 means that at the _next_ cycle PC will be
40 | 	 * increased. Thus, if we will do a successful fetch
41 | 	 * _now_, we should increase it _then_.
42 | 	 */
43 | 	assign step_pc = !reset && ack_in;
44 | 
45 | 	reg prefetched;
46 | 
47 | 	always @(posedge clk) begin
48 | 		if (reset) begin
49 | 			prefetched <= 0;
50 | 
51 | 			opcode     <= 0;
52 | 		end else begin
53 | 			prefetched <= 1'b1;
54 | 
55 | 			if (ack_in && prefetched)
56 | 				opcode <= id;
57 | 		end
58 | 	end
59 | 
60 | endmodule
61 | 


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/verilog/StageModify.v:
--------------------------------------------------------------------------------
 1 | `include "Constants.v"
 2 | 
 3 | module StageModify (
 4 | 	clk,
 5 | 	reset,
 6 | 
 7 | 	a_in,
 8 | 	a,
 9 | 
10 | 	operation_in,
11 | 	ack_in,
12 | 
13 | 	operation,
14 | 	ack
15 | );
16 | 
17 | 	parameter D_WIDTH = 8;
18 | 
19 | 	input clk;
20 | 	input reset;
21 | 
22 | 	input      [D_WIDTH - 1:0] a_in;
23 | 	output reg [D_WIDTH - 1:0] a;
24 | 
25 | 	input      [`OPCODE_MSB:0] operation_in;
26 | 	output     ack;
27 | 
28 | 	output reg [`OPCODE_MSB:0] operation;
29 | 	input      ack_in;
30 | 
31 | 	assign ack = ack_in;
32 | 
33 | 	always @(posedge clk) begin
34 | 		if (reset) begin
35 | 			operation <= 0;
36 | 
37 | 			a         <= 0;
38 | 		end else begin
39 | 			if (ack_in) begin
40 | 				operation <= operation_in;
41 | 
42 | 				if (operation_in[`OP_INC])
43 | 					a      <= a_in + 1;
44 | 				else if (operation_in[`OP_DEC])
45 | 					a      <= a_in - 1;
46 | 				else if (operation_in[`OP_IN] || operation_in[`OP_OUT])
47 | 					a      <= a_in;
48 | 				else
49 | 					a      <= 0;
50 | 			end
51 | 		end
52 | 	end
53 | 
54 | endmodule
55 | 


--------------------------------------------------------------------------------
/verilog/StageTemplate.v:
--------------------------------------------------------------------------------
 1 | `include "Constants.v"
 2 | 
 3 | module StageX (
 4 | 	clk,
 5 | 	reset,
 6 | 
 7 | 	operation_in,
 8 | 	ack_in,
 9 | 
10 | 	operation,
11 | 	ack,
12 | );
13 | 
14 | 	input clk;
15 | 	input reset;
16 | 
17 | 	input      [`OPCODE_MSB:0] operation_in;
18 | 	output reg ack;
19 | 
20 | 	output reg [`OPCODE_MSB:0] operation;
21 | 	input      ack_in;
22 | 
23 | 	assign ack = ack_in;
24 | 
25 | 	always @(posedge clk) begin
26 | 		if (reset) begin
27 | 			operation <= 0;
28 | 		end else begin
29 | 			if (ack_in) begin
30 | 				operation <= operation_in;
31 | 			end
32 | 		end
33 | 	end
34 | 
35 | endmodule
36 | 


--------------------------------------------------------------------------------
/verilog/StageWriteback.v:
--------------------------------------------------------------------------------
 1 | `include "Constants.v"
 2 | 
 3 | module StageWriteback (
 4 | 	clk,
 5 | 	reset,
 6 | 
 7 | 	dp,
 8 | 
 9 | 	dce,
10 | 	da,
11 | 	dq,
12 | 
13 | 	cq,
14 | 	cwre,
15 | 	cbsy,
16 | 
17 | 	a_in,
18 | 
19 | 	operation_in,
20 | 	ack_in,
21 | 
22 | 	operation,
23 | 	ack
24 | );
25 | 
26 | 	parameter A_WIDTH = 12;
27 | 	parameter D_WIDTH = 8;
28 | 
29 | 	input clk;
30 | 	input reset;
31 | 
32 | 	input      [A_WIDTH - 1:0] dp;
33 | 
34 | 	output                     dce;
35 | 	output     [A_WIDTH - 1:0] da;
36 | 	output     [D_WIDTH - 1:0] dq;
37 | 
38 | 	output               [7:0] cq;
39 | 	output                     cwre;
40 | 	input                      cbsy;
41 | 
42 | 	input      [D_WIDTH - 1:0] a_in;
43 | 
44 | 	input      [`OPCODE_MSB:0] operation_in;
45 | 	output                     ack;
46 | 
47 | 	output reg [`OPCODE_MSB:0] operation;
48 | 	input                      ack_in;
49 | 
50 | 	/*
51 | 	 * Writing to DRAM
52 | 	 */
53 | 	wire need_write_mem;
54 | 	assign need_write_mem = (operation_in[`OP_INC] || operation_in[`OP_DEC] ||
55 | 					operation_in[`OP_IN]);
56 | 
57 | 	assign da  = dp;
58 | 	assign dce = need_write_mem;
59 | 	assign dq  = a_in;
60 | 
61 | 	/*
62 | 	 * Writing to EXT
63 | 	 */
64 | 	wire need_write_ext;
65 | 	assign need_write_ext = operation_in[`OP_OUT];
66 | 
67 | 	assign cq   = a_in;
68 | 	assign cwre = !cbsy && need_write_ext;
69 | 
70 | 	wire ext_wait;
71 | 	assign ext_wait = need_write_ext && cbsy;
72 | 
73 | 	/*
74 | 	 * ACKing the previous stage
75 | 	 */
76 | 	assign ack = ack_in && !ext_wait;
77 | 
78 | 	always @(posedge clk) begin
79 | 		if (reset) begin
80 | 			operation <= 0;
81 | 		end else begin
82 | 			if (ack_in && !ext_wait)
83 | 				operation <= operation_in;
84 | 			else if (ack_in)
85 | 				operation <= 0; /* Bubble */
86 | 		end
87 | 	end
88 | 
89 | endmodule
90 | 


--------------------------------------------------------------------------------
/verilog/UART.v:
--------------------------------------------------------------------------------
 1 | module UART(
 2 | 	clk,
 3 | 	reset,
 4 | 	tx,
 5 | 	rx,
 6 | 	d,
 7 | 	q,
 8 | 	rda,
 9 | 	ack,
10 | 	bsy,
11 | 	wre
12 | );
13 | 
14 | 	input  clk;
15 | 	input  reset;
16 | 
17 | 	output tx;
18 | 	input  rx;
19 | 
20 | 	input       [7:0] d;
21 |    output reg        rda;
22 | 	input             ack;
23 | 
24 | 	output      [7:0] q;
25 |    output            bsy;
26 | 	input             wre;
27 | 
28 | 	parameter SYS_CLOCK = 50000000;
29 | 	parameter BAUD = 9600;
30 | 
31 | 	wire received;
32 | 
33 | 	osdvu #(
34 | 		.CLOCK_DIVIDE(SYS_CLOCK / (BAUD * 4))
35 | 	) uart (
36 | 		.clk(clk),
37 | 		.rst(reste),
38 | 		.rx(rx),
39 | 		.tx(tx),
40 | 		.transmit(wre),
41 | 		.tx_byte(d),
42 | 		.received(received),
43 | 		.rx_byte(q),
44 | 		.is_receiving(),
45 | 		.is_transmitting(bsy),
46 | 		.recv_error()
47 | 	);
48 | 
49 | 	always @(posedge clk) begin
50 | 		if(reset || ack)
51 | 			rda <= 1'b0;
52 | 		else if(received)
53 | 			rda <= 1'b1;
54 | 	end
55 | 
56 | endmodule
57 | 


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