├── .github ├── FUNDING.yml └── workflows │ └── BuildAndTest.yml ├── .gitignore ├── .gitmodules ├── .jvmopts ├── LICENSE.Apache ├── LICENSE.NPL ├── Makefile ├── README.md ├── doc ├── Configuration.md ├── Setup.md └── riftCore micro-architecture.png ├── project ├── build.properties └── plugins.sbt ├── src ├── docker │ ├── chisel5.do │ ├── dromajo.do │ ├── riscvtest.do │ ├── sbt.do │ ├── toolchain.do │ ├── verilator.do │ └── yosys.do ├── main │ └── scala │ │ ├── Config.scala │ │ ├── GF180SVPWM.scala │ │ ├── Parameters.scala │ │ ├── Sky130BLFSR.scala │ │ ├── axi │ │ ├── axi.scala │ │ └── axi_full_mem.scala │ │ ├── base │ │ ├── AgeMatrix.scala │ │ ├── CacheRAM.scala │ │ ├── Decoupled1toN.scala │ │ ├── Hash.scala │ │ ├── LRU.scala │ │ ├── MultiPortBuf.scala │ │ ├── MultiPortFifo.scala │ │ ├── PolicyMux.scala │ │ ├── RePort.scala │ │ ├── Sram.scala │ │ ├── Util.scala │ │ ├── XArbiter.scala │ │ └── ZipQueue.scala │ │ ├── rift2Chip │ │ ├── AClint.scala │ │ ├── Chiplink.scala │ │ ├── Debug │ │ │ ├── DM.scala │ │ │ ├── DMI.scala │ │ │ ├── DTM.scala │ │ │ ├── Debugger.scala │ │ │ ├── JTAG.scala │ │ │ ├── debugROM.scala │ │ │ └── sba.scala │ │ ├── Plic.scala │ │ ├── Rift2Chip.scala │ │ ├── Rift2Link.scala │ │ └── Rift2NoC.scala │ │ └── rift2Core │ │ ├── PreFetcher.scala │ │ ├── backend │ │ ├── Alu.scala │ │ ├── Bru.scala │ │ ├── Commit.scala │ │ ├── Csr.scala │ │ ├── Execute.scala │ │ ├── FPU │ │ │ ├── FAlu.scala │ │ │ ├── FIssue.scala │ │ │ ├── Float2Float.scala │ │ │ ├── Float2Int.scala │ │ │ ├── FloatDivSqrt.scala │ │ │ ├── FloatFma.scala │ │ │ └── Int2Float.scala │ │ ├── Fpu.scala │ │ ├── Issue.scala │ │ ├── LSU │ │ │ ├── Dcache.scala │ │ │ ├── DcacheStage.scala │ │ │ ├── IO_Lsu.scala │ │ │ ├── Lsu.scala │ │ │ ├── MissUnit.scala │ │ │ ├── ProbeUnit.scala │ │ │ ├── Store_queue.scala │ │ │ ├── Util.scala │ │ │ └── wrtieBackUnit.scala │ │ ├── Mul.scala │ │ ├── Regfiles.scala │ │ ├── Rename.scala │ │ └── WriteBack.scala │ │ ├── define │ │ ├── defVector.scala │ │ ├── frontend.scala │ │ └── riscv_isa.scala │ │ ├── diff.scala │ │ ├── frontend │ │ ├── BIM.scala │ │ ├── BTB.scala │ │ ├── Decoder.scala │ │ ├── IF1.scala │ │ ├── IF2.scala │ │ ├── IF3.scala │ │ ├── IF4.scala │ │ ├── RAS.scala │ │ ├── TAGE.scala │ │ └── uBTB.scala │ │ ├── privilege │ │ ├── CSRInfoTable.scala │ │ ├── CsrFiles.scala │ │ ├── CsrScoreBoard.scala │ │ ├── MMU.scala │ │ ├── PMP.scala │ │ ├── PTW.scala │ │ └── TLB.scala │ │ ├── rift2Core.scala │ │ └── vector │ │ ├── MultiplerAccumulater.scala │ │ ├── VDecode32.scala │ │ ├── VPU.scala │ │ ├── VRegfiles.scala │ │ ├── VecPreIssue.scala │ │ └── VecPreRename.scala ├── test │ └── scala │ │ ├── mem │ │ ├── tl_l2l3c_tb.bk │ │ └── tl_l3c_tb.bk │ │ └── rift2Core │ │ └── rift2Chip_tb.scala └── yosys │ └── area.ys └── tb ├── build └── .keep ├── ci ├── .keep └── vec │ └── testList.mk ├── compile ├── coremark │ ├── LICENSE │ ├── build-coremark.sh │ ├── coremark │ │ └── core_main.c │ └── riscv64-baremetal │ │ ├── core_portme.c │ │ ├── core_portme.h │ │ ├── core_portme.mak │ │ ├── crt.S │ │ └── syscalls.c └── riscv-tests │ ├── LICENSE │ ├── benchmarks │ ├── Makefile │ ├── common │ │ ├── crt.S │ │ └── syscalls.c │ └── dhrystone │ │ └── dhrystone_main.c │ ├── env │ ├── p │ │ └── riscv_test.h │ └── v │ │ ├── riscv_test.h │ │ └── vm.c │ └── isa │ └── Makefile ├── debugger ├── SimJTAG.cc ├── SimTop.v ├── remote_bitbang.cc ├── remote_bitbang.h ├── rift.lds ├── rift_test.py ├── sim_main.cpp └── test.cfg ├── sw ├── .gitignore ├── axi_gpio │ ├── gpio.c │ └── gpio.h ├── axi_timer │ ├── timer.c │ └── timer.h ├── axi_uart │ ├── uart.c │ └── uart.h ├── clint_Plic │ ├── Makefile │ ├── linker.lds │ ├── main.c │ └── startup.S ├── linker.lds └── src │ ├── main.c │ └── startup.S ├── verilator ├── SimLink.v ├── SimTop.v ├── diff.cpp ├── diff.h ├── dromajo.cpp ├── mdl_test │ ├── Reservation_top.cpp │ ├── Reservation_top.v │ ├── random_csr_req.v │ ├── random_op_rsl.v │ └── random_wb_ack.v ├── sim_main.cpp └── test.v └── vtb ├── SimJTAG.v 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