├── .github ├── FUNDING.yml └── workflows │ └── action.yml ├── .gitignore ├── LICENSE ├── README.md ├── RiftChip ├── SoC │ ├── Xbar_wrap.v │ ├── axi_ccm.v │ ├── axi_full_slv_sram.v │ ├── fxbar_wrap.v │ └── xilinx_IP │ │ └── axi_full_Xbar │ │ ├── axi_crossbar_v2_1_22_addr_arbiter_sasd.v │ │ ├── axi_crossbar_v2_1_22_addr_decoder.v │ │ ├── axi_crossbar_v2_1_22_axi_crossbar.v │ │ ├── axi_crossbar_v2_1_22_crossbar_sasd.v │ │ ├── axi_crossbar_v2_1_22_decerr_slave.v │ │ ├── axi_crossbar_v2_1_22_splitter.v │ │ ├── axi_crossbar_v2_1_vl_rfs.v │ │ ├── axi_data_fifo_v2_1_vl_rfs.v │ │ ├── axi_full_crossbar.v │ │ ├── axi_infrastructure_v1_1_0.vh │ │ ├── axi_infrastructure_v1_1_vl_rfs.v │ │ ├── axi_register_slice_v2_1_21_axic_register_slice.v │ │ ├── axi_register_slice_v2_1_vl_rfs.v │ │ ├── generic_baseblocks_v2_1_0_carry_and.v │ │ ├── generic_baseblocks_v2_1_0_comparator_static.v │ │ ├── generic_baseblocks_v2_1_0_mux_enc.v │ │ └── generic_baseblocks_v2_1_vl_rfs.v ├── axi │ ├── AXI BUS TEMPLE │ │ ├── axi4_full_master.v │ │ ├── axi4_full_slave.v │ │ ├── axi4_lite_master.v │ │ └── axi4_lite_slave.v │ ├── axi_full_mst.v │ ├── axi_full_slv.v │ ├── axi_lite_mst.v │ └── axi_lite_slv.v ├── debug │ ├── DM.v │ ├── DMI.v │ ├── DTM.v │ └── core_monitor.v ├── define.vh ├── element │ ├── gen_asymmetricFIFO.v │ ├── gen_bypassfifo.v │ ├── gen_counter.v │ ├── gen_csrreg.v │ ├── gen_dffr.v │ ├── gen_dffren.v │ ├── gen_dpdffren.v │ ├── gen_fifo.v │ ├── gen_ppbuff.v │ ├── gen_ringStack.v │ ├── gen_rsffr.v │ ├── gen_slffr.v │ ├── gen_sram.v │ ├── gen_suffr.v │ ├── gen_syn.v │ ├── lfsr.v │ └── lzp.v ├── riftChip.v └── riftCore │ ├── backEnd.v │ ├── backend │ ├── commit.v │ ├── csrFiles.v │ ├── dispatch.v │ ├── execute │ │ ├── alu.v │ │ ├── bru.v │ │ ├── csr.v │ │ ├── lsu.v │ │ └── mul.v │ ├── issue │ │ ├── alu_issue.v │ │ ├── bru_issue.v │ │ ├── csr_issue.v │ │ ├── issue_buffer.v │ │ ├── issue_fifo.v │ │ ├── lsu_issue.v │ │ └── mul_issue.v │ ├── phyRegister.v │ ├── regFiles.v │ ├── rename.v │ └── writeBack.v │ ├── cache │ ├── L2cache.v │ ├── L3cache.v │ ├── cache.v │ ├── cache_mem.v │ ├── dirty_block.v │ └── wt_block.v │ ├── frontEnd.v │ ├── frontend │ ├── branch_predict.v │ ├── decoder.v │ ├── decoder16.v │ ├── decoder32.v │ ├── iAlign.v │ ├── icache.v │ ├── iqueue.v │ ├── pcGenerate.v │ └── preDecode.v │ ├── instr_fifo.v │ └── riftCore.v ├── doc ├── Core Bus System.png ├── DFF.png ├── DFFen.png ├── FIFO.png ├── FPGA_implementation.png ├── RSFF.png ├── bpFIFO.png ├── branch_predict.png ├── front end.png ├── inner_bus_handshake.png ├── instrFIFO.png ├── out-of-order.png ├── paritymemory.png ├── pc_generate.png ├── rename.png ├── riftCore micro-architecture.png ├── ring_stack.png └── writeback.png ├── sw ├── .gitignore ├── axi_gpio │ ├── gpio.c │ └── gpio.h ├── axi_timer │ ├── timer.c │ └── timer.h ├── axi_uart │ ├── uart.c │ └── uart.h ├── compile.bat ├── createDownload.py ├── linker.lds └── src │ ├── main.c │ └── startup.S └── tb ├── CI.py ├── DS.py ├── build └── .keep ├── ci └── .keep ├── debuger.v ├── dhrystone.bat ├── dhrystone ├── LICENSE ├── Makefile ├── crt.S ├── dhrystone_main.c └── syscalls.c ├── isa └── Makefile ├── iverilog.vh ├── iverilogCompile.bat ├── module_test ├── axi_ccm_tb.v ├── axi_full_cache_tb.v ├── axi_full_l2l3c_tb.v ├── axi_full_l3c_tb.v ├── corssbar_tb.v ├── dcache_tb.v ├── div_tb.v ├── icache_tb.v ├── iverilogCompile.bat └── mem_access_tb.v ├── riftChip_CI.v ├── riftChip_DS.v ├── riftChip_TB.v └── waveAna.bat /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | github: [whutddk] 4 | patreon: # Replace with a single Patreon username 5 | open_collective: # Replace with a single Open Collective username 6 | ko_fi: # Replace with a single Ko-fi username 7 | tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel 8 | community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry 9 | liberapay: # Replace with a single Liberapay username 10 | issuehunt: # Replace with a single IssueHunt username 11 | otechie: # Replace with a single Otechie username 12 | lfx_crowdfunding: # Replace with a single LFX Crowdfunding project-name e.g., cloud-foundry 13 | custom: # Replace with up to 4 custom sponsorship URLs e.g., ['link1', 'link2'] 14 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Compiled Object files 5 | *.slo 6 | *.lo 7 | *.o 8 | *.obj 9 | 10 | # Precompiled Headers 11 | *.gch 12 | *.pch 13 | 14 | # Compiled Dynamic libraries 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files 20 | *.mod 21 | *.smod 22 | 23 | # Compiled Static libraries 24 | *.lai 25 | *.la 26 | *.a 27 | *.lib 28 | 29 | # Executables 30 | *.exe 31 | *.out 32 | *.app 33 | 34 | 35 | 36 | 37 | *.dump 38 | *.verilog 39 | *.vsdx 40 | tb/null 41 | *.iverilog 42 | 43 | tb/build/* 44 | tb/build/.keep 45 | *.json 46 | tb/ci/* 47 | !tb/ci/MakeFile 48 | tb/ci/.keep 49 | *.vcd 50 | sw/download.tcl 51 | *.~vsdx 52 | .tags 53 | .tags_sorted_by_file 54 | -------------------------------------------------------------------------------- /RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_22_splitter.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: axi_crossbar_v2_1_22_splitter 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-03-09 10:52:20 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-09 10:52:42 8 | */ 9 | 10 | 11 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 12 | // -- 13 | // -- This file contains confidential and proprietary information 14 | // -- of Xilinx, Inc. and is protected under U.S. and 15 | // -- international copyright and other intellectual property 16 | // -- laws. 17 | // -- 18 | // -- DISCLAIMER 19 | // -- This disclaimer is not a license and does not grant any 20 | // -- rights to the materials distributed herewith. Except as 21 | // -- otherwise provided in a valid license issued to you by 22 | // -- Xilinx, and to the maximum extent permitted by applicable 23 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 24 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 25 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 26 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 27 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 28 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 29 | // -- including negligence, or under any other theory of 30 | // -- liability) for any loss or damage of any kind or nature 31 | // -- related to, arising under or in connection with these 32 | // -- materials, including for any direct, or any indirect, 33 | // -- special, incidental, or consequential loss or damage 34 | // -- (including loss of data, profits, goodwill, or any type of 35 | // -- loss or damage suffered as a result of any action brought 36 | // -- by a third party) even if such damage or loss was 37 | // -- reasonably foreseeable or Xilinx had been advised of the 38 | // -- possibility of the same. 39 | // -- 40 | // -- CRITICAL APPLICATIONS 41 | // -- Xilinx products are not designed or intended to be fail- 42 | // -- safe, or for use in any application requiring fail-safe 43 | // -- performance, such as life-support or safety devices or 44 | // -- systems, Class III medical devices, nuclear facilities, 45 | // -- applications related to the deployment of airbags, or any 46 | // -- other applications that could lead to death, personal 47 | // -- injury, or severe property or environmental damage 48 | // -- (individually and collectively, "Critical 49 | // -- Applications"). Customer assumes the sole risk and 50 | // -- liability of any use of Xilinx products in Critical 51 | // -- Applications, subject only to applicable laws and 52 | // -- regulations governing limitations on product liability. 53 | // -- 54 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 55 | // -- PART OF THIS FILE AT ALL TIMES. 56 | //----------------------------------------------------------------------------- 57 | // 58 | // Description: AXI Splitter 59 | // Each transfer received on the AXI handshake slave port is replicated onto 60 | // each of the master ports, and is completed back to the slave (S_READY) 61 | // once all master ports have completed. 62 | // 63 | // M_VALID is asserted combinatorially from S_VALID assertion. 64 | // Each M_VALID is masked off beginning the cycle after each M_READY is 65 | // received (if S_READY remains low) until the cycle after both S_VALID 66 | // and S_READY are asserted. 67 | // S_READY is asserted combinatorially when the last (or all) of the M_READY 68 | // inputs have been received. 69 | // If all M_READYs are asserted when S_VALID is asserted, back-to-back 70 | // handshakes can occur without bubble cycles. 71 | // 72 | // Verilog-standard: Verilog 2001 73 | //-------------------------------------------------------------------------- 74 | // 75 | // Structure: 76 | // splitter 77 | // 78 | //-------------------------------------------------------------------------- 79 | `timescale 1ps/1ps 80 | 81 | module axi_crossbar_v2_1_22_splitter # 82 | ( 83 | parameter integer C_NUM_M = 2 // Number of master ports = [2:16] 84 | ) 85 | ( 86 | // Global Signals 87 | input wire ACLK, 88 | input wire ARESET, 89 | // Slave Port 90 | input wire S_VALID, 91 | output wire S_READY, 92 | // Master Ports 93 | output wire [C_NUM_M-1:0] M_VALID, 94 | input wire [C_NUM_M-1:0] M_READY 95 | ); 96 | 97 | reg [C_NUM_M-1:0] m_ready_d = 0; 98 | wire s_ready_i; 99 | wire [C_NUM_M-1:0] m_valid_i; 100 | 101 | always @(posedge ACLK) begin 102 | if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}}; 103 | else m_ready_d <= m_ready_d | (m_valid_i & M_READY); 104 | end 105 | 106 | assign s_ready_i = &(m_ready_d | M_READY); 107 | assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d; 108 | assign M_VALID = m_valid_i; 109 | assign S_READY = s_ready_i; 110 | 111 | endmodule 112 | 113 | -------------------------------------------------------------------------------- /RiftChip/SoC/xilinx_IP/axi_full_Xbar/generic_baseblocks_v2_1_0_carry_and.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: generic_baseblocks_v2_1_0_carry_and 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-03-09 11:00:58 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-09 11:01:12 8 | */ 9 | 10 | // -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. 11 | // -- 12 | // -- This file contains confidential and proprietary information 13 | // -- of Xilinx, Inc. and is protected under U.S. and 14 | // -- international copyright and other intellectual property 15 | // -- laws. 16 | // -- 17 | // -- DISCLAIMER 18 | // -- This disclaimer is not a license and does not grant any 19 | // -- rights to the materials distributed herewith. Except as 20 | // -- otherwise provided in a valid license issued to you by 21 | // -- Xilinx, and to the maximum extent permitted by applicable 22 | // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 23 | // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 24 | // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 25 | // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 26 | // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 27 | // -- (2) Xilinx shall not be liable (whether in contract or tort, 28 | // -- including negligence, or under any other theory of 29 | // -- liability) for any loss or damage of any kind or nature 30 | // -- related to, arising under or in connection with these 31 | // -- materials, including for any direct, or any indirect, 32 | // -- special, incidental, or consequential loss or damage 33 | // -- (including loss of data, profits, goodwill, or any type of 34 | // -- loss or damage suffered as a result of any action brought 35 | // -- by a third party) even if such damage or loss was 36 | // -- reasonably foreseeable or Xilinx had been advised of the 37 | // -- possibility of the same. 38 | // -- 39 | // -- CRITICAL APPLICATIONS 40 | // -- Xilinx products are not designed or intended to be fail- 41 | // -- safe, or for use in any application requiring fail-safe 42 | // -- performance, such as life-support or safety devices or 43 | // -- systems, Class III medical devices, nuclear facilities, 44 | // -- applications related to the deployment of airbags, or any 45 | // -- other applications that could lead to death, personal 46 | // -- injury, or severe property or environmental damage 47 | // -- (individually and collectively, "Critical 48 | // -- Applications"). Customer assumes the sole risk and 49 | // -- liability of any use of Xilinx products in Critical 50 | // -- Applications, subject only to applicable laws and 51 | // -- regulations governing limitations on product liability. 52 | // -- 53 | // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 54 | // -- PART OF THIS FILE AT ALL TIMES. 55 | //----------------------------------------------------------------------------- 56 | // 57 | // Description: 58 | // Optimized AND with generic_baseblocks_v2_1_0_carry logic. 59 | // 60 | // Verilog-standard: Verilog 2001 61 | //-------------------------------------------------------------------------- 62 | // 63 | // Structure: 64 | // 65 | // 66 | //-------------------------------------------------------------------------- 67 | `timescale 1ps/1ps 68 | 69 | 70 | (* DowngradeIPIdentifiedWarnings="yes" *) 71 | module generic_baseblocks_v2_1_0_carry_and # 72 | ( 73 | parameter C_FAMILY = "virtex6" 74 | // FPGA Family. Current version: virtex6 or spartan6. 75 | ) 76 | ( 77 | input wire CIN, 78 | input wire S, 79 | output wire COUT 80 | ); 81 | 82 | 83 | ///////////////////////////////////////////////////////////////////////////// 84 | // Variables for generating parameter controlled instances. 85 | ///////////////////////////////////////////////////////////////////////////// 86 | 87 | 88 | ///////////////////////////////////////////////////////////////////////////// 89 | // Local params 90 | ///////////////////////////////////////////////////////////////////////////// 91 | 92 | 93 | ///////////////////////////////////////////////////////////////////////////// 94 | // Functions 95 | ///////////////////////////////////////////////////////////////////////////// 96 | 97 | 98 | ///////////////////////////////////////////////////////////////////////////// 99 | // Internal signals 100 | ///////////////////////////////////////////////////////////////////////////// 101 | 102 | 103 | ///////////////////////////////////////////////////////////////////////////// 104 | // Instantiate or use RTL code 105 | ///////////////////////////////////////////////////////////////////////////// 106 | 107 | generate 108 | if ( C_FAMILY == "rtl" ) begin : USE_RTL 109 | assign COUT = CIN & S; 110 | 111 | end else begin : USE_FPGA 112 | MUXCY and_inst 113 | ( 114 | .O (COUT), 115 | .CI (CIN), 116 | .DI (1'b0), 117 | .S (S) 118 | ); 119 | 120 | end 121 | endgenerate 122 | 123 | 124 | endmodule 125 | 126 | 127 | -------------------------------------------------------------------------------- /RiftChip/axi/axi_lite_mst.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: axi_lite_mst 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-14 17:08:41 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-15 15:14:35 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | 30 | 31 | 32 | module axi_lite_mst 33 | ( 34 | output ERROR, 35 | 36 | output [63:0] M_AXI_AWADDR, 37 | output [2:0] M_AXI_AWPROT, 38 | output M_AXI_AWVALID, 39 | input M_AXI_AWREADY, 40 | 41 | output [63:0] M_AXI_WDATA, 42 | output [7:0] M_AXI_WSTRB, 43 | output M_AXI_WVALID, 44 | input M_AXI_WREADY, 45 | 46 | input [1:0] M_AXI_BRESP, 47 | input M_AXI_BVALID, 48 | output M_AXI_BREADY, 49 | 50 | output [63:0] M_AXI_ARADDR, 51 | output [2:0] M_AXI_ARPROT, 52 | output M_AXI_ARVALID, 53 | input M_AXI_ARREADY, 54 | 55 | input [63:0] M_AXI_RDATA, 56 | input [1:0] M_AXI_RRESP, 57 | input M_AXI_RVALID, 58 | output M_AXI_RREADY, 59 | 60 | input CLK, 61 | input RSTn 62 | ); 63 | 64 | wire axi_awvalid_set, axi_awvalid_rst, axi_awvalid_qout; 65 | wire axi_wvalid_set, axi_wvalid_rst, axi_wvalid_qout; 66 | wire axi_bready_set, axi_bready_rst, axi_bready_qout; 67 | 68 | wire axi_arvalid_set, axi_arvalid_rst, axi_arvalid_qout; 69 | wire axi_rready_set, axi_rready_rst, axi_rready_qout; 70 | 71 | wire write_resp_error, read_resp_error; 72 | 73 | 74 | assign write_resp_error = (axi_bready_qout & M_AXI_BVALID & M_AXI_BRESP[1]); 75 | assign read_resp_error = (axi_rready_qout & M_AXI_RVALID & M_AXI_RRESP[1]); 76 | assign ERROR = write_resp_error | read_resp_error; 77 | 78 | assign M_AXI_AWADDR = ; 79 | assign M_AXI_WDATA = ; 80 | assign M_AXI_AWPROT = 3'b000; 81 | assign M_AXI_AWVALID = axi_awvalid_qout; 82 | 83 | assign M_AXI_WVALID = axi_wvalid_qout; 84 | assign M_AXI_WSTRB = ; 85 | 86 | assign M_AXI_BREADY = axi_bready_qout; 87 | assign M_AXI_ARADDR = ; 88 | assign M_AXI_ARVALID = axi_arvalid_qout; 89 | assign M_AXI_ARPROT = 3'b001; 90 | assign M_AXI_RREADY = axi_rready_qout; 91 | 92 | 93 | 94 | assign axi_awvalid_set = ; 95 | assign axi_awvalid_rst = ~axi_awvalid_set & (M_AXI_AWREADY & axi_awvalid_qout); 96 | assign axi_wvalid_set = ; 97 | assign axi_wvalid_rst = ~axi_wvalid_set & (M_AXI_WREADY & axi_wvalid_qout); 98 | assign axi_bready_set = M_AXI_BVALID & ~axi_bready_qout; 99 | assign axi_bready_rst = axi_bready_qout; 100 | 101 | gen_rsffr # (.DW(1)) axi_awvalid_rsffr (.set_in(axi_awvalid_set), .rst_in(axi_awvalid_rst), .qout(axi_awvalid_qout), .CLK(CLK), .RSTn(RSTn)); 102 | gen_rsffr # (.DW(1)) axi_wvalid_rsffr (.set_in(axi_wvalid_set), .rst_in(axi_wvalid_rst), .qout(axi_wvalid_qout), .CLK(CLK), .RSTn(RSTn)); 103 | gen_rsffr # (.DW(1)) axi_bready_rsffr (.set_in(axi_bready_set), .rst_in(axi_bready_rst), .qout(axi_bready_qout), .CLK(CLK), .RSTn(RSTn)); 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | assign axi_arvalid_set = ; 113 | assign axi_arvalid_rst = ~axi_arvalid_set & (M_AXI_ARREADY & axi_arvalid_qout); 114 | assign axi_rready_set = M_AXI_RVALID & ~axi_rready_qout; 115 | assign axi_rready_rst = axi_rready_qout; 116 | 117 | 118 | gen_rsffr # (.DW(1)) axi_arvalid_rsffr (.set_in(axi_arvalid_set), .rst_in(axi_arvalid_rst), .qout(axi_arvalid_qout), .CLK(CLK), .RSTn(RSTn)); 119 | gen_rsffr # (.DW(1)) axi_rready_rsffr (.set_in(axi_rready_set), .rst_in(axi_rready_rst), .qout(axi_rready_qout), .CLK(CLK), .RSTn(RSTn)); 120 | 121 | 122 | 123 | 124 | endmodule 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | -------------------------------------------------------------------------------- /RiftChip/debug/DMI.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: DMI 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-11-24 11:35:08 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2020-12-30 17:13:18 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2020 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | 30 | module DMI ( 31 | 32 | // master 33 | input [4:0] M_DTM_AXI_AWADDR, 34 | input [2:0] M_DTM_AXI_AWPROT, 35 | input M_DTM_AXI_AWVALID, 36 | output M_DTM_AXI_AWREADY, 37 | 38 | input [31:0] M_DTM_AXI_WDATA, 39 | input [3:0] M_DTM_AXI_WSTRB, 40 | input M_DTM_AXI_WVALID, 41 | output M_DTM_AXI_WREADY, 42 | 43 | output [1:0] M_DTM_AXI_BRESP, 44 | output M_DTM_AXI_BVALID, 45 | input M_DTM_AXI_BREADY, 46 | 47 | input [4:0] M_DTM_AXI_ARADDR, 48 | input [2:0] M_DTM_AXI_ARPROT, 49 | input M_DTM_AXI_ARVALID, 50 | output M_DTM_AXI_ARREADY, 51 | 52 | output [31:0] M_DTM_AXI_RDATA, 53 | output [1:0] M_DTM_AXI_RRESP, 54 | output M_DTM_AXI_RVALID, 55 | input M_DTM_AXI_RREADY, 56 | 57 | input TCK, 58 | input TRST, 59 | 60 | 61 | output [7:0] S_DM_AXI_AWADDR, 62 | output [2:0] S_DM_AXI_AWPROT, 63 | output S_DM_AXI_AWVALID, 64 | input S_DM_AXI_AWREADY, 65 | 66 | output [31:0] S_DM_AXI_WDATA, 67 | output [3:0] S_DM_AXI_WSTRB, 68 | output S_DM_AXI_WVALID, 69 | input S_DM_AXI_WREADY, 70 | 71 | input [1:0] S_DM_AXI_BRESP, 72 | input S_DM_AXI_BVALID, 73 | output S_DM_AXI_BREADY, 74 | 75 | output [7:0] S_DM_AXI_ARADDR, 76 | output [2:0] S_DM_AXI_ARPROT, 77 | output S_DM_AXI_ARVALID, 78 | input S_DM_AXI_ARREADY, 79 | 80 | input [31:0] S_DM_AXI_RDATA, 81 | input [1:0] S_DM_AXI_RRESP, 82 | input S_DM_AXI_RVALID, 83 | output S_DM_AXI_RREADY 84 | 85 | input CLK, 86 | input RSTn 87 | 88 | ); 89 | 90 | 91 | 92 | 93 | assign M_DTM_AXI_BRESP = S_DM_AXI_BRESP; 94 | 95 | assign M_DTM_AXI_RDATA = S_DM_AXI_RDATA; 96 | assign M_DTM_AXI_RRESP = S_DM_AXI_RRESP; 97 | 98 | assign S_DM_AXI_AWADDR = M_DTM_AXI_AWADDR; 99 | assign S_DM_AXI_AWPROT = M_DTM_AXI_AWPROT; 100 | 101 | assign S_DM_AXI_WDATA = M_DTM_AXI_WDATA; 102 | assign S_DM_AXI_WSTRB = M_DTM_AXI_WSTRB; 103 | 104 | assign S_DM_AXI_ARADDR = M_DTM_AXI_ARADDR; 105 | assign S_DM_AXI_ARPROT = M_DTM_AXI_ARPROT; 106 | 107 | 108 | gen_syn # ( .lever(3)) AWREADY ( .data_asyn(S_DM_AXI_AWREADY), .data_syn(M_DTM_AXI_AWREADY), .CLK(TCK), .RSTn(~TRST) ); 109 | gen_syn # ( .lever(3)) WREADY ( .data_asyn(S_DM_AXI_WREADY), .data_syn(M_DTM_AXI_WREADY), .CLK(TCK), .RSTn(~TRST) ); 110 | gen_syn # ( .lever(3)) BVALID ( .data_asyn(S_DM_AXI_BVALID), .data_syn(M_DTM_AXI_BVALID), .CLK(TCK), .RSTn(~TRST) ); 111 | gen_syn # ( .lever(3)) ARREADY ( .data_asyn(S_DM_AXI_ARREADY), .data_syn(M_DTM_AXI_ARREADY), .CLK(TCK), .RSTn(~TRST) ); 112 | gen_syn # ( .lever(3)) RVALID ( .data_asyn(S_DM_AXI_RVALID), .data_syn(M_DTM_AXI_RVALID), .CLK(TCK), .RSTn(~TRST) ); 113 | 114 | 115 | 116 | gen_syn # ( .lever(3)) AWVALID ( .data_asyn(M_DTM_AXI_AWVALID), .data_syn(S_DM_AXI_AWVALID), .CLK(CLK), .RSTn(RSTn) ); 117 | gen_syn # ( .lever(3)) WVALID ( .data_asyn(M_DTM_AXI_WVALID), .data_syn(S_DM_AXI_WVALID), .CLK(CLK), .RSTn(RSTn) ); 118 | gen_syn # ( .lever(3)) BREADY ( .data_asyn(M_DTM_AXI_BREADY), .data_syn(S_DM_AXI_BREADY), .CLK(CLK), .RSTn(RSTn) ); 119 | gen_syn # ( .lever(3)) ARVALID ( .data_asyn(M_DTM_AXI_ARVALID), .data_syn(S_DM_AXI_ARVALID), .CLK(CLK), .RSTn(RSTn) ); 120 | gen_syn # ( .lever(3)) RREADY ( .data_asyn(M_DTM_AXI_RREADY), .data_syn(S_DM_AXI_RREADY), .CLK(CLK), .RSTn(RSTn) ); 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | endmodule 132 | 133 | -------------------------------------------------------------------------------- /RiftChip/debug/core_monitor.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: core_monitor 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-11-26 19:01:43 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:41 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | 30 | module core_monitor ( 31 | input reqReset, 32 | output hasReset, 33 | 34 | input reqHalt, 35 | output isHalt, 36 | 37 | output isDebugMode, 38 | 39 | 40 | 41 | 42 | 43 | input [127:0] accessReg_arg, 44 | input [15:0] accessReg_addr, 45 | input accessReg_wen, 46 | output [127:0] accessReg_res, 47 | output accessReg_ready, 48 | input accessReg_valid, 49 | 50 | 51 | input quickAccess_valid, 52 | output isExpection, 53 | output quickAccess_ready, 54 | 55 | ); 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | endmodule 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /RiftChip/define.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: define 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-22 11:47:58 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2020-11-02 16:43:31 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `define RP 4 //rename depth 28 | `define RB $clog2(`RP) 29 | 30 | 31 | 32 | `define DECODE_INFO_DW (53+13+1+6+13+2+1+64+64+6+5+5+5) 33 | `define REORDER_INFO_DW (64+(5+`RB)+10) 34 | 35 | `define ALU_ISSUE_INFO_DW (30+64+6+64+(5+`RB)+(5+`RB)+(5+`RB)) 36 | `define ALU_ISSUE_INFO_DP 2 37 | `define ALU_EXEPARAM_DW (10+4+(5+`RB)+(5+`RB)+(5+`RB)+64+64) 38 | 39 | `define BRU_ISSUE_INFO_DW (8+1+64+64+(5+`RB)+(5+`RB)+(5+`RB)) 40 | `define BRU_ISSUE_INFO_DP 2 41 | `define BRU_EXEPARAM_DW (8+1+(5+`RB)+(5+`RB)+(5+`RB)+64+64) 42 | 43 | `define LSU_ISSUE_INFO_DW (13+64+(5+`RB)+(5+`RB)+(5+`RB)) 44 | `define LSU_ISSUE_INFO_DP 2 45 | `define LSU_EXEPARAM_DW (13+(5+`RB)+64+64) 46 | 47 | 48 | `define CSR_ISSUE_INFO_DW (6+64+12+(5+`RB)+(5+`RB)) 49 | `define CSR_ISSUE_INFO_DP 2 50 | `define CSR_EXEPARAM_DW (3+(5+`RB)+(5+`RB)+1+12) 51 | 52 | `define MUL_ISSUE_INFO_DW (13+(5+`RB)+(5+`RB)+(5+`RB)) 53 | `define MUL_ISSUE_INFO_DP 2 54 | `define MUL_EXEPARAM_DW `MUL_ISSUE_INFO_DW 55 | 56 | 57 | 58 | -------------------------------------------------------------------------------- /RiftChip/element/gen_asymmetricFIFO.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_asymmetricFIFO 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-08 19:22:16 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-09 13:26:05 8 | */ 9 | 10 | 11 | 12 | /* 13 | Copyright (c) 2020 - 2021 Ruige Lee 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | 31 | module gen_asymmetricFIFO # ( 32 | parameter DW = 64, 33 | parameter AW = 3, 34 | 35 | parameter WP = 4, 36 | parameter RP = 4 37 | 38 | 39 | ) ( 40 | 41 | 42 | input fifo_push, 43 | input fifo_pop, 44 | 45 | output fifo_empty, 46 | output fifo_full, 47 | 48 | input [DW*WP-1:0] data_w, 49 | output [DW*RP-1:0] data_r, 50 | 51 | 52 | input flush, 53 | input CLK, 54 | input RSTn 55 | ); 56 | 57 | localpara DP = 2**AW; 58 | localpara FN = (WP > RP) ? WP : RP; 59 | 60 | generate 61 | for ( genvar i = 0; i < FN; i = i + 1 ) begin 62 | 63 | gen_fifo # ( 64 | .DW(DW), 65 | .AW(AW) 66 | ) bank( 67 | 68 | input fifo_pop, 69 | input fifo_push, 70 | input [DW-1:0] data_push, 71 | 72 | output fifo_empty, 73 | output fifo_full, 74 | output [DW-1:0] data_pop, 75 | 76 | input flush, 77 | input CLK, 78 | input RSTn 79 | ); 80 | 81 | 82 | 83 | 84 | 85 | 86 | end 87 | endgenerate 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | wire [AW+1-1:0] read_addr_dnxt, read_addr_qout; 102 | wire [AW+1-1:0] write_addr_dnxt, write_addr_qout; 103 | wire [DP*DW-1:0] fifo_data_dnxt, fifo_data_qout; 104 | wire [DP-1:0] fifo_status_dnxt, fifo_status_qout; 105 | 106 | gen_dffr # (.DW(AW+1)) read_addr (.dnxt(read_addr_dnxt), .qout(read_addr_qout), .CLK(CLK), .RSTn(RSTn)); 107 | gen_dffr # (.DW(AW+1)) write_addr (.dnxt(write_addr_dnxt), .qout(write_addr_qout), .CLK(CLK), .RSTn(RSTn)); 108 | 109 | wire [WP-1:0] fifo_full_all; 110 | wire [RP-1:0] fifo_empty_all; 111 | 112 | // assign fifo_empty[0] = (read_addr_qout == write_addr_qout); 113 | // assign fifo_full[0] = (read_addr_qout[AW-1:0] == write_addr_qout[AW-1:0]) & (read_addr_qout[AW] != write_addr_qout[AW]); 114 | 115 | assign fifo_empty = | fifo_empty_all; 116 | assign fifo_full = | fifo_full_all; 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | generate 132 | for ( genvar i = 0 ; i < WP; i = i + 1 ) begin 133 | wire [AW+1-1:0] write_addr_pre = write_addr_qout + WP; 134 | assign fifo_full_all[WP] = (read_addr_qout[AW-1:0] == write_addr_pre[AW-1:0]) & (read_addr_qout[AW] != write_addr_pre[AW]); 135 | end 136 | endgenerate 137 | 138 | generate 139 | for ( genvar i = 0 ; i < RP; i = i + 1 ) begin 140 | wire [AW+1-1:0] read_addr_pre = read_addr_qout + RP; 141 | assign fifo_empty_all[RP] = ( read_addr_pre == write_addr_qout ); 142 | end 143 | endgenerate 144 | 145 | 146 | 147 | 148 | // generate 149 | // for ( genvar i = 0; i < DP; i = i + 1 ) begin 150 | // for ( genvar j = 0; j < WR; j = j + 1 ) bgein 151 | // assign fifo_data_dnxt[DW*i+:DW] = (fifo_push & ~fifo_full & (write_addr_qout[AW-1:0] == i) ) ? data_push : fifo_data_qout[DW*i+:DW]; 152 | 153 | 154 | // gen_dffr # (.DW(DW)) fifo_data (.dnxt(fifo_data_dnxt[DW*i+:DW]), .qout(fifo_data_qout[DW*i+:DW]), .CLK(CLK), .RSTn(RSTn)); 155 | // end 156 | // end 157 | 158 | 159 | 160 | 161 | // endgenerate 162 | 163 | 164 | 165 | 166 | // assign data_pop = fifo_data_qout[DW*read_addr_qout[AW-1:0]+:DW]; 167 | 168 | // assign read_addr_dnxt = flush ? ({(AW+1){1'b1}}) : (( fifo_pop & ~fifo_empty ) ? read_addr_qout + 'd1 : read_addr_qout); 169 | // assign write_addr_dnxt = flush ? ({(AW+1){1'b1}}) : (( fifo_push & ~fifo_full ) ? write_addr_qout + 'd1 : write_addr_qout); 170 | 171 | 172 | endmodule 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | -------------------------------------------------------------------------------- /RiftChip/element/gen_bypassfifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_bypassfifo 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-05 14:33:30 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-07 11:45:19 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | 28 | 29 | `timescale 1 ns / 1 ps 30 | 31 | //This module is used at where the data is not a pineline stage FF but may be stalled by pineline 32 | 33 | 34 | module gen_bypassfifo # 35 | ( 36 | parameter DW = 64 37 | ) 38 | ( 39 | input valid_i, 40 | input [DW-1:0] data_i, 41 | output ready_i, 42 | 43 | output valid_o, 44 | output [DW-1:0] data_o, 45 | input ready_o, 46 | 47 | input flush, 48 | input CLK, 49 | input RSTn 50 | ); 51 | 52 | wire fifo_empty; 53 | wire fifo_full; 54 | wire [DW-1:0] data_pop; 55 | 56 | 57 | 58 | 59 | wire isLoad_set; 60 | wire isLoad_rst; 61 | wire isLoad_qout; 62 | 63 | assign isLoad_set = valid_i & ~ready_o; 64 | assign isLoad_rst = (ready_o & ~fifo_empty) | flush; 65 | assign fifo_empty = ~isLoad_qout; 66 | assign fifo_full = isLoad_qout; 67 | gen_dffren # ( .DW(DW)) fifo_bypass ( .dnxt(data_i), .qout(data_pop), .en(isLoad_set), .CLK(CLK), .RSTn(RSTn)); 68 | gen_rsffr # ( .DW(1) ) isLoad ( .set_in(isLoad_set), .rst_in(isLoad_rst), .qout(isLoad_qout), .CLK(CLK), .RSTn(RSTn)); 69 | 70 | 71 | 72 | 73 | 74 | assign data_o = fifo_empty ? data_i : data_pop; 75 | assign ready_i = ~fifo_full | flush; 76 | assign valid_o = valid_i | ~fifo_empty; 77 | 78 | 79 | 80 | 81 | 82 | 83 | //ASSERT 84 | always @( posedge CLK ) begin 85 | if ( fifo_full & valid_i ) begin 86 | $display("Assert Fail at bypass fifo"); 87 | $finish; 88 | end 89 | end 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | endmodule 102 | 103 | 104 | 105 | 106 | 107 | -------------------------------------------------------------------------------- /RiftChip/element/gen_counter.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_counter 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-03-03 11:35:15 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-03 11:43:13 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | module gen_counter # 31 | ( 32 | parameter AW = 3 33 | ) 34 | ( 35 | 36 | input push, 37 | input pop, 38 | 39 | output empty, 40 | output full, 41 | 42 | output [AW-1:0] cnt, 43 | 44 | input flush, 45 | input CLK, 46 | input RSTn 47 | 48 | ); 49 | 50 | wire [AW+1-1:0] rdp_dnxt; 51 | wire [AW+1-1:0] rdp_qout; 52 | wire [AW+1-1:0] wrp_dnxt; 53 | wire [AW+1-1:0] wrp_qout; 54 | 55 | gen_dffr #( .DW(AW+1) ) rdp_dffr ( .dnxt(rdp_dnxt), .qout(rdp_qout), .CLK(CLK), .RSTn(RSTn)); 56 | gen_dffr #( .DW(AW+1) ) wrp_dffr ( .dnxt(wrp_dnxt), .qout(wrp_qout), .CLK(CLK), .RSTn(RSTn)); 57 | 58 | assign rdp_dnxt = flush ? {(AW+1){1'b0}}: (pop ? rdp_qout + 'd1 : rdp_qout); 59 | assign wrp_dnxt = flush ? {(AW+1){1'b0}}: (push ? wrp_qout + 'd1 : wrp_qout); 60 | 61 | assign empty = (rdpr_qout == wrp_qout); 62 | assign full = (rdp_qout[AW-1:0] == wrp_qout[AW-1:0]) & (rdpr_qout[AW] != wrp_qout[AW]); 63 | 64 | assign cnt = wrp_qout[AW-1:0] - rdp_qout[AW-1:0]; 65 | 66 | 67 | 68 | 69 | 70 | 71 | endmodule 72 | 73 | 74 | 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /RiftChip/element/gen_csrreg.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_csrreg 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-02-05 11:14:21 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-05 14:50:15 8 | */ 9 | 10 | 11 | 12 | /* 13 | Copyright (c) 2020 - 2021 Ruige Lee 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | 28 | 29 | 30 | `timescale 1 ns / 1 ps 31 | 32 | module gen_csrreg #( 33 | parameter DW = 64, 34 | parameter rstValue = {DW{1'b0}}, 35 | parameter CSRADDR = 12'b0 36 | ) 37 | ( 38 | 39 | input [DW-1:0] privi_data, 40 | input isPrivi, 41 | 42 | input [DW-1:0] csr_op, 43 | input [11:0] addr, 44 | input rw, 45 | input rs, 46 | input rc, 47 | 48 | output [DW-1:0] qout, 49 | 50 | input CLK, 51 | input RSTn 52 | ); 53 | 54 | 55 | wire enb; 56 | wire [DW-1:0] dnxtb; 57 | 58 | assign enb = (addr == CSRADDR) & (rw | rs | rc); 59 | assign dnxtb = ({DW{rw}} & csr_op) 60 | | ({DW{rs}} & ( qout | csr_op ) ) 61 | | ({DW{rc}} & ( qout & (~csr_op)) ); 62 | 63 | 64 | 65 | gen_dpdffren #( .DW(DW), .rstValue(rstValue) ) dpdffren 66 | ( 67 | .dnxta(privi_data), 68 | .ena(isPrivi), 69 | 70 | .dnxtb(dnxtb), 71 | .enb(enb), 72 | 73 | .qout(qout), 74 | 75 | .CLK(CLK), 76 | .RSTn(RSTn) 77 | ); 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | //ASSERT 86 | always @( posedge CLK ) begin 87 | if ( (rw & rs) | (rs & rc) | (rw & rc) ) begin 88 | $display("Assert Fail at gen_csrreg"); 89 | $finish; 90 | end 91 | end 92 | 93 | 94 | endmodule 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | -------------------------------------------------------------------------------- /RiftChip/element/gen_dffr.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_dffr 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-09-14 10:25:09 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-18 11:43:32 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module gen_dffr # ( 29 | parameter DW = 32, 30 | parameter rstValue = {DW{1'b0}} 31 | ) 32 | ( 33 | 34 | input [DW-1:0] dnxt, 35 | output [DW-1:0] qout, 36 | 37 | input CLK, 38 | input RSTn 39 | ); 40 | 41 | reg [DW-1:0] qout_r; 42 | 43 | always @(posedge CLK or negedge RSTn) begin 44 | if ( ~RSTn ) 45 | qout_r <= #1 rstValue; 46 | else 47 | qout_r <= #1 dnxt; 48 | end 49 | 50 | assign qout = qout_r; 51 | 52 | endmodule 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /RiftChip/element/gen_dffren.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_dffren 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-12-28 10:04:54 6 | * @Last Modified by: Ruige Lee 7 | <<<<<<< HEAD:element/gen_dffren.v 8 | * @Last Modified time: 2020-12-28 10:09:35 9 | ======= 10 | * @Last Modified time: 2021-01-03 12:04:22 11 | >>>>>>> master:core/debug/DMI.v 12 | */ 13 | 14 | 15 | /* 16 | Copyright (c) 2020 - 2021 Ruige Lee 17 | 18 | Licensed under the Apache License, Version 2.0 (the "License"); 19 | you may not use this file except in compliance with the License. 20 | You may obtain a copy of the License at 21 | 22 | http://www.apache.org/licenses/LICENSE-2.0 23 | 24 | Unless required by applicable law or agreed to in writing, software 25 | distributed under the License is distributed on an "AS IS" BASIS, 26 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27 | See the License for the specific language governing permissions and 28 | limitations under the License. 29 | */ 30 | 31 | `timescale 1 ns / 1 ps 32 | 33 | 34 | module gen_dffren # ( 35 | parameter DW = 32, 36 | parameter rstValue = {DW{1'b0}} 37 | ) 38 | ( 39 | 40 | input [DW-1:0] dnxt, 41 | output [DW-1:0] qout, 42 | input en, 43 | 44 | input CLK, 45 | input RSTn 46 | ); 47 | 48 | 49 | 50 | wire [DW-1:0] dffren_dnxt; 51 | wire [DW-1:0] dffren_qout; 52 | 53 | 54 | gen_dffr # ( .DW(DW), .rstValue(rstValue) ) dffren 55 | ( 56 | .dnxt(dffren_dnxt), 57 | .qout(dffren_qout), 58 | 59 | .CLK(CLK), 60 | .RSTn(RSTn) 61 | ); 62 | 63 | 64 | assign dffren_dnxt = en ? dnxt : dffren_qout; 65 | assign qout = dffren_qout; 66 | 67 | 68 | endmodule 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /RiftChip/element/gen_dpdffren.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_dpdffren 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-02-05 11:03:45 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-05 11:33:54 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | 31 | module gen_dpdffren #( 32 | parameter DW = 32, 33 | parameter rstValue = {DW{1'b0}} 34 | ) 35 | ( 36 | 37 | input [DW-1:0] dnxta, 38 | input ena, 39 | 40 | input [DW-1:0] dnxtb, 41 | input enb, 42 | 43 | output [DW-1:0] qout, 44 | 45 | input CLK, 46 | input RSTn 47 | ); 48 | 49 | wire en; 50 | wire [DW-1:0] dnxt; 51 | 52 | 53 | 54 | assign en = ena | enb; 55 | assign dnxt = {DW{ena}} & dnxta 56 | | 57 | {DW{(~ena)&enb}} & dnxtb; 58 | 59 | 60 | gen_dffren # ( .DW(DW), .rstValue(rstValue) ) dffren 61 | ( 62 | 63 | .dnxt(dnxt), 64 | .qout(qout), 65 | .en(en), 66 | 67 | .CLK(CLK), 68 | .RSTn(RSTn) 69 | ); 70 | 71 | 72 | 73 | 74 | endmodule 75 | 76 | 77 | -------------------------------------------------------------------------------- /RiftChip/element/gen_fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_fifo 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-30 17:55:22 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-03 10:59:58 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | 29 | module gen_fifo # ( 30 | parameter DW = 64, 31 | parameter AW = 3 32 | ) ( 33 | 34 | input fifo_pop, 35 | input fifo_push, 36 | input [DW-1:0] data_push, 37 | 38 | output fifo_empty, 39 | output fifo_full, 40 | output [DW-1:0] data_pop, 41 | 42 | output [AW+1-1:0] read_addr, 43 | output [AW+1-1:0] write_addr, 44 | 45 | output [(DW*(2**AW))-1:0] expose_o, 46 | output [((2**AW)-1):0] valid, 47 | 48 | input flush, 49 | input CLK, 50 | input RSTn 51 | ); 52 | 53 | localparam DP = 2**AW; 54 | 55 | 56 | wire [AW+1-1:0] read_addr_dnxt, read_addr_qout; 57 | wire [AW+1-1:0] write_addr_dnxt, write_addr_qout; 58 | wire [DP*DW-1:0] fifo_data_dnxt,fifo_data_qout; 59 | wire [DP-1:0] valid_set, valid_rst, valid_qout, valid_en; 60 | 61 | 62 | 63 | gen_dffr # (.DW(AW+1)) read_addr_dffr (.dnxt(read_addr_dnxt), .qout(read_addr_qout), .CLK(CLK), .RSTn(RSTn)); 64 | gen_dffr # (.DW(AW+1)) write_addr_dffr (.dnxt(write_addr_dnxt), .qout(write_addr_qout), .CLK(CLK), .RSTn(RSTn)); 65 | 66 | assign fifo_empty = (read_addr_qout == write_addr_qout); 67 | assign fifo_full = (read_addr_qout[AW-1:0] == write_addr_qout[AW-1:0]) & (read_addr_qout[AW] != write_addr_qout[AW]); 68 | assign read_addr = read_addr_qout; 69 | assign write_addr = write_addr_qout; 70 | 71 | generate 72 | for ( genvar i = 0; i < DP; i = i + 1 ) begin 73 | assign fifo_data_dnxt[DW*i+:DW] = (fifo_push & ~fifo_full & (write_addr_qout[AW-1:0] == i) ) ? data_push : fifo_data_qout[DW*i+:DW]; 74 | 75 | 76 | gen_dffr # (.DW(DW)) fifo_data_dffr (.dnxt(fifo_data_dnxt[DW*i+:DW]), .qout(fifo_data_qout[DW*i+:DW]), .CLK(CLK), .RSTn(RSTn)); 77 | 78 | end 79 | 80 | 81 | 82 | 83 | endgenerate 84 | 85 | 86 | 87 | 88 | assign data_pop = fifo_data_qout[DW*read_addr_qout[AW-1:0]+:DW]; 89 | 90 | assign read_addr_dnxt = flush ? ({(AW+1){1'b0}}) : (( fifo_pop & ~fifo_empty ) ? read_addr_qout + 'd1 : read_addr_qout); 91 | assign write_addr_dnxt = flush ? ({(AW+1){1'b0}}) : (( fifo_push & ~fifo_full ) ? write_addr_qout + 'd1 : write_addr_qout); 92 | 93 | 94 | assign expose_o = fifo_data_qout; 95 | generate 96 | for ( genvar dp = 0; dp < DP; dp = dp + 1 ) begin 97 | assign valid_set[dp] = (fifo_push & ~fifo_full) & ( dp == write_addr_qout[AW-1:0 ] ); 98 | assign valid_rst[dp] = ((fifo_pop & ~fifo_empty) & ( dp == read_addr_qout[AW-1:0 ] )) | flush; 99 | 100 | 101 | gen_rsffr #(.DW(1)) valid_rsffr (.set_in(valid_set[dp]), .rst_in(valid_rst[dp]), .qout(valid_qout[dp]), .CLK(CLK), .RSTn(RSTn)); 102 | end 103 | endgenerate 104 | 105 | endmodule 106 | 107 | 108 | 109 | -------------------------------------------------------------------------------- /RiftChip/element/gen_ppbuff.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_ppbuff 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-02-22 17:07:27 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-25 11:30:59 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | 29 | module gen_ppbuff # 30 | ( 31 | parameter DW = 100, 32 | parameter DP = 8 33 | ) 34 | ( 35 | input pop, 36 | input push, 37 | input [$clog2(DP)-1:0] index, 38 | 39 | input [ DW - 1 : 0] info_i, 40 | output [ DW*DP - 1 : 0] info_o, 41 | 42 | output empty, 43 | output full, 44 | output [DP - 1 : 0] valid, 45 | 46 | input flush, 47 | input CLK, 48 | input RSTn 49 | 50 | ); 51 | 52 | 53 | 54 | 55 | 56 | wire [ DW*DP - 1 : 0] info_dnxt; 57 | wire [ DW*DP - 1 : 0] info_qout; 58 | wire [DP-1 : 0] info_en; 59 | 60 | 61 | wire [DP-1:0] valid_dnxt; 62 | wire [DP-1:0] valid_qout; 63 | wire [DP-1:0] valid_en; 64 | 65 | 66 | 67 | 68 | generate 69 | for ( genvar dp = 0; dp < DP; dp = dp + 1 ) begin 70 | 71 | assign info_dnxt[DW*dp +: DW] = info_i; 72 | assign info_en[dp] = push & (dp == index); 73 | assign valid_dnxt[dp] = push & (~flush); 74 | assign valid_en[dp] = (pop | push | flush) & (dp == index); 75 | 76 | gen_dffren #(.DW(DW)) info_dffren 77 | ( 78 | .dnxt(info_dnxt[DW*dp +: DW]), 79 | .qout(info_qout[DW*dp +: DW]), 80 | .en(info_en[dp]), 81 | .CLK(CLK), .RSTn(RSTn) 82 | ); 83 | 84 | gen_dffren #(.DW(1)) valid_dffren 85 | ( 86 | .dnxt(valid_dnxt[dp]), 87 | .qout(valid_qout[dp]), 88 | .en(valid_en[dp]), 89 | .CLK (CLK), 90 | .RSTn(RSTn) 91 | ); 92 | 93 | end 94 | endgenerate 95 | 96 | assign info_o = info_qout; 97 | assign valid = valid_qout; 98 | 99 | assign empty = & (~valid); 100 | assign full = & valid; 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | endmodule 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | -------------------------------------------------------------------------------- /RiftChip/element/gen_ringStack.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_ringStack 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-30 17:55:22 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:05:57 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | module gen_ringStack # ( 30 | parameter DW = 64, 31 | parameter AW = 3 32 | ) ( 33 | 34 | input stack_pop, 35 | input stack_push, 36 | 37 | output stack_empty, 38 | 39 | output [DW-1:0] data_pop, 40 | input [DW-1:0] data_push, 41 | 42 | input flush, 43 | input CLK, 44 | input RSTn 45 | ); 46 | 47 | localparam DP = 2**AW; 48 | 49 | wire stack_full; 50 | wire [AW+1-1:0] btm_addr_dnxt, btm_addr_qout; 51 | wire [AW+1-1:0] top_addr_dnxt, top_addr_qout; 52 | wire [DP*DW-1:0] stack_data_dnxt, stack_data_qout; 53 | 54 | gen_dffr #(.DW(AW+1)) btm_addr (.dnxt(btm_addr_dnxt), .qout(btm_addr_qout), .CLK(CLK), .RSTn(RSTn)); 55 | gen_dffr #(.DW(AW+1)) top_addr (.dnxt(top_addr_dnxt), .qout(top_addr_qout), .CLK(CLK), .RSTn(RSTn)); 56 | 57 | assign stack_empty = (btm_addr_qout == top_addr_qout); 58 | assign stack_full = (btm_addr_qout[AW-1:0] == top_addr_qout[AW-1:0]) & (btm_addr_qout[AW] != top_addr_qout[AW]); 59 | 60 | wire [AW-1:0] read_addr = top_addr_qout[AW-1:0] - 'd1; 61 | wire [AW-1:0] write_addr = top_addr_qout[AW-1:0]; 62 | 63 | 64 | generate 65 | for ( genvar i = 0; i < DP; i = i + 1 ) begin 66 | assign stack_data_dnxt[DW*i+:DW] = (stack_push & (write_addr == i) ) ? data_push : stack_data_qout[DW*i+:DW]; 67 | 68 | gen_dffr #(.DW(DW)) stack_data (.dnxt(stack_data_dnxt[DW*i+:DW]), .qout(stack_data_qout[DW*i+:DW]), .CLK(CLK), .RSTn(RSTn)); 69 | 70 | end 71 | endgenerate 72 | 73 | 74 | 75 | 76 | assign data_pop = stack_data_qout[DW*read_addr+:DW]; 77 | 78 | assign btm_addr_dnxt = flush ? {(AW+1){1'b0}} : ( (stack_push & stack_full) ? btm_addr_qout + 'd1 : btm_addr_qout ); 79 | assign top_addr_dnxt = flush ? {(AW+1){1'b0}} : (({(AW+1){stack_push}} & (top_addr_qout + 'd1 )) 80 | | 81 | ({(AW+1){stack_pop & ~stack_empty}} & (top_addr_qout - 'd1)) 82 | | 83 | ({(AW+1){~stack_push & ~(stack_pop & ~stack_empty)}} & top_addr_qout)); 84 | 85 | endmodule 86 | 87 | 88 | 89 | -------------------------------------------------------------------------------- /RiftChip/element/gen_rsffr.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_rsffr 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-12-29 18:02:54 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-05 19:17:21 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2020 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module gen_rsffr # ( 29 | parameter DW = 1, 30 | parameter rstValue = {DW{1'b0}} 31 | ) 32 | ( 33 | 34 | input [DW-1:0] set_in, 35 | input [DW-1:0] rst_in, 36 | 37 | output [DW-1:0] qout, 38 | 39 | input CLK, 40 | input RSTn 41 | ); 42 | 43 | reg [DW-1:0] qout_r; 44 | 45 | generate 46 | for ( genvar i = 0; i < DW; i = i + 1 ) begin 47 | 48 | always @(posedge CLK or negedge RSTn) begin 49 | if ( ~RSTn ) begin 50 | qout_r[i] <= #1 rstValue[i]; 51 | end 52 | else begin 53 | qout_r[i] <= #1 qout_r[i]; 54 | if ( set_in[i] ) begin 55 | qout_r[i] <= #1 1'b1; 56 | end 57 | if ( rst_in[i] ) begin 58 | qout_r[i] <= #1 1'b0; 59 | end 60 | end 61 | end 62 | end 63 | endgenerate 64 | 65 | assign qout = qout_r; 66 | 67 | endmodule 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /RiftChip/element/gen_slffr.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_slffr 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-18 11:43:15 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-18 11:53:19 8 | */ 9 | 10 | 11 | 12 | /* 13 | Copyright (c) 2020 - 2021 Ruige Lee 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | module gen_slffr # ( 31 | parameter DW = 1, 32 | parameter rstValue = 1'b0 33 | ) 34 | ( 35 | 36 | input [DW-1:0] set_in, 37 | input [DW-1:0] rst_in, 38 | 39 | output [DW-1:0] qout, 40 | 41 | input CLK, 42 | input RSTn 43 | ); 44 | 45 | 46 | wire [DW-1:0] rsffr_qout; 47 | gen_rsffr # ( .DW(DW), .rstValue(rstValue)) rsffr ( .set_in(set_in), .rst_in(rst_in), .qout(rsffr_qout), .CLK(CLK), .RSTn(RSTn)); 48 | 49 | 50 | assign qout = set_in | rsffr_qout; 51 | 52 | //ASSERT 53 | always @( posedge CLK ) begin 54 | if ( set_in & rst_in ) begin 55 | $display("Assert Fail at gen_slff"); 56 | $finish; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | -------------------------------------------------------------------------------- /RiftChip/element/gen_sram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_sram 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-04 17:37:00 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-24 17:38:10 8 | */ 9 | 10 | 11 | 12 | /* 13 | Copyright (c) 2020 - 2021 Ruige Lee 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | 31 | 32 | module gen_sram # 33 | ( 34 | parameter DW = 32, 35 | parameter AW = 14 36 | ) 37 | ( 38 | 39 | input [DW-1:0] data_w, 40 | input [AW-1:0] addr_w, 41 | input [(DW+7)/8-1:0] data_wstrb, 42 | input en_w, 43 | 44 | 45 | output [DW-1:0] data_r, 46 | input [AW-1:0] addr_r, 47 | input en_r, 48 | 49 | input CLK 50 | 51 | ); 52 | 53 | localparam DP = 2**AW; 54 | localparam DW_ZM = (DW+7)/8*8; 55 | 56 | reg [DW_ZM-1:0] ram[0:DP-1]; 57 | reg [DW_ZM-1:0] data_r_reg; 58 | wire [DW_ZM-1:0] data_w_zmask = {DW_ZM{1'b0}} | data_w; 59 | 60 | 61 | generate 62 | for ( genvar i = 0; i < (DW+7)/8; i = i + 1) begin 63 | always @(posedge CLK) begin 64 | if (en_w) begin 65 | if (data_wstrb[i]) begin 66 | ram[addr_w][i*8+:8] <= #1 data_w_zmask[i*8+:8] ; 67 | end 68 | end 69 | 70 | if (en_r) begin 71 | data_r_reg[i*8+:8] <= #1 ram[addr_r][i*8+:8]; 72 | end 73 | end 74 | 75 | 76 | end 77 | endgenerate 78 | 79 | assign data_r = data_r_reg[DW-1:0]; 80 | 81 | 82 | integer i; 83 | initial begin 84 | for ( i = 0; i < DP; i = i + 1 ) begin 85 | ram[i] = $random; 86 | end 87 | 88 | data_r_reg = $random; 89 | end 90 | 91 | 92 | endmodule 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | -------------------------------------------------------------------------------- /RiftChip/element/gen_suffr.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_suffr 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-18 11:48:30 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-18 11:53:26 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | module gen_suffr # ( 30 | parameter DW = 1, 31 | parameter rstValue = 1'b0 32 | ) 33 | ( 34 | 35 | input [DW-1:0] set_in, 36 | input [DW-1:0] rst_in, 37 | 38 | output [DW-1:0] qout, 39 | 40 | input CLK, 41 | input RSTn 42 | ); 43 | 44 | 45 | wire [DW-1:0] rsffr_qout; 46 | gen_rsffr # ( .DW(DW), .rstValue(rstValue)) rsffr ( .set_in(set_in), .rst_in(rst_in), .qout(rsffr_qout), .CLK(CLK), .RSTn(RSTn)); 47 | 48 | 49 | assign qout = ~rst_in & rsffr_qout; 50 | 51 | 52 | 53 | //ASSERT 54 | always @( posedge CLK ) begin 55 | if ( set_in & rst_in ) begin 56 | $display("Assert Fail at gen_suff"); 57 | $finish; 58 | end 59 | end 60 | 61 | endmodule 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /RiftChip/element/gen_syn.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: gen_syn 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-12-04 19:25:48 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-10 15:44:28 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | 31 | module gen_syn # 32 | ( 33 | parameter lever = 2 34 | ) 35 | ( 36 | 37 | input data_asyn, 38 | output data_syn, 39 | 40 | input CLK, 41 | input RSTn 42 | 43 | ); 44 | 45 | 46 | 47 | wire [lever-1 : 0] syn_dnxt; 48 | wire [lever-1 : 0] syn_qout; 49 | 50 | assign syn_dnxt = {syn_qout[lever-2:0], data_asyn}; 51 | assign data_syn = syn_qout[lever-1]; 52 | 53 | gen_dffr # ( .DW(lever) ) syn ( .dnxt(syn_dnxt), .qout(syn_qout), .CLK(CLK), .RSTn(RSTn) ); 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | endmodule 74 | 75 | 76 | 77 | 78 | 79 | -------------------------------------------------------------------------------- /RiftChip/element/lfsr.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: lfsr 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-28 17:59:22 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-26 17:38:38 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | module lfsr 30 | ( 31 | output [15:0] random, 32 | 33 | input CLK 34 | ); 35 | 36 | 37 | 38 | 39 | 40 | reg [15:0] shiftReg; 41 | 42 | initial begin shiftReg = $random; end 43 | 44 | wire tap; 45 | 46 | always @(posedge CLK) begin 47 | shiftReg <= #1 { shiftReg[14:0], tap }; 48 | end 49 | 50 | assign tap = shiftReg[15] ^ shiftReg[4] ^ shiftReg[2] ^ shiftReg[1]; 51 | assign random = shiftReg; 52 | 53 | 54 | 55 | 56 | endmodule 57 | 58 | 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /RiftChip/element/lzp.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: lzp 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-11-03 10:23:12 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:06:06 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | //find out last 0 29 | 30 | module lzp #( 31 | parameter CW = 2, 32 | parameter DW = 2**CW 33 | ) ( 34 | input [DW-1:0] in_i, 35 | output [CW-1:0] pos_o, 36 | output all1, 37 | output all0 38 | ); 39 | 40 | //all 0 41 | assign all0 = &(~in_i); 42 | //all 1 43 | assign all1 = &in_i; 44 | 45 | 46 | 47 | 48 | 49 | wire [127:0] invert_in = ~ (in_i | ( {{(128-DW){1'b1}} , {DW{1'b0}}} ) ); 50 | 51 | wire sel_lever0; 52 | wire index_lever0; 53 | 54 | wire [1:0] sel_lever1; 55 | wire [1:0] index_lever1; 56 | 57 | wire [3:0] sel_lever2; 58 | wire [3:0] index_lever2; 59 | 60 | wire [7:0] sel_lever3; 61 | wire [7:0] index_lever3; 62 | 63 | wire [15:0] sel_lever4; 64 | wire [15:0] index_lever4; 65 | 66 | wire [31:0] sel_lever5; 67 | wire [31:0] index_lever5; 68 | 69 | wire [63:0] sel_lever6; 70 | wire [63:0] index_lever6; 71 | 72 | wire [6:0] pos; 73 | generate 74 | for ( genvar i = 0; i < 64; i = i + 1 ) begin 75 | assign index_lever6[i] = invert_in[i*2] | invert_in[i*2+1]; 76 | assign sel_lever6[i] = ~invert_in[i*2]; 77 | end 78 | 79 | for ( genvar i = 0; i < 32; i = i + 1 ) begin 80 | assign index_lever5[i] = index_lever6[i*2] | index_lever6[i*2+1]; 81 | assign sel_lever5[i] = ~index_lever6[i*2]; 82 | end 83 | 84 | for ( genvar i = 0; i < 16; i = i + 1 ) begin 85 | assign index_lever4[i] = index_lever5[i*2] | index_lever5[i*2+1]; 86 | assign sel_lever4[i] = ~index_lever5[i*2]; 87 | end 88 | 89 | for ( genvar i = 0; i < 8; i = i + 1 ) begin 90 | assign index_lever3[i] = index_lever4[i*2] | index_lever4[i*2+1]; 91 | assign sel_lever3[i] = ~index_lever4[i*2]; 92 | end 93 | 94 | for ( genvar i = 0; i < 4; i = i + 1 ) begin 95 | assign index_lever2[i] = index_lever3[i*2] | index_lever3[i*2+1]; 96 | assign sel_lever2[i] = ~index_lever3[i*2]; 97 | end 98 | 99 | for ( genvar i = 0; i < 2; i = i + 1 ) begin 100 | assign index_lever1[i] = index_lever2[i*2] | index_lever2[i*2+1]; 101 | assign sel_lever1[i] = ~index_lever2[i*2]; 102 | end 103 | 104 | 105 | assign index_lever0 = index_lever1[0] | index_lever1[1]; 106 | assign sel_lever0 = ~index_lever1[0]; 107 | 108 | 109 | endgenerate 110 | 111 | assign pos[6] = sel_lever0; 112 | assign pos[5] = sel_lever1[pos[6]]; 113 | assign pos[4] = sel_lever2[pos[6:5]]; 114 | assign pos[3] = sel_lever3[pos[6:4]]; 115 | assign pos[2] = sel_lever4[pos[6:3]]; 116 | assign pos[1] = sel_lever5[pos[6:2]]; 117 | assign pos[0] = sel_lever6[pos[6:1]]; 118 | 119 | assign pos_o = pos[CW-1:0]; 120 | 121 | 122 | 123 | endmodule 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/execute/alu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: alu 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-11-16 09:37:52 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:33 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | `timescale 1 ns / 1 ps 28 | `include "define.vh" 29 | 30 | 31 | module alu #( 32 | parameter DW = `ALU_EXEPARAM_DW 33 | ) 34 | ( 35 | 36 | input alu_exeparam_valid, 37 | input [DW-1:0] alu_exeparam, 38 | 39 | output alu_writeback_valid, 40 | output [63:0] alu_res_qout, 41 | output [(5+`RB)-1:0] alu_rd0_qout, 42 | 43 | //from regFile 44 | input [(64*`RP*32)-1:0] regFileX_read, 45 | 46 | input flush, 47 | input CLK, 48 | input RSTn 49 | 50 | ); 51 | 52 | wire alu_fun_imm; 53 | wire alu_fun_add; 54 | wire alu_fun_sub; 55 | wire alu_fun_slt; 56 | wire alu_fun_xor; 57 | wire alu_fun_or; 58 | wire alu_fun_and; 59 | wire alu_fun_sll; 60 | wire alu_fun_srl; 61 | wire alu_fun_sra; 62 | wire is32w; 63 | wire isUsi; 64 | wire isImm; 65 | wire isShamt; 66 | 67 | wire [(5+`RB)-1:0] alu_rs1; 68 | wire [(5+`RB)-1:0] alu_rs2; 69 | wire [(5+`RB)-1:0] alu_rd0_dnxt; 70 | 71 | wire [63:0] exe_pc; 72 | wire [63:0] exe_imm; 73 | 74 | 75 | assign { 76 | alu_fun_imm, 77 | alu_fun_add, 78 | alu_fun_sub, 79 | alu_fun_slt, 80 | alu_fun_xor, 81 | alu_fun_or, 82 | alu_fun_and, 83 | alu_fun_sll, 84 | alu_fun_srl, 85 | alu_fun_sra, 86 | 87 | is32w, 88 | isUsi, 89 | isImm, 90 | isShamt, 91 | 92 | alu_rs1, 93 | alu_rs2, 94 | alu_rd0_dnxt, 95 | 96 | exe_pc, 97 | exe_imm 98 | 99 | } = alu_exeparam; 100 | 101 | 102 | wire [63:0] src1 = regFileX_read[ 64*alu_rs1 +: 64]; 103 | wire [63:0] src2 = regFileX_read[ 64*alu_rs2 +: 64]; 104 | 105 | wire [63:0] adder_op1 = ({64{alu_fun_imm}} & exe_pc) 106 | | 107 | ({64{alu_fun_add|alu_fun_sub}} & src1 ); 108 | 109 | wire [63:0] adder_op2 = ({64{alu_fun_imm}} & exe_imm) 110 | | 111 | ( {64{alu_fun_add & ~isImm}} & src2 ) 112 | | 113 | ( {64{alu_fun_add & isImm}} & exe_imm ) 114 | | 115 | ( {64{alu_fun_sub}} & (~src2 + 64'd1) ); 116 | 117 | 118 | wire [63:0] adder_cal = $unsigned( is32w ? { {32{adder_op1[31]}}, adder_op1[31:0]} : adder_op1) + $unsigned(is32w ? { {32{adder_op2[31]}}, adder_op2[31:0]} : adder_op2); 119 | wire [63:0] alu_add_res = is32w ? {{32{adder_cal[31]}}, adder_cal[31:0]} : adder_cal; 120 | 121 | 122 | 123 | 124 | wire [63:0] log_op1 = src1; 125 | wire [63:0] log_op2 = ({64{isImm}} & exe_imm) 126 | | 127 | ({64{~isImm}} & src2); 128 | 129 | 130 | wire [63:0] alu_xor_res = log_op1 ^ log_op2; 131 | wire [63:0] alu_or_res = log_op1 | log_op2; 132 | wire [63:0] alu_and_res = log_op1 & log_op2; 133 | 134 | 135 | wire [63:0] slt_sign_res = ( $signed(log_op1) < $signed(log_op2) ) ? 64'd1 : 64'd0; 136 | wire [63:0] slt_unsign_res = ( $unsigned(log_op1) < $unsigned(log_op2) ) ? 64'd1 : 64'd0; 137 | wire [63:0] alu_slt_res = isUsi ? slt_unsign_res : slt_sign_res; 138 | 139 | 140 | wire [63:0] shift_op1 = src1; 141 | wire [5:0] shamt = isShamt ? {~is32w & exe_imm[5], exe_imm[4:0]} : {~is32w & src2[5], src2[4:0]}; 142 | 143 | 144 | 145 | //shift SLL SRL SRA 146 | 147 | wire [63:0] shiftLeft_op1 = shift_op1; 148 | wire signed [64:0] shiftRigt_op1 = is32w ? { {33{(shift_op1[31] & alu_fun_sra)}}, shift_op1[31:0]} 149 | : { (shift_op1[63] & alu_fun_sra), shift_op1 }; 150 | 151 | wire [63:0] shift_left64 = shiftLeft_op1 << shamt; 152 | wire [63:0] shift_left32 = {{32{shift_left64[31]}},shift_left64[31:0]}; 153 | 154 | wire signed [63:0] shift_rigt64 = shiftRigt_op1 >>> shamt; 155 | wire signed [63:0] shift_rigt32 = {{32{shift_rigt64[31]}},shift_rigt64[31:0]}; 156 | 157 | wire [63:0] alu_sl_res = is32w ? shift_left32 : shift_left64; 158 | wire [63:0] alu_sr_res = is32w ? shift_rigt32 : shift_rigt64; 159 | 160 | 161 | 162 | 163 | 164 | wire [63:0] alu_res_dnxt = ( {64{alu_fun_imm | alu_fun_add | alu_fun_sub}} & alu_add_res ) 165 | | ( {64{alu_fun_slt}} & alu_slt_res ) 166 | | ( {64{alu_fun_xor}} & alu_xor_res ) 167 | | ( {64{alu_fun_or}} & alu_or_res ) 168 | | ( {64{alu_fun_and}} & alu_and_res ) 169 | | ( {64{alu_fun_sll}} & alu_sl_res ) 170 | | ( {64{alu_fun_srl | alu_fun_sra}} & alu_sr_res ); 171 | 172 | 173 | gen_dffr # (.DW((5+`RB))) alu_rd0 ( .dnxt(alu_rd0_dnxt), .qout(alu_rd0_qout), .CLK(CLK), .RSTn(RSTn)); 174 | gen_dffr # (.DW(64)) alu_res ( .dnxt(alu_res_dnxt), .qout(alu_res_qout), .CLK(CLK), .RSTn(RSTn)); 175 | gen_dffr # (.DW(1)) valid ( .dnxt(alu_exeparam_valid&(~flush)), .qout(alu_writeback_valid), .CLK(CLK), .RSTn(RSTn)); 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | endmodule 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/execute/bru.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: bru 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-09-20 16:41:01 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:32 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | `include "define.vh" 28 | 29 | module bru # 30 | ( 31 | parameter DW = `BRU_EXEPARAM_DW 32 | ) 33 | ( 34 | 35 | //from bru issue 36 | output bru_exeparam_ready, 37 | input bru_exeparam_valid, 38 | input [DW-1:0] bru_exeparam, 39 | 40 | // to pc generate 41 | output takenBranch_qout, 42 | output takenBranch_valid_qout, 43 | output jalr_valid_qout, 44 | output [63:0] jalr_pc_qout, 45 | 46 | output bru_writeback_valid, 47 | output [63:0] bru_res_qout, 48 | output [(5+`RB)-1:0] bru_rd0_qout, 49 | 50 | //from regFile 51 | input [(64*`RP*32)-1:0] regFileX_read, 52 | 53 | input flush, 54 | input CLK, 55 | input RSTn 56 | 57 | ); 58 | 59 | wire bru_pcGen_ready = 1'b1; 60 | 61 | wire bru_jal; 62 | wire bru_jalr; 63 | wire bru_eq; 64 | wire bru_ne; 65 | wire bru_lt; 66 | wire bru_ge; 67 | wire bru_ltu; 68 | wire bru_geu; 69 | 70 | wire is_rvc; 71 | 72 | wire [(5+`RB)-1:0] bru_rs1; 73 | wire [(5+`RB)-1:0] bru_rs2; 74 | wire [(5+`RB)-1:0] bru_rd0_dnxt; 75 | 76 | wire [63:0] bru_pc; 77 | wire [63:0] bru_imm; 78 | 79 | 80 | assign { 81 | bru_jal, 82 | bru_jalr, 83 | 84 | bru_eq, 85 | bru_ne, 86 | bru_lt, 87 | bru_ge, 88 | bru_ltu, 89 | bru_geu, 90 | 91 | is_rvc, 92 | 93 | bru_rs1, 94 | bru_rs2, 95 | bru_rd0_dnxt, 96 | 97 | bru_pc, 98 | bru_imm 99 | } = bru_exeparam; 100 | 101 | wire [63:0] src1 = regFileX_read[ 64*bru_rs1 +: 64]; 102 | wire [63:0] src2 = regFileX_read[ 64*bru_rs2 +: 64]; 103 | 104 | 105 | 106 | 107 | wire [63:0] jalr_pc_dnxt = (src1 + bru_imm) & ~(64'b1); 108 | wire jalr_valid_dnxt = (~flush) & bru_jalr & bru_exeparam_valid; 109 | 110 | gen_dffr # (.DW(1)) jalr_valid ( .dnxt(jalr_valid_dnxt), .qout(jalr_valid_qout), .CLK(CLK), .RSTn(RSTn)); 111 | gen_dffr # (.DW(64)) jalr_pc ( .dnxt(jalr_pc_dnxt), .qout(jalr_pc_qout), .CLK(CLK), .RSTn(RSTn)); 112 | 113 | 114 | 115 | 116 | wire take_eq = (bru_eq & (src1 == src2)); 117 | wire take_ne = (bru_ne & (src1 != src2)); 118 | wire take_lt = (bru_lt) & ($signed(src1) < $signed(src2)); 119 | wire take_ge = (bru_ge) & ($signed(src1) >= $signed(src2)); 120 | wire take_ltu = (bru_ltu) & ($unsigned(src1) < $unsigned(src2)); 121 | wire take_geu = (bru_geu) & ($unsigned(src1) >= $unsigned(src2)); 122 | 123 | wire valid_dnxt = (~flush) & bru_pcGen_ready & bru_exeparam_valid 124 | & ( bru_eq 125 | | bru_ne 126 | | bru_lt 127 | | bru_ge 128 | | bru_ltu 129 | | bru_geu ); 130 | 131 | wire takenBranch_dnxt = valid_dnxt 132 | ? (take_eq | take_ne | take_lt | take_ge | take_ltu | take_geu) 133 | : takenBranch_qout; 134 | 135 | 136 | 137 | 138 | gen_dffr # (.DW(1)) takenBranch ( .dnxt(takenBranch_dnxt), .qout(takenBranch_qout), .CLK(CLK), .RSTn(RSTn)); 139 | gen_dffr # (.DW(1)) takenBranch_valid ( .dnxt(valid_dnxt), .qout(takenBranch_valid_qout), .CLK(CLK), .RSTn(RSTn)); 140 | 141 | 142 | assign bru_exeparam_ready = bru_pcGen_ready; 143 | wire [63:0] bru_res_dnxt = ({64{(bru_jal | bru_jalr)}} & (bru_pc + (is_rvc ? 64'd2 : 64'd4))) 144 | | 145 | ( {64{(~bru_jal & ~bru_jalr)}} & 64'b0 ); 146 | 147 | gen_dffr # (.DW((5+`RB))) bru_rd0 ( .dnxt(bru_rd0_dnxt), .qout(bru_rd0_qout), .CLK(CLK), .RSTn(RSTn)); 148 | gen_dffr # (.DW(64)) bru_res ( .dnxt( bru_res_dnxt), .qout(bru_res_qout), .CLK(CLK), .RSTn(RSTn)); 149 | gen_dffr # (.DW(1)) valid ( .dnxt(bru_exeparam_valid&(~flush)), .qout(bru_writeback_valid), .CLK(CLK), .RSTn(RSTn)); 150 | 151 | 152 | 153 | 154 | 155 | 156 | endmodule 157 | 158 | 159 | 160 | 161 | 162 | 163 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/execute/csr.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: csr 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-30 14:30:32 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-05 14:36:14 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | `include "define.vh" 28 | 29 | module csr # 30 | ( 31 | parameter DW = `CSR_EXEPARAM_DW 32 | ) 33 | ( 34 | 35 | input csr_exeparam_valid, 36 | input [DW-1 :0] csr_exeparam, 37 | 38 | // //from csrfiles 39 | output [11:0] csrexe_addr, 40 | output [63:0] op, 41 | input [63:0] csrexe_res, 42 | output rw, 43 | output rs, 44 | output rc, 45 | 46 | output csr_writeback_valid, 47 | output [63:0] csr_res_qout, 48 | output [(5+`RB-1):0] csr_rd0_qout, 49 | 50 | input [(64*`RP*32)-1:0] regFileX_read, 51 | 52 | input CLK, 53 | input RSTn, 54 | input flush 55 | 56 | ); 57 | 58 | 59 | wire rv64csr_rw; 60 | wire rv64csr_rs; 61 | wire rv64csr_rc; 62 | 63 | wire [(5+`RB)-1:0] csr_rd0_dnxt; 64 | wire [(5+`RB)-1:0] csr_rs1; 65 | wire is_imm; 66 | wire [63:0] op; 67 | 68 | 69 | assign { 70 | rv64csr_rw, 71 | rv64csr_rs, 72 | rv64csr_rc, 73 | 74 | csr_rd0_dnxt, 75 | csr_rs1, 76 | is_imm, 77 | csrexe_addr 78 | 79 | } = csr_exeparam; 80 | 81 | 82 | assign op = ({64{~is_imm}} & regFileX_read[csr_rs1*64 +: 64]) 83 | | 84 | ({64{is_imm}} & {{(64-5){1'b0}}, csr_rs1[`RB +: 5]} ); 85 | 86 | 87 | 88 | 89 | 90 | wire dontRead = (csr_rd0_dnxt[`RB +: 5] == 5'd0) & rv64csr_rw; 91 | wire dontWrite = (op == 64'd0) & ( rv64csr_rs | rv64csr_rc ); 92 | 93 | initial $warning("no exception in csr exe at this version"); 94 | wire illagle_op = 1'b0; 95 | 96 | 97 | 98 | 99 | assign rw = ~dontWrite & csr_exeparam_valid & rv64csr_rw; 100 | assign rs = ~dontWrite & csr_exeparam_valid & rv64csr_rs; 101 | assign rc = ~dontWrite & csr_exeparam_valid & rv64csr_rc; 102 | 103 | wire [63:0] csr_res_dnxt = csrexe_res; 104 | 105 | 106 | gen_dffr # (.DW((5+`RB))) csr_rd0_dffr ( .dnxt(csr_rd0_dnxt), .qout(csr_rd0_qout), .CLK(CLK), .RSTn(RSTn)); 107 | gen_dffr # (.DW(64)) csr_res_dffr ( .dnxt(csr_res_dnxt), .qout(csr_res_qout), .CLK(CLK), .RSTn(RSTn)); 108 | gen_dffr # (.DW(1)) valid_dffr ( .dnxt(csr_exeparam_valid&(~flush)), .qout(csr_writeback_valid), .CLK(CLK), .RSTn(RSTn)); 109 | 110 | 111 | 112 | endmodule 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/issue/bru_issue.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: bru_issue 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-27 10:50:36 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:28 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | `include "define.vh" 29 | 30 | module bru_issue # 31 | ( 32 | parameter DW = `BRU_ISSUE_INFO_DW, 33 | parameter EXE_DW = `BRU_EXEPARAM_DW 34 | ) 35 | ( 36 | 37 | //from fifo 38 | output bru_fifo_pop, 39 | input bru_fifo_empty, 40 | input [DW-1:0] bru_issue_info, 41 | 42 | //from execute 43 | 44 | input bru_exeparam_ready, 45 | output bru_exeparam_valid_qout, 46 | output [EXE_DW-1:0] bru_exeparam_qout, 47 | input bruILP_ready, 48 | 49 | input [32*`RP-1 : 0] wbLog_qout, 50 | 51 | input flush, 52 | input CLK, 53 | input RSTn 54 | ); 55 | 56 | 57 | wire rv64i_jal; 58 | wire rv64i_jalr; 59 | wire rv64i_beq; 60 | wire rv64i_bne; 61 | wire rv64i_blt; 62 | wire rv64i_bge; 63 | wire rv64i_bltu; 64 | wire rv64i_bgeu; 65 | 66 | wire is_rvc; 67 | 68 | wire [63:0] bru_pc; 69 | wire [63:0] bru_imm; 70 | 71 | wire [5+`RB-1:0] bru_rd0; 72 | wire [5+`RB-1:0] bru_rs1; 73 | wire [5+`RB-1:0] bru_rs2; 74 | 75 | 76 | assign { 77 | rv64i_jal, 78 | rv64i_jalr, 79 | rv64i_beq, 80 | rv64i_bne, 81 | rv64i_blt, 82 | rv64i_bge, 83 | rv64i_bltu, 84 | rv64i_bgeu, 85 | 86 | is_rvc, 87 | 88 | bru_pc, 89 | bru_imm, 90 | 91 | bru_rd0, 92 | bru_rs1, 93 | bru_rs2 94 | } = bru_issue_info; 95 | 96 | 97 | wire rs1_ready = wbLog_qout[bru_rs1] | (bru_rs1[`RB +: 5] == 5'd0); 98 | wire rs2_ready = wbLog_qout[bru_rs2] | (bru_rs2[`RB +: 5] == 5'd0); 99 | 100 | wire bru_isClearRAW = ( ~bru_fifo_empty ) 101 | & ( 102 | ( ( rv64i_beq 103 | | rv64i_bne 104 | | rv64i_blt 105 | | rv64i_bge 106 | | rv64i_bltu 107 | | rv64i_bgeu 108 | ) & rs1_ready & rs2_ready & bruILP_ready) 109 | | rv64i_jal 110 | | ( rv64i_jalr & rs1_ready ) 111 | ); 112 | 113 | wire [EXE_DW-1:0] bru_exeparam_dnxt = bru_exeparam_valid_dnxt ? { 114 | rv64i_jal, 115 | rv64i_jalr, 116 | 117 | rv64i_beq, 118 | rv64i_bne, 119 | rv64i_blt, 120 | rv64i_bge, 121 | rv64i_bltu, 122 | rv64i_bgeu, 123 | 124 | is_rvc, 125 | 126 | bru_rs1, 127 | bru_rs2, 128 | bru_rd0, 129 | 130 | bru_pc, 131 | bru_imm 132 | } 133 | : bru_exeparam_qout; 134 | 135 | wire bru_exeparam_valid_dnxt = flush ? 1'b0 : (bru_exeparam_ready & bru_isClearRAW); 136 | assign bru_fifo_pop = bru_exeparam_valid_dnxt; 137 | 138 | gen_dffr # (.DW(EXE_DW)) bru_exeparam ( .dnxt(bru_exeparam_dnxt), .qout(bru_exeparam_qout), .CLK(CLK), .RSTn(RSTn)); 139 | gen_dffr # (.DW(1)) bru_exeparam_valid ( .dnxt(bru_exeparam_valid_dnxt), .qout(bru_exeparam_valid_qout), .CLK(CLK), .RSTn(RSTn)); 140 | 141 | 142 | 143 | 144 | 145 | 146 | endmodule 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/issue/csr_issue.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: csr_issue 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-27 10:51:47 6 | * @Last Modified by: Ruige Lee 7 | <<<<<<< HEAD:RiftChip/riftCore/backend/issue/csr_issue.v 8 | * @Last Modified time: 2021-01-05 16:45:28 9 | ======= 10 | * @Last Modified time: 2021-01-03 12:08:27 11 | >>>>>>> master:core/riftCore/backend/issue/csr_issue.v 12 | */ 13 | 14 | /* 15 | Copyright (c) 2020 - 2021 Ruige Lee 16 | 17 | Licensed under the Apache License, Version 2.0 (the "License"); 18 | you may not use this file except in compliance with the License. 19 | You may obtain a copy of the License at 20 | 21 | http://www.apache.org/licenses/LICENSE-2.0 22 | 23 | Unless required by applicable law or agreed to in writing, software 24 | distributed under the License is distributed on an "AS IS" BASIS, 25 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | See the License for the specific language governing permissions and 27 | limitations under the License. 28 | */ 29 | 30 | 31 | `timescale 1 ns / 1 ps 32 | `include "define.vh" 33 | 34 | module csr_issue # 35 | ( 36 | parameter DW = `CSR_ISSUE_INFO_DW, 37 | parameter EXE_DW = `CSR_EXEPARAM_DW 38 | ) 39 | ( 40 | 41 | //from fifo 42 | output csr_fifo_pop, 43 | input csr_fifo_empty, 44 | input [DW-1:0] csr_issue_info, 45 | 46 | output csr_exeparam_valid_qout, 47 | output [EXE_DW-1 :0] csr_exeparam_qout, 48 | 49 | //from regFile 50 | input [32*`RP-1 : 0] wbLog_qout, 51 | 52 | //from commit 53 | input [63:0] commit_pc, 54 | 55 | input flush, 56 | input CLK, 57 | input RSTn 58 | ); 59 | 60 | 61 | 62 | initial $info("the pervious instruction must be commited, then csr can issue and execute"); 63 | 64 | //csr must be ready 65 | wire csr_exeparam_ready = 1'b1; 66 | 67 | 68 | wire rv64csr_rw; 69 | wire rv64csr_rs; 70 | wire rv64csr_rc; 71 | wire rv64csr_rwi; 72 | wire rv64csr_rsi; 73 | wire rv64csr_rci; 74 | 75 | wire [63:0] issue_pc; 76 | wire [(5+`RB)-1:0] csr_rd0; 77 | wire [(5+`RB)-1:0] csr_rs1; 78 | wire [11:0] csr_imm; 79 | 80 | wire csrILP_ready = (commit_pc == issue_pc); 81 | 82 | assign { 83 | rv64csr_rw, rv64csr_rs, rv64csr_rc, rv64csr_rwi, rv64csr_rsi, rv64csr_rci, 84 | issue_pc, csr_imm, csr_rd0, csr_rs1 85 | 86 | 87 | } = csr_issue_info; 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | wire csr_rw = rv64csr_rw | rv64csr_rwi; 96 | wire csr_rs = rv64csr_rs | rv64csr_rsi; 97 | wire csr_rc = rv64csr_rc | rv64csr_rci; 98 | 99 | wire rs1_ready = wbLog_qout[csr_rs1] | (csr_rs1[`RB +: 5] == 5'd0); 100 | 101 | wire csr_isClearRAW = ( ~csr_fifo_empty ) & ( ((rv64csr_rw | rv64csr_rs | rv64csr_rc ) & rs1_ready ) 102 | | 103 | (rv64csr_rwi | rv64csr_rsi | rv64csr_rci ) 104 | ); 105 | 106 | wire is_imm = rv64csr_rwi | rv64csr_rsi | rv64csr_rci; 107 | wire [11:0] addr = csr_imm; 108 | 109 | 110 | wire [EXE_DW-1:0] csr_exeparam_dnxt = csr_exeparam_valid_dnxt ? { 111 | csr_rw, 112 | csr_rs, 113 | csr_rc, 114 | 115 | csr_rd0, 116 | csr_rs1, 117 | 118 | is_imm, 119 | addr 120 | } : csr_exeparam_qout; 121 | 122 | wire csr_exeparam_valid_dnxt = flush ? 1'b0 : (csr_isClearRAW & csrILP_ready & csr_exeparam_ready); 123 | 124 | assign csr_fifo_pop = csr_exeparam_valid_dnxt; 125 | 126 | 127 | gen_dffr # (.DW(EXE_DW)) csr_exeparam ( .dnxt(csr_exeparam_dnxt), .qout(csr_exeparam_qout), .CLK(CLK), .RSTn(RSTn)); 128 | gen_dffr # (.DW(1)) csr_exeparam_valid ( .dnxt(csr_exeparam_valid_dnxt), .qout(csr_exeparam_valid_qout), .CLK(CLK), .RSTn(RSTn)); 129 | 130 | 131 | 132 | 133 | endmodule 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/issue/issue_buffer.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: issue_buffer 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-27 18:04:15 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:26 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module issue_buffer # 29 | ( 30 | parameter DW = 100, 31 | parameter DP = 8 32 | ) 33 | 34 | 35 | ( 36 | 37 | input [ DW - 1 : 0] dispat_info, 38 | input buffer_push, 39 | output buffer_full, 40 | 41 | 42 | input buffer_pop, 43 | input [$clog2(DP)-1:0] pop_index, 44 | output [ DW*DP - 1 : 0] issue_info_qout, 45 | output [DP - 1 : 0] buffer_malloc_qout, 46 | 47 | input flush, 48 | input CLK, 49 | input RSTn 50 | 51 | ); 52 | 53 | 54 | 55 | wire [ DW*DP - 1 : 0] issue_info_dnxt; 56 | wire [$clog2(DP)-1:0] issue_push_index_pre; 57 | wire [$clog2(DP)-1:0] issue_push_index = (buffer_pop & buffer_push) ? pop_index : issue_push_index_pre; 58 | wire [DP-1:0] buffer_valid_dnxt; 59 | wire [DP-1:0] buffer_valid_qout; 60 | assign buffer_malloc_qout = buffer_valid_qout; 61 | 62 | generate 63 | for ( genvar dp = 0; dp < DP; dp = dp + 1 ) begin 64 | 65 | assign issue_info_dnxt[DW*dp +: DW] = buffer_push & ( dp == issue_push_index ) 66 | ? dispat_info 67 | : issue_info_qout[DW*dp +: DW]; 68 | 69 | gen_dffr #(.DW(DW)) issue_info ( .dnxt(issue_info_dnxt[DW*dp +: DW]), .qout(issue_info_qout[DW*dp +: DW]), .CLK(CLK), .RSTn(RSTn) ); 70 | 71 | end 72 | endgenerate 73 | 74 | 75 | 76 | 77 | gen_dffr #(.DW(DP)) buffer_valid ( .dnxt(buffer_valid_dnxt), .qout(buffer_valid_qout), .CLK(CLK), .RSTn(RSTn) ); 78 | 79 | assign buffer_valid_dnxt = flush ? {DP{1'b0}} : (( 80 | {DP{(buffer_pop & buffer_push) | (~buffer_pop & ~buffer_push)}} 81 | & buffer_valid_qout 82 | ) 83 | | 84 | ( 85 | {DP{(buffer_push & ~buffer_pop) }} 86 | & (buffer_valid_qout | (1'b1 << issue_push_index_pre)) 87 | ) 88 | | 89 | ( 90 | {DP{(~buffer_push & buffer_pop)}} 91 | & (buffer_valid_qout & ~(1'b1 << pop_index)) 92 | )); 93 | 94 | 95 | 96 | lzp #( 97 | .CW($clog2(DP)) 98 | ) empty_buffer( 99 | .in_i(buffer_valid_qout), 100 | .pos_o(issue_push_index_pre), 101 | .all0(), 102 | .all1(buffer_full) 103 | ); 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | endmodule 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/issue/issue_fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: issue_fifo 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-28 15:34:24 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:05:23 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | module issue_fifo #( 29 | parameter DW = 100, 30 | parameter DP = 8 31 | ) 32 | ( 33 | 34 | input [ DW - 1 : 0] issue_info_push, 35 | output [ DW - 1 : 0] issue_info_pop, 36 | 37 | input issue_push, 38 | input issue_pop, 39 | output fifo_full, 40 | output fifo_empty, 41 | 42 | input flush, 43 | input CLK, 44 | input RSTn 45 | 46 | ); 47 | 48 | 49 | 50 | gen_fifo # ( .DW(DW), .AW($clog2(DP))) 51 | i_fifo( 52 | .fifo_pop(issue_pop), 53 | .fifo_push(issue_push), 54 | .data_push(issue_info_push), 55 | 56 | .fifo_empty(fifo_empty), 57 | .fifo_full(fifo_full), 58 | .data_pop(issue_info_pop), 59 | 60 | .flush(flush), 61 | .CLK(CLK), 62 | .RSTn(RSTn) 63 | ); 64 | 65 | 66 | 67 | 68 | endmodule 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/issue/lsu_issue.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: lsu_issue 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-27 10:51:21 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-15 17:58:39 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | `include "define.vh" 28 | 29 | module lsu_issue # 30 | ( 31 | parameter DW = `LSU_ISSUE_INFO_DW, 32 | parameter DP = `LSU_ISSUE_INFO_DP, 33 | parameter EXE_DW = `LSU_EXEPARAM_DW 34 | 35 | ) 36 | ( 37 | output lsu_fifo_pop, 38 | input lsu_fifo_empty, 39 | input [DW-1:0] lsu_issue_info, 40 | 41 | input issue_lsu_ready, 42 | output issue_lsu_valid, 43 | output [EXE_DW-1:0] issue_lsu_info, 44 | 45 | //from regFile 46 | input [(64*`RP*32)-1:0] regFileX_read, 47 | input [32*`RP-1 : 0] wbLog_qout, 48 | 49 | 50 | 51 | input flush, 52 | input CLK, 53 | input RSTn 54 | ); 55 | 56 | 57 | 58 | wire rv64i_lb; 59 | wire rv64i_lh; 60 | wire rv64i_lw; 61 | wire rv64i_ld; 62 | 63 | wire rv64i_lbu; 64 | wire rv64i_lhu; 65 | wire rv64i_lwu; 66 | 67 | wire rv64i_sb; 68 | wire rv64i_sh; 69 | wire rv64i_sw; 70 | wire rv64i_sd; 71 | 72 | wire rv64zi_fence_i; 73 | wire rv64i_fence; 74 | 75 | wire [63:0] imm; 76 | 77 | wire [(5+`RB)-1:0] lsu_rd0; 78 | wire [(5+`RB)-1:0] lsu_rs1; 79 | wire [(5+`RB)-1:0] lsu_rs2; 80 | 81 | wire rs1_ready; 82 | wire rs2_ready; 83 | 84 | wire lsu_isClearRAW; 85 | 86 | wire [63:0] op1; 87 | wire [63:0] op2; 88 | 89 | 90 | 91 | 92 | 93 | 94 | assign { 95 | rv64i_lb, rv64i_lh, rv64i_lw, rv64i_ld, rv64i_lbu, rv64i_lhu, rv64i_lwu, 96 | rv64i_sb, rv64i_sh, rv64i_sw, rv64i_sd, 97 | rv64zi_fence_i, rv64i_fence, 98 | imm, 99 | lsu_rd0, 100 | lsu_rs1, 101 | lsu_rs2 102 | } = lsu_issue_info; 103 | 104 | 105 | assign rs1_ready = wbLog_qout[lsu_rs1] | ( lsu_rs1[`RB +: 5] == 5'd0 ); 106 | assign rs2_ready = wbLog_qout[lsu_rs2] | ( lsu_rs2[`RB +: 5] == 5'd0 ); 107 | 108 | assign lsu_isClearRAW = ( ~lsu_fifo_empty ) & ( 109 | ( 110 | (rv64i_lb | rv64i_lh | rv64i_lw | rv64i_ld | rv64i_lbu | rv64i_lhu | rv64i_lwu) 111 | & rs1_ready 112 | ) 113 | | 114 | ( 115 | (rv64i_sb | rv64i_sh | rv64i_sw | rv64i_sd) 116 | & rs1_ready & rs2_ready 117 | ) 118 | | 119 | ( 120 | rv64zi_fence_i | rv64i_fence 121 | ) 122 | ); 123 | 124 | 125 | assign op1 = regFileX_read[lsu_rs1 * 64 +: 64] + imm; 126 | assign op2 = regFileX_read[lsu_rs2 * 64 +: 64]; 127 | 128 | 129 | wire issue_lsu_valid_set, issue_lsu_valid_rst, issue_lsu_valid_qout; 130 | wire [EXE_DW-1:0] issue_lsu_info_dnxt; 131 | wire [EXE_DW-1:0] issue_lsu_info_qout; 132 | 133 | 134 | 135 | assign issue_lsu_info_dnxt = issue_lsu_valid_set ? 136 | { 137 | rv64i_lb, rv64i_lh, rv64i_lw, rv64i_ld, rv64i_lbu, rv64i_lhu, rv64i_lwu, 138 | rv64i_sb, rv64i_sh, rv64i_sw, rv64i_sd, 139 | rv64zi_fence_i, rv64i_fence, 140 | lsu_rd0, 141 | op1, 142 | op2 143 | } : issue_lsu_info_qout; 144 | assign issue_lsu_info = issue_lsu_info_qout; 145 | 146 | 147 | 148 | 149 | 150 | assign issue_lsu_valid_set = ~flush & (lsu_isClearRAW & ~issue_lsu_valid_qout); 151 | assign issue_lsu_valid_rst = flush | (issue_lsu_ready & issue_lsu_valid_qout); 152 | assign issue_lsu_valid = issue_lsu_valid_qout; 153 | 154 | assign lsu_fifo_pop = issue_lsu_valid_set; 155 | 156 | 157 | 158 | gen_dffr # (.DW(EXE_DW)) issue_lsu_info_dffr ( .dnxt(issue_lsu_info_dnxt), .qout(issue_lsu_info_qout), .CLK(CLK), .RSTn(RSTn)); 159 | gen_rsffr # (.DW(1)) issue_lsu_valid_rsffr ( .set_in(issue_lsu_valid_set), .rst_in(issue_lsu_valid_rst), .qout(issue_lsu_valid_qout), .CLK(CLK), .RSTn(RSTn)); 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | endmodule 194 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/issue/mul_issue.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: mul_issue 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-12-22 10:48:27 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:24 8 | */ 9 | 10 | 11 | 12 | /* 13 | Copyright (c) 2020 - 2021 Ruige Lee 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | 28 | `timescale 1 ns / 1 ps 29 | `include "define.vh" 30 | 31 | 32 | module mul_issue #( 33 | parameter DW = `MUL_ISSUE_INFO_DW, 34 | parameter DP = `MUL_ISSUE_INFO_DP, 35 | parameter EXE_DW = `MUL_EXEPARAM_DW 36 | ) 37 | ( 38 | //from fifo 39 | output mul_fifo_pop, 40 | input mul_fifo_empty, 41 | input [DW-1:0] mul_issue_info, 42 | 43 | //from execute 44 | input mul_execute_ready, 45 | output mul_exeparam_valid_qout, 46 | output [EXE_DW-1:0] mul_exeparam_qout, 47 | 48 | //from regFile 49 | input [32*`RP-1 : 0] wbLog_qout, 50 | 51 | input flush, 52 | input CLK, 53 | input RSTn 54 | ); 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | wire rv64m_mul, rv64m_mulh, rv64m_mullhsu, rv64m_mulhu, rv64m_div, rv64m_divu, rv64m_rem, rv64m_remu, rv64m_mulw, rv64m_divw, rv64m_divuw, rv64_remw, rv64m_remuw; 63 | 64 | 65 | 66 | 67 | wire [5+`RB-1:0] mul_rd0; 68 | wire [5+`RB-1:0] mul_rs1; 69 | wire [5+`RB-1:0] mul_rs2; 70 | 71 | assign { 72 | rv64m_mul, 73 | rv64m_mulh, 74 | rv64m_mullhsu, 75 | rv64m_mulhu, 76 | rv64m_div, 77 | rv64m_divu, 78 | rv64m_rem, 79 | rv64m_remu, 80 | rv64m_mulw, 81 | rv64m_divw, 82 | rv64m_divuw, 83 | rv64_remw, 84 | rv64m_remuw, 85 | 86 | mul_rd0, 87 | mul_rs1, 88 | mul_rs2 89 | 90 | } = mul_issue_info; 91 | 92 | 93 | 94 | wire rs1_ready = wbLog_qout[mul_rs1] | (mul_rs1[`RB +: 5] == 5'd0); 95 | wire rs2_ready = wbLog_qout[mul_rs2] | (mul_rs2[`RB +: 5] == 5'd0); 96 | 97 | wire mul_isClearRAW = ( ~mul_fifo_empty ) 98 | & 99 | ( 100 | ( 101 | rv64m_mul | rv64m_mulh | rv64m_mullhsu | rv64m_mulhu | rv64m_mulw 102 | | rv64m_div | rv64m_divu | rv64m_rem | rv64m_remu | rv64m_divw | rv64m_divuw | rv64_remw | rv64m_remuw 103 | ) 104 | & rs1_ready & rs2_ready 105 | ); 106 | 107 | wire [EXE_DW-1:0] mul_exeparam_dnxt = 108 | mul_exeparam_valid_dnxt ? 109 | mul_issue_info : 110 | mul_exeparam_qout; 111 | 112 | wire mul_exeparam_valid_dnxt = flush ? 1'b0 : (mul_execute_ready & mul_isClearRAW); 113 | assign mul_fifo_pop = mul_exeparam_valid_dnxt; 114 | 115 | gen_dffr # (.DW(EXE_DW)) mul_exeparam ( .dnxt(mul_exeparam_dnxt), .qout(mul_exeparam_qout), .CLK(CLK), .RSTn(RSTn)); 116 | gen_dffr # (.DW(1)) mul_exeparam_valid ( .dnxt(mul_exeparam_valid_dnxt), .qout(mul_exeparam_valid_qout), .CLK(CLK), .RSTn(RSTn)); 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | endmodule 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/phyRegister.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: phyRegister 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-23 15:42:33 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:05:41 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | `include "define.vh" 28 | 29 | module phyRegister ( 30 | input flush, 31 | 32 | 33 | input [(64*`RP*32)-1:0] regFileX_dnxt, 34 | output [(64*`RP*32)-1:0] regFileX_qout, 35 | 36 | 37 | input [ `RB*32 - 1 :0 ] rnAct_X_dnxt, 38 | output [ `RB*32 - 1 :0 ] rnAct_X_qout, 39 | 40 | input [32*`RP-1 : 0] rnBufU_rename_set, 41 | input [32*`RP-1 : 0] rnBufU_commit_rst, 42 | output [32*`RP-1 : 0] rnBufU_qout, 43 | 44 | input [32*`RP-1 : 0] wbLog_writeb_set, 45 | input [32*`RP-1 : 0] wbLog_commit_rst, 46 | output [32*`RP-1 : 0] wbLog_qout, 47 | 48 | input [ `RB*32 - 1 :0 ] archi_X_dnxt, 49 | output [ `RB*32 - 1 :0 ] archi_X_qout, 50 | 51 | input CLK, 52 | input RSTn 53 | 54 | ); 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | //代表架构寄存器，指向128个寄存器中的地址，完成commit 72 | //指向当前前端可以用的寄存器位置（只会读寄存器），读完不管,32个寄存器，每个可能深度为4 73 | //架构寄存器在commit阶段更新，同时释放rename位置 74 | 75 | generate 76 | for ( genvar i = 0 ; i < 32; i = i + 1 ) begin 77 | gen_dffr #(.DW(`RB)) archi_X ( .dnxt(archi_X_dnxt[`RB*i +: `RB]), .qout(archi_X_qout[`RB*i +: `RB]), .CLK(CLK), .RSTn(RSTn) ); 78 | end 79 | endgenerate 80 | 81 | 82 | //读操作不会改变重命名活动指针， 83 | //读操作需要通过重命名活动指针寻找正确的寄存器， 84 | //写操作需要改变重命名活动指针到一个新位置，需要是空的，否则挂起流水线 85 | 86 | 87 | generate 88 | for ( genvar i = 0 ; i < 32; i = i + 1 ) begin 89 | gen_dffr #(.DW(`RB)) 90 | rnActive_X 91 | ( 92 | .dnxt( {`RB{~flush}} & rnAct_X_dnxt[`RB*i +: `RB] 93 | | {`RB{flush}} & archi_X_qout[`RB*i +: `RB]), 94 | .qout(rnAct_X_qout[`RB*i +: `RB]), 95 | .CLK(CLK), 96 | .RSTn(RSTn) 97 | ); 98 | end 99 | endgenerate 100 | 101 | 102 | //指示128-32个寄存器组中哪些被用了 103 | wire [32*`RP-1 : 0] rnBufU_dnxt; 104 | 105 | generate 106 | for ( genvar i = 0; i < 32; i = i + 1 ) begin 107 | 108 | //commit的复位，重命名的置位 109 | assign rnBufU_dnxt[`RP*i +: `RP] = flush ? 110 | (1'b1 << archi_X_qout[`RB*i +: `RB]) 111 | : ( ( rnBufU_qout[`RP*i +: `RP] 112 | | rnBufU_rename_set[`RP*i +: `RP] ) 113 | & (~rnBufU_commit_rst[`RP*i +: `RP])); 114 | 115 | gen_dffr #(.DW(`RP), .rstValue(`RP'b1)) rnBufU ( .dnxt(rnBufU_dnxt[`RP*i +: `RP]), .qout(rnBufU_qout[`RP*i +: `RP]), .CLK(CLK), .RSTn(RSTn) ); 116 | 117 | 118 | end 119 | 120 | endgenerate 121 | 122 | 123 | 124 | //指示乱序写回是否完成,影响真数据冒险 125 | wire [32*`RP-1 : 0] wbLog_dnxt; 126 | 127 | generate 128 | for ( genvar i = 0; i < 32; i = i + 1 ) begin 129 | 130 | //写回时置1，commit时复位 131 | assign wbLog_dnxt[`RP*i +: `RP] = flush ? 132 | (1'b1 << archi_X_qout[`RB*i +: `RB]) 133 | : ( 134 | (wbLog_qout[`RP*i +: `RP] 135 | | wbLog_writeb_set[`RP*i +: `RP]) 136 | & ~wbLog_commit_rst[`RP*i +: `RP]); 137 | 138 | gen_dffr #(.DW(`RP), .rstValue(`RP'b1)) wbLog ( .dnxt(wbLog_dnxt[`RP*i +: `RP]), .qout(wbLog_qout[`RP*i +: `RP]), .CLK(CLK), .RSTn(RSTn) ); 139 | 140 | end 141 | endgenerate 142 | 143 | 144 | 145 | 146 | 147 | regFiles i_regFiles 148 | ( 149 | .regFileX_dnxt(regFileX_dnxt), 150 | .regFileX_qout(regFileX_qout), 151 | 152 | .CLK(CLK), 153 | .RSTn(RSTn) 154 | ); 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | endmodule 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/regFiles.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: regFiles 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-21 14:34:23 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:05:43 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | `include "define.vh" 28 | 29 | module regFiles 30 | ( 31 | 32 | output [(64*`RP*32)-1:0] regFileX_qout, 33 | input [(64*`RP*32)-1:0] regFileX_dnxt, 34 | 35 | input CLK, 36 | input RSTn 37 | ); 38 | 39 | assign regFileX_qout[64*`RP-1:0] = {64*`RP{1'b0}}; 40 | 41 | generate 42 | 43 | for ( genvar regNum = 1; regNum < 32; regNum = regNum + 1 ) begin 44 | for ( genvar depth = 0 ; depth < `RP; depth = depth + 1 ) begin 45 | 46 | localparam SEL = regNum*4+depth; 47 | 48 | gen_dffr #(.DW(64)) int_regX ( .dnxt(regFileX_dnxt[64*SEL +: 64]), .qout(regFileX_qout[64*SEL +: 64]), .CLK(CLK), .RSTn(RSTn) ); 49 | 50 | end 51 | end 52 | 53 | 54 | 55 | endgenerate 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | endmodule 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/rename.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: rename 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-09-19 14:29:53 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:35 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | 28 | `include "define.vh" 29 | 30 | 31 | module rename ( 32 | 33 | output [ `RB*32 - 1 :0 ] rnAct_X_dnxt, 34 | input [ `RB*32 - 1 :0 ] rnAct_X_qout, 35 | 36 | output [32*`RP-1 : 0] rnBufU_rename_set, 37 | input [32*`RP-1 : 0] rnBufU_qout, 38 | 39 | input [4:0] rs1_raw, 40 | output [5+`RB-1:0] rs1_reName, 41 | 42 | input [4:0] rs2_raw, 43 | output [5+`RB-1:0] rs2_reName, 44 | 45 | input rd0_raw_valid, 46 | input [4:0] rd0_raw, 47 | output [5+`RB-1:0] rd0_reName, 48 | output rd0_runOut 49 | 50 | ); 51 | 52 | 53 | wire [`RB-1:0] rd0_malloc; 54 | assign rd0_reName = {rd0_raw, rd0_malloc}; 55 | 56 | generate 57 | for ( genvar i = 0; i < 32; i = i + 1 )begin 58 | assign rnAct_X_dnxt[`RB*i +: `RB] = ( (rd0_raw == i) & rd0_raw_valid & ~rd0_runOut ) ? rd0_malloc : rnAct_X_qout[`RB*i +: `RB]; 59 | end 60 | endgenerate 61 | 62 | 63 | assign rs1_reName = {rs1_raw, rnAct_X_qout[rs1_raw*`RB +: `RB]}; 64 | assign rs2_reName = {rs2_raw, rnAct_X_qout[rs2_raw*`RB +: `RB]}; 65 | 66 | 67 | 68 | wire [`RP-1:0] regX_used = rnBufU_qout[ `RP*rd0_raw +: `RP ]; 69 | 70 | lzp #( 71 | .CW(`RB) 72 | ) rd0_index( 73 | .in_i(regX_used), 74 | .pos_o(rd0_malloc), 75 | .all0(), 76 | .all1(rd0_runOut) 77 | ); 78 | 79 | 80 | 81 | assign rnBufU_rename_set = (rd0_raw_valid & ~rd0_runOut) 82 | ? {32*`RP{1'b0}} | (1'b1 << rd0_reName) 83 | : {32*`RP{1'b0}}; 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | endmodule 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | -------------------------------------------------------------------------------- /RiftChip/riftCore/backend/writeBack.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: writeBack 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-09-11 15:41:38 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:34 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | `include "define.vh" 28 | 29 | module writeBack ( 30 | 31 | //from phyRegister 32 | input [(64*`RP*32)-1:0] regFileX_qout, 33 | output [(64*`RP*32)-1:0] regFileX_dnxt, 34 | 35 | output [32*`RP-1 : 0] wbLog_writeb_set, 36 | 37 | 38 | //from adder 39 | input alu_writeback_valid, 40 | input [63:0] alu_res, 41 | input [(5+`RB-1):0] alu_rd0, 42 | 43 | //from bru 44 | input bru_writeback_valid, 45 | input [(5+`RB-1):0] bru_rd0, 46 | input [63:0] bru_res, 47 | 48 | //from lsu 49 | input lsu_writeback_valid, 50 | input [(5+`RB-1):0] lsu_rd0, 51 | input [63:0] lsu_res, 52 | 53 | //from csr 54 | input csr_writeback_valid, 55 | input [(5+`RB-1):0] csr_rd0, 56 | input [63:0] csr_res, 57 | 58 | //from mul 59 | input mul_writeback_valid, 60 | input [(5+`RB-1):0] mul_rd0, 61 | input [63:0] mul_res 62 | ); 63 | 64 | // alu wb 65 | wire [(64*`RP*32)-1:0] alu_writeback_dnxt; 66 | //bru wb 67 | wire [(64*`RP*32)-1:0] bru_writeback_dnxt; 68 | //lsu wb 69 | wire [(64*`RP*32)-1:0] lsu_writeback_dnxt; 70 | //csr wb 71 | wire [(64*`RP*32)-1:0] csr_writeback_dnxt; 72 | //mul wb 73 | wire [(64*`RP*32)-1:0] mul_writeback_dnxt; 74 | 75 | //write back 76 | assign regFileX_dnxt[0 +: 64*`RP] = {64*`RP{1'b0}}; 77 | generate 78 | for ( genvar SEL = `RP; SEL < 32*`RP; SEL = SEL + 1 ) begin 79 | // localparam SEL = regNum*`RP+depth; 80 | 81 | assign regFileX_dnxt[64*SEL +: 64] = 82 | ( 83 | //adder wb 84 | ({64{alu_writeback_valid & (alu_rd0 == SEL)}} & alu_res) 85 | | 86 | //bru wb 87 | ({64{bru_writeback_valid & (bru_rd0 == SEL)}} & bru_res) 88 | | 89 | //lsu wb 90 | ({64{lsu_writeback_valid & (lsu_rd0 == SEL)}} & lsu_res) 91 | | 92 | //csr wb 93 | ({64{csr_writeback_valid & (csr_rd0 == SEL)}} & csr_res) 94 | | 95 | //mul wb 96 | ({64{mul_writeback_valid & (mul_rd0 == SEL)}} & mul_res) 97 | ) 98 | | 99 | ( 100 | //nobody wb 101 | ( 102 | 103 | {64{ ~(alu_writeback_valid & alu_rd0 == SEL) 104 | & ~(bru_writeback_valid & bru_rd0 == SEL) 105 | & ~(lsu_writeback_valid & lsu_rd0 == SEL) 106 | & ~(csr_writeback_valid & csr_rd0 == SEL) 107 | & ~(mul_writeback_valid & mul_rd0 == SEL) }} 108 | ) 109 | & regFileX_qout[64*SEL +: 64] 110 | ); 111 | 112 | 113 | 114 | end 115 | endgenerate 116 | 117 | 118 | assign wbLog_writeb_set = 119 | ( alu_writeback_valid << alu_rd0 ) 120 | | 121 | ( bru_writeback_valid << bru_rd0 ) 122 | | 123 | ( lsu_writeback_valid << lsu_rd0 ) 124 | | 125 | ( csr_writeback_valid << csr_rd0 ) 126 | | 127 | ( mul_writeback_valid << mul_rd0 ) 128 | ; 129 | 130 | 131 | 132 | 133 | 134 | endmodule 135 | 136 | -------------------------------------------------------------------------------- /RiftChip/riftCore/cache/cache_mem.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: cache_mem 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-02-22 10:00:20 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-24 17:43:51 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | 28 | 29 | `timescale 1 ns / 1 ps 30 | 31 | `include "define.vh" 32 | 33 | 34 | module cache_mem # 35 | ( 36 | parameter DW = 1024, 37 | parameter BK = 4, 38 | parameter CB = 1, 39 | parameter CL = 256, 40 | parameter TAG_W = 32 41 | 42 | ) 43 | ( 44 | input [31:0] cache_addr, 45 | input [CB-1:0] cache_en_w, 46 | input [CB-1:0] cache_en_r, 47 | input [7:0] cache_info_wstrb, 48 | input [63:0] cache_info_w, 49 | output [64*CB-1:0] cache_info_r, 50 | 51 | 52 | input [31:0] tag_addr, 53 | input [CB-1:0] tag_en_w, 54 | input [CB-1:0] tag_en_r, 55 | input [(TAG_W+7)/8-1:0] tag_info_wstrb, 56 | input [TAG_W-1:0] tag_info_w, 57 | output [TAG_W*CB-1:0] tag_info_r, 58 | 59 | input CLK, 60 | input RSTn 61 | ); 62 | 63 | localparam ADDR_LSB = $clog2(DW*BK/8); 64 | localparam LINE_W = $clog2(CL); 65 | 66 | 67 | wire [$clog2(BK)-1:0] bank_sel = cache_addr[ ADDR_LSB-1 -: $clog2(BK)]; 68 | wire [LINE_W-1:0] cache_address_sel = cache_addr[ADDR_LSB +: LINE_W]; 69 | wire [$clog2(DW/8)-1:0] data_sel = cache_addr[ADDR_LSB-$clog2(BK)-1:0]; 70 | 71 | wire [LINE_W-1:0] tag_address_sel = tag_addr[ADDR_LSB +: LINE_W]; 72 | wire [TAG_W-1:0] tag_sel = tag_addr[31 -: TAG_W]; 73 | 74 | wire [CB*BK-1:0] cache_bank_en_w; 75 | wire [CB*BK-1:0] cache_bank_en_r; 76 | wire [DW*BK*CB-1:0] cache_bank_data_r; 77 | wire [DW/8-1:0] cache_bank_wstrb = cache_info_wstrb << data_sel; 78 | 79 | 80 | generate 81 | for ( genvar cb = 0 ; cb < CB; cb = cb + 1 ) begin 82 | 83 | gen_sram # ( .DW((TAG_W)), .AW(LINE_W)) tag_ram 84 | ( 85 | .data_w(tag_info_w), 86 | .addr_w(tag_address_sel), 87 | .data_wstrb(tag_info_wstrb), 88 | .en_w(tag_en_w[cb]), 89 | 90 | .data_r(tag_info_r[TAG_W*cb +: TAG_W]), 91 | .addr_r(tag_address_sel), 92 | .en_r(tag_en_r[cb]), 93 | 94 | .CLK(CLK) 95 | ); 96 | 97 | for ( genvar bk = 0; bk < BK; bk = bk + 1 ) begin 98 | assign cache_bank_en_w[BK*cb+bk] = ( bank_sel == bk ) & cache_en_w[cb]; 99 | assign cache_bank_en_r[BK*cb+bk] = ( bank_sel == bk ) & cache_en_r[cb]; 100 | 101 | 102 | gen_sram # ( .DW(DW), .AW(LINE_W)) cache_bank_ram 103 | ( 104 | .data_w({(DW/64){cache_info_w}}), 105 | .addr_w(cache_address_sel), 106 | .data_wstrb(cache_bank_wstrb), 107 | .en_w(cache_bank_en_w[cb*BK+bk]), 108 | 109 | .data_r(cache_bank_data_r[DW*(cb*BK+bk) +: DW]), 110 | .addr_r(cache_address_sel), 111 | .en_r(cache_bank_en_r[cb*BK+bk]), 112 | 113 | .CLK(CLK) 114 | ); 115 | 116 | end 117 | 118 | wire [DW*BK-1:0] cache_block_data_r = cache_bank_data_r[DW*BK*cb +: DW*BK]; 119 | wire [DW-1:0] cache_data_r = cache_block_data_r[ DW*bank_sel +: DW ]; 120 | assign cache_info_r[64*cb +: 64] = cache_data_r[ 8*data_sel +: 64]; 121 | 122 | end 123 | endgenerate 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | endmodule 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | -------------------------------------------------------------------------------- /RiftChip/riftCore/cache/dirty_block.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: dirty_block 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-02-22 17:33:10 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-04 17:54:08 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | `include "define.vh" 31 | 32 | 33 | 34 | module dirty_block # 35 | ( 36 | parameter DW = 32, 37 | parameter DP = 16 38 | ) 39 | ( 40 | 41 | input push, 42 | input [DW-1:0] addr_i, 43 | 44 | input pop, 45 | output [DW-1:0] addr_o, 46 | 47 | output empty, 48 | output full, 49 | 50 | input CLK, 51 | input RSTn 52 | ); 53 | 54 | localparam CW = $clog2(DP); 55 | 56 | 57 | wire [CW-1:0] index; 58 | wire [CW-1:0] index_push; 59 | wire [CW-1:0] index_pop; 60 | wire [DW*DP-1:0] info_o; 61 | 62 | wire [DP-1:0] valid; 63 | wire [DP-1:0] addr_chk; 64 | wire push_chk; 65 | wire ppbuff_full; 66 | 67 | 68 | // push will be block when there is a same record in buff 69 | generate 70 | for ( genvar i = 0 ; i < DP; i = i + 1 ) begin 71 | assign addr_chk[i] = valid[i] & (addr_i == (info_o[ DW*i +: DW])); 72 | end 73 | endgenerate 74 | 75 | assign push_chk = push & ~(| addr_chk); 76 | 77 | 78 | 79 | 80 | 81 | assign full = ppbuff_full & ~(| addr_chk); 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | gen_ppbuff # ( .DW(DW), .DP(DP) ) 90 | dirty_index 91 | ( 92 | .pop(pop), 93 | .push(push_chk), 94 | .index(index), 95 | 96 | .info_i(addr_i), 97 | .info_o(info_o), 98 | 99 | .empty(empty), 100 | .full(ppbuff_full), 101 | .valid(valid), 102 | 103 | .flush(1'b0), 104 | .CLK(CLK), 105 | .RSTn(RSTn) 106 | 107 | ); 108 | 109 | 110 | assign index = 111 | ({CW{push_chk & ~pop}} & index_push) 112 | | 113 | ({CW{pop & ~push_chk}} & index_pop) 114 | | 115 | ({CW{pop & push_chk}} & index_pop); 116 | 117 | 118 | assign addr_o = info_o[ DW*index_pop +: DW]; 119 | 120 | 121 | lzp #( .CW(CW) ) buff_push 122 | ( 123 | .in_i(valid), 124 | .pos_o(index_push), 125 | .all0(), 126 | .all1() 127 | ); 128 | 129 | 130 | lzp #( .CW(CW) ) buff_pop 131 | ( 132 | .in_i(~valid), 133 | .pos_o(index_pop), 134 | .all0(), 135 | .all1() 136 | ); 137 | 138 | 139 | 140 | 141 | endmodule 142 | 143 | 144 | -------------------------------------------------------------------------------- /RiftChip/riftCore/cache/wt_block.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: wt_block 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-03-12 10:33:54 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-17 18:04:50 8 | */ 9 | 10 | 11 | 12 | /* 13 | Copyright (c) 2020 - 2021 Ruige Lee 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | 28 | `timescale 1 ns / 1 ps 29 | `include "define.vh" 30 | 31 | 32 | 33 | module wt_block # 34 | ( 35 | parameter DW = 64 + 8 + 32, 36 | parameter DP = 8, 37 | parameter TAG_W = 32 38 | ) 39 | ( 40 | input [31:0] chkAddr, 41 | output isHazard_r, 42 | 43 | input push, 44 | input [DW-1:0] data_i, 45 | 46 | input pop, 47 | output [DW-1:0] data_o, 48 | 49 | input commit, 50 | output isOpin_O, 51 | output isOpin_W, 52 | output empty, 53 | output full, 54 | 55 | input flush, 56 | input CLK, 57 | input RSTn 58 | ); 59 | 60 | 61 | 62 | 63 | 64 | 65 | // assign io_access = (& (~lsu_op1[63:32]) ) & ~lsu_op1[31] & ~lsu_op1[30]; 66 | // assign mem_access = (& (~lsu_op1[63:32]) ) & lsu_op1[31]; 67 | 68 | 69 | 70 | wire [DP-1:0] isAddrHit_r; 71 | wire [DP-1:0] Op_O; 72 | wire [DP-1:0] Op_W; 73 | 74 | generate 75 | for ( genvar dp = 0; dp < DP; dp = dp + 1 ) begin 76 | 77 | wire [31:0] wtb_addr_qout = wtb_info_qout[ DW*dp +: 32]; 78 | 79 | assign Op_O[dp] = ~wtb_addr_qout[31] & ~wtb_addr_qout[30]; 80 | assign Op_W[dp] = wtb_addr_qout[31]; 81 | 82 | assign isAddrHit_r[dp] = 83 | (Op_W[dp] & ( chkAddr[31 -: TAG_W] == wtb_addr_qout[31 -: TAG_W] ) & valid_qout[dp]) 84 | | (Op_O[dp] & ( chkAddr == wtb_addr_qout ) & valid_qout[dp]); 85 | 86 | end 87 | endgenerate 88 | 89 | assign isHazard_r = | isAddrHit_r; 90 | assign isOpin_O = | Op_O; 91 | assign isOpin_W = | Op_W; 92 | 93 | assign data_o = wtb_info_qout[DW*rdp_qout[AW-1:0]+:DW]; 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | wire [DW*DP-1:0] wtb_info_dnxt; 102 | wire [DW*DP-1:0] wtb_info_qout; 103 | wire [DP-1:0] wtb_info_en; 104 | 105 | wire [DP-1:0] valid_dnxt; 106 | wire [DP-1:0] valid_qout; 107 | wire [DP-1:0] valid_en; 108 | 109 | wire [DP-1:0] commit_dnxt; 110 | wire [DP-1:0] commit_qout; 111 | // wire [DP-1:0] commit_en; 112 | 113 | 114 | 115 | localparam AW = $clog2(DP); 116 | 117 | 118 | 119 | 120 | assign wtb_info_en = {DP{push}} & ((1 << wrp_qout[AW-1:0])); 121 | 122 | 123 | assign valid_en = 124 | ({DP{pop }} & (1 << rdp_qout[AW-1:0])) 125 | | ({DP{push}} & (1 << wrp_qout[AW-1:0])) 126 | | flush; 127 | 128 | 129 | 130 | 131 | // assign commit_en = 132 | // ({DP{pop }} & (1 << rdp_qout[AW-1:0])) 133 | // | ({DP{commit}} & (1 << ccp_qout[AW-1:0])); 134 | 135 | 136 | assign commit_dnxt = 137 | ( 138 | commit_qout 139 | & ~({DP{pop }} & (1 << rdp_qout[AW-1:0])) 140 | ) 141 | | ({DP{commit}} & (1 << ccp_qout[AW-1:0])); 142 | 143 | generate 144 | for ( genvar dp = 0; dp < DP; dp = dp + 1 ) begin 145 | 146 | 147 | assign wtb_info_dnxt[DW*dp+:DW] = data_i; 148 | assign valid_dnxt[dp] = flush ? commit_dnxt[dp] : (push & wrp_qout[AW-1:0] == dp ); 149 | // assign commit_dnxt[dp] = commit & (ccp_qout[AW-1:0] == dp); 150 | 151 | 152 | 153 | gen_dffren # (.DW(DW)) wtb_info_dffren 154 | ( 155 | .dnxt(wtb_info_dnxt[DW*dp +: DW]), 156 | .qout(wtb_info_qout[DW*dp +: DW]), 157 | .en(wtb_info_en[dp]), 158 | .CLK(CLK), 159 | .RSTn(RSTn) 160 | ); 161 | 162 | 163 | gen_dffr # (.DW(1)) commit_dffr 164 | ( 165 | .dnxt(commit_dnxt[dp]), 166 | .qout(commit_qout[dp]), 167 | // .en(commit_en[dp]), 168 | .CLK(CLK), 169 | .RSTn(RSTn) 170 | ); 171 | 172 | 173 | 174 | 175 | gen_dffren # (.DW(1)) valid_dffren 176 | ( 177 | .dnxt(valid_dnxt[dp]), 178 | .qout(valid_qout[dp]), 179 | .en(valid_en[dp]), 180 | .CLK(CLK), 181 | .RSTn(RSTn) 182 | ); 183 | 184 | end 185 | 186 | endgenerate 187 | 188 | 189 | 190 | 191 | 192 | 193 | wire [AW+1-1:0] rdp_dnxt; 194 | wire [AW+1-1:0] rdp_qout; 195 | wire [AW+1-1:0] wrp_dnxt; 196 | wire [AW+1-1:0] wrp_qout; 197 | wire [AW+1-1:0] ccp_dnxt; 198 | wire [AW+1-1:0] ccp_qout; 199 | 200 | 201 | gen_dffr #( .DW(AW+1) ) rdp_dffr ( .dnxt(rdp_dnxt), .qout(rdp_qout), .CLK(CLK), .RSTn(RSTn)); 202 | gen_dffr #( .DW(AW+1) ) wrp_dffr ( .dnxt(wrp_dnxt), .qout(wrp_qout), .CLK(CLK), .RSTn(RSTn)); 203 | gen_dffr #( .DW(AW+1) ) ccp_dffr ( .dnxt(ccp_dnxt), .qout(ccp_qout), .CLK(CLK), .RSTn(RSTn)); 204 | 205 | 206 | assign rdp_dnxt = pop ? rdp_qout + 'd1 : rdp_qout; 207 | assign wrp_dnxt = flush ? ccp_qout : (push ? wrp_qout + 'd1 : wrp_qout); 208 | assign ccp_dnxt = commit ? ccp_qout + 'd1 : ccp_qout; 209 | 210 | 211 | assign full = (wrp_qout[AW-1:0] == rdp_qout[AW-1:0]) & (wrp_qout[AW] != rdp_qout[AW]); 212 | assign empty = ccp_qout == rdp_qout; 213 | 214 | 215 | 216 | 217 | 218 | //ASSERT 219 | always @( negedge CLK ) begin 220 | 221 | if (0) begin 222 | $display("Assert Fail at wtb_block"); 223 | $stop; 224 | end 225 | 226 | end 227 | 228 | 229 | 230 | 231 | 232 | 233 | endmodule 234 | 235 | 236 | 237 | 238 | 239 | 240 | -------------------------------------------------------------------------------- /RiftChip/riftCore/frontEnd.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: frontEnd 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-31 15:42:48 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-17 15:02:39 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | `include "define.vh" 29 | 30 | module frontEnd ( 31 | 32 | input lsu_fencei_valid, 33 | 34 | //to MEM 35 | output [31:0] IL1_ARADDR, 36 | output [7:0] IL1_ARLEN, 37 | output [1:0] IL1_ARBURST, 38 | output IL1_ARVALID, 39 | input IL1_ARREADY, 40 | 41 | input [63:0] IL1_RDATA, 42 | input [1:0] IL1_RRESP, 43 | input IL1_RLAST, 44 | input IL1_RVALID, 45 | output IL1_RREADY, 46 | 47 | input instrFifo_reject, 48 | output instrFifo_push, 49 | output [`DECODE_INFO_DW-1:0] decode_microInstr, 50 | 51 | input bru_res_valid, 52 | input bru_takenBranch, 53 | input jalr_valid, 54 | input [63:0] jalr_pc, 55 | 56 | input [63:0] privileged_pc, 57 | input privileged_valid, 58 | 59 | output flush, 60 | input CLK, 61 | input RSTn 62 | 63 | ); 64 | 65 | 66 | wire branch_pc_valid; 67 | wire [63:0] branch_pc; 68 | wire [63:0] pc_ic_addr; 69 | wire pc_ic_ready; 70 | wire [63:0] ic_iq_pc; 71 | wire [63:0] ic_iq_instr; 72 | wire ic_iq_valid; 73 | wire ic_iq_ready; 74 | wire iq_id_valid; 75 | wire [32+64+1-1:0] iq_id_info; 76 | wire iq_id_ready; 77 | wire isMisPredict; 78 | 79 | wire fencei_stall; 80 | 81 | 82 | assign flush = isMisPredict | privileged_valid; 83 | 84 | 85 | pcGenerate i_pcGenerate( 86 | .privileged_pc(privileged_pc), 87 | .privileged_valid(privileged_valid), 88 | 89 | .branch_pc_valid(branch_pc_valid), 90 | .branch_pc(branch_pc), 91 | 92 | .fetch_addr_qout(pc_ic_addr), 93 | .pcGen_fetch_ready(pc_ic_ready), 94 | 95 | .flush(flush|branch_pc_valid), 96 | .CLK(CLK), 97 | .RSTn(RSTn) 98 | ); 99 | 100 | 101 | 102 | icache i_cache 103 | ( 104 | .IL1_ARADDR (IL1_ARADDR), 105 | .IL1_ARLEN (IL1_ARLEN), 106 | .IL1_ARBURST (IL1_ARBURST), 107 | .IL1_ARVALID (IL1_ARVALID), 108 | .IL1_ARREADY (IL1_ARREADY), 109 | .IL1_RDATA (IL1_RDATA), 110 | .IL1_RRESP (IL1_RRESP), 111 | .IL1_RLAST (IL1_RLAST), 112 | .IL1_RVALID (IL1_RVALID), 113 | .IL1_RREADY (IL1_RREADY), 114 | 115 | .pc_ic_addr(pc_ic_addr), 116 | .pc_ic_ready(pc_ic_ready), 117 | 118 | .ic_iq_pc(ic_iq_pc), 119 | .ic_iq_instr(ic_iq_instr), 120 | .ic_iq_valid(ic_iq_valid), 121 | .ic_iq_ready(ic_iq_ready), 122 | 123 | 124 | .il1_fence(fencei_stall), 125 | 126 | .flush(flush|branch_pc_valid), 127 | .CLK(CLK), 128 | .RSTn(RSTn) 129 | 130 | 131 | ); 132 | 133 | 134 | 135 | iqueue i_iqueue( 136 | 137 | .lsu_fencei_valid(lsu_fencei_valid), 138 | 139 | .fencei_stall (fencei_stall), 140 | .ic_iq_pc(ic_iq_pc), 141 | .ic_iq_instr(ic_iq_instr), 142 | .ic_iq_valid(ic_iq_valid), 143 | .ic_iq_ready(ic_iq_ready), 144 | 145 | .branch_pc_valid(branch_pc_valid), 146 | .branch_pc(branch_pc), 147 | 148 | .jalr_valid(jalr_valid), 149 | .jalr_pc(jalr_pc), 150 | .bru_res_valid(bru_res_valid), 151 | .bru_takenBranch(bru_takenBranch), 152 | 153 | .iq_id_valid(iq_id_valid), 154 | .iq_id_info(iq_id_info), 155 | .iq_id_ready(iq_id_ready), 156 | 157 | .isMisPredict(isMisPredict), 158 | 159 | .flush(flush), 160 | .CLK(CLK), 161 | .RSTn(RSTn) 162 | ); 163 | 164 | 165 | decoder i_decoder 166 | ( 167 | .iq_id_valid(iq_id_valid), 168 | .iq_id_ready(iq_id_ready), 169 | .iq_id_info(iq_id_info), 170 | 171 | .instrFifo_reject(instrFifo_reject), 172 | .decode_microInstr(decode_microInstr), 173 | .instrFifo_push(instrFifo_push), 174 | 175 | .flush(flush), 176 | .CLK(CLK), 177 | .RSTn(RSTn) 178 | 179 | ); 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | endmodule 190 | 191 | 192 | 193 | 194 | 195 | 196 | -------------------------------------------------------------------------------- /RiftChip/riftCore/frontend/branch_predict.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: branch_predict 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-05 16:42:46 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-19 16:27:01 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | 28 | 29 | `timescale 1 ns / 1 ps 30 | 31 | module branch_predict ( 32 | input isFencei, 33 | input lsu_fencei_valid, 34 | output fencei_stall, 35 | 36 | input isJal, 37 | input isJalr, 38 | input isBranch, 39 | input isCall, 40 | input isReturn, 41 | input [63:0] imm, 42 | input isRVC, 43 | input [63:0] pc_load, 44 | 45 | input jalr_valid, 46 | input [63:0] jalr_pc, 47 | input bru_res_valid, 48 | input bru_takenBranch, 49 | 50 | output branch_pc_valid, 51 | output [63:0] branch_pc, 52 | output isMisPredict, 53 | 54 | output jalr_stall, 55 | output bht_stall, 56 | input iq_id_ready, 57 | 58 | input flush, 59 | input CLK, 60 | input RSTn 61 | 62 | ); 63 | 64 | 65 | 66 | 67 | wire [63:0] next_pc; 68 | wire [63:0] take_pc; 69 | wire [63:0] resolve_pc; 70 | 71 | wire [63+1:0] bht_data_pop; 72 | wire [63+1:0] bht_data_push; 73 | 74 | wire isTakenBranch; 75 | wire bht_full; 76 | wire bht_pop; 77 | wire bht_push; 78 | 79 | wire jalr_stall; 80 | wire bht_stall; 81 | 82 | wire [63:0] ras_addr_pop; 83 | wire [63:0] ras_addr_push; 84 | wire ras_push; 85 | wire ras_pop; 86 | wire ras_empty; 87 | wire jalr_empty; 88 | wire jalr_last; 89 | wire jalr_front; 90 | 91 | 92 | 93 | assign bht_data_push = 94 | { 95 | isTakenBranch, 96 | (({64{~isTakenBranch}} & take_pc) | ({64{isTakenBranch}} & next_pc)) 97 | }; 98 | 99 | 100 | assign bht_pop = bru_res_valid; 101 | assign bht_push = isBranch & ~bht_full & iq_id_ready; 102 | 103 | assign isMisPredict = bru_res_valid & ( bru_takenBranch ^ bht_data_pop[64]); 104 | assign resolve_pc = bht_data_pop[63:0]; 105 | 106 | assign jalr_stall = isJalr & ~jalr_last & ( ras_empty | ~isReturn ); 107 | assign bht_stall = (bht_full & isBranch); 108 | assign fencei_stall = isFencei & ~lsu_fencei_valid; 109 | 110 | 111 | assign branch_pc_valid = 112 | isMisPredict //mis-predict 113 | | isTakenBranch // bru jump, jal jump, jalr ras pop 114 | | jalr_last //jalr return 115 | | (isFencei & lsu_fencei_valid) 116 | ; 117 | 118 | 119 | assign branch_pc = ({64{isMisPredict}} & resolve_pc) 120 | | 121 | ({64{isTakenBranch& ~isMisPredict}} & take_pc) 122 | | 123 | ({64{jalr_last}} & jalr_pc ) 124 | | 125 | ({64{isFencei & lsu_fencei_valid}} & next_pc); 126 | 127 | 128 | 129 | //static predict 130 | assign isTakenBranch = ( (isBranch) & ( imm[63] == 1'b0) ) 131 | | (isJal | ras_pop); 132 | 133 | 134 | 135 | 136 | 137 | 138 | assign ras_push = isCall & ( isJal | isJalr ) & iq_id_ready; 139 | assign ras_pop = isReturn & ( isJalr ) & ( !ras_empty ) & iq_id_ready; 140 | 141 | assign next_pc = pc_load + ( isRVC ? 64'd2 : 64'd4 ); 142 | assign take_pc = ( {64{isJal | isBranch}} & (pc_load + imm) ) 143 | | ( {64{ras_pop}} & ras_addr_pop ); 144 | 145 | assign ras_addr_push = next_pc; 146 | 147 | 148 | 149 | 150 | 151 | gen_fifo # ( .DW(64+1), .AW(4) ) bht( 152 | .fifo_pop(bht_pop), .fifo_push(bht_push), 153 | .data_push(bht_data_push), .data_pop(bht_data_pop), 154 | .fifo_empty(), .fifo_full(bht_full), 155 | 156 | .flush(flush), 157 | .CLK(CLK), 158 | .RSTn(RSTn) 159 | ); 160 | 161 | 162 | 163 | 164 | assign jalr_last = jalr_valid & jalr_empty; 165 | assign jalr_front = jalr_valid & ~jalr_empty; 166 | 167 | 168 | gen_ringStack # (.DW(64), .AW(4)) ras( 169 | .stack_pop(ras_pop), .stack_push(ras_push), 170 | .stack_empty(ras_empty), 171 | .data_pop(ras_addr_pop), .data_push(ras_addr_push), 172 | 173 | .flush(flush), 174 | .CLK(CLK), 175 | .RSTn(RSTn) 176 | ); 177 | 178 | gen_fifo # ( .DW(1), .AW(4) ) ras_cnt( 179 | .fifo_pop(jalr_front), .fifo_push(ras_pop), 180 | .data_push(1'b0), .data_pop(), 181 | .fifo_empty(jalr_empty), .fifo_full(), 182 | 183 | .flush(flush), 184 | .CLK(CLK), 185 | .RSTn(RSTn) 186 | ); 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | endmodule 196 | 197 | 198 | 199 | 200 | -------------------------------------------------------------------------------- /RiftChip/riftCore/frontend/decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: decoder 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-12-09 17:28:05 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-02-05 20:08:15 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | `timescale 1 ns / 1 ps 27 | `include "define.vh" 28 | 29 | 30 | 31 | module decoder 32 | ( 33 | input iq_id_valid, 34 | output iq_id_ready, 35 | input [32+64+1-1:0] iq_id_info, 36 | 37 | input instrFifo_reject, 38 | output [`DECODE_INFO_DW-1:0] decode_microInstr, 39 | output instrFifo_push, 40 | 41 | input flush, 42 | input CLK, 43 | input RSTn 44 | 45 | ); 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | wire [`DECODE_INFO_DW-1:0] decode_microInstr_16; 54 | wire [`DECODE_INFO_DW-1:0] decode_microInstr_32; 55 | 56 | 57 | wire bp_valid_i; 58 | wire bp_valid_o; 59 | wire bp_ready_i; 60 | wire bp_ready_o; 61 | 62 | wire [32+64+1-1:0] bp_data_i; 63 | wire [32+64+1-1:0] bp_data_o; 64 | 65 | assign iq_id_ready = ~instrFifo_reject & bp_ready_i; 66 | 67 | assign bp_valid_i = iq_id_valid; 68 | assign bp_ready_o = ~instrFifo_reject; 69 | assign bp_data_i = iq_id_info; 70 | 71 | gen_bypassfifo #( .DW(32+64+1) ) bp_fifo 72 | ( 73 | .valid_i(bp_valid_i), 74 | .data_i(bp_data_i), 75 | .ready_i(bp_ready_i), 76 | 77 | .valid_o(bp_valid_o), 78 | .data_o(bp_data_o), 79 | .ready_o(bp_ready_o), 80 | 81 | .flush(flush), 82 | .CLK(CLK), 83 | .RSTn(RSTn) 84 | ); 85 | 86 | 87 | wire privil_accessFault; 88 | wire [`DECODE_INFO_DW-1:0] accessFault_info; 89 | 90 | wire [63:0] id_pc = bp_data_o[64:1]; 91 | wire [31:0] id_instr32 = bp_data_o[96:65]; 92 | wire [15:0] id_instr16 = bp_data_o[80:65]; 93 | wire isRVC = bp_data_o[0]; 94 | 95 | assign privil_accessFault = bp_valid_o & bp_ready_o & ( |id_pc[63:32] ); 96 | 97 | 98 | 99 | assign accessFault_info = { 1'b0, 1'b0, 1'b0, 1'b0, 100 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 101 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 102 | 1'b0, 1'b0, 1'b0, 1'b0, 103 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 104 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 105 | 1'b0, 1'b0, 106 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 107 | 1'b0, 1'b0, 1'b0, 108 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 109 | 1'b1, 1'b0, 110 | 1'b0, 111 | id_pc, 64'b0, 6'b0, 5'd0,5'b0,5'b0 112 | }; 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | decoder16 i_decoder16 121 | ( 122 | .instr(id_instr16), 123 | .pc(id_pc), 124 | .is_rvc(isRVC), 125 | 126 | .decode_microInstr(decode_microInstr_16) 127 | ); 128 | 129 | 130 | 131 | decoder32 i_decoder32 132 | ( 133 | .instr(id_instr32), 134 | .pc(id_pc), 135 | .is_rvc(isRVC), 136 | 137 | .decode_microInstr(decode_microInstr_32) 138 | ); 139 | 140 | 141 | assign decode_microInstr = (~privil_accessFault) ? 142 | (isRVC ? decode_microInstr_16 : decode_microInstr_32) 143 | : accessFault_info; 144 | assign instrFifo_push = bp_valid_o & ~instrFifo_reject; 145 | 146 | 147 | 148 | 149 | 150 | 151 | endmodule 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | -------------------------------------------------------------------------------- /RiftChip/riftCore/frontend/iAlign.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: iAlign 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-11 10:11:32 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-10 17:29:14 8 | */ 9 | 10 | 11 | 12 | 13 | /* 14 | Copyright (c) 2020 - 2021 Ruige Lee 15 | 16 | Licensed under the Apache License, Version 2.0 (the "License"); 17 | you may not use this file except in compliance with the License. 18 | You may obtain a copy of the License at 19 | 20 | http://www.apache.org/licenses/LICENSE-2.0 21 | 22 | Unless required by applicable law or agreed to in writing, software 23 | distributed under the License is distributed on an "AS IS" BASIS, 24 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | See the License for the specific language governing permissions and 26 | limitations under the License. 27 | */ 28 | 29 | `timescale 1 ns / 1 ps 30 | `include "define.vh" 31 | 32 | //now if pc is 64bit align 33 | module iAlign ( 34 | 35 | input [63:0] ic_iq_pc, 36 | input [63:0] ic_iq_instr, 37 | 38 | output [63:0] align_instr, 39 | output [3:0] align_instr_mask 40 | 41 | ); 42 | 43 | wire [2:0] pc_lsb = ic_iq_pc[2:0]; 44 | 45 | 46 | assign align_instr = 47 | ( {64{pc_lsb == 3'b000}} & ic_iq_instr) 48 | | 49 | ( {64{pc_lsb == 3'b010}} & {16'b0, ic_iq_instr[63:16]} ) 50 | | 51 | ( {64{pc_lsb == 3'b100}} & {32'b0, ic_iq_instr[63:32]}) 52 | | 53 | ( {64{pc_lsb == 3'b110}} & {48'b0, ic_iq_instr[63:48]}); 54 | 55 | assign align_instr_mask = 56 | ( {4{pc_lsb == 3'b000}} & 4'b1111) 57 | | 58 | ( {4{pc_lsb == 3'b010}} & 4'b0111 ) 59 | | 60 | ( {4{pc_lsb == 3'b100}} & 4'b0011) 61 | | 62 | ( {4{pc_lsb == 3'b110}} & 4'b0001); 63 | 64 | 65 | 66 | 67 | 68 | endmodule 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | -------------------------------------------------------------------------------- /RiftChip/riftCore/frontend/pcGenerate.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: pcGenerate 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-10-13 16:56:39 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-12 11:39:52 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | `include "define.vh" 31 | 32 | module pcGenerate ( 33 | 34 | // from expection 35 | input [63:0] privileged_pc, 36 | input privileged_valid, 37 | 38 | //from instr_queue, 39 | input branch_pc_valid, 40 | input [63:0] branch_pc, 41 | 42 | //to ifetch 43 | output [63:0] fetch_addr_qout, 44 | input pcGen_fetch_ready, 45 | 46 | input flush, 47 | input CLK, 48 | input RSTn 49 | 50 | ); 51 | 52 | 53 | wire [63:0] fetch_addr_dnxt; 54 | 55 | 56 | 57 | 58 | 59 | 60 | assign fetch_addr_dnxt = 61 | privileged_valid ? privileged_pc : 62 | (branch_pc_valid ? branch_pc : ( (fetch_addr_qout&(~64'b111)) + 64'd8)); 63 | 64 | 65 | 66 | 67 | 68 | 69 | gen_dffren # (.DW(64), .rstValue(64'h8000_0000)) fetch_addr_en ( .dnxt(fetch_addr_dnxt), .qout(fetch_addr_qout), .en(pcGen_fetch_ready|flush), .CLK(CLK), .RSTn(RSTn)); 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | endmodule 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | -------------------------------------------------------------------------------- /RiftChip/riftCore/frontend/preDecode.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: preDecode 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-05 16:23:28 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-11 11:04:35 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | 28 | 29 | `timescale 1 ns / 1 ps 30 | 31 | 32 | 33 | 34 | module preDecode ( 35 | input [255:0] instr_load, 36 | input [15:0] iq_instr_mask_load, 37 | 38 | output instr_buf_empty, 39 | output isJal, 40 | output isJalr, 41 | output isBranch, 42 | output isCall, 43 | output isReturn, 44 | output isRVC, 45 | output isFencei, 46 | output [63:0] imm 47 | ); 48 | 49 | assign instr_buf_empty = ((iq_instr_mask_load[1] != 1'b1) & instr_load[1:0] == 2'b11) 50 | | 51 | ((iq_instr_mask_load[0] != 1'b1) ); 52 | 53 | wire [31:0] instr = instr_load[31:0]; 54 | 55 | assign isRVC = ~instr_buf_empty & (instr[1:0] != 2'b11); 56 | 57 | wire isIJal = ~isRVC & (instr[6:0] == 7'b1101111); 58 | wire isCJal = instr[1:0] == 2'b01 & instr[15:13] == 3'b101; 59 | 60 | wire isIJalr = ~isRVC & (instr[6:0] == 7'b1100111); 61 | wire isCJalr = (instr[1:0] == 2'b10 & instr[15:13] == 3'b100) 62 | & 63 | ( 64 | (~instr[12] & (instr[6:2] == 0)) 65 | | 66 | ( instr[12] & (|instr[11:7]) & (&(~instr[6:2]))) 67 | ); 68 | 69 | wire isIBranch = ~isRVC & (instr[6:0] == 7'b1100011); 70 | wire isCBranch = instr[1:0] == 2'b01 & instr[15:14] == 2'b11; 71 | 72 | wire isICall = (isIJalr | isIJal) & ((instr[11:7] == 5'd1) | instr[11:7] == 5'd5); 73 | wire isCCall = isCJalr & instr[12]; 74 | 75 | wire isIReturn = isIJalr & ((instr[19:15] == 5'd1) | instr[19:15] == 5'd5) 76 | & (instr[19:15] != instr[11:7]); 77 | 78 | wire isCReturn = isCJalr & ~instr[12] 79 | & ((instr[11:7] == 5'd1) | (instr[11:7] == 5'd5)); 80 | 81 | 82 | wire [63:0] Iimm = 83 | ({64{isIJal}} & {{44{instr[31]}},instr[19:12],instr[20],instr[30:21],1'b0}) 84 | | 85 | ({64{isIJalr}} & {{52{instr[31]}},instr[31:20]}) 86 | | 87 | ({64{isIBranch}} & {{52{instr[31]}},instr[7],instr[30:25],instr[11:8],1'b0}); 88 | 89 | wire [63:0] Cimm = 90 | ({64{isCJal}} & {{52{instr[12]}}, instr[12], instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0}) 91 | | 92 | ({64{isCJalr}} & 64'b0) 93 | | 94 | ({64{isCBranch}} & {{55{instr[12]}}, instr[12], instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0}); 95 | 96 | assign isJal = ~instr_buf_empty & (isIJal | isCJal); 97 | assign isJalr = ~instr_buf_empty & (isIJalr | isCJalr); 98 | assign isBranch = ~instr_buf_empty & (isIBranch | isCBranch); 99 | assign isCall = ~instr_buf_empty & (isICall | isCCall); 100 | assign isReturn = ~instr_buf_empty & (isIReturn | isCReturn); 101 | 102 | assign isFencei = (instr[6:0] == 7'b0001111) & (instr[14:12] == 3'b001); 103 | 104 | assign imm = isRVC ? Cimm : Iimm; 105 | 106 | 107 | endmodule 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | -------------------------------------------------------------------------------- /RiftChip/riftCore/instr_fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: instr_fifo 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-06 11:11:59 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-13 14:35:25 8 | */ 9 | 10 | 11 | 12 | /* 13 | Copyright (c) 2020 - 2021 Ruige Lee 14 | 15 | Licensed under the Apache License, Version 2.0 (the "License"); 16 | you may not use this file except in compliance with the License. 17 | You may obtain a copy of the License at 18 | 19 | http://www.apache.org/licenses/LICENSE-2.0 20 | 21 | Unless required by applicable law or agreed to in writing, software 22 | distributed under the License is distributed on an "AS IS" BASIS, 23 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | See the License for the specific language governing permissions and 25 | limitations under the License. 26 | */ 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | `timescale 1 ns / 1 ps 37 | 38 | `include "define.vh" 39 | 40 | 41 | 42 | 43 | 44 | module instr_fifo # ( 45 | parameter DW = 64, 46 | parameter AW = 3 47 | ) ( 48 | 49 | input instrFifo_pop, 50 | input instrFifo_push, 51 | input [DW-1:0] decode_microInstr_push, 52 | 53 | output instrFifo_empty, 54 | output instrFifo_reject, 55 | output [DW-1:0] decode_microInstr_pop, 56 | 57 | input feflush, 58 | input CLK, 59 | input RSTn 60 | ); 61 | 62 | wire [AW+1-1:0] read_addr; 63 | wire [AW+1-1:0] write_addr; 64 | 65 | 66 | 67 | gen_fifo # (.DW(`DECODE_INFO_DW),.AW(AW)) 68 | fifo ( 69 | .fifo_pop(instrFifo_pop), 70 | .fifo_push(instrFifo_push), 71 | 72 | .data_push(decode_microInstr_push), 73 | .data_pop(decode_microInstr_pop), 74 | 75 | .fifo_empty(instrFifo_empty), 76 | .fifo_full(), 77 | 78 | .read_addr(read_addr), 79 | .write_addr(write_addr), 80 | 81 | 82 | .flush(feflush), 83 | .CLK(CLK), 84 | .RSTn(RSTn) 85 | ); 86 | 87 | 88 | wire reject_set; 89 | wire reject_rst; 90 | 91 | assign reject_set = (write_addr[AW-1:AW-2] == (read_addr[AW-1:AW-2] - 2'b01)) & (write_addr[AW-3:0] == (read_addr[AW-3:0])); 92 | assign reject_rst = feflush 93 | | ((write_addr[AW-1:AW-2] == (read_addr[AW-1:AW-2] + 2'b01)) & (write_addr[AW-3:0] == (read_addr[AW-3:0]))); 94 | 95 | gen_rsffr # (.DW(1)) reject_rsffr ( .set_in(reject_set), .rst_in(reject_rst), .qout(instrFifo_reject), .CLK(CLK), .RSTn(RSTn) ); 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | endmodule 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | -------------------------------------------------------------------------------- /doc/Core Bus System.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/Core Bus System.png -------------------------------------------------------------------------------- /doc/DFF.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/DFF.png -------------------------------------------------------------------------------- /doc/DFFen.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/DFFen.png -------------------------------------------------------------------------------- /doc/FIFO.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/FIFO.png -------------------------------------------------------------------------------- /doc/FPGA_implementation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/FPGA_implementation.png -------------------------------------------------------------------------------- /doc/RSFF.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/RSFF.png -------------------------------------------------------------------------------- /doc/bpFIFO.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/bpFIFO.png -------------------------------------------------------------------------------- /doc/branch_predict.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/branch_predict.png -------------------------------------------------------------------------------- /doc/front end.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/front end.png -------------------------------------------------------------------------------- /doc/inner_bus_handshake.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/inner_bus_handshake.png -------------------------------------------------------------------------------- /doc/instrFIFO.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/instrFIFO.png -------------------------------------------------------------------------------- /doc/out-of-order.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/out-of-order.png -------------------------------------------------------------------------------- /doc/paritymemory.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/paritymemory.png -------------------------------------------------------------------------------- /doc/pc_generate.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/pc_generate.png -------------------------------------------------------------------------------- /doc/rename.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/rename.png -------------------------------------------------------------------------------- /doc/riftCore micro-architecture.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/riftCore micro-architecture.png -------------------------------------------------------------------------------- /doc/ring_stack.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/ring_stack.png -------------------------------------------------------------------------------- /doc/writeback.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/doc/writeback.png -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | *.elf 3 | *.o 4 | *.img 5 | *.bin 6 | -------------------------------------------------------------------------------- /sw/axi_gpio/gpio.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include "gpio.h" 4 | 5 | 6 | 7 | 8 | #ifndef GPIO_BASE 9 | #error GPIO Base address not define!!! 10 | #endif 11 | 12 | 13 | // for 8 bit gpio 14 | 15 | volatile uint32_t *gpio_dat_reg = (uint32_t*)( GPIO_BASE + GPIO_DATA ); 16 | volatile uint32_t *gpio_tri_reg = (uint32_t*)( GPIO_BASE + GPIO_TRI ); 17 | 18 | 19 | uint8_t gpio_read() 20 | { 21 | *gpio_tri_reg = 0xff; 22 | return (uint8_t)(*gpio_dat_reg); 23 | } 24 | 25 | 26 | uint32_t gpio_write( uint32_t data ) 27 | { 28 | *gpio_tri_reg = 0x00; 29 | (*gpio_dat_reg) = data; 30 | return 0; 31 | } 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /sw/axi_gpio/gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef _GPIO_H_ 2 | #define _GPIO_H_ 3 | 4 | #include 5 | 6 | #define GPIO_BASE 0x20000000U 7 | 8 | 9 | 10 | #define GPIO_DATA 0x0000 11 | #define GPIO_TRI 0x0004 12 | #define GPIO2_DATA 0x0008 13 | #define GPIO2_TRI 0x000C 14 | #define GIER 0x011C 15 | #define IP_IER 0x0128 16 | #define IP_ISR 0x0120 17 | 18 | 19 | extern uint8_t gpio_read(); 20 | extern uint32_t gpio_write( uint32_t data ); 21 | 22 | void gpio_test(); 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /sw/axi_timer/timer.c: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: Ruige Lee 3 | * @Date: 2020-10-12 14:27:54 4 | * @Last Modified by: Ruige Lee 5 | * @Last Modified time: 2020-10-12 17:16:04 6 | */ 7 | 8 | 9 | #include 10 | #include "timer.h" 11 | 12 | 13 | #ifndef TIMER_BASE 14 | #error Timer Base address not define!!! 15 | #endif 16 | 17 | 18 | 19 | 20 | volatile uint32_t *timer_tcsr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR0 ); 21 | volatile uint32_t *timer_tlr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR0 ); 22 | volatile uint32_t *timer_tcr0_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR0 ); 23 | 24 | 25 | volatile uint32_t *timer_tcsr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCSR1 ); 26 | volatile uint32_t *timer_tlr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TLR1 ); 27 | volatile uint32_t *timer_tcr1_reg = (uint32_t*)( TIMER_BASE + TIMER_TCR1 ); 28 | 29 | 30 | int32_t timerIsINT(uint8_t timerNo) 31 | { 32 | if ( ( ( (*timer_tcsr0_reg) & 0x00000100 ) && ( timerNo == 0 ) ) 33 | || 34 | ( ( (*timer_tcsr1_reg) & 0x00000100 ) && ( timerNo == 1 ) ) 35 | ) 36 | { 37 | return 1; 38 | } 39 | else 40 | { 41 | return 0; 42 | } 43 | } 44 | 45 | int32_t timerClearINT(uint8_t timerNo) 46 | { 47 | if ( timerNo == 0 ) 48 | { 49 | *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000100; 50 | } 51 | else 52 | { 53 | *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000100; 54 | } 55 | 56 | return 0; 57 | } 58 | 59 | int32_t timerEnableRun(uint8_t timerNo) 60 | { 61 | if ( timerNo == 0 ) 62 | { 63 | *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000080; 64 | } 65 | else 66 | { 67 | *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000080; 68 | } 69 | 70 | return 0; 71 | } 72 | 73 | int32_t timerDisableRun(uint8_t timerNo) 74 | { 75 | if ( timerNo == 0 ) 76 | { 77 | *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000080); 78 | } 79 | else 80 | { 81 | *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000080); 82 | } 83 | 84 | return 0; 85 | } 86 | 87 | int32_t timerEnableINT(uint8_t timerNo) 88 | { 89 | if ( timerNo == 0 ) 90 | { 91 | *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000020); 92 | *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000040; 93 | } 94 | else 95 | { 96 | *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000020); 97 | *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000040; 98 | } 99 | 100 | 101 | return 0; 102 | } 103 | 104 | int32_t timerDisableINT(uint8_t timerNo) 105 | { 106 | if ( timerNo == 0 ) 107 | { 108 | *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000040); 109 | } 110 | else 111 | { 112 | *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000040); 113 | } 114 | return 0; 115 | } 116 | 117 | int32_t timerLoad(uint8_t timerNo, uint32_t count) 118 | { 119 | if ( timerNo == 0 ) 120 | { 121 | *timer_tlr0_reg = count; 122 | *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000020; 123 | } 124 | else 125 | { 126 | *timer_tlr1_reg = count; 127 | *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000020; 128 | } 129 | 130 | return 0; 131 | } 132 | 133 | 134 | int32_t timerAutoReloadEnable(uint8_t timerNo) 135 | { 136 | if ( timerNo == 0 ) 137 | { 138 | *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000010; 139 | } 140 | else 141 | { 142 | *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000010; 143 | } 144 | 145 | return 0; 146 | } 147 | 148 | int32_t timerAutoReloadDisable(uint8_t timerNo) 149 | { 150 | if ( timerNo == 0 ) 151 | { 152 | *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000010); 153 | } 154 | else 155 | { 156 | *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000010); 157 | } 158 | 159 | 160 | return 0; 161 | } 162 | 163 | int32_t timerUpCount(uint8_t timerNo) 164 | { 165 | if ( timerNo == 0 ) 166 | { 167 | *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000002); 168 | } 169 | else 170 | { 171 | *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000002); 172 | } 173 | 174 | 175 | return 0; 176 | } 177 | 178 | int32_t timerDownCount(uint8_t timerNo) 179 | { 180 | if ( timerNo == 0 ) 181 | { 182 | *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000002; 183 | } 184 | else 185 | { 186 | *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000002; 187 | } 188 | 189 | return 0; 190 | } 191 | 192 | int32_t timerGenerate(uint8_t timerNo) 193 | { 194 | if ( timerNo == 0 ) 195 | { 196 | *timer_tcsr0_reg = (*timer_tcsr0_reg) & (~0x00000001); 197 | } 198 | else 199 | { 200 | *timer_tcsr1_reg = (*timer_tcsr1_reg) & (~0x00000001); 201 | } 202 | 203 | return 0; 204 | } 205 | 206 | int32_t timerCapture( uint8_t timerNo ) 207 | { 208 | if ( timerNo == 0 ) 209 | { 210 | *timer_tcsr0_reg = (*timer_tcsr0_reg) | 0x00000001; 211 | } 212 | else 213 | { 214 | *timer_tcsr1_reg = (*timer_tcsr1_reg) | 0x00000001; 215 | } 216 | 217 | return 0; 218 | } 219 | 220 | uint32_t timerCounterRead( uint8_t timerNo ) 221 | { 222 | if ( timerNo == 0 ) 223 | { 224 | return *timer_tcr0_reg; 225 | } 226 | else 227 | { 228 | return *timer_tcr1_reg; 229 | } 230 | } 231 | 232 | 233 | -------------------------------------------------------------------------------- /sw/axi_timer/timer.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | #ifndef _TIMER_H_ 4 | #define _TIMER_H_ 5 | 6 | 7 | #include 8 | 9 | 10 | 11 | #define TIMER_BASE 0x20000800U 12 | 13 | 14 | #define TIMER_TCSR0 0x00U 15 | #define TIMER_TLR0 0x04 16 | #define TIMER_TCR0 0x08 17 | 18 | // #define TIMER_RSVD 19 | 20 | #define TIMER_TCSR1 0x10U 21 | #define TIMER_TLR1 0x14U 22 | #define TIMER_TCR1 0x18U 23 | 24 | 25 | extern int32_t timerIsINT( uint8_t timerNo ); 26 | extern int32_t timerClearINT( uint8_t timerNo ); 27 | extern int32_t timerEnableRun( uint8_t timerNo ); 28 | extern int32_t timerDisableRun( uint8_t timerNo ); 29 | extern int32_t timerEnableINT( uint8_t timerNo ); 30 | extern int32_t timerDisableINT( uint8_t timerNo ); 31 | extern int32_t timerLoad( uint8_t timerNo, uint32_t count ); 32 | extern int32_t timerAutoReloadEnable( uint8_t timerNo ); 33 | extern int32_t timerAutoReloadDisable( uint8_t timerNo ); 34 | extern int32_t timerUpCount( uint8_t timerNo ); 35 | extern int32_t timerDownCount( uint8_t timerNo ); 36 | extern int32_t timerGenerate( uint8_t timerNo ); 37 | extern int32_t timerCapture( uint8_t timerNo ); 38 | extern uint32_t timerCounterRead( uint8_t timerNo ); 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | #endif 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /sw/axi_uart/uart.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | #include 4 | #include "uart.h" 5 | 6 | 7 | #ifndef UART_BASE 8 | #error UART Base address not define!!! 9 | #endif 10 | 11 | 12 | volatile uint32_t *uart_rfifo = (uint32_t*)( UART_BASE + RX_FIFO ); 13 | volatile uint32_t *uart_tfifo = (uint32_t*)( UART_BASE + TX_FIFO ); 14 | volatile uint32_t *uart_status = (uint32_t*)( UART_BASE + STAT_REG ); 15 | volatile uint32_t *uart_ctrl = (uint32_t*)( UART_BASE + CTRL_REG ); 16 | 17 | 18 | int32_t uart_init() 19 | { 20 | //reset rx & tx fifo, disable interrupt 21 | (*uart_status) = 0x03; 22 | (*uart_status) = 0x00; 23 | 24 | return 0; 25 | } 26 | 27 | 28 | 29 | int32_t uart_sendByte( uint8_t data ) 30 | { 31 | //wait unitl tx fifo not full 32 | while( ((*uart_status) & 0x08) != 0); 33 | 34 | uint64_t sent = (uint64_t)data << 32; 35 | 36 | (*(volatile uint64_t*)(UART_BASE)) = sent; 37 | 38 | return 0; 39 | } 40 | 41 | 42 | uint8_t uart_recByte() 43 | { 44 | //wait unitl rx fifo has data 45 | while( ((*uart_status) & 0x01) == 0); 46 | 47 | return (uint8_t)(*uart_rfifo); 48 | } 49 | 50 | 51 | 52 | int32_t print_uart(const char *str) 53 | { 54 | const char *cur = &str[0]; 55 | while (*cur != '\0') 56 | { 57 | uart_sendByte((uint8_t)*cur); 58 | cur++; 59 | } 60 | 61 | return 0; 62 | } 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /sw/axi_uart/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef _UART_H_ 2 | #define _UART_H_ 3 | 4 | #include 5 | 6 | #define UART_BASE 0x20600000U 7 | 8 | 9 | 10 | #define RX_FIFO 0x0000 11 | #define TX_FIFO 0x0004 12 | #define STAT_REG 0x0008 13 | #define CTRL_REG 0x000c 14 | 15 | 16 | extern int32_t uart_init(); 17 | extern int32_t uart_sendByte( uint8_t data ); 18 | extern uint8_t uart_recByte(); 19 | extern int32_t print_uart(const char *str); 20 | 21 | 22 | 23 | 24 | #endif 25 | 26 | 27 | -------------------------------------------------------------------------------- /sw/compile.bat: -------------------------------------------------------------------------------- 1 | 2 | 3 | rmdir /s /q .\build 4 | md .\build 5 | 6 | @echo Remove Complete 7 | 8 | @rem compile .c 9 | riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs ^ 10 | -I ./ -I ./src -I ./axi_gpio -I ./axi_uart -I ./axi_timer ^ 11 | -c ./src/main.c ^ 12 | -o ./build/main.o 13 | 14 | riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs ^ 15 | -I ./ -I ./src -I ./axi_timer ^ 16 | -c ./axi_timer/timer.c ^ 17 | -o ./build/timer.o 18 | 19 | riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs ^ 20 | -I ./ -I ./src -I ./axi_gpio ^ 21 | -c ./axi_gpio/gpio.c ^ 22 | -o ./build/gpio.o 23 | 24 | riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs ^ 25 | -I ./ -I ./src -I ./axi_uart ^ 26 | -c ./axi_uart/uart.c ^ 27 | -o ./build/uart.o 28 | 29 | 30 | 31 | @rem riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs ^ 32 | @rem -I./ -I ./src^ 33 | @rem -c .c 34 | @rem -o .\build\ .o 35 | 36 | @echo C Code Compile Complete 37 | 38 | 39 | @rem compile .s 40 | riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imc -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs ^ 41 | -I ./ -I ./src ^ 42 | -c ./src/startup.S ^ 43 | -o ./build/startup.o 44 | 45 | @rem riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imc -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs 46 | @rem -I./ -I ./src ^ 47 | @rem -c .s ^ 48 | @rem -o .\build\ .o 49 | 50 | @rem riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imc -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs 51 | @rem -I./ -I ./src ^ 52 | @rem -c .s ^ 53 | @rem -o .\build\ .o 54 | 55 | @echo Asm Code Compile Complete 56 | 57 | 58 | @rem linker 59 | riscv64-unknown-elf-gcc -Os -ggdb -march=rv64imc -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles ^ 60 | -I ./ -I ./src ^ 61 | -T linker.lds ^ 62 | ./build/startup.o ^ 63 | ./build/uart.o ./build/timer.o ./build/gpio.o ^ ./build/main.o ^ 64 | -o riftChip.elf 65 | 66 | @rem objcopy 67 | riscv64-unknown-elf-objcopy -O binary .\riftChip.elf ./riftChip.bin 68 | 69 | 70 | 71 | @rem dump 72 | riscv64-unknown-elf-objdump ^ 73 | --disassemble-all ^ 74 | --disassemble-zeroes ^ 75 | --section=.text ^ 76 | --section=.text.startup ^ 77 | --section=.text.init ^ 78 | --section=.data ^ 79 | --section=.bss ^ 80 | --section=.rodata ^ 81 | riftChip.elf >riftChip.dump 82 | 83 | 84 | riscv64-unknown-elf-objcopy -O verilog .\riftChip.elf ./riftChip.verilog 85 | 86 | 87 | @rem tcl 88 | python createDownload.py 89 | 90 | @pause 91 | 92 | 93 | 94 | 95 | -------------------------------------------------------------------------------- /sw/createDownload.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # @Author: Ruige Lee 3 | # @Date: 2021-01-20 14:27:44 4 | # @Last Modified by: Ruige Lee 5 | # @Last Modified time: 2021-01-22 14:14:11 6 | 7 | 8 | import sys 9 | import os 10 | 11 | downloadScript = "" 12 | 13 | program = "" 14 | 15 | size = os.path.getsize("./riftChip.bin") 16 | with open("./riftChip.bin","rb") as f: 17 | for i in range(size//8 + 1): 18 | data1 = f.read(1) 19 | data2 = f.read(1) 20 | data3 = f.read(1) 21 | data4 = f.read(1) 22 | data5 = f.read(1) 23 | data6 = f.read(1) 24 | data7 = f.read(1) 25 | data8 = f.read(1) 26 | # print (data, data.hex()) 27 | 28 | data = "0x" + data8.hex() + data7.hex() + data6.hex() + data5.hex() +data4.hex() + data3.hex() + data2.hex() + data1.hex() 29 | 30 | # program = program + " 0x" + str(data) 31 | # print(program) 32 | 33 | downloadScript = downloadScript + "create_hw_axi_txn download_sram" + str(i) + " [get_hw_axis hw_axi_1] -address " + str(hex(2147483648 + 8*i)) +" -data " + data + " -type write -force\n" 34 | downloadScript = downloadScript + "run_hw_axi download_sram" + str(i) + "\n" 35 | # print(program) 36 | 37 | 38 | 39 | # downloadScript = "create_hw_axi_txn download_sram [get_hw_axis hw_axi_1] -address 0x80000000 -data {" + program + "} -len " + str(size//8 + 1) + " -size 64 -type write -force\n" 40 | # create_hw_axi_txn download_sram 41 | 42 | 43 | # downloadScript = downloadScript + "run_hw_axi download_sram" 44 | 45 | with open("./download.tcl","w") as f: 46 | f.write(downloadScript) 47 | 48 | 49 | 50 | 51 | # run_hw_axi [create_hw_axi_txn readout [get_hw_axis hw_axi_1] -address 0x80000000 -type read -force] 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | -------------------------------------------------------------------------------- /sw/linker.lds: -------------------------------------------------------------------------------- 1 | ENTRY(_prog_start) 2 | 3 | SECTIONS 4 | { 5 | RAM_BASE = 0x80000000; 6 | 7 | . = RAM_BASE; 8 | 9 | .text.init : { *(.text.init) } 10 | 11 | .text : ALIGN(0x100) { 12 | _TEXT_START_ = .; 13 | *(.text) 14 | _TEXT_END_ = .; 15 | } 16 | 17 | .data : ALIGN(0x100) { 18 | _DATA_START_ = .; 19 | *(.data) 20 | _DATA_END_ = .; 21 | } 22 | 23 | PROVIDE(_data = ADDR(.data)); 24 | PROVIDE(_data_lma = LOADADDR(.data)); 25 | PROVIDE(_edata = .); 26 | 27 | .bss : ALIGN(0x100) { 28 | _BSS_START_ = .; 29 | *(.bss) 30 | _BSS_END_ = .; 31 | } 32 | 33 | .rodata : ALIGN(0x100) { 34 | _RODATA_START_ = .; 35 | *(.rodata) 36 | *(.rodata*) 37 | _RODATA_END_ = .; 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /sw/src/main.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include "uart.h" 4 | #include "gpio.h" 5 | #include "timer.h" 6 | 7 | int main() 8 | { 9 | uart_init(); 10 | 11 | 12 | print_uart("Hello World, RiftCore is now Waking Up!\r\n"); 13 | 14 | gpio_write( 0xfffffffa ); 15 | 16 | uint8_t i = 0; 17 | uint32_t data = 0; 18 | volatile uint32_t* reg = (uint32_t*)(0x80002000); 19 | 20 | for ( i = 0; i < 255; i++ ) 21 | { 22 | *(reg+i) = data; 23 | data ++; 24 | } 25 | 26 | 27 | 28 | while(1) 29 | { 30 | ; 31 | } 32 | return 0; 33 | 34 | } 35 | 36 | void handle_trap(void) 37 | { 38 | 39 | } -------------------------------------------------------------------------------- /sw/src/startup.S: -------------------------------------------------------------------------------- 1 | 2 | .section .text.init 3 | .globl _prog_start 4 | _prog_start: 5 | 6 | # csrwi satp,0 7 | # li t0,-1 8 | # csrw pmpaddr0,t0 9 | # li t0,31 10 | # csrw pmpcfg0,t0 11 | # csrwi medeleg,0 12 | # csrwi mideleg,0 13 | # li t0, 1 14 | # slli t0, t0, 31 15 | # csrw mtvec,t0 16 | # csrwi mie, 0 17 | # csrwi mstatus,0 18 | 19 | li sp, 0x80001000 20 | 21 | 22 | # li t1, 0x80000200 23 | # li t2, -1 24 | # sd t2, 0(t1) 25 | 26 | # li t1,0x80000000 27 | # jr t1 28 | 29 | call main 30 | 31 | 32 | 33 | # li s1, DDR_BASE 34 | # jr s1 35 | 36 | ecall 37 | 38 | -------------------------------------------------------------------------------- /tb/CI.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # @Author: Ruige Lee 3 | # @Date: 2020-11-18 15:37:18 4 | # @Last Modified by: Ruige Lee 5 | # @Last Modified time: 2021-03-18 11:09:55 6 | 7 | 8 | import sys 9 | import os 10 | 11 | 12 | CIReturn = 0 13 | 14 | testList = [ 15 | "rv64ui-p-simple", 16 | "rv64mi-p-ma_addr", 17 | "rv64mi-p-ma_fetch", 18 | "rv64ui-p-jal", 19 | "rv64ui-p-jalr", 20 | "rv64ui-p-beq", 21 | "rv64ui-p-bge", 22 | "rv64ui-p-bgeu", 23 | "rv64ui-p-blt", 24 | "rv64ui-p-bltu", 25 | "rv64ui-p-bne", 26 | "rv64ui-p-add", 27 | "rv64ui-p-addiw", 28 | "rv64ui-p-addw", 29 | "rv64ui-p-and", 30 | "rv64ui-p-andi", 31 | "rv64ui-p-auipc", 32 | "rv64ui-p-lb", 33 | "rv64ui-p-lbu", 34 | "rv64ui-p-ld", 35 | "rv64ui-p-lh", 36 | "rv64ui-p-lhu", 37 | "rv64ui-p-lui", 38 | "rv64ui-p-lw", 39 | "rv64ui-p-lwu", 40 | "rv64ui-p-or", 41 | "rv64ui-p-ori", 42 | "rv64ui-p-sb", 43 | "rv64ui-p-sd", 44 | "rv64ui-p-sh", 45 | "rv64ui-p-sll", 46 | "rv64ui-p-slli", 47 | "rv64ui-p-slliw", 48 | "rv64ui-p-sllw", 49 | "rv64ui-p-slt", 50 | "rv64ui-p-slti", 51 | "rv64ui-p-sltiu", 52 | "rv64ui-p-sltu", 53 | "rv64ui-p-sra", 54 | "rv64ui-p-srai", 55 | "rv64ui-p-sraiw", 56 | "rv64ui-p-sraw", 57 | "rv64ui-p-srl", 58 | "rv64ui-p-srli", 59 | "rv64ui-p-srliw", 60 | "rv64ui-p-srlw", 61 | "rv64ui-p-sub", 62 | "rv64ui-p-subw", 63 | "rv64ui-p-sw", 64 | "rv64ui-p-xor", 65 | "rv64ui-p-xori", 66 | "rv64mi-p-access", 67 | "rv64mi-p-illegal", 68 | "rv64mi-p-breakpoint", 69 | "rv64mi-p-csr", 70 | "rv64mi-p-mcsr", 71 | "rv64ui-p-fence_i", 72 | "rv64uc-p-rvc", 73 | "rv64um-p-div", 74 | "rv64um-p-divu", 75 | "rv64um-p-divuw", 76 | "rv64um-p-divw", 77 | "rv64um-p-mul", 78 | "rv64um-p-mulh", 79 | "rv64um-p-mulhsu", 80 | "rv64um-p-mulhu", 81 | "rv64um-p-mulw", 82 | "rv64um-p-rem", 83 | "rv64um-p-remu", 84 | "rv64um-p-remuw", 85 | "rv64um-p-remw" 86 | 87 | ] 88 | 89 | 90 | 91 | 92 | 93 | res = os.system("iverilog -Wall -o ./build/wave.iverilog -y ../RiftChip/ -y ../RiftChip/riftCore/ -y ../RiftChip/riftCore/backend -y ../RiftChip/riftCore/cache -y ../RiftChip/riftCore/backend/issue -y ../RiftChip/riftCore/backend/execute -y ../RiftChip/riftCore/frontend -y ../RiftChip/element -y ../RiftChip/SoC -y ../RiftChip/SoC/xilinx_IP/axi_full_Xbar -y ../RiftChip/debug -y ../tb -I ../tb -I ../RiftChip/ -I ../RiftChip/SoC/xilinx_IP/axi_full_Xbar ../tb/riftChip_CI.v ") 94 | 95 | if ( res == 0 ): 96 | print ("compile pass!") 97 | else: 98 | print ("compile Fail!") 99 | CIReturn = -1 100 | sys.exit(-1) 101 | 102 | for file in testList: 103 | cmd = "vvp -N ./build/wave.iverilog +./ci/" 104 | cmd = cmd + file 105 | cmd = cmd + ".verilog >> null" 106 | res = os.system(cmd) 107 | 108 | if (res == 0): 109 | print(file, "PASS!") 110 | else: 111 | 112 | CIReturn = -1 113 | print(file, "FAIL!!!!!!!!!!") 114 | 115 | jsonFile = "{\n\"schemaVersion\": 1,\n\"label\": \"" 116 | jsonFile = jsonFile + file 117 | jsonFile = jsonFile + "\",\n\"message\": \"" 118 | 119 | if ( res == 0 ): 120 | jsonFile = jsonFile + "PASS\",\n\"color\": \"blue\"\n}" 121 | 122 | else: 123 | jsonFile = jsonFile + "FAIL\",\n\"color\": \"red\"\n}" 124 | # print (jsonFile) 125 | 126 | with open("./ci/"+file+".json","w") as f: 127 | f.write(jsonFile) 128 | 129 | # if (CIReturn): 130 | # sys.exit(-1) 131 | 132 | 133 | 134 | 135 | 136 | 137 | -------------------------------------------------------------------------------- /tb/DS.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # @Author: Ruige Lee 3 | # @Date: 2021-02-02 17:06:19 4 | # @Last Modified by: Ruige Lee 5 | # @Last Modified time: 2021-02-07 19:14:14 6 | 7 | 8 | import sys 9 | import os 10 | import json 11 | import time 12 | 13 | import matplotlib.pyplot as plt 14 | 15 | 16 | def get_log(str): 17 | temp = os.popen(str) 18 | log = temp.read() 19 | temp.close() 20 | return log 21 | 22 | 23 | 24 | 25 | 26 | res = os.system("iverilog -Wall -o ./build/wave.iverilog -y ../RiftChip/ -y ../RiftChip/riftCore/ -y ../RiftChip/riftCore/backend -y ../RiftChip/riftCore/cache -y ../RiftChip/riftCore/backend/issue -y ../RiftChip/riftCore/backend/execute -y ../RiftChip/riftCore/frontend -y ../RiftChip/element -y ../RiftChip/SoC -y ../RiftChip/SoC/xilinx_IP/axi_full_Xbar -y ../RiftChip/debug -y ../tb -I ../tb -I ../RiftChip/ -I ../RiftChip/SoC/xilinx_IP/axi_full_Xbar ../tb/riftChip_DS.v ") 27 | 28 | 29 | if ( res == 0 ): 30 | print ("compile pass!") 31 | else: 32 | print ("compile Fail!") 33 | DSReturn = -1 34 | sys.exit(-1) 35 | 36 | 37 | 38 | res = os.system("vvp -N ./build/wave.iverilog -lxt2") 39 | 40 | 41 | if (res == 0): 42 | print("dhrystone PASS!") 43 | 44 | 45 | with open("./ci/dhrystone.json","r") as f1: 46 | benchmark = f1.read() 47 | bm = (json.loads(benchmark))['message'] 48 | 49 | # print(bm) 50 | 51 | # print(str) 52 | 53 | 54 | new = [] 55 | with open("./ci/performance.js","r") as f2: 56 | data = f2.read()[8:] 57 | # print ("data=", data) 58 | data = json.dumps(eval(data)) 59 | history = json.loads(data) 60 | # print ("benchmark =", history["benchmark"]) 61 | benchmark = history["benchmark"] 62 | 63 | lastUpdata = time.time() 64 | lastUpdata = int(lastUpdata) 65 | newBen_hash = get_log("git log -1 --pretty=format:\"%h\"") 66 | newBen_an = get_log("git log -1 --pretty=format:\"%an\"") 67 | newBen_ae = get_log("git log -1 --pretty=format:\"%ae\"") 68 | newBen_ad = get_log("git log -1 --pretty=format:\"%ad\"") 69 | newBen_cc = get_log("git log -1 --pretty=format:\"%s\"") 70 | newBen_ds = bm 71 | 72 | jsStr = "{\"hash\": \"" +newBen_hash+ "\", \"author name\": \"" +newBen_an+ "\", \"author email\": \"" +newBen_ae+ "\", \"author date\": \"" +newBen_ad+ "\", \"commit comment\": \"" +newBen_cc+ "\", \"dhrystone\": " +str(bm)+ "}" 73 | js = json.loads(jsStr) 74 | # print ("js", js) 75 | benchmark.append(js) 76 | # print (str(benchmark)) 77 | 78 | data = "data = \n{\n" 79 | data = data + " \'lastUpdata\': " + str(lastUpdata) + ",\n" 80 | data = data + " \'benchmark\': " + str(benchmark) 81 | data = data + "\n}" 82 | 83 | # print (data) 84 | 85 | 86 | with open("./ci/performance.js","w") as f3: 87 | f3.write(data) 88 | 89 | 90 | else: 91 | 92 | CIReturn = -1 93 | print(file, "dhrystone FAIL!!!!!!!!!!") 94 | sys.exit(-1) 95 | 96 | 97 | # performance = [] 98 | # for item in new: 99 | # performance.append(item["benchmark"]) 100 | 101 | # print("performance=", performance) 102 | 103 | # print(len(performance)) 104 | # x1 = range(0, len(performance)) 105 | 106 | 107 | # plt.xticks([]) 108 | # plt.scatter(x1, performance, marker='.', s = 1000//len(performance)) 109 | 110 | # # plt.show() 111 | # plt.savefig("./ci/performance.png") 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | # "git log -1 --pretty=format:\"%h\"" #短哈希 121 | # "git log -1 --pretty=format:\"%an\"" #作者 122 | # "git log -1 --pretty=format:\"%ae\"" #作者邮箱 123 | # "git log -1 --pretty=format:\"%ad\"" #作者日期 124 | # "git log -1 --pretty=format:\"%s\"" #提交说明 125 | 126 | 127 | # data = 128 | # { 129 | # "lastUpdata": 10000, 130 | # "benchmark": [{"hash": "f010753", "author name": "Ruige Lee", "author email": "295054118@qq.com", "author date": " Fri Jan 1 12:13:35 2021 ", "commit comment": "0.4.2", "dhrystone": 0.568016}] 131 | # } 132 | 133 | 134 | 135 | -------------------------------------------------------------------------------- /tb/build/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/tb/build/.keep -------------------------------------------------------------------------------- /tb/ci/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/whutddk/RiftCore/a9b93c5178272982d7f42eea4aefc2f0c2398048/tb/ci/.keep -------------------------------------------------------------------------------- /tb/dhrystone.bat: -------------------------------------------------------------------------------- 1 | @REM @Author: Ruige Lee 2 | @REM @Date: 2020-11-02 11:29:57 3 | @REM @Last Modified by: Ruige Lee 4 | @REM Modified time: 2021-03-11 11:34:52 5 | 6 | 7 | 8 | 9 | iverilog.exe -W all ^ 10 | -o ./build/wave.iverilog ^ 11 | -y ../RiftChip/ ^ 12 | -y ../RiftChip/riftCore/ ^ 13 | -y ../RiftChip/riftCore/backend ^ 14 | -y ../RiftChip/riftCore/cache ^ 15 | -y ../RiftChip/riftCore/backend/issue ^ 16 | -y ../RiftChip/riftCore/backend/execute ^ 17 | -y ../RiftChip/riftCore/frontend ^ 18 | -y ../RiftChip/element ^ 19 | -y ../RiftChip/Soc ^ 20 | -y ../RiftChip/SoC/xilinx_IP/axi_full_Xbar ^ 21 | -y ../RiftChip/debug ^ 22 | -y ../tb ^ 23 | -I ../tb ^ 24 | -I ../RiftChip/ ^ 25 | -I ../RiftChip/SoC/xilinx_IP/axi_full_Xbar ^ 26 | ../tb/riftChip_DS.v 27 | 28 | @pause 29 | 30 | vvp.exe -N ./build/wave.iverilog -lxt2 31 | 32 | rem @pause 33 | 34 | 35 | -------------------------------------------------------------------------------- /tb/dhrystone/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012-2015, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | 26 | 27 | -------------------------------------------------------------------------------- /tb/dhrystone/Makefile: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # UCB VLSI FLOW: Makefile for riscv-bmarks 3 | #----------------------------------------------------------------------- 4 | # Yunsup Lee (yunsup@cs.berkeley.edu) 5 | # 6 | 7 | XLEN ?= 64 8 | 9 | default: all 10 | 11 | src_dir = . 12 | 13 | instname = riscv-bmarks 14 | instbasedir = $(UCB_VLSI_HOME)/install 15 | 16 | #-------------------------------------------------------------------- 17 | # Sources 18 | #-------------------------------------------------------------------- 19 | 20 | bmarks = \ 21 | dhrystone \ 22 | 23 | 24 | #-------------------------------------------------------------------- 25 | # Build rules 26 | #-------------------------------------------------------------------- 27 | 28 | RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- 29 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 30 | RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf 31 | RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs) 32 | RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld 33 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data 34 | RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy -O verilog 35 | RISCV_SIM ?= spike --isa=rv$(XLEN)gc 36 | 37 | incs += -I$(src_dir)/../env -I$(src_dir)/common $(addprefix -I$(src_dir)/, $(bmarks)) 38 | objs := 39 | 40 | define compile_template 41 | $(1).riscv: $(wildcard $(src_dir)/$(1)/*) $(wildcard $(src_dir)/common/*) 42 | $$(RISCV_GCC) $$(incs) $$(RISCV_GCC_OPTS) -o $$@ $(wildcard $(src_dir)/$(1)/*.c) $(wildcard $(src_dir)/common/*.c) $(wildcard $(src_dir)/common/*.S) $$(RISCV_LINK_OPTS) 43 | endef 44 | 45 | $(foreach bmark,$(bmarks),$(eval $(call compile_template,$(bmark)))) 46 | 47 | #------------------------------------------------------------ 48 | # Build and run benchmarks on riscv simulator 49 | 50 | bmarks_riscv_bin = $(addsuffix .riscv, $(bmarks)) 51 | bmarks_riscv_dump = $(addsuffix .riscv.dump, $(bmarks)) 52 | bmarks_riscv_out = $(addsuffix .riscv.out, $(bmarks)) 53 | bmarks_riscv_verilog = $(addsuffix .verilog, $(tests)) 54 | 55 | $(bmarks_riscv_dump): %.riscv.dump: %.riscv 56 | $(RISCV_OBJDUMP) $< > $@ 57 | $(RISCV_OBJCOPY) $< $<.verilog 58 | sed -i 's/@800/@000/g' $<.verilog 59 | # sed -i 's/@00002FB8/@00002000/g' $<.verilog 60 | 61 | $(bmarks_riscv_out): %.riscv.out: %.riscv 62 | $(RISCV_SIM) $< > $@ 63 | 64 | riscv: $(bmarks_riscv_dump) 65 | run: $(bmarks_riscv_out) 66 | 67 | junk += $(bmarks_riscv_verilog) $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(bmarks_riscv_hex) $(bmarks_riscv_out) 68 | 69 | #------------------------------------------------------------ 70 | # Default 71 | 72 | all: riscv 73 | 74 | #------------------------------------------------------------ 75 | # Install 76 | 77 | date_suffix = $(shell date +%Y-%m-%d_%H-%M) 78 | install_dir = $(instbasedir)/$(instname)-$(date_suffix) 79 | latest_install = $(shell ls -1 -d $(instbasedir)/$(instname)* | tail -n 1) 80 | 81 | install: 82 | mkdir $(install_dir) 83 | cp -r $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(install_dir) 84 | 85 | install-link: 86 | rm -rf $(instbasedir)/$(instname) 87 | ln -s $(latest_install) $(instbasedir)/$(instname) 88 | 89 | #------------------------------------------------------------ 90 | # Clean up 91 | 92 | clean: 93 | rm -rf $(objs) $(junk) 94 | -------------------------------------------------------------------------------- /tb/dhrystone/crt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "encoding.h" 4 | 5 | #if __riscv_xlen == 64 6 | # define LREG ld 7 | # define SREG sd 8 | # define REGBYTES 8 9 | #else 10 | # define LREG lw 11 | # define SREG sw 12 | # define REGBYTES 4 13 | #endif 14 | 15 | .section ".text.init" 16 | .globl _start 17 | _start: 18 | li x1, 0 19 | li x2, 0 20 | li x3, 0 21 | li x4, 0 22 | li x5, 0 23 | li x6, 0 24 | li x7, 0 25 | li x8, 0 26 | li x9, 0 27 | li x10,0 28 | li x11,0 29 | li x12,0 30 | li x13,0 31 | li x14,0 32 | li x15,0 33 | li x16,0 34 | li x17,0 35 | li x18,0 36 | li x19,0 37 | li x20,0 38 | li x21,0 39 | li x22,0 40 | li x23,0 41 | li x24,0 42 | li x25,0 43 | li x26,0 44 | li x27,0 45 | li x28,0 46 | li x29,0 47 | li x30,0 48 | li x31,0 49 | 50 | # enable FPU and accelerator if present 51 | li t0, MSTATUS_FS | MSTATUS_XS 52 | csrs mstatus, t0 53 | 54 | # make sure XLEN agrees with compilation choice 55 | li t0, 1 56 | slli t0, t0, 31 57 | #if __riscv_xlen == 64 58 | bgez t0, 1f 59 | #else 60 | bltz t0, 1f 61 | #endif 62 | 2: 63 | li a0, 1 64 | sw a0, tohost, t0 65 | j 2b 66 | 1: 67 | 68 | #ifdef __riscv_flen 69 | # initialize FPU if we have one 70 | la t0, 1f 71 | csrw mtvec, t0 72 | 73 | 74 | 1: 75 | #endif 76 | 77 | # initialize trap vector 78 | la t0, trap_entry 79 | csrw mtvec, t0 80 | 81 | # initialize global pointer 82 | .option push 83 | .option norelax 84 | la gp, __global_pointer$ 85 | .option pop 86 | 87 | la tp, _end + 63 88 | and tp, tp, -64 89 | 90 | # get core id 91 | csrr a0, mhartid 92 | # for now, assume only 1 core 93 | li a1, 1 94 | 1:bgeu a0, a1, 1b 95 | 96 | # give each core 128KB of stack + TLS 97 | #define STKSHIFT 17 98 | add sp, a0, 1 99 | sll sp, sp, STKSHIFT 100 | add sp, sp, tp 101 | sll a2, a0, STKSHIFT 102 | add tp, tp, a2 103 | 104 | j _init 105 | 106 | .align 2 107 | trap_entry: 108 | addi sp, sp, -272 109 | 110 | SREG x1, 1*REGBYTES(sp) 111 | SREG x2, 2*REGBYTES(sp) 112 | SREG x3, 3*REGBYTES(sp) 113 | SREG x4, 4*REGBYTES(sp) 114 | SREG x5, 5*REGBYTES(sp) 115 | SREG x6, 6*REGBYTES(sp) 116 | SREG x7, 7*REGBYTES(sp) 117 | SREG x8, 8*REGBYTES(sp) 118 | SREG x9, 9*REGBYTES(sp) 119 | SREG x10, 10*REGBYTES(sp) 120 | SREG x11, 11*REGBYTES(sp) 121 | SREG x12, 12*REGBYTES(sp) 122 | SREG x13, 13*REGBYTES(sp) 123 | SREG x14, 14*REGBYTES(sp) 124 | SREG x15, 15*REGBYTES(sp) 125 | SREG x16, 16*REGBYTES(sp) 126 | SREG x17, 17*REGBYTES(sp) 127 | SREG x18, 18*REGBYTES(sp) 128 | SREG x19, 19*REGBYTES(sp) 129 | SREG x20, 20*REGBYTES(sp) 130 | SREG x21, 21*REGBYTES(sp) 131 | SREG x22, 22*REGBYTES(sp) 132 | SREG x23, 23*REGBYTES(sp) 133 | SREG x24, 24*REGBYTES(sp) 134 | SREG x25, 25*REGBYTES(sp) 135 | SREG x26, 26*REGBYTES(sp) 136 | SREG x27, 27*REGBYTES(sp) 137 | SREG x28, 28*REGBYTES(sp) 138 | SREG x29, 29*REGBYTES(sp) 139 | SREG x30, 30*REGBYTES(sp) 140 | SREG x31, 31*REGBYTES(sp) 141 | 142 | csrr a0, mcause 143 | csrr a1, mepc 144 | mv a2, sp 145 | jal handle_trap 146 | csrw mepc, a0 147 | 148 | # Remain in M-mode after eret 149 | li t0, MSTATUS_MPP 150 | csrs mstatus, t0 151 | 152 | LREG x1, 1*REGBYTES(sp) 153 | LREG x2, 2*REGBYTES(sp) 154 | LREG x3, 3*REGBYTES(sp) 155 | LREG x4, 4*REGBYTES(sp) 156 | LREG x5, 5*REGBYTES(sp) 157 | LREG x6, 6*REGBYTES(sp) 158 | LREG x7, 7*REGBYTES(sp) 159 | LREG x8, 8*REGBYTES(sp) 160 | LREG x9, 9*REGBYTES(sp) 161 | LREG x10, 10*REGBYTES(sp) 162 | LREG x11, 11*REGBYTES(sp) 163 | LREG x12, 12*REGBYTES(sp) 164 | LREG x13, 13*REGBYTES(sp) 165 | LREG x14, 14*REGBYTES(sp) 166 | LREG x15, 15*REGBYTES(sp) 167 | LREG x16, 16*REGBYTES(sp) 168 | LREG x17, 17*REGBYTES(sp) 169 | LREG x18, 18*REGBYTES(sp) 170 | LREG x19, 19*REGBYTES(sp) 171 | LREG x20, 20*REGBYTES(sp) 172 | LREG x21, 21*REGBYTES(sp) 173 | LREG x22, 22*REGBYTES(sp) 174 | LREG x23, 23*REGBYTES(sp) 175 | LREG x24, 24*REGBYTES(sp) 176 | LREG x25, 25*REGBYTES(sp) 177 | LREG x26, 26*REGBYTES(sp) 178 | LREG x27, 27*REGBYTES(sp) 179 | LREG x28, 28*REGBYTES(sp) 180 | LREG x29, 29*REGBYTES(sp) 181 | LREG x30, 30*REGBYTES(sp) 182 | LREG x31, 31*REGBYTES(sp) 183 | 184 | addi sp, sp, 272 185 | mret 186 | 187 | .section ".tohost","aw",@progbits 188 | .align 6 189 | .globl tohost 190 | tohost: .dword 0 191 | .align 6 192 | .globl fromhost 193 | fromhost: .dword 0 194 | 195 | -------------------------------------------------------------------------------- /tb/isa/Makefile: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefile for riscv-tests/isa 3 | #----------------------------------------------------------------------- 4 | 5 | XLEN ?= 64 6 | 7 | src_dir := . 8 | 9 | ifeq ($(XLEN),64) 10 | include $(src_dir)/rv64ui/Makefrag 11 | include $(src_dir)/rv64uc/Makefrag 12 | include $(src_dir)/rv64um/Makefrag 13 | include $(src_dir)/rv64ua/Makefrag 14 | include $(src_dir)/rv64uf/Makefrag 15 | include $(src_dir)/rv64ud/Makefrag 16 | include $(src_dir)/rv64si/Makefrag 17 | include $(src_dir)/rv64mi/Makefrag 18 | endif 19 | include $(src_dir)/rv32ui/Makefrag 20 | include $(src_dir)/rv32uc/Makefrag 21 | include $(src_dir)/rv32um/Makefrag 22 | include $(src_dir)/rv32ua/Makefrag 23 | include $(src_dir)/rv32uf/Makefrag 24 | include $(src_dir)/rv32ud/Makefrag 25 | include $(src_dir)/rv32si/Makefrag 26 | include $(src_dir)/rv32mi/Makefrag 27 | 28 | default: all 29 | 30 | #-------------------------------------------------------------------- 31 | # Build rules 32 | #-------------------------------------------------------------------- 33 | 34 | RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- 35 | RISCV_GCC ?= $(RISCV_PREFIX)gcc 36 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 37 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data 38 | RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy -O verilog 39 | RISCV_SIM ?= spike 40 | 41 | vpath %.S $(src_dir) 42 | 43 | #------------------------------------------------------------ 44 | # Build assembly tests 45 | 46 | %.dump: % 47 | $(RISCV_OBJDUMP) $< > $@ 48 | $(RISCV_OBJCOPY) $< $<.verilog 49 | sed -i 's/@800/@000/g' $<.verilog 50 | sed -i 's/@00002FB8/@00002000/g' $<.verilog 51 | 52 | %.out: % 53 | $(RISCV_SIM) --isa=rv64gc $< 2> $@ 54 | 55 | %.out32: % 56 | $(RISCV_SIM) --isa=rv32gc $< 2> $@ 57 | 58 | define compile_template 59 | 60 | $$($(1)_p_tests): $(1)-p-%: $(1)/%.S 61 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@ 62 | $(1)_tests += $$($(1)_p_tests) 63 | 64 | $$($(1)_v_tests): $(1)-v-%: $(1)/%.S 65 | $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@ 66 | $(1)_tests += $$($(1)_v_tests) 67 | 68 | $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests)) 69 | 70 | $(1): $$($(1)_tests_dump) 71 | 72 | .PHONY: $(1) 73 | 74 | tests += $$($(1)_tests) 75 | 76 | endef 77 | 78 | $(eval $(call compile_template,rv32ui,-march=rv32gc -mabi=ilp32)) 79 | $(eval $(call compile_template,rv32uc,-march=rv32gc -mabi=ilp32)) 80 | $(eval $(call compile_template,rv32um,-march=rv32gc -mabi=ilp32)) 81 | $(eval $(call compile_template,rv32ua,-march=rv32gc -mabi=ilp32)) 82 | $(eval $(call compile_template,rv32uf,-march=rv32gc -mabi=ilp32)) 83 | $(eval $(call compile_template,rv32ud,-march=rv32gc -mabi=ilp32)) 84 | $(eval $(call compile_template,rv32si,-march=rv32gc -mabi=ilp32)) 85 | $(eval $(call compile_template,rv32mi,-march=rv32gc -mabi=ilp32)) 86 | ifeq ($(XLEN),64) 87 | $(eval $(call compile_template,rv64ui,-march=rv64gc -mabi=lp64)) 88 | $(eval $(call compile_template,rv64uc,-march=rv64gc -mabi=lp64)) 89 | $(eval $(call compile_template,rv64um,-march=rv64gc -mabi=lp64)) 90 | $(eval $(call compile_template,rv64ua,-march=rv64gc -mabi=lp64)) 91 | $(eval $(call compile_template,rv64uf,-march=rv64gc -mabi=lp64)) 92 | $(eval $(call compile_template,rv64ud,-march=rv64gc -mabi=lp64)) 93 | $(eval $(call compile_template,rv64si,-march=rv64gc -mabi=lp64)) 94 | $(eval $(call compile_template,rv64mi,-march=rv64gc -mabi=lp64)) 95 | endif 96 | 97 | tests_verilog = $(addsuffix .verilog, $(tests)) 98 | tests_dump = $(addsuffix .dump, $(tests)) 99 | tests_hex = $(addsuffix .hex, $(tests)) 100 | tests_out = $(addsuffix .out, $(spike_tests)) 101 | tests32_out = $(addsuffix .out32, $(spike32_tests)) 102 | 103 | run: $(tests_out) $(tests32_out) 104 | 105 | junk += $(tests_verilog) $(tests) $(tests_dump) $(tests_hex) $(tests_out) $(tests32_out) 106 | 107 | #------------------------------------------------------------ 108 | # Default 109 | 110 | all: $(tests_dump) 111 | 112 | #------------------------------------------------------------ 113 | # Clean up 114 | 115 | clean: 116 | rm -rf $(junk) 117 | -------------------------------------------------------------------------------- /tb/iverilog.vh: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | Copyright (c) 2020 - 2020 Ruige Lee 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | 9 | http://www.apache.org/licenses/LICENSE-2.0 10 | 11 | Unless required by applicable law or agreed to in writing, software 12 | distributed under the License is distributed on an "AS IS" BASIS, 13 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | See the License for the specific language governing permissions and 15 | limitations under the License. 16 | */ 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /tb/iverilogCompile.bat: -------------------------------------------------------------------------------- 1 | @REM @Author: Ruige Lee 2 | @REM @Date: 2020-11-02 11:29:57 3 | @REM @Last Modified by: Ruige Lee 4 | @REM Modified time: 2021-03-10 14:18:03 5 | 6 | 7 | 8 | 9 | iverilog.exe -Wall ^ 10 | -o ./build/wave.iverilog ^ 11 | -y ../RiftChip/ ^ 12 | -y ../RiftChip/riftCore/ ^ 13 | -y ../RiftChip/riftCore/backend ^ 14 | -y ../RiftChip/riftCore/cache ^ 15 | -y ../RiftChip/riftCore/backend/issue ^ 16 | -y ../RiftChip/riftCore/backend/execute ^ 17 | -y ../RiftChip/riftCore/frontend ^ 18 | -y ../RiftChip/element ^ 19 | -y ../RiftChip/Soc ^ 20 | -y ../RiftChip/SoC/xilinx_IP/axi_full_Xbar ^ 21 | -y ../RiftChip/debug ^ 22 | -y ../tb ^ 23 | -I ../tb ^ 24 | -I ../RiftChip/ ^ 25 | -I ../RiftChip/SoC/xilinx_IP/axi_full_Xbar ^ 26 | ../tb/riftChip_TB.v 27 | 28 | @pause 29 | 30 | vvp.exe -N ./build/wave.iverilog -lxt2 31 | 32 | rem @pause 33 | 34 | 35 | -------------------------------------------------------------------------------- /tb/module_test/axi_ccm_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: axi_ccm_tb 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-21 16:46:54 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-21 17:07:23 8 | */ 9 | 10 | 11 | `timescale 1 ns / 1 ps 12 | 13 | 14 | 15 | module axi_ccm_tb ( 16 | 17 | ); 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | reg [63:0] S_AXI_AWADDR; 26 | reg S_AXI_AWVALID; 27 | wire S_AXI_AWREADY; 28 | reg [63:0] S_AXI_WDATA; 29 | reg [7:0] S_AXI_WSTRB; 30 | reg S_AXI_WVALID; 31 | wire S_AXI_WREADY; 32 | wire [1:0] S_AXI_BRESP; 33 | wire S_AXI_BVALID; 34 | reg S_AXI_BREADY; 35 | reg [63:0] S_AXI_ARADDR; 36 | reg S_AXI_ARVALID; 37 | wire S_AXI_ARREADY; 38 | wire [63:0] S_AXI_RDATA; 39 | wire [1:0] S_AXI_RRESP; 40 | wire S_AXI_RVALID; 41 | reg S_AXI_RREADY; 42 | reg CLK; 43 | reg RSTn; 44 | 45 | 46 | 47 | 48 | axi_ccm s_axi_ccm 49 | ( 50 | .S_AXI_AWADDR (S_AXI_AWADDR), 51 | .S_AXI_AWVALID(S_AXI_AWVALID), 52 | .S_AXI_AWREADY(S_AXI_AWREADY), 53 | .S_AXI_WDATA (S_AXI_WDATA), 54 | .S_AXI_WSTRB (S_AXI_WSTRB), 55 | .S_AXI_WVALID (S_AXI_WVALID), 56 | .S_AXI_WREADY (S_AXI_WREADY), 57 | .S_AXI_BRESP (S_AXI_BRESP), 58 | .S_AXI_BVALID (S_AXI_BVALID), 59 | .S_AXI_BREADY (S_AXI_BREADY), 60 | .S_AXI_ARADDR (S_AXI_ARADDR), 61 | .S_AXI_ARVALID(S_AXI_ARVALID), 62 | .S_AXI_ARREADY(S_AXI_ARREADY), 63 | .S_AXI_RDATA (S_AXI_RDATA), 64 | .S_AXI_RRESP (S_AXI_RRESP), 65 | .S_AXI_RVALID (S_AXI_RVALID), 66 | .S_AXI_RREADY (S_AXI_RREADY), 67 | .CLK (CLK), 68 | .RSTn (RSTn) 69 | ); 70 | 71 | 72 | initial begin 73 | forever 74 | begin 75 | #5 CLK <= ~CLK; 76 | end 77 | end 78 | 79 | initial begin 80 | 81 | 82 | CLK = 0; 83 | RSTn = 0; 84 | 85 | s_axi_ccm.i_sram_odd.ram[0] = 64'h01234567_89abcdef; 86 | s_axi_ccm.i_sram_eve.ram[0] = 64'hfedcba98_76543210; 87 | 88 | S_AXI_AWADDR = 64'b0; 89 | S_AXI_AWVALID = 1'b0; 90 | S_AXI_WDATA = 64'b0; 91 | S_AXI_WSTRB = 8'b0; 92 | S_AXI_WVALID = 1'b0; 93 | S_AXI_BREADY = 1'b0; 94 | S_AXI_ARADDR = 64'b0; 95 | S_AXI_ARVALID = 1'b0; 96 | S_AXI_RREADY = 1'b0; 97 | 98 | #20 99 | 100 | RSTn <= 1; 101 | 102 | #50 103 | 104 | S_AXI_AWADDR = 64'b0; 105 | S_AXI_AWVALID = 1'b0; 106 | S_AXI_WDATA = 64'b0; 107 | S_AXI_WSTRB = 8'b0; 108 | S_AXI_WVALID = 1'b0; 109 | S_AXI_BREADY = 1'b0; 110 | S_AXI_ARADDR = 64'h80000009; 111 | S_AXI_ARVALID = 1'b1; 112 | S_AXI_RREADY = 1'b0; 113 | 114 | 115 | 116 | #80000 117 | 118 | $finish; 119 | end 120 | 121 | 122 | initial 123 | begin 124 | $dumpfile("../build/axi_ccm.vcd"); //生成的vcd文件名称 125 | $dumpvars(0, axi_ccm_tb);//tb模块名称 126 | end 127 | 128 | endmodule 129 | 130 | 131 | 132 | -------------------------------------------------------------------------------- /tb/module_test/corssbar_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: corssbar_tb 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-01-14 11:36:12 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-14 12:11:52 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | 28 | `timescale 1 ns / 1 ps 29 | 30 | 31 | 32 | module corssbar_tb ( 33 | 34 | ); 35 | 36 | 37 | 38 | 39 | reg lsu_mstReq_valid; 40 | wire lsu_mstReq_ready; 41 | reg [63:0] lsu_addr; 42 | reg [63:0] lsu_data_w; 43 | wire [63:0] lsu_data_r; 44 | reg [7:0] lsu_wstrb; 45 | reg lsu_wen; 46 | wire lsu_slvRsp_valid; 47 | 48 | reg ifu_mstReq_valid; 49 | wire ifu_mstReq_ready; 50 | reg [63:0] ifu_addr; 51 | reg [63:0] ifu_data_w; 52 | wire [63:0] ifu_data_r; 53 | reg [7:0] ifu_wstrb; 54 | reg ifu_wen; 55 | wire ifu_slvRsp_valid; 56 | 57 | wire clint_mstReq_valid; 58 | reg clint_mstReq_ready; 59 | wire [63:0] clint_addr; 60 | wire [63:0] clint_data_w; 61 | reg [63:0] clint_data_r; 62 | wire [7:0] clint_wstrb; 63 | wire clint_wen; 64 | reg clint_slvRsp_valid; 65 | 66 | wire plic_mstReq_valid; 67 | reg plic_mstReq_ready; 68 | wire [63:0] plic_addr; 69 | wire [63:0] plic_data_w; 70 | reg [63:0] plic_data_r; 71 | wire [7:0] plic_wstrb; 72 | wire plic_wen; 73 | reg plic_slvRsp_valid; 74 | 75 | wire sysbus_mstReq_valid; 76 | reg sysbus_mstReq_ready; 77 | wire [63:0] sysbus_addr; 78 | wire [63:0] sysbus_data_w; 79 | reg [63:0] sysbus_data_r; 80 | wire [7:0] sysbus_wstrb; 81 | wire sysbus_wen; 82 | reg sysbus_slvRsp_valid; 83 | 84 | wire perip_mstReq_valid; 85 | reg perip_mstReq_ready; 86 | wire [63:0] perip_addr; 87 | wire [63:0] perip_data_w; 88 | reg [63:0] perip_data_r; 89 | wire [7:0] perip_wstrb; 90 | wire perip_wen; 91 | reg perip_slvRsp_valid; 92 | 93 | wire mem_mstReq_valid; 94 | reg mem_mstReq_ready; 95 | wire [63:0] mem_addr; 96 | wire [63:0] mem_data_w; 97 | reg [63:0] mem_data_r; 98 | wire [7:0] mem_wstrb; 99 | wire mem_wen; 100 | reg mem_slvRsp_valid; 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | innerbus_crossbar s_Xbar( 113 | 114 | .dm_mstReq_valid(1'b0), 115 | .dm_mstReq_ready(), 116 | .dm_addr('d0), 117 | .dm_data_w('d0), 118 | .dm_data_r(), 119 | .dm_wstrb('d0), 120 | .dm_wen('b0), 121 | .dm_slvRsp_valid(), 122 | 123 | .lsu_mstReq_valid(lsu_mstReq_valid), 124 | .lsu_mstReq_ready(lsu_mstReq_ready), 125 | .lsu_addr(lsu_addr), 126 | .lsu_data_w(lsu_data_w), 127 | .lsu_data_r(lsu_data_r), 128 | .lsu_wstrb(lsu_wstrb), 129 | .lsu_wen(lsu_wen), 130 | .lsu_slvRsp_valid(lsu_slvRsp_valid), 131 | 132 | .ifu_mstReq_valid(ifu_mstReq_valid), 133 | .ifu_mstReq_ready(ifu_mstReq_ready), 134 | .ifu_addr(ifu_addr), 135 | .ifu_data_w(ifu_data_w), 136 | .ifu_data_r(ifu_data_r), 137 | .ifu_wstrb(ifu_wstrb), 138 | .ifu_wen(ifu_wen), 139 | .ifu_slvRsp_valid(ifu_slvRsp_valid), 140 | 141 | .clint_mstReq_valid(clint_mstReq_valid), 142 | .clint_mstReq_ready(clint_mstReq_ready), 143 | .clint_addr(clint_addr), 144 | .clint_data_w(clint_data_w), 145 | .clint_data_r(clint_data_r), 146 | .clint_wstrb(clint_wstrb), 147 | .clint_wen(clint_wen), 148 | .clint_slvRsp_valid(clint_slvRsp_valid), 149 | 150 | output plic_mstReq_valid, 151 | input plic_mstReq_ready, 152 | output [63:0] plic_addr, 153 | output [63:0] plic_data_w, 154 | input [63:0] plic_data_r, 155 | output [7:0] plic_wstrb, 156 | output plic_wen, 157 | input plic_slvRsp_valid, 158 | 159 | output sysbus_mstReq_valid, 160 | input sysbus_mstReq_ready, 161 | output [63:0] sysbus_addr, 162 | output [63:0] sysbus_data_w, 163 | input [63:0] sysbus_data_r, 164 | output [7:0] sysbus_wstrb, 165 | output sysbus_wen, 166 | input sysbus_slvRsp_valid, 167 | 168 | output perip_mstReq_valid, 169 | input perip_mstReq_ready, 170 | output [63:0] perip_addr, 171 | output [63:0] perip_data_w, 172 | input [63:0] perip_data_r, 173 | output [7:0] perip_wstrb, 174 | output perip_wen, 175 | input perip_slvRsp_valid, 176 | 177 | output mem_mstReq_valid, 178 | input mem_mstReq_ready, 179 | output [63:0] mem_addr, 180 | output [63:0] mem_data_w, 181 | input [63:0] mem_data_r, 182 | output [7:0] mem_wstrb, 183 | output mem_wen, 184 | input mem_slvRsp_valid, 185 | 186 | input feflush, 187 | input beflush, 188 | input CLK, 189 | input RSTn 190 | 191 | 192 | ); 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | endmodule 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | -------------------------------------------------------------------------------- /tb/module_test/dcache_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: dcache_tb 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-03-04 10:38:19 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-04 14:27:37 8 | */ 9 | 10 | 11 | 12 | 13 | /* 14 | Copyright (c) 2020 - 2021 Ruige Lee 15 | 16 | Licensed under the Apache License, Version 2.0 (the "License"); 17 | you may not use this file except in compliance with the License. 18 | You may obtain a copy of the License at 19 | 20 | http://www.apache.org/licenses/LICENSE-2.0 21 | 22 | Unless required by applicable law or agreed to in writing, software 23 | distributed under the License is distributed on an "AS IS" BASIS, 24 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | See the License for the specific language governing permissions and 26 | limitations under the License. 27 | */ 28 | 29 | 30 | 31 | `timescale 1 ns / 1 ps 32 | 33 | module dcache_tb ( 34 | 35 | ); 36 | 37 | reg lsu_req_valid; 38 | reg [31:0] lsu_addr_req; 39 | reg [63:0] lsu_wdata_req; 40 | reg [7:0] lsu_wstrb_req; 41 | reg lsu_wen_req; 42 | reg lsu_rsp_ready; 43 | 44 | wire lsu_req_ready; 45 | wire [31:0] lsu_rdata_rsp; 46 | wire lsu_rsp_valid; 47 | 48 | 49 | 50 | 51 | reg dl1_fence; 52 | reg CLK; 53 | reg RSTn; 54 | 55 | 56 | 57 | 58 | 59 | wire [31:0] DL1_AWADDR; 60 | wire [7:0] DL1_AWLEN; 61 | wire [1:0] DL1_AWBURST; 62 | wire DL1_AWVALID; 63 | wire DL1_AWREADY; 64 | 65 | wire [63:0] DL1_WDATA; 66 | wire [7:0] DL1_WSTRB; 67 | wire DL1_WLAST; 68 | wire DL1_WVALID; 69 | wire DL1_WREADY; 70 | 71 | wire [1:0] DL1_BRESP; 72 | wire DL1_BVALID; 73 | wire DL1_BREADY; 74 | 75 | wire [31:0] DL1_ARADDR; 76 | wire [7:0] DL1_ARLEN; 77 | wire [1:0] DL1_ARBURST; 78 | wire DL1_ARVALID; 79 | wire DL1_ARREADY; 80 | 81 | wire [63:0] DL1_RDATA; 82 | wire [1:0] DL1_RRESP; 83 | wire DL1_RLAST; 84 | wire DL1_RVALID; 85 | wire DL1_RREADY; 86 | 87 | 88 | 89 | dcache i_dcache 90 | ( 91 | .DL1_AWADDR(DL1_AWADDR), 92 | .DL1_AWLEN(DL1_AWLEN), 93 | .DL1_AWBURST(DL1_AWBURST), 94 | .DL1_AWVALID(DL1_AWVALID), 95 | .DL1_AWREADY(DL1_AWREADY), 96 | 97 | .DL1_WDATA(DL1_WDATA), 98 | .DL1_WSTRB(DL1_WSTRB), 99 | .DL1_WLAST(DL1_WLAST), 100 | .DL1_WVALID(DL1_WVALID), 101 | .DL1_WREADY(DL1_WREADY), 102 | 103 | .DL1_BRESP(DL1_BRESP), 104 | .DL1_BVALID(DL1_BVALID), 105 | .DL1_BREADY(DL1_BREADY), 106 | 107 | .DL1_ARADDR(DL1_ARADDR), 108 | .DL1_ARLEN(DL1_ARLEN), 109 | .DL1_ARBURST(DL1_ARBURST), 110 | .DL1_ARVALID(DL1_ARVALID), 111 | .DL1_ARREADY(DL1_ARREADY), 112 | 113 | .DL1_RDATA(DL1_RDATA), 114 | .DL1_RRESP(DL1_RRESP), 115 | .DL1_RLAST(DL1_RLAST), 116 | .DL1_RVALID(DL1_RVALID), 117 | .DL1_RREADY(DL1_RREADY), 118 | 119 | //from lsu 120 | .lsu_req_valid(lsu_req_valid), 121 | .lsu_req_ready(lsu_req_ready), 122 | .lsu_addr_req(lsu_addr_req), 123 | .lsu_wdata_req(lsu_wdata_req), 124 | .lsu_wstrb_req(lsu_wstrb_req), 125 | .lsu_wen_req(lsu_wen_req), 126 | 127 | .lsu_rdata_rsp(lsu_rdata_rsp), 128 | .lsu_rsp_valid(lsu_rsp_valid), 129 | .lsu_rsp_ready(lsu_rsp_ready), 130 | 131 | 132 | 133 | .dl1_fence(dl1_fence), 134 | .CLK(CLK), 135 | .RSTn(RSTn) 136 | ); 137 | 138 | 139 | 140 | 141 | axi_full_slv_sram s_axi_full_slv_sram 142 | ( 143 | 144 | .S_AXI_AWADDR(DL1_AWADDR), 145 | .S_AXI_AWLEN(DL1_AWLEN), 146 | .S_AXI_AWSIZE(3'd3), 147 | .S_AXI_AWBURST(DL1_AWBURST), 148 | .S_AXI_AWVALID(DL1_AWVALID), 149 | .S_AXI_AWREADY(DL1_AWREADY), 150 | 151 | .S_AXI_WDATA(DL1_WDATA), 152 | .S_AXI_WSTRB(DL1_WSTRB), 153 | .S_AXI_WLAST(DL1_WLAST), 154 | .S_AXI_WVALID(DL1_WVALID), 155 | .S_AXI_WREADY(DL1_WREADY), 156 | 157 | .S_AXI_BRESP(DL1_BRESP), 158 | .S_AXI_BVALID(DL1_BVALID), 159 | .S_AXI_BREADY(DL1_BREADY), 160 | 161 | .S_AXI_ARADDR(DL1_ARADDR), 162 | .S_AXI_ARLEN(DL1_ARLEN), 163 | .S_AXI_ARSIZE(3'd3), 164 | .S_AXI_ARBURST(DL1_ARBURST), 165 | .S_AXI_ARVALID(DL1_ARVALID), 166 | .S_AXI_ARREADY(DL1_ARREADY), 167 | 168 | .S_AXI_RDATA(DL1_RDATA), 169 | .S_AXI_RRESP(DL1_RRESP), 170 | .S_AXI_RLAST(DL1_RLAST), 171 | .S_AXI_RVALID(DL1_RVALID), 172 | .S_AXI_RREADY(DL1_RREADY), 173 | 174 | .CLK(CLK), 175 | .RSTn(RSTn) 176 | ); 177 | 178 | 179 | 180 | initial 181 | begin 182 | $dumpfile("../build/wave.vcd"); //生成的vcd文件名称 183 | $dumpvars(0, dcache_tb);//tb模块名称 184 | end 185 | 186 | 187 | 188 | initial begin 189 | 190 | CLK = 0; 191 | RSTn = 0; 192 | 193 | #20 194 | 195 | RSTn <= 1; 196 | 197 | #80000 198 | $display("Time Out !!!"); 199 | $finish; 200 | end 201 | 202 | initial begin 203 | forever begin 204 | #5 CLK <= ~CLK; 205 | end 206 | end 207 | 208 | 209 | 210 | 211 | 212 | initial begin 213 | 214 | lsu_addr_req = 32'h18; 215 | lsu_wdata_req = 8'haa; 216 | lsu_wstrb_req = 8'hff; 217 | lsu_wen_req = 1'b0; 218 | 219 | lsu_rsp_ready = 1'b1; 220 | lsu_req_valid = 1'b0; 221 | dl1_fence = 1'b0; 222 | #100 223 | 224 | #22 225 | lsu_req_valid = 1'b1; 226 | lsu_wen_req = 1'b0; 227 | #10 228 | lsu_req_valid = 1'b0; 229 | lsu_wen_req = 1'b0; 230 | 231 | #1000 232 | lsu_req_valid = 1'b1; 233 | lsu_wen_req = 1'b1; 234 | 235 | #10 236 | lsu_req_valid = 1'b0; 237 | lsu_wen_req = 1'b0; 238 | 239 | #1000 240 | lsu_req_valid = 1'b1; 241 | lsu_wen_req = 1'b0; 242 | 243 | #10 244 | lsu_req_valid = 1'b0; 245 | lsu_wen_req = 1'b0; 246 | end 247 | 248 | 249 | 250 | 251 | endmodule 252 | 253 | 254 | 255 | -------------------------------------------------------------------------------- /tb/module_test/div_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: div_tb 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-12-23 14:37:23 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-01-03 12:08:10 8 | */ 9 | 10 | 11 | /* 12 | Copyright (c) 2020 - 2021 Ruige Lee 13 | 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | you may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | 18 | http://www.apache.org/licenses/LICENSE-2.0 19 | 20 | Unless required by applicable law or agreed to in writing, software 21 | distributed under the License is distributed on an "AS IS" BASIS, 22 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | See the License for the specific language governing permissions and 24 | limitations under the License. 25 | */ 26 | 27 | `timescale 1 ns / 1 ps 28 | 29 | 30 | 31 | module div_tb ( 32 | 33 | ); 34 | reg CLK; 35 | reg RSTn; 36 | reg mulDiv_exeparam_valid; 37 | reg rv64m_div,rv64m_divu, rv64m_rem, rv64m_remu, rv64m_divw, rv64m_divuw, rv64_remw, rv64m_remuw; 38 | 39 | reg [63:0] src1; 40 | reg [63:0] src2; 41 | 42 | 43 | 44 | 45 | 46 | 47 | //div 48 | wire div_fun = 49 | rv64m_div 50 | | rv64m_divu 51 | | rv64m_rem 52 | | rv64m_remu 53 | | rv64m_divw 54 | | rv64m_divuw 55 | | rv64_remw 56 | | rv64m_remuw; 57 | 58 | wire is32w = rv64m_divw | rv64m_divuw | rv64_remw | rv64m_remuw; 59 | wire isUsi = rv64m_divu | rv64m_remu | rv64m_divuw | rv64m_remuw; 60 | 61 | 62 | wire [127:0] dividend_dnxt, dividend_qout; 63 | wire [63:0] divisor_dnxt, divisor_qout; 64 | wire [63:0] div_res_dnxt, div_res_qout; 65 | wire [6:0] div_cnt_dnxt, div_cnt_qout; 66 | 67 | wire [63:0] dividend_load = isUsi ? 68 | src1 : 69 | ( 70 | is32w ? 71 | { 32'b0, (src1[31] ? $signed(-src1[31:0]) : src1[31:0])} : 72 | (src1[63] ? $signed(-src1) : src1) 73 | ); 74 | 75 | wire [63:0] divisor_load = isUsi ? 76 | src2 : 77 | ( 78 | is32w ? 79 | { {32'b0}, (src2[31] ? $signed(-src2[31:0]) : src2[31:0])} : 80 | (src2[63] ? $signed(-src2) : src2) 81 | ); 82 | 83 | 84 | wire div_cmp; 85 | wire [127:0] dividend_shift; 86 | wire [127:0] divided; 87 | 88 | assign dividend_dnxt = 89 | (mulDiv_exeparam_valid & div_fun) ? 90 | {64'd0, dividend_load} : 91 | ((div_cnt_qout == 6'd0) ? dividend_qout : divided) 92 | ; 93 | 94 | assign divisor_dnxt = (mulDiv_exeparam_valid & div_fun) ? 95 | divisor_load : 96 | divisor_qout; 97 | 98 | 99 | assign div_cnt_dnxt = (mulDiv_exeparam_valid & div_fun) ? 100 | 7'd64 : 101 | (div_cnt_qout == 6'd0 ? div_cnt_qout : div_cnt_qout - 1); 102 | 103 | 104 | assign dividend_shift = dividend_qout << 1; 105 | assign div_cmp = dividend_shift[127:64] >= divisor_qout; 106 | assign divided = div_cmp ? 107 | {(dividend_shift[127:64] - divisor_qout), dividend_shift[63:1], 1'b1} : 108 | dividend_shift; 109 | 110 | 111 | 112 | wire dividend_sign = isUsi ? 1'b0 : (is32w ? src1[31] : src1[63]); 113 | wire divisor_sign = isUsi ? 1'b0 : (is32w ? src2[31] : src2[63]); 114 | wire div_by_zero = (src2 == 64'd0); 115 | wire div_overflow = ~isUsi & 116 | ( 117 | (is32w & (src1[31] & ~src1[30:0]) & (&src2[31:0])) 118 | | 119 | (~is32w & (src1[63] & ~src1[62:0]) & (&src2[63:0])) 120 | ); 121 | 122 | 123 | 124 | wire [63:0] quot = 125 | ({64{div_by_zero}} & {64{1'b1}}) 126 | | 127 | ({64{div_overflow}} & (is32w ? { {33{1'b1}}, 31'b0 } : {1'b1, 63'b0})) 128 | | 129 | ( 130 | {64{(~div_by_zero)&(~div_overflow)}} & 131 | dividend_sign ? $signed(-dividend_qout[63:0]) : dividend_qout[63:0] 132 | ); 133 | 134 | wire [63:0] rema = 135 | ({64{div_by_zero}} & (is32w ? { {32{src1[31]}}, src1} : src1 ) ) 136 | | 137 | ({64{div_overflow}} & 64'd0 ) 138 | | 139 | ( 140 | {64{(~div_by_zero)&(~div_overflow)}} & 141 | (dividend_sign^divisor_sign) ? $signed(-dividend_qout[127:64]): dividend_qout[127:64] 142 | ); 143 | 144 | 145 | 146 | 147 | 148 | 149 | gen_dffr # (.DW(128)) dividend ( .dnxt(dividend_dnxt), .qout(dividend_qout), .CLK(CLK), .RSTn(RSTn)); 150 | gen_dffr # (.DW(64)) divisor ( .dnxt(divisor_dnxt), .qout(divisor_qout), .CLK(CLK), .RSTn(RSTn)); 151 | gen_dffr # (.DW(7)) div_cnt ( .dnxt(div_cnt_dnxt), .qout(div_cnt_qout), .CLK(CLK), .RSTn(RSTn)); 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | initial 161 | begin 162 | $dumpfile("../build/div_tb.vcd"); //生成的vcd文件名称 163 | $dumpvars(0, div_tb);//tb模块名称 164 | end 165 | 166 | 167 | 168 | initial begin 169 | 170 | CLK = 0; 171 | RSTn = 0; 172 | 173 | #20 174 | 175 | RSTn <= 1; 176 | 177 | #8000 178 | $display("Time Out !!!"); 179 | $finish; 180 | end 181 | 182 | initial begin 183 | forever begin 184 | #5 CLK <= ~CLK; 185 | end 186 | end 187 | 188 | initial begin 189 | 190 | mulDiv_exeparam_valid = 0; 191 | rv64m_div = 0; 192 | rv64m_divu = 0; 193 | rv64m_rem = 0; 194 | rv64m_remu = 0; 195 | rv64m_divw = 0; 196 | rv64m_divuw = 0; 197 | rv64_remw = 0; 198 | rv64m_remuw = 0; 199 | 200 | src1 = 0; 201 | src2 = 0; 202 | 203 | #36 204 | 205 | mulDiv_exeparam_valid = 1; 206 | rv64m_div = 0; 207 | rv64m_divu = 1; 208 | rv64m_rem = 0; 209 | rv64m_remu = 0; 210 | rv64m_divw = 0; 211 | rv64m_divuw = 0; 212 | rv64_remw = 0; 213 | rv64m_remuw = 0; 214 | 215 | src1 = 64'hffffffffffff0000; 216 | src2 = 1; 217 | 218 | # 10 219 | 220 | mulDiv_exeparam_valid = 0; 221 | 222 | 223 | 224 | 225 | end 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | endmodule 259 | 260 | 261 | 262 | -------------------------------------------------------------------------------- /tb/module_test/icache_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: icache_tb 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2021-03-04 10:38:19 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-04 15:10:32 8 | */ 9 | 10 | 11 | 12 | 13 | /* 14 | Copyright (c) 2020 - 2021 Ruige Lee 15 | 16 | Licensed under the Apache License, Version 2.0 (the "License"); 17 | you may not use this file except in compliance with the License. 18 | You may obtain a copy of the License at 19 | 20 | http://www.apache.org/licenses/LICENSE-2.0 21 | 22 | Unless required by applicable law or agreed to in writing, software 23 | distributed under the License is distributed on an "AS IS" BASIS, 24 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | See the License for the specific language governing permissions and 26 | limitations under the License. 27 | */ 28 | 29 | 30 | 31 | `timescale 1 ns / 1 ps 32 | 33 | module icache_tb ( 34 | 35 | ); 36 | 37 | 38 | wire ifu_req_ready; 39 | wire [63:0] ifu_data_rsp; 40 | wire ifu_rsp_valid; 41 | 42 | reg ifu_rsp_ready; 43 | reg ifu_req_valid; 44 | reg [31:0] ifu_addr_req; 45 | 46 | reg il1_fence; 47 | reg CLK; 48 | reg RSTn; 49 | 50 | 51 | 52 | 53 | 54 | wire [31:0] IL1_ARADDR; 55 | wire [7:0] IL1_ARLEN; 56 | wire [1:0] IL1_ARBURST; 57 | wire IL1_ARVALID; 58 | wire IL1_ARREADY; 59 | 60 | wire [63:0] IL1_RDATA; 61 | wire [1:0] IL1_RRESP; 62 | wire IL1_RLAST; 63 | wire IL1_RVALID; 64 | wire IL1_RREADY; 65 | 66 | 67 | icache i_icache( 68 | 69 | .IL1_ARADDR(IL1_ARADDR), 70 | .IL1_ARLEN(IL1_ARLEN), 71 | .IL1_ARBURST(IL1_ARBURST), 72 | .IL1_ARVALID(IL1_ARVALID), 73 | .IL1_ARREADY(IL1_ARREADY), 74 | .IL1_RDATA(IL1_RDATA), 75 | .IL1_RRESP(IL1_RRESP), 76 | .IL1_RLAST(IL1_RLAST), 77 | .IL1_RVALID(IL1_RVALID), 78 | .IL1_RREADY(IL1_RREADY), 79 | 80 | .ifu_req_valid(ifu_req_valid), 81 | .ifu_req_ready(ifu_req_ready), 82 | .ifu_addr_req(ifu_addr_req), 83 | .ifu_data_rsp(ifu_data_rsp), 84 | .ifu_rsp_valid(ifu_rsp_valid), 85 | .ifu_rsp_ready(ifu_rsp_ready), 86 | 87 | .il1_fence(il1_fence), 88 | .CLK(CLK), 89 | .RSTn(RSTn) 90 | 91 | ); 92 | 93 | 94 | 95 | 96 | axi_full_slv_sram s_axi_full_slv_sram 97 | ( 98 | 99 | .S_AXI_AWADDR(32'h0), 100 | .S_AXI_AWLEN(8'h0), 101 | .S_AXI_AWSIZE(3'h0), 102 | .S_AXI_AWBURST(2'h0), 103 | .S_AXI_AWVALID(1'b0), 104 | .S_AXI_AWREADY(), 105 | 106 | .S_AXI_WDATA(64'h0), 107 | .S_AXI_WSTRB(8'h0), 108 | .S_AXI_WLAST(1'b1), 109 | .S_AXI_WVALID(1'b0), 110 | .S_AXI_WREADY(), 111 | 112 | .S_AXI_BRESP(), 113 | .S_AXI_BVALID(), 114 | .S_AXI_BREADY(1'b1), 115 | 116 | .S_AXI_ARADDR(IL1_ARADDR), 117 | .S_AXI_ARLEN(IL1_ARLEN), 118 | .S_AXI_ARSIZE(3'd3), 119 | .S_AXI_ARBURST(IL1_ARBURST), 120 | .S_AXI_ARVALID(IL1_ARVALID), 121 | .S_AXI_ARREADY(IL1_ARREADY), 122 | 123 | .S_AXI_RDATA(IL1_RDATA), 124 | .S_AXI_RRESP(IL1_RRESP), 125 | .S_AXI_RLAST(IL1_RLAST), 126 | .S_AXI_RVALID(IL1_RVALID), 127 | .S_AXI_RREADY(IL1_RREADY), 128 | 129 | .CLK(CLK), 130 | .RSTn(RSTn) 131 | ); 132 | 133 | 134 | 135 | initial 136 | begin 137 | $dumpfile("../build/wave.vcd"); //生成的vcd文件名称 138 | $dumpvars(0, icache_tb);//tb模块名称 139 | end 140 | 141 | 142 | 143 | initial begin 144 | 145 | CLK = 0; 146 | RSTn = 0; 147 | 148 | #20 149 | 150 | RSTn <= 1; 151 | 152 | #80000 153 | $display("Time Out !!!"); 154 | $finish; 155 | end 156 | 157 | initial begin 158 | forever begin 159 | #5 CLK <= ~CLK; 160 | end 161 | end 162 | 163 | 164 | 165 | 166 | 167 | initial begin 168 | ifu_rsp_ready = 1'b1; 169 | ifu_req_valid = 1'b0; 170 | ifu_addr_req = 32'h18; 171 | 172 | il1_fence = 1'b0; 173 | 174 | #100 175 | 176 | #22 177 | ifu_req_valid = 1'b1; 178 | ifu_addr_req = 32'h18; 179 | #10 180 | ifu_req_valid = 1'b0; 181 | 182 | #1000 183 | ifu_req_valid = 1'b1; 184 | ifu_addr_req = 32'h10; 185 | #10 186 | ifu_req_valid = 1'b0; 187 | 188 | 189 | #1000 190 | ifu_req_valid = 1'b1; 191 | ifu_addr_req = 32'h80000010; 192 | #10 193 | ifu_req_valid = 1'b0; 194 | 195 | #1000 196 | ifu_req_valid = 1'b1; 197 | ifu_addr_req = 32'h90000010; 198 | #10 199 | ifu_req_valid = 1'b0; 200 | 201 | end 202 | 203 | 204 | 205 | 206 | endmodule 207 | 208 | 209 | 210 | -------------------------------------------------------------------------------- /tb/module_test/iverilogCompile.bat: -------------------------------------------------------------------------------- 1 | @REM @Author: Ruige Lee 2 | @REM @Date: 2020-11-02 11:29:57 3 | @REM @Last Modified by: Ruige Lee 4 | @REM Modified time: 2021-03-11 14:57:23 5 | 6 | 7 | 8 | 9 | iverilog.exe -W all -o ../build/mem_access_tb.iverilog ^ 10 | -y ../../RiftChip/ ^ 11 | -y ../../RiftChip/riftCore/ ^ 12 | -y ../../RiftChip/riftCore/backend ^ 13 | -y ../../RiftChip/riftCore/backend/issue ^ 14 | -y ../../RiftChip/riftCore/backend/execute ^ 15 | -y ../../RiftChip/riftCore/frontend ^ 16 | -y ../../RiftChip/riftCore/cache ^ 17 | -y ../../RiftChip/element ^ 18 | -y ../../RiftChip/Soc ^ 19 | -y ../../RiftChip/Soc/xilinx_IP/axi_Xbar ^ 20 | -y ../../RiftChip/debug ^ 21 | -y ../../tb ^ 22 | -y ../../tb/module_test ^ 23 | -I ../../tb ^ 24 | -I ../../RiftChip ^ 25 | ./mem_access_tb.v 26 | 27 | @pause 28 | 29 | vvp.exe -N ../build/mem_access_tb.iverilog -lxt2 30 | 31 | rem @pause 32 | 33 | 34 | rem gtkwave.exe ../build/axi_ccm.vcd 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /tb/riftChip_CI.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: riftChip_CI 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-11-05 17:03:49 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-18 14:35:01 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | `include "iverilog.vh" 29 | `include "define.vh" 30 | 31 | 32 | module riftChip_CI ( 33 | 34 | ); 35 | 36 | reg CLK; 37 | reg RSTn; 38 | 39 | 40 | 41 | riftChip s_riftChip( 42 | 43 | .CLK(CLK), 44 | .RSTn(RSTn) 45 | ); 46 | 47 | 48 | reg [255:0] testName; 49 | 50 | 51 | 52 | 53 | 54 | initial begin 55 | if ( $value$plusargs("%s",testName[255:0]) ) begin 56 | $display("%s",testName); 57 | end 58 | 59 | CLK = 0; 60 | RSTn = 0; 61 | 62 | #20 63 | 64 | RSTn <= 1; 65 | 66 | #160000 67 | $display("Time Out !!!"); 68 | $stop; 69 | end 70 | 71 | 72 | initial begin 73 | forever 74 | begin 75 | #5 CLK <= ~CLK; 76 | end 77 | end 78 | 79 | 80 | 81 | 82 | `define SRAM s_riftChip.i_axi_full_slv_sram.i_sram 83 | 84 | `define RGF s_riftChip.i_riftCore.i_backEnd.i_phyRegister.regFileX_qout 85 | `define INDEX s_riftChip.i_riftCore.i_backEnd.i_phyRegister.archi_X_qout[`RB*3 +: `RB] 86 | 87 | 88 | 89 | localparam DP = 2**14; 90 | integer i, by; 91 | 92 | reg [7:0] mem [0:200000]; 93 | initial begin 94 | $readmemh(testName, mem); 95 | for ( i = 0; i < DP; i = i + 1 ) begin 96 | for ( by = 0; by < 8; by = by + 1 ) begin 97 | if ( | mem[i*8+by] ) begin 98 | `SRAM.ram[i][8*by +: 8] = mem[i*8+by]; 99 | end 100 | else begin 101 | `SRAM.ram[i][8*by +: 8] = 8'h0; 102 | end 103 | end 104 | 105 | // $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]); 106 | end 107 | end 108 | 109 | 110 | wire [63:0] x3 = `RGF[(3*`RP+`INDEX)*64 +: 64]; 111 | wire isEcall = s_riftChip.i_riftCore.i_backEnd.i_commit.isEcall; 112 | 113 | always @(negedge CLK)begin 114 | if (isEcall) begin 115 | if ( x3 == 64'd1 ) begin 116 | $display("PASS"); 117 | $finish; 118 | end 119 | else begin 120 | $display("Fail"); 121 | $stop; 122 | end 123 | 124 | 125 | 126 | end 127 | 128 | end 129 | 130 | 131 | 132 | 133 | 134 | endmodule 135 | 136 | 137 | -------------------------------------------------------------------------------- /tb/riftChip_DS.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: riftChip_DS 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-11-05 17:03:49 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-18 16:03:54 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | `include "define.vh" 29 | 30 | 31 | module riftChip_DS ( 32 | 33 | ); 34 | 35 | 36 | reg CLK; 37 | reg RSTn; 38 | 39 | 40 | riftChip s_riftChip( 41 | 42 | .CLK(CLK), 43 | .RSTn(RSTn) 44 | ); 45 | 46 | 47 | 48 | initial begin 49 | 50 | 51 | CLK = 0; 52 | RSTn = 0; 53 | 54 | #20 55 | 56 | RSTn <= 1; 57 | 58 | 59 | end 60 | 61 | 62 | initial begin 63 | forever 64 | begin 65 | #5 CLK <= ~CLK; 66 | end 67 | end 68 | 69 | 70 | 71 | `define SRAM s_riftChip.i_axi_full_slv_sram.i_sram 72 | 73 | `define RGF s_riftChip.i_riftCore.i_backEnd.i_phyRegister.regFileX_qout 74 | `define INDEX s_riftChip.i_riftCore.i_backEnd.i_phyRegister.archi_X_qout[`RB*3 +: `RB] 75 | 76 | 77 | 78 | 79 | localparam DP = 2**14; 80 | integer i, by; 81 | 82 | reg [7:0] mem [0:200000]; 83 | initial begin 84 | $readmemh("./ci/dhrystone.riscv.verilog", mem); 85 | for ( i = 0; i < DP; i = i + 1 ) begin 86 | for ( by = 0; by < 8; by = by + 1 ) begin 87 | if ( | mem[i*8+by] ) begin 88 | `SRAM.ram[i][8*by +: 8] = mem[i*8+by]; 89 | end 90 | else begin 91 | `SRAM.ram[i][8*by +: 8] = 8'h0; 92 | end 93 | end 94 | 95 | // $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]); 96 | end 97 | 98 | end 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | // initial 107 | // begin 108 | // $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 109 | // $dumpvars(0, riftChip_DS);//tb模块名称 110 | // end 111 | 112 | endmodule 113 | 114 | 115 | -------------------------------------------------------------------------------- /tb/riftChip_TB.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @File name: riftChip_TB 3 | * @Author: Ruige Lee 4 | * @Email: wut.ruigeli@gmail.com 5 | * @Date: 2020-11-05 17:03:49 6 | * @Last Modified by: Ruige Lee 7 | * @Last Modified time: 2021-03-18 14:33:37 8 | */ 9 | 10 | /* 11 | Copyright (c) 2020 - 2021 Ruige Lee 12 | 13 | Licensed under the Apache License, Version 2.0 (the "License"); 14 | you may not use this file except in compliance with the License. 15 | You may obtain a copy of the License at 16 | 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | 19 | Unless required by applicable law or agreed to in writing, software 20 | distributed under the License is distributed on an "AS IS" BASIS, 21 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | See the License for the specific language governing permissions and 23 | limitations under the License. 24 | */ 25 | 26 | 27 | `timescale 1 ns / 1 ps 28 | `include "iverilog.vh" 29 | `include "define.vh" 30 | 31 | 32 | module riftChip_TB ( 33 | 34 | ); 35 | 36 | 37 | reg CLK; 38 | reg RSTn; 39 | 40 | 41 | riftChip s_riftChip( 42 | 43 | .CLK(CLK), 44 | .RSTn(RSTn) 45 | ); 46 | 47 | 48 | 49 | initial begin 50 | 51 | 52 | CLK = 0; 53 | RSTn = 0; 54 | 55 | #20 56 | 57 | RSTn <= 1; 58 | 59 | #160000 60 | $display("Time Out !!!"); 61 | $stop; 62 | end 63 | 64 | 65 | initial begin 66 | forever 67 | begin 68 | #5 CLK <= ~CLK; 69 | end 70 | end 71 | 72 | 73 | 74 | 75 | `define SRAM s_riftChip.i_axi_full_slv_sram.i_sram 76 | 77 | 78 | `define RGF s_riftChip.i_riftCore.i_backEnd.i_phyRegister.regFileX_qout 79 | `define INDEX s_riftChip.i_riftCore.i_backEnd.i_phyRegister.archi_X_qout[`RB*3 +: `RB] 80 | 81 | 82 | 83 | 84 | localparam DP = 2**14; 85 | integer i, by; 86 | 87 | reg [7:0] mem [0:200000]; 88 | initial begin 89 | $readmemh("./ci/rv64ui-p-simple.verilog", mem); 90 | for ( i = 0; i < DP; i = i + 1 ) begin 91 | for ( by = 0; by < 8; by = by + 1 ) begin 92 | if ( | mem[i*8+by] ) begin 93 | `SRAM.ram[i][8*by +: 8] = mem[i*8+by]; 94 | end 95 | else begin 96 | `SRAM.ram[i][8*by +: 8] = 8'h0; 97 | end 98 | end 99 | 100 | // $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]); 101 | end 102 | 103 | end 104 | 105 | 106 | wire [63:0] x3 = `RGF[(3*`RP+`INDEX)*64 +: 64]; 107 | wire isEcall = s_riftChip.i_riftCore.i_backEnd.i_commit.isEcall; 108 | 109 | always @(negedge CLK)begin 110 | if (isEcall) begin 111 | if ( x3 == 64'd1 ) begin 112 | $display("PASS"); 113 | $finish; 114 | end 115 | else begin 116 | $display("Fail"); 117 | $stop; 118 | end 119 | 120 | 121 | 122 | end 123 | 124 | end 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | initial 135 | begin 136 | $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 137 | $dumpvars(0, riftChip_TB);//tb模块名称 138 | end 139 | 140 | endmodule 141 | 142 | 143 | -------------------------------------------------------------------------------- /tb/waveAna.bat: -------------------------------------------------------------------------------- 1 | @REM @Author: Ruige Lee 2 | @REM @Date: 2020-11-08 15:05:17 3 | @REM @Last Modified by: Ruige Lee 4 | @REM Modified time: 2020-11-18 19:53:22 5 | 6 | gtkwave.exe ./build/wave.vcd 7 | --------------------------------------------------------------------------------