├── LICENSE ├── PirateSWD.py ├── README ├── STM32.py ├── SWDCommon.py ├── SWDErrors.py ├── flashSTM32.py └── stm32-firmwares ├── blink ├── blink.c ├── makefile ├── stm32.cmd └── stm32f10x.h ├── blink100k.bin ├── blink1M.bin ├── blink200k.bin └── blink500k.bin /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2010, Will Donnelly 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without modification, 5 | are permitted provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | * Redistributions in binary form must reproduce the above copyright notice, this 10 | list of conditions and the following disclaimer in the documentation and/or 11 | other materials provided with the distribution. 12 | * Neither the name of the software nor the names of its contributors may be used 13 | to endorse or promote products derived from this software without specific 14 | prior written permission. 15 | 16 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 17 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 19 | CLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 20 | ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 | ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | -------------------------------------------------------------------------------- /PirateSWD.py: -------------------------------------------------------------------------------- 1 | import serial 2 | 3 | from SWDErrors import * 4 | 5 | class PirateSWD: 6 | def __init__ (self, f = "/dev/bus_pirate"): 7 | self.port = serial.Serial(port = f, baudrate = 115200, timeout = 0.01) 8 | self.resetBP() 9 | self.sendBytes([0xFF] * 8) 10 | self.sendBytes([0x79, 0xE7]) 11 | self.resyncSWD() 12 | 13 | def resetBP (self): 14 | self.expected = 9999 15 | self.clear() 16 | self.port.write(bytearray([0x0F])) 17 | while self.port.read(5) != "BBIO1": 18 | self.clear(9999) 19 | self.port.write(bytearray([0x00])) 20 | self.port.write(bytearray([0x05])) 21 | if self.port.read(4) != "RAW1": 22 | raise SWDInitError("error initializing bus pirate") 23 | self.port.write(bytearray([0x63,0x88])) 24 | self.clear(9999) 25 | 26 | # this is the fastest port-clearing scheme I could devise 27 | def clear (self, more = 0): 28 | vals = self.port.read(self.expected + more) 29 | self.expected = 0 30 | return vals[-more:] 31 | 32 | def readBits (self, count): 33 | self.port.write(bytearray([0x07] * count)) 34 | return [ord(x) for x in self.clear(count)] 35 | 36 | def skipBits (self, count): 37 | self.port.write(bytearray([0x07] * count)) 38 | self.expected = self.expected + count 39 | 40 | def readBytes (self, count): 41 | self.port.write(bytearray([0x06] * count)) 42 | return [ord(x) for x in self.clear(count)] 43 | 44 | def sendBytes (self, data): 45 | self.port.write(bytearray([0x10 + ((len(data) - 1) & 0x0F)] + data)) 46 | self.expected = self.expected + 1 + len(data) 47 | 48 | def resyncSWD (self): 49 | self.sendBytes([0xFF] * 8) 50 | self.sendBytes([0x00] * 8) 51 | 52 | def readSWD (self, ap, register): 53 | # transmit the opcode 54 | self.sendBytes([calcOpcode(ap, register, True)]) 55 | # check the response 56 | ack = self.readBits(3) 57 | if ack[0:3] != [1,0,0]: 58 | if ack[0:3] == [0,1,0]: 59 | raise SWDWaitError(ack[0:3]) 60 | elif ack[0:3] == [0,0,1]: 61 | raise SWDFaultError(ack[0:3]) 62 | else: 63 | raise SWDProtocolError(ack[0:3]) 64 | # read the next 4 bytes 65 | data = [reverseBits(b) for b in self.readBytes(4)] 66 | data.reverse() 67 | # read the parity bit and turnaround period 68 | extra = self.readBits(3) 69 | # check the parity 70 | if sum([bitCount(x) for x in data[0:4]]) % 2 != extra[0]: 71 | raise SWDParityError() 72 | # idle clocking to allow transactions to complete 73 | self.sendBytes([0x00]) 74 | # return the data 75 | return (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3] 76 | 77 | def writeSWD (self, ap, register, data, ignoreACK = False): 78 | # transmit the opcode 79 | self.sendBytes([calcOpcode(ap, register, False)]) 80 | # check the response if required 81 | if ignoreACK: 82 | self.skipBits(5) 83 | else: 84 | ack = self.readBits(5) 85 | if ack[0:3] != [1,0,0]: 86 | if ack[0:3] == [0,1,0]: 87 | raise SWDWaitError(ack[0:3]) 88 | elif ack[0:3] == [0,0,1]: 89 | raise SWDFaultError(ack[0:3]) 90 | else: 91 | raise SWDProtocolError(ack[0:3]) 92 | # mangle the data endianness 93 | payload = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00] 94 | payload[0] = reverseBits((data >> 0) & 0xFF) 95 | payload[1] = reverseBits((data >> 8) & 0xFF) 96 | payload[2] = reverseBits((data >> 16) & 0xFF) 97 | payload[3] = reverseBits((data >> 24) & 0xFF) 98 | # add the parity bit 99 | if sum([bitCount(x) for x in payload[0:4]]) % 2: 100 | payload[4] = 0x80 101 | # output the data, idle clocking is on the end of the payload 102 | self.sendBytes(payload) 103 | 104 | def bitCount(int_type): 105 | count = 0 106 | while(int_type): 107 | int_type &= int_type - 1 108 | count += 1 109 | return(count) 110 | 111 | def reverseBits (x): 112 | a = ((x & 0xAA) >> 1) | ((x & 0x55) << 1) 113 | b = ((a & 0xCC) >> 2) | ((a & 0x33) << 2) 114 | c = ((b & 0xF0) >> 4) | ((b & 0x0F) << 4) 115 | return c 116 | 117 | def calcOpcode (ap, register, read): 118 | opcode = 0x00 119 | opcode = opcode | (0x20 if read else 0x00) 120 | opcode = opcode | (0x40 if ap else 0x00) 121 | opcode = opcode | ((register & 0x01) << 4) | ((register & 0x02) << 2) 122 | opcode = opcode | ((bitCount(opcode) & 1) << 2) 123 | opcode = opcode | 0x81 124 | return opcode 125 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | Pirate-SWD 2 | ---------- 3 | 4 | This is a basic implementation of the SWD protocol using the Bus Pirate. 5 | 6 | The 'PirateSWD', 'DebugPort' and 'MEM_AP' classes should be portable to 7 | all ARM chips supporting the SWD protocol. 8 | 9 | Also included is a 'STM32' class, which encapsulates some basic operations 10 | on the STM32 microcontroller, allowing it to be halted and reset, and the 11 | flash memory programmed with a sequence of words. 12 | 13 | There are some example firmware files for the STM32VLDISCOVERY board, as 14 | I mainly developed this code so I could program mine from Linux without 15 | bothering with the embedded bootloader. 16 | -------------------------------------------------------------------------------- /STM32.py: -------------------------------------------------------------------------------- 1 | from SWDCommon import * 2 | 3 | class STM32: 4 | def __init__ (self, debugPort): 5 | self.ahb = MEM_AP(debugPort, 0) 6 | 7 | def halt (self): 8 | # halt the processor core 9 | self.ahb.writeWord(0xE000EDF0, 0xA05F0003) 10 | 11 | def unhalt (self): 12 | # unhalt the processor core 13 | self.ahb.writeWord(0xE000EDF0, 0xA05F0000) 14 | 15 | def sysReset (self): 16 | # restart the processor and peripherals 17 | self.ahb.writeWord(0xE000ED0C, 0x05FA0004) 18 | 19 | def flashUnlock (self): 20 | # unlock main flash 21 | self.ahb.writeWord(0x40022004, 0x45670123) 22 | self.ahb.writeWord(0x40022004, 0xCDEF89AB) 23 | 24 | def flashErase (self): 25 | # start the mass erase 26 | self.ahb.writeWord(0x40022010, 0x00000204) 27 | self.ahb.writeWord(0x40022010, 0x00000244) 28 | # check the BSY flag 29 | while (self.ahb.readWord(0x4002200C) & 1) == 1: 30 | print "waiting for erase completion..." 31 | time.sleep(0.01) 32 | self.ahb.writeWord(0x40022010, 0x00000200) 33 | 34 | def flashProgram (self): 35 | self.ahb.writeWord(0x40022010, 0x00000201) 36 | 37 | def flashProgramEnd (self): 38 | self.ahb.writeWord(0x40022010, 0x00000200) 39 | -------------------------------------------------------------------------------- /SWDCommon.py: -------------------------------------------------------------------------------- 1 | import time 2 | 3 | class DebugPort: 4 | def __init__ (self, swd): 5 | self.swd = swd 6 | # read the IDCODE 7 | if self.idcode() != 0x1BA01477: 8 | print "warning: unexpected idcode" 9 | # power shit up 10 | self.swd.writeSWD(False, 1, 0x54000000) 11 | if (self.status() >> 24) != 0xF4: 12 | print "error powering up system" 13 | sys.exit(1) 14 | # get the SELECT register to a known state 15 | self.select(0,0) 16 | self.curAP = 0 17 | self.curBank = 0 18 | 19 | def idcode (self): 20 | return self.swd.readSWD(False, 0) 21 | 22 | def abort (self, orunerr, wdataerr, stickyerr, stickycmp, dap): 23 | value = 0x00000000 24 | value = value | (0x10 if orunerr else 0x00) 25 | value = value | (0x08 if wdataerr else 0x00) 26 | value = value | (0x04 if stickyerr else 0x00) 27 | value = value | (0x02 if stickycmp else 0x00) 28 | value = value | (0x01 if dap else 0x00) 29 | self.swd.writeSWD(False, 0, value) 30 | 31 | def status (self): 32 | return self.swd.readSWD(False, 1) 33 | 34 | def control (self, trnCount = 0, trnMode = 0, maskLane = 0, orunDetect = 0): 35 | value = 0x54000000 36 | value = value | ((trnCount & 0xFFF) << 12) 37 | value = value | ((maskLane & 0x00F) << 8) 38 | value = value | ((trnMode & 0x003) << 2) 39 | value = value | (0x1 if orunDetect else 0x0) 40 | self.swd.writeSWD(False, 1, value) 41 | 42 | def select (self, apsel, apbank): 43 | value = 0x00000000 44 | value = value | ((apsel & 0xFF) << 24) 45 | value = value | ((apbank & 0x0F) << 4) 46 | self.swd.writeSWD(False, 2, value) 47 | 48 | def readRB (self): 49 | return self.swd.readSWD(False, 3) 50 | 51 | def readAP (self, apsel, address): 52 | adrBank = (address >> 4) & 0xF 53 | adrReg = (address >> 2) & 0x3 54 | if apsel != self.curAP or adrBank != self.curBank: 55 | self.select(apsel, adrBank) 56 | self.curAP = apsel 57 | self.curBank = adrBank 58 | return self.swd.readSWD(True, adrReg) 59 | 60 | def writeAP (self, apsel, address, data, ignore = False): 61 | adrBank = (address >> 4) & 0xF 62 | adrReg = (address >> 2) & 0x3 63 | if apsel != self.curAP or adrBank != self.curBank: 64 | self.select(apsel, adrBank) 65 | self.curAP = apsel 66 | self.curBank = adrBank 67 | self.swd.writeSWD(True, adrReg, data, ignore) 68 | 69 | class MEM_AP: 70 | def __init__ (self, dp, apsel): 71 | self.dp = dp 72 | self.apsel = apsel 73 | self.csw(1,2) # 32-bit auto-incrementing addressing 74 | 75 | def csw (self, addrInc, size): 76 | self.dp.readAP(self.apsel, 0x00) 77 | csw = self.dp.readRB() & 0xFFFFFF00 78 | self.dp.writeAP(self.apsel, 0x00, csw + (addrInc << 4) + size) 79 | 80 | def idcode (self): 81 | self.dp.readAP(self.apsel, 0xFC) 82 | return self.dp.readRB() 83 | 84 | def readWord (self, adr): 85 | self.dp.writeAP(self.apsel, 0x04, adr) 86 | self.dp.readAP(self.apsel, 0x0C) 87 | return self.dp.readRB() 88 | 89 | def writeWord (self, adr, data): 90 | self.dp.writeAP(self.apsel, 0x04, adr) 91 | self.dp.writeAP(self.apsel, 0x0C, data) 92 | return self.dp.readRB() 93 | 94 | def readBlock (self, adr, count): 95 | self.dp.writeAP(self.apsel, 0x04, adr) 96 | vals = [self.dp.readAP(self.apsel, 0x0C) for off in range(count)] 97 | vals.append(self.dp.readRB()) 98 | return vals[1:] 99 | 100 | def writeBlock (self, adr, data): 101 | self.dp.writeAP(self.apsel, 0x04, adr) 102 | for val in data: 103 | self.dp.writeAP(self.apsel, 0x0C, val) 104 | 105 | def writeHalfs (self, adr, data): 106 | self.csw(2, 1) # 16-bit packed-incrementing addressing 107 | self.dp.writeAP(self.apsel, 0x04, adr) 108 | for val in data: 109 | time.sleep(0.001) 110 | self.dp.writeAP(self.apsel, 0x0C, val, ignore = True) 111 | self.csw(1, 2) # 32-bit auto-incrementing addressing 112 | -------------------------------------------------------------------------------- /SWDErrors.py: -------------------------------------------------------------------------------- 1 | class SWDInitError(Exception): 2 | "There was an error initializing SWD communications" 3 | pass 4 | class SWDProtocolError(Exception): 5 | "The target responded with an invalid ACK" 6 | pass 7 | class SWDFaultError(Exception): 8 | "The target responded with a 'fault' ACK" 9 | pass 10 | class SWDWaitError(Exception): 11 | "The target responded with a 'wait' ACK" 12 | pass 13 | class SWDParityError(Exception): 14 | "The target sent data with incorrect parity" 15 | pass 16 | -------------------------------------------------------------------------------- /flashSTM32.py: -------------------------------------------------------------------------------- 1 | import time 2 | import sys 3 | import array 4 | 5 | from PirateSWD import * 6 | from SWDCommon import * 7 | from STM32 import * 8 | 9 | def loadFile(path): 10 | arr = array.array('L') 11 | try: 12 | arr.fromfile(open(sys.argv[1], 'rb'), 1024*1024) 13 | except EOFError: 14 | pass 15 | return arr.tolist() 16 | 17 | def main(): 18 | busPirate = PirateSWD("/dev/ttyUSB0") 19 | debugPort = DebugPort(busPirate) 20 | stm32 = STM32(debugPort) 21 | 22 | print "DP.IDCODE: %08X" % debugPort.idcode() 23 | print "AP.IDCODE: %08X" % stm32.ahb.idcode() 24 | print "" 25 | print "Loading File: '%s'" % sys.argv[1] 26 | vals = loadFile(sys.argv[1]) 27 | 28 | print "Halting Processor" 29 | stm32.halt() 30 | print "Erasing Flash" 31 | stm32.flashUnlock() 32 | stm32.flashErase() 33 | print "Programming Flash" 34 | stm32.flashProgram() 35 | stm32.ahb.writeHalfs(0x08000000, vals) 36 | stm32.flashProgramEnd() 37 | print "Resetting" 38 | stm32.sysReset() 39 | 40 | if __name__ == "__main__": 41 | main() 42 | -------------------------------------------------------------------------------- /stm32-firmwares/blink/blink.c: -------------------------------------------------------------------------------- 1 | #define STACK_TOP 0x20002000 2 | #include "stm32f10x.h" 3 | 4 | #define DELAY_COUNT 1000000 5 | 6 | int main(void){ 7 | RCC->APB2ENR |= 0x14; 8 | GPIOC->CRH = 0x11; 9 | 10 | while(1) { 11 | GPIOC->BRR |= 1<<8; 12 | delay(DELAY_COUNT); 13 | GPIOC->BSRR |= 1<<8; 14 | delay(DELAY_COUNT); 15 | } 16 | } 17 | 18 | void delay (unsigned int ii) { 19 | unsigned int jj; 20 | for(jj = ii; jj > 0; jj--) 21 | asm("nop"); 22 | } 23 | 24 | /* do nothing functions */ 25 | int assert_param (void *v) { return 0; } 26 | void handle_nmi (void) { return; } 27 | void handle_hardfault (void) { return; } 28 | 29 | /* vector table */ 30 | unsigned int *myvectors[4] __attribute__ ((section("vectors")))= { 31 | (unsigned int *) STACK_TOP, // stack pointer 32 | (unsigned int *) main, // code entry point 33 | (unsigned int *) handle_nmi, // handle non-maskable interrupts 34 | (unsigned int *) handle_hardfault // handle hard faults 35 | }; 36 | -------------------------------------------------------------------------------- /stm32-firmwares/blink/makefile: -------------------------------------------------------------------------------- 1 | .SUFFIXES: .c .o .h 2 | .PHONY: clean 3 | 4 | CHIP = STM32F10X_LD_VL 5 | NAME = blink 6 | FILES = blink.c 7 | 8 | CC = arm-none-eabi-gcc 9 | LD = arm-none-eabi-ld 10 | OBJCP = arm-none-eabi-objcopy 11 | STRIP = arm-none-eabi-strip 12 | CFLAGS = -I./ -fno-common -Os -mcpu=cortex-m3 -mthumb 13 | LDFLAGS = -nostartfiles 14 | 15 | OBJECTS = $(FILES:.c=.o) 16 | 17 | all: $(NAME) 18 | 19 | $(NAME): $(OBJECTS) stm32.cmd 20 | $(LD) -Tstm32.cmd $(LFLAGS) -o $(NAME).out $(OBJECTS) 21 | $(OBJCP) -Obinary $(NAME).out $(NAME).bin 22 | 23 | .c.o: 24 | $(CC) -c $(CFLAGS) -D$(CHIP) -o $@ $< 25 | 26 | clean: 27 | -rm -f $(OBJECTS) $(NAME).{out,bin} 28 | -------------------------------------------------------------------------------- /stm32-firmwares/blink/stm32.cmd: -------------------------------------------------------------------------------- 1 | /* Linker script for lm3s6730 2 | * 3 | * Version:Sourcery G++ 4.2-62 4 | * BugURL:https://support.codesourcery.com/GNUToolchain/ 5 | * 6 | * Copyright 2007 CodeSourcery. 7 | * 8 | * The authors hereby grant permission to use, copy, modify, distribute, 9 | * and license this software and its documentation for any purpose, provided 10 | * that existing copyright notices are retained in all copies and that this 11 | * notice is included verbatim in any distributions. No written agreement, 12 | * license, or royalty fee is required for any of the authorized uses. 13 | * Modifications to this software may be copyrighted by their authors 14 | * and need not follow the licensing terms described here, provided that 15 | * the new terms are clearly indicated on the first page of each file where 16 | * they apply. */ 17 | /* 18 | OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") 19 | ENTRY(_start) 20 | SEARCH_DIR(.)*/ 21 | /*GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3stellaris) here*/ 22 | 23 | MEMORY 24 | { 25 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K 26 | rom (rx) : ORIGIN = 0x00000000, LENGTH = 128K 27 | } 28 | SECTIONS 29 | { 30 | . = 0x0; /* From 0x00000000 */ 31 | .text : { 32 | *(vectors) /* Vector table */ 33 | *(.text) /* Program code */ 34 | *(.rodata) /* Read only data */ 35 | } >rom 36 | . = 0x20000000; /* From 0x20000000 */ 37 | .data : { 38 | *(.data) /* Data memory */ 39 | } >ram AT > rom 40 | .bss : { 41 | *(.bss) /* Zero-filled run time allocate data memory */ 42 | } >ram AT > rom 43 | } 44 | /*========== end of file ==========*/ 45 | -------------------------------------------------------------------------------- /stm32-firmwares/blink/stm32f10x.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * File Name : stm32f10x.h 4 | * Author : MCD Application Team, Paul Robson 5 | * Version : V2.0 6 | * Date : 20/09/2010 7 | * Description : Includes as needed for STM32VLDISCOVERY coding. 8 | * Built from _type.h and _map.h and simplified. 9 | * Original Copyright : (c) 2007 ST Microelectronics 10 | * 11 | ******************************************************************************** 12 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 14 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 15 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 16 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 17 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | *******************************************************************************/ 19 | 20 | #ifndef __STM32F10x_H 21 | #define __STM32F10x_H 22 | 23 | /******************************************************************************/ 24 | /* Data Types Needed */ 25 | /******************************************************************************/ 26 | 27 | typedef signed long s32; 28 | typedef signed short s16; 29 | typedef signed char s8; 30 | 31 | typedef signed long const sc32; /* Read Only */ 32 | typedef signed short const sc16; /* Read Only */ 33 | typedef signed char const sc8; /* Read Only */ 34 | 35 | typedef volatile signed long vs32; 36 | typedef volatile signed short vs16; 37 | typedef volatile signed char vs8; 38 | 39 | typedef volatile signed long const vsc32; /* Read Only */ 40 | typedef volatile signed short const vsc16; /* Read Only */ 41 | typedef volatile signed char const vsc8; /* Read Only */ 42 | 43 | typedef unsigned long u32; 44 | typedef unsigned short u16; 45 | typedef unsigned char u8; 46 | 47 | typedef unsigned long const uc32; /* Read Only */ 48 | typedef unsigned short const uc16; /* Read Only */ 49 | typedef unsigned char const uc8; /* Read Only */ 50 | 51 | typedef volatile unsigned long vu32; 52 | typedef volatile unsigned short vu16; 53 | typedef volatile unsigned char vu8; 54 | 55 | typedef volatile unsigned long const vuc32; /* Read Only */ 56 | typedef volatile unsigned short const vuc16; /* Read Only */ 57 | typedef volatile unsigned char const vuc8; /* Read Only */ 58 | 59 | /******************************************************************************/ 60 | /* Peripheral registers structures */ 61 | /******************************************************************************/ 62 | 63 | /*------------------------ Analog to Digital Converter -----------------------*/ 64 | typedef struct 65 | { 66 | vu32 SR; 67 | vu32 CR1; 68 | vu32 CR2; 69 | vu32 SMPR1; 70 | vu32 SMPR2; 71 | vu32 JOFR1; 72 | vu32 JOFR2; 73 | vu32 JOFR3; 74 | vu32 JOFR4; 75 | vu32 HTR; 76 | vu32 LTR; 77 | vu32 SQR1; 78 | vu32 SQR2; 79 | vu32 SQR3; 80 | vu32 JSQR; 81 | vu32 JDR1; 82 | vu32 JDR2; 83 | vu32 JDR3; 84 | vu32 JDR4; 85 | vu32 DR; 86 | } ADC_TypeDef; 87 | 88 | /*------------------------ Backup Registers ----------------------------------*/ 89 | typedef struct 90 | { 91 | u32 RESERVED0; 92 | vu16 DR1; 93 | u16 RESERVED1; 94 | vu16 DR2; 95 | u16 RESERVED2; 96 | vu16 DR3; 97 | u16 RESERVED3; 98 | vu16 DR4; 99 | u16 RESERVED4; 100 | vu16 DR5; 101 | u16 RESERVED5; 102 | vu16 DR6; 103 | u16 RESERVED6; 104 | vu16 DR7; 105 | u16 RESERVED7; 106 | vu16 DR8; 107 | u16 RESERVED8; 108 | vu16 DR9; 109 | u16 RESERVED9; 110 | vu16 DR10; 111 | u16 RESERVED10; 112 | vu16 RTCCR; 113 | u16 RESERVED11; 114 | vu16 CR; 115 | u16 RESERVED12; 116 | vu16 CSR; 117 | u16 RESERVED13; 118 | } BKP_TypeDef; 119 | 120 | /*------------------------ Controller Area Network ---------------------------*/ 121 | typedef struct 122 | { 123 | vu32 TIR; 124 | vu32 TDTR; 125 | vu32 TDLR; 126 | vu32 TDHR; 127 | } CAN_TxMailBox_TypeDef; 128 | 129 | typedef struct 130 | { 131 | vu32 RIR; 132 | vu32 RDTR; 133 | vu32 RDLR; 134 | vu32 RDHR; 135 | } CAN_FIFOMailBox_TypeDef; 136 | 137 | typedef struct 138 | { 139 | vu32 FR0; 140 | vu32 FR1; 141 | } CAN_FilterRegister_TypeDef; 142 | 143 | typedef struct 144 | { 145 | vu32 MCR; 146 | vu32 MSR; 147 | vu32 TSR; 148 | vu32 RF0R; 149 | vu32 RF1R; 150 | vu32 IER; 151 | vu32 ESR; 152 | vu32 BTR; 153 | u32 RESERVED0[88]; 154 | CAN_TxMailBox_TypeDef sTxMailBox[3]; 155 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; 156 | u32 RESERVED1[12]; 157 | vu32 FMR; 158 | vu32 FM0R; 159 | u32 RESERVED2[1]; 160 | vu32 FS0R; 161 | u32 RESERVED3[1]; 162 | vu32 FFA0R; 163 | u32 RESERVED4[1]; 164 | vu32 FA0R; 165 | u32 RESERVED5[8]; 166 | CAN_FilterRegister_TypeDef sFilterRegister[14]; 167 | } CAN_TypeDef; 168 | 169 | /*------------------------ DMA Controller ------------------------------------*/ 170 | typedef struct 171 | { 172 | vu32 CCR; 173 | vu32 CNDTR; 174 | vu32 CPAR; 175 | vu32 CMAR; 176 | } DMA_Channel_TypeDef; 177 | 178 | typedef struct 179 | { 180 | vu32 ISR; 181 | vu32 IFCR; 182 | } DMA_TypeDef; 183 | 184 | /*------------------------ External Interrupt/Event Controller ---------------*/ 185 | typedef struct 186 | { 187 | vu32 IMR; 188 | vu32 EMR; 189 | vu32 RTSR; 190 | vu32 FTSR; 191 | vu32 SWIER; 192 | vu32 PR; 193 | } EXTI_TypeDef; 194 | 195 | /*------------------------ FLASH and Option Bytes Registers ------------------*/ 196 | typedef struct 197 | { 198 | vu32 ACR; 199 | vu32 KEYR; 200 | vu32 OPTKEYR; 201 | vu32 SR; 202 | vu32 CR; 203 | vu32 AR; 204 | vu32 RESERVED; 205 | vu32 OBR; 206 | vu32 WRPR; 207 | } FLASH_TypeDef; 208 | 209 | typedef struct 210 | { 211 | vu16 RDP; 212 | vu16 USER; 213 | vu16 Data0; 214 | vu16 Data1; 215 | vu16 WRP0; 216 | vu16 WRP1; 217 | vu16 WRP2; 218 | vu16 WRP3; 219 | } OB_TypeDef; 220 | 221 | /*------------------------ General Purpose and Alternate Function IO ---------*/ 222 | typedef struct 223 | { 224 | vu32 CRL; 225 | vu32 CRH; 226 | vu32 IDR; 227 | vu32 ODR; 228 | vu32 BSRR; 229 | vu32 BRR; 230 | vu32 LCKR; 231 | } GPIO_TypeDef; 232 | 233 | typedef struct 234 | { 235 | vu32 EVCR; 236 | vu32 MAPR; 237 | vu32 EXTICR[4]; 238 | } AFIO_TypeDef; 239 | 240 | /*------------------------ Inter-integrated Circuit Interface ----------------*/ 241 | typedef struct 242 | { 243 | vu16 CR1; 244 | u16 RESERVED0; 245 | vu16 CR2; 246 | u16 RESERVED1; 247 | vu16 OAR1; 248 | u16 RESERVED2; 249 | vu16 OAR2; 250 | u16 RESERVED3; 251 | vu16 DR; 252 | u16 RESERVED4; 253 | vu16 SR1; 254 | u16 RESERVED5; 255 | vu16 SR2; 256 | u16 RESERVED6; 257 | vu16 CCR; 258 | u16 RESERVED7; 259 | vu16 TRISE; 260 | u16 RESERVED8; 261 | } I2C_TypeDef; 262 | 263 | /*------------------------ Independent WATCHDOG ------------------------------*/ 264 | typedef struct 265 | { 266 | vu32 KR; 267 | vu32 PR; 268 | vu32 RLR; 269 | vu32 SR; 270 | } IWDG_TypeDef; 271 | 272 | /*------------------------ Nested Vectored Interrupt Controller --------------*/ 273 | typedef struct 274 | { 275 | vu32 ISER[2]; 276 | u32 RESERVED0[30]; 277 | vu32 ICER[2]; 278 | u32 RSERVED1[30]; 279 | vu32 ISPR[2]; 280 | u32 RESERVED2[30]; 281 | vu32 ICPR[2]; 282 | u32 RESERVED3[30]; 283 | vu32 IABR[2]; 284 | u32 RESERVED4[62]; 285 | vu32 IPR[11]; 286 | } NVIC_TypeDef; 287 | 288 | typedef struct 289 | { 290 | vuc32 CPUID; 291 | vu32 ICSR; 292 | vu32 VTOR; 293 | vu32 AIRCR; 294 | vu32 SCR; 295 | vu32 CCR; 296 | vu32 SHPR[3]; 297 | vu32 SHCSR; 298 | vu32 CFSR; 299 | vu32 HFSR; 300 | vu32 DFSR; 301 | vu32 MMFAR; 302 | vu32 BFAR; 303 | vu32 AFSR; 304 | } SCB_TypeDef; 305 | 306 | /*------------------------ Power Control -------------------------------------*/ 307 | typedef struct 308 | { 309 | vu32 CR; 310 | vu32 CSR; 311 | } PWR_TypeDef; 312 | 313 | /*------------------------ Reset and Clock Control ---------------------------*/ 314 | typedef struct 315 | { 316 | vu32 CR; 317 | vu32 CFGR; 318 | vu32 CIR; 319 | vu32 APB2RSTR; 320 | vu32 APB1RSTR; 321 | vu32 AHBENR; 322 | vu32 APB2ENR; 323 | vu32 APB1ENR; 324 | vu32 BDCR; 325 | vu32 CSR; 326 | } RCC_TypeDef; 327 | 328 | /*------------------------ Real-Time Clock -----------------------------------*/ 329 | typedef struct 330 | { 331 | vu16 CRH; 332 | u16 RESERVED0; 333 | vu16 CRL; 334 | u16 RESERVED1; 335 | vu16 PRLH; 336 | u16 RESERVED2; 337 | vu16 PRLL; 338 | u16 RESERVED3; 339 | vu16 DIVH; 340 | u16 RESERVED4; 341 | vu16 DIVL; 342 | u16 RESERVED5; 343 | vu16 CNTH; 344 | u16 RESERVED6; 345 | vu16 CNTL; 346 | u16 RESERVED7; 347 | vu16 ALRH; 348 | u16 RESERVED8; 349 | vu16 ALRL; 350 | u16 RESERVED9; 351 | } RTC_TypeDef; 352 | 353 | /*------------------------ Serial Peripheral Interface -----------------------*/ 354 | typedef struct 355 | { 356 | vu16 CR1; 357 | u16 RESERVED0; 358 | vu16 CR2; 359 | u16 RESERVED1; 360 | vu16 SR; 361 | u16 RESERVED2; 362 | vu16 DR; 363 | u16 RESERVED3; 364 | vu16 CRCPR; 365 | u16 RESERVED4; 366 | vu16 RXCRCR; 367 | u16 RESERVED5; 368 | vu16 TXCRCR; 369 | u16 RESERVED6; 370 | } SPI_TypeDef; 371 | 372 | /*------------------------ SystemTick ----------------------------------------*/ 373 | typedef struct 374 | { 375 | vu32 CTRL; 376 | vu32 LOAD; 377 | vu32 VAL; 378 | vuc32 CALIB; 379 | } SysTick_TypeDef; 380 | 381 | /*------------------------ Advanced Control Timer ----------------------------*/ 382 | typedef struct 383 | { 384 | vu16 CR1; 385 | u16 RESERVED0; 386 | vu16 CR2; 387 | u16 RESERVED1; 388 | vu16 SMCR; 389 | u16 RESERVED2; 390 | vu16 DIER; 391 | u16 RESERVED3; 392 | vu16 SR; 393 | u16 RESERVED4; 394 | vu16 EGR; 395 | u16 RESERVED5; 396 | vu16 CCMR1; 397 | u16 RESERVED6; 398 | vu16 CCMR2; 399 | u16 RESERVED7; 400 | vu16 CCER; 401 | u16 RESERVED8; 402 | vu16 CNT; 403 | u16 RESERVED9; 404 | vu16 PSC; 405 | u16 RESERVED10; 406 | vu16 ARR; 407 | u16 RESERVED11; 408 | vu16 RCR; 409 | u16 RESERVED12; 410 | vu16 CCR1; 411 | u16 RESERVED13; 412 | vu16 CCR2; 413 | u16 RESERVED14; 414 | vu16 CCR3; 415 | u16 RESERVED15; 416 | vu16 CCR4; 417 | u16 RESERVED16; 418 | vu16 BDTR; 419 | u16 RESERVED17; 420 | vu16 DCR; 421 | u16 RESERVED18; 422 | vu16 DMAR; 423 | u16 RESERVED19; 424 | } TIM1_TypeDef; 425 | 426 | /*------------------------ General Purpose Timer -----------------------------*/ 427 | typedef struct 428 | { 429 | vu16 CR1; 430 | u16 RESERVED0; 431 | vu16 CR2; 432 | u16 RESERVED1; 433 | vu16 SMCR; 434 | u16 RESERVED2; 435 | vu16 DIER; 436 | u16 RESERVED3; 437 | vu16 SR; 438 | u16 RESERVED4; 439 | vu16 EGR; 440 | u16 RESERVED5; 441 | vu16 CCMR1; 442 | u16 RESERVED6; 443 | vu16 CCMR2; 444 | u16 RESERVED7; 445 | vu16 CCER; 446 | u16 RESERVED8; 447 | vu16 CNT; 448 | u16 RESERVED9; 449 | vu16 PSC; 450 | u16 RESERVED10; 451 | vu16 ARR; 452 | u16 RESERVED11[3]; 453 | vu16 CCR1; 454 | u16 RESERVED12; 455 | vu16 CCR2; 456 | u16 RESERVED13; 457 | vu16 CCR3; 458 | u16 RESERVED14; 459 | vu16 CCR4; 460 | u16 RESERVED15[3]; 461 | vu16 DCR; 462 | u16 RESERVED16; 463 | vu16 DMAR; 464 | u16 RESERVED17; 465 | } TIM_TypeDef; 466 | 467 | /*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ 468 | typedef struct 469 | { 470 | vu16 SR; 471 | u16 RESERVED0; 472 | vu16 DR; 473 | u16 RESERVED1; 474 | vu16 BRR; 475 | u16 RESERVED2; 476 | vu16 CR1; 477 | u16 RESERVED3; 478 | vu16 CR2; 479 | u16 RESERVED4; 480 | vu16 CR3; 481 | u16 RESERVED5; 482 | vu16 GTPR; 483 | u16 RESERVED6; 484 | } USART_TypeDef; 485 | 486 | /*------------------------ Window WATCHDOG -----------------------------------*/ 487 | typedef struct 488 | { 489 | vu32 CR; 490 | vu32 CFR; 491 | vu32 SR; 492 | } WWDG_TypeDef; 493 | 494 | 495 | /******************************************************************************/ 496 | /* Peripheral memory map */ 497 | /******************************************************************************/ 498 | /* Peripheral and SRAM base address in the alias region */ 499 | #define PERIPH_BB_BASE ((u32)0x42000000) 500 | #define SRAM_BB_BASE ((u32)0x22000000) 501 | 502 | /* Peripheral and SRAM base address in the bit-band region */ 503 | #define SRAM_BASE ((u32)0x20000000) 504 | #define PERIPH_BASE ((u32)0x40000000) 505 | 506 | /* Flash refisters base address */ 507 | #define FLASH_BASE ((u32)0x40022000) 508 | /* Flash Option Bytes base address */ 509 | #define OB_BASE ((u32)0x1FFFF800) 510 | 511 | /* Peripheral memory map */ 512 | #define APB1PERIPH_BASE PERIPH_BASE 513 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) 514 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) 515 | 516 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 517 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 518 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 519 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 520 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 521 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 522 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 523 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 524 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 525 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 526 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 527 | #define CAN_BASE (APB1PERIPH_BASE + 0x6400) 528 | #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) 529 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 530 | 531 | #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) 532 | #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) 533 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) 534 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) 535 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) 536 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) 537 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) 538 | #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) 539 | #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) 540 | #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) 541 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 542 | #define USART1_BASE (APB2PERIPH_BASE + 0x3800) 543 | 544 | #define DMA_BASE (AHBPERIPH_BASE + 0x0000) 545 | #define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008) 546 | #define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C) 547 | #define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030) 548 | #define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044) 549 | #define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058) 550 | #define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C) 551 | #define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080) 552 | #define RCC_BASE (AHBPERIPH_BASE + 0x1000) 553 | 554 | /* System Control Space memory map */ 555 | #define SCS_BASE ((u32)0xE000E000) 556 | 557 | #define SysTick_BASE (SCS_BASE + 0x0010) 558 | #define NVIC_BASE (SCS_BASE + 0x0100) 559 | #define SCB_BASE (SCS_BASE + 0x0D00) 560 | 561 | 562 | /******************************************************************************/ 563 | /* Peripheral declaration */ 564 | /******************************************************************************/ 565 | 566 | #define TIM1 ((TIM1_TypeDef *) TIM1_BASE) 567 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 568 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 569 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 570 | 571 | #define RTC ((RTC_TypeDef *) RTC_BASE) 572 | 573 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 574 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 575 | 576 | #define USART2 ((USART_TypeDef *) USART2_BASE) 577 | #define USART3 ((USART_TypeDef *) USART3_BASE) 578 | 579 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 580 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 581 | 582 | #define CAN ((CAN_TypeDef *) CAN_BASE) 583 | 584 | #define BKP ((BKP_TypeDef *) BKP_BASE) 585 | 586 | #define PWR ((PWR_TypeDef *) PWR_BASE) 587 | 588 | #define AFIO ((AFIO_TypeDef *) AFIO_BASE) 589 | 590 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 591 | 592 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 593 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 594 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 595 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 596 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 597 | 598 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 599 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 600 | 601 | 602 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 603 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 604 | 605 | #define USART1 ((USART_TypeDef *) USART1_BASE) 606 | 607 | #define DMA ((DMA_TypeDef *) DMA_BASE) 608 | #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE) 609 | #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE) 610 | #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE) 611 | #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE) 612 | #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE) 613 | #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE) 614 | #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE) 615 | 616 | #define FLASH ((FLASH_TypeDef *) FLASH_BASE) 617 | #define OB ((OB_TypeDef *) OB_BASE) 618 | 619 | #define RCC ((RCC_TypeDef *) RCC_BASE) 620 | 621 | #define SysTick ((SysTick_TypeDef *) SysTick_BASE) 622 | 623 | #define NVIC ((NVIC_TypeDef *) NVIC_BASE) 624 | #define SCB ((SCB_TypeDef *) SCB_BASE) 625 | 626 | #endif 627 | -------------------------------------------------------------------------------- /stm32-firmwares/blink100k.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/willdonnelly/pirate-swd/3b13dfaae80cc6ce7c4fa40531e48839f86ab2c1/stm32-firmwares/blink100k.bin -------------------------------------------------------------------------------- /stm32-firmwares/blink1M.bin: -------------------------------------------------------------------------------- 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