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-------------------------------------------------------------------------------- 1 | .PHONY: all 2 | 3 | all: 4 | arm-linux-gnueabi-gcc gpio.c -o gpio 5 | 6 | clean: 7 | -rm gpio 8 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # f1c100s-gpio-tools 2 | Command-line access to F1C100s GPIO 3 | ``` 4 | root@f1c100s:~#gpio 5 | usage: gpio help 6 | gpio read [PA0|PA1...] 7 | gpio write [PA0|PA1...] 8 | gpio mode [PA0|PA1...] [in|out|...] 9 | gpio readall 10 | gpio dumpall 11 | gpio info 12 | -- github.com/wuxx/f1c100s-gpio-tools -- 13 | 14 | root@f1c100s:~#gpio read PA0 15 | PA0: 1 16 | 17 | root@f1c100s:~#gpio write PA0 0 18 | root@f1c100s:~#gpio read PA0 19 | PA0: 0 20 | root@f1c100s:~#gpio mode PA0 in 21 | 22 | root@f1c100s:~#gpio readall 23 | value mode 24 | PA: 25 | PA0: 0 [in] 26 | PA1: 0 [disabled] 27 | PA2: 0 [out] 28 | PA3: 1 [out] 29 | PB: 30 | PB3: 0 [disabled] 31 | PC: 32 | PC0: 0 [spi0_clk] 33 | PC1: 0 [spi0_cs] 34 | PC2: 0 [spi0_miso] 35 | PC3: 0 [spi0_mosi] 36 | PD: 37 | PD0: 0 [lcd_d2] 38 | PD1: 0 [lcd_d3] 39 | PD2: 0 [lcd_d4] 40 | PD3: 0 [lcd_d5] 41 | PD4: 0 [lcd_d6] 42 | PD5: 0 [lcd_d7] 43 | PD6: 0 [lcd_d10] 44 | PD7: 0 [lcd_d11] 45 | PD8: 0 [lcd_d12] 46 | PD9: 0 [lcd_d13] 47 | PD10: 0 [lcd_d14] 48 | PD11: 0 [lcd_d15] 49 | PD12: 0 [lcd_d18] 50 | PD13: 0 [lcd_d19] 51 | PD14: 0 [lcd_d20] 52 | PD15: 0 [lcd_d21] 53 | PD16: 0 [lcd_d22] 54 | PD17: 0 [lcd_d23] 55 | PD18: 0 [lcd_clk] 56 | PD19: 0 [lcd_de] 57 | PD20: 0 [lcd_hsync] 58 | PD21: 0 [lcd_vsync] 59 | PE: 60 | PE0: 0 [uart0_rx] 61 | PE1: 0 [uart0_tx] 62 | PE2: 0 [out] 63 | PE3: 1 [out] 64 | PE4: 1 [out] 65 | PE5: 1 [in] 66 | PE6: 1 [out] 67 | PE7: 0 [disabled] 68 | PE8: 0 [disabled] 69 | PE9: 0 [disabled] 70 | PE10: 1 [out] 71 | PE11: 0 [twi0_sck] 72 | PE12: 0 [twi0_sda] 73 | PF: 74 | PF0: 0 [sdc0_d1] 75 | PF1: 0 [sdc0_d0] 76 | PF2: 0 [sdc0_clk] 77 | PF3: 0 [sdc0_cmd] 78 | PF4: 0 [sdc0_d3] 79 | PF5: 0 [sdc0_d2] 80 | 81 | root@f1c100s:~#gpio info 82 | PA0: (in out tp_x1 reserved da_bclk uart1_rts spi1_cs disabled ) 83 | PA1: (in out tp_x2 reserved da_lrck uart1_cts spi1_miso disabled ) 84 | PA2: (in out tp_y1 pwm0 da_in uart1_rx spi1_clk disabled ) 85 | PA3: (in out tp_y2 ir_rx da_out uart1_tx spi1_miso disabled ) 86 | PB3: (in out ddr_ref_d ir_rx reserved reserved reserved disabled ) 87 | PC0: (reserved out spi0_clk sdc1_clk reserved reserved reserved disabled ) 88 | PC1: (in out spi0_cs sdc1_cmd reserved reserved reserved disabled ) 89 | PC2: (in out spi0_miso sdc1_d0 reserved reserved reserved disabled ) 90 | PC3: (in out spi0_mosi uart0_tx reserved reserved reserved disabled ) 91 | PD0: (in out lcd_d2 twi0_sda rsb_sda reserved eintd0 disabled ) 92 | PD1: (in out lcd_d3 uart1_rts reserved reserved eintd1 disabled ) 93 | PD2: (in out lcd_d4 uart1_cts reserved reserved eintd2 disabled ) 94 | PD3: (in out lcd_d5 uart1_rx reserved reserved eintd3 disabled ) 95 | PD4: (in out lcd_d6 uart1_tx reserved reserved eintd4 disabled ) 96 | PD5: (in out lcd_d7 twi1_sck reserved reserved eintd5 disabled ) 97 | PD6: (in out lcd_d10 twi1_sda reserved reserved eintd6 disabled ) 98 | PD7: (in out lcd_d11 da_mclk reserved reserved eintd7 disabled ) 99 | PD8: (in out lcd_d12 da_bclk reserved reserved eintd8 disabled ) 100 | PD9: (in out lcd_d13 da_lrck reserved reserved eintd9 disabled ) 101 | PD10: (in out lcd_d14 da_in reserved reserved eintd10 disabled ) 102 | PD11: (in out lcd_d15 da_out reserved reserved eintd11 disabled ) 103 | PD12: (in out lcd_d18 twi0_sck rsb_sck reserved eintd12 disabled ) 104 | PD13: (in out lcd_d19 uart2_tx rsb_sck reserved eintd13 disabled ) 105 | PD14: (in out lcd_d20 uart2_rx reserved reserved eintd14 disabled ) 106 | PD15: (in out lcd_d21 uart2_rts twi2_sck reserved eintd15 disabled ) 107 | PD16: (in out lcd_d22 uart2_cts twi2_sda reserved eintd16 disabled ) 108 | PD17: (in out lcd_d23 owa_out reserved reserved eintd17 disabled ) 109 | PD18: (in out lcd_clk spi0_cs reserved reserved eintd18 disabled ) 110 | PD19: (in out lcd_de spi0_mosi reserved reserved eintd19 disabled ) 111 | PD20: (in out lcd_hsync spi0_clk reserved reserved eintd20 disabled ) 112 | PD21: (in out lcd_vsync spi0_miso reserved reserved eintd21 disabled ) 113 | PE0: (in out csi_hsync lcd_d0 twi2_sck uart0_rx einte0 disabled ) 114 | PE1: (in out csi_vsync lcd_d1 twi2_sda uart0_tx einte1 disabled ) 115 | PE2: (in out csi_pclk lcd_d8 clk_out reserved einte2 disabled ) 116 | PE3: (in out csi_d0 lcd_d9 da_bclk rsb_sck einte3 disabled ) 117 | PE4: (in out csi_d1 lcd_d16 da_lrck rsb_sda einte4 disabled ) 118 | PE5: (in out csi_d2 lcd_d17 da_in reserved einte5 disabled ) 119 | PE6: (in out csi_d3 pwm1 da_out owa_out einte6 disabled ) 120 | PE7: (in out csi_d4 uart2_tx spi1_cs reserved einte7 disabled ) 121 | PE8: (in out csi_d5 uart2_rx spi1_mosi reserved einte8 disabled ) 122 | PE9: (in out csi_d6 uart2_rts spi1_clk reserved einte9 disabled ) 123 | PE10: (in out csi_d7 uart2_cts spi1_miso reserved einte10 disabled ) 124 | PE11: (in out clk_out twi0_sck ir_rx reserved einte11 disabled ) 125 | PE12: (in out da_mclk twi0_sda pwm0 reserved einte12 disabled ) 126 | PF0: (in out sdc0_d1 dbg_ms ir_rx reserved eintf0 disabled ) 127 | PF1: (in out sdc0_d0 dbg_di reserved reserved eintf1 disabled ) 128 | PF2: (in out sdc0_clk uart0_tx reserved reserved eintf2 disabled ) 129 | PF3: (in out sdc0_cmd dbg_do reserved reserved eintf3 disabled ) 130 | PF4: (in out sdc0_d3 uart0_tx reserved reserved eintf4 disabled ) 131 | PF5: (in out sdc0_d2 dbg_ck pwm1 reserved eintf5 disabled ) 132 | 133 | root@f1c100s:~#gpio dumpall 134 | PA: 135 | GPIO_CFG0: 0x00001170 136 | GPIO_CFG1: 0x00000000 137 | GPIO_CFG2: 0x00000000 138 | GPIO_CFG3: 0x00000000 139 | GPIO_DATA: 0x00000008 140 | GPIO_DRV0: 0x00000055 141 | GPIO_DRV1: 0x00000000 142 | GPIO_PUL0: 0x00000000 143 | GPIO_PUL1: 0x00000000 144 | PB: 145 | GPIO_CFG0: 0x00007222 146 | GPIO_CFG1: 0x00000000 147 | GPIO_CFG2: 0x00000000 148 | GPIO_CFG3: 0x00000000 149 | GPIO_DATA: 0x00000000 150 | GPIO_DRV0: 0x00000055 151 | GPIO_DRV1: 0x00000000 152 | GPIO_PUL0: 0x00000000 153 | GPIO_PUL1: 0x00000000 154 | PC: 155 | GPIO_CFG0: 0x00002222 156 | GPIO_CFG1: 0x00000000 157 | GPIO_CFG2: 0x00000000 158 | GPIO_CFG3: 0x00000000 159 | GPIO_DATA: 0x00000000 160 | GPIO_DRV0: 0x00000000 161 | GPIO_DRV1: 0x00000000 162 | GPIO_PUL0: 0x00000000 163 | GPIO_PUL1: 0x00000000 164 | PD: 165 | GPIO_CFG0: 0x22222222 166 | GPIO_CFG1: 0x22222222 167 | GPIO_CFG2: 0x00222222 168 | GPIO_CFG3: 0x00000000 169 | GPIO_DATA: 0x00000000 170 | GPIO_DRV0: 0x55555555 171 | GPIO_DRV1: 0x00000555 172 | GPIO_PUL0: 0x00000000 173 | GPIO_PUL1: 0x00000000 174 | PE: 175 | GPIO_CFG0: 0x71011155 176 | GPIO_CFG1: 0x00033177 177 | GPIO_CFG2: 0x00000000 178 | GPIO_CFG3: 0x00000000 179 | GPIO_DATA: 0x00000478 180 | GPIO_DRV0: 0x01555555 181 | GPIO_DRV1: 0x00000000 182 | GPIO_PUL0: 0x00000004 183 | GPIO_PUL1: 0x00000000 184 | PF: 185 | GPIO_CFG0: 0x00222222 186 | GPIO_CFG1: 0x00000000 187 | GPIO_CFG2: 0x00000000 188 | GPIO_CFG3: 0x00000000 189 | GPIO_DATA: 0x00000000 190 | GPIO_DRV0: 0x00000aaa 191 | GPIO_DRV1: 0x00000000 192 | GPIO_PUL0: 0x00000555 193 | GPIO_PUL1: 0x00000000 194 | ``` 195 | -------------------------------------------------------------------------------- /gpio: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/wuxx/f1c100s-gpio-tools/f70509a5f0b0252c6a4fa531017c6be2eade785c/gpio -------------------------------------------------------------------------------- /gpio.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | /* author: wuxx */ 6 | 7 | enum GPIO_GROUP_E { 8 | PA = 0, 9 | PB = 1, 10 | PC = 2, 11 | PD = 3, 12 | PE = 4, 13 | PF = 5, 14 | }; 15 | 16 | enum GPIO_MODE_E { 17 | IN = 0, 18 | OUT = 1, 19 | }; 20 | 21 | #define GPIO_BASE (0x01C20800) 22 | 23 | #define GPIO_CFG0(n) (GPIO_BASE + ((n) * 0x24) + 0x0) 24 | #define GPIO_CFG1(n) (GPIO_BASE + ((n) * 0x24) + 0x4) 25 | #define GPIO_CFG2(n) (GPIO_BASE + ((n) * 0x24) + 0x8) 26 | #define GPIO_CFG3(n) (GPIO_BASE + ((n) * 0x24) + 0xC) 27 | #define GPIO_DATA(n) (GPIO_BASE + ((n) * 0x24) + 0x10) 28 | #define GPIO_DRV0(n) (GPIO_BASE + ((n) * 0x24) + 0x14) 29 | #define GPIO_DRV1(n) (GPIO_BASE + ((n) * 0x24) + 0x18) 30 | #define GPIO_PUL0(n) (GPIO_BASE + ((n) * 0x24) + 0x1C) 31 | #define GPIO_PUL1(n) (GPIO_BASE + ((n) * 0x24) + 0x20) 32 | 33 | #define MAKE_PID(group, index) (#group#index), ((group) << 5 | index) 34 | 35 | #define get_bit(x, index) (((x) >> index) & 0x1) 36 | 37 | 38 | typedef unsigned char u8; 39 | typedef signed char s8; 40 | typedef unsigned short u16; 41 | typedef signed short s16; 42 | typedef unsigned int u32; 43 | typedef signed int s32; 44 | 45 | /* pio */ 46 | /* | | */ 47 | /* 7 6 5 4 3 2 1 0 */ 48 | struct gpio_info { 49 | char name[16]; /* PA, PB, PC, PD, PE, PF */ 50 | u8 pio; 51 | u32 cfg_addr; 52 | u32 cfg_off; 53 | u32 mode; /* 3 bit */ 54 | char mode_desc[32]; 55 | }; 56 | 57 | /* 6 * 32 * 8 (PA-PF = 6, io0-io32, 8 mode) */ 58 | u32 gindex = 0; 59 | struct gpio_info gi[2048]; 60 | 61 | /* ADD(PA, offset, mode, mode_desc)*/ 62 | 63 | void set_bit(unsigned int *x, unsigned int bit_index, unsigned int b) 64 | { 65 | unsigned int _x; 66 | unsigned int bit_mask; 67 | _x = *x; 68 | if (get_bit(_x, bit_index) != b) { 69 | if (b == 0) { 70 | bit_mask = ~(0x1 << bit_index); 71 | *x = (_x) & bit_mask; 72 | } else { /* b == 1 */ 73 | bit_mask = (0x1 << bit_index); 74 | *x = (_x) | bit_mask; 75 | } 76 | } 77 | } 78 | 79 | 80 | u32 writel(u32 addr, u32 data) 81 | { 82 | FILE *fp; 83 | u32 value = 0; 84 | char cmd[1024]; 85 | 86 | snprintf(cmd, sizeof(cmd), "devmem 0x%08x 32 0x%08x", addr, data); 87 | 88 | fp = popen(cmd, "r"); 89 | 90 | if (fp == NULL) { 91 | fprintf(stderr, "%s: popen(%s) fail!\n", __func__, cmd); 92 | goto err; 93 | } 94 | 95 | err: 96 | pclose(fp); 97 | return value; 98 | 99 | } 100 | 101 | u32 readl(u32 addr) 102 | { 103 | FILE *fp; 104 | u32 value = 0; 105 | char cmd[1024]; 106 | char buf[32]; 107 | 108 | snprintf(cmd, sizeof(cmd), "devmem 0x%08x", addr); 109 | 110 | fp = popen(cmd, "r"); 111 | if (fp == NULL) { 112 | fprintf(stderr, "%s: popen(%s) fail!\n", __func__, cmd); 113 | } 114 | 115 | fread(buf, sizeof(char), sizeof(buf), fp); 116 | sscanf(buf, "0x%x", &value); 117 | 118 | err: 119 | pclose(fp); 120 | return value; 121 | } 122 | 123 | struct gpio_info * gi_get(char *name, char *mode) 124 | { 125 | u32 i; 126 | for(i = 0; i < gindex; i++) { 127 | if ((strcmp(gi[i].name, name) == 0)) { 128 | if (mode == NULL) { 129 | return &(gi[i]); 130 | } else { 131 | if (strcmp(gi[i].mode_desc, mode) == 0) { 132 | return &(gi[i]); 133 | } 134 | } 135 | } 136 | } 137 | return NULL; 138 | } 139 | char * gi_get_mode_desc(u8 pio, u32 mode) 140 | { 141 | u32 i; 142 | for(i = 0; i < gindex; i++) { 143 | if (gi[i].pio == pio && gi[i].mode == mode) { 144 | return gi[i].mode_desc; 145 | } 146 | } 147 | 148 | fprintf(stdout, "%s(0x%x, 0x%x) fail\n", __func__, pio, mode); 149 | return NULL; 150 | } 151 | 152 | void gi_add(char *name, u8 pio, u32 cfg_addr, u32 offset, u32 mode, char *mode_desc) 153 | { 154 | if (gindex >= (sizeof(gi) / sizeof(gi[0]))) { 155 | fprintf(stderr, "gindex overflow!\n"); 156 | exit(-1); 157 | } 158 | 159 | strncpy(gi[gindex].name, name, sizeof(gi[gindex].name)); 160 | gi[gindex].pio = pio; 161 | gi[gindex].cfg_addr = cfg_addr; 162 | gi[gindex].cfg_off = offset; 163 | gi[gindex].mode = mode; 164 | strncpy(gi[gindex].mode_desc, mode_desc, sizeof(gi[gindex].mode_desc)); 165 | 166 | gindex++; 167 | } 168 | 169 | void gi_init() 170 | { 171 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 0, "in"); 172 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 1, "out"); 173 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 2, "tp_x1"); 174 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 3, "reserved"); 175 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 4, "da_bclk"); 176 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 5, "uart1_rts"); 177 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 6, "spi1_cs"); 178 | gi_add(MAKE_PID(PA, 0), GPIO_CFG0(PA), 0x0, 7, "disabled"); 179 | 180 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 0, "in"); 181 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 1, "out"); 182 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 2, "tp_x2"); 183 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 3, "reserved"); 184 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 4, "da_lrck"); 185 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 5, "uart1_cts"); 186 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 6, "spi1_miso"); 187 | gi_add(MAKE_PID(PA, 1), GPIO_CFG0(PA), 0x4, 7, "disabled"); 188 | 189 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 0, "in"); 190 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 1, "out"); 191 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 2, "tp_y1"); 192 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 3, "pwm0"); 193 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 4, "da_in"); 194 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 5, "uart1_rx"); 195 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 6, "spi1_clk"); 196 | gi_add(MAKE_PID(PA, 2), GPIO_CFG0(PA), 0x8, 7, "disabled"); 197 | 198 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 0, "in"); 199 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 1, "out"); 200 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 2, "tp_y2"); 201 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 3, "ir_rx"); 202 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 4, "da_out"); 203 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 5, "uart1_tx"); 204 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 6, "spi1_miso"); 205 | gi_add(MAKE_PID(PA, 3), GPIO_CFG0(PA), 0xc, 7, "disabled"); 206 | 207 | 208 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 0, "in"); 209 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 1, "out"); 210 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 2, "ddr_ref_d"); 211 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 3, "ir_rx"); 212 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 4, "reserved"); 213 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 5, "reserved"); 214 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 6, "reserved"); 215 | gi_add(MAKE_PID(PB, 3), GPIO_CFG0(PB), 0xc, 7, "disabled"); 216 | 217 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 0, "reserved"); 218 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 1, "out"); 219 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 2, "spi0_clk"); 220 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 3, "sdc1_clk"); 221 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 4, "reserved"); 222 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 5, "reserved"); 223 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 6, "reserved"); 224 | gi_add(MAKE_PID(PC, 0), GPIO_CFG0(PC), 0x0, 7, "disabled"); 225 | 226 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 0, "in"); 227 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 1, "out"); 228 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 2, "spi0_cs"); 229 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 3, "sdc1_cmd"); 230 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 4, "reserved"); 231 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 5, "reserved"); 232 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 6, "reserved"); 233 | gi_add(MAKE_PID(PC, 1), GPIO_CFG0(PC), 0x4, 7, "disabled"); 234 | 235 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 0, "in"); 236 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 1, "out"); 237 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 2, "spi0_miso"); 238 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 3, "sdc1_d0"); 239 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 4, "reserved"); 240 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 5, "reserved"); 241 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 6, "reserved"); 242 | gi_add(MAKE_PID(PC, 2), GPIO_CFG0(PC), 0x8, 7, "disabled"); 243 | 244 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 0, "in"); 245 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 1, "out"); 246 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 2, "spi0_mosi"); 247 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 3, "uart0_tx"); 248 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 4, "reserved"); 249 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 5, "reserved"); 250 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 6, "reserved"); 251 | gi_add(MAKE_PID(PC, 3), GPIO_CFG0(PC), 0xc, 7, "disabled"); 252 | 253 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 0, "in"); 254 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 1, "out"); 255 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 2, "lcd_d2"); 256 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 3, "twi0_sda"); 257 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 4, "rsb_sda"); 258 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 5, "reserved"); 259 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 6, "eintd0"); 260 | gi_add(MAKE_PID(PD, 0), GPIO_CFG0(PD), 0x0, 7, "disabled"); 261 | 262 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 0, "in"); 263 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 1, "out"); 264 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 2, "lcd_d3"); 265 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 3, "uart1_rts"); 266 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 4, "reserved"); 267 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 5, "reserved"); 268 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 6, "eintd1"); 269 | gi_add(MAKE_PID(PD, 1), GPIO_CFG0(PD), 0x4, 7, "disabled"); 270 | 271 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 0, "in"); 272 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 1, "out"); 273 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 2, "lcd_d4"); 274 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 3, "uart1_cts"); 275 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 4, "reserved"); 276 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 5, "reserved"); 277 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 6, "eintd2"); 278 | gi_add(MAKE_PID(PD, 2), GPIO_CFG0(PD), 0x8, 7, "disabled"); 279 | 280 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 0, "in"); 281 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 1, "out"); 282 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 2, "lcd_d5"); 283 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 3, "uart1_rx"); 284 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 4, "reserved"); 285 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 5, "reserved"); 286 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 6, "eintd3"); 287 | gi_add(MAKE_PID(PD, 3), GPIO_CFG0(PD), 0xc, 7, "disabled"); 288 | 289 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 0, "in"); 290 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 1, "out"); 291 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 2, "lcd_d6"); 292 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 3, "uart1_tx"); 293 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 4, "reserved"); 294 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 5, "reserved"); 295 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 6, "eintd4"); 296 | gi_add(MAKE_PID(PD, 4), GPIO_CFG0(PD), 0x10, 7, "disabled"); 297 | 298 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 0, "in"); 299 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 1, "out"); 300 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 2, "lcd_d7"); 301 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 3, "twi1_sck"); 302 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 4, "reserved"); 303 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 5, "reserved"); 304 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 6, "eintd5"); 305 | gi_add(MAKE_PID(PD, 5), GPIO_CFG0(PD), 0x14, 7, "disabled"); 306 | 307 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 0, "in"); 308 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 1, "out"); 309 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 2, "lcd_d10"); 310 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 3, "twi1_sda"); 311 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 4, "reserved"); 312 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 5, "reserved"); 313 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 6, "eintd6"); 314 | gi_add(MAKE_PID(PD, 6), GPIO_CFG0(PD), 0x18, 7, "disabled"); 315 | 316 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 0, "in"); 317 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 1, "out"); 318 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 2, "lcd_d11"); 319 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 3, "da_mclk"); 320 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 4, "reserved"); 321 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 5, "reserved"); 322 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 6, "eintd7"); 323 | gi_add(MAKE_PID(PD, 7), GPIO_CFG0(PD), 0x1c, 7, "disabled"); 324 | 325 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 0, "in"); 326 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 1, "out"); 327 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 2, "lcd_d12"); 328 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 3, "da_bclk"); 329 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 4, "reserved"); 330 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 5, "reserved"); 331 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 6, "eintd8"); 332 | gi_add(MAKE_PID(PD, 8), GPIO_CFG1(PD), 0x0, 7, "disabled"); 333 | 334 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 0, "in"); 335 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 1, "out"); 336 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 2, "lcd_d13"); 337 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 3, "da_lrck"); 338 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 4, "reserved"); 339 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 5, "reserved"); 340 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 6, "eintd9"); 341 | gi_add(MAKE_PID(PD, 9), GPIO_CFG1(PD), 0x4, 7, "disabled"); 342 | 343 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 0, "in"); 344 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 1, "out"); 345 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 2, "lcd_d14"); 346 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 3, "da_in"); 347 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 4, "reserved"); 348 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 5, "reserved"); 349 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 6, "eintd10"); 350 | gi_add(MAKE_PID(PD, 10), GPIO_CFG1(PD), 0x8, 7, "disabled"); 351 | 352 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 0, "in"); 353 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 1, "out"); 354 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 2, "lcd_d15"); 355 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 3, "da_out"); 356 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 4, "reserved"); 357 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 5, "reserved"); 358 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 6, "eintd11"); 359 | gi_add(MAKE_PID(PD, 11), GPIO_CFG1(PD), 0xc, 7, "disabled"); 360 | 361 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 0, "in"); 362 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 1, "out"); 363 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 2, "lcd_d18"); 364 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 3, "twi0_sck"); 365 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 4, "rsb_sck"); 366 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 5, "reserved"); 367 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 6, "eintd12"); 368 | gi_add(MAKE_PID(PD, 12), GPIO_CFG1(PD), 0x10, 7, "disabled"); 369 | 370 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 0, "in"); 371 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 1, "out"); 372 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 2, "lcd_d19"); 373 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 3, "uart2_tx"); 374 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 4, "rsb_sck"); 375 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 5, "reserved"); 376 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 6, "eintd13"); 377 | gi_add(MAKE_PID(PD, 13), GPIO_CFG1(PD), 0x14, 7, "disabled"); 378 | 379 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 0, "in"); 380 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 1, "out"); 381 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 2, "lcd_d20"); 382 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 3, "uart2_rx"); 383 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 4, "reserved"); 384 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 5, "reserved"); 385 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 6, "eintd14"); 386 | gi_add(MAKE_PID(PD, 14), GPIO_CFG1(PD), 0x18, 7, "disabled"); 387 | 388 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 0, "in"); 389 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 1, "out"); 390 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 2, "lcd_d21"); 391 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 3, "uart2_rts"); 392 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 4, "twi2_sck"); 393 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 5, "reserved"); 394 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 6, "eintd15"); 395 | gi_add(MAKE_PID(PD, 15), GPIO_CFG1(PD), 0x1c, 7, "disabled"); 396 | 397 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 0, "in"); 398 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 1, "out"); 399 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 2, "lcd_d22"); 400 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 3, "uart2_cts"); 401 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 4, "twi2_sda"); 402 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 5, "reserved"); 403 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 6, "eintd16"); 404 | gi_add(MAKE_PID(PD, 16), GPIO_CFG2(PD), 0x0, 7, "disabled"); 405 | 406 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 0, "in"); 407 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 1, "out"); 408 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 2, "lcd_d23"); 409 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 3, "owa_out"); 410 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 4, "reserved"); 411 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 5, "reserved"); 412 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 6, "eintd17"); 413 | gi_add(MAKE_PID(PD, 17), GPIO_CFG2(PD), 0x4, 7, "disabled"); 414 | 415 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 0, "in"); 416 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 1, "out"); 417 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 2, "lcd_clk"); 418 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 3, "spi0_cs"); 419 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 4, "reserved"); 420 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 5, "reserved"); 421 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 6, "eintd18"); 422 | gi_add(MAKE_PID(PD, 18), GPIO_CFG2(PD), 0x8, 7, "disabled"); 423 | 424 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 0, "in"); 425 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 1, "out"); 426 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 2, "lcd_de"); 427 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 3, "spi0_mosi"); 428 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 4, "reserved"); 429 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 5, "reserved"); 430 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 6, "eintd19"); 431 | gi_add(MAKE_PID(PD, 19), GPIO_CFG2(PD), 0xc, 7, "disabled"); 432 | 433 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 0, "in"); 434 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 1, "out"); 435 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 2, "lcd_hsync"); 436 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 3, "spi0_clk"); 437 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 4, "reserved"); 438 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 5, "reserved"); 439 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 6, "eintd20"); 440 | gi_add(MAKE_PID(PD, 20), GPIO_CFG2(PD), 0x10, 7, "disabled"); 441 | 442 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 0, "in"); 443 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 1, "out"); 444 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 2, "lcd_vsync"); 445 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 3, "spi0_miso"); 446 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 4, "reserved"); 447 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 5, "reserved"); 448 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 6, "eintd21"); 449 | gi_add(MAKE_PID(PD, 21), GPIO_CFG2(PD), 0x14, 7, "disabled"); 450 | 451 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 0, "in"); 452 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 1, "out"); 453 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 2, "csi_hsync"); 454 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 3, "lcd_d0"); 455 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 4, "twi2_sck"); 456 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 5, "uart0_rx"); 457 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 6, "einte0"); 458 | gi_add(MAKE_PID(PE, 0), GPIO_CFG0(PE), 0x0, 7, "disabled"); 459 | 460 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 0, "in"); 461 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 1, "out"); 462 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 2, "csi_vsync"); 463 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 3, "lcd_d1"); 464 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 4, "twi2_sda"); 465 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 5, "uart0_tx"); 466 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 6, "einte1"); 467 | gi_add(MAKE_PID(PE, 1), GPIO_CFG0(PE), 0x4, 7, "disabled"); 468 | 469 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 0, "in"); 470 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 1, "out"); 471 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 2, "csi_pclk"); 472 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 3, "lcd_d8"); 473 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 4, "clk_out"); 474 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 5, "reserved"); 475 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 6, "einte2"); 476 | gi_add(MAKE_PID(PE, 2), GPIO_CFG0(PE), 0x8, 7, "disabled"); 477 | 478 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 0, "in"); 479 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 1, "out"); 480 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 2, "csi_d0"); 481 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 3, "lcd_d9"); 482 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 4, "da_bclk"); 483 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 5, "rsb_sck"); 484 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 6, "einte3"); 485 | gi_add(MAKE_PID(PE, 3), GPIO_CFG0(PE), 0xc, 7, "disabled"); 486 | 487 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 0, "in"); 488 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 1, "out"); 489 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 2, "csi_d1"); 490 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 3, "lcd_d16"); 491 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 4, "da_lrck"); 492 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 5, "rsb_sda"); 493 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 6, "einte4"); 494 | gi_add(MAKE_PID(PE, 4), GPIO_CFG0(PE), 0x10, 7, "disabled"); 495 | 496 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 0, "in"); 497 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 1, "out"); 498 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 2, "csi_d2"); 499 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 3, "lcd_d17"); 500 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 4, "da_in"); 501 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 5, "reserved"); 502 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 6, "einte5"); 503 | gi_add(MAKE_PID(PE, 5), GPIO_CFG0(PE), 0x14, 7, "disabled"); 504 | 505 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 0, "in"); 506 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 1, "out"); 507 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 2, "csi_d3"); 508 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 3, "pwm1"); 509 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 4, "da_out"); 510 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 5, "owa_out"); 511 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 6, "einte6"); 512 | gi_add(MAKE_PID(PE, 6), GPIO_CFG0(PE), 0x18, 7, "disabled"); 513 | 514 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 0, "in"); 515 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 1, "out"); 516 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 2, "csi_d4"); 517 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 3, "uart2_tx"); 518 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 4, "spi1_cs"); 519 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 5, "reserved"); 520 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 6, "einte7"); 521 | gi_add(MAKE_PID(PE, 7), GPIO_CFG0(PE), 0x1c, 7, "disabled"); 522 | 523 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 0, "in"); 524 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 1, "out"); 525 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 2, "csi_d5"); 526 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 3, "uart2_rx"); 527 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 4, "spi1_mosi"); 528 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 5, "reserved"); 529 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 6, "einte8"); 530 | gi_add(MAKE_PID(PE, 8), GPIO_CFG1(PE), 0x0, 7, "disabled"); 531 | 532 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 0, "in"); 533 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 1, "out"); 534 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 2, "csi_d6"); 535 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 3, "uart2_rts"); 536 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 4, "spi1_clk"); 537 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 5, "reserved"); 538 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 6, "einte9"); 539 | gi_add(MAKE_PID(PE, 9), GPIO_CFG1(PE), 0x4, 7, "disabled"); 540 | 541 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 0, "in"); 542 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 1, "out"); 543 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 2, "csi_d7"); 544 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 3, "uart2_cts"); 545 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 4, "spi1_miso"); 546 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 5, "reserved"); 547 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 6, "einte10"); 548 | gi_add(MAKE_PID(PE, 10), GPIO_CFG1(PE), 0x8, 7, "disabled"); 549 | 550 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 0, "in"); 551 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 1, "out"); 552 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 2, "clk_out"); 553 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 3, "twi0_sck"); 554 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 4, "ir_rx"); 555 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 5, "reserved"); 556 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 6, "einte11"); 557 | gi_add(MAKE_PID(PE, 11), GPIO_CFG1(PE), 0xc, 7, "disabled"); 558 | 559 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 0, "in"); 560 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 1, "out"); 561 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 2, "da_mclk"); 562 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 3, "twi0_sda"); 563 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 4, "pwm0"); 564 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 5, "reserved"); 565 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 6, "einte12"); 566 | gi_add(MAKE_PID(PE, 12), GPIO_CFG1(PE), 0x10, 7, "disabled"); 567 | 568 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 0, "in"); 569 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 1, "out"); 570 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 2, "sdc0_d1"); 571 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 3, "dbg_ms"); 572 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 4, "ir_rx"); 573 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 5, "reserved"); 574 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 6, "eintf0"); 575 | gi_add(MAKE_PID(PF, 0), GPIO_CFG0(PF), 0x0, 7, "disabled"); 576 | 577 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 0, "in"); 578 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 1, "out"); 579 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 2, "sdc0_d0"); 580 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 3, "dbg_di"); 581 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 4, "reserved"); 582 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 5, "reserved"); 583 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 6, "eintf1"); 584 | gi_add(MAKE_PID(PF, 1), GPIO_CFG0(PF), 0x4, 7, "disabled"); 585 | 586 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 0, "in"); 587 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 1, "out"); 588 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 2, "sdc0_clk"); 589 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 3, "uart0_tx"); 590 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 4, "reserved"); 591 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 5, "reserved"); 592 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 6, "eintf2"); 593 | gi_add(MAKE_PID(PF, 2), GPIO_CFG0(PF), 0x8, 7, "disabled"); 594 | 595 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 0, "in"); 596 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 1, "out"); 597 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 2, "sdc0_cmd"); 598 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 3, "dbg_do"); 599 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 4, "reserved"); 600 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 5, "reserved"); 601 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 6, "eintf3"); 602 | gi_add(MAKE_PID(PF, 3), GPIO_CFG0(PF), 0xc, 7, "disabled"); 603 | 604 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 0, "in"); 605 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 1, "out"); 606 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 2, "sdc0_d3"); 607 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 3, "uart0_tx"); 608 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 4, "reserved"); 609 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 5, "reserved"); 610 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 6, "eintf4"); 611 | gi_add(MAKE_PID(PF, 4), GPIO_CFG0(PF), 0x10, 7, "disabled"); 612 | 613 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 0, "in"); 614 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 1, "out"); 615 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 2, "sdc0_d2"); 616 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 3, "dbg_ck"); 617 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 4, "pwm1"); 618 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 5, "reserved"); 619 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 6, "eintf5"); 620 | gi_add(MAKE_PID(PF, 5), GPIO_CFG0(PF), 0x14, 7, "disabled"); 621 | } 622 | 623 | void usage(char *program_name) 624 | { 625 | fprintf(stdout, "usage: %s help \n", program_name); 626 | fprintf(stdout, " %s read [PA0|PA1...] \n", program_name); 627 | fprintf(stdout, " %s write [PA0|PA1...] \n", program_name); 628 | fprintf(stdout, " %s mode [PA0|PA1...] [in|out|...]\n", program_name); 629 | fprintf(stdout, " %s readall\n", program_name); 630 | fprintf(stdout, " %s dumpall\n", program_name); 631 | fprintf(stdout, " %s info\n", program_name); 632 | fprintf(stdout, "-- github.com/wuxx/f1c100s-gpio-tools --\n"); 633 | exit(0); 634 | } 635 | 636 | void dump_gpio_info() 637 | { 638 | u32 i; 639 | u32 group, index; 640 | u32 cfg_value, cfg_mask; 641 | u32 dvalue; 642 | u32 current_group = PA; 643 | u32 current_index = 0; 644 | u32 mode = 0; 645 | u32 b = 0; 646 | 647 | fprintf(stdout, "\tvalue\tmode\n"); 648 | fprintf(stdout, "PA:\n"); 649 | 650 | for(i = 0; i < gindex; i = i + 8) { 651 | 652 | group = gi[i].pio >> 5; 653 | index = gi[i].pio & 0x1f; 654 | 655 | if (group != current_group) { 656 | fprintf(stdout, "P%c:\n", 'A' + group); 657 | current_group = group; 658 | } 659 | 660 | fprintf(stdout, "P%c%d:", 'A' + group, index); 661 | 662 | cfg_value = readl(gi[i].cfg_addr); 663 | mode = (cfg_value >> gi[i].cfg_off) & 0x7; 664 | 665 | dvalue = readl(GPIO_DATA(group)); 666 | b = get_bit(dvalue, index); 667 | 668 | fprintf(stdout, "\t%d\t[%s]\n", b, gi_get_mode_desc(gi[i].pio, mode)); 669 | } 670 | 671 | } 672 | 673 | void dump_gpio_mode() 674 | { 675 | u32 i, x; 676 | u32 group, index; 677 | 678 | for(i = 0; i < gindex; i = i + 8) { 679 | group = gi[i].pio >> 5; 680 | index = gi[i].pio & 0x1f; 681 | 682 | fprintf(stdout, "P%c%d:\t(", 'A' + group, index); 683 | 684 | for(x = 0; x < 8; x++) { 685 | fprintf(stdout, "%s ", gi[i + x].mode_desc); 686 | } 687 | 688 | fprintf(stdout, ")\n"); 689 | } 690 | } 691 | 692 | void dump_reg(u32 pio) 693 | { 694 | fprintf(stdout, "GPIO_CFG0: 0x%08x\n", readl(GPIO_CFG0(pio))); 695 | fprintf(stdout, "GPIO_CFG1: 0x%08x\n", readl(GPIO_CFG1(pio))); 696 | fprintf(stdout, "GPIO_CFG2: 0x%08x\n", readl(GPIO_CFG2(pio))); 697 | fprintf(stdout, "GPIO_CFG3: 0x%08x\n", readl(GPIO_CFG3(pio))); 698 | fprintf(stdout, "GPIO_DATA: 0x%08x\n", readl(GPIO_DATA(pio))); 699 | fprintf(stdout, "GPIO_DRV0: 0x%08x\n", readl(GPIO_DRV0(pio))); 700 | fprintf(stdout, "GPIO_DRV1: 0x%08x\n", readl(GPIO_DRV1(pio))); 701 | fprintf(stdout, "GPIO_PUL0: 0x%08x\n", readl(GPIO_PUL0(pio))); 702 | fprintf(stdout, "GPIO_PUL1: 0x%08x\n", readl(GPIO_PUL1(pio))); 703 | } 704 | 705 | void dump_gpio_reg() 706 | { 707 | fprintf(stdout, "PA:\n"); 708 | dump_reg(PA); 709 | 710 | fprintf(stdout, "PB:\n"); 711 | dump_reg(PB); 712 | 713 | fprintf(stdout, "PC:\n"); 714 | dump_reg(PC); 715 | 716 | fprintf(stdout, "PD:\n"); 717 | dump_reg(PD); 718 | 719 | fprintf(stdout, "PE:\n"); 720 | dump_reg(PE); 721 | 722 | fprintf(stdout, "PF:\n"); 723 | dump_reg(PF); 724 | } 725 | 726 | 727 | int main(int argc, char **argv) 728 | { 729 | u32 group, index; 730 | u32 cfg_value, cfg_mask; 731 | u32 dvalue, b; 732 | char *m; 733 | 734 | struct gpio_info *pgi; 735 | 736 | if (argc == 1) { 737 | usage(argv[0]); 738 | } 739 | 740 | gi_init(); 741 | 742 | if (strcmp("read", argv[1]) == 0) { 743 | /* e.g. gpio read PA0 */ 744 | if(argc != 3) { 745 | fprintf(stderr, "%s read pio, e.g. %s read PA0\n", argv[0], argv[0]); 746 | exit(-1); 747 | } 748 | pgi = gi_get(argv[2], NULL); 749 | 750 | if (pgi == NULL) { 751 | fprintf(stderr, "gi_get(%s) fail!\n", argv[2]); 752 | exit(-1); 753 | } 754 | 755 | group = pgi->pio >> 5; /* high 3 bit */ 756 | index = pgi->pio & 0x1f; /* low 5 bit */ 757 | dvalue = readl(GPIO_DATA(group)); 758 | fprintf(stdout, "%s: %d\n", argv[2], get_bit(dvalue, index)); 759 | 760 | } else if (strcmp("write", argv[1]) == 0) { 761 | /* e.g. gpio write PA0 1 */ 762 | if (argc != 4) { 763 | fprintf(stderr, "%s write pio [0|1], e.g. %s write PA 1\n", argv[0], argv[0]); 764 | exit(-1); 765 | } 766 | 767 | pgi = gi_get(argv[2], NULL); 768 | b = atoi(argv[3]); 769 | 770 | if (pgi == NULL) { 771 | fprintf(stderr, "gi_get(%s) fail!\n", argv[2]); 772 | exit(-1); 773 | } 774 | 775 | group = pgi->pio >> 5; /* high 3 bit */ 776 | index = pgi->pio & 0x1f; /* low 5 bit */ 777 | 778 | cfg_value = readl(pgi->cfg_addr); 779 | cfg_mask = 0x7 << pgi->cfg_off; 780 | cfg_value = cfg_value & (~cfg_mask); 781 | cfg_value = cfg_value | OUT << pgi->cfg_off; 782 | writel(pgi->cfg_addr, cfg_value); 783 | 784 | dvalue = readl(GPIO_DATA(group)); 785 | set_bit(&dvalue, index, b); 786 | writel(GPIO_DATA(group), dvalue); 787 | } else if (strcmp("mode", argv[1]) == 0) { 788 | /* e.g. gpio mode PA0 in|out|... */ 789 | if (argc != 4) { 790 | fprintf(stderr, "%s mode pio [in|out|...], e.g. %s mode PA in\n", argv[0], argv[0]); 791 | exit(-1); 792 | } 793 | 794 | m = argv[3]; 795 | pgi = gi_get(argv[2], m); 796 | 797 | if (pgi == NULL) { 798 | fprintf(stderr, "gi_get(%s, %s) fail!\n", argv[2], m); 799 | exit(-1); 800 | } 801 | 802 | group = pgi->pio >> 5; /* high 3 bit */ 803 | index = pgi->pio & 0x1f; /* low 5 bit */ 804 | 805 | cfg_value = readl(pgi->cfg_addr); 806 | cfg_mask = 0x7 << pgi->cfg_off; 807 | cfg_value = cfg_value & (~cfg_mask); 808 | cfg_value = cfg_value | pgi->mode << pgi->cfg_off; 809 | writel(pgi->cfg_addr, cfg_value); 810 | 811 | } else if (strcmp("readall", argv[1]) == 0) { 812 | dump_gpio_info(); 813 | 814 | } else if (strcmp("dumpall", argv[1]) == 0) { 815 | dump_gpio_reg(); 816 | } else if (strcmp("info", argv[1]) == 0) { 817 | dump_gpio_mode(); 818 | } else { 819 | fprintf(stderr, "unknown cmd [%s]\n", argv[1]); 820 | usage(argv[0]); 821 | } 822 | 823 | 824 | return 0; 825 | } 826 | --------------------------------------------------------------------------------