├── LICENSE ├── README.md ├── bench └── verilog │ ├── test_bench_top.v │ ├── tests.v │ ├── tests_lib.v │ └── timescale.v ├── doc ├── README.txt └── success_story.txt ├── rtl └── verilog │ ├── timescale.v │ ├── usb1_core.v │ ├── usb1_crc16.v │ ├── usb1_crc5.v │ ├── usb1_ctrl.v │ ├── usb1_defines.v │ ├── usb1_fifo2.v │ ├── usb1_idma.v │ ├── usb1_pa.v │ ├── usb1_pd.v │ ├── usb1_pe.v │ ├── usb1_pl.v │ ├── usb1_rom1.v │ └── usb1_utmi_if.v └── sim └── rtl_sim ├── bin └── Makefile └── run ├── Makefile └── waves └── waves.do /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/www-asics-ws/usb1_device/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/www-asics-ws/usb1_device/HEAD/README.md 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