├── LICENSE ├── README.md ├── isa ├── 1 ├── rv32mi-p-breakpoint ├── rv32mi-p-breakpoint.dump ├── rv32mi-p-breakpoint.verilog ├── rv32mi-p-csr ├── rv32mi-p-csr.dump ├── rv32mi-p-csr.verilog ├── rv32mi-p-illegal ├── rv32mi-p-illegal.dump ├── rv32mi-p-illegal.verilog ├── rv32mi-p-ma_addr ├── rv32mi-p-ma_addr.dump ├── rv32mi-p-ma_addr.verilog ├── rv32mi-p-mcsr ├── rv32mi-p-mcsr.dump ├── rv32mi-p-mcsr.verilog ├── rv32mi-p-scall ├── rv32mi-p-scall.dump ├── rv32mi-p-scall.verilog ├── rv32ui-p-add ├── rv32ui-p-add.dump ├── rv32ui-p-add.verilog ├── rv32ui-p-addi ├── rv32ui-p-addi.dump ├── rv32ui-p-addi.verilog ├── rv32ui-p-and ├── rv32ui-p-and.dump ├── rv32ui-p-and.verilog ├── rv32ui-p-andi ├── rv32ui-p-andi.dump ├── rv32ui-p-andi.verilog ├── rv32ui-p-auipc ├── rv32ui-p-auipc.dump ├── rv32ui-p-auipc.verilog ├── rv32ui-p-beq ├── rv32ui-p-beq.dump ├── rv32ui-p-beq.verilog ├── rv32ui-p-bge ├── rv32ui-p-bge.dump ├── rv32ui-p-bge.verilog ├── rv32ui-p-bgeu ├── rv32ui-p-bgeu.dump ├── rv32ui-p-bgeu.verilog ├── rv32ui-p-blt ├── rv32ui-p-blt.dump ├── rv32ui-p-blt.verilog ├── rv32ui-p-bltu ├── rv32ui-p-bltu.dump ├── rv32ui-p-bltu.verilog ├── rv32ui-p-bne ├── rv32ui-p-bne.dump ├── rv32ui-p-bne.verilog ├── rv32ui-p-fence_i ├── rv32ui-p-fence_i.dump ├── rv32ui-p-fence_i.verilog ├── rv32ui-p-jal ├── rv32ui-p-jal.dump ├── rv32ui-p-jal.verilog ├── rv32ui-p-jalr ├── rv32ui-p-jalr.dump ├── rv32ui-p-jalr.verilog ├── rv32ui-p-lb ├── rv32ui-p-lb.dump ├── rv32ui-p-lb.verilog ├── rv32ui-p-lbu ├── rv32ui-p-lbu.dump ├── rv32ui-p-lbu.verilog ├── rv32ui-p-lh ├── rv32ui-p-lh.dump ├── rv32ui-p-lh.verilog ├── rv32ui-p-lhu ├── rv32ui-p-lhu.dump ├── rv32ui-p-lhu.verilog ├── rv32ui-p-lui ├── rv32ui-p-lui.dump ├── rv32ui-p-lui.verilog ├── rv32ui-p-lw ├── rv32ui-p-lw.dump ├── rv32ui-p-lw.verilog ├── rv32ui-p-or ├── rv32ui-p-or.dump ├── rv32ui-p-or.verilog ├── rv32ui-p-ori ├── rv32ui-p-ori.dump ├── rv32ui-p-ori.verilog ├── rv32ui-p-sb ├── rv32ui-p-sb.dump ├── rv32ui-p-sb.verilog ├── rv32ui-p-sh ├── rv32ui-p-sh.dump ├── rv32ui-p-sh.verilog ├── rv32ui-p-simple ├── rv32ui-p-simple.dump ├── rv32ui-p-simple.verilog ├── rv32ui-p-sll ├── rv32ui-p-sll.dump ├── rv32ui-p-sll.verilog ├── rv32ui-p-slli ├── rv32ui-p-slli.dump ├── rv32ui-p-slli.verilog ├── rv32ui-p-slt ├── rv32ui-p-slt.dump ├── rv32ui-p-slt.verilog ├── rv32ui-p-slti ├── rv32ui-p-slti.dump ├── rv32ui-p-slti.verilog ├── rv32ui-p-sltiu ├── rv32ui-p-sltiu.dump ├── rv32ui-p-sltiu.verilog ├── rv32ui-p-sltu ├── rv32ui-p-sltu.dump ├── rv32ui-p-sltu.verilog ├── rv32ui-p-sra ├── rv32ui-p-sra.dump ├── rv32ui-p-sra.verilog ├── rv32ui-p-srai ├── rv32ui-p-srai.dump ├── rv32ui-p-srai.verilog ├── rv32ui-p-srl ├── rv32ui-p-srl.dump ├── rv32ui-p-srl.verilog ├── rv32ui-p-srli ├── rv32ui-p-srli.dump ├── rv32ui-p-srli.verilog ├── rv32ui-p-sub ├── rv32ui-p-sub.dump ├── rv32ui-p-sub.verilog ├── rv32ui-p-sw ├── rv32ui-p-sw.dump ├── rv32ui-p-sw.verilog ├── rv32ui-p-xor ├── rv32ui-p-xor.dump ├── rv32ui-p-xor.verilog ├── rv32ui-p-xori ├── rv32ui-p-xori.dump ├── rv32ui-p-xori.verilog ├── rv32um-p-div ├── rv32um-p-div.dump ├── rv32um-p-div.verilog ├── rv32um-p-divu ├── rv32um-p-divu.dump ├── rv32um-p-divu.verilog ├── rv32um-p-mul ├── rv32um-p-mul.dump ├── rv32um-p-mul.verilog ├── rv32um-p-mulh ├── rv32um-p-mulh.dump ├── rv32um-p-mulh.verilog ├── rv32um-p-mulhsu ├── rv32um-p-mulhsu.dump ├── rv32um-p-mulhsu.verilog ├── rv32um-p-mulhu ├── rv32um-p-mulhu.dump ├── rv32um-p-mulhu.verilog ├── rv32um-p-rem ├── rv32um-p-rem.dump ├── rv32um-p-rem.verilog ├── rv32um-p-remu ├── rv32um-p-remu.dump └── rv32um-p-remu.verilog ├── rtl ├── core_top.v ├── cpu_top.v ├── csr.v ├── defines.v ├── dtcm.v ├── flush_unit.v ├── forward_unit.v ├── idex │ ├── alu.v │ ├── csru.v │ ├── decode.v │ ├── defines.v │ ├── exu.v │ ├── idex_unit.v │ ├── jump_unit.v │ ├── lsu_agu.v │ ├── mdu.v │ ├── radix_4_booth_mul.v │ └── srt4 │ │ ├── on_the_fly_conversion.v │ │ ├── pre_processing.v │ │ ├── radix4_table.v │ │ └── srt_4_div.v ├── ifu │ ├── bpu.v │ ├── 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