├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── docker.sh ├── docs └── res │ ├── balancer.png │ ├── balancer_arch.png │ ├── balancer_arch_arp.png │ ├── monitor.png │ └── system.png ├── env ├── Dockerfile ├── Makefile ├── README.md ├── install_hardcaml.sh ├── install_openocd_vex.sh ├── install_quartus.sh ├── install_riscv_toolchain.sh ├── install_sbt.sh └── install_verilator.sh ├── hardcaml ├── .gitignore ├── Makefile ├── README.md ├── dune ├── dune-project ├── main.ml ├── src │ ├── arp.ml │ ├── balancer.ml │ ├── common.ml │ ├── dataplane.ml │ ├── dune │ ├── ip.ml │ ├── lib │ │ ├── arbiter.ml │ │ ├── bus.ml │ │ ├── flow.ml │ │ ├── hashes.ml │ │ ├── hashes.mli │ │ ├── memory.ml │ │ ├── timer.ml │ │ ├── transaction.ml │ │ └── utilities.ml │ ├── load_generator.ml │ └── stat.ml └── test │ ├── lib │ ├── dune │ ├── packet.ml │ ├── sim.ml │ └── sim_elements.ml │ ├── res │ ├── arp.gtkw │ ├── arp_table.gtkw │ ├── arp_table_bus_write_adapter.gtkw │ ├── balancer.gtkw │ ├── bus_interconnect_comb.gtkw │ ├── dataplane.gtkw │ ├── depacketizer_unaligned.gtkw │ ├── flow_with_hdr_arbitrate.gtkw │ ├── flow_with_hdr_dispatcher.gtkw │ ├── flow_with_hdr_synchronize.gtkw │ ├── load_generator.gtkw │ ├── packetizer_full_unaligned.gtkw │ ├── packetizer_unaligned.gtkw │ ├── transaction_deserializer.gtkw │ └── transaction_serializer.gtkw │ ├── tap │ ├── dune │ ├── main.ml │ └── setup.sh │ └── tb │ ├── dune │ ├── lib │ ├── test_bus.ml │ ├── test_flow.ml │ └── test_hashes.ml │ ├── test_arp.ml │ ├── test_balancer.ml │ ├── test_dataplane.ml │ ├── test_ip.ml │ └── test_load_generator.ml ├── ip └── pll │ ├── pll.ppf │ ├── pll.qip │ └── pll.v ├── monitor ├── .gitignore ├── README.md └── monitor.py ├── quartus ├── .gitignore ├── Makefile ├── build │ ├── board.de1soc.mk │ ├── board.de2-115.mk │ ├── common.mk │ ├── qsys-component.mk │ └── tools.mk ├── config.mk ├── dcs │ └── rgmii_io.sdc ├── fpga_lb.qsf ├── fpga_lb.sdc ├── project │ └── Makefile ├── qsys │ ├── Makefile │ ├── components │ │ ├── VexRiscvCpu │ │ │ ├── Makefile │ │ │ ├── VexRiscvCpu.tcl │ │ │ └── comp.mk │ │ ├── gpio_ctrl │ │ │ ├── Makefile │ │ │ ├── comp.mk │ │ │ └── gpio_ctrl.tcl │ │ ├── lb_dataplane │ │ │ ├── Makefile │ │ │ ├── comp.mk │ │ │ └── lb_dataplane.tcl │ │ ├── load_generator │ │ │ ├── Makefile │ │ │ ├── comp.mk │ │ │ └── load_generator.tcl │ │ └── riscv_mtime │ │ │ ├── Makefile │ │ │ ├── comp.mk │ │ │ └── riscv_mtime.tcl │ └── lb_system.qsys ├── signaltap │ ├── dataplane.stp │ ├── tse.stp │ └── vexriscv.stp └── tcl │ └── console.tcl ├── rtl ├── fpga_lb.v ├── gpio_ctrl │ └── gpio_ctrl.v ├── riscv_mtime │ └── riscv_mtime.v └── signal_sync.v ├── sim └── cpp │ ├── .gitignore │ ├── common │ ├── build │ │ └── build.mk │ └── lib │ │ └── include │ │ └── testb.h │ └── vexriscv │ ├── Makefile │ ├── VexRiscvCpu.gtkw │ ├── bus.cpp │ ├── bus.h │ ├── main.cpp │ ├── memctrl.cpp │ ├── memctrl.h │ ├── periph.cpp │ ├── periph.h │ ├── signal.h │ ├── sim.cpp │ └── sim.h ├── spinal ├── .gitignore ├── Makefile ├── build.sbt ├── project │ ├── build.properties │ └── plugins.sbt └── src │ └── main │ └── scala │ └── cpu │ └── VexRiscvCpu.scala ├── sw ├── .gitignore ├── FreeRTOS │ ├── croutine.c │ ├── event_groups.c │ ├── include │ │ ├── FreeRTOS.h │ │ ├── StackMacros.h │ │ ├── atomic.h │ │ ├── croutine.h │ │ ├── deprecated_definitions.h │ │ ├── event_groups.h │ │ ├── list.h │ │ ├── message_buffer.h │ │ ├── mpu_prototypes.h │ │ ├── mpu_wrappers.h │ │ ├── portable.h │ │ ├── projdefs.h │ │ ├── queue.h │ │ ├── semphr.h │ │ ├── stack_macros.h │ │ ├── stdint.readme │ │ ├── stream_buffer.h │ │ ├── task.h │ │ └── timers.h │ ├── list.c │ ├── portable │ │ ├── GCC │ │ │ └── RISC-V │ │ │ │ ├── port.c │ │ │ │ ├── portASM.S │ │ │ │ └── portmacro.h │ │ └── MemMang │ │ │ ├── ReadMe.url │ │ │ ├── heap_1.c │ │ │ ├── heap_2.c │ │ │ ├── heap_3.c │ │ │ ├── heap_4.c │ │ │ └── heap_5.c │ ├── queue.c │ ├── stream_buffer.c │ ├── tasks.c │ └── timers.c ├── Makefile ├── README.md ├── common │ ├── boot.S │ └── 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