├── .gitignore ├── .gitmodules ├── CMakeLists.txt ├── LICENSE ├── Makefile.am ├── README.md ├── appimage ├── .gitignore ├── default.desktop └── icon.png ├── configure.ac ├── deploy_linux.sh ├── deploy_macos.sh ├── deploy_windows.sh ├── enclosure ├── drawing.pdf ├── drawing20180327.pdf └── front_back_panel.fcstd ├── env.cfg ├── generate_source_tarball ├── include └── xavna ├── lib_mock ├── libxavna.so ├── libxavna_mock_ui.so ├── libxavna_mock_ui.so.1 ├── libxavna_mock_ui.so.1.0 └── libxavna_mock_ui.so.1.0.0 ├── libxavna ├── CMakeLists.txt ├── Makefile.am ├── README.md ├── calibration.C ├── common.H ├── common_types.h ├── include │ ├── calibration.H │ ├── common.H │ ├── platform_abstraction.H │ ├── workarounds.H │ ├── xavna.h │ ├── xavna_cpp.H │ └── xavna_generic.H ├── platform_abstraction.C ├── platform_abstraction_windows.C ├── xavna.C ├── xavna_cpp.C └── xavna_mock_ui │ ├── .gitignore │ ├── CMakeLists.txt │ ├── xavna_mock.C │ ├── xavna_mock_ui.C │ ├── xavna_mock_ui.H │ ├── xavna_mock_ui.pro │ ├── xavna_mock_ui_dialog.C │ ├── xavna_mock_ui_dialog.H │ ├── xavna_mock_ui_dialog.ui │ └── xavna_mock_ui_global.h ├── lo_amp.cct ├── lo_amp_2.cct ├── lo_amp_3.cct ├── pcb ├── README.md ├── bb_amp.asc ├── bb_amp_2.asc ├── cmy210_matching.cct ├── coupler.pcb ├── fpga_pins.xcf ├── main.gsch2pcb ├── main.pcb ├── main.sch ├── main2.gsch2pcb ├── main2.mapping.csv ├── main2.pcb ├── main2.sch ├── main2_2.gsch2pcb ├── main2_2.mapping.csv ├── main2_2.pcb ├── main2_2.sch ├── main3.gsch2pcb ├── main3.pcb ├── main3.sch ├── main3_2.gsch2pcb ├── main3_2.mapping.csv ├── main3_2.pcb ├── main3_2.sch ├── packages │ ├── 0402.fp │ ├── 0402_s.fp │ ├── 0402_s.pcb │ ├── 0603.fp │ ├── 0603_0805.fp │ ├── 0805.fp │ ├── 1211.fp │ ├── LQFP144_20.fp │ ├── MSOP10.fp │ ├── QFN16_3_EP.fp │ ├── QFN16_3_EP_ADA4932.fp │ ├── QFN16_4_EP.fp │ ├── QFN24_4_EP.fp │ ├── SC70_5.fp │ ├── SO8.fp │ ├── SO8W.fp │ ├── SOT26.fp │ ├── SSOP28.fp │ ├── TSSOP16.fp │ ├── bga_1.0_25.fp │ ├── bgs14ga14.fp │ ├── connector12_1_25mm.fp │ ├── connector5.fp │ ├── connector9.fp │ ├── custom_bead.fp │ ├── custom_button1.fp │ ├── custom_button2.fp │ ├── custom_cdrh127.fp │ ├── custom_cmy211.fp │ ├── custom_coax1.fp │ ├── custom_coax1_1.fp │ ├── custom_coax1_2.fp │ ├── custom_coax2.fp │ ├── custom_coax3.fp │ ├── custom_coaxial1.fp │ ├── custom_jumper1cm.fp │ ├── custom_jumper1cm5.fp │ ├── custom_lvds1.fp │ ├── custom_microusb1.fp │ ├── custom_miniusb1.fp │ ├── custom_pad1.fp │ ├── custom_pad_edge.fp │ ├── custom_pot_3362.fp │ ├── custom_qfn24.fp │ ├── custom_qfn32.fp │ ├── custom_shield1.fp │ ├── custom_sma1.fp │ ├── custom_sma2.fp │ ├── custom_sma3.fp │ ├── custom_sma4.fp │ ├── custom_sma5.fp │ ├── custom_sma_upright.fp │ ├── custom_so8.fp │ ├── custom_switch1.fp │ ├── cx2156nl.fp │ ├── lp0603.fp │ ├── mcw-0630.fp │ ├── rfsw6024.fp │ ├── sot23_bjt.fp │ ├── tcxo3225.fp │ ├── trf37a75.fp │ └── ufl.fp ├── pwr_filtering.asc ├── rx_lpf.cct ├── sym │ ├── ADV7123.sym │ ├── ad8342.csv │ ├── ad8342.sym │ ├── ad9200.csv │ ├── ad9200.sym │ ├── ada4932-1.csv │ ├── ada4932-1.sym │ ├── adc10065.csv │ ├── adc10065.sym │ ├── adf4350.csv │ ├── adf4350.sym │ ├── ap3419.csv │ ├── ap3419.sym │ ├── bgs12pl6.csv │ ├── bgs12pl6.sym │ ├── bgs14ga14.csv │ ├── bgs14ga14.sym │ ├── blob.sym │ ├── cmy211.csv │ ├── cmy211.sym │ ├── connector_coaxial.sym │ ├── ics511.csv │ ├── ics511.sym │ ├── lp0603.csv │ ├── lp0603.sym │ ├── lt1819.sym │ ├── nc7s04.csv │ ├── nc7s04.sym │ ├── pe4302.csv │ ├── pe4302.sym │ ├── pl133.csv │ ├── pl133.sym │ ├── rfsw6024.csv │ ├── rfsw6024.sym │ ├── s27kl0641.sym │ ├── si53360.csv │ ├── si53360.sym │ ├── solderbridge.sym │ ├── tcxo3225.csv │ ├── tcxo3225.sym │ ├── tragesym │ ├── trf37a75.csv │ ├── trf37a75.sym │ ├── usb.sym │ ├── usb3343.csv │ ├── usb3343.sym │ ├── w25q32.csv │ ├── w25q32.sym │ └── xc6slx9.sym ├── tx.gsch2pcb ├── tx.pcb ├── tx.sch ├── vna_tester.gsch2pcb ├── vna_tester.pcb └── vna_tester.sch ├── pictures ├── all.jpg ├── calibration_standards.jpg ├── cmp_attenuator_200_2180.png ├── cmp_open_stub_200_2180.png ├── cmp_shorted_stub_200_2180.png ├── coupler_top.png ├── drift_100C_short_200_2180.png ├── drift_load_200_2180.png ├── drift_open_200_2180.png ├── drift_resistor_200_2180.png ├── drift_short_200_2180.png ├── fpga_logic.png ├── fpga_logic.xml ├── main2_top.jpg ├── main_top.png ├── overall_diagram.png ├── overall_diagram.xml ├── screenshot_antenna.png ├── screenshot_new_antenna.png ├── screenshot_new_coax.png ├── screenshot_new_ttf.png ├── screenshot_open_stub.png ├── screenshot_pa_900.png ├── screenshot_shorted_stub.png ├── tx_top.png ├── vna_main.png ├── vna_main.xml ├── vna_tx.png └── vna_tx.xml ├── run ├── tester ├── Makefile ├── main.C ├── platform.H ├── platform_opi.C ├── simple_ili9341.H └── ui.H ├── vhdl ├── .gitignore ├── adf4350_calc.vhd ├── bounce_sprite.vhd ├── cic.vhd ├── common │ ├── axi_delay.vhd │ ├── cdc_sync.vhd │ ├── dcfifo.vhd │ ├── dcram.vhd │ ├── edge_detector_sync.vhd │ ├── grey.vhd │ ├── serial_config_register.vhd │ └── spi_data_tx.vhd ├── graphics_types.vhd ├── ili9341_output.vhd ├── ipcore_dir │ ├── clk_wiz_v3_6.asy │ ├── clk_wiz_v3_6.ncf │ ├── clk_wiz_v3_6.sym │ ├── clk_wiz_v3_6.ucf │ ├── clk_wiz_v3_6.vhd │ ├── clk_wiz_v3_6.vho │ ├── clk_wiz_v3_6.xco │ ├── clk_wiz_v3_6.xdc │ ├── clk_wiz_v3_6.xise │ ├── clk_wiz_v3_6_flist.txt │ ├── coregen.cgc │ └── coregen.cgp ├── production │ ├── bitfile.bit │ ├── spiflash.svf │ ├── top2.bin │ └── volatile.svf ├── pulse_extender.vhd ├── reset_generator.vhd ├── sin2.vhd ├── slow_clock.vhd ├── sr.vhd ├── third_party │ ├── fpga-usb-serial-20131205 │ │ ├── COPYING │ │ ├── MANUAL.pdf │ │ ├── README.txt │ │ ├── crcformula.py │ │ ├── fpgaser.inf │ │ ├── perftest │ │ ├── perftest.c │ │ ├── te0146.ucf │ │ ├── testdev.py │ │ ├── usb_control.vhdl │ │ ├── usb_init.vhdl │ │ ├── usb_packet.vhdl │ │ ├── usb_pkg.vhdl │ │ ├── usb_serial.vhdl │ │ ├── usb_transact.vhdl │ │ ├── usbtest.vhdl │ │ └── usbtest.xst-script │ └── ulpi_port.vhdl ├── top.ucf ├── top.vhd ├── top.xdl ├── top2.ucf ├── top2.vhd ├── ulpi_serial.vhd ├── vna.xise └── vna_tx_new.vhd ├── vhdl_twoport ├── .gitignore ├── ipcore_dir │ ├── clk_wiz_v3_6.asy │ ├── clk_wiz_v3_6.ncf │ ├── clk_wiz_v3_6.sym │ ├── clk_wiz_v3_6.ucf │ ├── clk_wiz_v3_6.vhd │ ├── clk_wiz_v3_6.vho │ ├── clk_wiz_v3_6.xco │ ├── clk_wiz_v3_6.xdc │ ├── clk_wiz_v3_6.xise │ ├── clk_wiz_v3_6_2.asy │ ├── clk_wiz_v3_6_2.ncf │ ├── clk_wiz_v3_6_2.sym │ ├── clk_wiz_v3_6_2.ucf │ ├── clk_wiz_v3_6_2.vhd │ ├── clk_wiz_v3_6_2.vho │ ├── clk_wiz_v3_6_2.xco │ ├── clk_wiz_v3_6_2.xdc │ ├── clk_wiz_v3_6_2.xise │ ├── clk_wiz_v3_6_2_flist.txt │ ├── clk_wiz_v3_6_flist.txt │ └── coregen.cgp ├── spiflash.cfi ├── spiflash.mcs ├── spiflash.prm ├── top.ucf ├── top.vhd ├── vhdl_twoport.xise └── vna_tx_new2.vhd ├── vna_diagtool ├── main.cpp ├── mainwindow.C ├── mainwindow.H ├── mainwindow.ui └── vna_diagtool.pro ├── vna_gtk ├── common_types.h ├── configure.ac ├── graph_view.H ├── polar_view.H ├── vna.glade ├── vna_main.C ├── vna_ui_core.C ├── vna_ui_core.H └── xavna_mock.glade └── vna_qt ├── .gitignore ├── CMakeLists.txt ├── add.svg ├── calkitsettings.C ├── calkitsettings.H ├── calkitsettingsdialog.C ├── calkitsettingsdialog.H ├── calkitsettingsdialog.ui ├── calkitsettingswidget.ui ├── configureviewdialog.C ├── configureviewdialog.H ├── configureviewdialog.ui ├── dtfwindow.C ├── dtfwindow.H ├── dtfwindow.ui ├── edit-redo-symbolic.svg ├── emblem-ok-symbolic.svg ├── frequencydialog.C ├── frequencydialog.H ├── frequencydialog.ui ├── graphlimitsdialog.ui ├── graphpanel.C ├── graphpanel.H ├── graphpanel.ui ├── impedancedisplay.C ├── impedancedisplay.H ├── impedancedisplay.ui ├── main.C ├── mainwindow.C ├── mainwindow.H ├── mainwindow.ui ├── markerslider.C ├── markerslider.H ├── markerslider.ui ├── networkview.C ├── networkview.H ├── polarview.C ├── polarview.H ├── resources.qrc ├── touchstone.C ├── touchstone.H ├── utility.H ├── vna_qt.pro ├── xfce-wm-close.svg ├── xfce-wm-maximize.svg └── xfce-wm-unmaximize.svg /.gitignore: -------------------------------------------------------------------------------- 1 | vna_main 2 | *.glade.c 3 | *~ 4 | build-*/* 5 | */build-*/* 6 | cal/* 7 | *.pro.user* 8 | *.a 9 | lib/*.so 10 | pcb/*.png 11 | pcb/*/*.png 12 | *.tar.gz 13 | vhdl/spiflash.* 14 | /Makefile 15 | /xavna_windows/* 16 | /xavna-src/* 17 | /*.zip 18 | /*.tar.gz 19 | libtool 20 | *.AppImage 21 | 22 | */.deps/* 23 | */.libs/* 24 | *.lo 25 | *.la 26 | Makefile.Debug 27 | Makefile.Release 28 | .qmake.* 29 | qrc_resources.cpp 30 | *.svf.gz 31 | vna_qt/release 32 | *_plugin_import.cpp 33 | moc_*.cpp 34 | moc_*.h 35 | ui_*.h 36 | *.exe 37 | *.o 38 | Makefile 39 | Makefile.in 40 | /ar-lib 41 | /mdate-sh 42 | /py-compile 43 | /test-driver 44 | /ylwrap 45 | 46 | # http://www.gnu.org/software/autoconf 47 | 48 | /autom4te.cache 49 | /autoscan.log 50 | /autoscan-*.log 51 | /aclocal.m4 52 | /compile 53 | /config.guess 54 | /config.h.in 55 | /config.sub 56 | /configure 57 | /configure.scan 58 | /depcomp 59 | /install-sh 60 | /missing 61 | /stamp-h1 62 | 63 | # https://www.gnu.org/software/libtool/ 64 | 65 | /ltmain.sh 66 | 67 | # http://www.gnu.org/software/texinfo 68 | 69 | /texinfo.tex 70 | 71 | # http://www.gnu.org/software/m4/ 72 | 73 | m4/libtool.m4 74 | m4/ltoptions.m4 75 | m4/ltsugar.m4 76 | m4/ltversion.m4 77 | m4/lt~obsolete.m4 78 | autom4te.cache 79 | 80 | 81 | 82 | pcb/*_out/* 83 | *.pcb.bak* 84 | pcb/*.raw 85 | pcb/*.fft 86 | pcb/*.net 87 | pcb/*.png 88 | pcb/.* 89 | pcb/*.bom.csv 90 | pcb/#*# 91 | *.log 92 | *.pcb- 93 | pcb/fab/* 94 | pcb/gerber/* 95 | 96 | *.gtl 97 | *.gto 98 | *.gtp 99 | *.gts 100 | *.gbl 101 | *.gbo 102 | *.gbp 103 | *.gbs 104 | *.gm1 105 | *.fab 106 | *.drl 107 | *.g1 108 | *.g2 109 | *.g3 110 | *.g4 111 | *.g5 112 | *.g6 113 | *.g7 114 | 115 | 116 | 117 | # http://www.gnu.org/software/automake 118 | /ar-lib 119 | /mdate-sh 120 | /py-compile 121 | /test-driver 122 | /ylwrap 123 | # http://www.gnu.org/software/autoconf 124 | /autom4te.cache 125 | /autoscan.log 126 | /autoscan-*.log 127 | /aclocal.m4 128 | /compile 129 | /config.guess 130 | /config.h.in 131 | /config.sub 132 | /config.status 133 | /config.log 134 | /configure 135 | /configure.scan 136 | /depcomp 137 | /install-sh 138 | /missing 139 | /stamp-h1 140 | # https://www.gnu.org/software/libtool/ 141 | /ltmain.sh 142 | # http://www.gnu.org/software/texinfo 143 | /texinfo.tex 144 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "tester/svfplayer"] 2 | path = tester/svfplayer 3 | url = https://github.com/xaxaxa-dev/svfplayer.git 4 | -------------------------------------------------------------------------------- /Makefile.am: -------------------------------------------------------------------------------- 1 | ACLOCAL_AMFLAGS = -I m4 --install 2 | 3 | SUBDIRS = libxavna 4 | -------------------------------------------------------------------------------- /appimage/.gitignore: -------------------------------------------------------------------------------- 1 | doc/ 2 | lib/ 3 | plugins/ 4 | translations/ 5 | qt.conf 6 | vna_qt 7 | AppRun 8 | .DirIcon 9 | -------------------------------------------------------------------------------- /appimage/default.desktop: -------------------------------------------------------------------------------- 1 | [Desktop Entry] 2 | Type=Application 3 | Name=xaVNA GUI 4 | Exec=AppRun %F 5 | Icon=icon 6 | Comment=Example application using libxavna 7 | Terminal=false 8 | Categories=Science; 9 | -------------------------------------------------------------------------------- /appimage/icon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/appimage/icon.png -------------------------------------------------------------------------------- /configure.ac: -------------------------------------------------------------------------------- 1 | AC_INIT(vna, version-0.1, private0x01@gmail.com) 2 | AM_INIT_AUTOMAKE([-Wall -Werror foreign]) 3 | m4_ifdef([AM_PROG_AR], [AM_PROG_AR]) 4 | AC_PROG_CXX 5 | AC_LANG(C++) 6 | AC_CONFIG_MACRO_DIR([m4]) 7 | #AC_CONFIG_HEADERS([libxavna/include/xavna.h]) 8 | AC_CONFIG_FILES([ 9 | Makefile 10 | libxavna/Makefile 11 | ]) 12 | LT_INIT([win32-dll]) 13 | AC_CANONICAL_HOST 14 | 15 | is_windows=no 16 | case "${host_os}" in 17 | cygwin*|mingw*) 18 | is_windows=yes 19 | ;; 20 | linux-androideabi) 21 | is_android=yes 22 | ;; 23 | esac 24 | 25 | AM_CONDITIONAL([WINDOWS], [test "$is_windows" = "yes"]) 26 | AM_CONDITIONAL([ANDROID], [test "$is_android" = "yes"]) 27 | 28 | AC_CHECK_HEADER(eigen3/Eigen/Dense) 29 | if test "$ac_cv_header_eigen3_Eigen_Dense" == no 30 | then 31 | AC_MSG_ERROR([eigen3 not installed (eigen3/Eigen/Dense include not found)]) 32 | fi 33 | 34 | 35 | AC_CHECK_HEADER(fftw3.h) 36 | if test "$ac_cv_header_fftw3_h" == no 37 | then 38 | AC_MSG_ERROR([fftw3 not installed (fftw3.h include not found)]) 39 | fi 40 | 41 | 42 | 43 | #if test -z $CXXFLAGS; then 44 | # CXXFLAGS='-O2 -std=c++0x -fPIC -fwrapv -fno-delete-null-pointer-checks -funsigned-char -fno-strict-aliasing -Wno-pmf-conversions' 45 | #fi 46 | 47 | #AC_SUBST(OBJECTS) 48 | #OBJECTS="lib/libxavna.so" 49 | 50 | 51 | 52 | #AC_SUBST(EXTRA_LIBRARIES) 53 | #AC_SUBST(EXTRA_SOURCES) 54 | 55 | #AC_ARG_VAR([QMAKE], [Path to qmake]) 56 | 57 | #AC_ARG_WITH([qt_gui], 58 | #[AS_HELP_STRING([--with-qt-gui], 59 | #[Build QT GUI @<:@default=yes@:>@])], 60 | #[], 61 | #[with_qt_gui=yes]) 62 | 63 | 64 | #if test "$with_qt_gui" == "yes" 65 | #then 66 | #AC_CHECK_PROG([QMAKE], [qmake], [qmake]) 67 | #OBJECTS+=" vna_qt/vna_qt" 68 | #fi 69 | 70 | AC_OUTPUT 71 | -------------------------------------------------------------------------------- /deploy_linux.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # please edit env.cfg and set the correct paths before running 4 | 5 | cd "$(dirname $0)" 6 | . env.cfg 7 | if [ ! -e "$QT" ]; then 8 | echo "please edit env.cfg and set \$QT" 9 | exit 1 10 | fi 11 | if [ ! -e "$LINUXDEPLOYQT" ]; then 12 | echo "please edit env.cfg and set \$LINUXDEPLOYQT" 13 | exit 1 14 | fi 15 | QMAKE="$QT/bin/qmake" 16 | 17 | autoreconf --install 18 | ./configure 19 | make -j$(nproc) 20 | 21 | pushd libxavna/xavna_mock_ui 22 | $QMAKE 23 | make -j$(nproc) 24 | popd 25 | 26 | pushd vna_qt 27 | $QMAKE 28 | make -j$(nproc) 29 | popd 30 | 31 | export LD_LIBRARY_PATH="$(pwd)/libxavna/.libs:$(pwd)/libxavna/xavna_mock_ui:$QT/lib" 32 | cp -a vna_qt/vna_qt appimage/ 33 | rm -rf appimage/lib appimage/plugins 34 | "$LINUXDEPLOYQT" appimage/vna_qt -qmake="$QMAKE" -appimage 35 | 36 | -------------------------------------------------------------------------------- /deploy_macos.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd "$(dirname $0)" 4 | . env.cfg 5 | if [ ! -e "$QT" ]; then 6 | echo "please edit env.cfg and set \$QT" 7 | exit 1 8 | fi 9 | QMAKE="$QT/bin/qmake" 10 | 11 | autoreconf --install 12 | ./configure 13 | make -j8 14 | 15 | pushd libxavna/xavna_mock_ui 16 | $QMAKE 17 | make -j8 18 | popd 19 | 20 | pushd vna_qt 21 | rm -rf *.app 22 | $QMAKE 23 | make -j8 24 | "$QT"/bin/macdeployqt vna_qt.app -libpath=../libxavna/xavna_mock_ui 25 | cp -a ../libxavna/.libs/libxavna.0.dylib vna_qt.app/Contents/Frameworks 26 | 27 | pushd vna_qt.app/Contents 28 | install_name_tool -add_rpath "@executable_path/../Frameworks" MacOS/vna_qt 29 | install_name_tool -change libxavna_mock_ui.1.dylib @executable_path/../Frameworks/libxavna_mock_ui.1.dylib MacOS/vna_qt 30 | install_name_tool -change /usr/local/lib/libxavna.0.dylib @executable_path/../Frameworks/libxavna.0.dylib MacOS/vna_qt 31 | install_name_tool -change /usr/local/lib/libxavna.0.dylib @executable_path/../Frameworks/libxavna.0.dylib Frameworks/libxavna_mock_ui.1.dylib 32 | popd 33 | 34 | rm -rf dmg_contents ../xaVNA_MacOS.dmg tmp.dmg 35 | mkdir dmg_contents 36 | cp -a vna_qt.app dmg_contents/ 37 | 38 | hdiutil create tmp.dmg -ov -volname "xaVNA GUI" -fs HFS+ -srcfolder dmg_contents 39 | hdiutil convert tmp.dmg -format UDZO -o ../xaVNA_MacOS.dmg 40 | 41 | -------------------------------------------------------------------------------- /deploy_windows.sh: -------------------------------------------------------------------------------- 1 | MXE=/persist/mxe 2 | export PATH="$MXE/usr/bin:$PATH" 3 | HOST="i686-w64-mingw32.shared" 4 | QMAKE="$HOST-qmake-qt5" 5 | 6 | autoreconf --install 7 | ./configure --host "$HOST" CXXFLAGS=-O2 8 | make -j8 9 | 10 | pushd libxavna/xavna_mock_ui 11 | "$QMAKE" 12 | make -j8 13 | popd 14 | 15 | pushd vna_qt 16 | "$QMAKE" 17 | make -j8 18 | for x in Qt5Charts Qt5Core Qt5Gui Qt5Widgets Qt5Svg; do 19 | cp "$MXE/usr/$HOST/qt5/bin/$x.dll" release/ 20 | done 21 | mkdir -p release/platforms 22 | mkdir -p release/styles 23 | mkdir -p release/imageformats 24 | mkdir -p release/iconengines 25 | 26 | for x in platforms/qwindows styles/qwindowsvistastyle \ 27 | imageformats/qsvg iconengines/qsvgicon; do 28 | cp "$MXE/usr/$HOST/qt5/plugins/$x.dll" release/"$x".dll 29 | done; 30 | 31 | for x in libgcc_s_sjlj-1 libstdc++-6 libpcre2-16-0 zlib1 libharfbuzz-0 \ 32 | libpng16-16 libfreetype-6 libglib-2.0-0 libbz2 libintl-8 libpcre-1\ 33 | libiconv-2 libwinpthread-1 libjasper libjpeg-9 libmng-2 libtiff-5\ 34 | libwebp-5 libwebpdemux-1 liblcms2-2 liblzma-5 libfftw3-3; do 35 | cp "$MXE/usr/$HOST/bin/$x.dll" release/ 36 | done 37 | cp ../libxavna/.libs/libxavna-0.dll release/ 38 | cp ../libxavna/xavna_mock_ui/release/xavna_mock_ui.dll release/ 39 | rm release/*.cpp release/*.o release/*.h 40 | rm ../*.zip 41 | zip -r ../xaVNA_win32.zip release 42 | -------------------------------------------------------------------------------- /enclosure/drawing.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/enclosure/drawing.pdf -------------------------------------------------------------------------------- /enclosure/drawing20180327.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/enclosure/drawing20180327.pdf -------------------------------------------------------------------------------- /enclosure/front_back_panel.fcstd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/enclosure/front_back_panel.fcstd -------------------------------------------------------------------------------- /env.cfg: -------------------------------------------------------------------------------- 1 | 2 | # path to a qt build, e.g. ~/qt/5.10.1/gcc_64 3 | QT=/persist/qt/5.10.1/gcc_64 4 | 5 | # path to a linuxdeployqt binary, e.g. ~/linuxdeployqt-continuous-x86_64.AppImage 6 | LINUXDEPLOYQT=/persist/linuxdeployqt-continuous-x86_64.AppImage 7 | 8 | -------------------------------------------------------------------------------- /generate_source_tarball: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf xavna-src 4 | rsync -a ./ xavna-src --exclude xavna-src --exclude 'xavna_windows*' --exclude '*.gz' --exclude 'lib/*' --exclude vhdl --exclude pcb --exclude 'build-*' --exclude pictures --exclude '*.cache' --exclude .git --exclude '*~' 5 | tar cfz xavna-src.tar.gz xavna-src 6 | -------------------------------------------------------------------------------- /include/xavna: -------------------------------------------------------------------------------- 1 | ../libxavna/include -------------------------------------------------------------------------------- /lib_mock/libxavna.so: -------------------------------------------------------------------------------- 1 | ../libxavna/build-xavna_mock_ui-Desktop-Debug/libxavna_mock_ui.so -------------------------------------------------------------------------------- /lib_mock/libxavna_mock_ui.so: -------------------------------------------------------------------------------- 1 | ../libxavna/build-xavna_mock_ui-Desktop-Debug/libxavna_mock_ui.so -------------------------------------------------------------------------------- /lib_mock/libxavna_mock_ui.so.1: -------------------------------------------------------------------------------- 1 | ../libxavna/build-xavna_mock_ui-Desktop-Debug/libxavna_mock_ui.so.1 -------------------------------------------------------------------------------- /lib_mock/libxavna_mock_ui.so.1.0: -------------------------------------------------------------------------------- 1 | ../libxavna/build-xavna_mock_ui-Desktop-Debug/libxavna_mock_ui.so.1.0 -------------------------------------------------------------------------------- /lib_mock/libxavna_mock_ui.so.1.0.0: -------------------------------------------------------------------------------- 1 | ../libxavna/build-xavna_mock_ui-Desktop-Debug/libxavna_mock_ui.so.1.0.0 -------------------------------------------------------------------------------- /libxavna/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | set(libxavna_SRC xavna.C 3 | xavna_cpp.C 4 | calibration.C) 5 | 6 | if(WIN32) 7 | list(APPEND libxavna_SRC platform_abstraction_windows.C) 8 | else() 9 | list(APPEND libxavna_SRC platform_abstraction.C) 10 | endif() 11 | 12 | add_library(xavna SHARED ${libxavna_SRC}) 13 | 14 | set_target_properties(xavna PROPERTIES 15 | VERSION ${xaVNA_VERSION_STRING} 16 | SOVERSION ${xaVNA_VERSION_MAJOR}) 17 | 18 | target_link_libraries(xavna ${xa_LIBRARIES}) 19 | 20 | # Declare destinations 21 | install(TARGETS xavna 22 | LIBRARY DESTINATION ${LIB_INSTALL_DIR} 23 | ARCHIVE DESTINATION ${LIB_INSTALL_DIR}) 24 | -------------------------------------------------------------------------------- /libxavna/Makefile.am: -------------------------------------------------------------------------------- 1 | AM_CPPFLAGS = -I../include -O2 -std=c++0x -fPIC -fwrapv -fno-delete-null-pointer-checks -funsigned-char -fno-strict-aliasing -Wno-pmf-conversions 2 | AM_LDFLAGS = -no-undefined 3 | lib_LTLIBRARIES = libxavna.la 4 | libxavna_la_SOURCES = xavna.C xavna_cpp.C calibration.C 5 | 6 | 7 | AM_CPPFLAGS += -DEIGEN_DONT_VECTORIZE -DEIGEN_DISABLE_UNALIGNED_ARRAY_ASSERT 8 | 9 | if !ANDROID 10 | AM_LDFLAGS += -lpthread 11 | endif 12 | 13 | if WINDOWS 14 | libxavna_la_SOURCES += platform_abstraction_windows.C 15 | else 16 | libxavna_la_SOURCES += platform_abstraction.C 17 | endif 18 | -------------------------------------------------------------------------------- /libxavna/common.H: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | using namespace std; 6 | using namespace Eigen; 7 | 8 | template array, N> operator*(const array, N>& a, double b) { 9 | array, N> res; 10 | for(int i=0;i freeNodes, vector forcedNodes, vector > forcedNodeValues) { 31 | assert(freeNodes.size() == forcedNodes.size()); 32 | assert(forcedNodes.size() == forcedNodeValues.size()); 33 | 34 | for(int i=0;i<(int)freeNodes.size();i++) { 35 | // create a self-loop of gain 1 on the free node 36 | // the self-loop allows the free node to take on any value with no incoming edge 37 | sfg(freeNodes[i], freeNodes[i]) = 1.; 38 | 39 | // create an edge from the forced node to the free node with value -1 40 | sfg(freeNodes[i], forcedNodes[i]) = -1.; 41 | // add an excitation on the free node with the value of the forced node value 42 | excitation(forcedNodes[i]) = forcedNodeValues[i]; 43 | 44 | // the self-loop of gain 1 on the free node enforces all the incoming edges must sum to 0, 45 | // because otherwise the feedback will cause the value to blow up; 46 | // the effect of this constraint is that the forced node must in the end have a value 47 | // equal to the forced value 48 | } 49 | return solveSFG(sfg, excitation); 50 | } 51 | 52 | 53 | -------------------------------------------------------------------------------- /libxavna/common_types.h: -------------------------------------------------------------------------------- 1 | #ifndef __COMMON_TYPES_H 2 | #define __COMMON_TYPES_H 3 | 4 | 5 | typedef unsigned long ul; 6 | typedef unsigned int ui; 7 | typedef long long ll; 8 | typedef unsigned long long ull; 9 | typedef uint64_t u64; 10 | typedef uint32_t u32; 11 | typedef uint16_t u16; 12 | typedef uint8_t u8; 13 | typedef int8_t s8; 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /libxavna/include/common.H: -------------------------------------------------------------------------------- 1 | #ifndef __XAVNA_COMMON_H 2 | #define __XAVNA_COMMON_H 3 | #include 4 | #include 5 | #include 6 | using namespace Eigen; 7 | using namespace std; 8 | 9 | 10 | //EIGEN_DEFINE_STL_VECTOR_SPECIALIZATION(Matrix2cd); 11 | 12 | 13 | namespace xaxaxa { 14 | using VNARawValue = Matrix2cd; 15 | using VNACalibratedValue = Matrix2cd; 16 | inline Matrix2cd mirror(Matrix2cd a) { 17 | complex tmp; 18 | tmp = a(0,0); 19 | a(0,0) = a(1,1); 20 | a(1,1) = tmp; 21 | tmp = a(0,1); 22 | a(0,1) = a(1,0); 23 | a(1,0) = tmp; 24 | return a; 25 | } 26 | } 27 | 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /libxavna/include/platform_abstraction.H: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | 5 | 6 | // functions with platform specific implementation go here 7 | 8 | vector xavna_find_devices(); 9 | int xavna_open_serial(const char* path); 10 | void xavna_drainfd(int fd); 11 | bool xavna_detect_autosweep(int fd); 12 | -------------------------------------------------------------------------------- /libxavna/include/workarounds.H: -------------------------------------------------------------------------------- 1 | #ifdef ANDROID_WORKAROUNDS 2 | 3 | #define pthread_cancel(x) /**/ 4 | #define to_string(x) my_to_string(x) 5 | 6 | inline string my_to_string(int x) { 7 | char buf[32]; 8 | snprintf(buf,32,"%d",x); 9 | return buf; 10 | } 11 | inline string my_to_string(double x) { 12 | char buf[32]; 13 | snprintf(buf,32,"%lf",x); 14 | return buf; 15 | } 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /libxavna/include/xavna_generic.H: -------------------------------------------------------------------------------- 1 | #include 2 | #include "xavna.h" 3 | 4 | using namespace std; 5 | class xavna_generic { 6 | public: 7 | virtual bool is_tr()=0; 8 | virtual bool is_autosweep()=0; 9 | virtual int set_params(int freq_khz, int atten, int port, int nWait)=0; 10 | virtual int set_autosweep(double sweepStartHz, double sweepStepHz, int sweepPoints, int nValues=1)=0; 11 | virtual int set_if_freq(int freq_khz)=0; 12 | virtual int read_values(double* out_values, int n_samples)=0; 13 | virtual int read_values_raw(double* out_values, int n_samples)=0; 14 | virtual int read_autosweep(autoSweepDataPoint* out_values, int n_values)=0; 15 | virtual ~xavna_generic() {} 16 | }; 17 | 18 | typedef function xavna_constructor; 19 | 20 | 21 | -------------------------------------------------------------------------------- /libxavna/platform_abstraction.C: -------------------------------------------------------------------------------- 1 | #include "include/platform_abstraction.H" 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | 12 | using namespace std; 13 | vector xavna_find_devices() { 14 | vector ret; 15 | DIR *dir; 16 | struct dirent *ent; 17 | if ((dir = opendir ("/dev")) == NULL) 18 | throw runtime_error("xavna_find_devices: could not list /dev: " + 19 | string(strerror(errno))); 20 | 21 | /* print all the files and directories within directory */ 22 | while ((ent = readdir (dir)) != NULL) { 23 | string name = ent->d_name; 24 | if(name.find("ttyACM")==0) 25 | ret.push_back("/dev/"+name); 26 | if(name.find("cu.usbmodem")==0) 27 | ret.push_back("/dev/"+name); 28 | } 29 | closedir (dir); 30 | return ret; 31 | } 32 | 33 | int xavna_open_serial(const char* path) { 34 | int fd = open(path,O_RDWR); 35 | if(fd<0) return fd; 36 | struct termios tc; 37 | /* Set TTY mode. */ 38 | if (tcgetattr(fd, &tc) < 0) { 39 | perror("tcgetattr"); 40 | return fd; 41 | } 42 | /*tc.c_iflag &= ~(INLCR|IGNCR|ICRNL|IGNBRK|IUCLC|INPCK|ISTRIP|IXON|IXOFF|IXANY); 43 | tc.c_oflag &= ~OPOST; 44 | tc.c_cflag &= ~(CSIZE|CSTOPB|PARENB|PARODD|CRTSCTS); 45 | tc.c_cflag |= CS8 | CREAD | CLOCAL; 46 | tc.c_lflag &= ~(ICANON|ECHO|ECHOE|ECHOK|ECHONL|ISIG|IEXTEN);*/ 47 | 48 | tc.c_iflag = 0; 49 | tc.c_oflag = 0; 50 | tc.c_lflag = 0; 51 | tc.c_cflag = CS8 | CREAD | CLOCAL; 52 | tc.c_cc[VMIN] = 1; 53 | tc.c_cc[VTIME] = 0; 54 | tcsetattr(fd, TCSANOW, &tc); 55 | return fd; 56 | } 57 | 58 | void xavna_drainfd(int fd) { 59 | pollfd pfd; 60 | pfd.fd = fd; 61 | pfd.events = POLLIN; 62 | while(poll(&pfd,1,0)>0) { 63 | if(!(pfd.revents&POLLIN)) continue; 64 | char buf[4096]; 65 | read(fd,buf,sizeof(buf)); 66 | } 67 | } 68 | 69 | 70 | bool xavna_detect_autosweep(int fd) { 71 | pollfd pfd; 72 | pfd.fd = fd; 73 | pfd.events = POLLIN; 74 | if(poll(&pfd,1,100) == 0) { 75 | // no data was received => autosweep device 76 | return true; 77 | } 78 | return false; 79 | } 80 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/.gitignore: -------------------------------------------------------------------------------- 1 | *.so 2 | *.so.* 3 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | add_definitions(-DXAVNA_MOCK_UI_LIBRARY) 3 | 4 | include_directories(${Qt5Charts_INCLUDE_DIRS}) 5 | 6 | # Instruct CMake to run moc automatically when needed 7 | set(CMAKE_AUTOMOC ON) 8 | # Create code from a list of Qt designer ui files 9 | set(CMAKE_AUTOUIC ON) 10 | 11 | set(xavna_mock_ui_SRCS 12 | xavna_mock_ui.C 13 | xavna_mock.C 14 | xavna_mock_ui_dialog.C) 15 | 16 | set(xavna_mock_ui_FRMS 17 | xavna_mock_ui_dialog.ui) 18 | 19 | set(xavna_mock_ui_HDRS 20 | xavna_mock_ui.H 21 | xavna_mock_ui_dialog.H 22 | xavna_mock_ui_global.h 23 | ../include/calibration.H) 24 | 25 | add_library(xavna_mock_ui SHARED ${xavna_mock_ui_SRCS} ${xavna_mock_ui_FRMS} ${xavna_mock_ui_HDRS}) 26 | 27 | set_target_properties(xavna_mock_ui PROPERTIES 28 | VERSION ${xaVNA_VERSION_STRING} 29 | SOVERSION ${xaVNA_VERSION_MAJOR}) 30 | 31 | target_link_libraries(xavna_mock_ui Qt5::Core Qt5::Widgets Qt5::Gui xavna) 32 | 33 | # Declare destinations 34 | install(TARGETS xavna_mock_ui 35 | LIBRARY DESTINATION ${LIB_INSTALL_DIR} 36 | ARCHIVE DESTINATION ${LIB_INSTALL_DIR}) 37 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/xavna_mock_ui.C: -------------------------------------------------------------------------------- 1 | #include "xavna_mock_ui.H" 2 | #include "xavna_mock_ui_dialog.H" 3 | #include 4 | #include 5 | #include 6 | 7 | QApplication* app; 8 | pthread_t pth; 9 | 10 | void* thread1(void*) { 11 | //app->exec(); 12 | while(true) { 13 | usleep(100000); 14 | QApplication::processEvents(); 15 | } 16 | } 17 | 18 | char tmp[10] = ""; 19 | char* tmp1[] = {tmp}; 20 | int argc1=1; 21 | 22 | xavna_mock_ui::xavna_mock_ui() { 23 | bool createApp = (QCoreApplication::instance()==NULL); 24 | if(createApp) { 25 | fprintf(stderr,"NO QAPPLICATION FOUND; STARTING QAPPLICATION IN BACKGROUND THREAD\n"); 26 | fflush(stderr); 27 | app = new QApplication(argc1,tmp1); 28 | } 29 | 30 | xavna_mock_ui_dialog* wnd=new xavna_mock_ui_dialog(); 31 | this->wnd = wnd; 32 | wnd->show(); 33 | if(createApp) { 34 | QMetaObject::invokeMethod(qApp, "quit", Qt::QueuedConnection); 35 | app->exec(); 36 | pthread_create(&pth, NULL, &thread1, NULL); 37 | } 38 | } 39 | 40 | xavna_mock_ui::~xavna_mock_ui() { 41 | xavna_mock_ui_dialog* wnd = (xavna_mock_ui_dialog*)this->wnd; 42 | wnd->close(); 43 | } 44 | 45 | void xavna_mock_ui::set_cb(const xavna_ui_changed_cb& cb) { 46 | xavna_mock_ui_dialog* wnd = (xavna_mock_ui_dialog*)this->wnd; 47 | wnd->cb = cb; 48 | } 49 | 50 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/xavna_mock_ui.H: -------------------------------------------------------------------------------- 1 | #ifndef XAVNA_MOCK_UI_H 2 | #define XAVNA_MOCK_UI_H 3 | 4 | #include 5 | #include 6 | 7 | using namespace std; 8 | typedef function xavna_ui_changed_cb; 9 | 10 | class xavna_mock_ui 11 | { 12 | void* wnd=NULL; 13 | public: 14 | xavna_mock_ui(); 15 | ~xavna_mock_ui(); 16 | void set_cb(const xavna_ui_changed_cb &cb); 17 | }; 18 | 19 | #endif // XAVNA_MOCK_UI_H 20 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/xavna_mock_ui.pro: -------------------------------------------------------------------------------- 1 | #------------------------------------------------- 2 | # 3 | # Project created by QtCreator 2018-02-15T07:40:00 4 | # 5 | #------------------------------------------------- 6 | 7 | QT += widgets 8 | CONFIG += shared 9 | 10 | QMAKE_CXXFLAGS += -Wextra -std=c++11 -I/usr/local/include -I../../include 11 | QMAKE_CXXFLAGS += -DEIGEN_DONT_VECTORIZE -DEIGEN_DISABLE_UNALIGNED_ARRAY_ASSERT 12 | android: QMAKE_CXXFLAGS += -DANDROID_WORKAROUNDS 13 | 14 | TARGET = xavna_mock_ui 15 | TEMPLATE = lib 16 | 17 | DEFINES += XAVNA_MOCK_UI_LIBRARY 18 | 19 | # The following define makes your compiler emit warnings if you use 20 | # any feature of Qt which as been marked as deprecated (the exact warnings 21 | # depend on your compiler). Please consult the documentation of the 22 | # deprecated API in order to know how to port your code away from it. 23 | DEFINES += QT_DEPRECATED_WARNINGS 24 | 25 | # You can also make your code fail to compile if you use deprecated APIs. 26 | # In order to do so, uncomment the following line. 27 | # You can also select to disable deprecated APIs only up to a certain version of Qt. 28 | #DEFINES += QT_DISABLE_DEPRECATED_BEFORE=0x060000 # disables all the APIs deprecated before Qt 6.0.0 29 | 30 | SOURCES += xavna_mock_ui.C \ 31 | xavna_mock.C \ 32 | xavna_mock_ui_dialog.C 33 | 34 | HEADERS += xavna_mock_ui.H\ 35 | xavna_mock_ui_dialog.H \ 36 | xavna_mock_ui_global.h \ 37 | ../include/calibration.H 38 | 39 | unix { 40 | target.path = /usr/lib 41 | INSTALLS += target 42 | } 43 | 44 | FORMS += \ 45 | xavna_mock_ui_dialog.ui 46 | 47 | LIBS += -L$$PWD/../.libs/ -lxavna 48 | !android: LIBS += -lpthread 49 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/xavna_mock_ui_dialog.C: -------------------------------------------------------------------------------- 1 | #include "xavna_mock_ui_dialog.H" 2 | #include "ui_xavna_mock_ui_dialog.h" 3 | #include 4 | #include 5 | #include 6 | 7 | 8 | using namespace std; 9 | inline string ssprintf(int maxLen, const char* fmt, ...) { 10 | string tmp(maxLen, '\0'); 11 | va_list args; 12 | va_start(args, fmt); 13 | vsnprintf((char*)tmp.data(), maxLen, fmt, args); 14 | va_end(args); 15 | return tmp; 16 | } 17 | 18 | xavna_mock_ui_dialog::xavna_mock_ui_dialog(QWidget *parent) : 19 | QMainWindow(parent), 20 | ui(new Ui::xavna_mock_ui_dialog) 21 | { 22 | ui->setupUi(this); 23 | 24 | for(auto& btn:ui->buttonGroup->buttons()) { 25 | connect(btn, SIGNAL(clicked()), SLOT(cb_changed())); 26 | } 27 | this->setWindowFlags(Qt::WindowStaysOnTopHint); 28 | cb = [](string,double,double){}; 29 | } 30 | 31 | xavna_mock_ui_dialog::~xavna_mock_ui_dialog() { 32 | delete ui; 33 | } 34 | 35 | void xavna_mock_ui_dialog::cb_changed() { 36 | this->cb(ui->buttonGroup->checkedButton()->text().toStdString(), ui->slider1->value(), ui->slider2->value()); 37 | } 38 | 39 | void set_text(QLabel* l, string text) { 40 | QString tmp = QString::fromStdString(text); 41 | l->setText(tmp); 42 | } 43 | void xavna_mock_ui_dialog::on_slider1_valueChanged(int value) { 44 | set_text(ui->l_slider1, to_string(value)); 45 | cb_changed(); 46 | } 47 | void xavna_mock_ui_dialog::on_slider2_valueChanged(int value) { 48 | set_text(ui->l_slider2, to_string(value)); 49 | cb_changed(); 50 | } 51 | 52 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/xavna_mock_ui_dialog.H: -------------------------------------------------------------------------------- 1 | #ifndef MAINWINDOW_H 2 | #define MAINWINDOW_H 3 | 4 | #include 5 | #include "xavna_mock_ui.H" 6 | namespace Ui { 7 | class xavna_mock_ui_dialog; 8 | } 9 | 10 | class xavna_mock_ui_dialog : public QMainWindow 11 | { 12 | Q_OBJECT 13 | 14 | public: 15 | explicit xavna_mock_ui_dialog(QWidget *parent = 0); 16 | ~xavna_mock_ui_dialog(); 17 | xavna_ui_changed_cb cb; 18 | 19 | private slots: 20 | void cb_changed(); 21 | 22 | 23 | void on_slider2_valueChanged(int value); 24 | 25 | void on_slider1_valueChanged(int value); 26 | 27 | private: 28 | Ui::xavna_mock_ui_dialog *ui; 29 | }; 30 | 31 | #endif // MAINWINDOW_H 32 | -------------------------------------------------------------------------------- /libxavna/xavna_mock_ui/xavna_mock_ui_global.h: -------------------------------------------------------------------------------- 1 | #ifndef XAVNA_MOCK_UI_GLOBAL_H 2 | #define XAVNA_MOCK_UI_GLOBAL_H 3 | 4 | #include 5 | 6 | #if defined(XAVNA_MOCK_UI_LIBRARY) 7 | # define XAVNA_MOCK_UISHARED_EXPORT Q_DECL_EXPORT 8 | #else 9 | # define XAVNA_MOCK_UISHARED_EXPORT Q_DECL_IMPORT 10 | #endif 11 | 12 | #endif // XAVNA_MOCK_UI_GLOBAL_H 13 | -------------------------------------------------------------------------------- /pcb/bb_amp.asc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pcb/bb_amp.asc -------------------------------------------------------------------------------- /pcb/bb_amp_2.asc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pcb/bb_amp_2.asc -------------------------------------------------------------------------------- /pcb/fpga_pins.xcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pcb/fpga_pins.xcf -------------------------------------------------------------------------------- /pcb/main.gsch2pcb: -------------------------------------------------------------------------------- 1 | schematics main.sch 2 | output-name main 3 | -------------------------------------------------------------------------------- /pcb/main2.gsch2pcb: -------------------------------------------------------------------------------- 1 | schematics main2.sch 2 | output-name main2 3 | -------------------------------------------------------------------------------- /pcb/main2.mapping.csv: -------------------------------------------------------------------------------- 1 | device footprint value expression priority 2 | BGS14GA14 * * 'BGS14GA14E6327XTSA1' 3 | INDUCTOR 0603 fb 'FBMH1608HM601-T' 4 | INDUCTOR 0805 15n 'CE201210-15NJ' 5 | INDUCTOR 0805 2.2u 'CV201210-2R2K' 6 | INDUCTOR 0805 4.7u 'CV201210-4R7K' 7 | LED 0603 blue '' 8 | LED 0603 green '' 9 | LED 0603 red '' 10 | LP0603A0947 lp0603 * 'LP0603A0947ANTR' 11 | LP0603A2140 lp0603 * 'LP0603A2140ANTR' 12 | LT1819 SO8 * 'LT1819CS8#PBF' 13 | USB3343 QFN24_4_EP * 'USB3343-CP-TR' 14 | W25Q32FV custom_so8 * ('W25Q32JVSSIQ', 'W25Q32JV', 'SO8', value) 15 | XC6SLX9 LQFP144_20 * 'XC6SLX9-2TQG144C' 16 | ad9200 SSOP28 * 'AD9200JRSZ' 17 | adf4350 custom_qfn32 * ('ADF4350BCPZ', 'adf4350', 'QFN32_EP', value) 18 | ap3419 SOT26 * 'AP3429KTTR-G1' 19 | cmy210 custom_cmy211 * ('CMY210', 'cmy210', 'SOT23-6', value) 20 | nc7s04 SC70_5 * 'NC7S04P5X' 21 | pe4312 QFN20_4_EP * 'PE4312MLBA-Z' 22 | si53365 TSSOP16 * 'SI53365-B-GT' 23 | tcxo3225 tcxo3225 * ('ASVTX-11-121-19.200MHZ-T', 'tcxo', '3225', value) 24 | trf37a75 trf37a75 * 'TRF37A75IDSGR' 25 | terminal custom_shield1 * 'DNI' 26 | RESISTOR 0603 1.8 'RC0603JR-071R8L' -1 27 | RESISTOR 0603 36 'RC0603FR-0736RL' -1 28 | RESISTOR 0603 39 'RC0603FR-0739RL' -1 29 | RESISTOR 0603 8.06k 'RC0603FR-078K06L' -1 30 | RESISTOR 0603 36 findResistor(device,footprint,value,'1%') 31 | RESISTOR 0603 39 findResistor(device,footprint,value,'1%') 32 | RESISTOR 0603 8.06k findResistor(device,footprint,value,'1%') 33 | RESISTOR 0603 66 findResistor(device,footprint,value,'1%') 34 | RESISTOR 0603 270 findResistor(device,footprint,value,'1%') 35 | RESISTOR 0603 100 findResistor(device,footprint,value,'1%') 36 | RESISTOR 0603 50 findResistor(device,footprint,'49.9','1%') 37 | INDUCTOR mcw-0630 10uH ('06030 (0630) 10uH 20% 4A', 'INDUCTOR', '06030', '10u') 38 | CONNECTOR_5 custom_microusb1 * ('10118193-0001LF', 'CONNECTOR', 'micro usb', '') 39 | * custom_sma4 * ('CON-SMA-EDGE-S', 'CONNECTOR', 'SMA','') 40 | CAPACITOR * * findCapacitor(device,footprint,value) 41 | RESISTOR * * findResistor(device,footprint,value) 42 | CAPACITOR * * findComponentElecrow(device,footprint,value) -1 43 | RESISTOR * * findComponentElecrow(device,footprint,value) -1 44 | -------------------------------------------------------------------------------- /pcb/main2_2.gsch2pcb: -------------------------------------------------------------------------------- 1 | schematics main2_2.sch 2 | output-name main2_2 3 | -------------------------------------------------------------------------------- /pcb/main2_2.mapping.csv: -------------------------------------------------------------------------------- 1 | device footprint value expression priority 2 | BGS14GA14 * * 'BGS14GA14E6327XTSA1' 3 | INDUCTOR 0603_0805 fb ('FBMH1608HM601-T', device, '0805', value) 4 | INDUCTOR 0603 rffb 'FBMH1608HM601-T' 5 | INDUCTOR 0805 15n 'CE201210-15NJ' 6 | INDUCTOR 0805 2.2u 'CV201210-2R2K' 7 | INDUCTOR 0805 4.7u 'CV201210-4R7K' 8 | LED 0603 blue '' 9 | LED 0603 green '' 10 | LED 0603 red '' 11 | LP0603A0947 lp0603 * 'LP0603A0947ANTR' 12 | LP0603A2140 lp0603 * 'LP0603A2140ANTR' 13 | LT1819 SO8 * 'LT1819CS8#PBF' 14 | USB3343 QFN24_4_EP * 'USB3343-CP-TR' 15 | W25Q32FV custom_so8 * ('W25Q32JVSSIQ', 'W25Q32JV', 'SO8', value) 16 | XC6SLX9 LQFP144_20 * 'XC6SLX9-2TQG144C' 17 | ad9200 SSOP28 * 'AD9200JRSZ' 18 | adf4350 custom_qfn32 * ('ADF4350BCPZ', 'adf4350', 'QFN32_EP', value) 19 | ap3419 SOT26 * 'AP3429KTTR-G1' 20 | cmy210 custom_cmy211 * ('CMY210', 'cmy210', 'SOT23-6', value) 21 | ad8342 * * 'AD8342ACPZ' 22 | nc7s04 SC70_5 * 'NC7S04P5X' 23 | pe4312 QFN20_4_EP * 'PE4312MLBA-Z' 24 | si53360 TSSOP16 * 'SI53360-B-GT' 25 | tcxo3225 tcxo3225 * ('ASVTX-11-121-19.200MHZ-T', 'tcxo', '3225', value) 26 | trf37a75 trf37a75 * 'TRF37A75IDSGR' 27 | terminal custom_shield1 * 'DNI' 28 | RESISTOR 0603 1.8 'RC0603JR-071R8L' -1 29 | RESISTOR 0603 36 'RC0603FR-0736RL' -1 30 | RESISTOR 0603 39 'RC0603FR-0739RL' -1 31 | RESISTOR 0603 8.06k 'RC0603FR-078K06L' -1 32 | RESISTOR 0603 36 findResistor(device,footprint,value,'1%') 33 | RESISTOR 0603 39 findResistor(device,footprint,value,'1%') 34 | RESISTOR 0603 8.06k findResistor(device,footprint,value,'1%') 35 | RESISTOR 0603 66 findResistor(device,footprint,value,'1%') 36 | RESISTOR 0603 270 findResistor(device,footprint,value,'1%') 37 | RESISTOR 0603 100 findResistor(device,footprint,value,'1%') 38 | RESISTOR 0603 50 findResistor(device,footprint,'49.9','1%') 39 | INDUCTOR mcw-0630 10uH ('06030 (0630) 10uH 20% 4A', 'INDUCTOR', '06030', '10u') 40 | CONNECTOR_5 custom_microusb1 * ('10118193-0001LF', 'CONNECTOR', 'micro usb', '') 41 | CONNECTOR_5 connector5 * 'DNI' 42 | connector9 connector9 * 'DNI' 43 | * adhoc * 'DNI' 44 | * custom_pad1 * 'DNI' 45 | * custom_sma4 * ('CON-SMA-EDGE-S', 'CONNECTOR', 'SMA','') 46 | CAPACITOR * * findCapacitor(device,footprint,value) 47 | RESISTOR * * findResistor(device,footprint,value) 48 | CAPACITOR * * findComponentElecrow(device,footprint,value) -1 49 | RESISTOR * * findComponentElecrow(device,footprint,value) -1 50 | -------------------------------------------------------------------------------- /pcb/main3.gsch2pcb: -------------------------------------------------------------------------------- 1 | schematics main3.sch 2 | output-name main3 3 | -------------------------------------------------------------------------------- /pcb/main3_2.gsch2pcb: -------------------------------------------------------------------------------- 1 | schematics main3_2.sch 2 | output-name main3_2 3 | -------------------------------------------------------------------------------- /pcb/packages/0402.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["hidename" "" "a" "" 8.6000mm 7.1000mm 0.0500mm 0.0500mm 0 100 ""] 3 | ( 4 | Pad[0.4500mm 0.0000 0.5500mm 0.0000 0.5000mm 20.00mil 0.5580mm "" "1" "square,edge2"] 5 | Pad[-0.5500mm 0.0000 -0.4500mm 0.0000 0.5000mm 0.5080mm 0.5580mm "" "2" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/0402_s.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 21.3000mm 74.7000mm 1.1000mm 1.2000mm 2 54 ""] 3 | ( 4 | Pad[-0.4500mm -0.0500mm -0.4500mm -0.0500mm 0.5000mm 0.6000mm 0.5412mm "" "2" "square"] 5 | Pad[0.4500mm -0.0500mm 0.4500mm -0.0500mm 0.5000mm 0.6000mm 0.5412mm "" "1" "square,edge2"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/0402_s.pcb: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 21.3000mm 74.7000mm 1.1000mm 1.2000mm 2 54 ""] 3 | ( 4 | Pad[-0.4500mm -0.0500mm -0.4500mm -0.0500mm 0.5000mm 0.6000mm 0.5412mm "" "2" "square"] 5 | Pad[0.4500mm -0.0500mm 0.4500mm -0.0500mm 0.5000mm 0.6000mm 0.5412mm "" "1" "square,edge2"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/0603.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 2.8000mm 1.3000mm 1.2000mm -0.1000mm 2 100 ""] 3 | ( 4 | Pad[0.7500mm -0.0500mm 0.7500mm 0.0500mm 0.9000mm 0.6000mm 1.0000mm "" "1" "square"] 5 | Pad[-0.7500mm -0.0500mm -0.7500mm 0.0500mm 0.9000mm 0.6000mm 1.0000mm "" "2" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/0603_0805.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 101.4000mm 20.7000mm -0.8000mm -2.0000mm 0 77 ""] 3 | ( 4 | Pad[0.8000mm -0.2000mm 0.8000mm 0.1000mm 1.0000mm 0.6000mm 1.0460mm "" "1" "square"] 5 | Pad[-0.8000mm -0.2000mm -0.8000mm 0.1000mm 1.0000mm 0.6000mm 1.0460mm "" "2" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/0805.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 5.7000mm 2.1000mm -2.0000mm -1.0000mm 3 82 ""] 3 | ( 4 | Pad[1.0500mm -0.1500mm 1.0500mm 0.1500mm 1.3000mm 0.6000mm 1.4000mm "" "1" "square"] 5 | Pad[-1.0500mm -0.1500mm -1.0500mm 0.1500mm 1.3000mm 0.6000mm 1.4000mm "" "2" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/1211.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 5.0426mm 2.4574mm 0.0000 0.0000 3 100 ""] 3 | ( 4 | Pad[1.7500mm -0.7500mm 1.7500mm 0.7500mm 1.7000mm 20.00mil 1.9540mm "" "1" "square"] 5 | Pad[-1.7500mm -0.7500mm -1.7500mm 0.7500mm 1.7000mm 20.00mil 1.9540mm "" "2" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/MSOP10.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 15.2000mm 13.6000mm 0.0000 0.0000 1 100 ""] 3 | ( 4 | Pad[-1.0000mm 1.7500mm -1.0000mm 2.6500mm 0.2800mm 0.5000mm 0.3800mm "" "1" "square,edge2"] 5 | Pad[-0.5000mm 1.7500mm -0.5000mm 2.6500mm 0.2800mm 0.5000mm 0.3800mm "" "2" "square,edge2"] 6 | Pad[0.0000 1.7500mm 0.0000 2.6500mm 0.2800mm 0.5000mm 0.3800mm "" "3" "square,edge2"] 7 | Pad[0.5000mm 1.7500mm 0.5000mm 2.6500mm 0.2800mm 0.5000mm 0.3800mm "" "4" "square,edge2"] 8 | Pad[1.0000mm 1.7500mm 1.0000mm 2.6500mm 0.2800mm 0.5000mm 0.3800mm "" "5" "square,edge2"] 9 | Pad[-1.0000mm -2.6500mm -1.0000mm -1.7500mm 0.2800mm 0.5000mm 0.3800mm "" "10" "square"] 10 | Pad[-0.5000mm -2.6500mm -0.5000mm -1.7500mm 0.2800mm 0.5000mm 0.3800mm "" "9" "square"] 11 | Pad[0.0000 -2.6500mm 0.0000 -1.7500mm 0.2800mm 0.5000mm 0.3800mm "" "8" "square"] 12 | Pad[0.5000mm -2.6500mm 0.5000mm -1.7500mm 0.2800mm 0.5000mm 0.3800mm "" "7" "square"] 13 | Pad[1.0000mm -2.6500mm 1.0000mm -1.7500mm 0.2800mm 0.5000mm 0.3800mm "" "6" "square"] 14 | ElementLine [-1.5000mm 1.5000mm -2.0000mm 2.0000mm 0.2800mm] 15 | ElementLine [-1.5000mm 0.4000mm -1.5000mm 1.5000mm 0.2800mm] 16 | ElementLine [-1.5000mm -1.5000mm -1.5000mm -0.4000mm 0.2800mm] 17 | ElementLine [-1.5000mm 1.5000mm 1.5000mm 1.5000mm 0.2000mm] 18 | ElementLine [-1.5000mm -1.5000mm 1.5000mm -1.5000mm 0.2000mm] 19 | ElementLine [1.5000mm -1.5000mm 1.5000mm 1.5000mm 0.2000mm] 20 | ElementArc [-1.5000mm 0.0000 0.4000mm 0.4000mm 90 90 0.2800mm] 21 | ElementArc [-1.5000mm 0.0000 0.4000mm 0.4000mm 180 90 0.2800mm] 22 | 23 | ) 24 | -------------------------------------------------------------------------------- /pcb/packages/QFN16_3_EP.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 50.1000mm 16.1000mm 0.0000 0.0000 3 100 ""] 3 | ( 4 | Pad[-1.9000mm -0.7500mm -46.85mil -29.52mil 11.02mil 20.00mil 31.02mil "" "1" "square"] 5 | Pad[-1.9000mm -0.2500mm -46.85mil -9.84mil 11.02mil 20.00mil 31.02mil "" "2" "square"] 6 | Pad[-1.9000mm 0.2500mm -46.85mil 9.84mil 11.02mil 20.00mil 31.02mil "" "3" "square,edge2"] 7 | Pad[-1.9000mm 0.7500mm -46.85mil 29.52mil 11.02mil 20.00mil 31.02mil "" "4" "square,edge2"] 8 | Pad[-0.7500mm 1.9000mm -29.52mil 46.85mil 11.02mil 20.00mil 31.02mil "" "5" "square,edge2"] 9 | Pad[-0.2500mm 1.9000mm -9.84mil 46.85mil 11.02mil 20.00mil 31.02mil "" "6" "square,edge2"] 10 | Pad[9.84mil 46.85mil 0.2500mm 1.9000mm 11.02mil 20.00mil 31.02mil "" "7" "square,edge2"] 11 | Pad[29.52mil 46.85mil 0.7500mm 1.9000mm 11.02mil 20.00mil 31.02mil "" "8" "square,edge2"] 12 | Pad[46.85mil 29.52mil 1.9000mm 0.7500mm 11.02mil 20.00mil 31.02mil "" "9" "square,edge2"] 13 | Pad[46.85mil 9.84mil 1.9000mm 0.2500mm 11.02mil 20.00mil 31.02mil "" "10" "square,edge2"] 14 | Pad[46.85mil -9.84mil 1.9000mm -0.2500mm 11.02mil 20.00mil 31.02mil "" "11" "square"] 15 | Pad[46.85mil -29.52mil 1.9000mm -0.7500mm 11.02mil 20.00mil 31.02mil "" "12" "square"] 16 | Pad[29.52mil -46.85mil 0.7500mm -1.9000mm 11.02mil 20.00mil 31.02mil "" "13" "square"] 17 | Pad[9.84mil -46.85mil 0.2500mm -1.9000mm 11.02mil 20.00mil 31.02mil "" "14" "square"] 18 | Pad[-0.2500mm -1.9000mm -9.84mil -46.85mil 11.02mil 20.00mil 31.02mil "" "15" "square"] 19 | Pad[-0.7500mm -1.9000mm -29.52mil -46.85mil 11.02mil 20.00mil 31.02mil "" "16" "square"] 20 | Pad[0.0000 0.0000 0.0000 0.0000 59.05mil 0.0000 59.05mil "" "17" "square,edge2"] 21 | ElementLine [2.2000mm -2.2000mm 2.2000mm 2.2000mm 10.00mil] 22 | ElementLine [-2.2000mm -2.2000mm 2.2000mm -2.2000mm 10.00mil] 23 | ElementLine [-2.2000mm -2.2000mm -2.2000mm 2.2076mm 10.00mil] 24 | ElementLine [-2.2000mm 2.2000mm 2.2000mm 2.2000mm 10.00mil] 25 | ElementLine [-2.2000mm -2.2000mm -2.5810mm -2.5810mm 10.00mil] 26 | 27 | ) 28 | -------------------------------------------------------------------------------- /pcb/packages/QFN16_3_EP_ADA4932.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 59.5000mm 37.4000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[1.2500mm -0.2500mm 1.8500mm -0.2500mm 0.2800mm 0.6000mm 0.3300mm "" "11" "square,edge2"] 5 | Pad[1.2500mm 0.2500mm 1.8500mm 0.2500mm 0.2800mm 0.6000mm 0.3300mm "" "10" "square,edge2"] 6 | Pad[1.2500mm 0.7500mm 1.8500mm 0.7500mm 0.2800mm 0.6000mm 0.3300mm "" "9" "square,edge2"] 7 | Pad[1.2500mm -0.7500mm 1.8500mm -0.7500mm 0.2800mm 0.6000mm 0.3300mm "" "12" "square,edge2"] 8 | Pad[0.2500mm -1.8500mm 0.2500mm -1.2500mm 0.2800mm 0.6000mm 0.3300mm "" "14" "square"] 9 | Pad[-0.2500mm -1.8500mm -0.2500mm -1.2500mm 0.2800mm 0.6000mm 0.3300mm "" "15" "square"] 10 | Pad[-0.7500mm -1.8500mm -0.7500mm -1.2500mm 0.2800mm 0.6000mm 0.3300mm "" "16" "square"] 11 | Pad[0.7500mm -1.8500mm 0.7500mm -1.2500mm 0.2800mm 0.6000mm 0.3300mm "" "13" "square"] 12 | Pad[0.2500mm 1.2500mm 0.2500mm 1.8500mm 0.2800mm 0.6000mm 0.3300mm "" "7" "square,edge2"] 13 | Pad[-0.2500mm 1.2500mm -0.2500mm 1.8500mm 0.2800mm 0.6000mm 0.3300mm "" "6" "square,edge2"] 14 | Pad[-0.7500mm 1.2500mm -0.7500mm 1.8500mm 0.2800mm 0.6000mm 0.3300mm "" "5" "square,edge2"] 15 | Pad[0.7500mm 1.2500mm 0.7500mm 1.8500mm 0.2800mm 0.6000mm 0.3300mm "" "8" "square,edge2"] 16 | Pad[-1.8500mm -0.2500mm -1.2500mm -0.2500mm 0.2800mm 0.6000mm 0.3300mm "" "2" "square"] 17 | Pad[-1.8500mm 0.2500mm -1.2500mm 0.2500mm 0.2800mm 0.6000mm 0.3300mm "" "3" "square"] 18 | Pad[-1.8500mm 0.7500mm -1.2500mm 0.7500mm 0.2800mm 0.6000mm 0.3300mm "" "4" "square"] 19 | Pad[-1.8500mm -0.7500mm -1.2500mm -0.7500mm 0.2800mm 0.6000mm 0.3300mm "" "1" "square"] 20 | Pad[0.0000 0.0000 0.0000 0.0000 1.3000mm 0.6000mm 1.3500mm "" "17" "square"] 21 | ElementLine [-1.5000mm -1.5000mm -1.1500mm -1.5000mm 0.2000mm] 22 | ElementLine [-1.5000mm -1.5000mm -1.5000mm -1.1500mm 0.2000mm] 23 | ElementLine [1.5000mm -1.5000mm 1.5000mm -1.1500mm 0.2000mm] 24 | ElementLine [1.1500mm -1.5000mm 1.5000mm -1.5000mm 0.2000mm] 25 | ElementLine [1.1500mm 1.5000mm 1.5000mm 1.5000mm 0.2000mm] 26 | ElementLine [1.5000mm 1.1500mm 1.5000mm 1.5000mm 0.2000mm] 27 | ElementLine [-1.5000mm 1.1500mm -1.5000mm 1.5000mm 0.2000mm] 28 | ElementLine [-1.5000mm 1.5000mm -1.1500mm 1.5000mm 0.2000mm] 29 | ElementLine [-1.5000mm -1.5000mm -1.9000mm -1.9000mm 0.2000mm] 30 | 31 | ) 32 | -------------------------------------------------------------------------------- /pcb/packages/QFN16_4_EP.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 96.2000mm 93.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-2.3750mm 0.9750mm -1.5250mm 0.9750mm 0.3500mm 0.4000mm 0.4500mm "" "4" "square"] 5 | Pad[-2.3750mm 0.3250mm -1.5250mm 0.3250mm 0.3500mm 0.4000mm 0.4500mm "" "3" "square"] 6 | Pad[-2.3750mm -0.3250mm -1.5250mm -0.3250mm 0.3500mm 0.4000mm 0.4500mm "" "2" "square"] 7 | Pad[-2.3750mm -0.9750mm -1.5250mm -0.9750mm 0.3500mm 0.4000mm 0.4500mm "" "1" "square"] 8 | Pad[1.5250mm 0.9750mm 2.3750mm 0.9750mm 0.3500mm 0.4000mm 0.4500mm "" "9" "square,edge2"] 9 | Pad[1.5250mm 0.3250mm 2.3750mm 0.3250mm 0.3500mm 0.4000mm 0.4500mm "" "10" "square,edge2"] 10 | Pad[1.5250mm -0.3250mm 2.3750mm -0.3250mm 0.3500mm 0.4000mm 0.4500mm "" "11" "square,edge2"] 11 | Pad[1.5250mm -0.9750mm 2.3750mm -0.9750mm 0.3500mm 0.4000mm 0.4500mm "" "12" "square,edge2"] 12 | Pad[0.9750mm 1.5250mm 0.9750mm 2.3750mm 0.3500mm 0.4000mm 0.4500mm "" "8" "square,edge2"] 13 | Pad[0.3250mm 1.5250mm 0.3250mm 2.3750mm 0.3500mm 0.4000mm 0.4500mm "" "7" "square,edge2"] 14 | Pad[-0.3250mm 1.5250mm -0.3250mm 2.3750mm 0.3500mm 0.4000mm 0.4500mm "" "6" "square,edge2"] 15 | Pad[-0.9750mm 1.5250mm -0.9750mm 2.3750mm 0.3500mm 0.4000mm 0.4500mm "" "5" "square,edge2"] 16 | Pad[0.9750mm -2.3750mm 0.9750mm -1.5250mm 0.3500mm 0.4000mm 0.4500mm "" "13" "square"] 17 | Pad[0.3250mm -2.3750mm 0.3250mm -1.5250mm 0.3500mm 0.4000mm 0.4500mm "" "14" "square"] 18 | Pad[-0.3250mm -2.3750mm -0.3250mm -1.5250mm 0.3500mm 0.4000mm 0.4500mm "" "15" "square"] 19 | Pad[-0.9750mm -2.3750mm -0.9750mm -1.5250mm 0.3500mm 0.4000mm 0.4500mm "" "16" "square"] 20 | Pad[0.0000 0.0000 0.0000 0.0000 2.1000mm 0.4000mm 2.2000mm "" "17" "square,edge2"] 21 | ElementLine [-2.0000mm -2.0000mm -1.5000mm -2.0000mm 0.2500mm] 22 | ElementLine [-2.0000mm -2.0000mm -2.0000mm -1.5000mm 0.2500mm] 23 | ElementLine [2.0000mm -2.0000mm 2.0000mm -1.5000mm 0.2500mm] 24 | ElementLine [1.5000mm -2.0000mm 2.0000mm -2.0000mm 0.2500mm] 25 | ElementLine [1.5000mm 2.0000mm 2.0000mm 2.0000mm 0.2500mm] 26 | ElementLine [2.0000mm 1.5000mm 2.0000mm 2.0000mm 0.2500mm] 27 | ElementLine [-2.0000mm 1.5000mm -2.0000mm 2.0000mm 0.2500mm] 28 | ElementLine [-2.0000mm 2.0000mm -1.5000mm 2.0000mm 0.2500mm] 29 | ElementLine [-2.0000mm -2.0000mm -2.8000mm -2.8000mm 0.2500mm] 30 | 31 | ) 32 | -------------------------------------------------------------------------------- /pcb/packages/SC70_5.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 73.8000mm 19.7000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[0.5460mm 0.7000mm 1.0540mm 0.7000mm 15.00mil 30.00mil 19.00mil "" "4" "square,edge2"] 5 | Pad[0.5460mm -0.5954mm 1.0540mm -0.5954mm 15.00mil 30.00mil 19.00mil "" "5" "square,edge2"] 6 | Pad[-1.2320mm -0.5954mm -0.7240mm -0.5954mm 15.00mil 30.00mil 19.00mil "" "1" "square"] 7 | Pad[-1.2320mm 0.0396mm -0.7240mm 0.0396mm 15.00mil 30.00mil 19.00mil "" "2" "square"] 8 | Pad[-1.2320mm 0.7000mm -0.7240mm 0.7000mm 15.00mil 30.00mil 19.00mil "" "3" "square"] 9 | ElementLine [-1.5876mm 1.0556mm 1.4350mm 1.0556mm 10.00mil] 10 | ElementLine [1.4350mm -0.9764mm 1.4350mm 1.0556mm 10.00mil] 11 | ElementLine [-1.5876mm -0.9764mm 1.4350mm -0.9764mm 10.00mil] 12 | ElementLine [-1.5876mm -0.9764mm -1.5876mm 1.0556mm 10.00mil] 13 | 14 | ) 15 | -------------------------------------------------------------------------------- /pcb/packages/SO8.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "Small outline package, narrow (150mil)" "" "SO8" 0.0000 0.0000 -60.00mil 20.00mil 1 100 ""] 3 | ( 4 | Pad[-75.00mil 70.00mil -75.00mil 135.00mil 20.00mil 10.00mil 30.00mil "1" "1" "square,edge2"] 5 | Pad[-25.00mil 70.00mil -25.00mil 135.00mil 20.00mil 10.00mil 30.00mil "2" "2" "square,edge2"] 6 | Pad[25.00mil 70.00mil 25.00mil 135.00mil 20.00mil 10.00mil 30.00mil "3" "3" "square,edge2"] 7 | Pad[75.00mil 70.00mil 75.00mil 135.00mil 20.00mil 10.00mil 30.00mil "4" "4" "square,edge2"] 8 | Pad[75.00mil -135.00mil 75.00mil -70.00mil 20.00mil 10.00mil 30.00mil "5" "5" "square"] 9 | Pad[25.00mil -135.00mil 25.00mil -70.00mil 20.00mil 10.00mil 30.00mil "6" "6" "square"] 10 | Pad[-25.00mil -135.00mil -25.00mil -70.00mil 20.00mil 10.00mil 30.00mil "7" "7" "square"] 11 | Pad[-75.00mil -135.00mil -75.00mil -70.00mil 20.00mil 10.00mil 30.00mil "8" "8" "square"] 12 | ElementLine [-95.00mil 155.00mil 95.00mil 155.00mil 10.00mil] 13 | ElementLine [95.00mil -155.00mil 95.00mil 155.00mil 10.00mil] 14 | ElementLine [-95.00mil -155.00mil 95.00mil -155.00mil 10.00mil] 15 | ElementLine [-95.00mil 25.00mil -95.00mil 155.00mil 10.00mil] 16 | ElementLine [-95.00mil -155.00mil -95.00mil -25.00mil 10.00mil] 17 | ElementArc [-95.00mil 0.0000 25.00mil 25.00mil 90 180 10.00mil] 18 | 19 | ) 20 | -------------------------------------------------------------------------------- /pcb/packages/SO8W.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "Small outline package, wide (300mil)" "" "SO8W" 0.0000 0.0000 -20.00mil -60.00mil 0 100 ""] 3 | ( 4 | Pad[-210.00mil -75.00mil -150.00mil -75.00mil 20.00mil 10.00mil 30.00mil "1" "1" "square"] 5 | Pad[-210.00mil -25.00mil -150.00mil -25.00mil 20.00mil 10.00mil 30.00mil "2" "2" "square"] 6 | Pad[-210.00mil 25.00mil -150.00mil 25.00mil 20.00mil 10.00mil 30.00mil "3" "3" "square"] 7 | Pad[-210.00mil 75.00mil -150.00mil 75.00mil 20.00mil 10.00mil 30.00mil "4" "4" "square"] 8 | Pad[150.00mil 75.00mil 210.00mil 75.00mil 20.00mil 10.00mil 30.00mil "5" "5" "square,edge2"] 9 | Pad[150.00mil 25.00mil 210.00mil 25.00mil 20.00mil 10.00mil 30.00mil "6" "6" "square,edge2"] 10 | Pad[150.00mil -25.00mil 210.00mil -25.00mil 20.00mil 10.00mil 30.00mil "7" "7" "square,edge2"] 11 | Pad[150.00mil -75.00mil 210.00mil -75.00mil 20.00mil 10.00mil 30.00mil "8" "8" "square,edge2"] 12 | ElementLine [-230.00mil -95.00mil -230.00mil 95.00mil 10.00mil] 13 | ElementLine [-230.00mil 95.00mil 230.00mil 95.00mil 10.00mil] 14 | ElementLine [230.00mil 95.00mil 230.00mil -95.00mil 10.00mil] 15 | ElementLine [-230.00mil -95.00mil -25.00mil -95.00mil 10.00mil] 16 | ElementLine [230.00mil -95.00mil 25.00mil -95.00mil 10.00mil] 17 | ElementArc [0.0000 -95.00mil 25.00mil 25.00mil 0 180 10.00mil] 18 | 19 | ) 20 | -------------------------------------------------------------------------------- /pcb/packages/SOT26.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 41.0000mm 10.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-1.0000mm 0.7968mm -1.0000mm 1.2032mm 24.00mil 30.00mil 54.00mil "" "1" "square,edge2"] 5 | Pad[-0.0094mm 0.7968mm -0.0094mm 1.2032mm 24.00mil 30.00mil 54.00mil "" "2" "square,edge2"] 6 | Pad[0.9812mm 0.7968mm 0.9812mm 1.2032mm 24.00mil 30.00mil 54.00mil "" "3" "square,edge2"] 7 | Pad[0.9812mm -1.2860mm 0.9812mm -0.8796mm 24.00mil 30.00mil 54.00mil "" "4" "square"] 8 | Pad[-0.0094mm -1.2860mm -0.0094mm -0.8796mm 24.00mil 30.00mil 54.00mil "" "5" "square"] 9 | Pad[-1.0000mm -1.2860mm -1.0000mm -0.8796mm 24.00mil 30.00mil 54.00mil "" "6" "square"] 10 | ElementLine [-1.5080mm -1.7940mm -1.5080mm 1.7366mm 10.00mil] 11 | ElementLine [-1.5080mm 1.7366mm 1.4892mm 1.7366mm 10.00mil] 12 | ElementLine [1.4892mm -1.7940mm 1.4892mm 1.7366mm 10.00mil] 13 | ElementLine [-1.5080mm -1.7940mm 1.4892mm -1.7940mm 10.00mil] 14 | 15 | ) 16 | -------------------------------------------------------------------------------- /pcb/packages/TSSOP16.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "Thin shrink small outline package, standard (4.4mm)" "" "TSSOP16" 0.0000 0.0000 -20.00mil -60.00mil 0 100 ""] 3 | ( 4 | Pad[-139.17mil -89.56mil -93.11mil -89.56mil 12.99mil 10.00mil 22.99mil "1" "1" "square"] 5 | Pad[-139.17mil -63.97mil -93.11mil -63.97mil 12.99mil 10.00mil 22.99mil "2" "2" "square"] 6 | Pad[-139.17mil -38.38mil -93.11mil -38.38mil 12.99mil 10.00mil 22.99mil "3" "3" "square"] 7 | Pad[-139.17mil -12.79mil -93.11mil -12.79mil 12.99mil 10.00mil 22.99mil "4" "4" "square"] 8 | Pad[-139.17mil 12.79mil -93.11mil 12.79mil 12.99mil 10.00mil 22.99mil "5" "5" "square"] 9 | Pad[-139.17mil 38.38mil -93.11mil 38.38mil 12.99mil 10.00mil 22.99mil "6" "6" "square"] 10 | Pad[-139.17mil 63.97mil -93.11mil 63.97mil 12.99mil 10.00mil 22.99mil "7" "7" "square"] 11 | Pad[-139.17mil 89.56mil -93.11mil 89.56mil 12.99mil 10.00mil 22.99mil "8" "8" "square"] 12 | Pad[93.11mil 89.56mil 139.17mil 89.56mil 12.99mil 10.00mil 22.99mil "9" "9" "square,edge2"] 13 | Pad[93.11mil 63.97mil 139.17mil 63.97mil 12.99mil 10.00mil 22.99mil "10" "10" "square,edge2"] 14 | Pad[93.11mil 38.38mil 139.17mil 38.38mil 12.99mil 10.00mil 22.99mil "11" "11" "square,edge2"] 15 | Pad[93.11mil 12.79mil 139.17mil 12.79mil 12.99mil 10.00mil 22.99mil "12" "12" "square,edge2"] 16 | Pad[93.11mil -12.79mil 139.17mil -12.79mil 12.99mil 10.00mil 22.99mil "13" "13" "square,edge2"] 17 | Pad[93.11mil -38.38mil 139.17mil -38.38mil 12.99mil 10.00mil 22.99mil "14" "14" "square,edge2"] 18 | Pad[93.11mil -63.97mil 139.17mil -63.97mil 12.99mil 10.00mil 22.99mil "15" "15" "square,edge2"] 19 | Pad[93.11mil -89.56mil 139.17mil -89.56mil 12.99mil 10.00mil 22.99mil "16" "16" "square,edge2"] 20 | ElementLine [-155.66mil -106.06mil -155.66mil 106.06mil 10.00mil] 21 | ElementLine [-155.66mil 106.06mil 155.66mil 106.06mil 10.00mil] 22 | ElementLine [155.66mil 106.06mil 155.66mil -106.06mil 10.00mil] 23 | ElementLine [-155.66mil -106.06mil -25.00mil -106.06mil 10.00mil] 24 | ElementLine [155.66mil -106.06mil 25.00mil -106.06mil 10.00mil] 25 | ElementArc [0.0000 -106.06mil 25.00mil 25.00mil 0 180 10.00mil] 26 | 27 | ) 28 | -------------------------------------------------------------------------------- /pcb/packages/bga_1.0_25.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 100.5000mm 126.8000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[0.2000mm 0.2000mm 0.2000mm 0.2000mm 0.4000mm 0.6000mm 1.0000mm "" "A1" ""] 5 | Pad[1.2000mm 0.2000mm 1.2000mm 0.2000mm 0.4000mm 0.6000mm 1.0000mm "" "A2" ""] 6 | Pad[2.2000mm 0.2000mm 2.2000mm 0.2000mm 0.4000mm 0.6000mm 1.0000mm "" "A3" ""] 7 | Pad[3.2000mm 0.2000mm 3.2000mm 0.2000mm 0.4000mm 0.6000mm 1.0000mm "" "A4" "edge2"] 8 | Pad[4.2000mm 0.2000mm 4.2000mm 0.2000mm 0.4000mm 0.6000mm 1.0000mm "" "A5" "edge2"] 9 | Pad[0.2000mm 1.2000mm 0.2000mm 1.2000mm 0.4000mm 0.6000mm 1.0000mm "" "B1" ""] 10 | Pad[1.2000mm 1.2000mm 1.2000mm 1.2000mm 0.4000mm 0.6000mm 1.0000mm "" "B2" ""] 11 | Pad[2.2000mm 1.2000mm 2.2000mm 1.2000mm 0.4000mm 0.6000mm 1.0000mm "" "B3" ""] 12 | Pad[3.2000mm 1.2000mm 3.2000mm 1.2000mm 0.4000mm 0.6000mm 1.0000mm "" "B4" "edge2"] 13 | Pad[4.2000mm 1.2000mm 4.2000mm 1.2000mm 0.4000mm 0.6000mm 1.0000mm "" "B5" "edge2"] 14 | Pad[0.2000mm 2.2000mm 0.2000mm 2.2000mm 0.4000mm 0.6000mm 1.0000mm "" "C1" ""] 15 | Pad[1.2000mm 2.2000mm 1.2000mm 2.2000mm 0.4000mm 0.6000mm 1.0000mm "" "C2" ""] 16 | Pad[2.2000mm 2.2000mm 2.2000mm 2.2000mm 0.4000mm 0.6000mm 1.0000mm "" "C3" ""] 17 | Pad[3.2000mm 2.2000mm 3.2000mm 2.2000mm 0.4000mm 0.6000mm 1.0000mm "" "C4" "edge2"] 18 | Pad[4.2000mm 2.2000mm 4.2000mm 2.2000mm 0.4000mm 0.6000mm 1.0000mm "" "C5" "edge2"] 19 | Pad[0.2000mm 3.2000mm 0.2000mm 3.2000mm 0.4000mm 0.6000mm 1.0000mm "" "D1" ""] 20 | Pad[1.2000mm 3.2000mm 1.2000mm 3.2000mm 0.4000mm 0.6000mm 1.0000mm "" "D2" ""] 21 | Pad[2.2000mm 3.2000mm 2.2000mm 3.2000mm 0.4000mm 0.6000mm 1.0000mm "" "D3" ""] 22 | Pad[3.2000mm 3.2000mm 3.2000mm 3.2000mm 0.4000mm 0.6000mm 1.0000mm "" "D4" "edge2"] 23 | Pad[4.2000mm 3.2000mm 4.2000mm 3.2000mm 0.4000mm 0.6000mm 1.0000mm "" "D5" "edge2"] 24 | Pad[0.2000mm 4.2000mm 0.2000mm 4.2000mm 0.4000mm 0.6000mm 1.0000mm "" "E1" ""] 25 | Pad[1.2000mm 4.2000mm 1.2000mm 4.2000mm 0.4000mm 0.6000mm 1.0000mm "" "E2" ""] 26 | Pad[2.2000mm 4.2000mm 2.2000mm 4.2000mm 0.4000mm 0.6000mm 1.0000mm "" "E3" ""] 27 | Pad[3.2000mm 4.2000mm 3.2000mm 4.2000mm 0.4000mm 0.6000mm 1.0000mm "" "E4" "edge2"] 28 | Pad[4.2000mm 4.2000mm 4.2000mm 4.2000mm 0.4000mm 0.6000mm 1.0000mm "" "E5" "edge2"] 29 | 30 | ) 31 | -------------------------------------------------------------------------------- /pcb/packages/bgs14ga14.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 16.9000mm 44.1000mm 0.0000 0.0000 1 100 ""] 3 | ( 4 | Pad[0.0000 0.0000 0.0000 0.0000 1.0000mm 0.6000mm 1.0500mm "" "0" "square"] 5 | Pad[-1.1250mm 0.6750mm -0.8750mm 0.6750mm 0.2500mm 0.6000mm 0.3000mm "" "4" "square"] 6 | Pad[-1.1250mm 0.2250mm -0.8750mm 0.2250mm 0.2500mm 0.6000mm 0.3000mm "" "3" "square"] 7 | Pad[-1.1250mm -0.2250mm -0.8750mm -0.2250mm 0.2500mm 0.6000mm 0.3000mm "" "2" "square"] 8 | Pad[-1.1250mm -0.6750mm -0.8750mm -0.6750mm 0.2500mm 0.6000mm 0.3000mm "" "1" "square"] 9 | Pad[0.8750mm 0.6750mm 1.1250mm 0.6750mm 0.2500mm 0.6000mm 0.3000mm "" "8" "square,edge2"] 10 | Pad[0.8750mm 0.2250mm 1.1250mm 0.2250mm 0.2500mm 0.6000mm 0.3000mm "" "9" "square,edge2"] 11 | Pad[0.8750mm -0.2250mm 1.1250mm -0.2250mm 0.2500mm 0.6000mm 0.3000mm "" "10" "square,edge2"] 12 | Pad[0.8750mm -0.6750mm 1.1250mm -0.6750mm 0.2500mm 0.6000mm 0.3000mm "" "11" "square,edge2"] 13 | Pad[-0.4000mm 0.8500mm -0.4000mm 1.1000mm 0.2000mm 0.6000mm 0.2500mm "" "5" "square,edge2"] 14 | Pad[0.4000mm 0.8500mm 0.4000mm 1.1000mm 0.2000mm 0.6000mm 0.2500mm "" "7" "square,edge2"] 15 | Pad[0.0000 0.8500mm 0.0000 1.1000mm 0.2000mm 0.6000mm 0.2500mm "" "6" "square,edge2"] 16 | Pad[-0.4000mm -1.1000mm -0.4000mm -0.8500mm 0.2000mm 0.6000mm 0.2500mm "" "14" "square"] 17 | Pad[0.4000mm -1.1000mm 0.4000mm -0.8500mm 0.2000mm 0.6000mm 0.2500mm "" "12" "square"] 18 | Pad[0.0000 -1.1000mm 0.0000 -0.8500mm 0.2000mm 0.6000mm 0.2500mm "" "13" "square"] 19 | ElementLine [-1.2000mm -1.0000mm -1.0000mm -1.0000mm 0.1500mm] 20 | ElementLine [-1.0000mm -1.2000mm -1.0000mm -1.0000mm 0.1500mm] 21 | 22 | ) 23 | -------------------------------------------------------------------------------- /pcb/packages/connector12_1_25mm.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 119.7000mm 73.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[3.3000mm -6.9000mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "1" ""] 5 | Pin[3.3000mm -5.6500mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "2" ""] 6 | Pin[3.3000mm -4.4000mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "3" ""] 7 | Pin[3.3000mm -3.1500mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "4" ""] 8 | Pin[3.3000mm -1.9000mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "5" ""] 9 | Pin[3.3000mm -0.6500mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "6" ""] 10 | Pin[3.3000mm 0.6000mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "7" ""] 11 | Pin[3.3000mm 1.8500mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "8" ""] 12 | Pin[3.3000mm 3.1000mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "9" ""] 13 | Pin[3.3000mm 4.3500mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "10" ""] 14 | Pin[3.3000mm 5.6000mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "11" ""] 15 | Pin[3.3000mm 6.8500mm 1.0000mm 0.6000mm 1.1024mm 0.6000mm "" "12" ""] 16 | ElementLine [4.2000mm 8.5000mm -3.7000mm 8.5000mm 0.3000mm] 17 | ElementLine [-3.7000mm -8.5000mm -3.7000mm 8.5000mm 0.3000mm] 18 | ElementLine [4.2000mm -8.5000mm 4.2000mm 8.5000mm 0.3000mm] 19 | ElementLine [4.2000mm -8.5000mm -3.7000mm -8.5000mm 0.3000mm] 20 | 21 | ) 22 | -------------------------------------------------------------------------------- /pcb/packages/connector5.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 78.8000mm 9.9000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[5.1000mm 0.0000 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "3" "edge2"] 5 | Pin[2.5500mm 0.0000 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "2" "edge2"] 6 | Pin[0.0000 0.0000 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "1" "edge2"] 7 | Pin[7.6000mm 0.0000 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "4" "edge2"] 8 | Pin[10.1500mm 0.0000 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "5" "edge2"] 9 | ElementLine [0.0000 50.00mil 400.00mil 50.00mil 10.00mil] 10 | ElementLine [0.0000 -50.00mil 400.00mil -50.00mil 10.00mil] 11 | ElementLine [50.00mil -50.00mil 50.00mil 50.00mil 10.00mil] 12 | ElementArc [0.0000 0.0000 50.00mil 50.00mil 270 180 10.00mil] 13 | ElementArc [400.00mil 0.0000 50.00mil 50.00mil 90 180 10.00mil] 14 | 15 | ) 16 | -------------------------------------------------------------------------------- /pcb/packages/connector9.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 133.9000mm 56.8000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[0.0000 0.0000 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "1" ""] 5 | Pin[0.0000 -2.5500mm 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "2" ""] 6 | Pin[0.0000 -5.1000mm 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "3" ""] 7 | Pin[0.0000 -7.6000mm 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "4" ""] 8 | Pin[0.0000 -10.1500mm 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "5" ""] 9 | Pin[0.0000 -500.00mil 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "6" ""] 10 | Pin[0.0000 -15.2500mm 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "7" ""] 11 | Pin[0.0000 -17.8000mm 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "8" ""] 12 | Pin[0.0000 -20.3000mm 1.7000mm 0.6000mm 1.8524mm 1.0000mm "" "9" ""] 13 | ElementLine [-50.00mil -50.00mil 50.00mil -50.00mil 10.00mil] 14 | ElementLine [-50.00mil -800.00mil -50.00mil 0.0000 0.3080mm] 15 | ElementLine [50.00mil -800.00mil 50.00mil 0.0000 0.3080mm] 16 | ElementArc [0.0000 -800.00mil 50.00mil 50.00mil 180 180 0.3080mm] 17 | ElementArc [0.0000 0.0000 50.00mil 50.00mil 0 180 0.3080mm] 18 | 19 | ) 20 | -------------------------------------------------------------------------------- /pcb/packages/custom_bead.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 25.3000mm 22.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-0.4000mm -0.2000mm -0.4000mm 0.2000mm 0.6000mm 20.00mil 0.8040mm "" "1" "square"] 5 | Pad[0.4000mm -0.2000mm 0.4000mm 0.2000mm 0.6000mm 20.00mil 0.8040mm "" "2" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/custom_button1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 68.7000mm 94.6000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-1.7500mm -3.3500mm -1.7500mm -3.3500mm 1.7000mm 0.4000mm 2.1000mm "" "0" "square"] 5 | Pad[1.7500mm -3.3500mm 1.7500mm -3.3500mm 1.7000mm 0.4000mm 2.1000mm "" "1" "square,edge2"] 6 | Pad[-1.7500mm 3.2500mm -1.7500mm 3.2500mm 1.7000mm 0.4000mm 2.1000mm "" "2" "square"] 7 | Pad[1.7500mm 3.2500mm 1.7500mm 3.2500mm 1.7000mm 0.4000mm 2.1000mm "" "3" "square,edge2"] 8 | ElementLine [-0.6000mm -4.1000mm 0.6000mm -4.1000mm 0.2800mm] 9 | ElementLine [-2.5000mm -2.1000mm -2.5000mm 2.0000mm 0.2800mm] 10 | ElementLine [2.5000mm -2.1000mm 2.5000mm 2.0000mm 0.2800mm] 11 | ElementLine [-0.6000mm 3.9000mm 0.6000mm 3.9000mm 0.2800mm] 12 | 13 | ) 14 | -------------------------------------------------------------------------------- /pcb/packages/custom_button2.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 10.7000mm 18.8000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-1.7500mm -3.1500mm -1.7500mm -3.1500mm 1.7000mm 0.4000mm 1.8460mm "" "1" "square"] 5 | Pad[1.7500mm -3.1500mm 1.7500mm -3.1500mm 1.7000mm 0.4000mm 1.8460mm "" "0" "square,edge2"] 6 | Pad[-1.7500mm 3.4500mm -1.7500mm 3.4500mm 1.7000mm 0.4000mm 1.7952mm "" "3" "square"] 7 | Pad[1.7500mm 3.4500mm 1.7500mm 3.4500mm 1.7000mm 0.4000mm 1.7952mm "" "2" "square,edge2"] 8 | ElementLine [-0.6000mm -3.9000mm 0.6000mm -3.9000mm 0.2800mm] 9 | ElementLine [-2.5000mm -1.9000mm -2.5000mm 2.2000mm 0.2800mm] 10 | ElementLine [2.5000mm -1.9000mm 2.5000mm 2.2000mm 0.2800mm] 11 | ElementLine [-0.6000mm 4.1000mm 0.6000mm 4.1000mm 0.2800mm] 12 | 13 | ) 14 | -------------------------------------------------------------------------------- /pcb/packages/custom_cdrh127.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 13.0000mm 90.0000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-1.0000mm 5.2500mm 1.0000mm 5.2500mm 3.5000mm 0.6000mm 3.8000mm "" "1" "square"] 5 | Pad[-1.0000mm -5.2500mm 1.0000mm -5.2500mm 3.5000mm 0.6000mm 3.8000mm "" "2" "square"] 6 | ElementLine [-6.0000mm 6.0000mm 6.0000mm 6.0000mm 0.4000mm] 7 | ElementLine [6.0000mm 6.0000mm 6.0000mm -6.0000mm 0.4000mm] 8 | ElementLine [6.0000mm -6.0000mm -6.0000mm -6.0000mm 0.4000mm] 9 | ElementLine [-6.0000mm -6.0000mm -6.0000mm 6.0000mm 0.4000mm] 10 | 11 | ) 12 | -------------------------------------------------------------------------------- /pcb/packages/custom_cmy211.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 19.2000mm 79.0000mm 0.0000 0.0000 3 100 ""] 3 | ( 4 | Pad[0.8500mm -0.9500mm 1.3500mm -0.9500mm 0.5000mm 0.6000mm 1.1000mm "" "6" "square,edge2"] 5 | Pad[1.0000mm 0.0000 1.2000mm 0.0000 0.8000mm 0.6000mm 1.4000mm "" "5" "square,edge2"] 6 | Pad[0.8500mm 0.9500mm 1.3500mm 0.9500mm 0.5000mm 0.6000mm 1.1000mm "" "4" "square,edge2"] 7 | Pad[-1.3500mm -0.9500mm -0.8500mm -0.9500mm 0.5000mm 0.6000mm 1.1000mm "" "1" "square"] 8 | Pad[-1.3500mm 0.0000 -0.8500mm 0.0000 0.5000mm 0.6000mm 1.1000mm "" "2" "square"] 9 | Pad[-1.3500mm 0.9500mm -0.8500mm 0.9500mm 0.5000mm 0.6000mm 1.1000mm "" "3" "square"] 10 | ElementLine [-1.7000mm -1.5000mm 1.6000mm -1.5000mm 0.2000mm] 11 | ElementLine [-1.7000mm -1.5000mm -1.7000mm 1.5000mm 0.2000mm] 12 | ElementLine [-1.7000mm 1.5000mm 1.6000mm 1.5000mm 0.2000mm] 13 | ElementLine [1.6000mm -1.5000mm 1.6000mm 1.5000mm 0.2000mm] 14 | 15 | ) 16 | -------------------------------------------------------------------------------- /pcb/packages/custom_coax1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 93.0000mm 46.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[0.0000 4.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 5 | Pin[1.3000mm 4.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 6 | Pin[-1.3000mm 4.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 7 | Pin[0.0000 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 8 | Pin[1.3000mm 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 9 | Pin[-1.3000mm 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 10 | Pin[0.0000 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 11 | Pin[1.3000mm 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 12 | Pin[-1.3000mm 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 13 | Pin[0.0000 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 14 | Pin[1.3000mm 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 15 | Pin[-1.3000mm 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 16 | Pad[0.0000 2.2000mm 0.0000 3.5000mm 4.0000mm 0.6000mm 4.6000mm "" "0" "square,edge2"] 17 | Pad[0.0000 -2.4000mm 0.0000 -1.2000mm 1.8000mm 0.6000mm 2.4000mm "" "1" "square"] 18 | Pad[0.0000 2.2000mm 0.0000 3.5000mm 4.0000mm 0.6000mm 4.6000mm "" "0" "onsolder,square,edge2"] 19 | 20 | ) 21 | -------------------------------------------------------------------------------- /pcb/packages/custom_coax1_1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 94.0000mm 17.0000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[0.0000 -3.9000mm 1.6000mm 0.6000mm 1.6500mm 1.0000mm "" "1" ""] 5 | Pad[0.0000 -0.5000mm 0.0000 0.5000mm 4.0000mm 0.6000mm 4.6000mm "" "0" "square,edge2"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/custom_coax1_2.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 56.0000mm 114.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[2.2500mm 0.2500mm 3.2500mm 0.2500mm 0.5000mm 0.6000mm 1.1000mm "" "1" "square,edge2"] 5 | Pad[0.0000 0.0000 0.0000 0.5000mm 3.0000mm 0.6000mm 3.6000mm "" "0" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/custom_coax2.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 34.4000mm 42.6000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[-1.3000mm 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 5 | Pin[1.3000mm 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 6 | Pin[0.0000 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 7 | Pin[-1.3000mm 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 8 | Pin[1.3000mm 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 9 | Pin[0.0000 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 10 | Pin[-1.3000mm 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 11 | Pin[1.3000mm 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 12 | Pin[0.0000 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 13 | Pin[-1.5500mm -2.7500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 14 | Pin[-1.5500mm -1.8500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 15 | Pin[-1.5500mm -0.9500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 16 | Pin[-1.5500mm -0.0500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 17 | Pin[1.5500mm -2.7500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 18 | Pin[1.5500mm -1.8500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 19 | Pin[1.5500mm -0.9500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 20 | Pin[1.5500mm -0.0500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 21 | Pad[0.0000 -2.6000mm 0.0000 -1.0000mm 1.4000mm 0.6000mm 2.0000mm "" "1" "square"] 22 | Pad[0.0000 2.2000mm 0.0000 2.2000mm 4.0000mm 0.6000mm 4.6000mm "" "0" "square"] 23 | Pad[-1.5000mm -2.8000mm -1.5000mm -0.3000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square"] 24 | Pad[1.5000mm -2.8000mm 1.5000mm -0.3000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square"] 25 | 26 | ) 27 | -------------------------------------------------------------------------------- /pcb/packages/custom_coax3.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 93.2000mm 42.7000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[1.5500mm -0.0500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 5 | Pin[1.5500mm -0.9500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 6 | Pin[1.5500mm -1.8500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 7 | Pin[1.5500mm -2.7500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 8 | Pin[-1.5500mm -0.0500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 9 | Pin[-1.5500mm -0.9500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 10 | Pin[-1.5500mm -1.8500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 11 | Pin[-1.5500mm -2.7500mm 1.1000mm 0.0000 1.2524mm 0.5000mm "" "0" ""] 12 | Pin[0.0000 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 13 | Pin[1.3000mm 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 14 | Pin[-1.3000mm 3.5000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 15 | Pin[0.0000 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 16 | Pin[1.3000mm 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 17 | Pin[-1.3000mm 2.2000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 18 | Pin[0.0000 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 19 | Pin[1.3000mm 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 20 | Pin[-1.3000mm 0.9000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" ""] 21 | Pad[1.5000mm -2.8000mm 1.5000mm -0.3000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square"] 22 | Pad[-1.5000mm -2.8000mm -1.5000mm -0.3000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square"] 23 | Pad[0.0000 -2.6000mm 0.0000 -1.0000mm 1.4000mm 0.6000mm 2.0000mm "" "1" "square"] 24 | Pad[-0.0500mm 2.1500mm 0.0500mm 2.1500mm 3.9000mm 0.6000mm 4.5000mm "" "0" "square"] 25 | 26 | ) 27 | -------------------------------------------------------------------------------- /pcb/packages/custom_coaxial1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 32.2000mm 10.2000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[0.0000 0.0000 1.4000mm 0.6000mm 1.5524mm 0.7000mm "" "1" ""] 5 | Pad[-0.7000mm -1.6000mm 0.7000mm -1.6000mm 1.2000mm 0.0000 1.8000mm "" "0" ""] 6 | Pad[1.6000mm -0.7000mm 1.6000mm 0.7000mm 1.2000mm 0.0000 1.8000mm "" "0" ""] 7 | Pad[0.7000mm -1.6000mm 1.6000mm -0.7000mm 1.2000mm 0.0000 1.8000mm "" "0" ""] 8 | Pad[-1.6000mm -0.7000mm -1.6000mm 0.7000mm 1.2000mm 0.0000 1.8000mm "" "0" ""] 9 | Pad[-0.7000mm 1.6000mm 0.7000mm 1.6000mm 1.2000mm 0.0000 1.8000mm "" "0" ""] 10 | Pad[-1.6000mm -0.7000mm -0.7000mm -1.6000mm 1.2000mm 0.0000 1.8000mm "" "0" ""] 11 | Pad[-1.6000mm 0.7000mm -0.7000mm 1.6000mm 1.2000mm 0.0000 1.8000mm "" "0" "edge2"] 12 | Pad[0.7000mm 1.6000mm 1.6000mm 0.7000mm 1.2000mm 0.0000 1.8000mm "" "0" "edge2"] 13 | 14 | ) 15 | -------------------------------------------------------------------------------- /pcb/packages/custom_jumper1cm.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 15.5000mm 9.0000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-5.5000mm 0.0000 -4.5000mm 0.0000 1.0000mm 0.6000mm 1.3000mm "" "1" "square"] 5 | Pad[4.5000mm 0.0000 5.5000mm 0.0000 1.0000mm 0.6000mm 1.3000mm "" "2" "square,edge2"] 6 | ElementLine [-5.0000mm 0.0000 5.0000mm 0.0000 0.3000mm] 7 | 8 | ) 9 | -------------------------------------------------------------------------------- /pcb/packages/custom_jumper1cm5.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 15.5000mm 6.0000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-8.5000mm 0.0000 -7.5000mm 0.0000 1.0000mm 0.6000mm 1.3000mm "" "1" "square"] 5 | Pad[7.5000mm 0.0000 8.5000mm 0.0000 1.0000mm 0.6000mm 1.3000mm "" "2" "square,edge2"] 6 | ElementLine [-7.5000mm 0.0000 7.5000mm 0.0000 0.3000mm] 7 | 8 | ) 9 | -------------------------------------------------------------------------------- /pcb/packages/custom_lvds1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 0.5000mm 1.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[0.0000 -1.0000mm 0.0000 1.0000mm 1.0000mm 0.6000mm 1.3000mm "" "1" "square"] 5 | 6 | ) 7 | -------------------------------------------------------------------------------- /pcb/packages/custom_microusb1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 47.0000mm 13.3000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[-3.6500mm 1.2000mm 2.0000mm 0.6000mm 2.1524mm 1.2000mm "" "0" "edge2"] 5 | Pin[3.6500mm 1.2000mm 2.0000mm 0.6000mm 2.1524mm 1.2000mm "" "0" "edge2"] 6 | Pad[-3.3000mm -1.2000mm -3.1000mm -1.2000mm 1.4000mm 0.6000mm 2.0000mm "" "0" "square"] 7 | Pad[3.1000mm -1.2000mm 3.3000mm -1.2000mm 1.4000mm 0.6000mm 2.0000mm "" "0" "square,edge2"] 8 | Pad[-1.3000mm -2.3000mm -1.3000mm -1.0000mm 0.4000mm 0.6000mm 1.0000mm "" "5" "square"] 9 | Pad[1.3000mm -2.3000mm 1.3000mm -1.0000mm 0.4000mm 0.6000mm 1.0000mm "" "1" "square"] 10 | Pad[-0.6500mm -2.3000mm -0.6500mm -1.0000mm 0.4000mm 0.6000mm 1.0000mm "" "4" "square"] 11 | Pad[0.6500mm -2.3000mm 0.6500mm -1.0000mm 0.4000mm 0.6000mm 1.0000mm "" "2" "square"] 12 | Pad[0.0000 -2.3000mm 0.0000 -1.0000mm 0.4000mm 0.6000mm 1.0000mm "" "3" "square"] 13 | Pad[-1.2000mm 1.2500mm -1.2000mm 1.2500mm 1.9000mm 0.6000mm 2.5000mm "" "0" "square"] 14 | Pad[1.2000mm 1.2500mm 1.2000mm 1.2500mm 1.9000mm 0.6000mm 2.5000mm "" "0" "square,edge2"] 15 | 16 | ) 17 | -------------------------------------------------------------------------------- /pcb/packages/custom_miniusb1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 56.0000mm 92.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[-2.6000mm 5.6000mm 1.7000mm 0.0000 1.7500mm 0.8000mm "" "0" ""] 5 | Pin[-2.6000mm -5.6000mm 1.7000mm 0.0000 1.7500mm 0.8000mm "" "0" ""] 6 | Pin[3.0000mm -5.6000mm 1.7000mm 0.0000 1.7500mm 0.8000mm "" "0" ""] 7 | Pin[3.0000mm 5.6000mm 1.7000mm 0.0000 1.7500mm 0.8000mm "" "0" ""] 8 | Pin[0.0000 -2.2000mm 1.5000mm 0.0000 1.6524mm 0.9000mm "" "0" ""] 9 | Pin[0.0000 2.2000mm 1.5000mm 0.0000 1.6524mm 0.9000mm "" "0" ""] 10 | Pad[-3.6000mm -1.6000mm -1.7000mm -1.6000mm 0.5000mm 20.00mil 1.0080mm "" "1" "square"] 11 | Pad[-3.6000mm -0.8000mm -1.7000mm -0.8000mm 0.5000mm 20.00mil 1.0080mm "" "2" "square"] 12 | Pad[-3.6000mm 0.0000 -1.7000mm 0.0000 0.5000mm 20.00mil 1.0080mm "" "3" "square"] 13 | Pad[-3.6000mm 0.8000mm -1.7000mm 0.8000mm 0.5000mm 20.00mil 1.0080mm "" "4" "square"] 14 | Pad[-3.6000mm 1.6000mm -1.7000mm 1.6000mm 0.5000mm 20.00mil 1.0080mm "" "5" "square"] 15 | Pad[-2.5500mm -5.2500mm -2.5500mm -4.7500mm 2.5000mm 0.0000 2.5000mm "" "0" "square"] 16 | Pad[-2.5500mm 4.7500mm -2.5500mm 5.2500mm 2.5000mm 0.0000 2.5000mm "" "0" "square,edge2"] 17 | Pad[2.9500mm -5.2500mm 2.9500mm -4.7500mm 2.5000mm 0.0000 2.5000mm "" "0" "square"] 18 | Pad[2.9500mm 4.7500mm 2.9500mm 5.2500mm 2.5000mm 0.0000 2.5000mm "" "0" "square,edge2"] 19 | 20 | ) 21 | -------------------------------------------------------------------------------- /pcb/packages/custom_pad1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 42.0000mm 57.0000mm -1.0000mm 1.3000mm 0 100 ""] 3 | ( 4 | Pad[0.0500mm -0.2500mm 0.0500mm 0.2500mm 1.5000mm 0.6000mm 1.8000mm "" "1" "square"] 5 | 6 | ) 7 | -------------------------------------------------------------------------------- /pcb/packages/custom_pad_edge.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 49.4000mm 66.4000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-0.1000mm 0.0000 0.2000mm 0.0000 1.0000mm 0.4000mm 1.4000mm "" "1" "square,edge2"] 5 | Pad[-1.1500mm 0.0000 -0.4500mm 0.0000 0.5000mm 0.4000mm 0.9000mm "" "1" "square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/custom_pot_3362.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 56.5000mm 41.6000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[0.0000 -2.5000mm 1.5000mm 0.8032mm 1.5508mm 0.7000mm "" "2" ""] 5 | Pin[2.5000mm 0.0000 1.5000mm 0.8032mm 1.5508mm 0.7000mm "" "3" ""] 6 | Pin[-2.5000mm 0.0000 1.5000mm 0.8032mm 1.5508mm 0.7000mm "" "1" ""] 7 | ElementLine [-3.3000mm 3.5000mm 3.3000mm 3.5000mm 0.6000mm] 8 | ElementLine [3.3000mm 3.5000mm 3.3000mm -3.5000mm 0.6000mm] 9 | ElementLine [3.3000mm -3.5000mm -3.3000mm -3.5000mm 0.6000mm] 10 | ElementLine [-3.3000mm -3.5000mm -3.3000mm 3.5000mm 0.6000mm] 11 | 12 | ) 13 | -------------------------------------------------------------------------------- /pcb/packages/custom_shield1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "custom_shield1" "T3" "unknown" 36.9000mm 105.4000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-0.5000mm 18.4000mm 18.4000mm 18.4000mm 1.0000mm 0.6000mm 1.0500mm "terminal" "1" ""] 5 | Pad[-0.5000mm -0.5000mm -0.5000mm 18.4000mm 1.0000mm 0.6000mm 1.1000mm "terminal" "1" ""] 6 | Pad[-0.5000mm -0.5000mm 18.4000mm -0.5000mm 1.0000mm 0.6000mm 1.0500mm "terminal" "1" ""] 7 | Pad[18.4000mm -0.5000mm 18.4000mm 18.4000mm 1.0000mm 0.6000mm 1.0500mm "terminal" "1" ""] 8 | 9 | ) 10 | -------------------------------------------------------------------------------- /pcb/packages/custom_sma1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 121.0000mm 75.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[1.5000mm 0.0000 3.5000mm 0.0000 3.0000mm 0.0000 3.2000mm "" "1" "square"] 5 | Pad[2.5000mm -1.5000mm 2.5000mm 1.5000mm 5.0000mm 15.75mil 5.2000mm "" "0" "onsolder,square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/custom_sma2.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 70.0000mm 14.0000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-1.6000mm 0.0000 1.6000mm 0.0000 1.8000mm 0.6000mm 2.4000mm "" "1" "square"] 5 | Pad[0.0000 -1.5000mm 0.0000 1.5000mm 5.0000mm 0.6000mm 5.6000mm "" "0" "onsolder,square"] 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /pcb/packages/custom_sma3.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 62.0000mm 77.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[-3.3000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 5 | Pin[-2.2000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 6 | Pin[-3.3000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 7 | Pin[-2.2000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 8 | Pin[-3.3000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 9 | Pin[-2.2000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 10 | Pin[-3.3000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 11 | Pin[-2.2000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 12 | Pin[2.2000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 13 | Pin[3.3000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 14 | Pin[2.2000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 15 | Pin[3.3000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 16 | Pin[2.2000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 17 | Pin[3.3000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 18 | Pin[2.2000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 19 | Pin[3.3000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 20 | Pad[0.0000 -1.6000mm 0.0000 1.6000mm 1.8000mm 0.6000mm 2.4000mm "" "1" "square"] 21 | Pad[-2.7500mm -1.2500mm -2.7500mm 1.2500mm 2.5000mm 0.6000mm 3.1000mm "" "0" "square"] 22 | Pad[2.7500mm -1.2500mm 2.7500mm 1.2500mm 2.5000mm 0.6000mm 3.1000mm "" "0" "square"] 23 | Pad[-1.5000mm 0.0000 1.5000mm 0.0000 5.0000mm 0.0000 5.0000mm "" "0" "onsolder,square"] 24 | 25 | ) 26 | -------------------------------------------------------------------------------- /pcb/packages/custom_sma4.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 21.5000mm 84.6000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[-3.3000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 5 | Pin[-2.2000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 6 | Pin[-3.3000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 7 | Pin[-2.2000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 8 | Pin[-3.3000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 9 | Pin[-2.2000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 10 | Pin[-3.3000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 11 | Pin[-2.2000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 12 | Pin[2.2000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 13 | Pin[3.3000mm -1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 14 | Pin[2.2000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 15 | Pin[3.3000mm -0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 16 | Pin[2.2000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 17 | Pin[3.3000mm 0.6000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 18 | Pin[2.2000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 19 | Pin[3.3000mm 1.8000mm 1.4000mm 0.0000 1.5524mm 0.7000mm "" "0" "edge2"] 20 | Pad[0.0000 -1.5000mm 0.0000 1.5000mm 2.0000mm 0.6000mm 2.6000mm "" "1" "square"] 21 | Pad[-2.7500mm -1.2500mm -2.7500mm 1.2500mm 2.5000mm 0.6000mm 3.1000mm "" "0" "square"] 22 | Pad[2.7500mm -1.2500mm 2.7500mm 1.2500mm 2.5000mm 0.6000mm 3.1000mm "" "0" "square"] 23 | Pad[-1.5000mm 0.0000 1.5000mm 0.0000 5.0000mm 0.0000 5.0000mm "" "0" "onsolder,square"] 24 | 25 | ) 26 | -------------------------------------------------------------------------------- /pcb/packages/custom_sma5.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 123.5000mm 15.5000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[0.8000mm -3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 5 | Pin[-0.3000mm -3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 6 | Pin[1.9000mm -3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 7 | Pin[0.8000mm -2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 8 | Pin[-0.3000mm -2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 9 | Pin[1.9000mm -2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 10 | Pin[-1.4000mm -2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 11 | Pin[0.8000mm 2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 12 | Pin[-0.3000mm 2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 13 | Pin[1.9000mm 2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 14 | Pin[-1.4000mm 2.1000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 15 | Pin[0.8000mm 3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 16 | Pin[-0.3000mm 3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 17 | Pin[1.9000mm 3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 18 | Pin[-1.4000mm 3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 19 | Pin[-1.4000mm -3.3000mm 1.2000mm 0.0000 1.3524mm 0.6000mm "" "0" ""] 20 | Pad[-0.7500mm -2.7500mm 1.2500mm -2.7500mm 2.5000mm 0.0000 2.7000mm "" "0" "square"] 21 | Pad[-0.7500mm 2.7500mm 1.2500mm 2.7500mm 2.5000mm 0.0000 2.7000mm "" "0" "square"] 22 | Pad[-1.0000mm 0.0000 1.5000mm 0.0000 2.0000mm 1.0000mm 2.2000mm "" "1" "square"] 23 | Pad[0.2500mm -1.7500mm 0.2500mm 1.7500mm 4.5000mm 0.6000mm 4.8000mm "" "0" "onsolder,square"] 24 | 25 | ) 26 | -------------------------------------------------------------------------------- /pcb/packages/custom_sma_upright.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 58.4000mm 15.4000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[-100.00mil -100.00mil 100.00mil 30.00mil 2.6520mm 60.00mil "" "0" ""] 5 | Pin[100.00mil -100.00mil 100.00mil 30.00mil 2.6520mm 60.00mil "" "0" ""] 6 | Pin[100.00mil 100.00mil 100.00mil 30.00mil 2.6520mm 60.00mil "" "0" ""] 7 | Pin[-100.00mil 100.00mil 100.00mil 30.00mil 2.6520mm 60.00mil "" "0" ""] 8 | Pin[0.0000 0.0000 100.00mil 30.00mil 2.6520mm 60.00mil "" "1" ""] 9 | ElementLine [-150.00mil -150.00mil 150.00mil -150.00mil 10.00mil] 10 | ElementLine [-150.00mil 150.00mil -150.00mil -150.00mil 10.00mil] 11 | ElementLine [150.00mil -150.00mil 150.00mil 150.00mil 10.00mil] 12 | ElementLine [150.00mil 150.00mil -150.00mil 150.00mil 10.00mil] 13 | 14 | ) 15 | -------------------------------------------------------------------------------- /pcb/packages/custom_so8.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 76.3000mm 31.7000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-4.1074mm -1.9102mm -1.8468mm -1.9102mm 20.00mil 0.6000mm 30.00mil "" "1" "square"] 5 | Pad[-4.1074mm -0.6402mm -1.8468mm -0.6402mm 20.00mil 0.6000mm 30.00mil "" "2" "square"] 6 | Pad[-4.1074mm 0.6298mm -1.8468mm 0.6298mm 20.00mil 0.6000mm 30.00mil "" "3" "square"] 7 | Pad[-4.1074mm 1.8998mm -1.8468mm 1.8998mm 20.00mil 0.6000mm 30.00mil "" "4" "square"] 8 | Pad[1.7600mm 1.8998mm 4.0206mm 1.8998mm 20.00mil 0.6000mm 30.00mil "" "5" "square,edge2"] 9 | Pad[1.7600mm 0.6298mm 4.0206mm 0.6298mm 20.00mil 0.6000mm 30.00mil "" "6" "square,edge2"] 10 | Pad[1.7600mm -0.6402mm 4.0206mm -0.6402mm 20.00mil 0.6000mm 30.00mil "" "7" "square,edge2"] 11 | Pad[1.7600mm -1.9102mm 4.0206mm -1.9102mm 20.00mil 0.6000mm 30.00mil "" "8" "square,edge2"] 12 | ElementLine [-4.6154mm -2.4182mm -4.6154mm 2.4078mm 10.00mil] 13 | ElementLine [-4.6154mm 2.4078mm 4.5286mm 2.4078mm 10.00mil] 14 | ElementLine [4.5286mm 2.4078mm 4.5286mm -2.4182mm 10.00mil] 15 | ElementLine [-4.6154mm -2.4182mm -0.6784mm -2.4182mm 10.00mil] 16 | ElementLine [4.5286mm -2.4182mm 0.5916mm -2.4182mm 10.00mil] 17 | ElementArc [-0.0434mm -2.4182mm 25.00mil 25.00mil -180 -180 10.00mil] 18 | 19 | ) 20 | -------------------------------------------------------------------------------- /pcb/packages/custom_switch1.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 50.4000mm 36.0000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pin[2.5000mm 0.0000 1.2000mm 0.6000mm 48.00mil 0.6000mm "" "3" "edge2"] 5 | Pin[-2.5000mm 0.0000 1.2000mm 0.6000mm 48.00mil 0.6000mm "" "2" "edge2"] 6 | Pin[0.0000 0.0000 1.2000mm 0.6000mm 48.00mil 0.6000mm "" "1" "edge2"] 7 | Pin[-2.5000mm 1.4000mm 1.0000mm 0.0000 1.1524mm 0.4500mm "" "0" "edge2"] 8 | Pin[2.5000mm 1.4000mm 1.0000mm 0.0000 1.1524mm 0.4500mm "" "0" "edge2"] 9 | Pin[2.5000mm -1.4000mm 1.0000mm 0.0000 1.1524mm 0.4500mm "" "0" "edge2"] 10 | Pin[-2.5000mm -1.4000mm 1.0000mm 0.0000 1.1524mm 0.4500mm "" "0" "edge2"] 11 | Pad[-3.3000mm 1.4000mm -1.8000mm 1.4000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square"] 12 | Pad[1.7000mm 1.4000mm 3.2000mm 1.4000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square,edge2"] 13 | Pad[1.7000mm -1.4000mm 3.2000mm -1.4000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square,edge2"] 14 | Pad[-3.3000mm -1.4000mm -1.8000mm -1.4000mm 1.0000mm 0.6000mm 1.6000mm "" "0" "square"] 15 | ElementLine [4.5000mm -2.0000mm 4.5000mm 2.0000mm 0.3000mm] 16 | ElementLine [-4.5000mm -2.0000mm 4.5000mm -2.0000mm 0.3000mm] 17 | ElementLine [-4.5000mm -2.0000mm -4.5000mm 2.0000mm 0.3000mm] 18 | ElementLine [-4.5000mm 2.0000mm 4.5000mm 2.0000mm 0.3000mm] 19 | 20 | ) 21 | -------------------------------------------------------------------------------- /pcb/packages/cx2156nl.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 110.8000mm 63.3000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-1.5000mm 2.0000mm -1.5000mm 2.6000mm 1.0000mm 0.4000mm 1.1500mm "" "1" "square,edge2"] 5 | Pad[0.0000 2.0000mm 0.0000 2.6000mm 1.0000mm 0.4000mm 1.1500mm "" "2" "square,edge2"] 6 | Pad[1.5000mm 2.0000mm 1.5000mm 2.6000mm 1.0000mm 0.4000mm 1.1500mm "" "3" "square,edge2"] 7 | Pad[-1.5000mm -2.4000mm -1.5000mm -1.8000mm 1.0000mm 0.4000mm 1.1500mm "" "6" "square"] 8 | Pad[1.5000mm -2.4000mm 1.5000mm -1.8000mm 1.0000mm 0.4000mm 1.1500mm "" "4" "square"] 9 | 10 | ) 11 | -------------------------------------------------------------------------------- /pcb/packages/lp0603.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 89.6000mm 19.6000mm 0.0000 -0.1000mm 0 100 ""] 3 | ( 4 | Pad[-0.6000mm -0.3000mm -0.5000mm -0.3000mm 0.4000mm 0.6000mm 1.0000mm "" "1" "square"] 5 | Pad[0.6500mm -0.3000mm 0.7500mm -0.3000mm 0.4000mm 0.6000mm 1.0000mm "" "4" "square,edge2"] 6 | Pad[-0.6000mm 0.4000mm -0.5000mm 0.4000mm 0.4000mm 0.6000mm 1.0000mm "" "3" "square"] 7 | Pad[0.6500mm 0.4000mm 0.7500mm 0.4000mm 0.4000mm 0.6000mm 1.0000mm "" "3" "square,edge2"] 8 | 9 | ) 10 | -------------------------------------------------------------------------------- /pcb/packages/mcw-0630.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 143.2000mm 85.4000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-3.0000mm -0.5000mm -3.0000mm 0.6000mm 2.4000mm 0.6000mm 2.7000mm "" "1" "square"] 5 | Pad[3.0000mm -0.5000mm 3.0000mm 0.6000mm 2.4000mm 0.6000mm 2.7000mm "" "2" "square"] 6 | ElementLine [-3.5000mm -3.3000mm 3.5000mm -3.3000mm 0.3000mm] 7 | ElementLine [-3.5000mm -3.3000mm -3.5000mm 3.4000mm 0.3000mm] 8 | ElementLine [3.5000mm -3.3000mm 3.5000mm 3.4000mm 0.3000mm] 9 | ElementLine [-3.5000mm 3.4000mm 3.5000mm 3.4000mm 0.3000mm] 10 | 11 | ) 12 | -------------------------------------------------------------------------------- /pcb/packages/rfsw6024.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 14.9000mm 12.6000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[0.9750mm -2.3750mm 0.9750mm -1.7750mm 0.3000mm 0.6000mm 0.4000mm "" "13" "square"] 5 | Pad[0.3250mm -2.3750mm 0.3250mm -1.7750mm 0.3000mm 0.6000mm 0.4000mm "" "14" "square"] 6 | Pad[-0.3250mm -2.3750mm -0.3250mm -1.7750mm 0.3000mm 0.6000mm 0.4000mm "" "15" "square"] 7 | Pad[-0.9750mm -2.3750mm -0.9750mm -1.7750mm 0.3000mm 0.6000mm 0.4000mm "" "16" "square"] 8 | Pad[1.7750mm -0.9750mm 2.3750mm -0.9750mm 0.3000mm 0.6000mm 0.4000mm "" "12" "square,edge2"] 9 | Pad[1.7750mm -0.3250mm 2.3750mm -0.3250mm 0.3000mm 0.6000mm 0.4000mm "" "11" "square,edge2"] 10 | Pad[1.7750mm 0.3250mm 2.3750mm 0.3250mm 0.3000mm 0.6000mm 0.4000mm "" "10" "square,edge2"] 11 | Pad[1.7750mm 0.9750mm 2.3750mm 0.9750mm 0.3000mm 0.6000mm 0.4000mm "" "9" "square,edge2"] 12 | Pad[-2.3750mm -0.9750mm -1.7750mm -0.9750mm 0.3000mm 0.6000mm 0.4000mm "" "1" "square"] 13 | Pad[-2.3750mm -0.3250mm -1.7750mm -0.3250mm 0.3000mm 0.6000mm 0.4000mm "" "2" "square"] 14 | Pad[-2.3750mm 0.3250mm -1.7750mm 0.3250mm 0.3000mm 0.6000mm 0.4000mm "" "3" "square"] 15 | Pad[-2.3750mm 0.9750mm -1.7750mm 0.9750mm 0.3000mm 0.6000mm 0.4000mm "" "4" "square"] 16 | Pad[0.9750mm 1.7750mm 0.9750mm 2.3750mm 0.3000mm 0.6000mm 0.4000mm "" "8" "square,edge2"] 17 | Pad[0.3250mm 1.7750mm 0.3250mm 2.3750mm 0.3000mm 0.6000mm 0.4000mm "" "7" "square,edge2"] 18 | Pad[-0.3250mm 1.7750mm -0.3250mm 2.3750mm 0.3000mm 0.6000mm 0.4000mm "" "6" "square,edge2"] 19 | Pad[-0.9750mm 1.7750mm -0.9750mm 2.3750mm 0.3000mm 0.6000mm 0.4000mm "" "5" "square,edge2"] 20 | Pad[0.0000 0.0000 0.0000 0.0000 2.3500mm 0.4000mm 2.4500mm "" "17" "square,edge2"] 21 | ElementLine [2.0250mm 1.3750mm 2.0250mm 1.9750mm 0.2000mm] 22 | ElementLine [2.0250mm 1.9750mm 1.3750mm 1.9750mm 0.2000mm] 23 | ElementLine [2.0250mm -2.0250mm 2.0250mm -1.3750mm 0.2000mm] 24 | ElementLine [2.0250mm -2.0250mm 1.3750mm -2.0250mm 0.2000mm] 25 | ElementLine [-1.3750mm -2.0250mm -1.9750mm -2.0250mm 0.2000mm] 26 | ElementLine [-1.9750mm -2.0250mm -1.9750mm -1.3750mm 0.2000mm] 27 | ElementLine [-1.9750mm 1.3750mm -1.9750mm 1.9750mm 0.2000mm] 28 | ElementLine [-1.9750mm 1.9750mm -1.3750mm 1.9750mm 0.2000mm] 29 | ElementLine [-1.9750mm -2.0250mm -2.7750mm -2.8250mm 0.2000mm] 30 | 31 | ) 32 | -------------------------------------------------------------------------------- /pcb/packages/sot23_bjt.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 41.0000mm 23.0000mm 0.0000 0.0000 1 100 ""] 3 | ( 4 | Pad[0.9238mm 1.0000mm 1.0762mm 1.0000mm 34.00mil 0.5620mm 0.9756mm "" "B" "square,edge2"] 5 | Pad[0.9238mm -0.9812mm 1.0762mm -0.9812mm 34.00mil 0.5620mm 0.9756mm "" "E" "square,edge2"] 6 | Pad[-1.1590mm 0.0094mm -1.0066mm 0.0094mm 34.00mil 0.5620mm 0.9756mm "" "C" "square"] 7 | ElementLine [-1.7940mm 1.6350mm 1.7366mm 1.6350mm 10.00mil] 8 | ElementLine [1.7366mm -1.6162mm 1.7366mm 1.6350mm 10.00mil] 9 | ElementLine [-1.7940mm -1.6162mm 1.7366mm -1.6162mm 10.00mil] 10 | ElementLine [-1.7940mm -1.6162mm -1.7940mm 1.6350mm 10.00mil] 11 | 12 | ) 13 | -------------------------------------------------------------------------------- /pcb/packages/tcxo3225.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 132.1000mm 88.4000mm 0.0000 0.0000 3 100 ""] 3 | ( 4 | Pad[0.9000mm -1.3000mm 0.9000mm -1.3000mm 1.4000mm 0.6000mm 2.0000mm "" "4" "square,edge2"] 5 | Pad[0.9000mm 1.3000mm 0.9000mm 1.3000mm 1.4000mm 0.6000mm 2.0000mm "" "3" "square,edge2"] 6 | Pad[-1.0000mm 1.3000mm -1.0000mm 1.3000mm 1.4000mm 0.6000mm 2.0000mm "" "2" "square"] 7 | Pad[-1.0000mm -1.3000mm -1.0000mm -1.3000mm 1.4000mm 0.6000mm 2.0000mm "" "1" "square"] 8 | ElementLine [1.2000mm -0.4000mm 1.2000mm 0.4000mm 0.3000mm] 9 | ElementLine [-0.2000mm -1.6000mm 0.1000mm -1.6000mm 0.3000mm] 10 | ElementLine [-0.2000mm 1.6000mm 0.1000mm 1.6000mm 0.3000mm] 11 | ElementLine [-1.3000mm -0.4000mm -1.3000mm 0.4000mm 0.3000mm] 12 | 13 | ) 14 | -------------------------------------------------------------------------------- /pcb/packages/trf37a75.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 17.2000mm 10.4000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[-1.3250mm 0.7750mm -0.8250mm 0.7750mm 0.2500mm 0.6000mm 0.8500mm "" "4" "square"] 5 | Pad[-1.3250mm 0.2750mm -0.8250mm 0.2750mm 0.2500mm 0.6000mm 0.8500mm "" "3" "square"] 6 | Pad[-1.3250mm -0.2250mm -0.8250mm -0.2250mm 0.2500mm 0.6000mm 0.8500mm "" "2" "square"] 7 | Pad[-1.3250mm -0.7250mm -0.8250mm -0.7250mm 0.2500mm 0.6000mm 0.8500mm "" "1" "square"] 8 | Pad[0.8250mm 0.7750mm 1.3250mm 0.7750mm 0.2500mm 0.6000mm 0.8500mm "" "5" "square,edge2"] 9 | Pad[0.8250mm 0.2750mm 1.3250mm 0.2750mm 0.2500mm 0.6000mm 0.8500mm "" "6" "square,edge2"] 10 | Pad[0.8250mm -0.2250mm 1.3250mm -0.2250mm 0.2500mm 0.6000mm 0.8500mm "" "7" "square,edge2"] 11 | Pad[0.8250mm -0.7250mm 1.3250mm -0.7250mm 0.2500mm 0.6000mm 0.8500mm "" "8" "square,edge2"] 12 | Pad[0.0000 -0.3000mm 0.0000 0.3500mm 0.7000mm 0.6000mm 1.3000mm "" "0" "square,edge2"] 13 | ElementLine [-1.3000mm -1.2000mm -1.7000mm -1.2000mm 0.2500mm] 14 | ElementLine [-1.7000mm -1.2000mm -1.7000mm -0.9000mm 0.2500mm] 15 | 16 | ) 17 | -------------------------------------------------------------------------------- /pcb/packages/ufl.fp: -------------------------------------------------------------------------------- 1 | 2 | Element["" "" "" "" 14.5000mm 6.7000mm 0.0000 0.0000 0 100 ""] 3 | ( 4 | Pad[1.5000mm -0.5500mm 1.5000mm 0.5500mm 1.1000mm 0.4000mm 1.5000mm "" "0" "square,edge2"] 5 | Pad[-1.5000mm -0.5500mm -1.5000mm 0.5500mm 1.1000mm 0.4000mm 1.5000mm "" "0" "square,edge2"] 6 | Pad[0.0000 -1.6000mm 0.0000 -1.5000mm 1.0000mm 0.4000mm 1.4000mm "" "1" "square"] 7 | ElementLine [-1.5500mm 1.6000mm -0.9500mm 1.6000mm 0.2000mm] 8 | ElementLine [1.5500mm -1.6000mm 1.5500mm -1.3000mm 0.2000mm] 9 | ElementLine [0.9500mm -1.6000mm 1.5500mm -1.6000mm 0.2000mm] 10 | ElementLine [-1.5500mm 1.3000mm -1.5500mm 1.6000mm 0.2000mm] 11 | ElementLine [1.5500mm 1.3000mm 1.5500mm 1.6000mm 0.2000mm] 12 | ElementLine [-1.5500mm -1.6000mm -1.5500mm -1.3000mm 0.2000mm] 13 | ElementLine [-1.5500mm -1.6000mm -0.9500mm -1.6000mm 0.2000mm] 14 | ElementLine [0.9500mm 1.6000mm 1.5500mm 1.6000mm 0.2000mm] 15 | 16 | ) 17 | -------------------------------------------------------------------------------- /pcb/pwr_filtering.asc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pcb/pwr_filtering.asc -------------------------------------------------------------------------------- /pcb/sym/ap3419.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1000 17 | sym_height 1000 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name ap3419 26 | device ap3419 27 | refdes U? 28 | footprint 29 | description buck converter 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l EN 59 | 2 pwr line l GND 60 | 3 pwr line l LX 61 | 6 io line r FB 62 | 5 io line r NC 63 | 4 pwr line r VIN 64 | 65 | -------------------------------------------------------------------------------- /pcb/sym/ap3419.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 900 400 900 1 0 0 3 | { 4 | T 300 950 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 850 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 900 9 8 1 1 0 0 1 9 | pinlabel=EN 10 | T 450 900 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 600 400 600 1 0 0 14 | { 15 | T 300 650 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 550 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 600 9 8 1 1 0 0 1 20 | pinlabel=GND 21 | T 450 600 5 8 0 1 0 2 1 22 | pintype=pwr 23 | } 24 | P 100 300 400 300 1 0 0 25 | { 26 | T 300 350 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 250 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 300 9 8 1 1 0 0 1 31 | pinlabel=LX 32 | T 450 300 5 8 0 1 0 2 1 33 | pintype=pwr 34 | } 35 | P 1700 900 1400 900 1 0 0 36 | { 37 | T 1500 950 5 8 1 1 0 0 1 38 | pinnumber=6 39 | T 1500 850 5 8 0 1 0 2 1 40 | pinseq=4 41 | T 1350 900 9 8 1 1 0 6 1 42 | pinlabel=FB 43 | T 1350 900 5 8 0 1 0 8 1 44 | pintype=io 45 | } 46 | P 1700 600 1400 600 1 0 0 47 | { 48 | T 1500 650 5 8 1 1 0 0 1 49 | pinnumber=5 50 | T 1500 550 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1350 600 9 8 1 1 0 6 1 53 | pinlabel=NC 54 | T 1350 600 5 8 0 1 0 8 1 55 | pintype=io 56 | } 57 | P 1700 300 1400 300 1 0 0 58 | { 59 | T 1500 350 5 8 1 1 0 0 1 60 | pinnumber=4 61 | T 1500 250 5 8 0 1 0 2 1 62 | pinseq=6 63 | T 1350 300 9 8 1 1 0 6 1 64 | pinlabel=VIN 65 | T 1350 300 5 8 0 1 0 8 1 66 | pintype=pwr 67 | } 68 | B 400 100 1000 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 69 | T 1400 1200 8 10 1 1 0 6 1 70 | refdes=U? 71 | T 400 1200 9 10 1 0 0 0 1 72 | ap3419 73 | T 400 1400 5 10 0 0 0 0 1 74 | device=ap3419 75 | T 400 1600 5 10 0 0 0 0 1 76 | description=buck converter 77 | T 400 1800 5 10 0 0 0 0 1 78 | numslots=0 79 | -------------------------------------------------------------------------------- /pcb/sym/bgs12pl6.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1000 17 | sym_height 1000 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name bgs12pl6 26 | device bgs12pl6 27 | refdes U? 28 | footprint 29 | description rf switch 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l RF_H 59 | 2 pwr line l GND 60 | 3 io line l RF_L 61 | 6 io line r CTRL 62 | 5 io line r RFIN 63 | 4 pwr line r VDD 64 | 65 | -------------------------------------------------------------------------------- /pcb/sym/bgs12pl6.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 900 400 900 1 0 0 3 | { 4 | T 300 950 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 850 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 900 9 8 1 1 0 0 1 9 | pinlabel=RF_H 10 | T 450 900 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 600 400 600 1 0 0 14 | { 15 | T 300 650 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 550 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 600 9 8 1 1 0 0 1 20 | pinlabel=GND 21 | T 450 600 5 8 0 1 0 2 1 22 | pintype=pwr 23 | } 24 | P 100 300 400 300 1 0 0 25 | { 26 | T 300 350 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 250 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 300 9 8 1 1 0 0 1 31 | pinlabel=RF_L 32 | T 450 300 5 8 0 1 0 2 1 33 | pintype=io 34 | } 35 | P 1700 900 1400 900 1 0 0 36 | { 37 | T 1500 950 5 8 1 1 0 0 1 38 | pinnumber=6 39 | T 1500 850 5 8 0 1 0 2 1 40 | pinseq=4 41 | T 1350 900 9 8 1 1 0 6 1 42 | pinlabel=CTRL 43 | T 1350 900 5 8 0 1 0 8 1 44 | pintype=io 45 | } 46 | P 1700 600 1400 600 1 0 0 47 | { 48 | T 1500 650 5 8 1 1 0 0 1 49 | pinnumber=5 50 | T 1500 550 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1350 600 9 8 1 1 0 6 1 53 | pinlabel=RFIN 54 | T 1350 600 5 8 0 1 0 8 1 55 | pintype=io 56 | } 57 | P 1700 300 1400 300 1 0 0 58 | { 59 | T 1500 350 5 8 1 1 0 0 1 60 | pinnumber=4 61 | T 1500 250 5 8 0 1 0 2 1 62 | pinseq=6 63 | T 1350 300 9 8 1 1 0 6 1 64 | pinlabel=VDD 65 | T 1350 300 5 8 0 1 0 8 1 66 | pintype=pwr 67 | } 68 | B 400 100 1000 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 69 | T 1400 1200 8 10 1 1 0 6 1 70 | refdes=U? 71 | T 400 1200 9 10 1 0 0 0 1 72 | bgs12pl6 73 | T 400 1400 5 10 0 0 0 0 1 74 | device=bgs12pl6 75 | T 400 1600 5 10 0 0 0 0 1 76 | description=rf switch 77 | T 400 1800 5 10 0 0 0 0 1 78 | numslots=0 79 | -------------------------------------------------------------------------------- /pcb/sym/bgs14ga14.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1600 17 | sym_height 1700 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20170801 1 25 | name BGS14GA14 26 | device BGS14GA14 27 | refdes U? 28 | footprint 29 | description rf switch SP4T 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l NC 59 | 2 io line l RX3 60 | 3 io line l RX1 61 | 4 pwr line l VDD 62 | 5 io line b V3 63 | 6 io line b V2 64 | 7 io line b V1 65 | 11 io line r NC 66 | 10 io line r RX4 67 | 9 io line r RX2 68 | 8 io line r NC 69 | 14 io line t NC 70 | 13 io line t ANT 71 | 12 io line t NC 72 | 0 pwr line b PAD 73 | -------------------------------------------------------------------------------- /pcb/sym/blob.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | T 400 800 8 10 0 0 0 0 1 3 | device=SPDT 4 | P 300 100 0 100 1 0 1 5 | { 6 | T 150 150 5 10 1 1 0 0 1 7 | pinnumber=1 8 | T 150 150 5 10 0 0 0 0 1 9 | pinseq=1 10 | T 150 150 5 10 0 1 0 0 1 11 | pinlabel=1 12 | T 150 150 5 10 0 1 0 0 1 13 | pintype=pas 14 | } 15 | T 400 300 8 10 1 1 0 0 1 16 | refdes=B? 17 | P 800 100 1100 100 1 0 1 18 | { 19 | T 950 150 5 10 1 1 0 0 1 20 | pinnumber=2 21 | T 950 150 5 10 0 0 0 0 1 22 | pinseq=2 23 | T 950 150 5 10 0 1 0 0 1 24 | pinlabel=2 25 | T 950 150 5 10 0 1 0 0 1 26 | pintype=pas 27 | } 28 | B 300 0 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 29 | B 600 0 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 30 | -------------------------------------------------------------------------------- /pcb/sym/cmy211.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1000 17 | sym_height 1000 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name cmy211 26 | device cmy211 27 | refdes U? 28 | footprint 29 | description rf mixer 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l in 59 | 2 pwr line l GND 60 | 3 io line l LO in 61 | 6 io line r out 62 | 5 pwr line r GND 63 | 4 pwr line r Vdd 64 | 65 | -------------------------------------------------------------------------------- /pcb/sym/cmy211.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 900 400 900 1 0 0 3 | { 4 | T 300 950 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 850 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 900 9 8 1 1 0 0 1 9 | pinlabel=in 10 | T 450 900 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 600 400 600 1 0 0 14 | { 15 | T 300 650 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 550 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 600 9 8 1 1 0 0 1 20 | pinlabel=GND 21 | T 450 600 5 8 0 1 0 2 1 22 | pintype=pwr 23 | } 24 | P 100 300 400 300 1 0 0 25 | { 26 | T 300 350 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 250 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 300 9 8 1 1 0 0 1 31 | pinlabel=LO in 32 | T 450 300 5 8 0 1 0 2 1 33 | pintype=io 34 | } 35 | P 1700 900 1400 900 1 0 0 36 | { 37 | T 1500 950 5 8 1 1 0 0 1 38 | pinnumber=6 39 | T 1500 850 5 8 0 1 0 2 1 40 | pinseq=4 41 | T 1350 900 9 8 1 1 0 6 1 42 | pinlabel=out 43 | T 1350 900 5 8 0 1 0 8 1 44 | pintype=io 45 | } 46 | P 1700 600 1400 600 1 0 0 47 | { 48 | T 1500 650 5 8 1 1 0 0 1 49 | pinnumber=5 50 | T 1500 550 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1350 600 9 8 1 1 0 6 1 53 | pinlabel=GND 54 | T 1350 600 5 8 0 1 0 8 1 55 | pintype=pwr 56 | } 57 | P 1700 300 1400 300 1 0 0 58 | { 59 | T 1500 350 5 8 1 1 0 0 1 60 | pinnumber=4 61 | T 1500 250 5 8 0 1 0 2 1 62 | pinseq=6 63 | T 1350 300 9 8 1 1 0 6 1 64 | pinlabel=Vdd 65 | T 1350 300 5 8 0 1 0 8 1 66 | pintype=pwr 67 | } 68 | B 400 100 1000 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 69 | T 1400 1200 8 10 1 1 0 6 1 70 | refdes=U? 71 | T 400 1200 9 10 1 0 0 0 1 72 | cmy211 73 | T 400 1400 5 10 0 0 0 0 1 74 | device=cmy211 75 | T 400 1600 5 10 0 0 0 0 1 76 | description=rf mixer 77 | T 400 1800 5 10 0 0 0 0 1 78 | numslots=0 79 | -------------------------------------------------------------------------------- /pcb/sym/connector_coaxial.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | V 150 450 150 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 3 | T 350 650 5 10 0 0 0 0 1 4 | device=BNC 5 | V 150 450 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 6 | P 100 300 100 0 1 0 1 7 | { 8 | T 150 100 5 8 1 1 0 0 1 9 | pinnumber=0 10 | T 150 100 5 8 0 0 0 0 1 11 | pinseq=0 12 | T 150 100 5 8 0 1 0 0 1 13 | pinlabel=0 14 | T 150 100 5 8 0 1 0 0 1 15 | pintype=pas 16 | } 17 | L 200 500 185 485 3 0 0 0 -1 -1 18 | P 200 500 500 500 1 0 1 19 | { 20 | T 350 550 5 8 1 1 0 0 1 21 | pinnumber=1 22 | T 350 550 5 8 0 0 0 0 1 23 | pinseq=1 24 | T 350 550 5 8 0 1 0 0 1 25 | pinlabel=1 26 | T 350 550 5 8 0 1 0 0 1 27 | pintype=pas 28 | } 29 | L 100 300 104 307 3 0 0 0 -1 -1 30 | T 0 800 8 10 1 1 0 0 1 31 | refdes=CONN? 32 | T 0 0 8 10 0 1 0 0 1 33 | class=IO 34 | T 0 0 8 10 0 1 0 0 1 35 | pins=2 36 | -------------------------------------------------------------------------------- /pcb/sym/ics511.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1400 17 | sym_height 1500 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name ICS511 26 | device ICS511 27 | refdes U? 28 | footprint 29 | description spi flash 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l X1 59 | 2 pwr line l VDD 60 | 3 pwr line l GND 61 | 4 io line l S1 62 | 8 io line r X2 63 | 7 io line r OE 64 | 6 io line r S0 65 | 5 io line r CLK 66 | 67 | -------------------------------------------------------------------------------- /pcb/sym/ics511.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 1300 400 1300 1 0 0 3 | { 4 | T 300 1350 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 1250 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 1300 9 8 1 1 0 0 1 9 | pinlabel=X1 10 | T 450 1300 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 1000 400 1000 1 0 0 14 | { 15 | T 300 1050 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 950 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 1000 9 8 1 1 0 0 1 20 | pinlabel=VDD 21 | T 450 1000 5 8 0 1 0 2 1 22 | pintype=pwr 23 | } 24 | P 100 700 400 700 1 0 0 25 | { 26 | T 300 750 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 650 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 700 9 8 1 1 0 0 1 31 | pinlabel=GND 32 | T 450 700 5 8 0 1 0 2 1 33 | pintype=pwr 34 | } 35 | P 100 400 400 400 1 0 0 36 | { 37 | T 300 450 5 8 1 1 0 6 1 38 | pinnumber=4 39 | T 300 350 5 8 0 1 0 8 1 40 | pinseq=4 41 | T 450 400 9 8 1 1 0 0 1 42 | pinlabel=S1 43 | T 450 400 5 8 0 1 0 2 1 44 | pintype=io 45 | } 46 | P 2100 1300 1800 1300 1 0 0 47 | { 48 | T 1900 1350 5 8 1 1 0 0 1 49 | pinnumber=8 50 | T 1900 1250 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1750 1300 9 8 1 1 0 6 1 53 | pinlabel=X2 54 | T 1750 1300 5 8 0 1 0 8 1 55 | pintype=io 56 | } 57 | P 2100 1000 1800 1000 1 0 0 58 | { 59 | T 1900 1050 5 8 1 1 0 0 1 60 | pinnumber=7 61 | T 1900 950 5 8 0 1 0 2 1 62 | pinseq=6 63 | T 1750 1000 9 8 1 1 0 6 1 64 | pinlabel=OE 65 | T 1750 1000 5 8 0 1 0 8 1 66 | pintype=io 67 | } 68 | P 2100 700 1800 700 1 0 0 69 | { 70 | T 1900 750 5 8 1 1 0 0 1 71 | pinnumber=6 72 | T 1900 650 5 8 0 1 0 2 1 73 | pinseq=7 74 | T 1750 700 9 8 1 1 0 6 1 75 | pinlabel=S0 76 | T 1750 700 5 8 0 1 0 8 1 77 | pintype=io 78 | } 79 | P 2100 400 1800 400 1 0 0 80 | { 81 | T 1900 450 5 8 1 1 0 0 1 82 | pinnumber=5 83 | T 1900 350 5 8 0 1 0 2 1 84 | pinseq=8 85 | T 1750 400 9 8 1 1 0 6 1 86 | pinlabel=CLK 87 | T 1750 400 5 8 0 1 0 8 1 88 | pintype=io 89 | } 90 | B 400 100 1400 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 91 | T 1800 1700 8 10 1 1 0 6 1 92 | refdes=U? 93 | T 400 1700 9 10 1 0 0 0 1 94 | ICS511 95 | T 400 1900 5 10 0 0 0 0 1 96 | device=ICS511 97 | T 400 2100 5 10 0 0 0 0 1 98 | description=spi flash 99 | T 400 2300 5 10 0 0 0 0 1 100 | numslots=0 101 | -------------------------------------------------------------------------------- /pcb/sym/lp0603.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 800 17 | sym_height 700 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name LP0603 26 | device LP0603 27 | refdes U? 28 | footprint 29 | description low pass filter 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l OUT 59 | 2 pwr line l GND 60 | 4 io line r IN 61 | 3 pwr line r GND 62 | 63 | -------------------------------------------------------------------------------- /pcb/sym/lp0603.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 600 400 600 1 0 0 3 | { 4 | T 300 650 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 550 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 600 9 8 1 1 0 0 1 9 | pinlabel=OUT 10 | T 450 600 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 300 400 300 1 0 0 14 | { 15 | T 300 350 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 250 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 300 9 8 1 1 0 0 1 20 | pinlabel=GND 21 | T 450 300 5 8 0 1 0 2 1 22 | pintype=pwr 23 | } 24 | P 1500 600 1200 600 1 0 0 25 | { 26 | T 1300 650 5 8 1 1 0 0 1 27 | pinnumber=4 28 | T 1300 550 5 8 0 1 0 2 1 29 | pinseq=3 30 | T 1150 600 9 8 1 1 0 6 1 31 | pinlabel=IN 32 | T 1150 600 5 8 0 1 0 8 1 33 | pintype=io 34 | } 35 | P 1500 300 1200 300 1 0 0 36 | { 37 | T 1300 350 5 8 1 1 0 0 1 38 | pinnumber=3 39 | T 1300 250 5 8 0 1 0 2 1 40 | pinseq=4 41 | T 1150 300 9 8 1 1 0 6 1 42 | pinlabel=GND 43 | T 1150 300 5 8 0 1 0 8 1 44 | pintype=pwr 45 | } 46 | B 400 100 800 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 47 | T 1200 900 8 10 1 1 0 6 1 48 | refdes=U? 49 | T 400 900 9 10 1 0 0 0 1 50 | LP0603 51 | T 400 1100 5 10 0 0 0 0 1 52 | device=LP0603 53 | T 400 1300 5 10 0 0 0 0 1 54 | description=low pass filter 55 | T 400 1500 5 10 0 0 0 0 1 56 | numslots=0 57 | -------------------------------------------------------------------------------- /pcb/sym/nc7s04.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1000 17 | sym_height 1000 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name nc7s04 26 | device nc7s04 27 | refdes U? 28 | footprint 29 | description inverter 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l NC 59 | 2 io line l IN 60 | 3 pwr line l GND 61 | 5 pwr line r VCC 62 | 4 io line r OUT 63 | 64 | -------------------------------------------------------------------------------- /pcb/sym/nc7s04.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 900 400 900 1 0 0 3 | { 4 | T 300 950 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 850 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 900 9 8 1 1 0 0 1 9 | pinlabel=NC 10 | T 450 900 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 600 400 600 1 0 0 14 | { 15 | T 300 650 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 550 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 600 9 8 1 1 0 0 1 20 | pinlabel=IN 21 | T 450 600 5 8 0 1 0 2 1 22 | pintype=io 23 | } 24 | P 100 300 400 300 1 0 0 25 | { 26 | T 300 350 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 250 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 300 9 8 1 1 0 0 1 31 | pinlabel=GND 32 | T 450 300 5 8 0 1 0 2 1 33 | pintype=pwr 34 | } 35 | P 1700 900 1400 900 1 0 0 36 | { 37 | T 1500 950 5 8 1 1 0 0 1 38 | pinnumber=5 39 | T 1500 850 5 8 0 1 0 2 1 40 | pinseq=4 41 | T 1350 900 9 8 1 1 0 6 1 42 | pinlabel=VCC 43 | T 1350 900 5 8 0 1 0 8 1 44 | pintype=pwr 45 | } 46 | P 1700 600 1400 600 1 0 0 47 | { 48 | T 1500 650 5 8 1 1 0 0 1 49 | pinnumber=4 50 | T 1500 550 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1350 600 9 8 1 1 0 6 1 53 | pinlabel=OUT 54 | T 1350 600 5 8 0 1 0 8 1 55 | pintype=io 56 | } 57 | B 400 100 1000 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 58 | T 1400 1200 8 10 1 1 0 6 1 59 | refdes=U? 60 | T 400 1200 9 10 1 0 0 0 1 61 | nc7s04 62 | T 400 1400 5 10 0 0 0 0 1 63 | device=nc7s04 64 | T 400 1600 5 10 0 0 0 0 1 65 | description=inverter 66 | T 400 1800 5 10 0 0 0 0 1 67 | numslots=0 68 | -------------------------------------------------------------------------------- /pcb/sym/pl133.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1000 17 | sym_height 1000 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name PL133-37 26 | device PL133-37 27 | refdes U? 28 | footprint 29 | description clock buffer 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l CLK1 59 | 2 pwr line l GND 60 | 3 io line l FIN 61 | 6 io line r CLK2 62 | 5 pwr line r VDD 63 | 4 io line r CLK0 64 | 65 | -------------------------------------------------------------------------------- /pcb/sym/pl133.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 900 400 900 1 0 0 3 | { 4 | T 300 950 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 850 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 900 9 8 1 1 0 0 1 9 | pinlabel=CLK1 10 | T 450 900 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 600 400 600 1 0 0 14 | { 15 | T 300 650 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 550 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 600 9 8 1 1 0 0 1 20 | pinlabel=GND 21 | T 450 600 5 8 0 1 0 2 1 22 | pintype=pwr 23 | } 24 | P 100 300 400 300 1 0 0 25 | { 26 | T 300 350 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 250 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 300 9 8 1 1 0 0 1 31 | pinlabel=FIN 32 | T 450 300 5 8 0 1 0 2 1 33 | pintype=io 34 | } 35 | P 1700 900 1400 900 1 0 0 36 | { 37 | T 1500 950 5 8 1 1 0 0 1 38 | pinnumber=6 39 | T 1500 850 5 8 0 1 0 2 1 40 | pinseq=4 41 | T 1350 900 9 8 1 1 0 6 1 42 | pinlabel=CLK2 43 | T 1350 900 5 8 0 1 0 8 1 44 | pintype=io 45 | } 46 | P 1700 600 1400 600 1 0 0 47 | { 48 | T 1500 650 5 8 1 1 0 0 1 49 | pinnumber=5 50 | T 1500 550 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1350 600 9 8 1 1 0 6 1 53 | pinlabel=VDD 54 | T 1350 600 5 8 0 1 0 8 1 55 | pintype=pwr 56 | } 57 | P 1700 300 1400 300 1 0 0 58 | { 59 | T 1500 350 5 8 1 1 0 0 1 60 | pinnumber=4 61 | T 1500 250 5 8 0 1 0 2 1 62 | pinseq=6 63 | T 1350 300 9 8 1 1 0 6 1 64 | pinlabel=CLK0 65 | T 1350 300 5 8 0 1 0 8 1 66 | pintype=io 67 | } 68 | B 400 100 1000 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 69 | T 1400 1200 8 10 1 1 0 6 1 70 | refdes=U? 71 | T 400 1200 9 10 1 0 0 0 1 72 | PL133-37 73 | T 400 1400 5 10 0 0 0 0 1 74 | device=PL133-37 75 | T 400 1600 5 10 0 0 0 0 1 76 | description=clock buffer 77 | T 400 1800 5 10 0 0 0 0 1 78 | numslots=0 79 | -------------------------------------------------------------------------------- /pcb/sym/solderbridge.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | P 1500 400 2200 400 1 0 1 3 | { 4 | T 2000 400 5 8 0 1 0 0 1 5 | pinnumber=1 6 | T 2100 300 5 8 0 1 0 0 1 7 | pinseq=1 8 | } 9 | T 1600 831 5 10 1 1 0 0 1 10 | refdes=B? 11 | T 900 100 5 8 0 0 0 0 1 12 | device=pad 13 | B 300 0 1600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 14 | V 1500 400 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 15 | T 1100 150 5 8 1 0 0 4 1 16 | Solder bridge 17 | B 1150 50 700 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 18 | B 350 50 700 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 19 | P 700 400 0 400 1 0 1 20 | { 21 | T 605 445 5 8 0 1 0 6 1 22 | pinnumber=2 23 | T 100 500 5 8 0 1 180 0 1 24 | pinseq=2 25 | } 26 | V 700 400 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 27 | -------------------------------------------------------------------------------- /pcb/sym/tcxo3225.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1000 17 | sym_height 1000 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name tcxo3225 26 | device tcxo3225 27 | refdes U? 28 | footprint 29 | description generic tcxo 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 2 io line t GND 59 | 1 pwr line t Vcont 60 | 3 pwr line b OUT 61 | 4 io line b Vdd 62 | 63 | -------------------------------------------------------------------------------- /pcb/sym/tcxo3225.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 800 1700 800 1400 1 0 0 3 | { 4 | T 750 1500 5 8 1 1 90 0 1 5 | pinnumber=2 6 | T 850 1500 5 8 0 1 90 2 1 7 | pinseq=1 8 | T 800 1350 9 8 1 1 90 6 1 9 | pinlabel=GND 10 | T 800 1350 5 8 0 1 90 8 1 11 | pintype=io 12 | } 13 | P 1100 1700 1100 1400 1 0 0 14 | { 15 | T 1050 1500 5 8 1 1 90 0 1 16 | pinnumber=1 17 | T 1150 1500 5 8 0 1 90 2 1 18 | pinseq=2 19 | T 1100 1350 9 8 1 1 90 6 1 20 | pinlabel=Vcont 21 | T 1100 1350 5 8 0 1 90 8 1 22 | pintype=pwr 23 | } 24 | P 800 100 800 400 1 0 0 25 | { 26 | T 750 300 5 8 1 1 90 6 1 27 | pinnumber=3 28 | T 850 300 5 8 0 1 90 8 1 29 | pinseq=3 30 | T 800 450 9 8 1 1 90 0 1 31 | pinlabel=OUT 32 | T 800 450 5 8 0 1 90 2 1 33 | pintype=pwr 34 | } 35 | P 1100 100 1100 400 1 0 0 36 | { 37 | T 1050 300 5 8 1 1 90 6 1 38 | pinnumber=4 39 | T 1150 300 5 8 0 1 90 8 1 40 | pinseq=4 41 | T 1100 450 9 8 1 1 90 0 1 42 | pinlabel=Vdd 43 | T 1100 450 5 8 0 1 90 2 1 44 | pintype=io 45 | } 46 | B 400 400 1000 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 47 | T 1400 1500 8 10 1 1 0 6 1 48 | refdes=U? 49 | T 500 800 9 10 1 0 0 0 1 50 | tcxo3225 51 | T 500 1100 5 10 0 0 0 0 1 52 | device=tcxo3225 53 | T 500 1300 5 10 0 0 0 0 1 54 | description=generic tcxo 55 | T 500 1500 5 10 0 0 0 0 1 56 | numslots=0 57 | -------------------------------------------------------------------------------- /pcb/sym/tragesym: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pcb/sym/tragesym -------------------------------------------------------------------------------- /pcb/sym/trf37a75.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1300 17 | sym_height 1500 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20170801 1 25 | name trf37a75 26 | device trf37a75 27 | refdes U? 28 | footprint 29 | description rf gain block 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 pwr line l VCC 59 | 2 io line l RFIN 60 | 3 io line l NC 61 | 4 io line l NC 62 | 8 io line r NC 63 | 7 io line r RFOUT 64 | 6 io line r NC 65 | 5 io line r PWDN 66 | 0 pwr line b GND 67 | -------------------------------------------------------------------------------- /pcb/sym/trf37a75.sym: -------------------------------------------------------------------------------- 1 | v 20170801 1 2 | P 100 1600 400 1600 1 0 0 3 | { 4 | T 300 1650 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 1550 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 1600 9 8 1 1 0 0 1 9 | pinlabel=VCC 10 | T 450 1600 5 8 0 1 0 2 1 11 | pintype=pwr 12 | } 13 | P 100 1300 400 1300 1 0 0 14 | { 15 | T 300 1350 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 1250 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 1300 9 8 1 1 0 0 1 20 | pinlabel=RFIN 21 | T 450 1300 5 8 0 1 0 2 1 22 | pintype=io 23 | } 24 | P 100 1000 400 1000 1 0 0 25 | { 26 | T 300 1050 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 950 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 1000 9 8 1 1 0 0 1 31 | pinlabel=NC 32 | T 450 1000 5 8 0 1 0 2 1 33 | pintype=io 34 | } 35 | P 100 700 400 700 1 0 0 36 | { 37 | T 300 750 5 8 1 1 0 6 1 38 | pinnumber=4 39 | T 300 650 5 8 0 1 0 8 1 40 | pinseq=4 41 | T 450 700 9 8 1 1 0 0 1 42 | pinlabel=NC 43 | T 450 700 5 8 0 1 0 2 1 44 | pintype=io 45 | } 46 | P 2000 1600 1700 1600 1 0 0 47 | { 48 | T 1800 1650 5 8 1 1 0 0 1 49 | pinnumber=8 50 | T 1800 1550 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1650 1600 9 8 1 1 0 6 1 53 | pinlabel=NC 54 | T 1650 1600 5 8 0 1 0 8 1 55 | pintype=io 56 | } 57 | P 2000 1300 1700 1300 1 0 0 58 | { 59 | T 1800 1350 5 8 1 1 0 0 1 60 | pinnumber=7 61 | T 1800 1250 5 8 0 1 0 2 1 62 | pinseq=6 63 | T 1650 1300 9 8 1 1 0 6 1 64 | pinlabel=RFOUT 65 | T 1650 1300 5 8 0 1 0 8 1 66 | pintype=io 67 | } 68 | P 2000 1000 1700 1000 1 0 0 69 | { 70 | T 1800 1050 5 8 1 1 0 0 1 71 | pinnumber=6 72 | T 1800 950 5 8 0 1 0 2 1 73 | pinseq=7 74 | T 1650 1000 9 8 1 1 0 6 1 75 | pinlabel=NC 76 | T 1650 1000 5 8 0 1 0 8 1 77 | pintype=io 78 | } 79 | P 2000 700 1700 700 1 0 0 80 | { 81 | T 1800 750 5 8 1 1 0 0 1 82 | pinnumber=5 83 | T 1800 650 5 8 0 1 0 2 1 84 | pinseq=8 85 | T 1650 700 9 8 1 1 0 6 1 86 | pinlabel=PWDN 87 | T 1650 700 5 8 0 1 0 8 1 88 | pintype=io 89 | } 90 | P 1100 100 1100 400 1 0 0 91 | { 92 | T 1050 300 5 8 1 1 90 6 1 93 | pinnumber=0 94 | T 1150 300 5 8 0 1 90 8 1 95 | pinseq=9 96 | T 1100 450 9 8 1 1 90 0 1 97 | pinlabel=GND 98 | T 1100 450 5 8 0 1 90 2 1 99 | pintype=pwr 100 | } 101 | B 400 400 1300 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 102 | T 1700 2000 8 10 1 1 0 6 1 103 | refdes=U? 104 | T 400 2000 9 10 1 0 0 0 1 105 | trf37a75 106 | T 400 2200 5 10 0 0 0 0 1 107 | device=trf37a75 108 | T 400 2400 5 10 0 0 0 0 1 109 | description=rf gain block 110 | T 400 2600 5 10 0 0 0 0 1 111 | numslots=0 112 | -------------------------------------------------------------------------------- /pcb/sym/usb.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | T 700 2500 8 10 1 1 0 6 1 3 | refdes=CONN? 4 | T 300 2450 5 10 0 0 0 0 1 5 | device=CONNECTOR_5 6 | T 300 2650 5 10 0 0 0 0 1 7 | footprint=SIP5N 8 | T 300 2850 5 10 0 0 0 0 1 9 | author=Leon Kos 10 | T 300 3050 5 10 0 0 0 0 1 11 | description=generic connector 12 | T 300 3250 5 10 0 0 0 0 1 13 | numslots=0 14 | P 0 2000 200 2000 1 0 0 15 | { 16 | T 200 2050 5 8 0 1 0 6 1 17 | pinnumber=1 18 | T 200 1950 5 8 0 1 0 8 1 19 | pinseq=1 20 | T 350 2000 9 8 1 1 0 0 1 21 | pinlabel=1 22 | T 350 2000 5 8 0 1 0 2 1 23 | pintype=pas 24 | } 25 | V 250 2000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 26 | P 0 1600 200 1600 1 0 0 27 | { 28 | T 200 1650 5 8 0 1 0 6 1 29 | pinnumber=2 30 | T 200 1550 5 8 0 1 0 8 1 31 | pinseq=2 32 | T 350 1600 9 8 1 1 0 0 1 33 | pinlabel=2 34 | T 350 1600 5 8 0 1 0 2 1 35 | pintype=pas 36 | } 37 | V 250 1600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 38 | P 0 1200 200 1200 1 0 0 39 | { 40 | T 200 1250 5 8 0 1 0 6 1 41 | pinnumber=3 42 | T 200 1150 5 8 0 1 0 8 1 43 | pinseq=3 44 | T 350 1200 9 8 1 1 0 0 1 45 | pinlabel=3 46 | T 350 1200 5 8 0 1 0 2 1 47 | pintype=pas 48 | } 49 | V 250 1200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 50 | P 0 800 200 800 1 0 0 51 | { 52 | T 200 850 5 8 0 1 0 6 1 53 | pinnumber=4 54 | T 200 750 5 8 0 1 0 8 1 55 | pinseq=4 56 | T 350 800 9 8 1 1 0 0 1 57 | pinlabel=4 58 | T 350 800 5 8 0 1 0 2 1 59 | pintype=pas 60 | } 61 | V 250 800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 62 | P 0 400 200 400 1 0 0 63 | { 64 | T 200 450 5 8 0 1 0 6 1 65 | pinnumber=5 66 | T 200 350 5 8 0 1 0 8 1 67 | pinseq=5 68 | T 350 400 9 8 1 1 0 0 1 69 | pinlabel=5 70 | T 350 400 5 8 0 1 0 2 1 71 | pintype=pas 72 | } 73 | V 250 400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 74 | B 200 0 1000 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 75 | P 1400 2000 1200 2000 1 0 0 76 | { 77 | T 1295 2045 5 8 0 1 0 0 1 78 | pinnumber=0 79 | T 1200 2050 5 8 0 1 180 8 1 80 | pinseq=0 81 | T 1145 1995 9 8 1 1 0 6 1 82 | pinlabel=0 83 | T 1050 2000 5 8 0 1 180 2 1 84 | pintype=pas 85 | } 86 | T 500 2000 9 10 1 0 0 0 1 87 | GND 88 | T 500 1500 9 10 1 0 0 0 1 89 | ID 90 | T 500 1100 9 10 1 0 0 0 1 91 | data+ 92 | T 500 700 9 10 1 0 0 0 1 93 | data- 94 | T 500 300 9 10 1 0 0 0 1 95 | Vbus 96 | -------------------------------------------------------------------------------- /pcb/sym/w25q32.csv: -------------------------------------------------------------------------------- 1 | # This is the template file for creating symbols with tragesym 2 | # every line starting with '#' is a comment line. 3 | # save it as text file with tab separated cells and start tragesym 4 | 5 | [options] 6 | # wordswap swaps labels if the pin is on the right side an looks like this: 7 | "# ""PB1 (CLK)"". That's useful for micro controller port labels" 8 | # rotate_labels rotates the pintext of top and bottom pins 9 | # this is useful for large symbols like FPGAs with more than 100 pins 10 | # sort_labels will sort the pins by it's labels 11 | # useful for address ports, busses, ... 12 | wordswap yes 13 | rotate_labels yes 14 | sort_labels no 15 | generate_pinseq yes 16 | sym_width 1400 17 | sym_height 1500 18 | pinwidthvertical 300 19 | pinwidthhorizontal 300 20 | [geda_attr] 21 | # name will be printed in the top of the symbol 22 | # if you have a device with slots, you'll have to use slot= and slotdef= 23 | # use comment= if there are special information you want to add 24 | version 20060113 1 25 | name W25Q32FV 26 | device W25Q32FV 27 | refdes U? 28 | footprint 29 | description spi flash 30 | documentation 31 | 32 | numslots 0 33 | dist-license 34 | use-license 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | [pins] 45 | # tabseparated list of pin descriptions 46 | # 47 | # pinnr is the physical number of the pin 48 | # seq is the pinseq= attribute, leave it blank if it doesn't matter 49 | # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) 50 | # style can be (line,dot,clk,dotclk,none). none if only want to add a net 51 | # posit. can be (l,r,t,b) or empty for nets 52 | # net specifies the name of the net. Vcc or GND for example. 53 | # label represents the pinlabel. 54 | # "negation lines can be added with ""\_"" example: \_enable\_ " 55 | # "if you want to write a ""\"" use ""\\"" as escape sequence" 56 | # 57 | #pinnr seq type style posit. net label 58 | 1 io line l CS_n 59 | 2 io line l DO 60 | 3 io line l WP_n 61 | 4 pwr line l GND 62 | 8 pwr line r Vcc 63 | 7 io line r RESET_n 64 | 6 io line r CLK 65 | 5 io line r DI 66 | 67 | -------------------------------------------------------------------------------- /pcb/sym/w25q32.sym: -------------------------------------------------------------------------------- 1 | v 20060113 1 2 | P 100 1300 400 1300 1 0 0 3 | { 4 | T 300 1350 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 300 1250 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 450 1300 9 8 1 1 0 0 1 9 | pinlabel=CS_n 10 | T 450 1300 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 100 1000 400 1000 1 0 0 14 | { 15 | T 300 1050 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 300 950 5 8 0 1 0 8 1 18 | pinseq=2 19 | T 450 1000 9 8 1 1 0 0 1 20 | pinlabel=DO 21 | T 450 1000 5 8 0 1 0 2 1 22 | pintype=io 23 | } 24 | P 100 700 400 700 1 0 0 25 | { 26 | T 300 750 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 300 650 5 8 0 1 0 8 1 29 | pinseq=3 30 | T 450 700 9 8 1 1 0 0 1 31 | pinlabel=WP_n 32 | T 450 700 5 8 0 1 0 2 1 33 | pintype=io 34 | } 35 | P 100 400 400 400 1 0 0 36 | { 37 | T 300 450 5 8 1 1 0 6 1 38 | pinnumber=4 39 | T 300 350 5 8 0 1 0 8 1 40 | pinseq=4 41 | T 450 400 9 8 1 1 0 0 1 42 | pinlabel=GND 43 | T 450 400 5 8 0 1 0 2 1 44 | pintype=pwr 45 | } 46 | P 2100 1300 1800 1300 1 0 0 47 | { 48 | T 1900 1350 5 8 1 1 0 0 1 49 | pinnumber=8 50 | T 1900 1250 5 8 0 1 0 2 1 51 | pinseq=5 52 | T 1750 1300 9 8 1 1 0 6 1 53 | pinlabel=Vcc 54 | T 1750 1300 5 8 0 1 0 8 1 55 | pintype=pwr 56 | } 57 | P 2100 1000 1800 1000 1 0 0 58 | { 59 | T 1900 1050 5 8 1 1 0 0 1 60 | pinnumber=7 61 | T 1900 950 5 8 0 1 0 2 1 62 | pinseq=6 63 | T 1750 1000 9 8 1 1 0 6 1 64 | pinlabel=RESET_n 65 | T 1750 1000 5 8 0 1 0 8 1 66 | pintype=io 67 | } 68 | P 2100 700 1800 700 1 0 0 69 | { 70 | T 1900 750 5 8 1 1 0 0 1 71 | pinnumber=6 72 | T 1900 650 5 8 0 1 0 2 1 73 | pinseq=7 74 | T 1750 700 9 8 1 1 0 6 1 75 | pinlabel=CLK 76 | T 1750 700 5 8 0 1 0 8 1 77 | pintype=io 78 | } 79 | P 2100 400 1800 400 1 0 0 80 | { 81 | T 1900 450 5 8 1 1 0 0 1 82 | pinnumber=5 83 | T 1900 350 5 8 0 1 0 2 1 84 | pinseq=8 85 | T 1750 400 9 8 1 1 0 6 1 86 | pinlabel=DI 87 | T 1750 400 5 8 0 1 0 8 1 88 | pintype=io 89 | } 90 | B 400 100 1400 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 91 | T 1800 1700 8 10 1 1 0 6 1 92 | refdes=U? 93 | T 400 1700 9 10 1 0 0 0 1 94 | W25Q32FV 95 | T 400 1900 5 10 0 0 0 0 1 96 | device=W25Q32FV 97 | T 400 2100 5 10 0 0 0 0 1 98 | description=spi flash 99 | T 400 2300 5 10 0 0 0 0 1 100 | numslots=0 101 | -------------------------------------------------------------------------------- /pcb/tx.gsch2pcb: -------------------------------------------------------------------------------- 1 | schematics tx.sch 2 | output-name tx 3 | -------------------------------------------------------------------------------- /pcb/vna_tester.gsch2pcb: -------------------------------------------------------------------------------- 1 | schematics vna_tester.sch 2 | output-name vna_tester 3 | -------------------------------------------------------------------------------- /pictures/all.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/all.jpg -------------------------------------------------------------------------------- /pictures/calibration_standards.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/calibration_standards.jpg -------------------------------------------------------------------------------- /pictures/cmp_attenuator_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/cmp_attenuator_200_2180.png -------------------------------------------------------------------------------- /pictures/cmp_open_stub_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/cmp_open_stub_200_2180.png -------------------------------------------------------------------------------- /pictures/cmp_shorted_stub_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/cmp_shorted_stub_200_2180.png -------------------------------------------------------------------------------- /pictures/coupler_top.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/coupler_top.png -------------------------------------------------------------------------------- /pictures/drift_100C_short_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/drift_100C_short_200_2180.png -------------------------------------------------------------------------------- /pictures/drift_load_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/drift_load_200_2180.png -------------------------------------------------------------------------------- /pictures/drift_open_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/drift_open_200_2180.png -------------------------------------------------------------------------------- /pictures/drift_resistor_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/drift_resistor_200_2180.png -------------------------------------------------------------------------------- /pictures/drift_short_200_2180.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/drift_short_200_2180.png -------------------------------------------------------------------------------- /pictures/fpga_logic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/fpga_logic.png -------------------------------------------------------------------------------- /pictures/main2_top.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/main2_top.jpg -------------------------------------------------------------------------------- /pictures/main_top.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/main_top.png -------------------------------------------------------------------------------- /pictures/overall_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/overall_diagram.png -------------------------------------------------------------------------------- /pictures/overall_diagram.xml: -------------------------------------------------------------------------------- 1 | 7Vzfc6I6FP5rfGwHCEF9VFt378ztzM7t7tzdx1QiZIvEi7Hq/vU3wYSfUbFi2mp5aOEkhHC+853knEQ6YDRbf0nQPHygPo46juWvO+Cu4zi25Xj8n5BsthLoSkGQEF9WygWP5A9Wd0rpkvh4UarIKI0YmZeFExrHeMJKMpQkdFWuNqVR+alzFOCa4HGCorr0X+KzUPXOsvKCr5gEIauWPKHJc5DQZSwf2HHAND22xTOkGpP1FyHy6aogAvcdMEooZduz2XqEI6FcpbftfeMdpVnHExyzJjdIXF5QtMSqx2m/2EYpI30bLOpbHTBchYThxzmaiNIVh5/LQjaL+JXNTxcsoc94RCOapHcDcYz504dTGrOKHAAulx3ACcPrnS9hZ6rhNofpDLNkw6uslXlJbUpzA0q7qxw84ElZWMDNUTciaTBB1nauM34i1aZXYVejQi/iTxg+8ZNAnIxoiNOXcaw4tc8nxA2Ev2KIFrgjeuuhmdDk9m9qKEFM2NIXpT5m3Mi54mSzvENZyy2j5aXHHrR8tAjT1u2WoPNgGTq3Dp3taqDzWkCu97bIyUcll4qlaxvEsv+J5Vmx7BnE0rYPg/njUQBEYoaTKZqQOLhE79itDGzQaohCG+Oa7RxGQQmEQkqa9v5bUlVws0gneANewYbzdV6oWhl/+zIowLdtrPyAvahyBbN90MU0xqIvJIoqIhSRIOaXEywMiQsEXIRPBAeyYEZ8XzxGaysluA3Ob5x+3Qx0VuC0YAWezgoq+sc+nz3LS5qwkAY0RtF9Lh2WeVcCCiVsIJxxDkoqGxPRpbT6b8zYRgYJaMkoF+VP+ZvSeSMERCf365+/E10mE1ULbGW8MwFWzm0HTgmOECMv5fZP4h44zL3HTcxCLLhlYmaYz+MLLOLycXqc1/57sGz/Nqzbf19j/7027B+2ae54TdhPKRbnv8T5LRRXMe/YT1VNXORl75cknorOCyRxgCGSeA2mCYPZPCJTcvEUqc4UTFIE6uKoaxgiHM0QAbuGrN9pMERwDYlpjUhLxc8XzgAPvOEg0fscJHbTBHbrNLE9QzSBDdJzA8ZwvERmUmxvyRHovB1HbPcwEHckwRNGhDV2RHZ/OY8ufuR2qiM3qGOije7sNsI7qEPFqCsrXP6SNd+vK7OhxpX19+J7Y906luOWML5RmdHG7k42/42SNNGiqtDpdMH7UQU860WzBYx6iP8PnkaciRzSw7mWRMSg6CmtIJCZiz6m/YPDDrw7KssSoSccDbM1tAJwchXtFVSUi4Syh50sK1KEekuDvRg6rlPm6WkIqpZBxTAqLbQCsLLaAsB0yRpAayaNZtK5atLY4EyZM7u+tkria1C6W03XGFQ6PM/wtR2j5ACWTb6zke2jzMRtzUx8h+c7zq/xt0WbQgU5Bux0e8Aum4iaYY531Hes0+q7rlWxom2PX+1R61FFcsSQ+eEpnkUECg/NpFW74aINioNPiu+heK9OcedEijce8eqJwClNVii5Ck64VZ+m4QQ8FyfOs0pxKZzo1zlhapGiW1+k+B5yzQdhA05cRGgF97KGh1a2VY6sgDTmU0OrCh9VFNRuaNVg39Hdj+8GcljjsSV2odZyWAJbhM7r+ryypoHG8+nSim3sFQJ2TY9n9nzlfNX7W6Fq08vtmF33+7de4eiWs1sQVorL7W89s2wyB/roEKIyxYfwQEjQg/vqnxwSAOOR53s3xNJS6buJPKuR4aFIsqffCNma2RiPZj662ZwazbRjNvaRZmO3azZNfnXwQTaI+WrRTzwHL/KutZr5hV59TpKtoLW91qmWCq5vR4zGy5vaM6nTeYURD2RtmAvmljZAw7X8NraGu2fZ76LOdYvEHynd4Gom4qZ2hbn1dEN9u8vd6EI4UE25GeVAfVH1Ony8q/Hxp07lGyv9un28q/lh69nsu//p4/eQQMOCnikSNGDB5fp4oxzQRVnX4OM1G9tdUzt2G+xrv2gfr/lx37nsW02XPn281sd7dRbs2OvZvo/XfZjjeny8SQ7UNT1Val0sM63+NS7ouiBXUp+8VEWFWtZt/+Hrn/0tcGmpkQqKF7hjAjT4bova2dA27N1jf2ErFru5wqNr+M5A46+wvAIJfpl/3mib+c4/IgXu/wc= -------------------------------------------------------------------------------- /pictures/screenshot_antenna.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/screenshot_antenna.png -------------------------------------------------------------------------------- /pictures/screenshot_new_antenna.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/screenshot_new_antenna.png -------------------------------------------------------------------------------- /pictures/screenshot_new_coax.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/screenshot_new_coax.png -------------------------------------------------------------------------------- /pictures/screenshot_new_ttf.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/screenshot_new_ttf.png -------------------------------------------------------------------------------- /pictures/screenshot_open_stub.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/screenshot_open_stub.png -------------------------------------------------------------------------------- /pictures/screenshot_pa_900.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/screenshot_pa_900.png -------------------------------------------------------------------------------- /pictures/screenshot_shorted_stub.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/screenshot_shorted_stub.png -------------------------------------------------------------------------------- /pictures/tx_top.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/tx_top.png -------------------------------------------------------------------------------- /pictures/vna_main.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/vna_main.png -------------------------------------------------------------------------------- /pictures/vna_main.xml: -------------------------------------------------------------------------------- 1 | 7Vxbc6pIEP41VmUf1oIZbj4aE3O26qSOtdlL8kh0VDaEcWGMur9+B5mR22C8DAPx6EMKegYYvv66abo7dODgff0Quov5I54gvwO0yboD7zoAODagf2PBJhEYlpEIZqE3SUR6Knjy/kNMqDHp0pugKDeRYOwTb5EXjnEQoDHJydwwxKv8tCn281dduDNUEjyNXb8s/dubkDlfnaalA9+QN5uzS1t84NUdv81CvAzY9ToATre/ZPjd5edi86O5O8GrjAjed+AgxJgkW+/rAfJjaDlsyXHDitHdukMUkEMOAJCtg2z4vaMJhYLt4pDM8QwHrn+fSm+394fiM2h0b07efbqp00209shzZvslntI1472AhJtndsR2Jx37BxGyYRxwlwRTUXrd7xgv2BnL98ZuN8LLcMxWz4hH3HCG2Cx2i/F9ZQ5jeDwg/I7ocuiEEPku8T7yFHAZk2a7eSmadIMBKgbX6tUPLtiHLjgG3ikOyAD7ONyuFCY/Ko8olqQfGxUdGPtuFHljLh56vn+MdmBZO5bWlHrYYj5cf4m4tVo+XdbtK92Yke1NJYIYm5wirX+XmA/8Gm3B7dMJOlys00F+luHooc/PRBeVnCx/ASrOXLRAmjwlVnOPoKeFu8V0Rd1vniYRCfEbKihyONynoQ8UErTeCz4bNSHTFvPrwDGT/VXGS/I584yD1LnDO0dh3LibclZHmdNB9mC0yFvxxTSFri0dXatF6FqqnE3/jq5Fu+nf9YCm/XIZbgf28m7H4OFWxu04Aq9jSnA6ui3QnDw7kUp4u0x4oynCi2CrhfDfR8NO/HShAu12OZ2i8DJIv4uM+LPWKJNe1+tivfN1WO+UWQ+aYr0Itivrz2A9BCpZ3/s6rO+VWW81xXoRbFfWn8F6UYBTH+sbDvylx/0cqKxtOE3Zhm5dGrp6GV27MXTNS0NXkMDsNYYuUOXYH7117Mu1m8HjC7XfC3lv1Q9w63W9t3KPJ9cytD2WkclFv7CpZ5tG1gy445FnB+zQEfa23OVJTqB1YeZn5nSoG2ZuFNr58yfGzE6Zqqsfhu4mM20RT4j2LiJ/WVgo5BTm687e+XQjWUHKnR1gh9GpllpGmU5yGSO9tnBBjAFavYzhZQCFDsiu2QFJTytcEp32zz+bTtz7X2MRObGIKJ1YWw5du+pOpu5ESbG6dAdriSPLb1hS36KgkvDxYAiVua7f4/SYF5zD+mjuLuLNOVq7FHs6ZYFCj94zClPpiIvA55Yx9Xw/YxdIn5jIFllMz7Kha3WqO1EkWFKxf8EQ9C9oAksyZFiSgnYgKZZUd3xTcmefRDSJFZcimvJ5oSY8z4GXqQicTohVDP2qaXECBCjR9GeXkahpZU1kV9d+nGuHQKFrN4wrDdpJA0NTSANTUTXi3Jbeg2JoQ9RNJL2MdlJuwigmO3vm3sdFab5pFtR6Xm7CVPCOZEtLtktnRWNNlXYttdV8ijHfYK93Ti7/SYfdNhvDvZ5iAMOaQa+3lu+N9VQ69aTUu3tgbw/q0pPvB6Ney9sc9+hi2E+vZEjHvbGuMqO6hThauMHpMXQpNP9j8Pyjw/rKRAH0TpZcNy+eeB9FkeTllTrdDl0aFedW19oEd7HBX7fVJbiN6p5dyXr8HpPsaROQOYqP3dYp+ndDA5q5QsXn2m2tHs1iTVnUvSv6/zBbgiJBpR4lv4P/DP9io7LEpCx58jMoTmVdl2d363edfz7FLd+jby+tfEDf0OVBaMDjvPgXe0bbBd8OegLfLsqsWTKYVl1ClaxL2IV/xVTDqyNDrtYqzipmvyyB4oBAcY4MxVUXSCQrTu+CC1ecoStUnF3Ll0H2tO/VkFqT+ekKW9BS0ty3KxzQvHZy6AY4QAVolWUthKqRnpQ+qVLhGAUTNuV2RTotsNJ286CeTodzecCbr2XxwK6OjyS/Qz16gUcHl9HrtQZd9eAuahuK/p2zriI0LwvVT4WBj8dvdBQvyZULVVzYvWgzLggym7VRwbEVPx20bk938k8ITbO4YJRRq3Z4eKbk2eG06WNBjrKvBT2MfvsRXY238g2sp8x46W762cckAkg/rQnv/wc= -------------------------------------------------------------------------------- /pictures/vna_tx.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/pictures/vna_tx.png -------------------------------------------------------------------------------- /pictures/vna_tx.xml: -------------------------------------------------------------------------------- 1 | 7Vtvk5o8EP80zrQvekMIiL707Gk7006d2pmnz8ucRKCHhMZ4aj99AyTyXx0PEIv3og2bhYTd/e1m16UHx6vdlCLf/kpM7PZUxdz14Meeqg4Hff5vQNhHBG04jAgWdcyIBGLC3PmDBVER1I1j4nWKkRHiMsdPExfE8/CCpWiIUrJNsy2Jm17VRxbOEeYL5Oap/zkms+XuFCWe+IQdyxZL63LiGS1eLEo2nlivp8Jl+BdNr5B8luBf28gk2wQJPvXgmBLCotFqN8ZuIFoptui+ScnsYd8Ue+ycG/TohlfkbrDccbgvtpeywCYXjbgklNnEIh5yn2LqY/i+OHiiwq9stnL5EPDhmiHKRoE+OMEjHpa0ieO6gv0XZmwvLABtGOGkeJUvhPjiWUvisTFxCQ13BaM/To/2G2yyVASCtCYbuhBcUBgVohYWXNpB/NyqMVlhRvechWIXMec1/XQk7Ms68MUy5gMh5mKRwwKR910mXjEl+/7vDZETH9ahjEacAUB/F0/ykSX+D5/yLAnzvcdsHNxG5Rzf23OWn9OihdNk03nNkire37vRx4kGdeX9Bbvj5NQGMzabtsit7TA891Go/C13WFkrpeQFZ2xrMjlpc6+YMrw7bnV5e5I3SI8hPCSA4nqb8DfSS9gJVzNQ3m6Cg46iXsuj3mgI9Vop6tc+8ipE1Wjlu87SOYn5aNmTmK94d+9+fJ9AY2Top0BftL1/DvSq1iDo5dmqc6g38qgfNoR6MKhSxHjnsJ+J8f8BywM/w/FLj+/sp7glvIgm9VvTDGjKIYNh/aox/i3V9BtSTbWOSapGqkNoB6RUk0CRnLwt3ahv1E14K39btE8w+MTx2Drx5FlAiOMZhOl4pimZbDPDr+tH+fkg2kFsJYdXOctwjKYOWd8nnHe+ddjCbucx63E6B9p0BLROnrMO56qrnLOKEvwunLOGNbilc4U+bAr5X2aTViIePATvP/30p4t417J5la7n8D4ogLteAdw7W0IFah7vjRVR5eL3UN/xUK+rVwz1ai05ZJQaHrLIdJ5yQ2lKUbk1Kj03kUM2VnCdUWJRtFqhZ/44VRkxhr0NYqSlBdjZkwYVtZO+oj+4pq8AOYlVXm86Vm4y2l1vAv0rZg9y8e6mDyq3nXv6IPwCVPN+obb0QckJrFG3oLbcLdRR6zzbLTRWT2yrWwDBj4bK17tbCLmHzbkFCK/rFtrtFWQDS9IrQKVYmdVnFkXdM/W0crQ7lfgQHBnMxy66hmwmAQpODLVlEvJHt/o7CMPaF9mwEypON+hllLm2kR8MbbxD3CtwFh9Th780pjF1JknqBQof9g2I+kcUvuT+KkHHwNSxUY0hDDK/NAGYrzwXGkIlQaKW7hLl7CDR8pQSFtSfYENBApaXn6ru8p19vsOzDJ7Zhjuon+mnq4CnXktqdwye6eqw0m50FhR8GkNneb2nYnSOXbJ4CVb27iAtA2m2W2PQYAjVtIYxCno3lGfBgpaO5r6TKe/puIfQ651wi3or6oOnWgs8H440gt5QCNXkp5HXKI5qtVSojp5ujBvXzVtb2y/r0TUyGaqmJ9V8kj/3BemJHuAM/5t7eqUg6w8D09nnb/c4UBYHdHBhyeuCOMAv40+gI5uJPzOHT38B -------------------------------------------------------------------------------- /run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | if [ "$QT" == "" ]; then 3 | QT=/persist/qt/5.10.1/gcc_64 4 | fi 5 | LIBDIR="$(dirname $0)" 6 | LD_LIBRARY_PATH="$LIBDIR/libxavna/.libs:$LIBDIR/libxavna/xavna_mock_ui:$QT/lib" "$@" 7 | -------------------------------------------------------------------------------- /tester/Makefile: -------------------------------------------------------------------------------- 1 | CXX = g++ -O2 2 | LDFLAGS = 3 | 4 | vna_tester: main.C 5 | $(CXX) main.C ../libxavna/xavna.C ../libxavna/platform_abstraction.C platform_opi.C -I ../include -o vna_tester -std=c++0x -lwiringPi -lpthread `pkg-config --cflags --libs cairomm-1.0` 6 | 7 | -------------------------------------------------------------------------------- /tester/platform.H: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | // platform specific functions 4 | 5 | 6 | int platform_init(); 7 | 8 | // bit-bang the jtag waveform; 9 | // if progress is not NULL, it is kept updated with the current index of the playback 10 | int platform_writeJtag(uint8_t* data, int len, volatile int* progress=0); 11 | 12 | -------------------------------------------------------------------------------- /vhdl/.gitignore: -------------------------------------------------------------------------------- 1 | a.svf 2 | *.b64 3 | *.tcl 4 | *.debug 5 | planAhead_* 6 | ipcore_dir/*/* 7 | 8 | # intermediate build files 9 | *.bgn 10 | top.bit 11 | top2.bit 12 | *.bld 13 | *.cmd_log 14 | *.drc 15 | *.ll 16 | *.lso 17 | *.msd 18 | *.msk 19 | *.ncd 20 | *.ngc 21 | *.ngd 22 | *.ngr 23 | *.pad 24 | *.par 25 | *.pcf 26 | *.prj 27 | *.ptwx 28 | *.rbb 29 | *.rbd 30 | *.stx 31 | *.syr 32 | *.twr 33 | *.twx 34 | *.unroutes 35 | *.ut 36 | *.xpi 37 | *.xst 38 | *_bitgen.xwbt 39 | *_envsettings.html 40 | *_map.map 41 | *_map.mrp 42 | *_map.ngm 43 | *_map.xrpt 44 | *_ngdbuild.xrpt 45 | *_pad.csv 46 | *_pad.txt 47 | *_par.xrpt 48 | *_summary.html 49 | *_summary.xml 50 | *_usage.xml 51 | *_xst.xrpt 52 | 53 | # iMPACT generated files 54 | _impactbatch.log 55 | impact.xsl 56 | impact_impact.xwbt 57 | ise_impact.cmd 58 | webtalk_impact.xml 59 | 60 | # Core Generator generated files 61 | xaw2verilog.log 62 | 63 | # project-wide generated files 64 | *.gise 65 | par_usage_statistics.html 66 | usage_statistics_webtalk.html 67 | webtalk.log 68 | webtalk_pn.xml 69 | 70 | # generated folders 71 | iseconfig/ 72 | xlnx_auto_0_xdb/ 73 | xst/ 74 | _ngo/ 75 | _xmsgs/ 76 | -------------------------------------------------------------------------------- /vhdl/bounce_sprite.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | use work.graphics_types.all; 5 | entity bounce_sprite is 6 | generic(W,H,spriteW,spriteH: integer; 7 | initX,initY: integer := 0); 8 | port(clk, en: in std_logic; 9 | sprite_p: out position; 10 | initvX,initvY: in unsigned(14 downto 0)); 11 | end entity; 12 | architecture a of bounce_sprite is 13 | --4 bits after decimal point 14 | type position_f is array(0 to 1) of unsigned(15 downto 0); 15 | --there are only 4 possible velocities 16 | signal cv,nv: std_logic_vector(1 downto 0); 17 | signal cp,np: position_f := (X"0000",X"0000"); 18 | signal vx,vy: signed(15 downto 0); 19 | begin 20 | cv <= nv when en='1' and rising_edge(clk); 21 | nv(0) <= '1' when cp(0)+spriteW*16+initvX*2>W*16 and cv(0)='0' else 22 | '0' when cp(0)H*16 and cv(1)='0' else 24 | '0' when cp(1)) of std_logic_vector(7 downto 0); 8 | end package; 9 | 10 | library ieee; 11 | library work; 12 | use ieee.numeric_std.all; 13 | use ieee.std_logic_1164.all; 14 | use work.configRegisterTypes.all; 15 | 16 | -- command format: 1 byte cmd followed by 1 byte value; cmd is either 0 17 | -- (for no-op) or addr+1 (to write to address addr) 18 | entity serialConfigRegister is 19 | generic(bytes: integer; 20 | defaultValue: array8(0 to 254) := (others=>X"00")); 21 | port(clk: in std_logic; 22 | rxdat: in std_logic_vector(7 downto 0); 23 | rxval: in std_logic; 24 | 25 | registers: out array8(0 to bytes-1); 26 | write_indicator: out std_logic; 27 | write_indicator_addr: out unsigned(7 downto 0) 28 | ); 29 | end entity; 30 | architecture a of serialConfigRegister is 31 | signal regs: array8(0 to bytes-1) := defaultValue(0 to bytes-1); 32 | 33 | signal state,stateNext: std_logic; 34 | signal waddr,waddrNext: unsigned(7 downto 0); 35 | 36 | signal wi: std_logic; 37 | signal wi_addr: unsigned(7 downto 0); 38 | begin 39 | assert bytes<=254; 40 | registers <= regs; 41 | 42 | stateNext <= '0' when state='0' and rxdat="00000000" else 43 | '1' when state='0' else 44 | '0' when state='1'; 45 | state <= stateNext when rxval='1' and rising_edge(clk); 46 | 47 | waddrNext <= unsigned(rxdat)-1 when state='0' else waddr; 48 | waddr <= waddrNext when rxval='1' and rising_edge(clk); 49 | 50 | wi <= '1' when state='1' and rxval='1' else '0'; 51 | wi_addr <= waddr; 52 | 53 | -- delay write indicator so when it fires the register already 54 | -- has the new value 55 | write_indicator <= wi when rising_edge(clk); 56 | write_indicator_addr <= wi_addr when rising_edge(clk); 57 | 58 | process(clk) 59 | begin 60 | if(rising_edge(clk)) then 61 | if(state='1' and rxval='1') then 62 | regs(to_integer(waddr)) <= rxdat; 63 | end if; 64 | end if; 65 | end process; 66 | 67 | end architecture; 68 | -------------------------------------------------------------------------------- /vhdl/common/spi_data_tx.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | library work; 3 | use ieee.numeric_std.all; 4 | use ieee.std_logic_1164.all; 5 | USE ieee.math_real.log2; 6 | USE ieee.math_real.ceil; 7 | 8 | entity spiDataTx is 9 | generic(words: integer; 10 | wordsize: integer; 11 | addrBits: integer := 3); 12 | 13 | -- data is transmitted MSB first 14 | port(datarom: std_logic_vector(words*wordsize-1 downto 0); 15 | clk,doSend: in std_logic; 16 | scl,le,sdi: out std_logic; 17 | startAddr: in unsigned(addrBits-1 downto 0) := to_unsigned(0, addrBits)); 18 | end entity; 19 | 20 | architecture a of spiDataTx is 21 | type rom_t is array(0 to words-1) of std_logic_vector(wordsize-1 downto 0); 22 | signal rom: rom_t; 23 | 24 | type states is (stop,load,send,done); 25 | signal state,stateNext: states; 26 | signal addr,addrNext: unsigned(addrBits-1 downto 0); 27 | signal cnt,cntNext: unsigned(7 downto 0); 28 | signal sr,srNext: unsigned(wordsize-1 downto 0); 29 | signal data: unsigned(wordsize-1 downto 0); 30 | signal clken,clkenNext: std_logic; 31 | 32 | signal outClk,outData,outLe,leNext: std_logic; 33 | begin 34 | assert(addrBits=integer(ceil(log2(real(words))))); 35 | -- cast datarom to internal type 36 | g: for I in 0 to words-1 generate 37 | rom(I) <= datarom((words-I)*wordsize-1 downto (words-I-1)*wordsize); 38 | end generate; 39 | 40 | state <= stateNext when rising_edge(clk); 41 | addr <= addrNext when rising_edge(clk); 42 | cnt <= cntNext when rising_edge(clk); 43 | sr <= srNext when rising_edge(clk); 44 | stateNext <= load when state=stop and doSend='1' else 45 | send when state=load else 46 | done when state=send and cnt=wordsize-1 else 47 | stop when state=done and addr=words-1 else 48 | load when state=done else 49 | state; 50 | cntNext <= to_unsigned(0,8) when state=stop else 51 | cnt+1 when state=send else 52 | to_unsigned(0,8); --when state=done else 53 | addrNext <= addr+1 when state=done else 54 | startAddr when state=stop else 55 | addr; 56 | srNext <= sr(wordsize-2 downto 0)&"0" when state=send else 57 | data; 58 | 59 | data <= unsigned(rom(to_integer(unsigned(addr)))); 60 | 61 | le <= leNext when rising_edge(clk); 62 | leNext <= '0' when state=send else 63 | '0' when state=done else 64 | '1'; 65 | clken <= clkenNext when rising_edge(clk); 66 | clkenNext <= '1' when state=send else '0'; 67 | scl <= clken and (not clk); 68 | sdi <= sr(wordsize-1) and clkenNext when rising_edge(clk); 69 | end architecture; 70 | -------------------------------------------------------------------------------- /vhdl/graphics_types.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | 5 | package graphics_types is 6 | type color is array(0 to 2) of unsigned(7 downto 0); 7 | type position is array(0 to 1) of unsigned(11 downto 0); 8 | constant position_zero: position := ("000000000000","000000000000"); 9 | end package; 10 | -------------------------------------------------------------------------------- /vhdl/ipcore_dir/clk_wiz_v3_6.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk_wiz_v3_6 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | LINE Normal 608 272 576 272 18 | PIN 608 272 RIGHT 36 19 | PINATTR PinName clk_out3 20 | PINATTR Polarity OUT 21 | LINE Normal 608 368 576 368 22 | PIN 608 368 RIGHT 36 23 | PINATTR PinName clk_out4 24 | PINATTR Polarity OUT 25 | LINE Normal 608 976 576 976 26 | PIN 608 976 RIGHT 36 27 | PINATTR PinName locked 28 | PINATTR Polarity OUT 29 | 30 | -------------------------------------------------------------------------------- /vhdl/ipcore_dir/clk_wiz_v3_6.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2017-9-1T5:3:31 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | clk_wiz_v3_6 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /vhdl/ipcore_dir/clk_wiz_v3_6_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | clk_wiz_v3_6/clk_wiz_v3_6_readme.txt 4 | clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt 5 | clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html 6 | clk_wiz_v3_6/doc/pg065_clk_wiz.pdf 7 | clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf 8 | clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.vhd 9 | clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc 10 | clk_wiz_v3_6/implement/implement.bat 11 | clk_wiz_v3_6/implement/implement.sh 12 | clk_wiz_v3_6/implement/planAhead_ise.bat 13 | clk_wiz_v3_6/implement/planAhead_ise.sh 14 | clk_wiz_v3_6/implement/planAhead_ise.tcl 15 | clk_wiz_v3_6/implement/planAhead_rdn.bat 16 | clk_wiz_v3_6/implement/planAhead_rdn.sh 17 | clk_wiz_v3_6/implement/planAhead_rdn.tcl 18 | clk_wiz_v3_6/implement/xst.prj 19 | clk_wiz_v3_6/implement/xst.scr 20 | clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.vhd 21 | clk_wiz_v3_6/simulation/functional/simcmds.tcl 22 | clk_wiz_v3_6/simulation/functional/simulate_isim.bat 23 | clk_wiz_v3_6/simulation/functional/simulate_isim.sh 24 | clk_wiz_v3_6/simulation/functional/simulate_mti.bat 25 | clk_wiz_v3_6/simulation/functional/simulate_mti.do 26 | clk_wiz_v3_6/simulation/functional/simulate_mti.sh 27 | clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh 28 | clk_wiz_v3_6/simulation/functional/simulate_vcs.sh 29 | clk_wiz_v3_6/simulation/functional/wave.do 30 | clk_wiz_v3_6/simulation/functional/wave.sv 31 | clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.vhd 32 | clk_wiz_v3_6/simulation/timing/sdf_cmd_file 33 | clk_wiz_v3_6/simulation/timing/simcmds.tcl 34 | clk_wiz_v3_6/simulation/timing/simulate_isim.sh 35 | clk_wiz_v3_6/simulation/timing/simulate_mti.bat 36 | clk_wiz_v3_6/simulation/timing/simulate_mti.do 37 | clk_wiz_v3_6/simulation/timing/simulate_mti.sh 38 | clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh 39 | clk_wiz_v3_6/simulation/timing/simulate_vcs.sh 40 | clk_wiz_v3_6/simulation/timing/ucli_commands.key 41 | clk_wiz_v3_6/simulation/timing/vcs_session.tcl 42 | clk_wiz_v3_6/simulation/timing/wave.do 43 | clk_wiz_v3_6.asy 44 | clk_wiz_v3_6.gise 45 | clk_wiz_v3_6.sym 46 | clk_wiz_v3_6.ucf 47 | clk_wiz_v3_6.vhd 48 | clk_wiz_v3_6.vho 49 | clk_wiz_v3_6.xco 50 | clk_wiz_v3_6.xdc 51 | clk_wiz_v3_6.xise 52 | clk_wiz_v3_6_flist.txt 53 | clk_wiz_v3_6_xmdf.tcl 54 | -------------------------------------------------------------------------------- /vhdl/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -3 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /vhdl/production/bitfile.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/vhdl/production/bitfile.bit -------------------------------------------------------------------------------- /vhdl/production/top2.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/vhdl/production/top2.bin -------------------------------------------------------------------------------- /vhdl/pulse_extender.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:06:12 06/12/2016 6 | -- Design Name: 7 | -- Module Name: pulse_extender - a 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | --use IEEE.NUMERIC_STD.ALL; 23 | entity pulseExtender is 24 | generic(registered: boolean := true; --whether to register the output 25 | extend: integer := 1); 26 | Port (clk : in STD_LOGIC; 27 | inp: in std_logic; 28 | outp: out std_logic); 29 | end pulseExtender; 30 | 31 | architecture a of pulseExtender is 32 | signal sr: std_logic_vector(extend downto 0); 33 | signal ors: std_logic_vector(extend downto 0); 34 | begin 35 | g: for I in 1 to extend generate 36 | sr(I) <= sr(I-1) when rising_edge(clk); 37 | ors(I) <= ors(I-1) or sr(I); 38 | end generate; 39 | sr(0) <= inp; 40 | ors(0) <= inp; 41 | g2:if registered generate 42 | outp <= ors(extend) when rising_edge(clk); 43 | end generate; 44 | g3:if not registered generate 45 | outp <= ors(extend); 46 | end generate; 47 | end a; 48 | 49 | library IEEE; 50 | use IEEE.STD_LOGIC_1164.ALL; 51 | use IEEE.NUMERIC_STD.ALL; 52 | USE ieee.math_real.log2; 53 | USE ieee.math_real.ceil; 54 | entity pulseExtenderCounted is 55 | generic(extend: integer := 32); 56 | Port (clk : in STD_LOGIC; 57 | inp: in std_logic; 58 | outp: out std_logic); 59 | end pulseExtenderCounted; 60 | 61 | architecture a of pulseExtenderCounted is 62 | constant bits: integer := integer(ceil(log2(real(extend+2)))); 63 | signal state, stateNext: unsigned(bits-1 downto 0) := (others=>'0'); 64 | signal outNext: std_logic; 65 | begin 66 | stateNext <= to_unsigned(1, bits) when inp='1' else 67 | to_unsigned(0, bits) when state=0 else 68 | to_unsigned(0, bits) when state=extend else 69 | state+1; 70 | state <= stateNext when rising_edge(clk); 71 | outNext <= '0' when stateNext=0 else '1'; 72 | outp <= outNext when rising_edge(clk); 73 | end a; 74 | 75 | -------------------------------------------------------------------------------- /vhdl/reset_generator.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | library work; 3 | use ieee.numeric_std.all; 4 | use ieee.std_logic_1164.all; 5 | entity resetGenerator is 6 | generic(cnt: integer := 100); 7 | port(clk: in std_logic; 8 | rst: out std_logic); 9 | end entity; 10 | architecture a of resetGenerator is 11 | signal counter,counterNext: unsigned(31 downto 0) := to_unsigned(0,32); 12 | signal tmp: std_logic; 13 | begin 14 | counterNext <= to_unsigned(cnt,32) when counter=cnt else counter+1; 15 | counter <= counterNext when rising_edge(clk); 16 | tmp <= '0' when counter=cnt else '1'; 17 | rst <= tmp when rising_edge(clk); 18 | end architecture; 19 | -------------------------------------------------------------------------------- /vhdl/slow_clock.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.numeric_std.all; 3 | use ieee.std_logic_1164.all; 4 | USE ieee.math_real.log2; 5 | USE ieee.math_real.ceil; 6 | 7 | -- output will start from 1 2 clock cycles after rst is pulsed 8 | entity slow_clock is 9 | generic (divide: integer := 50000000; 10 | dutycycle: integer := 20000000); 11 | port (clk: in std_logic; 12 | o: out std_logic; 13 | rst: in std_logic := '0'; 14 | phase: out unsigned(integer(ceil(log2(real(divide))))-1 downto 0) 15 | := (others=>'X'); 16 | skip: in std_logic := '0'); 17 | end; 18 | 19 | architecture a of slow_clock is 20 | constant b: integer := integer(ceil(log2(real(divide)))); 21 | signal cs,ns: unsigned(b-1 downto 0); 22 | signal next_out: std_logic; 23 | begin 24 | cs <= ns when rising_edge(clk); 25 | ns <= to_unsigned(0,b) when rst='1' else 26 | cs+2 when cs<(divide-2) and skip='1' else 27 | to_unsigned(1,b) when skip='1' else 28 | cs+1 when cs<(divide-1) else 29 | to_unsigned(0,b); 30 | next_out <= '1' when cs 21 | -case maintain 22 | -slice_utilization_ratio 100 23 | -verilog2001 yes 24 | -fsm_extract yes 25 | -fsm_encoding auto 26 | -fsm_style lut 27 | -ram_extract yes 28 | -ram_style auto 29 | -rom_extract yes 30 | -rom_style auto 31 | -mux_extract yes 32 | -mux_style auto 33 | -decoder_extract yes 34 | -priority_extract yes 35 | -shreg_extract yes 36 | -shift_extract yes 37 | -xor_collapse yes 38 | -resource_sharing yes 39 | -mult_style auto 40 | -iobuf yes 41 | -max_fanout 500 42 | -bufg 8 43 | -register_duplication yes 44 | -equivalent_register_removal yes 45 | -register_balancing no 46 | -slice_packing yes 47 | -optimize_primitives no 48 | -iob auto 49 | -------------------------------------------------------------------------------- /vhdl/top.xdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xaxaxa-dev/vna/272fc6f9125a468b0881f3a059458721ee699e4b/vhdl/top.xdl -------------------------------------------------------------------------------- /vhdl_twoport/.gitignore: -------------------------------------------------------------------------------- 1 | *.svf 2 | *.b64 3 | *.tcl 4 | *.debug 5 | planAhead_* 6 | ipcore_dir/*/* 7 | 8 | # intermediate build files 9 | *.bgn 10 | *.bit 11 | *.bld 12 | *.cmd_log 13 | *.drc 14 | *.ll 15 | *.lso 16 | *.msd 17 | *.msk 18 | *.ncd 19 | *.ngc 20 | *.ngd 21 | *.ngr 22 | *.pad 23 | *.par 24 | *.pcf 25 | *.prj 26 | *.ptwx 27 | *.rbb 28 | *.rbd 29 | *.stx 30 | *.syr 31 | *.twr 32 | *.twx 33 | *.unroutes 34 | *.ut 35 | *.xpi 36 | *.xst 37 | *_bitgen.xwbt 38 | *_envsettings.html 39 | *_map.map 40 | *_map.mrp 41 | *_map.ngm 42 | *_map.xrpt 43 | *_ngdbuild.xrpt 44 | *_pad.csv 45 | *_pad.txt 46 | *_par.xrpt 47 | *_summary.html 48 | *_summary.xml 49 | *_usage.xml 50 | *_xst.xrpt 51 | 52 | # iMPACT generated files 53 | _impactbatch.log 54 | impact.xsl 55 | impact_impact.xwbt 56 | ise_impact.cmd 57 | webtalk_impact.xml 58 | 59 | # Core Generator generated files 60 | xaw2verilog.log 61 | 62 | # project-wide generated files 63 | *.gise 64 | par_usage_statistics.html 65 | usage_statistics_webtalk.html 66 | webtalk.log 67 | webtalk_pn.xml 68 | 69 | # generated folders 70 | iseconfig/ 71 | xlnx_auto_0_xdb/ 72 | xst/ 73 | _ngo/ 74 | _xmsgs/ 75 | -------------------------------------------------------------------------------- /vhdl_twoport/ipcore_dir/clk_wiz_v3_6.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk_wiz_v3_6 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | LINE Normal 608 272 576 272 18 | PIN 608 272 RIGHT 36 19 | PINATTR PinName clk_out3 20 | PINATTR Polarity OUT 21 | LINE Normal 608 368 576 368 22 | PIN 608 368 RIGHT 36 23 | PINATTR PinName clk_out4 24 | PINATTR Polarity OUT 25 | LINE Normal 608 976 576 976 26 | PIN 608 976 RIGHT 36 27 | PINATTR PinName locked 28 | PINATTR Polarity OUT 29 | 30 | -------------------------------------------------------------------------------- /vhdl_twoport/ipcore_dir/clk_wiz_v3_6.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2018-5-19T5:16:51 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | clk_wiz_v3_6 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /vhdl_twoport/ipcore_dir/clk_wiz_v3_6_2.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk_wiz_v3_6_2 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | LINE Normal 608 976 576 976 18 | PIN 608 976 RIGHT 36 19 | PINATTR PinName locked 20 | PINATTR Polarity OUT 21 | 22 | -------------------------------------------------------------------------------- /vhdl_twoport/ipcore_dir/clk_wiz_v3_6_2.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2018-9-6T10:50:22 5 | 6 | 7 | 8 | 9 | 10 | clk_wiz_v3_6_2 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /vhdl_twoport/ipcore_dir/clk_wiz_v3_6_2_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | clk_wiz_v3_6_2/clk_wiz_v3_6_readme.txt 4 | clk_wiz_v3_6_2/doc/clk_wiz_v3_6_readme.txt 5 | clk_wiz_v3_6_2/doc/clk_wiz_v3_6_vinfo.html 6 | clk_wiz_v3_6_2/doc/pg065_clk_wiz.pdf 7 | clk_wiz_v3_6_2/example_design/clk_wiz_v3_6_2_exdes.ucf 8 | clk_wiz_v3_6_2/example_design/clk_wiz_v3_6_2_exdes.vhd 9 | clk_wiz_v3_6_2/example_design/clk_wiz_v3_6_2_exdes.xdc 10 | clk_wiz_v3_6_2/implement/implement.bat 11 | clk_wiz_v3_6_2/implement/implement.sh 12 | clk_wiz_v3_6_2/implement/planAhead_ise.bat 13 | clk_wiz_v3_6_2/implement/planAhead_ise.sh 14 | clk_wiz_v3_6_2/implement/planAhead_ise.tcl 15 | clk_wiz_v3_6_2/implement/planAhead_rdn.bat 16 | clk_wiz_v3_6_2/implement/planAhead_rdn.sh 17 | clk_wiz_v3_6_2/implement/planAhead_rdn.tcl 18 | clk_wiz_v3_6_2/implement/xst.prj 19 | clk_wiz_v3_6_2/implement/xst.scr 20 | clk_wiz_v3_6_2/simulation/clk_wiz_v3_6_2_tb.vhd 21 | clk_wiz_v3_6_2/simulation/functional/simcmds.tcl 22 | clk_wiz_v3_6_2/simulation/functional/simulate_isim.bat 23 | clk_wiz_v3_6_2/simulation/functional/simulate_isim.sh 24 | clk_wiz_v3_6_2/simulation/functional/simulate_mti.bat 25 | clk_wiz_v3_6_2/simulation/functional/simulate_mti.do 26 | clk_wiz_v3_6_2/simulation/functional/simulate_mti.sh 27 | clk_wiz_v3_6_2/simulation/functional/simulate_ncsim.sh 28 | clk_wiz_v3_6_2/simulation/functional/simulate_vcs.sh 29 | clk_wiz_v3_6_2/simulation/functional/wave.do 30 | clk_wiz_v3_6_2/simulation/functional/wave.sv 31 | clk_wiz_v3_6_2/simulation/timing/clk_wiz_v3_6_2_tb.vhd 32 | clk_wiz_v3_6_2/simulation/timing/sdf_cmd_file 33 | clk_wiz_v3_6_2/simulation/timing/simcmds.tcl 34 | clk_wiz_v3_6_2/simulation/timing/simulate_isim.sh 35 | clk_wiz_v3_6_2/simulation/timing/simulate_mti.bat 36 | clk_wiz_v3_6_2/simulation/timing/simulate_mti.do 37 | clk_wiz_v3_6_2/simulation/timing/simulate_mti.sh 38 | clk_wiz_v3_6_2/simulation/timing/simulate_ncsim.sh 39 | clk_wiz_v3_6_2/simulation/timing/simulate_vcs.sh 40 | clk_wiz_v3_6_2/simulation/timing/ucli_commands.key 41 | clk_wiz_v3_6_2/simulation/timing/vcs_session.tcl 42 | clk_wiz_v3_6_2/simulation/timing/wave.do 43 | clk_wiz_v3_6_2.asy 44 | clk_wiz_v3_6_2.gise 45 | clk_wiz_v3_6_2.sym 46 | clk_wiz_v3_6_2.ucf 47 | clk_wiz_v3_6_2.vhd 48 | clk_wiz_v3_6_2.vho 49 | clk_wiz_v3_6_2.xco 50 | clk_wiz_v3_6_2.xdc 51 | clk_wiz_v3_6_2.xise 52 | clk_wiz_v3_6_2_flist.txt 53 | clk_wiz_v3_6_2_xmdf.tcl 54 | -------------------------------------------------------------------------------- /vhdl_twoport/ipcore_dir/clk_wiz_v3_6_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | clk_wiz_v3_6/clk_wiz_v3_6_readme.txt 4 | clk_wiz_v3_6/doc/clk_wiz_v3_6_readme.txt 5 | clk_wiz_v3_6/doc/clk_wiz_v3_6_vinfo.html 6 | clk_wiz_v3_6/doc/pg065_clk_wiz.pdf 7 | clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.ucf 8 | clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.vhd 9 | clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.xdc 10 | clk_wiz_v3_6/implement/implement.bat 11 | clk_wiz_v3_6/implement/implement.sh 12 | clk_wiz_v3_6/implement/planAhead_ise.bat 13 | clk_wiz_v3_6/implement/planAhead_ise.sh 14 | clk_wiz_v3_6/implement/planAhead_ise.tcl 15 | clk_wiz_v3_6/implement/planAhead_rdn.bat 16 | clk_wiz_v3_6/implement/planAhead_rdn.sh 17 | clk_wiz_v3_6/implement/planAhead_rdn.tcl 18 | clk_wiz_v3_6/implement/xst.prj 19 | clk_wiz_v3_6/implement/xst.scr 20 | clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.vhd 21 | clk_wiz_v3_6/simulation/functional/simcmds.tcl 22 | clk_wiz_v3_6/simulation/functional/simulate_isim.bat 23 | clk_wiz_v3_6/simulation/functional/simulate_isim.sh 24 | clk_wiz_v3_6/simulation/functional/simulate_mti.bat 25 | clk_wiz_v3_6/simulation/functional/simulate_mti.do 26 | clk_wiz_v3_6/simulation/functional/simulate_mti.sh 27 | clk_wiz_v3_6/simulation/functional/simulate_ncsim.sh 28 | clk_wiz_v3_6/simulation/functional/simulate_vcs.sh 29 | clk_wiz_v3_6/simulation/functional/wave.do 30 | clk_wiz_v3_6/simulation/functional/wave.sv 31 | clk_wiz_v3_6/simulation/timing/clk_wiz_v3_6_tb.vhd 32 | clk_wiz_v3_6/simulation/timing/sdf_cmd_file 33 | clk_wiz_v3_6/simulation/timing/simcmds.tcl 34 | clk_wiz_v3_6/simulation/timing/simulate_isim.sh 35 | clk_wiz_v3_6/simulation/timing/simulate_mti.bat 36 | clk_wiz_v3_6/simulation/timing/simulate_mti.do 37 | clk_wiz_v3_6/simulation/timing/simulate_mti.sh 38 | clk_wiz_v3_6/simulation/timing/simulate_ncsim.sh 39 | clk_wiz_v3_6/simulation/timing/simulate_vcs.sh 40 | clk_wiz_v3_6/simulation/timing/ucli_commands.key 41 | clk_wiz_v3_6/simulation/timing/vcs_session.tcl 42 | clk_wiz_v3_6/simulation/timing/wave.do 43 | clk_wiz_v3_6.asy 44 | clk_wiz_v3_6.gise 45 | clk_wiz_v3_6.sym 46 | clk_wiz_v3_6.ucf 47 | clk_wiz_v3_6.vhd 48 | clk_wiz_v3_6.vho 49 | clk_wiz_v3_6.xco 50 | clk_wiz_v3_6.xdc 51 | clk_wiz_v3_6.xise 52 | clk_wiz_v3_6_flist.txt 53 | clk_wiz_v3_6_xmdf.tcl 54 | -------------------------------------------------------------------------------- /vhdl_twoport/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /vhdl_twoport/spiflash.cfi: -------------------------------------------------------------------------------- 1 | # PROMGEN: Xilinx Prom Generator P.20131013 2 | # Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | SOFTWARE_VERSION P.20131013 5 | DATE 5/24/2018 - 17:48 6 | SOURCE spiflash.mcs 7 | DEVICE 512K 8 | DATA_WIDTH 4 9 | FILL_DATA 0xFF 10 | START_ADDRESS 0x00000000 END_ADDRESS 0x000534EB DIRECTION_UP "top.bit" 6slx9tqg144 11 | -------------------------------------------------------------------------------- /vhdl_twoport/spiflash.prm: -------------------------------------------------------------------------------- 1 | PROMGEN: Xilinx Prom Generator P.20131013 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | promgen -spi -p mcs -o spiflash.mcs -s 512 -u 0 top.bit -w 5 | 6 | PROM spiflash.prm map: Thu May 24 17:48:50 2018 7 | 8 | Format Mcs86 (32-bit) 9 | Size 512K 10 | PROM start 0000:0000 11 | PROM end 0007:ffff 12 | 13 | Addr1 Addr2 Date File(s) 14 | 0000:0000 0005:34eb May 24 17:48:39 2018 top.bit 15 | -------------------------------------------------------------------------------- /vna_diagtool/main.cpp: -------------------------------------------------------------------------------- 1 | #include "mainwindow.H" 2 | #include 3 | 4 | int main(int argc, char *argv[]) 5 | { 6 | QApplication a(argc, argv); 7 | a.setStyle("fusion"); 8 | MainWindow w; 9 | w.show(); 10 | 11 | return a.exec(); 12 | } 13 | -------------------------------------------------------------------------------- /vna_diagtool/mainwindow.H: -------------------------------------------------------------------------------- 1 | #ifndef MAINWINDOW_H 2 | #define MAINWINDOW_H 3 | 4 | #include 5 | #include 6 | #include 7 | namespace Ui { 8 | class MainWindow; 9 | } 10 | 11 | namespace QtCharts { 12 | class QChartView; 13 | class QChart; 14 | class QValueAxis; 15 | class QLineSeries; 16 | } 17 | namespace xaxaxa { 18 | class VNADevice; 19 | class VNACalibration; 20 | } 21 | class QTimer; 22 | class MarkerSlider; 23 | class QTextStream; 24 | 25 | using namespace QtCharts; 26 | using namespace xaxaxa; 27 | using namespace std; 28 | 29 | class MainWindow : public QMainWindow 30 | { 31 | Q_OBJECT 32 | 33 | public: 34 | explicit MainWindow(QWidget *parent = 0); 35 | ~MainWindow(); 36 | 37 | void populateDevicesMenu(); 38 | void openDevice(string dev); 39 | double freqAt(int i); 40 | void setCallbacks(); 41 | public slots: 42 | void updateViews(int freqIndex); 43 | void handleBackgroundError(QString msg); 44 | void on_menuDevice_aboutToShow(); 45 | private slots: 46 | void on_slider_valueChanged(int value); 47 | 48 | void on_r_port1_clicked(); 49 | 50 | void on_r_port2_clicked(); 51 | 52 | private: 53 | Ui::MainWindow *ui; 54 | VNADevice* vna=NULL; 55 | int excitation=0; 56 | 57 | vector, 4> > > rawValues; 58 | 59 | 60 | QChart* chart; 61 | QChartView* chartView; 62 | vector series; 63 | QValueAxis* axisX; 64 | QValueAxis* axisY; 65 | }; 66 | 67 | inline QString qs(const string& s) { 68 | return QString::fromStdString(s); 69 | } 70 | 71 | inline double dB(double power) { 72 | return log10(power)*10; 73 | } 74 | 75 | #endif // MAINWINDOW_H 76 | -------------------------------------------------------------------------------- /vna_diagtool/vna_diagtool.pro: -------------------------------------------------------------------------------- 1 | #------------------------------------------------- 2 | # 3 | # Project created by QtCreator 2018-04-26T10:12:14 4 | # 5 | #------------------------------------------------- 6 | 7 | QT += core gui charts 8 | 9 | greaterThan(QT_MAJOR_VERSION, 4): QT += widgets 10 | 11 | TARGET = vna_diagtool 12 | TEMPLATE = app 13 | 14 | # The following define makes your compiler emit warnings if you use 15 | # any feature of Qt which has been marked as deprecated (the exact warnings 16 | # depend on your compiler). Please consult the documentation of the 17 | # deprecated API in order to know how to port your code away from it. 18 | DEFINES += QT_DEPRECATED_WARNINGS 19 | 20 | # You can also make your code fail to compile if you use deprecated APIs. 21 | # In order to do so, uncomment the following line. 22 | # You can also select to disable deprecated APIs only up to a certain version of Qt. 23 | #DEFINES += QT_DISABLE_DEPRECATED_BEFORE=0x060000 # disables all the APIs deprecated before Qt 6.0.0 24 | 25 | 26 | SOURCES += \ 27 | main.cpp \ 28 | mainwindow.C 29 | 30 | HEADERS += \ 31 | mainwindow.H 32 | 33 | FORMS += \ 34 | mainwindow.ui 35 | 36 | INCLUDEPATH += $$PWD/../include /usr/local/include 37 | DEPENDPATH += $$PWD/../include 38 | 39 | win32:CONFIG(release, debug|release): LIBS += -L$$PWD/../libxavna/xavna_mock_ui/release/ -lxavna_mock_ui 40 | else:win32:CONFIG(debug, debug|release): LIBS += -L$$PWD/../libxavna/xavna_mock_ui/debug/ -lxavna_mock_ui 41 | else:unix: LIBS += -L$$PWD/../libxavna/xavna_mock_ui/ -lxavna_mock_ui 42 | 43 | LIBS += -L$$PWD/../libxavna/.libs/ -L/usr/local/lib/ -lxavna 44 | android: LIBS += -L$$PWD/../lib 45 | 46 | -------------------------------------------------------------------------------- /vna_gtk/common_types.h: -------------------------------------------------------------------------------- 1 | #ifndef __COMMON_TYPES_H 2 | #define __COMMON_TYPES_H 3 | #include 4 | 5 | typedef unsigned long ul; 6 | typedef unsigned int ui; 7 | typedef long long ll; 8 | typedef unsigned long long ull; 9 | typedef uint64_t u64; 10 | typedef uint32_t u32; 11 | typedef uint16_t u16; 12 | typedef uint8_t u8; 13 | typedef int8_t s8; 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /vna_gtk/configure.ac: -------------------------------------------------------------------------------- 1 | AC_INIT(vna, version-0.1, private0x01@gmail.com) 2 | 3 | if test -z $CXXFLAGS; then 4 | CXXFLAGS='-O2 -std=c++0x -fPIC -fwrapv -fno-delete-null-pointer-checks -funsigned-char -fno-strict-aliasing -Wno-pmf-conversions' 5 | fi 6 | 7 | AC_PROG_CXX 8 | AC_LANG(C++) 9 | 10 | AC_SUBST(EXTRA_LIBRARIES) 11 | AC_SUBST(EXTRA_SOURCES) 12 | 13 | PKG_CHECK_MODULES([GTK], [gtkmm-3.0]) 14 | PKG_CHECK_MODULES([FFTW], [fftw3]) 15 | 16 | AC_OUTPUT(Makefile) 17 | -------------------------------------------------------------------------------- /vna_qt/.gitignore: -------------------------------------------------------------------------------- 1 | vna_qt 2 | *-deployment-settings.json 3 | 4 | -------------------------------------------------------------------------------- /vna_qt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | include_directories(${Qt5Charts_INCLUDE_DIRS}) 3 | 4 | # Instruct CMake to run moc automatically when needed 5 | set(CMAKE_AUTOMOC ON) 6 | # Create code from a list of Qt designer ui files 7 | set(CMAKE_AUTOUIC ON) 8 | 9 | set(vna_qt_SRCS 10 | polarview.C 11 | mainwindow.C 12 | main.C 13 | markerslider.C 14 | impedancedisplay.C 15 | frequencydialog.C 16 | graphpanel.C 17 | configureviewdialog.C 18 | touchstone.C 19 | calkitsettingsdialog.C 20 | calkitsettings.C 21 | networkview.C 22 | dtfwindow.C) 23 | 24 | set(vna_qt_FRMS 25 | mainwindow.ui 26 | markerslider.ui 27 | impedancedisplay.ui 28 | frequencydialog.ui 29 | graphpanel.ui 30 | configureviewdialog.ui 31 | calkitsettingsdialog.ui 32 | calkitsettingswidget.ui 33 | dtfwindow.ui 34 | graphlimitsdialog.ui) 35 | 36 | set(vna_qt_HDRS 37 | polarview.H 38 | mainwindow.H 39 | markerslider.H 40 | impedancedisplay.H 41 | utility.H 42 | frequencydialog.H 43 | graphpanel.H 44 | configureviewdialog.H 45 | touchstone.H 46 | calkitsettingsdialog.H 47 | calkitsettings.H 48 | networkview.H 49 | dtfwindow.H) 50 | 51 | 52 | add_executable(vna_qt ${vna_qt_SRCS} ${vna_qt_FRMS} ${vna_qt_HDRS}) 53 | 54 | target_link_libraries(vna_qt Qt5::Charts ${FFTW3_LIBRARIES} xavna xavna_mock_ui) 55 | 56 | # Install destinations 57 | install(TARGETS vna_qt RUNTIME DESTINATION ${BIN_INSTALL_DIR}) 58 | -------------------------------------------------------------------------------- /vna_qt/calkitsettings.H: -------------------------------------------------------------------------------- 1 | #ifndef CALKITSETTINGS_H 2 | #define CALKITSETTINGS_H 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include "touchstone.H" 9 | using namespace std; 10 | using namespace xaxaxa; 11 | 12 | // the in-memory structure that holds the calibration kit settings 13 | struct CalKitSettings { 14 | // if any given cal kit type is not present here, it should be assumed 15 | // to use ideal parameters 16 | map calKitModels; 17 | map calKitNames; 18 | }; 19 | #ifdef Q_DECLARE_METATYPE 20 | Q_DECLARE_METATYPE(CalKitSettings); 21 | #endif 22 | 23 | class QDataStream; 24 | 25 | // binary serializers for QSettings 26 | 27 | QDataStream &operator<<(QDataStream &out, const complex &myObj); 28 | QDataStream &operator>>(QDataStream &in, complex &myObj); 29 | 30 | QDataStream &operator<<(QDataStream &out, const string &myObj); 31 | QDataStream &operator>>(QDataStream &in, string &myObj); 32 | 33 | QDataStream &operator<<(QDataStream &out, const MatrixXcd &myObj); 34 | QDataStream &operator>>(QDataStream &in, MatrixXcd &myObj); 35 | 36 | QDataStream &operator<<(QDataStream &out, const SParamSeries &myObj); 37 | QDataStream &operator>>(QDataStream &in, SParamSeries &myObj); 38 | 39 | QDataStream &operator<<(QDataStream &out, const CalKitSettings &myObj); 40 | QDataStream &operator>>(QDataStream &in, CalKitSettings &myObj); 41 | 42 | // text serializers 43 | void serialize(ostream& out, const SParamSeries& obj); 44 | void deserialize(istream& in, SParamSeries& obj); 45 | 46 | void serialize(ostream& out, const CalKitSettings& obj); 47 | void deserialize(istream &in, CalKitSettings &obj); 48 | 49 | #endif // CALKITSETTINGS_H 50 | -------------------------------------------------------------------------------- /vna_qt/calkitsettingsdialog.H: -------------------------------------------------------------------------------- 1 | #ifndef CALKITSETTINGSDIALOG_H 2 | #define CALKITSETTINGSDIALOG_H 3 | 4 | #include 5 | #include "calkitsettings.H" 6 | #include "ui_calkitsettingswidget.h" 7 | namespace Ui { 8 | class CalKitSettingsDialog; 9 | } 10 | 11 | class CalKitSettingsDialog : public QDialog 12 | { 13 | Q_OBJECT 14 | 15 | struct calKitInfo { 16 | Ui::CalKitSettingsWidget ui; 17 | SParamSeries data; 18 | bool useIdeal; 19 | }; 20 | public: 21 | explicit CalKitSettingsDialog(QWidget *parent = 0); 22 | ~CalKitSettingsDialog(); 23 | 24 | void fromSettings(const CalKitSettings& settings); 25 | void toSettings(CalKitSettings& settings); 26 | 27 | map info; 28 | private: 29 | Ui::CalKitSettingsDialog *ui; 30 | }; 31 | 32 | #endif // CALKITSETTINGSDIALOG_H 33 | -------------------------------------------------------------------------------- /vna_qt/configureviewdialog.C: -------------------------------------------------------------------------------- 1 | #include "configureviewdialog.H" 2 | #include "ui_configureviewdialog.h" 3 | 4 | ConfigureViewDialog::ConfigureViewDialog(QWidget *parent) : 5 | QDialog(parent), 6 | ui(new Ui::ConfigureViewDialog) 7 | { 8 | ui->setupUi(this); 9 | } 10 | 11 | ConfigureViewDialog::~ConfigureViewDialog() 12 | { 13 | delete ui; 14 | } 15 | -------------------------------------------------------------------------------- /vna_qt/configureviewdialog.H: -------------------------------------------------------------------------------- 1 | #ifndef CONFIGUREVIEWDIALOG_H 2 | #define CONFIGUREVIEWDIALOG_H 3 | 4 | #include 5 | 6 | namespace Ui { 7 | class ConfigureViewDialog; 8 | } 9 | 10 | class ConfigureViewDialog : public QDialog 11 | { 12 | Q_OBJECT 13 | 14 | public: 15 | explicit ConfigureViewDialog(QWidget *parent = 0); 16 | ~ConfigureViewDialog(); 17 | 18 | private: 19 | Ui::ConfigureViewDialog *ui; 20 | }; 21 | 22 | #endif // CONFIGUREVIEWDIALOG_H 23 | -------------------------------------------------------------------------------- /vna_qt/dtfwindow.H: -------------------------------------------------------------------------------- 1 | #ifndef DTFWINDOW_H 2 | #define DTFWINDOW_H 3 | 4 | #include 5 | #include 6 | #include "networkview.H" 7 | 8 | namespace Ui { 9 | class DTFWindow; 10 | } 11 | 12 | class DTFWindow : public QMainWindow 13 | { 14 | Q_OBJECT 15 | 16 | public: 17 | NetworkView nv; 18 | fftw_plan p; 19 | complex* fft_in = nullptr; 20 | complex* fft_out = nullptr; 21 | complex* fft_window = nullptr; 22 | 23 | double timeScale = 1e9; 24 | explicit DTFWindow(QWidget *parent = 0); 25 | ~DTFWindow(); 26 | 27 | void initFFT(int sz); 28 | void deinitFFT(); 29 | void updateSweepParams(double stepFreqHz, int nPoints); 30 | void updateValues(const vector& freqDomainValues); 31 | signals: 32 | void hidden(); 33 | protected: 34 | void closeEvent(QCloseEvent *event); 35 | private: 36 | Ui::DTFWindow *ui; 37 | }; 38 | 39 | #endif // DTFWINDOW_H 40 | -------------------------------------------------------------------------------- /vna_qt/frequencydialog.H: -------------------------------------------------------------------------------- 1 | #ifndef FREQUENCYDIALOG_H 2 | #define FREQUENCYDIALOG_H 3 | 4 | #include 5 | #include 6 | 7 | namespace Ui { 8 | class FrequencyDialog; 9 | } 10 | namespace xaxaxa { 11 | class VNADevice; 12 | } 13 | using namespace xaxaxa; 14 | class FrequencyDialog : public QDialog 15 | { 16 | Q_OBJECT 17 | 18 | public: 19 | explicit FrequencyDialog(QWidget *parent = 0); 20 | ~FrequencyDialog(); 21 | 22 | // populate the UI with parameters from dev 23 | void fromVNA(const VNADevice& dev); 24 | 25 | // update dev with parameters from the UI 26 | // returns true if frequency parameters were changed, false otherwise 27 | bool toVNA(VNADevice& dev); 28 | 29 | void updateLabels(); 30 | 31 | private slots: 32 | void on_slider_power_valueChanged(int value); 33 | void on_t_start_valueChanged(const QString &arg1); 34 | void on_t_stop_valueChanged(const QString &arg1); 35 | void on_t_points_valueChanged(const QString &arg1); 36 | 37 | void on_c_advanced_stateChanged(int); 38 | 39 | private: 40 | Ui::FrequencyDialog *ui; 41 | }; 42 | 43 | #endif // FREQUENCYDIALOG_H 44 | -------------------------------------------------------------------------------- /vna_qt/graphpanel.H: -------------------------------------------------------------------------------- 1 | #ifndef GRAPHPANEL_H 2 | #define GRAPHPANEL_H 3 | 4 | #include 5 | #include 6 | 7 | namespace Ui { 8 | class GraphPanel; 9 | } 10 | namespace QtCharts { 11 | class QChartView; 12 | class QChart; 13 | class QValueAxis; 14 | class QLineSeries; 15 | } 16 | class QComboBox; 17 | class QPushButton; 18 | 19 | using namespace QtCharts; 20 | using namespace std; 21 | class GraphPanel : public QWidget 22 | { 23 | Q_OBJECT 24 | 25 | public: 26 | explicit GraphPanel(QWidget *parent = 0); 27 | ~GraphPanel(); 28 | 29 | QChart* chart; 30 | QChartView* chartView; 31 | vector series; 32 | QValueAxis* axisX; 33 | vector axisY; 34 | 35 | // combo box 0 is the leftmost one; 1 is the rightmost one 36 | void populateComboBox(int index, const vector& items); 37 | QComboBox* comboBox(int index); 38 | QPushButton* maximizeButton(); 39 | 40 | signals: 41 | void comboBoxSelectionChanged(int index, int selection); 42 | 43 | private slots: 44 | void on_d1_currentIndexChanged(int index); 45 | void on_d2_currentIndexChanged(int index); 46 | 47 | private: 48 | Ui::GraphPanel *ui; 49 | }; 50 | 51 | #endif // GRAPHPANEL_H 52 | -------------------------------------------------------------------------------- /vna_qt/impedancedisplay.C: -------------------------------------------------------------------------------- 1 | #include "utility.H" 2 | #include "impedancedisplay.H" 3 | #include "ui_impedancedisplay.h" 4 | 5 | 6 | ImpedanceDisplay::ImpedanceDisplay(QWidget *parent) : 7 | QWidget(parent), 8 | ui(new Ui::ImpedanceDisplay) 9 | { 10 | ui->setupUi(this); 11 | } 12 | 13 | ImpedanceDisplay::~ImpedanceDisplay() 14 | { 15 | delete ui; 16 | } 17 | 18 | void ImpedanceDisplay::setValue(complex s11, double freqHz, double z0) { 19 | complex Z = -z0*(s11+1.)/(s11-1.); 20 | complex Y = -(s11-1.)/(z0*(s11+1.)); 21 | 22 | ui->l_impedance->setText(qs(ssprintf(127, " %.2f\n%s j%.2f", Z.real(), Z.imag()>=0 ? "+" : "-", fabs(Z.imag())))); 23 | ui->l_admittance->setText(qs(ssprintf(127, " %.4f\n%s j%.4f", Y.real(), Y.imag()>=0 ? "+" : "-", fabs(Y.imag())))); 24 | ui->l_s_admittance->setText(qs(ssprintf(127, " %.4f\n%s j%.4f", 1./Z.real(), Z.imag()>=0 ? "+" : "-", fabs(1./Z.imag())))); 25 | ui->l_p_impedance->setText(qs(ssprintf(127, " %.2f\n|| j%.2f", 1./Y.real(), 1./Y.imag()))); 26 | 27 | double value = capacitance_inductance(freqHz, Z.imag()); 28 | ui->l_series->setText(qs(ssprintf(127, "%.2f Ω\n%.2f %s%s", Z.real(), fabs(si_scale(value)), si_unit(value), value>0?"H":"F"))); 29 | 30 | value = capacitance_inductance_Y(freqHz, Y.imag()); 31 | ui->l_parallel->setText(qs(ssprintf(127, "%.2f Ω\n%.2f %s%s", 1./Y.real(), fabs(si_scale(value)), si_unit(value), value>0?"H":"F"))); 32 | } 33 | 34 | void ImpedanceDisplay::clearValue() { 35 | QString p = "-"; 36 | ui->l_impedance->setText(p); 37 | ui->l_admittance->setText(p); 38 | ui->l_s_admittance->setText(p); 39 | ui->l_p_impedance->setText(p); 40 | ui->l_series->setText(p); 41 | ui->l_parallel->setText(p); 42 | } 43 | -------------------------------------------------------------------------------- /vna_qt/impedancedisplay.H: -------------------------------------------------------------------------------- 1 | #ifndef IMPEDANCEDISPLAY_H 2 | #define IMPEDANCEDISPLAY_H 3 | 4 | #include 5 | #include 6 | 7 | using namespace std; 8 | namespace Ui { 9 | class ImpedanceDisplay; 10 | } 11 | 12 | class ImpedanceDisplay : public QWidget 13 | { 14 | Q_OBJECT 15 | 16 | public: 17 | explicit ImpedanceDisplay(QWidget *parent = 0); 18 | ~ImpedanceDisplay(); 19 | 20 | void setValue(complex s11, double freqHz, double z0=50.); 21 | void clearValue(); 22 | 23 | private: 24 | Ui::ImpedanceDisplay *ui; 25 | }; 26 | 27 | #endif // IMPEDANCEDISPLAY_H 28 | -------------------------------------------------------------------------------- /vna_qt/main.C: -------------------------------------------------------------------------------- 1 | #include "mainwindow.H" 2 | #include "calkitsettings.H" 3 | #include 4 | #include 5 | 6 | int main(int argc, char *argv[]) 7 | { 8 | qRegisterMetaType("string"); 9 | qRegisterMetaType("CalKitSettings"); 10 | qRegisterMetaTypeStreamOperators("CalKitSettings"); 11 | 12 | QCoreApplication::setOrganizationName("xaxaxa Development Ltd"); 13 | QCoreApplication::setApplicationName("xaVNA QT GUI"); 14 | 15 | QApplication a(argc, argv); 16 | a.setStyle("fusion"); 17 | MainWindow* w = new MainWindow(); 18 | w->show(); 19 | 20 | return a.exec(); 21 | } 22 | -------------------------------------------------------------------------------- /vna_qt/markerslider.C: -------------------------------------------------------------------------------- 1 | #include "markerslider.H" 2 | #include "ui_markerslider.h" 3 | 4 | MarkerSlider::MarkerSlider(QWidget *parent) : 5 | QWidget(parent), 6 | ui(new Ui::MarkerSlider) 7 | { 8 | ui->setupUi(this); 9 | labels = {ui->l1, ui->l2, ui->l3, ui->l4}; 10 | } 11 | 12 | MarkerSlider::~MarkerSlider() 13 | { 14 | delete ui; 15 | } 16 | 17 | void MarkerSlider::setLabelText(int index, string text) { 18 | labels.at(index)->setText(QString::fromStdString(text)); 19 | labels.at(index)->setVisible(text!=""); 20 | } 21 | 22 | -------------------------------------------------------------------------------- /vna_qt/markerslider.H: -------------------------------------------------------------------------------- 1 | #ifndef MARKERSLIDER_H 2 | #define MARKERSLIDER_H 3 | 4 | #include 5 | #include 6 | 7 | namespace Ui { 8 | class MarkerSlider; 9 | } 10 | class QLabel; 11 | 12 | using namespace std; 13 | 14 | class MarkerSlider : public QWidget 15 | { 16 | Q_OBJECT 17 | 18 | public: 19 | int id = -1; 20 | vector labels; 21 | explicit MarkerSlider(QWidget *parent = 0); 22 | ~MarkerSlider(); 23 | 24 | void setLabelText(int index, string text); 25 | 26 | public: 27 | Ui::MarkerSlider *ui; 28 | }; 29 | 30 | #endif // MARKERSLIDER_H 31 | -------------------------------------------------------------------------------- /vna_qt/polarview.H: -------------------------------------------------------------------------------- 1 | #ifndef POLARVIEW_H 2 | #define POLARVIEW_H 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | using namespace std; 9 | 10 | 11 | class QPainter; 12 | 13 | class PolarView : public QWidget 14 | { 15 | Q_OBJECT 16 | public: 17 | struct Marker { 18 | uint32_t color; // rgb 19 | int index; 20 | }; 21 | vector > points; 22 | vector markers; 23 | double scale=1.; 24 | double margin=10; // pixels 25 | bool persistence = false; 26 | 27 | explicit PolarView(QWidget *parent = 0); 28 | 29 | double radius(); 30 | QPointF val_to_point(QPointF center, double r, complex val); 31 | void draw_grid(QPainter& painter); 32 | void draw_chart(QPainter& painter); 33 | void draw_full(QPainter& painter); 34 | void draw_point(QPainter& painter, complex pt, double size); 35 | 36 | void clearPersistence(); 37 | void commitTrace(); 38 | 39 | protected: 40 | QImage image; 41 | void paintEvent(QPaintEvent *event) override; 42 | signals: 43 | 44 | public slots: 45 | }; 46 | 47 | #endif // POLARVIEW_H 48 | -------------------------------------------------------------------------------- /vna_qt/resources.qrc: -------------------------------------------------------------------------------- 1 | 2 | 3 | edit-redo-symbolic.svg 4 | emblem-ok-symbolic.svg 5 | add.svg 6 | xfce-wm-close.svg 7 | xfce-wm-maximize.svg 8 | xfce-wm-unmaximize.svg 9 | 10 | 11 | -------------------------------------------------------------------------------- /vna_qt/touchstone.H: -------------------------------------------------------------------------------- 1 | #ifndef TOUCHSTONE_H 2 | #define TOUCHSTONE_H 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | using namespace std; 9 | using namespace Eigen; 10 | 11 | class SParamSeries { 12 | public: 13 | // map from frequency (in Hz) to value 14 | map values; 15 | MatrixXcd interpolate(double freqHz) { 16 | assert(!values.empty()); 17 | 18 | // find the item just right of freqHz 19 | auto it2 = values.lower_bound(freqHz); 20 | 21 | // if there is none, return the last value 22 | if(it2 == values.end()) return (*values.rbegin()).second; 23 | 24 | // if it is the first value, return the first value 25 | if(it2 == values.begin()) return (*it2).second; 26 | 27 | // otherwise interpolate 28 | auto it1 = it2; 29 | it2--; 30 | double freq1 = (*it1).first, freq2 = (*it2).first; 31 | MatrixXcd val1 = (*it1).second, val2 = (*it2).second; 32 | double scale = 1./(freq2-freq1); 33 | return val1*((freq2 - freqHz)*scale) + val2*((freqHz - freq1)*scale); 34 | } 35 | }; 36 | 37 | string serializeTouchstone(vector > data, double startFreqHz, double stepFreqHz); 38 | string serializeTouchstone(vector data, double startFreqHz, double stepFreqHz); 39 | void parseTouchstone(string data, int &nPorts, map& results); 40 | 41 | #endif // TOUCHSTONE_H 42 | --------------------------------------------------------------------------------