├── .gitignore ├── LICENSE ├── README.md ├── riscv-disasm.sln └── riscv-disasm ├── Helpers └── parse_riscv_opcodes.py ├── disassembler.cpp ├── disassembler.hpp ├── elf.cpp ├── elf.hpp ├── instruction_handlers.cpp ├── instructions.cpp ├── instructions.hpp ├── main.cpp ├── notes.txt ├── pe.cpp ├── pe.hpp ├── registers.hpp ├── riscv-disasm.vcxproj ├── riscv-disasm.vcxproj.filters ├── riscv.cpp └── riscv.hpp /.gitignore: -------------------------------------------------------------------------------- 1 | ## Ignore Visual Studio temporary files, build results, and 2 | ## files generated by popular Visual Studio add-ons. 3 | ## 4 | ## Get latest from https://github.com/github/gitignore/blob/master/VisualStudio.gitignore 5 | 6 | # User-specific files 7 | *.rsuser 8 | *.suo 9 | *.user 10 | *.userosscache 11 | *.sln.docstates 12 | 13 | # User-specific files (MonoDevelop/Xamarin Studio) 14 | *.userprefs 15 | 16 | # Mono auto generated files 17 | mono_crash.* 18 | 19 | # Build results 20 | [Dd]ebug/ 21 | [Dd]ebugPublic/ 22 | [Rr]elease/ 23 | [Rr]eleases/ 24 | x64/ 25 | x86/ 26 | [Aa][Rr][Mm]/ 27 | [Aa][Rr][Mm]64/ 28 | bld/ 29 | [Bb]in/ 30 | [Oo]bj/ 31 | [Ll]og/ 32 | 33 | # Visual Studio 2015/2017 cache/options directory 34 | .vs/ 35 | # Uncomment if you have tasks that create the project's static files in wwwroot 36 | #wwwroot/ 37 | 38 | # Visual Studio 2017 auto generated files 39 | Generated\ Files/ 40 | 41 | # MSTest test Results 42 | [Tt]est[Rr]esult*/ 43 | [Bb]uild[Ll]og.* 44 | 45 | # NUnit 46 | *.VisualState.xml 47 | TestResult.xml 48 | nunit-*.xml 49 | 50 | # Build Results of an ATL Project 51 | [Dd]ebugPS/ 52 | [Rr]eleasePS/ 53 | dlldata.c 54 | 55 | # Benchmark Results 56 | BenchmarkDotNet.Artifacts/ 57 | 58 | # .NET Core 59 | project.lock.json 60 | project.fragment.lock.json 61 | artifacts/ 62 | 63 | # StyleCop 64 | StyleCopReport.xml 65 | 66 | # Files built by Visual Studio 67 | *_i.c 68 | *_p.c 69 | *_h.h 70 | *.ilk 71 | *.meta 72 | *.obj 73 | *.iobj 74 | *.pch 75 | *.pdb 76 | *.ipdb 77 | *.pgc 78 | *.pgd 79 | *.rsp 80 | *.sbr 81 | *.tlb 82 | *.tli 83 | *.tlh 84 | *.tmp 85 | *.tmp_proj 86 | *_wpftmp.csproj 87 | *.log 88 | *.vspscc 89 | *.vssscc 90 | .builds 91 | *.pidb 92 | *.svclog 93 | *.scc 94 | 95 | # Chutzpah Test files 96 | _Chutzpah* 97 | 98 | # Visual C++ cache files 99 | ipch/ 100 | *.aps 101 | *.ncb 102 | *.opendb 103 | *.opensdf 104 | *.sdf 105 | *.cachefile 106 | *.VC.db 107 | *.VC.VC.opendb 108 | 109 | # Visual Studio profiler 110 | *.psess 111 | *.vsp 112 | *.vspx 113 | *.sap 114 | 115 | # Visual Studio Trace Files 116 | *.e2e 117 | 118 | # TFS 2012 Local Workspace 119 | $tf/ 120 | 121 | # Guidance Automation Toolkit 122 | *.gpState 123 | 124 | # ReSharper is a .NET coding add-in 125 | _ReSharper*/ 126 | *.[Rr]e[Ss]harper 127 | *.DotSettings.user 128 | 129 | # JustCode is a .NET coding add-in 130 | .JustCode 131 | 132 | # TeamCity is a build add-in 133 | _TeamCity* 134 | 135 | # DotCover is a Code Coverage Tool 136 | *.dotCover 137 | 138 | # AxoCover is a Code Coverage Tool 139 | .axoCover/* 140 | !.axoCover/settings.json 141 | 142 | # Visual Studio code coverage results 143 | *.coverage 144 | *.coveragexml 145 | 146 | # NCrunch 147 | _NCrunch_* 148 | .*crunch*.local.xml 149 | nCrunchTemp_* 150 | 151 | # MightyMoose 152 | *.mm.* 153 | AutoTest.Net/ 154 | 155 | # Web workbench (sass) 156 | .sass-cache/ 157 | 158 | # Installshield output folder 159 | [Ee]xpress/ 160 | 161 | # DocProject is a documentation generator add-in 162 | DocProject/buildhelp/ 163 | DocProject/Help/*.HxT 164 | DocProject/Help/*.HxC 165 | DocProject/Help/*.hhc 166 | DocProject/Help/*.hhk 167 | DocProject/Help/*.hhp 168 | DocProject/Help/Html2 169 | DocProject/Help/html 170 | 171 | # Click-Once directory 172 | publish/ 173 | 174 | # Publish Web Output 175 | *.[Pp]ublish.xml 176 | *.azurePubxml 177 | # Note: Comment the next line if you want to checkin your web deploy settings, 178 | # but database connection strings (with potential passwords) will be unencrypted 179 | *.pubxml 180 | *.publishproj 181 | 182 | # Microsoft Azure Web App publish settings. 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If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V Disassembler 2 | 3 | This is a simple RISC-V disassembler made in C++. 4 | 5 | Currently the I, M, A, F, D, Q, Zicsr, and Zfencei instruction extensions are supported. 6 | 7 | 8 | Upcoming is support for the C extension and file format parsing for ELF and PE files in order to make the disassembler a bit more accessible. 9 | 10 | 11 | Work on more efficient code and structure will be done at some point in time. 12 | 13 | 14 | Note: this software is not finished (yet) and has not been properly tested. 15 | -------------------------------------------------------------------------------- /riscv-disasm.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.29728.190 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "riscv-disasm", "riscv-disasm\riscv-disasm.vcxproj", "{CD79A079-DF01-4B56-B297-49153AC6632A}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|x64 = Debug|x64 11 | Debug|x86 = Debug|x86 12 | Release|x64 = Release|x64 13 | Release|x86 = Release|x86 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Debug|x64.ActiveCfg = Debug|x64 17 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Debug|x64.Build.0 = Debug|x64 18 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Debug|x86.ActiveCfg = Debug|Win32 19 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Debug|x86.Build.0 = Debug|Win32 20 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Release|x64.ActiveCfg = Release|x64 21 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Release|x64.Build.0 = Release|x64 22 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Release|x86.ActiveCfg = Release|Win32 23 | {CD79A079-DF01-4B56-B297-49153AC6632A}.Release|x86.Build.0 = Release|Win32 24 | EndGlobalSection 25 | GlobalSection(SolutionProperties) = preSolution 26 | HideSolutionNode = FALSE 27 | EndGlobalSection 28 | GlobalSection(ExtensibilityGlobals) = postSolution 29 | SolutionGuid = {1C318DD0-2F41-413E-9DCA-6D4867ACA252} 30 | EndGlobalSection 31 | EndGlobal 32 | -------------------------------------------------------------------------------- /riscv-disasm/Helpers/parse_riscv_opcodes.py: -------------------------------------------------------------------------------- 1 | # Copyright(C) 2020 xenocidewiki 2 | # This file is part of riscv-disasm. 3 | # 4 | # riscv-disasm is free software : you can redistribute it and /or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # riscv-disasm is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | # You should have received a copy of the GNU General Public License 15 | # along with riscv-disasm. If not, see . 16 | file = open("riscvopcodes.txt", "r") 17 | 18 | lines = file.readlines() 19 | 20 | mnemonic = [] 21 | match = [] 22 | mask = [] 23 | i = 0 24 | for line in lines: 25 | split = line.split(" ") 26 | mnemonic_name = split[1].split("_") 27 | 28 | if i % 2 == 0: 29 | if len(mnemonic_name) == 4: 30 | mnemonic.append(mnemonic_name[1] + "." + mnemonic_name[2] + "." + mnemonic_name[3]) 31 | elif len(mnemonic_name) == 3: 32 | mnemonic.append(mnemonic_name[1] + "." + mnemonic_name[2]) 33 | else: 34 | mnemonic.append(mnemonic_name[1]) 35 | 36 | match.append(split[2].strip()) 37 | else: 38 | mask.append(split[3].strip()) 39 | 40 | i += 1 41 | 42 | old_opcode = 0 43 | for i in range(len(mnemonic)): 44 | opcode = hex(int(match[i], 0) & 0x7F) 45 | 46 | if opcode == old_opcode: 47 | print(", { " + match[i] + ", " + mask[i] + ", \"" + mnemonic[i] + "\" }", end='') 48 | else: 49 | print(" } },") 50 | old_opcode = opcode 51 | print("{ " + opcode + ", { {" + match[i] + ", " + mask[i] + ", \"" + mnemonic[i] + "\" }", end='') 52 | 53 | -------------------------------------------------------------------------------- /riscv-disasm/disassembler.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #include "disassembler.hpp" 17 | #include "registers.hpp" 18 | #include 19 | 20 | namespace riscv 21 | { 22 | std::vector disassembler::get_instructions(const std::vector& code) 23 | { 24 | std::vector instruction_objects; 25 | for (auto instruction : code) 26 | { 27 | instruction_objects.emplace_back(instruction::object{ instruction }); 28 | } 29 | 30 | return instruction_objects; 31 | } 32 | 33 | std::vector disassembler::get_instructions(std::vector&& code) 34 | { 35 | return get_instructions(code); 36 | } 37 | 38 | void disassembler::parse_instructions() 39 | { 40 | for (const instruction::object& instruction : m_instructions) 41 | { 42 | switch (instruction.get_type()) 43 | { 44 | case instruction::type_identifier::R: 45 | parse_instruction(std::get(instruction.get_data())); 46 | break; 47 | 48 | case instruction::type_identifier::R4: 49 | parse_instruction(std::get(instruction.get_data())); 50 | break; 51 | 52 | case instruction::type_identifier::I: 53 | parse_instruction(std::get(instruction.get_data())); 54 | break; 55 | 56 | case instruction::type_identifier::J: 57 | parse_instruction(std::get(instruction.get_data())); 58 | break; 59 | 60 | case instruction::type_identifier::U: 61 | parse_instruction(std::get(instruction.get_data())); 62 | break; 63 | 64 | case instruction::type_identifier::S: 65 | parse_instruction(std::get(instruction.get_data())); 66 | break; 67 | 68 | case instruction::type_identifier::B: 69 | parse_instruction(std::get(instruction.get_data())); 70 | break; 71 | 72 | default: 73 | return; 74 | } 75 | } 76 | } 77 | 78 | void disassembler::parse_instruction(const instruction::type_i& instruction) 79 | { 80 | auto potential_instructions = instruction::instruction_table.at(instruction.opcode); 81 | 82 | for (auto& instr_data : potential_instructions) 83 | { 84 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 85 | 86 | if ((instruction.instruction & mask) == proper_opcode) { 87 | auto& destination = registers::x_reg_name_table[instruction.rd].second; 88 | auto& source = registers::x_reg_name_table[instruction.rs1].second; 89 | signed int immediate = instruction.imm; 90 | 91 | if (flags.is_fence) { 92 | fence_instruction_handler(mnemonic, immediate); 93 | return; 94 | } 95 | 96 | if (flags.is_e_sys) { 97 | std::cout << mnemonic << "\n"; 98 | return; 99 | } 100 | 101 | //double check this, these are CSR setting instructions that use rs1 as an immediate rather than register 102 | //do we need to make a function for this or eh? (seems wasteful) 103 | if (flags.is_imm_csr) { 104 | uint8_t csr_source = instruction.rs1; 105 | 106 | std::cout << mnemonic << " " << destination << ", 0x" << std::hex << csr_source << ", 0x" << immediate << "\n"; 107 | return; 108 | } 109 | 110 | //Make better l8r 111 | if (flags.is_float) { 112 | destination = registers::f_reg_name_table[instruction.rd].second; 113 | source = registers::f_reg_name_table[instruction.rs1].second; 114 | } 115 | 116 | //check for shamt instructions 117 | if (flags.is_shamt) 118 | immediate = (immediate & 0x3F); //This handles both the RV64I and RV32I case, note that this is 000000111111, this will pull out the shamt correctly for both, look in manual 119 | 120 | if (flags.is_sl) { 121 | std::cout << mnemonic << " " << destination << ", 0x" << std::hex << immediate << "(" << source << ")\n"; 122 | return; 123 | } 124 | 125 | std::cout << mnemonic << " " << destination << ", " << source << ", 0x" << std::hex << immediate << "\n"; 126 | return; 127 | } 128 | } 129 | } 130 | 131 | void disassembler::parse_instruction(const instruction::type_r& instruction) 132 | { 133 | auto potential_instructions = instruction::instruction_table.at(instruction.opcode); 134 | 135 | for (auto& instr_data : potential_instructions) 136 | { 137 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 138 | 139 | if ((instruction.instruction & mask) == proper_opcode) { 140 | 141 | //A extension checks 142 | if (flags.is_a_ext) { 143 | a_ext_instruction_handler(instruction, instr_data); 144 | return; 145 | } 146 | 147 | if (flags.is_float) { 148 | float_instruction_handler(instruction, instr_data); 149 | return; 150 | } 151 | 152 | auto& destination = registers::x_reg_name_table[instruction.rd].second; 153 | auto& middle = registers::x_reg_name_table[instruction.rs1].second; 154 | auto& last = registers::x_reg_name_table[instruction.rs2].second; 155 | 156 | std::cout << mnemonic << " " << destination << ", " << middle << ", " << last << "\n"; 157 | 158 | return; 159 | } 160 | } 161 | } 162 | 163 | void disassembler::parse_instruction(const instruction::type_r4& instruction) 164 | { 165 | auto potential_instructions = instruction::instruction_table.at(instruction.opcode); 166 | 167 | for (auto& instr_data : potential_instructions) 168 | { 169 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 170 | 171 | if ((instruction.instruction & mask) == proper_opcode) { 172 | auto& destination = registers::f_reg_name_table[instruction.rd].second; 173 | auto& first = registers::f_reg_name_table[instruction.rs1].second; 174 | auto& middle = registers::f_reg_name_table[instruction.rs2].second; 175 | auto& last = registers::f_reg_name_table[instruction.rs3].second; 176 | auto& mode = instruction::float_rounding_name[instruction.funct3].second; 177 | 178 | std::cout << mnemonic << "(" << mode << ") " << destination << ", " << first << ", " << middle << ", " << last << "\n"; 179 | 180 | return; 181 | } 182 | } 183 | } 184 | 185 | void disassembler::parse_instruction(const instruction::type_b& instruction) 186 | { 187 | auto potential_instructions = instruction::instruction_table.at(instruction.opcode); 188 | 189 | for (auto& instr_data : potential_instructions) 190 | { 191 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 192 | 193 | if ((instruction.instruction & mask) == proper_opcode) { 194 | auto& destination = registers::x_reg_name_table[instruction.rs1].second; 195 | auto& source = registers::x_reg_name_table[instruction.rs2].second; 196 | signed int immediate = 0; 197 | 198 | //Might be wrong, make sure to double check.... 199 | immediate |= (instruction.imm_a << 11); 200 | immediate |= (instruction.imm_b << 1); 201 | immediate |= (instruction.imm_c << 5); 202 | immediate |= (instruction.imm_d << 12); 203 | 204 | //Implement actual pc relative addressing later 205 | std::cout << mnemonic << " " << destination << ", " << source << ", 0x" << std::hex << immediate << "(pc)\n"; 206 | 207 | return; 208 | } 209 | } 210 | } 211 | 212 | void disassembler::parse_instruction(const instruction::type_u& instruction) 213 | { 214 | auto potential_instructions = instruction::instruction_table.at(instruction.opcode); 215 | 216 | for (auto& instr_data : potential_instructions) 217 | { 218 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 219 | 220 | if ((instruction.instruction & mask) == proper_opcode) { 221 | auto& destination = registers::x_reg_name_table[instruction.rd].second; 222 | signed int immediate = instruction.imm; 223 | 224 | std::cout << mnemonic << " " << destination << ", 0x" << std::hex << immediate << "\n"; 225 | } 226 | } 227 | } 228 | 229 | void disassembler::parse_instruction(const instruction::type_s& instruction) 230 | { 231 | auto potential_instructions = instruction::instruction_table.at(instruction.opcode); 232 | 233 | for (auto& instr_data : potential_instructions) 234 | { 235 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 236 | 237 | if ((instruction.instruction & mask) == proper_opcode) { 238 | auto& destination = registers::x_reg_name_table[instruction.rs2].second; 239 | auto& source = registers::x_reg_name_table[instruction.rs1].second; 240 | signed int immediate = 0; 241 | 242 | if (flags.is_float) { 243 | destination = registers::f_reg_name_table[instruction.rs2].second; 244 | source = registers::f_reg_name_table[instruction.rs1].second; 245 | } 246 | 247 | immediate |= instruction.imm_a; 248 | immediate |= (instruction.imm_b << 5); 249 | 250 | std::cout << mnemonic << " " << destination << ", 0x" << std::hex << immediate << "(" << source << ")\n"; 251 | } 252 | } 253 | } 254 | 255 | void disassembler::parse_instruction(const instruction::type_j& instruction) 256 | { 257 | auto potential_instructions = instruction::instruction_table.at(instruction.opcode); 258 | 259 | for (auto& instr_data : potential_instructions) 260 | { 261 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 262 | 263 | if ((instruction.instruction & mask) == proper_opcode) { 264 | auto& destination = registers::x_reg_name_table[instruction.rd].second; 265 | signed int immediate = 0; 266 | 267 | if (flags.is_float) 268 | destination = registers::f_reg_name_table[instruction.rd].second; 269 | 270 | //double check 271 | immediate |= (instruction.imm_a << 12); 272 | immediate |= (instruction.imm_b << 11); 273 | immediate |= (instruction.imm_c << 1); 274 | immediate |= (instruction.imm_d << 20); 275 | 276 | std::cout << mnemonic << " " << destination << ", 0x" << std::hex << immediate << "(pc)\n"; 277 | } 278 | } 279 | } 280 | 281 | void parse_instruction(const instruction::type_cr& instruction) 282 | {} 283 | 284 | void parse_instruction(const instruction::type_ci& instruction) 285 | {} 286 | 287 | void parse_instruction(const instruction::type_css& instruction) 288 | {} 289 | 290 | void parse_instruction(const instruction::type_ciw& instruction) 291 | {} 292 | 293 | void parse_instruction(const instruction::type_cl& instruction) 294 | {} 295 | 296 | void parse_instruction(const instruction::type_cs& instruction) 297 | {} 298 | 299 | void parse_instruction(const instruction::type_ca& instruction) 300 | {} 301 | 302 | void parse_instruction(const instruction::type_cb& instruction) 303 | {} 304 | 305 | void parse_instruction(const instruction::type_cj& instruction) 306 | {} 307 | } -------------------------------------------------------------------------------- /riscv-disasm/disassembler.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #pragma once 17 | 18 | #include "instructions.hpp" 19 | 20 | namespace riscv { 21 | enum class isa 22 | { 23 | RV32, 24 | RV64, 25 | RV128 26 | }; 27 | 28 | class disassembler 29 | { 30 | using instruction_data = std::tuple; 31 | 32 | std::vector m_instructions; 33 | isa m_architecture; 34 | 35 | //Use std::span when msvc decides to get off their lazy ass and implement it 36 | std::vector get_instructions(const std::vector& code); 37 | std::vector get_instructions(std::vector&& code); 38 | 39 | void parse_instruction(const instruction::type_i& instruction); 40 | void parse_instruction(const instruction::type_r& instruction); 41 | void parse_instruction(const instruction::type_r4& instruction); 42 | void parse_instruction(const instruction::type_b& instruction); 43 | void parse_instruction(const instruction::type_u& instruction); 44 | void parse_instruction(const instruction::type_s& instruction); 45 | void parse_instruction(const instruction::type_j& instruction); 46 | void parse_instruction(const instruction::type_cr& instruction); 47 | void parse_instruction(const instruction::type_ci& instruction); 48 | void parse_instruction(const instruction::type_css& instruction); 49 | void parse_instruction(const instruction::type_ciw& instruction); 50 | void parse_instruction(const instruction::type_cl& instruction); 51 | void parse_instruction(const instruction::type_cs& instruction); 52 | void parse_instruction(const instruction::type_ca& instruction); 53 | void parse_instruction(const instruction::type_cb& instruction); 54 | void parse_instruction(const instruction::type_cj& instruction); 55 | 56 | void fence_instruction_handler(const std::string& mnemonic, const signed int& imm); 57 | void float_instruction_handler(const instruction::type_r& instruction, instruction_data instr_data); 58 | void a_ext_instruction_handler(const instruction::type_r& instruction, instruction_data instr_data); 59 | 60 | public: 61 | disassembler() = delete; 62 | disassembler(const disassembler& disasm) = delete; 63 | disassembler(disassembler&& disasm) = delete; 64 | 65 | disassembler(const std::vector& code, const isa arch) : m_instructions{ get_instructions(code) }, m_architecture{ arch } 66 | {} 67 | 68 | disassembler(std::vector&& code, const isa arch) : m_instructions{ get_instructions(std::move(code)) }, m_architecture{ arch } 69 | {} 70 | 71 | void parse_instructions(); 72 | }; 73 | } -------------------------------------------------------------------------------- /riscv-disasm/elf.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . -------------------------------------------------------------------------------- /riscv-disasm/elf.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #pragma once 17 | 18 | namespace elf 19 | { 20 | 21 | } -------------------------------------------------------------------------------- /riscv-disasm/instruction_handlers.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #include "disassembler.hpp" 17 | #include "registers.hpp" 18 | #include 19 | 20 | namespace riscv 21 | { 22 | void disassembler::fence_instruction_handler(const std::string& mnemonic, const signed int& immediate) 23 | { 24 | if (mnemonic == "FENCE.I") { 25 | std::cout << mnemonic << "\n"; 26 | } else { 27 | 28 | //FENCE.TSO 29 | if (immediate >> 8) { 30 | std::cout << "FENCE.TSO rw, rw\n"; 31 | return; 32 | } 33 | 34 | union iorw 35 | { 36 | int encoding; 37 | struct { 38 | int8_t w : 1; 39 | int8_t r : 1; 40 | int8_t o : 1; 41 | int8_t i : 1; 42 | int8_t pad : 4; 43 | }; 44 | }; 45 | 46 | auto successor = iorw{ immediate & 0x0f }; 47 | auto predecessor = iorw{ (immediate & 0b000011110000) >> 4 }; 48 | 49 | std::string succ_str; 50 | std::string pre_str; 51 | 52 | if (successor.i != 0) 53 | succ_str.append("i"); 54 | if (successor.o != 0) 55 | succ_str.append("o"); 56 | if (successor.r != 0) 57 | succ_str.append("r"); 58 | if (successor.w != 0) 59 | succ_str.append("w"); 60 | 61 | if (predecessor.i != 0) 62 | pre_str.append("i"); 63 | if (predecessor.o != 0) 64 | pre_str.append("o"); 65 | if (predecessor.r != 0) 66 | pre_str.append("r"); 67 | if (predecessor.w != 0) 68 | pre_str.append("w"); 69 | 70 | std::cout << mnemonic << " " << pre_str << ", " << succ_str << "\n"; 71 | } 72 | } 73 | 74 | void disassembler::float_instruction_handler(const instruction::type_r& instruction, instruction_data instr_data) 75 | { 76 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 77 | 78 | auto& destination = registers::f_reg_name_table[instruction.rd].second; 79 | auto& first = registers::f_reg_name_table[instruction.rs1].second; 80 | auto& last = registers::f_reg_name_table[instruction.rs2].second; 81 | auto& mode = instruction::float_rounding_name[instruction.funct3].second; 82 | 83 | if (flags.is_special_float) { 84 | std::cout << mnemonic << "(" << mode << ") " << destination << ", " << first << "\n"; 85 | return; 86 | } 87 | 88 | std::cout << mnemonic << "(" << mode << ") " << destination << ", " << first << ", " << last << "\n"; 89 | } 90 | 91 | void disassembler::a_ext_instruction_handler(const instruction::type_r& instruction, instruction_data instr_data) 92 | { 93 | auto& [proper_opcode, mask, mnemonic, flags] { instr_data }; 94 | 95 | auto& destination = registers::x_reg_name_table[instruction.rd].second; 96 | auto& address = registers::x_reg_name_table[instruction.rs1].second; 97 | auto& middle = registers::x_reg_name_table[instruction.rs2].second; 98 | 99 | std::string aq_rl{}; 100 | 101 | uint8_t aq = instruction.funct7 & 0b0000010; 102 | uint8_t rl = instruction.funct7 & 0b0000001; 103 | 104 | if (aq) 105 | aq_rl.append(".AQ"); 106 | if (rl) 107 | aq_rl.append(".RL"); 108 | 109 | if (mnemonic == "LR.W" || mnemonic == "LR.D") 110 | std::cout << mnemonic << aq_rl << " " << destination << ", (" << address << ")\n"; 111 | else 112 | std::cout << mnemonic << aq_rl << " " << destination << ", " << middle << ", (" << address << ")\n"; 113 | } 114 | } -------------------------------------------------------------------------------- /riscv-disasm/instructions.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #include "instructions.hpp" 17 | 18 | namespace riscv { 19 | namespace instruction { 20 | const uint8_t object::get_opcode(const uint32_t instruction) const 21 | { 22 | /* 23 | Clears out all bits except last 7 (opcode) 24 | */ 25 | 26 | return instruction & 0x0000007f; 27 | } 28 | 29 | //add errorchecks here omegalul 30 | const type_identifier object::set_instruction_format(const uint32_t instruction) const 31 | { 32 | const uint8_t opcode = get_opcode(instruction); 33 | 34 | return opcode_instruction_type.at(opcode); 35 | } 36 | 37 | const object::instruction_format object::set_instruction_data(const type_identifier type, const uint32_t instruction) 38 | { 39 | switch(type) 40 | { 41 | case type_identifier::B: 42 | return type_b{ instruction }; 43 | 44 | case type_identifier::I: 45 | return type_i{ instruction }; 46 | 47 | case type_identifier::J: 48 | return type_j{ instruction }; 49 | 50 | case type_identifier::R: 51 | return type_r{ instruction }; 52 | 53 | case type_identifier::R4: 54 | return type_r4{ instruction }; 55 | 56 | case type_identifier::S: 57 | return type_s{ instruction }; 58 | 59 | case type_identifier::U: 60 | return type_u{ instruction }; 61 | 62 | case type_identifier::CEXT: 63 | return cext_handler(instruction); //TODO: Pass instruction as uint16_t make sure that works properly 64 | break; 65 | 66 | default: 67 | return type_r{ 0 }; 68 | } 69 | } 70 | 71 | const object::instruction_format object::get_data() const 72 | { 73 | return m_data; 74 | } 75 | 76 | const type_identifier object::get_type() const 77 | { 78 | return m_type; 79 | } 80 | 81 | const object::instruction_format object::cext_handler(const uint16_t instruction) const 82 | { 83 | 84 | } 85 | } 86 | } -------------------------------------------------------------------------------- /riscv-disasm/instructions.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #pragma once 17 | 18 | #include 19 | #include 20 | #include 21 | #include 22 | 23 | namespace riscv 24 | { 25 | namespace instruction 26 | { 27 | enum class type_identifier : uint8_t 28 | { 29 | R, R4, I, S, B, U, J, CEXT 30 | }; 31 | 32 | enum class extensions 33 | { 34 | I, 35 | ZIFENCEI, 36 | ZICSR, 37 | M, 38 | A, 39 | F, 40 | D, 41 | Q, 42 | C 43 | }; 44 | 45 | union instruction_flags { 46 | uint8_t flag; 47 | struct 48 | { 49 | bool is_special_float : 1; 50 | bool is_a_ext : 1; 51 | bool is_sl : 1; 52 | bool is_imm_csr : 1; 53 | bool is_e_sys : 1; 54 | bool is_fence : 1; 55 | bool is_shamt : 1; 56 | bool is_float : 1; 57 | }; 58 | 59 | instruction_flags(const uint8_t& f) : flag{ f } {} 60 | instruction_flags(uint8_t&& f) : flag{ std::move(f) } {} 61 | }; 62 | 63 | enum class float_rounding_mode 64 | { 65 | RNE, 66 | RTZ, 67 | RDN, 68 | RUP, 69 | RMM, 70 | DYN = 0x7 71 | }; 72 | 73 | inline std::array float_rounding_name = { 74 | std::pair{float_rounding_mode::RNE, "RNE"}, 75 | std::pair{float_rounding_mode::RTZ, "RTZ"}, 76 | std::pair{float_rounding_mode::RDN, "RDN"}, 77 | std::pair{float_rounding_mode::RUP, "RUP"}, 78 | std::pair{float_rounding_mode::RMM, "RMM"}, 79 | std::pair{float_rounding_mode::DYN, "DYN"}, 80 | }; 81 | 82 | union type_r { 83 | uint32_t instruction; 84 | struct 85 | { 86 | uint32_t opcode : 7; 87 | uint32_t rd : 5; 88 | uint32_t funct3 : 3; 89 | uint32_t rs1 : 5; 90 | uint32_t rs2 : 5; 91 | uint32_t funct7 : 7; 92 | }; 93 | }; 94 | 95 | union type_r4 { 96 | uint32_t instruction; 97 | struct 98 | { 99 | uint32_t opcode : 7; 100 | uint32_t rd : 5; 101 | uint32_t funct3 : 3; 102 | uint32_t rs1 : 5; 103 | uint32_t rs2 : 5; 104 | uint32_t funct2 : 2; 105 | uint32_t rs3 : 5; 106 | }; 107 | }; 108 | 109 | union type_i { 110 | uint32_t instruction; 111 | struct 112 | { 113 | uint32_t opcode : 7; 114 | uint32_t rd : 5; 115 | uint32_t funct3 : 3; 116 | uint32_t rs1 : 5; 117 | signed int imm : 12; 118 | }; 119 | }; 120 | 121 | union type_s { 122 | uint32_t instruction; 123 | struct 124 | { 125 | uint32_t opcode : 7; 126 | signed int imm_a : 5; 127 | uint32_t funct3 : 3; 128 | uint32_t rs1 : 5; 129 | uint32_t rs2 : 5; 130 | signed int imm_b : 7; 131 | }; 132 | }; 133 | 134 | union type_b { 135 | uint32_t instruction; 136 | struct 137 | { 138 | uint32_t opcode : 7; 139 | signed int imm_a : 1; 140 | signed int imm_b : 4; 141 | uint32_t funct3 : 3; 142 | uint32_t rs1 : 5; 143 | uint32_t rs2 : 5; 144 | signed int imm_c : 6; 145 | signed int imm_d : 1; 146 | }; 147 | }; 148 | 149 | union type_u { 150 | uint32_t instruction; 151 | struct 152 | { 153 | uint32_t opcode : 7; 154 | uint32_t rd : 5; 155 | signed int imm : 20; 156 | }; 157 | }; 158 | 159 | union type_j { 160 | uint32_t instruction; 161 | struct 162 | { 163 | uint32_t opcode : 7; 164 | uint32_t rd : 5; 165 | signed int imm_a : 8; 166 | signed int imm_b : 1; 167 | signed int imm_c : 10; 168 | signed int imm_d : 1; 169 | }; 170 | }; 171 | 172 | //CEXT types 173 | union type_cr 174 | { 175 | uint16_t instruction; 176 | struct 177 | { 178 | uint16_t opcode : 2; 179 | uint16_t rs2 : 5; 180 | uint16_t rs1 : 5; 181 | uint16_t funct4 : 4; 182 | }; 183 | }; 184 | 185 | union type_ci 186 | { 187 | uint16_t instruction; 188 | struct 189 | { 190 | uint16_t opcode : 2; 191 | int16_t imm1 : 5; 192 | uint16_t rs1 : 5; 193 | int16_t imm2 : 1; 194 | uint16_t funct3 : 3; 195 | }; 196 | }; 197 | 198 | union type_css 199 | { 200 | uint16_t instruction; 201 | struct 202 | { 203 | uint16_t opcode : 2; 204 | uint16_t rs2 : 5; 205 | int16_t imm : 6; 206 | uint16_t funct3 : 3; 207 | }; 208 | }; 209 | 210 | union type_ciw 211 | { 212 | uint16_t instruction; 213 | struct 214 | { 215 | uint16_t opcode : 2; 216 | uint16_t rd : 3; 217 | int16_t imm : 8; 218 | uint16_t funct3 : 3; 219 | }; 220 | }; 221 | 222 | union type_cl 223 | { 224 | uint16_t instruction; 225 | struct 226 | { 227 | uint16_t opcode : 2; 228 | uint16_t rd : 3; 229 | int16_t imm1 : 2; 230 | uint16_t rs1 : 3; 231 | int16_t imm2 : 3; 232 | uint16_t funct3 : 3; 233 | }; 234 | }; 235 | 236 | union type_cs 237 | { 238 | uint16_t instruction; 239 | struct 240 | { 241 | uint16_t opcode : 2; 242 | uint16_t rs2 : 3; 243 | int16_t imm1 : 2; 244 | uint16_t rs1 : 3; 245 | int16_t imm2 : 3; 246 | uint16_t funct3 : 3; 247 | }; 248 | }; 249 | 250 | union type_ca 251 | { 252 | uint16_t instruction; 253 | struct 254 | { 255 | uint16_t opcode : 2; 256 | uint16_t rs2 : 3; 257 | uint16_t funct2 : 2; 258 | uint16_t rs1 : 3; 259 | int16_t funct6 : 6; 260 | }; 261 | }; 262 | 263 | union type_cb 264 | { 265 | uint16_t instruction; 266 | struct 267 | { 268 | uint16_t opcode : 2; 269 | uint16_t offset1 : 5; 270 | uint16_t rs1 : 3; 271 | uint16_t offset2 : 3; 272 | uint16_t funct3 : 3; 273 | }; 274 | }; 275 | 276 | union type_cj 277 | { 278 | uint16_t instruction; 279 | struct 280 | { 281 | uint16_t opcode : 2; 282 | uint16_t jump_target : 11; 283 | uint16_t funct3 : 3; 284 | }; 285 | }; 286 | 287 | class object 288 | { 289 | using instruction_format = std::variant; 290 | 291 | const type_identifier m_type; 292 | const instruction_format m_data; 293 | 294 | const uint8_t get_opcode(const uint32_t instruction) const; 295 | const type_identifier set_instruction_format(const uint32_t instruction) const; 296 | const instruction_format cext_handler(const uint16_t instruction) const; 297 | const instruction_format set_instruction_data(const type_identifier type, const uint32_t instruction); 298 | 299 | public: 300 | object() = delete; 301 | object(const object& obj) = default; 302 | object(object&& obj) = default; 303 | 304 | explicit object(const uint32_t inst) : m_type { set_instruction_format(inst) }, m_data{ set_instruction_data(m_type, inst) } 305 | {} 306 | 307 | const type_identifier get_type() const; 308 | const instruction_format get_data() const; 309 | }; 310 | 311 | //Probably better (and faster) to generate an array filled with null spaces for potential instructions 312 | //Can be done later tho 313 | const std::unordered_map opcode_instruction_type { 314 | {0x37, type_identifier::U}, 315 | {0x17, type_identifier::U}, 316 | {0x6F, type_identifier::J}, 317 | {0x67, type_identifier::I}, 318 | {0x63, type_identifier::B}, 319 | {0x23, type_identifier::S}, 320 | {0x13, type_identifier::I}, //its a mutated I format! architecture dependent ;-; check x64 vs x86 321 | {0x33, type_identifier::R}, 322 | {0x0F, type_identifier::I}, //Fence fucking instruction damnit, its either I, or its custom bullshit, FENCE.I is I, FENCE is garbo custom (its I but the fields are garbo) APPARENTLY THERE IS FENCE.TSO TOO? 323 | {0x73, type_identifier::I}, //CSR or ECALL/EBREAK 324 | {0x03, type_identifier::I}, 325 | {0x1B, type_identifier::I}, //modified I, uses shamt bs on 64bit 326 | {0x3B, type_identifier::R}, 327 | {0x2F, type_identifier::R}, //RV32/64A extension 328 | 329 | //RV(32/64)(F/D/Q) Extensions 330 | {0x07, type_identifier::I}, //FLW/FLD/FLQ 331 | {0x27, type_identifier::S}, //FSW/FSD/FSQ 332 | {0x43, type_identifier::R4}, //FMADD.S/D/Q 333 | {0x47, type_identifier::R4}, //FMSUB.S/D/Q 334 | {0x4B, type_identifier::R4}, //FNMSUB.S/D/Q 335 | {0x4F, type_identifier::R4}, //FNMADD.S/D/Q 336 | {0x53, type_identifier::R}, //Everything else 337 | 338 | //C Extension 339 | {0x0, type_identifier::CEXT}, 340 | {0x1, type_identifier::CEXT}, 341 | {0x2, type_identifier::CEXT}, 342 | {0x21, type_identifier::CEXT}, 343 | {0x41, type_identifier::CEXT}, 344 | {0x61, type_identifier::CEXT} 345 | }; 346 | 347 | /* 348 | Have another array/unordered_map based on opcode index/key where you have a list of matches and masks, basically you can detect which type of instruction you want, ... 349 | then detect the specific instruction and do work based on that, which is quite sweet if you ask me. I attached a python script which helped me generate this bullshit. 350 | */ 351 | 352 | //essentially maps each opcode to a set of instructions with said opcode, which each have a { match, mask, mnemonic, is_load_or_store_instr, is_floating_pt } tuple that we can use for parsing and checking which instruction it actually is 353 | //change to constexpr when msvc decides to fucking implement it -_- 354 | const std::unordered_map>> instruction_table { 355 | //CEXT 356 | //TODO: fix the instruction_flags for this ext 357 | { 0x1, { 358 | { 0x1, 0xffff, "C.NOP", 0b00000000 }, 359 | { 0x6101, 0xef83, "C.ADDI16SP", 0b00000000 }, 360 | { 0x1, 0xe003, "C.ADDI", 0b00000000 }, 361 | { 0x2001, 0xe003, "C.JAL", 0b00000000 }, 362 | { 0x4001, 0xe003, "C.LI", 0b00000000 }, 363 | { 0x6001, 0xe003, "C.LUI", 0b00000000 }, 364 | { 0x8001, 0xec03, "C.SRLI", 0b00000000 }, 365 | { 0x8401, 0xec03, "C.SRAI", 0b00000000 }, 366 | { 0x8801, 0xec03, "C.ANDI", 0b00000000 }, 367 | { 0x8c01, 0xfc63, "C.SUB", 0b00000000 }, 368 | { 0xa001, 0xe003, "C.J", 0b00000000 }, 369 | { 0xc001, 0xe003, "C.BEQZ", 0b00000000 }, 370 | { 0xe001, 0xe003, "C.BNEZ", 0b00000000 }, 371 | { 0x2001, 0xe003, "C.ADDIW", 0b00000000 }, 372 | { 0x8001, 0xfc03, "C.SRLI.RV32", 0b00000000 }, 373 | { 0x8401, 0xfc03, "C.SRAI.RV32", 0b00000000 }, 374 | { 0x9c01, 0xfc63, "C.SUBW", 0b00000000 } 375 | } 376 | }, 377 | 378 | { 0x2, { 379 | { 0x8002, 0xf07f, "C.JR", 0b00000000 }, 380 | { 0x9002, 0xf07f, "C.JALR", 0b00000000 }, 381 | { 0x9002, 0xffff, "C.EBREAK", 0b00000000 }, 382 | { 0x2, 0xe003, "C.SLLI", 0b00000000 }, 383 | { 0x2002, 0xe003, "C.FLDSP", 0b00000000 }, 384 | { 0x4002, 0xe003, "C.LWSP", 0b00000000 }, 385 | { 0x6002, 0xe003, "C.FLWSP", 0b00000000 }, 386 | { 0x8002, 0xf003, "C.MV", 0b00000000 }, 387 | { 0x9002, 0xf003, "C.ADD", 0b00000000 }, 388 | { 0xa002, 0xe003, "C.FSDSP", 0b00000000 }, 389 | { 0xc002, 0xe003, "C.SWSP", 0b00000000 }, 390 | { 0xe002, 0xe003, "C.FSWSP", 0b00000000 }, 391 | { 0x6002, 0xe003, "C.LDSP", 0b00000000 }, 392 | { 0xe002, 0xe003, "C.SDSP", 0b00000000 }, 393 | { 0x2, 0xf003, "C.SLLI.RV32", 0b00000000 } 394 | } 395 | }, 396 | 397 | { 0x0, { 398 | { 0x0, 0xe003, "C.ADDI4SPN", 0b00000000 }, 399 | { 0x2000, 0xe003, "C.FLD", 0b00000000 }, 400 | { 0x4000, 0xe003, "C.LW", 0b00000000 }, 401 | { 0x6000, 0xe003, "C.FLW", 0b00000000 }, 402 | { 0xa000, 0xe003, "C.FSD", 0b00000000 }, 403 | { 0xc000, 0xe003, "C.SW", 0b00000000 }, 404 | { 0xe000, 0xe003, "C.FSW", 0b00000000 }, 405 | { 0x6000, 0xe003, "C.LD", 0b00000000 }, 406 | { 0xe000, 0xe003, "C.SD", 0b00000000 } 407 | } 408 | }, 409 | 410 | { 0x21, { 411 | { 0x8c21, 0xfc63, "C.XOR", 0b00000000 }, 412 | { 0x9c21, 0xfc63, "C.ADDW", 0b00000000 } 413 | } 414 | }, 415 | 416 | { 0x41, { 417 | { 0x8c41, 0xfc63, "C.OR", 0b00000000 } 418 | } 419 | }, 420 | 421 | { 0x61, { 422 | { 0x8c61, 0xfc63, "C.AND", 0b00000000 } 423 | } 424 | }, 425 | 426 | //RV32I Instructions 427 | { 0x63, { 428 | { 0x63, 0x707f, "BEQ", 0b00000000 }, 429 | { 0x1063, 0x707f, "BNE", 0b00000000 }, 430 | { 0x4063, 0x707f, "BLT", 0b00000000 }, 431 | { 0x5063, 0x707f, "BGE", 0b00000000 }, 432 | { 0x6063, 0x707f, "BLTU", 0b00000000 }, 433 | { 0x7063, 0x707f, "BGEU", 0b00000000 } 434 | } 435 | }, 436 | 437 | { 0x67, { 438 | { 0x67, 0x707f, "JALR", 0b00000000 } 439 | } 440 | }, 441 | 442 | { 0x6f, { 443 | { 0x6f, 0x7f, "JAL", 0b00000000 } 444 | } 445 | }, 446 | 447 | { 0x37, { 448 | { 0x37, 0x7f, "LUI", 0b00000100 } 449 | } 450 | }, 451 | 452 | { 0x17, { 453 | { 0x17, 0x7f, "AUIPC", 0b00000000 } 454 | } 455 | }, 456 | 457 | { 0x13, { 458 | { 0x13, 0x707f, "ADDI", 0b00000000 }, 459 | { 0x1013, 0xfc00707f, "SLLI", 0b01000000 }, 460 | { 0x2013, 0x707f, "SLTI", 0b00000000 }, 461 | { 0x3013, 0x707f, "SLTIU", 0b00000000 }, 462 | { 0x4013, 0x707f, "XORI", 0b00000000 }, 463 | { 0x5013, 0xfc00707f, "SRLI", 0b01000000 }, 464 | { 0x40005013, 0xfc00707f, "SRAI", 0b01000000 }, 465 | { 0x6013, 0x707f, "ORI", 0b00000000 }, 466 | { 0x7013, 0x707f, "ANDI", 0b00000000 } 467 | } 468 | }, 469 | 470 | { 0x33, { 471 | { 0x33, 0xfe00707f, "ADD", 0b00000000 }, 472 | { 0x40000033, 0xfe00707f, "SUB", 0b00000000 }, 473 | { 0x1033, 0xfe00707f, "SLL", 0b00000000 }, 474 | { 0x2033, 0xfe00707f, "SLT", 0b00000000 }, 475 | { 0x3033, 0xfe00707f, "SLTU", 0b00000000 }, 476 | { 0x4033, 0xfe00707f, "XOR", 0b00000000 }, 477 | { 0x5033, 0xfe00707f, "SRL", 0b00000000 }, 478 | { 0x40005033, 0xfe00707f, "SRA", 0b00000000 }, 479 | { 0x6033, 0xfe00707f, "OR", 0b00000000 }, 480 | { 0x7033, 0xfe00707f, "AND", 0b00000000 }, 481 | 482 | //RV32M Extension 483 | { 0x2000033, 0xfe00707f, "MUL", 0b00000000 }, 484 | { 0x2001033, 0xfe00707f, "MULH", 0b00000000 }, 485 | { 0x2002033, 0xfe00707f, "MULHSU", 0b00000000 }, 486 | { 0x2003033, 0xfe00707f, "MULHU", 0b00000000 }, 487 | { 0x2004033, 0xfe00707f, "DIV", 0b00000000 }, 488 | { 0x2005033, 0xfe00707f, "DIVU", 0b00000000 }, 489 | { 0x2006033, 0xfe00707f, "REM", 0b00000000 }, 490 | { 0x2007033, 0xfe00707f, "REMU", 0b00000000 } 491 | } 492 | }, 493 | 494 | { 0x03, { 495 | { 0x3, 0x707f, "LB", 0b00000100 }, 496 | { 0x1003, 0x707f, "LH", 0b00000100 }, 497 | { 0x2003, 0x707f, "LW", 0b00000100 }, 498 | { 0x4003, 0x707f, "LBU", 0b00000100 }, 499 | { 0x5003, 0x707f, "LHU", 0b00000100 }, 500 | 501 | //RV64I Instructions 502 | { 0x3003, 0x707f, "LD", 0b00000100 }, 503 | { 0x6003, 0x707f, "LWU", 0b00000100 } 504 | } 505 | }, 506 | 507 | { 0x23, { 508 | { 0x23, 0x707f, "SB", 0b00000100 }, 509 | { 0x1023, 0x707f, "SH", 0b00000100 }, 510 | { 0x2023, 0x707f, "SW", 0b00000100 }, 511 | 512 | //RV64I Instruction 513 | { 0x3023, 0x707f, "SD", 0b00000100 } 514 | } 515 | }, 516 | 517 | { 0x0f, { 518 | { 0xf, 0x707f, "FENCE", 0b00100000 }, 519 | 520 | //Zfencei instruction 521 | { 0x100f, 0x707f, "FENCE.I", 0b00100000 } 522 | } 523 | }, 524 | 525 | //Zicsr Instructions 526 | { 0x73, { 527 | { 0x73, 0xffffffff, "ECALL", 0b00010000 }, 528 | { 0x100073, 0xffffffff, "EBREAK", 0b00010000 }, 529 | { 0x1073, 0x707f, "CSRRW", 0b00000000 }, 530 | { 0x2073, 0x707f, "CSRRS", 0b00000000 }, 531 | { 0x3073, 0x707f, "CSRRC", 0b00000000 }, 532 | { 0x5073, 0x707f, "CSRRWI", 0b00001000 }, 533 | { 0x6073, 0x707f, "CSRRSI", 0b00001000 }, 534 | { 0x7073, 0x707f, "CSRRCI", 0b00001000 } 535 | } 536 | }, 537 | 538 | //RV64I Instructions 539 | { 0x1b, { 540 | { 0x1b, 0x707f, "ADDIW", 0b00000000 }, 541 | { 0x101b, 0xfe00707f, "SLLIW", 0b01000000 }, 542 | { 0x501b, 0xfe00707f, "SRLIW", 0b01000000 }, 543 | { 0x4000501b, 0xfe00707f, "SRAIW", 0b01000000 } 544 | } 545 | }, 546 | 547 | { 0x3b, { 548 | { 0x3b, 0xfe00707f, "ADDW", 0b00000000 }, 549 | { 0x4000003b, 0xfe00707f, "SUBW", 0b00000000 }, 550 | { 0x103b, 0xfe00707f, "SLLW", 0b00000000 }, 551 | { 0x503b, 0xfe00707f, "SRLW", 0b00000000 }, 552 | { 0x4000503b, 0xfe00707f, "SRAW", 0b00000000 }, 553 | 554 | //RV64M Extension 555 | { 0x200003b, 0xfe00707f, "MULW", 0b00000000 }, 556 | { 0x200403b, 0xfe00707f, "DIVW", 0b00000000 }, 557 | { 0x200503b, 0xfe00707f, "DIVUW", 0b00000000 }, 558 | { 0x200603b, 0xfe00707f, "REMW", 0b00000000 }, 559 | { 0x200703b, 0xfe00707f, "REMUW", 0b00000000 } 560 | } 561 | }, 562 | 563 | { 0x2f, { 564 | //RV32A Extension 565 | { 0x202f, 0xf800707f, "AMOADD.W", 0b00000010 }, 566 | { 0x2000202f, 0xf800707f, "AMOXOR.W", 0b00000010 }, 567 | { 0x4000202f, 0xf800707f, "AMOOR.W", 0b00000010 }, 568 | { 0x6000202f, 0xf800707f, "AMOAND.W", 0b00000010 }, 569 | { 0x8000202f, 0xf800707f, "AMOMIN.W", 0b00000010 }, 570 | { 0xa000202f, 0xf800707f, "AMOMAX.W", 0b00000010 }, 571 | { 0xc000202f, 0xf800707f, "AMOMINU.W", 0b00000010 }, 572 | { 0xe000202f, 0xf800707f, "AMOMAXU.W", 0b00000010 }, 573 | { 0x800202f, 0xf800707f, "AMOSWAP.W", 0b00000010 }, 574 | { 0x1000202f, 0xf9f0707f, "LR.W", 0b00000110 }, 575 | { 0x1800202f, 0xf800707f, "SC.W", 0b00000110 }, 576 | 577 | //RV64A Extension 578 | { 0x302f, 0xf800707f, "AMOADD.D", 0b00000010 }, 579 | { 0x2000302f, 0xf800707f, "AMOXOR.D", 0b00000010 }, 580 | { 0x4000302f, 0xf800707f, "AMOOR.D", 0b00000010 }, 581 | { 0x6000302f, 0xf800707f, "AMOAND.D", 0b00000010 }, 582 | { 0x8000302f, 0xf800707f, "AMOMIN.D", 0b00000010 }, 583 | { 0xa000302f, 0xf800707f, "AMOMAX.D", 0b00000010 }, 584 | { 0xc000302f, 0xf800707f, "AMOMINU.D", 0b00000010 }, 585 | { 0xe000302f, 0xf800707f, "AMOMAXU.D", 0b00000010 }, 586 | { 0x800302f, 0xf800707f, "AMOSWAP.D", 0b00000010 }, 587 | { 0x1000302f, 0xf9f0707f, "LR.D", 0b00000110 }, 588 | { 0x1800302f, 0xf800707f, "SC.D", 0b00000110 } 589 | } 590 | }, 591 | 592 | //RV(32/64)(F/D/Q) Extensions 593 | { 0x07, { 594 | //RV32/64F Extension 595 | { 0x2007, 0x707f, "FLW", 0b10000100 }, 596 | { 0x3007, 0x707f, "FLD", 0b10000100 }, 597 | { 0x4007, 0x707f, "FLQ", 0b10000100 } 598 | } 599 | }, 600 | 601 | { 0x27, { 602 | //RV32/64F Extension 603 | { 0x2027, 0x707f, "FSW", 0b10000100 }, 604 | { 0x3027, 0x707f, "FSD", 0b10000100 }, 605 | { 0x4027, 0x707f, "FSQ", 0b10000100 } 606 | } 607 | }, 608 | 609 | { 0x43, { 610 | //RV32/64F Extension 611 | { 0x43, 0x600007f, "FMADD.S", 0b10000000 }, 612 | { 0x2000043, 0x600007f, "FMADD.D", 0b10000000 }, 613 | { 0x6000043, 0x600007f, "FMADD.Q", 0b10000000 } 614 | } 615 | }, 616 | 617 | { 0x47, { 618 | //RV32/64F Extension 619 | { 0x47, 0x600007f, "FMSUB.S", 0b10000000 }, 620 | { 0x2000047, 0x600007f, "FMSUB.D", 0b10000000 }, 621 | { 0x6000047, 0x600007f, "FMSUB.Q", 0b10000000 } 622 | } 623 | }, 624 | 625 | { 0x4B, { 626 | //RV32/64F Extension 627 | { 0x4b, 0x600007f, "FNMSUB.S", 0b10000000 }, 628 | { 0x200004b, 0x600007f, "FNMSUB.D", 0b10000000 }, 629 | { 0x600004b, 0x600007f, "FNMSUB.Q", 0b10000000 } 630 | } 631 | }, 632 | 633 | { 0x4F, { 634 | //RV32/64F Extension 635 | { 0x4f, 0x600007f, "FNMADD.S", 0b10000000 }, 636 | { 0x200004f, 0x600007f, "FNMADD.D", 0b10000000 }, 637 | { 0x600004f, 0x600007f, "FNMADD.Q", 0b10000000 } 638 | } 639 | }, 640 | 641 | { 0x53, { 642 | //RV32/64F Extension 643 | { 0x53, 0xfe00007f, "FADD.S", 0b10000000 }, 644 | { 0x8000053, 0xfe00007f, "FSUB.S", 0b10000000 }, 645 | { 0x10000053, 0xfe00007f, "FMUL.S", 0b10000000 }, 646 | { 0x18000053, 0xfe00007f, "FDIV.S", 0b10000000 }, 647 | { 0x20000053, 0xfe00707f, "FSGNJ.S", 0b10000000 }, 648 | { 0x20001053, 0xfe00707f, "FSGNJN.S", 0b10000000 }, 649 | { 0x20002053, 0xfe00707f, "FSGNJX.S", 0b10000000 }, 650 | { 0x28000053, 0xfe00707f, "FMIN.S", 0b10000000 }, 651 | { 0x28001053, 0xfe00707f, "FMAX.S", 0b10000000 }, 652 | { 0x58000053, 0xfff0007f, "FSQRT.S", 0b10000001 }, 653 | { 0xa0000053, 0xfe00707f, "FLE.S", 0b10000000 }, 654 | { 0xa0001053, 0xfe00707f, "FLT.S", 0b10000000 }, 655 | { 0xa0002053, 0xfe00707f, "FEQ.S", 0b10000000 }, 656 | { 0xc0000053, 0xfff0007f, "FCVT.W.S", 0b10000001 }, 657 | { 0xc0100053, 0xfff0007f, "FCVT.WU.S", 0b10000001 }, 658 | { 0xe0000053, 0xfff0707f, "FMV.X.W", 0b10000001 }, 659 | { 0xe0001053, 0xfff0707f, "FCLASS.S", 0b10000001 }, 660 | { 0xd0000053, 0xfff0007f, "FCVT.S.W", 0b10000001 }, 661 | { 0xd0100053, 0xfff0007f, "FCVT.S.WU", 0b10000001 }, 662 | { 0xf0000053, 0xfff0707f, "FMV.W.X", 0b10000001 }, 663 | { 0xc0200053, 0xfff0007f, "FCVT.L.S", 0b10000001 }, 664 | { 0xc0300053, 0xfff0007f, "FCVT.LU.S", 0b10000001 }, 665 | { 0xd0200053, 0xfff0007f, "FCVT.S.L", 0b10000001 }, 666 | { 0xd0300053, 0xfff0007f, "FCVT.S.LU", 0b10000001 }, 667 | 668 | //RV32/64D Extension 669 | { 0x2000053, 0xfe00007f, "FADD.D", 0b10000000 }, 670 | { 0xa000053, 0xfe00007f, "FSUB.D", 0b10000000 }, 671 | { 0x12000053, 0xfe00007f, "FMUL.D", 0b10000000 }, 672 | { 0x1a000053, 0xfe00007f, "FDIV.D", 0b10000000 }, 673 | { 0x22000053, 0xfe00707f, "FSGNJ.D", 0b10000000 }, 674 | { 0x22001053, 0xfe00707f, "FSGNJN.D", 0b10000000 }, 675 | { 0x22002053, 0xfe00707f, "FSGNJX.D", 0b10000000 }, 676 | { 0x2a000053, 0xfe00707f, "FMIN.D", 0b10000000 }, 677 | { 0x2a001053, 0xfe00707f, "FMAX.D", 0b10000000 }, 678 | { 0x40100053, 0xfff0007f, "FCVT.S.D", 0b10000001 }, 679 | { 0x42000053, 0xfff0007f, "FCVT.D.S", 0b10000001 }, 680 | { 0x5a000053, 0xfff0007f, "FSQRT.D", 0b10000001 }, 681 | { 0xa2000053, 0xfe00707f, "FLE.D", 0b10000000 }, 682 | { 0xa2001053, 0xfe00707f, "FLT.D", 0b10000000 }, 683 | { 0xa2002053, 0xfe00707f, "FEQ.D", 0b10000000 }, 684 | { 0xc2000053, 0xfff0007f, "FCVT.W.D", 0b10000001 }, 685 | { 0xc2100053, 0xfff0007f, "FCVT.WU.D", 0b10000001 }, 686 | { 0xe2001053, 0xfff0707f, "FCLASS.D", 0b10000001 }, 687 | { 0xd2000053, 0xfff0007f, "FCVT.D.W", 0b10000001 }, 688 | { 0xd2100053, 0xfff0007f, "FCVT.D.WU", 0b10000001 }, 689 | { 0xc2200053, 0xfff0007f, "FCVT.L.D", 0b10000001 }, 690 | { 0xc2300053, 0xfff0007f, "FCVT.LU.D", 0b10000001 }, 691 | { 0xe2000053, 0xfff0707f, "FMV.X.D", 0b10000001 }, 692 | { 0xd2200053, 0xfff0007f, "FCVT.D.L", 0b10000001 }, 693 | { 0xd2300053, 0xfff0007f, "FCVT.D.LU", 0b10000001 }, 694 | { 0xf2000053, 0xfff0707f, "FMV.D.X", 0b10000001 }, 695 | 696 | //RV32/64Q Extension 697 | { 0x6000053, 0xfe00007f, "FADD.Q", 0b10000000 }, 698 | { 0xe000053, 0xfe00007f, "FSUB.Q", 0b10000000 }, 699 | { 0x16000053, 0xfe00007f, "FMUL.Q", 0b10000000 }, 700 | { 0x1e000053, 0xfe00007f, "FDIV.Q", 0b10000000 }, 701 | { 0x26000053, 0xfe00707f, "FSGNJ.Q", 0b10000000 }, 702 | { 0x26001053, 0xfe00707f, "FSGNJN.Q", 0b10000000 }, 703 | { 0x26002053, 0xfe00707f, "FSGNJX.Q", 0b10000000 }, 704 | { 0x2e000053, 0xfe00707f, "FMIN.Q", 0b10000000 }, 705 | { 0x2e001053, 0xfe00707f, "FMAX.Q", 0b10000000 }, 706 | { 0x40300053, 0xfff0007f, "FCVT.S.Q", 0b10000001 }, 707 | { 0x46000053, 0xfff0007f, "FCVT.Q.S", 0b10000001 }, 708 | { 0x42300053, 0xfff0007f, "FCVT.D.Q", 0b10000001 }, 709 | { 0x46100053, 0xfff0007f, "FCVT.Q.D", 0b10000001 }, 710 | { 0x5e000053, 0xfff0007f, "FSQRT.Q", 0b10000001 }, 711 | { 0xa6000053, 0xfe00707f, "FLE.Q", 0b10000000 }, 712 | { 0xa6001053, 0xfe00707f, "FLT.Q", 0b10000000 }, 713 | { 0xa6002053, 0xfe00707f, "FEQ.Q", 0b10000000 }, 714 | { 0xc6000053, 0xfff0007f, "FCVT.W.Q", 0b10000001 }, 715 | { 0xc6100053, 0xfff0007f, "FCVT.WU.Q", 0b10000001 }, 716 | { 0xe6001053, 0xfff0707f, "FCLASS.Q", 0b10000001 }, 717 | { 0xd6000053, 0xfff0007f, "FCVT.Q.W", 0b10000001 }, 718 | { 0xd6100053, 0xfff0007f, "FCVT.Q.WU", 0b10000001 }, 719 | { 0xc6200053, 0xfff0007f, "FCVT.L.Q", 0b10000001 }, 720 | { 0xc6300053, 0xfff0007f, "FCVT.LU.Q", 0b10000001 }, 721 | { 0xd6200053, 0xfff0007f, "FCVT.Q.L", 0b10000001 }, 722 | { 0xd6300053, 0xfff0007f, "FCVT.Q.LU", 0b10000001 } 723 | } 724 | } 725 | }; 726 | } 727 | } -------------------------------------------------------------------------------- /riscv-disasm/main.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #include "riscv.hpp" 17 | 18 | int main(int argc, char* argv[]) 19 | { 20 | std::vector inst_test = { 21 | 0xE218103, 0x00850463, 0x00002e17, 0xee1ff0ef, 0x00E12423, 22 | 0x4027d79b, 0x40f707bb, 0x0CF2030F, 0x940133, 0x1e30a12f, 0x1200a12f, 23 | 0x80660143, 0x257106ef, 0x55533107 24 | }; 25 | 26 | riscv::disassembler disasm { inst_test, riscv::isa::RV64 }; 27 | 28 | disasm.parse_instructions(); 29 | return 0; 30 | } -------------------------------------------------------------------------------- /riscv-disasm/notes.txt: -------------------------------------------------------------------------------- 1 | * Type of instruction is opcode dependent -> can further simplify that way, parse it, and then do instruction detection 2 | 3 | Be careful with extensions, there is a lot of bullshit going on there 4 | >need unique parsing routines for that 5 | 6 | >After imlpementing all available extensions provided by hte manual, look into working with compressed instructions (See "C" extension in the manual) 7 | >Need to fix load instructions to do load a, offset(b) instead of load a, b, offset 8 | >Fix use of rs1 and rs2 in S-type instructions 9 | make an opcode enum, to give opcodes names, which would be useful yknow, esp in large tables i have -------------------------------------------------------------------------------- /riscv-disasm/pe.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . -------------------------------------------------------------------------------- /riscv-disasm/pe.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #pragma once 17 | 18 | namespace pe 19 | { 20 | 21 | } -------------------------------------------------------------------------------- /riscv-disasm/registers.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #pragma once 17 | 18 | #include 19 | 20 | namespace riscv 21 | { 22 | namespace registers 23 | { 24 | enum x_reg : uint8_t 25 | { 26 | x0, x1, x2, x3, x4, x5, x6, x7, 27 | x8, x9, x10, x11, x12, x13, x14, x15, 28 | x16, x17, x18, x19, x20, x21, x22, x23, 29 | x24, x25, x26, x27, x28, x29, x30, x31 30 | }; 31 | 32 | enum f_reg : uint8_t 33 | { 34 | f0, f1, f2, f3, f4, f5, f6, f7, 35 | f8, f9, f10, f11, f12, f13, f14, f15, 36 | f16, f17, f18, f19, f20, f21, f22, f23, 37 | f24, f25, f26, f27, f28, f29, f30, f31 38 | }; 39 | 40 | inline std::array x_reg_name_table = { 41 | std::pair{x_reg::x0, "zero"}, 42 | std::pair{x_reg::x1, "ra"}, 43 | std::pair{x_reg::x2, "sp"}, 44 | std::pair{x_reg::x3, "gp"}, 45 | std::pair{x_reg::x4, "tp"}, 46 | std::pair{x_reg::x5, "t0"}, 47 | std::pair{x_reg::x6, "t1"}, 48 | std::pair{x_reg::x7, "t2"}, 49 | std::pair{x_reg::x8, "s0"}, 50 | std::pair{x_reg::x9, "s1"}, 51 | std::pair{x_reg::x10, "a0"}, 52 | std::pair{x_reg::x11, "a1"}, 53 | std::pair{x_reg::x12, "a2"}, 54 | std::pair{x_reg::x13, "a3"}, 55 | std::pair{x_reg::x14, "a4"}, 56 | std::pair{x_reg::x15, "a5"}, 57 | std::pair{x_reg::x16, "a6"}, 58 | std::pair{x_reg::x17, "a7"}, 59 | std::pair{x_reg::x18, "s2"}, 60 | std::pair{x_reg::x19, "s3"}, 61 | std::pair{x_reg::x20, "s4"}, 62 | std::pair{x_reg::x21, "s5"}, 63 | std::pair{x_reg::x22, "s6"}, 64 | std::pair{x_reg::x23, "s7"}, 65 | std::pair{x_reg::x24, "s8"}, 66 | std::pair{x_reg::x25, "s9"}, 67 | std::pair{x_reg::x26, "s10"}, 68 | std::pair{x_reg::x27, "s11"}, 69 | std::pair{x_reg::x28, "t3"}, 70 | std::pair{x_reg::x29, "t4"}, 71 | std::pair{x_reg::x30, "t5"}, 72 | std::pair{x_reg::x31, "t6"} 73 | }; 74 | 75 | inline std::array f_reg_name_table = { 76 | std::pair{f_reg::f0, "ft0"}, 77 | std::pair{f_reg::f1, "ft1"}, 78 | std::pair{f_reg::f2, "ft2"}, 79 | std::pair{f_reg::f3, "ft3"}, 80 | std::pair{f_reg::f4, "ft4"}, 81 | std::pair{f_reg::f5, "ft5"}, 82 | std::pair{f_reg::f6, "ft6"}, 83 | std::pair{f_reg::f7, "ft7"}, 84 | std::pair{f_reg::f8, "fs0"}, 85 | std::pair{f_reg::f9, "fs1"}, 86 | std::pair{f_reg::f10, "fa0"}, 87 | std::pair{f_reg::f11, "fa1"}, 88 | std::pair{f_reg::f12, "fa2"}, 89 | std::pair{f_reg::f13, "fa3"}, 90 | std::pair{f_reg::f14, "fa4"}, 91 | std::pair{f_reg::f15, "fa5"}, 92 | std::pair{f_reg::f16, "fa6"}, 93 | std::pair{f_reg::f17, "fa7"}, 94 | std::pair{f_reg::f18, "fs2"}, 95 | std::pair{f_reg::f19, "fs3"}, 96 | std::pair{f_reg::f20, "fs4"}, 97 | std::pair{f_reg::f21, "fs5"}, 98 | std::pair{f_reg::f22, "fs6"}, 99 | std::pair{f_reg::f23, "fs7"}, 100 | std::pair{f_reg::f24, "fs8"}, 101 | std::pair{f_reg::f25, "fs9"}, 102 | std::pair{f_reg::f26, "fs10"}, 103 | std::pair{f_reg::f27, "fs11"}, 104 | std::pair{f_reg::f28, "ft8"}, 105 | std::pair{f_reg::f29, "ft9"}, 106 | std::pair{f_reg::f30, "ft10"}, 107 | std::pair{f_reg::f31, "ft11"} 108 | }; 109 | } 110 | } -------------------------------------------------------------------------------- /riscv-disasm/riscv-disasm.vcxproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Release 10 | Win32 11 | 12 | 13 | Debug 14 | x64 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | 16.0 23 | {CD79A079-DF01-4B56-B297-49153AC6632A} 24 | Win32Proj 25 | riscvdisasm 26 | 10.0 27 | 28 | 29 | 30 | Application 31 | true 32 | v142 33 | Unicode 34 | 35 | 36 | Application 37 | false 38 | v142 39 | true 40 | Unicode 41 | 42 | 43 | Application 44 | true 45 | v142 46 | Unicode 47 | 48 | 49 | Application 50 | false 51 | v142 52 | true 53 | Unicode 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | true 75 | 76 | 77 | true 78 | 79 | 80 | false 81 | 82 | 83 | false 84 | 85 | 86 | 87 | Level3 88 | true 89 | WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) 90 | true 91 | stdcpplatest 92 | 93 | 94 | Console 95 | true 96 | 97 | 98 | 99 | 100 | Level3 101 | true 102 | _DEBUG;_CONSOLE;%(PreprocessorDefinitions) 103 | true 104 | stdcpplatest 105 | 106 | 107 | Console 108 | true 109 | 110 | 111 | 112 | 113 | Level3 114 | true 115 | true 116 | true 117 | WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) 118 | true 119 | stdcpplatest 120 | 121 | 122 | Console 123 | true 124 | true 125 | true 126 | 127 | 128 | 129 | 130 | Level3 131 | true 132 | true 133 | true 134 | NDEBUG;_CONSOLE;%(PreprocessorDefinitions) 135 | true 136 | stdcpplatest 137 | 138 | 139 | Console 140 | true 141 | true 142 | true 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | -------------------------------------------------------------------------------- /riscv-disasm/riscv-disasm.vcxproj.filters: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | {4FC737F1-C7A5-4376-A066-2A32D752A2FF} 6 | cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx 7 | 8 | 9 | {93995380-89BD-4b04-88EB-625FBE52EBFB} 10 | h;hh;hpp;hxx;hm;inl;inc;ipp;xsd 11 | 12 | 13 | {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} 14 | rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms 15 | 16 | 17 | {fe5eb1ed-fcca-489c-a95f-96b66850e866} 18 | 19 | 20 | {a3e12f8f-6cd3-4c07-83ca-8e4b60247b1e} 21 | 22 | 23 | 24 | 25 | Source Files 26 | 27 | 28 | Source Files 29 | 30 | 31 | Source Files 32 | 33 | 34 | Source Files\riscv 35 | 36 | 37 | Source Files\riscv 38 | 39 | 40 | Source Files\riscv 41 | 42 | 43 | Source Files\riscv 44 | 45 | 46 | 47 | 48 | Header Files 49 | 50 | 51 | Header Files 52 | 53 | 54 | Header Files\riscv 55 | 56 | 57 | Header Files\riscv 58 | 59 | 60 | Header Files\riscv 61 | 62 | 63 | Header Files\riscv 64 | 65 | 66 | 67 | 68 | Source Files 69 | 70 | 71 | -------------------------------------------------------------------------------- /riscv-disasm/riscv.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #include "riscv.hpp" -------------------------------------------------------------------------------- /riscv-disasm/riscv.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 xenocidewiki 2 | // This file is part of riscv-disasm. 3 | // 4 | // riscv-disasm is free software : you can redistribute it and /or modify 5 | // it under the terms of the GNU General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // riscv-disasm is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU General Public License 15 | // along with riscv-disasm. If not, see . 16 | #pragma once 17 | 18 | #include 19 | #include "disassembler.hpp" 20 | 21 | namespace riscv 22 | { 23 | } --------------------------------------------------------------------------------