├── 0_Getting Started ├── 01_Step_one.v └── 02_Zero.v ├── 1_Verilog language ├── 03_Wire.v ├── 04_Wire4.v ├── 05_Inverter.v ├── 06_Andgate.v ├── 07_Norgate.v ├── 08_Xnorgate.v ├── 09_Wire_decl.v ├── 10_7458.v ├── 11_Vector0.v ├── 12_7Vector1.v ├── 13_Vector2.v ├── 14_Vectorgates.v ├── 15_Gates4.v ├── 16_Vector3.v ├── 17_Vectorr.v ├── 18_Vector4.v ├── 19_Vector5.v ├── 20_Module.v ├── 21_Module_pos.v ├── 22_Module_name.v ├── 23_Module_shift.v ├── 24_Module_shift8v.v ├── 25_Module_add.v ├── 26_Module_fadd.v ├── 27_Module_cseladd.v ├── 28_Module_addsub.v ├── 29_Alwaysblock1.v ├── 30_Alwaysblock2.v ├── 31_Always if.v ├── 32_Always if2.v ├── 33_Always_case.v ├── 34_Always_case2v.v ├── 35_Always casezv.v ├── 36_Always_nolatches.v ├── 37_Conditional.v ├── 38_Reduction.v ├── 39_Gates100.v ├── 40_Vector100r.v ├── 41_Popcount255.v ├── 42_Adder100i.v └── 43_Bcdadd100.v ├── 2_Circuits ├── 044_Wire_q4h.v ├── 045_GND_q4i.v ├── 046_NOR_q4e.v ├── 047_Anothergate_q4f.v ├── 048_TwoGates_q4g.v ├── 049_Gates.v ├── 050_7420.v ├── 051_Truthtable1.v ├── 052_Mt2015 eq2.v ├── 053_Mt2015 q4a.v ├── 054_.Mt2015 q4bv.v ├── 055_Mt2015 q4.v ├── 056_Ringer.v ├── 057_Thermostat.v ├── 058_Popcount3.v ├── 059_Gates.v ├── 060_Gatesv100.v ├── 061_Mux2to1.v ├── 062_Mux2to1v.v ├── 063_Mux9to1v.v ├── 064_Mux256to1.v ├── 065_Mux256to1v.v ├── 066_Hadd.v ├── 067_Fadd.v ├── 068_Adder3.v ├── 069_m2014 q4j.v ├── 070_ece241 2014 q1c.v ├── 071_Adder100.v ├── 072_Bcdadd4.v ├── 073_Kmap1.v ├── 074_Kmap2.v ├── 075_Kmap3.v ├── 076_Kmap4.v ├── 077_ece241 2013 q2.v ├── 078_m2014 q3.v ├── 079_2012 q1g.v ├── 080_ece241 2014 q3.v ├── 081_Dff.v ├── 082_Dff8.v ├── 083_Dff8r.v ├── 084_Dff8p.v ├── 085_Dff8ar.v ├── 086_Dff16e.v ├── 087_m2014 q4a.v ├── 088_m2014 q4b.v ├── 089_m2014 q4c.v ├── 090_m2014 q4d.v ├── 091_muxdff.v ├── 092_2014 q4a.v ├── 093_ece241 2014 q4.v ├── 094_ece241 2013 q7.v ├── 095_Edgedetect.v ├── 096_Edgedetect2.v ├── 097_Edgecapture_high.v ├── 098_Dualedge_high.v ├── 099_Count15.v ├── 100_Count10.v ├── 101_Count1to10.v ├── 102_Countslow.v ├── 103_Exams:ece241 2014 q7a.v ├── 104_Exams:ece241 2014 q7b_high.v ├── 105_Countbcd.v ├── 106_Count clock.v ├── 107_Shift4.v ├── 108_Rotate100_high.v ├── 109_Shift18.v ├── 110_Lfsr5.v ├── 111_Mt2015 lfsr.v ├── 112_Lfsr32.v ├── 114_Exams:m2014 q4k.v ├── 115_Exams:2014 q4b.v ├── 116_Exams:ece241 2013 q12_high.v ├── 117_Rule90.v ├── 118_ Rule110.v ├── 119_ Conwaylife.v ├── 120_ Fsm1.v ├── 121_ Fsm1s.v ├── 122_ Fsm2.v ├── 123_ Fsm2s.v ├── 124_ Fsm3comb.v ├── 125_ Fsm3onehot.v ├── 126_ Fsm3.v ├── 127_ Fsm3s.v ├── 128_ece241 2013 q4.v ├── 129_Lemmings1.v ├── 130_Lemmings2.v ├── 131_Lemmings3.v ├── 132_Lemmings4.v ├── 133_Fsm onehot.v ├── 134_Fsm ps2.v ├── 135_Fsm ps2data.v ├── 136_Fsm serial.v ├── 137_Fsm serialdata.v ├── 138_Fsm serialdp.v ├── 139_Fsm hdlc.v ├── 140_ece241 2013 q.v ├── 141_ece241 2014 q5a.v ├── 142_ece241 2014 q5b_high.v ├── 143_2014 q3fsm.v ├── 144_2014 q3bfsm.v ├── 145_2014 q3c.v ├── 146_m2014 q6b.v ├── 147_m2014 q6c.v ├── 148_m2014 q6.v ├── 149_2012 q2fsm.v ├── 150_2012 q2b.v ├── 151_2013 q2afsm.v ├── 152_2013 q2bfsm.v ├── 153_review2015 count1k.v ├── 154_review2015 fancytimer.v ├── 155_review2015 fsmonehot.v ├── 156_review2015 shiftcount.v ├── 157_review2015 fsmseq.v ├── 158_review2015 fsmshift_high.v └── 159_review2015 fsm.v ├── 3_Verification Reading simulations ├── 161_Bugs mux2.v ├── 162_Bugs nand3.v ├── 163_Bugs mux4.v ├── 164_Bugs addsubz.v ├── 165_Bugs case.v ├── 166_Sim:circuit1.v ├── 167_Sim:circuit2.v ├── 168_Sim:circuit3.v ├── 169_Sim:circuit4.v ├── 170_Sim:circuit5.v ├── 171_Sim:circuit6.v ├── 172_Sim:circuit7.v ├── 173_Sim:circuit8.v ├── 174_Sim:circuit9.v └── 175_Sim:circui10_high.v ├── 4_Verification Writing Testbenches ├── 176_Tb:clock.v ├── 177_Tb:tb1.v ├── 178_Tb:and.v ├── 179_Tb:tb2.v └── 180_Tb:tff.v ├── 5_CS450 ├── 181_CS450_timer.v ├── 182_CS450_counter_2bc.v ├── 183_CS450_history_shift.v └── 184_CS450_gshare.v └── README.md /0_Getting Started/01_Step_one.v: -------------------------------------------------------------------------------- 1 | module top_module( output one ); 2 | 3 | // Insert your code here 4 | assign one = 1'b1; 5 | endmodule 6 | -------------------------------------------------------------------------------- /0_Getting Started/02_Zero.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | output zero 3 | );// Module body starts after semicolon 4 | assign zero = 1'b0; 5 | endmodule -------------------------------------------------------------------------------- /1_Verilog language/03_Wire.v: -------------------------------------------------------------------------------- 1 | module top_module( input in, output out ); 2 | assign out = in; 3 | endmodule 4 | -------------------------------------------------------------------------------- /1_Verilog language/04_Wire4.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a,b,c, 3 | output w,x,y,z ); 4 | assign w = a; 5 | assign x = b; 6 | assign y = b; 7 | assign z = c; 8 | endmodule -------------------------------------------------------------------------------- /1_Verilog language/05_Inverter.v: -------------------------------------------------------------------------------- 1 | module top_module( input in, output out ); 2 | assign out = ~in; 3 | endmodule 4 | -------------------------------------------------------------------------------- /1_Verilog language/06_Andgate.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | output out ); 5 | assign out = a & b; 6 | endmodule 7 | -------------------------------------------------------------------------------- /1_Verilog language/07_Norgate.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | output out ); 5 | assign out = ~(a | b); 6 | endmodule 7 | -------------------------------------------------------------------------------- /1_Verilog language/08_Xnorgate.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | output out ); 5 | assign out = ~(a ^ b); 6 | endmodule 7 | -------------------------------------------------------------------------------- /1_Verilog language/09_Wire_decl.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module top_module( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output out, 8 | output out_n ); 9 | 10 | wire wire1, wire2, wire3; 11 | assign wire1 = a & b; 12 | assign wire2 = c & d; 13 | assign wire3 = wire1 | wire2; 14 | assign out = wire3; 15 | assign out_n = ~wire3; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /1_Verilog language/10_7458.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input p1a, p1b, p1c, p1d, p1e, p1f, 3 | output p1y, 4 | input p2a, p2b, p2c, p2d, 5 | output p2y ); 6 | 7 | wire abc1, def1, ab2, cd2; 8 | assign abc1 = p1c & p1b & p1a; 9 | assign def1 = p1f & p1e & p1d; 10 | assign p1y = abc1 | def1; 11 | 12 | assign ab2 = p2a & p2b; 13 | assign cd2 = p2c & p2d; 14 | assign p2y = ab2 | cd2; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /1_Verilog language/11_Vector0.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input wire [2:0] vec, 3 | output wire [2:0] outv, 4 | output wire o2, 5 | output wire o1, 6 | output wire o0 ); // Module body starts after module declaration 7 | 8 | assign outv = vec; 9 | assign o0 = outv[0]; 10 | assign o1 = outv[1]; 11 | assign o2 = outv[2]; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /1_Verilog language/12_7Vector1.v: -------------------------------------------------------------------------------- 1 | `default_nettype none // Disable implicit nets. Reduces some types of bugs. 2 | module top_module( 3 | input wire [15:0] in, 4 | output wire [7:0] out_hi, 5 | output wire [7:0] out_lo ); 6 | 7 | assign out_hi = in[15:8]; 8 | assign out_lo = in[7:0]; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /1_Verilog language/13_Vector2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] in, 3 | output [31:0] out );// 4 | 5 | // assign out[31:24] = ...; 6 | assign out = {in[7:0], in[15:8], in[23:16], in[31:24]}; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /1_Verilog language/14_Vectorgates.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [2:0] a, 3 | input [2:0] b, 4 | output [2:0] out_or_bitwise, 5 | output out_or_logical, 6 | output [5:0] out_not 7 | ); 8 | 9 | assign out_or_bitwise = a | b; 10 | assign out_or_logical = a || b; 11 | assign out_not[5:3] = ~b; 12 | assign out_not[2:0] = ~a; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /1_Verilog language/15_Gates4.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [3:0] in, 3 | output out_and, 4 | output out_or, 5 | output out_xor 6 | ); 7 | 8 | assign out_and = in[0] & in[1] & in[2] & in[3]; 9 | assign out_or = in[0] | in[1] | in[2] | in[3]; 10 | assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3]; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /1_Verilog language/16_Vector3.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [4:0] a, b, c, d, e, f, 3 | output [7:0] w, x, y, z );// 4 | 5 | // assign { ... } = { ... }; 6 | // assign {w[7:0], x[7:0], y[7:0], z[7:0]} = {a[4:0], b[4:0], c[4:0], d[4:0], e[4:0], f[4:0], 2'b11}; 7 | assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11}; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /1_Verilog language/17_Vectorr.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [7:0] in, 3 | output [7:0] out 4 | ); 5 | assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]}; 6 | endmodule 7 | -------------------------------------------------------------------------------- /1_Verilog language/18_Vector4.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] in, 3 | output [31:0] out );// 4 | 5 | // assign out = { replicate-sign-bit , the-input }; 6 | assign out = {{24{in[7]}}, in}; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /1_Verilog language/19_Vector5.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, b, c, d, e, 3 | output [24:0] out );// 4 | 5 | assign out[24:20] = ~ {5{a}} ^ {a, b, c, d, e}; 6 | assign out[19:15] = ~ {5{b}} ^ {a, b, c, d, e}; 7 | assign out[14:10] = ~ {5{c}} ^ {a, b, c, d, e}; 8 | assign out[9:5] = ~ {5{d}} ^ {a, b, c, d, e}; 9 | assign out[4:0] = ~ {5{e}} ^ {a, b, c, d, e}; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1_Verilog language/20_Module.v: -------------------------------------------------------------------------------- 1 | module top_module ( input a, input b, output out ); 2 | mod_a instance1(.out(out), .in1(a), .in2(b)); 3 | endmodule 4 | -------------------------------------------------------------------------------- /1_Verilog language/21_Module_pos.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out1, 7 | output out2 8 | ); 9 | mod_a instance1(out1, out2, a, b, c, d); 10 | endmodule 11 | -------------------------------------------------------------------------------- /1_Verilog language/22_Module_name.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out1, 7 | output out2 8 | ); 9 | mod_a instance1(.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2),); 10 | endmodule 11 | -------------------------------------------------------------------------------- /1_Verilog language/23_Module_shift.v: -------------------------------------------------------------------------------- 1 | module top_module ( input clk, input d, output q ); 2 | wire q1, q2; 3 | my_dff instance1(.clk(clk), .d(d), .q(q1)); 4 | my_dff instance2(.clk(clk), .d(q1), .q(q2)); 5 | my_dff instance3(.clk(clk), .d(q2), .q(q)); 6 | endmodule 7 | -------------------------------------------------------------------------------- /1_Verilog language/24_Module_shift8v.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] d, 4 | input [1:0] sel, 5 | output [7:0] q 6 | ); 7 | 8 | wire [7:0] q1, q2, q3; 9 | my_dff8 instance1(.clk(clk), .d(d), .q(q1)); 10 | my_dff8 instance2(.clk(clk), .d(q1), .q(q2)); 11 | my_dff8 instance3(.clk(clk), .d(q2), .q(q3)); 12 | 13 | always @(*) begin 14 | case(sel) 15 | 0 : q = d; 16 | 1 : q = q1; 17 | 2 : q = q2; 18 | 3 : q = q3; 19 | endcase 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /1_Verilog language/25_Module_add.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] a, 3 | input [31:0] b, 4 | output [31:0] sum 5 | ); 6 | 7 | wire cin1, cout1,cout2; 8 | wire [15:0] sum1, sum2; 9 | assign cin1 = 0; 10 | 11 | add16 instance1(.a(a[15:0]), .b(b[15:0]), .cin(cin1), .cout(cout1), .sum(sum1)); 12 | add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(cout1), .cout(cout2), .sum(sum2)); 13 | 14 | assign sum = {sum2, sum1}; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /1_Verilog language/26_Module_fadd.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [31:0] a, 3 | input [31:0] b, 4 | output [31:0] sum 5 | );// 6 | wire cin1, cout1, cout2; 7 | wire [15:0] sum1, sum2; 8 | assign cin1 = 0; 9 | add16 instance1(.a(a[15:0]), .b(b[15:0]), .cin(cin1), .cout(cout1), .sum(sum1)); 10 | add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(cout1), .cout(cout2), .sum(sum2)); 11 | 12 | assign sum = {sum2, sum1}; 13 | 14 | endmodule 15 | 16 | module add1 ( input a, input b, input cin, output sum, output cout ); 17 | 18 | // Full adder module here 19 | assign {cout, sum} = a + b + cin; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /1_Verilog language/27_Module_cseladd.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] a, 3 | input [31:0] b, 4 | output [31:0] sum 5 | ); 6 | 7 | wire cin1, cout1, cin2, cout2, cin3, cout3; 8 | wire [15:0] sum1, sum2, sum3, sum_h; 9 | assign cin1 = 0; 10 | assign cin2 = 0; 11 | assign cin3 = 1; 12 | 13 | add16 instance1(.a(a[15:0]), .b(b[15:0]), .cin(cin1), .cout(cout1), .sum(sum1)); 14 | add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(cin2), .cout(cout2), .sum(sum2)); 15 | add16 instance3(.a(a[31:16]), .b(b[31:16]), .cin(cin3), .cout(cout3), .sum(sum3)); 16 | 17 | always @(*) begin 18 | case(cout1) 19 | 0 : sum_h = sum2; 20 | 1 : sum_h = sum3; 21 | endcase 22 | end 23 | 24 | assign sum = {sum_h, sum1}; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /1_Verilog language/28_Module_addsub.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] a, 3 | input [31:0] b, 4 | input sub, 5 | output [31:0] sum 6 | ); 7 | 8 | wire cout1, cout2; 9 | wire [15:0] sum1, sum2; 10 | wire [31:0] b_xor; 11 | 12 | always @(*) begin 13 | if(sub) 14 | b_xor = ~b; 15 | else 16 | b_xor = b; 17 | end 18 | 19 | add16 instance1(.a(a[15:0]), .b(b_xor[15:0]), .cin(sub), .cout(cout1), .sum(sum1)); 20 | add16 instance2(.a(a[31:16]), .b(b_xor[31:16]), .cin(cout1), .cout(cout2), .sum(sum2)); 21 | 22 | assign sum = {sum2, sum1}; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /1_Verilog language/29_Alwaysblock1.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module( 3 | input a, 4 | input b, 5 | output wire out_assign, 6 | output reg out_alwaysblock 7 | ); 8 | 9 | assign out_assign = a & b; 10 | always @(*) out_alwaysblock = a & b; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /1_Verilog language/30_Alwaysblock2.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module( 3 | input clk, 4 | input a, 5 | input b, 6 | output wire out_assign, 7 | output reg out_always_comb, 8 | output reg out_always_ff ); 9 | 10 | assign out_assign = a ^ b; 11 | always @(*) out_always_comb = a ^ b; 12 | always @(posedge clk) out_always_ff <= a ^ b; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /1_Verilog language/31_Always if.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module( 3 | input a, 4 | input b, 5 | input sel_b1, 6 | input sel_b2, 7 | output wire out_assign, 8 | output reg out_always ); 9 | 10 | assign out_assign = (sel_b1 && sel_b2) ? b : a; 11 | always @(*) out_always = (sel_b1 && sel_b2) ? b : a; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /1_Verilog language/32_Always if2.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module ( 3 | input cpu_overheated, 4 | output reg shut_off_computer, 5 | input arrived, 6 | input gas_tank_empty, 7 | output reg keep_driving ); // 8 | 9 | always @(*) begin 10 | if (cpu_overheated) 11 | shut_off_computer = 1; 12 | else 13 | shut_off_computer = 0; 14 | end 15 | 16 | always @(*) begin 17 | if (~arrived) 18 | keep_driving = ~gas_tank_empty; 19 | else 20 | keep_driving = 0; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /1_Verilog language/33_Always_case.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module ( 3 | input [2:0] sel, 4 | input [3:0] data0, 5 | input [3:0] data1, 6 | input [3:0] data2, 7 | input [3:0] data3, 8 | input [3:0] data4, 9 | input [3:0] data5, 10 | output reg [3:0] out );// 11 | 12 | always@(*) begin // This is a combinational circuit 13 | case(sel) 14 | 0 : out = data0; 15 | 1 : out = data1; 16 | 2 : out = data2; 17 | 3 : out = data3; 18 | 4 : out = data4; 19 | 5 : out = data5; 20 | default : out = 0; 21 | endcase 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /1_Verilog language/34_Always_case2v.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module ( 3 | input [3:0] in, 4 | output reg [1:0] pos ); 5 | 6 | always @(*) begin 7 | case(in) 8 | 4'b0000 : pos = 0; 9 | 4'b0001 : pos = 0; 10 | 4'b0010 : pos = 1; 11 | 4'b0011 : pos = 0; 12 | 4'b0100 : pos = 2; 13 | 4'b0101 : pos = 0; 14 | 4'b0110 : pos = 1; 15 | 4'b0111 : pos = 0; 16 | 4'b1000 : pos = 3; 17 | 4'b1001 : pos = 0; 18 | 4'b1010 : pos = 1; 19 | 4'b1011 : pos = 0; 20 | 4'b1100 : pos = 2; 21 | 4'b1101 : pos = 0; 22 | 4'b1110 : pos = 1; 23 | 4'b1111 : pos = 0; 24 | endcase 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /1_Verilog language/35_Always casezv.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module ( 3 | input [7:0] in, 4 | output reg [2:0] pos ); 5 | 6 | always @(*) begin 7 | casez(in) 8 | 8'bzzzzzzz1 : pos = 0; 9 | 8'bzzzzzz1z : pos = 1; 10 | 8'bzzzzz1zz : pos = 2; 11 | 8'bzzzz1zzz : pos = 3; 12 | 8'bzzz1zzzz : pos = 4; 13 | 8'bzz1zzzzz : pos = 5; 14 | 8'bz1zzzzzz : pos = 6; 15 | 8'b1zzzzzzz : pos = 7; 16 | default : pos = 0; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /1_Verilog language/36_Always_nolatches.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module ( 3 | input [15:0] scancode, 4 | output reg left, 5 | output reg down, 6 | output reg right, 7 | output reg up ); 8 | 9 | always @(*) begin 10 | left = 0; down = 0; right = 0; up = 0; 11 | case(scancode) 12 | 16'he06b : left = 1; 13 | 16'he072 : down = 1; 14 | 16'he074 : right = 1; 15 | 16'he075 : up = 1; 16 | default : ; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /1_Verilog language/37_Conditional.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] a, b, c, d, 3 | output [7:0] min);// 4 | 5 | // assign intermediate_result1 = compare? true: false; 6 | wire [7:0] min_mid, min_mid1, min_mid2; 7 | assign min_mid = (a < b) ? a : b; 8 | assign min_mid1 = (c < min_mid) ? c : min_mid; 9 | assign min_mid2 = (d < min_mid1) ? d : min_mid1; 10 | assign min = min_mid2; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /1_Verilog language/38_Reduction.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] in, 3 | output parity); 4 | assign parity = ^ in[7:0]; 5 | endmodule 6 | -------------------------------------------------------------------------------- /1_Verilog language/39_Gates100.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] in, 3 | output out_and, 4 | output out_or, 5 | output out_xor 6 | ); 7 | assign out_and = & in[99:0]; 8 | assign out_or = | in[99:0]; 9 | assign out_xor = ^ in[99:0]; 10 | endmodule 11 | -------------------------------------------------------------------------------- /1_Verilog language/40_Vector100r.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] in, 3 | output [99:0] out 4 | ); 5 | 6 | always @(*) begin 7 | for(integer i = 0; i < 100; i++) 8 | out[i] = in[99 - i]; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1_Verilog language/41_Popcount255.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [254:0] in, 3 | output [7:0] out ); 4 | 5 | always @(*) begin 6 | out = 0; 7 | for(int i = 0; i < 255; i++) begin 8 | if(in[i]) 9 | out = out + 1; 10 | else 11 | out = out + 0; 12 | end 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /1_Verilog language/42_Adder100i.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] a, b, 3 | input cin, 4 | output [99:0] cout, 5 | output [99:0] sum ); 6 | 7 | always @(*) begin 8 | for(int i = 0; i < 100; i++) begin 9 | if(!i) begin // 加法刚开始，所以进位标志用cin 10 | if(!cin) begin // 第一种情况，无进位 11 | if(a[i] == 0 && b[i] == 0) begin 12 | sum[i] = 0; 13 | cout[i] = 0; 14 | end 15 | else if((a[i] == 0 && b[i] == 1) || (a[i] == 1 && b[i] == 0)) begin 16 | sum[i] = 1; 17 | cout[i] = 0; 18 | end 19 | else begin 20 | sum[i] = 0; 21 | cout[i] = 1; 22 | end 23 | end 24 | else begin // 第二种情况，进位 25 | if(a[i] == 0 && b[i] == 0) begin 26 | sum[i] = 1; 27 | cout[i] = 0; 28 | end 29 | else if((a[i] == 0 && b[i] == 1) || (a[i] == 1 && b[i] == 0)) begin 30 | sum[i] = 0; 31 | cout[i] = 1; 32 | end 33 | else begin 34 | sum[i] = 1; 35 | cout[i] = 1; 36 | end 37 | end 38 | end 39 | else begin // 加法已经开始，所以进位标志用cout[i - 1] 40 | if(!cout[i - 1]) begin // 第一种情况，无进位 41 | if(a[i] == 0 && b[i] == 0) begin 42 | sum[i] = 0; 43 | cout[i] = 0; 44 | end 45 | else if((a[i] == 0 && b[i] == 1) || (a[i] == 1 && b[i] == 0)) begin 46 | sum[i] = 1; 47 | cout[i] = 0; 48 | end 49 | else begin 50 | sum[i] = 0; 51 | cout[i] = 1; 52 | end 53 | end 54 | else begin // 第二种情况，进位 55 | if(a[i] == 0 && b[i] == 0) begin 56 | sum[i] = 1; 57 | cout[i] = 0; 58 | end 59 | else if((a[i] == 0 && b[i] == 1) || (a[i] == 1 && b[i] == 0)) begin 60 | sum[i] = 0; 61 | cout[i] = 1; 62 | end 63 | else begin 64 | sum[i] = 1; 65 | cout[i] = 1; 66 | end 67 | end 68 | end 69 | end 70 | end 71 | 72 | // M-HHH 提供的精简思路 73 | // assign cout[0] = a[0] & b[0] | a[0] & cin | b[0] & cin; 74 | // assign sum[0] = a[0] ^ b[0] ^ cin; 75 | 76 | // integer i, j; 77 | 78 | // always @ (*) 79 | // begin 80 | // for (i=1; i<100; i++) 81 | // begin 82 | // sum[i] = a[i] ^ b[i] ^ cout[i-1]; 83 | // end 84 | // end 85 | 86 | // always @ (*) 87 | // begin 88 | // for(i=1; i<100; i++) 89 | // begin 90 | // cout[i] = a[i] & b[i] | a[i] & cout[i-1] | b[i] & cout[i-1]; 91 | // end 92 | // end 93 | 94 | //基于 M-HHH 的思路作出的二次优化 95 | // assign cout[0] = a[0] & b[0] | a[0] & cin | b[0] & cin; 96 | // assign sum[0] = a[0] ^ b[0] ^ cin; 97 | 98 | // integer i; 99 | 100 | // always @ (*) begin 101 | // for (i=1; i<100; i++) begin 102 | // cout[i] = a[i] & b[i] | a[i] & cout[i-1] | b[i] & cout[i-1]; 103 | // sum[i] = a[i] ^ b[i] ^ cout[i-1]; 104 | // end 105 | // end 106 | 107 | 108 | endmodule 109 | -------------------------------------------------------------------------------- /1_Verilog language/43_Bcdadd100.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [399:0] a, b, 3 | input cin, 4 | output cout, 5 | output [399:0] sum ); 6 | 7 | wire [399:0] cout_tmp; 8 | bcd_fadd fadd(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(cout_tmp[0]),.sum(sum[3:0])); 9 | assign cout = cout_tmp[396]; 10 | 11 | generate 12 | genvar i; 13 | for(i = 4; i < 400; i=i+4) begin : adder 14 | bcd_fadd fadd(.a(a[i+3:i]), .b(b[i+3:i]), .cin(cout_tmp[i-4]), .cout(cout_tmp[i]),.sum(sum[i+3:i])); 15 | end 16 | endgenerate 17 | 18 | endmodule -------------------------------------------------------------------------------- /2_Circuits/044_Wire_q4h.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in, 3 | output out); 4 | 5 | assign out = in; 6 | 7 | endmodule -------------------------------------------------------------------------------- /2_Circuits/045_GND_q4i.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | output out); 3 | 4 | assign out = 1'b0; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /2_Circuits/046_NOR_q4e.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in1, 3 | input in2, 4 | output out); 5 | 6 | assign out = ~(in1 | in2); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/047_Anothergate_q4f.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in1, 3 | input in2, 4 | output out); 5 | 6 | assign out = in1 & (~in2); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/048_TwoGates_q4g.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in1, 3 | input in2, 4 | input in3, 5 | output out); 6 | 7 | assign out = (~(in1 ^ in2)) ^ in3; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2_Circuits/049_Gates.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, 3 | output out_and, 4 | output out_or, 5 | output out_xor, 6 | output out_nand, 7 | output out_nor, 8 | output out_xnor, 9 | output out_anotb 10 | ); 11 | 12 | assign out_and = a & b; 13 | assign out_or = a | b; 14 | assign out_xor = a ^ b; 15 | assign out_nand = ~(a & b); 16 | assign out_nor = ~(a | b); 17 | assign out_xnor = ~(a ^ b); 18 | assign out_anotb = a & ~b; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2_Circuits/050_7420.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input p1a, p1b, p1c, p1d, 3 | output p1y, 4 | input p2a, p2b, p2c, p2d, 5 | output p2y ); 6 | 7 | assign p1y = ~(p1a & p1b & p1c & p1d); 8 | assign p2y = ~(p2a & p2b & p2c & p2d); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2_Circuits/051_Truthtable1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input x3, 3 | input x2, 4 | input x1, // three inputs 5 | output f // one output 6 | ); 7 | wire [2:0] tmp; 8 | assign tmp = {x3,x2,x1}; 9 | always @(*) begin 10 | case(tmp) 11 | 2,3,5,7: begin 12 | f = 1; 13 | end 14 | 0,1,4,6: begin 15 | f = 0; 16 | end 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2_Circuits/052_Mt2015 eq2.v: -------------------------------------------------------------------------------- 1 | module top_module ( input [1:0] A, input [1:0] B, output z ); 2 | always @(*) begin 3 | if(A == B) 4 | z = 1; 5 | else 6 | z = 0; 7 | end 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/053_Mt2015 q4a.v: -------------------------------------------------------------------------------- 1 | module top_module (input x, input y, output z); 2 | assign z = (x ^ y) & x; 3 | endmodule 4 | -------------------------------------------------------------------------------- /2_Circuits/054_.Mt2015 q4bv.v: -------------------------------------------------------------------------------- 1 | module top_module ( input x, input y, output z ); 2 | always @(*) begin 3 | if(x == y) 4 | z = 1; 5 | else 6 | z = 0; 7 | end 8 | endmodule -------------------------------------------------------------------------------- /2_Circuits/055_Mt2015 q4.v: -------------------------------------------------------------------------------- 1 | module top_module (input x, input y, output z); 2 | wire [3:0] z_tmp; 3 | 4 | task A; 5 | input x,y; 6 | output z; 7 | begin 8 | z = (x ^ y) & x; 9 | end 10 | endtask 11 | 12 | task B; 13 | input x,y; 14 | output z; 15 | begin 16 | if(x == y) 17 | z = 1; 18 | else 19 | z = 0; 20 | end 21 | endtask 22 | 23 | always @(*) begin 24 | A(x,y,z_tmp[0]); 25 | B(x,y,z_tmp[1]); 26 | A(x,y,z_tmp[2]); 27 | B(x,y,z_tmp[3]); 28 | end 29 | 30 | assign z = (z_tmp[0] | z_tmp[1]) ^ (z_tmp[2] & z_tmp[3]); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /2_Circuits/056_Ringer.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input ring, 3 | input vibrate_mode, 4 | output ringer, // Make sound 5 | output motor // Vibrate 6 | ); 7 | 8 | assign ringer = ring & (~vibrate_mode); 9 | assign motor = ring & vibrate_mode; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2_Circuits/057_Thermostat.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input too_cold, 3 | input too_hot, 4 | input mode, 5 | input fan_on, 6 | output heater, 7 | output aircon, 8 | output fan 9 | ); 10 | 11 | assign heater = mode & too_cold; 12 | assign aircon = (~mode) & too_hot; 13 | assign fan = (heater | aircon) | fan_on; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /2_Circuits/058_Popcount3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [2:0] in, 3 | output [1:0] out ); 4 | 5 | integer i; 6 | 7 | always @(*) begin 8 | out = 0; 9 | for(i = 0; i < 3; i ++) begin 10 | if(in[i]) 11 | out = out + 1; 12 | end 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /2_Circuits/059_Gates.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [3:0] in, 3 | output [2:0] out_both, 4 | output [3:1] out_any, 5 | output [3:0] out_different ); 6 | 7 | integer i; 8 | 9 | always @(*) begin 10 | for(i = 0; i < 3; i ++) begin 11 | out_both[i] = in[i] & in[i+1]; 12 | out_any[i+1] = in[i] | in[i+1]; 13 | out_different[i] = (in[i] != in[i+1]) ? 1:0; 14 | end 15 | out_different[3] = (in[0] != in[3]) ? 1:0; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /2_Circuits/060_Gatesv100.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] in, 3 | output [98:0] out_both, 4 | output [99:1] out_any, 5 | output [99:0] out_different ); 6 | 7 | integer i; 8 | 9 | always @(*) begin 10 | for(i = 0; i < 99; i ++) begin 11 | out_both[i] = in[i] & in[i+1]; 12 | out_any[i+1] = in[i] | in[i+1]; 13 | out_different[i] = (in[i] != in[i+1]) ? 1:0; 14 | end 15 | out_different[99] = (in[0] != in[99]) ? 1:0; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /2_Circuits/061_Mux2to1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, sel, 3 | output out ); 4 | 5 | assign out = sel ? b : a; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /2_Circuits/062_Mux2to1v.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] a, b, 3 | input sel, 4 | output [99:0] out ); 5 | 6 | assign out = sel ? b : a; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/063_Mux9to1v.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [15:0] a, b, c, d, e, f, g, h, i, 3 | input [3:0] sel, 4 | output [15:0] out ); 5 | 6 | always @(*) begin 7 | case(sel) 8 | 0 : out = a; 9 | 1 : out = b; 10 | 2 : out = c; 11 | 3 : out = d; 12 | 4 : out = e; 13 | 5 : out = f; 14 | 6 : out = g; 15 | 7 : out = h; 16 | 8 : out = i; 17 | default : out = 16'hffff; 18 | endcase 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /2_Circuits/064_Mux256to1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [255:0] in, 3 | input [7:0] sel, 4 | output out ); 5 | 6 | assign out = in[sel]; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/065_Mux256to1v.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [1023:0] in, 3 | input [7:0] sel, 4 | output [3:0] out ); 5 | 6 | assign out = in[sel*4+3 -: 4]; // - and : should be put together 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/066_Hadd.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, 3 | output cout, sum ); 4 | 5 | assign {cout, sum} = a + b; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /2_Circuits/067_Fadd.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, cin, 3 | output cout, sum ); 4 | 5 | assign sum = a ^ b ^ cin; 6 | assign cout = a & b | a & cin | b & cin; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/068_Adder3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [2:0] a, b, 3 | input cin, 4 | output [2:0] cout, 5 | output [2:0] sum ); 6 | 7 | integer i; 8 | assign sum[0] = a[0] ^ b[0] ^ cin; 9 | assign cout[0] = a[0] & b[0] | a[0] & cin | b[0] & cin; 10 | always @(*) begin 11 | for(i = 1; i < 3; i=i+1) begin 12 | sum[i] = a[i] ^ b[i] ^ cout[i-1]; 13 | cout[i] = a[i] & b[i] | a[i] & cout[i-1] | b[i] & cout[i-1]; 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2_Circuits/069_m2014 q4j.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:0] x, 3 | input [3:0] y, 4 | output [4:0] sum); 5 | 6 | integer i; 7 | wire [3:0] cout; 8 | assign sum[0] = x[0] ^ y[0]; 9 | assign cout[0] = x[0] & y[0]; 10 | always @(*) begin 11 | for(i = 1; i < 4; i=i+1) begin 12 | sum[i] = x[i] ^ y[i] ^ cout[i-1]; 13 | cout[i] = x[i] & y[i] | x[i] & cout[i-1] | y[i] & cout[i-1]; 14 | end 15 | sum[4] = cout[3]; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /2_Circuits/070_ece241 2014 q1c.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] a, 3 | input [7:0] b, 4 | output [7:0] s, 5 | output overflow 6 | ); // 7 | 8 | assign s = a + b; 9 | assign overflow = (a[7] == b[7] && a[7] != s[7]) ? 1 : 0; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2_Circuits/071_Adder100.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] a, b, 3 | input cin, 4 | output cout, 5 | output [99:0] sum ); 6 | 7 | wire [99:0] cout_tmp; 8 | assign sum[0] = a[0] ^ b[0] ^ cin; 9 | assign cout_tmp[0] = a[0] & b[0] | a[0] & cin | b[0] & cin; 10 | integer i; 11 | always @(*) begin 12 | for(i = 1; i < 100; i = i + 1) begin 13 | sum[i] = a[i] ^ b[i] ^ cout_tmp[i-1]; 14 | cout_tmp[i] = a[i] & b[i] | a[i] & cout_tmp[i-1] | b[i] & cout_tmp[i-1]; 15 | end 16 | cout = cout_tmp[99]; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /2_Circuits/072_Bcdadd4.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [15:0] a, b, 3 | input cin, 4 | output cout, 5 | output [15:0] sum ); 6 | 7 | wire [15:0] cout_tmp; 8 | bcd_fadd fadd(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(cout_tmp[0]), .sum(sum[3:0])); 9 | assign cout = cout_tmp[12]; 10 | generate 11 | genvar i; 12 | for(i = 4; i < 16; i = i + 4) begin:adder 13 | bcd_fadd fadd(.a(a[i + 3:i]), .b(b[i + 3:i]), .cin(cout_tmp[i-4]), .cout(cout_tmp[i]), .sum(sum[i + 3:i])); 14 | end 15 | endgenerate 16 | 17 | endmodule 18 | 19 | // Below solution is designed by @Lysias-1998 20 | 21 | // module top_module( 22 | // input [15:0] a, b, 23 | // input cin, 24 | // output cout, 25 | // output [15:0] sum ); 26 | 27 | // wire [4:0] c; 28 | 29 | // assign c[0] = cin; 30 | // assign cout = c[4]; 31 | // generate 32 | // genvar i; 33 | // for (i = 0; i < 4; i = i + 1) begin : adders 34 | // bcd_fadd the_bcd_fadders ( 35 | // .a(a[i*4+3 : i*4]), 36 | // .b(b[i*4+3 : i*4]), 37 | // .cin(c[i]), 38 | // .cout(c[i+1]), 39 | // .sum(sum[i*4+3 : i*4]) 40 | // ); 41 | // end 42 | // endgenerate 43 | 44 | // endmodule 45 | -------------------------------------------------------------------------------- /2_Circuits/073_Kmap1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | output out ); 6 | 7 | assign out = ~(~a & ~b & ~c); 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2_Circuits/074_Kmap2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out ); 7 | 8 | assign out = (~a&~b&~c) | (~a&~c&~d) | (a&~b&~c) | (b&c&d) | (a&c&d) | (~a&b&c) | (~a&c&~d); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2_Circuits/075_Kmap3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out ); 7 | 8 | assign out = (~b & c) | (a & c) | (a & ~c); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2_Circuits/076_Kmap4.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out ); 7 | 8 | assign out = (~a&b&~c&~d) | (a&~b&~c&~d) | (~a&~b&~c&d) | (a&b&~c&d) | (~a&b&c&d) | (a&~b&c&d) | (~a&~b&c&~d) | (a&b&c&~d); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2_Circuits/077_ece241 2013 q2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out_sop, 7 | output out_pos 8 | ); 9 | 10 | assign out_sop = (~a & ~b & c) | (b & c & d) | (a & c & d); 11 | assign out_pos = out_sop; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /2_Circuits/078_m2014 q3.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [4:1] x, 3 | output f ); 4 | 5 | assign f = ~((~x[2] & ~x[3] & x[4]) | (~x[1] & x[2] & ~x[3] & x[4]) | (x[1] & x[2] & x[3] & ~x[4]) | (~x[1] & x[2] & ~x[3] & ~x[4])); 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /2_Circuits/079_2012 q1g.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [4:1] x, 3 | output f 4 | ); 5 | 6 | assign f = (~x[1] & x[3]) | (~x[2] & ~x[3] & ~x[4]) | (x[1] & ~x[2] & x[3] & ~x[4]) | (x[2] & x[3] & x[4]); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2_Circuits/080_ece241 2014 q3.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input c, 3 | input d, 4 | output [3:0] mux_in 5 | ); 6 | 7 | assign mux_in[0] = c | d; 8 | assign mux_in[1] = 0; 9 | assign mux_in[2] = ~d; 10 | assign mux_in[3] = c & d; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2_Circuits/081_Dff.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, // Clocks are used in sequential circuits 3 | input d, 4 | output reg q );// 5 | 6 | always @(posedge clk) begin 7 | q <= d; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2_Circuits/082_Dff8.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] d, 4 | output [7:0] q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | q <= d; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2_Circuits/083_Dff8r.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input [7:0] d, 5 | output [7:0] q 6 | ); 7 | 8 | always @(posedge clk) begin 9 | if(reset) begin 10 | q <= 0; 11 | end 12 | else begin 13 | q <= d; 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2_Circuits/084_Dff8p.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input [7:0] d, 5 | output [7:0] q 6 | ); 7 | 8 | always @(negedge clk) begin 9 | if(reset) begin 10 | q <= 8'h34; 11 | end 12 | else begin 13 | q <= d; 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2_Circuits/085_Dff8ar.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input areset, // active high asynchronous reset 4 | input [7:0] d, 5 | output [7:0] q 6 | ); 7 | 8 | always @(posedge clk or posedge areset) begin 9 | if(areset) begin 10 | q <= 0; 11 | end 12 | else begin 13 | q <= d; 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2_Circuits/086_Dff16e.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, 4 | input [1:0] byteena, 5 | input [15:0] d, 6 | output [15:0] q 7 | ); 8 | 9 | always @(posedge clk) begin 10 | if(!resetn) begin 11 | q <= 0; 12 | end 13 | else begin 14 | q[15:8] <= byteena[1] ? d[15:8] : q[15:8]; 15 | q[7:0] <= byteena[0] ? d[7:0] : q[7:0]; 16 | end 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /2_Circuits/087_m2014 q4a.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input d, 3 | input ena, 4 | output q); 5 | 6 | always @(*) begin 7 | if (ena) begin 8 | q <= d; 9 | end 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2_Circuits/088_m2014 q4b.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | input ar, // asynchronous reset 5 | output q); 6 | 7 | always @(posedge clk or posedge ar) begin 8 | if(ar) begin 9 | q <= 0; 10 | end 11 | else begin 12 | q <= d; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2_Circuits/089_m2014 q4c.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | input r, // synchronous reset 5 | output q); 6 | 7 | always @(posedge clk) begin 8 | if(r) begin 9 | q <= 0; 10 | end 11 | else begin 12 | q <= d; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2_Circuits/090_m2014 q4d.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input in, 4 | output out); 5 | 6 | always @(posedge clk) begin 7 | out <= out ^ in; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2_Circuits/091_muxdff.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input L, 4 | input r_in, 5 | input q_in, 6 | output reg Q); 7 | 8 | always @(posedge clk) begin 9 | Q <= L ? r_in : q_in; 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2_Circuits/092_2014 q4a.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input w, R, E, L, 4 | output Q 5 | ); 6 | 7 | reg tmp; 8 | //not use <= 9 | always @(posedge clk) begin 10 | tmp = E ? w : Q; 11 | Q = L ? R : tmp; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /2_Circuits/093_ece241 2014 q4.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input x, 4 | output z 5 | ); 6 | reg [2:0] Q; 7 | initial z = 1; 8 | always @(posedge clk) begin 9 | Q[0] = Q[0] ^ x; 10 | Q[1] = ~Q[1] & x; 11 | Q[2] = ~Q[2] | x; 12 | z = ~(Q[0] | Q[1] | Q[2]); 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /2_Circuits/094_ece241 2013 q7.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input j, 4 | input k, 5 | output Q); 6 | 7 | always @(posedge clk) begin 8 | if(!j) begin 9 | Q <= k ? j : Q; 10 | end 11 | else begin 12 | Q <= k ? ~Q : j; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2_Circuits/095_Edgedetect.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] in, 4 | output [7:0] pedge 5 | ); 6 | integer i; 7 | reg [7:0] in_tmp; 8 | always @(posedge clk) begin 9 | for(i = 0; i < 8; i = i + 1) begin 10 | if(in_tmp[i] != in[i] && in[i] == 1) begin 11 | pedge[i] = 1; 12 | end 13 | else begin 14 | pedge[i] = 0; 15 | end 16 | in_tmp[i] = in[i]; 17 | end 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2_Circuits/096_Edgedetect2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] in, 4 | output [7:0] anyedge 5 | ); 6 | 7 | integer i; 8 | reg [7:0] in_tmp; 9 | always @(posedge clk) begin 10 | for(i = 0; i < 8; i = i + 1) begin 11 | if(in_tmp[i] != in[i]) begin 12 | anyedge[i] = 1; 13 | end 14 | else begin 15 | anyedge[i] = 0; 16 | end 17 | in_tmp[i] = in[i]; 18 | end 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /2_Circuits/097_Edgecapture_high.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input [31:0] in, 5 | output [31:0] out 6 | ); 7 | 8 | reg [31:0] old, result, tmp; 9 | initial tmp = 0; 10 | always @(posedge clk) begin 11 | if(reset) begin 12 | old = in; 13 | result = 0; 14 | out = 0; 15 | end 16 | else begin 17 | tmp = (in ^ old) & old; 18 | result = result | tmp; 19 | out = result; 20 | old = in; 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /2_Circuits/098_Dualedge_high.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | output q 5 | ); 6 | 7 | reg [1:0] status; 8 | 9 | always @(posedge clk) begin 10 | status[0] = d; 11 | end 12 | 13 | always @(negedge clk) begin 14 | status[1] = d; 15 | end 16 | 17 | assign q = clk ? status[0] : status[1]; 18 | 19 | endmodule -------------------------------------------------------------------------------- /2_Circuits/099_Count15.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous active-high reset 4 | output [3:0] q); 5 | 6 | always @(posedge clk) begin 7 | if(reset) begin 8 | q <= 0; 9 | end 10 | else begin 11 | if(q == 15) begin 12 | q <= 0; 13 | end 14 | else begin 15 | q <= q + 1; 16 | end 17 | end 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2_Circuits/100_Count10.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous active-high reset 4 | output [3:0] q); 5 | 6 | always @(posedge clk) begin 7 | if(reset) begin 8 | q <= 0; 9 | end 10 | else begin 11 | if(q == 9) begin 12 | q <= 0; 13 | end 14 | else begin 15 | q <= q + 1; 16 | end 17 | end 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2_Circuits/101_Count1to10.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output [3:0] q); 5 | 6 | always @(posedge clk) begin 7 | if(reset) begin 8 | q <= 1; 9 | end 10 | else begin 11 | if(q == 10) begin 12 | q <= 1; 13 | end 14 | else begin 15 | q <= q + 1; 16 | end 17 | end 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2_Circuits/102_Countslow.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input slowena, 4 | input reset, 5 | output [3:0] q); 6 | 7 | always @(posedge clk) begin 8 | if(reset) begin 9 | q <= 0; 10 | end 11 | else begin 12 | if(slowena) begin 13 | if(q == 9) begin 14 | q <= 0; 15 | end 16 | else begin 17 | q <= q + 1; 18 | end 19 | end 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /2_Circuits/103_Exams:ece241 2014 q7a.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input enable, 5 | output [3:0] Q, 6 | output c_enable, 7 | output c_load, 8 | output [3:0] c_d 9 | ); // 10 | wire [3:0] Q_tmp; 11 | assign c_enable = enable; 12 | assign c_d = c_load ? 1 : 0; 13 | always @(posedge clk) begin 14 | if(reset) begin 15 | Q <= 1; 16 | Q_tmp <= 1; 17 | end 18 | else begin 19 | if(enable) begin 20 | if(Q == 12) begin 21 | Q <= 1; 22 | Q_tmp <= 1; 23 | end 24 | else begin 25 | Q <= Q + 1; 26 | Q_tmp <= Q_tmp + 1; 27 | end 28 | end 29 | end 30 | end 31 | 32 | always @(*) begin 33 | if(reset || (Q == 12 && c_enable)) begin 34 | c_load <= 1; 35 | end 36 | else begin 37 | c_load <= 0; 38 | end 39 | end 40 | 41 | count4 the_counter (clk, c_enable, c_load, c_d, Q_tmp); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /2_Circuits/104_Exams:ece241 2014 q7b_high.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output OneHertz, 5 | output [2:0] c_enable 6 | ); // 7 | 8 | wire [3:0] q0, q1, q2; 9 | 10 | bcdcount counter0 (clk, reset, c_enable[0], q0); 11 | bcdcount counter1 (clk, reset, c_enable[1], q1); 12 | bcdcount counter2 (clk, reset, c_enable[2], q2); 13 | 14 | assign c_enable = {(q1 == 4'd9) && (q0 == 4'd9), q0 == 4'd9, 1'b1}; 15 | assign OneHertz = (q2 == 4'd9) && (q1 == 4'd9) && (q0 == 4'd9); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2_Circuits/105_Countbcd.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous active-high reset 4 | output [3:1] ena, 5 | output [15:0] q); 6 | 7 | always @(posedge clk) begin 8 | if(reset) begin 9 | q = 0; 10 | ena = 0; 11 | end 12 | else begin 13 | q[3:0] = q[3:0] + 1; 14 | ena[1] = (q[3:0] == 9) ? 1 : 0; 15 | if(q[3:0] == 10) begin 16 | q[3:0] = 0; 17 | q[7:4] = q[7:4] + 1; 18 | end 19 | ena[2] = ((q[7:4] == 9) && (q[3:0] == 9)) ? 1 : 0; 20 | if(q[7:4] == 10) begin 21 | q[7:4] = 0; 22 | q[11:8] = q[11:8] + 1; 23 | end 24 | ena[3] = ((q[11:8] == 9) && (q[7:4] == 9) && (q[3:0] == 9)) ? 1 : 0; 25 | if(q[11:8] == 10) begin 26 | q[11:8] = 0; 27 | q[15:12] = q[15:12] + 1; 28 | end 29 | if(q[15:12] == 10) begin 30 | q = 0; 31 | end 32 | end 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /2_Circuits/106_Count clock.v: -------------------------------------------------------------------------------- 1 | module top_module 2 | ( 3 | input clk, 4 | input reset, 5 | input ena, 6 | output pm, 7 | output [7:0] hh, 8 | output [7:0] mm, 9 | output [7:0] ss 10 | ); 11 | 12 | reg p; //0: am, 1: pm 13 | reg [7:0] h; 14 | reg [7:0] m; 15 | reg [7:0] s; 16 | 17 | always @ (posedge clk) 18 | begin 19 | if(reset) 20 | begin 21 | p <= 0; 22 | h <= 8'h12; 23 | m <= 8'h00; 24 | s <= 8'h00; 25 | end 26 | else 27 | begin 28 | if(ena) 29 | begin 30 | if(s < 8'h59) 31 | begin 32 | if(s[3:0] < 4'h9) 33 | begin 34 | s[3:0] <= s[3:0] + 1'h1; 35 | end 36 | else 37 | begin 38 | s[3:0] <= 0; 39 | s[7:4] <= s[7:4] + 1'h1; 40 | end 41 | end 42 | else 43 | begin 44 | s <= 0; 45 | if(m < 8'h59) 46 | begin 47 | if(m[3:0] < 4'h9) 48 | begin 49 | m[3:0] <= m[3:0] + 1'h1; 50 | end 51 | else 52 | begin 53 | m[3:0] <= 0; 54 | m[7:4] <= m[7:4] + 1'h1; 55 | end 56 | end 57 | else 58 | begin 59 | m <= 1'h0; 60 | if(h == 8'h11) 61 | p = !p; 62 | if(h < 8'h12) 63 | begin 64 | if(h[3:0] < 4'h9) 65 | h[3:0] <= h[3:0] + 1'h1; 66 | else 67 | begin 68 | h[3:0] <= 4'h0; 69 | h[7:4] <= h[7:4] + 1'h1; 70 | end 71 | end 72 | else 73 | begin 74 | h <= 1'h1; 75 | end 76 | end 77 | end 78 | end 79 | end 80 | end 81 | 82 | assign pm = p; 83 | assign hh = h; 84 | assign mm = m; 85 | assign ss = s; 86 | 87 | endmodule -------------------------------------------------------------------------------- /2_Circuits/107_Shift4.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // async active-high reset to zero 4 | input load, 5 | input ena, 6 | input [3:0] data, 7 | output reg [3:0] q); 8 | 9 | always @(posedge clk or posedge areset) begin 10 | if(areset) begin 11 | q <= 0; 12 | end 13 | else begin 14 | if(load == 1) begin 15 | q <= data; 16 | end 17 | else begin 18 | if(ena == 1) begin 19 | /*q[0] = q[1]; 20 | q[1] = q[2]; 21 | q[2] = q[3]; 22 | q[3] = 0;*/ 23 | q = q >> 1; 24 | end 25 | end 26 | end 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /2_Circuits/108_Rotate100_high.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [1:0] ena, 5 | input [99:0] data, 6 | output reg [99:0] q); 7 | 8 | always @(posedge clk) begin 9 | if(load == 1) begin 10 | q = data; 11 | end 12 | else begin 13 | if(ena[0]^ena[1]) begin 14 | case (ena) 15 | /*right*/ 16 | 2'b01: begin 17 | q <= {q[0], q[99:1]}; 18 | end 19 | /*left*/ 20 | 2'b10: begin 21 | q <= {q[98:0], q[99]}; 22 | end 23 | endcase 24 | end 25 | end 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /2_Circuits/109_Shift18.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if(load == 1)begin 11 | q = data; 12 | end 13 | else begin 14 | if(ena == 1) begin 15 | case(amount) 16 | 2'b00: q <= q << 1; 17 | 2'b01: q <= q << 8; 18 | 2'b10: begin 19 | q <= q >> 1; 20 | if(q[63] == 1) begin 21 | q[63] <= 1; 22 | end 23 | end 24 | 2'b11: begin 25 | q <= q >> 8; 26 | if(q[63] == 1) begin 27 | q[63:56] <= {8{1'b1}}; 28 | end 29 | end 30 | endcase 31 | end 32 | end 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /2_Circuits/110_Lfsr5.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, // Active-high synchronous reset to 5'h1 4 | output [4:0] q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | if(reset) begin 9 | q <= 5'h1; 10 | end 11 | else begin 12 | q <= {0 ^ q[0], q[4], q[3] ^ q[0], q[2], q[1]}; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2_Circuits/111_Mt2015 lfsr.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [2:0] SW, // R 3 | input [1:0] KEY, // L and clk 4 | output [2:0] LEDR); // Q 5 | 6 | wire clk, L; 7 | wire [2:0] R; 8 | reg [2:0] Q; 9 | assign clk = KEY[0]; 10 | assign L = KEY[1]; 11 | assign R = SW; 12 | 13 | always @(posedge clk) begin 14 | Q <= {(L) ? R[2] : (Q[1] ^ Q[2]), (L) ? R[1] : Q[0], (L) ? R[0] : Q[2]}; 15 | end 16 | 17 | assign LEDR = Q; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /2_Circuits/112_Lfsr32.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, // Active-high synchronous reset to 32'h1 4 | output [31:0] q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | if(reset) begin 9 | q <= 32'h1; 10 | end 11 | else begin 12 | q <= {0 ^ q[0], q[31:23], q[22] ^ q[0], q[21:3], q[2] ^ q[0], q[1] ^ q[0]}; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2_Circuits/114_Exams:m2014 q4k.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, // synchronous reset 4 | input in, 5 | output out); 6 | 7 | reg [2:0] Q; 8 | 9 | always @(posedge clk) begin 10 | Q[0] <= (resetn) ? in : 0; 11 | Q[1] <= (resetn) ? Q[0] : 0; 12 | Q[2] <= (resetn) ? Q[1] : 0; 13 | out <= (resetn) ? Q[2] : 0; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2_Circuits/115_Exams:2014 q4b.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:0] SW, 3 | input [3:0] KEY, 4 | output [3:0] LEDR 5 | ); // 6 | 7 | MUXDFF ins0(SW[3], KEY[0], KEY[1], KEY[2], KEY[3], LEDR[3]); 8 | MUXDFF ins1(SW[2], KEY[0], KEY[1], KEY[2], LEDR[3], LEDR[2]); 9 | MUXDFF ins2(SW[1], KEY[0], KEY[1], KEY[2], LEDR[2], LEDR[1]); 10 | MUXDFF ins3(SW[0], KEY[0], KEY[1], KEY[2], LEDR[1], LEDR[0]); 11 | 12 | endmodule 13 | 14 | module MUXDFF ( 15 | input R, 16 | input clk, 17 | input E, 18 | input L, 19 | input w, 20 | output out 21 | ); 22 | wire [1:0] mid; 23 | assign mid[0] = E ? w : out; 24 | assign mid[1] = L ? R : mid[0]; 25 | 26 | always @(posedge clk) begin 27 | out <= mid[1]; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2_Circuits/116_Exams:ece241 2013 q12_high.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input enable, 4 | input S, 5 | input A, B, C, 6 | output Z ); 7 | 8 | reg [7:0] Q = 0; 9 | 10 | always @(posedge clk) begin 11 | if(enable) begin 12 | Q <= {Q[6:0], S}; 13 | end 14 | end 15 | 16 | assign Z = Q[{A, B, C}]; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /2_Circuits/117_Rule90.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [511:0] data, 5 | output [511:0] q ); 6 | 7 | always @(posedge clk) began 8 | if(load) began 9 | q <= data; 10 | end 11 | else began 12 | q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0}; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2_Circuits/118_ Rule110.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [511:0] data, 5 | output [511:0] q 6 | ); 7 | 8 | always @(posedge clk) begin 9 | if (load) begin 10 | q <= data; 11 | end 12 | else begin 13 | q <= (((q[511:0] ^ {q[510:0], 1'b0}) & q[511:1]) | ((q[511:0] | {q[510:0], 1'b0}) & (~q[511:1]))); 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2_Circuits/119_ Conwaylife.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [255:0] data, 5 | output [255:0] q ); 6 | 7 | reg [3:0] sum; 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else begin 14 | for (integer i = 0; i < 256; i++) begin 15 | if (i == 0) begin 16 | sum = q[1]+q[16]+q[17]+q[240]+q[241]+q[15]+q[31]+q[255]; 17 | end 18 | else if (i == 15) begin 19 | sum = q[14]+q[16]+q[0]+q[240]+q[254]+q[30]+q[31]+q[255]; 20 | end 21 | else if (i == 240) begin 22 | sum = q[0]+q[15]+q[239]+q[241]+q[1]+q[224]+q[225]+q[255]; 23 | end 24 | else if (i == 255) begin 25 | sum = q[0]+q[15]+q[14]+q[224]+q[238]+q[240]+q[239]+q[254]; 26 | end 27 | else if (i > 0 && i < 15) begin 28 | sum = q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i+17]+q[i+239]+q[i+240]+q[i+241]; 29 | end 30 | else if (i % 16 == 0) begin 31 | sum = q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i+17]+q[i-16]+q[i-15]+q[i+31]; 32 | end 33 | else if (i % 16 == 15) begin 34 | sum = q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i-17]+q[i-16]+q[i-15]+q[i-31]; 35 | end 36 | else if (i > 240 && i < 255) begin 37 | sum = q[i-1]+q[i+1]+q[i-17]+q[i-16]+q[i-15]+q[i-239]+q[i-240]+q[i-241]; 38 | end 39 | else begin 40 | sum = q[i-1]+q[i+1]+q[i-17]+q[i-16]+q[i-15]+q[i+15]+q[i+16]+q[i+17]; 41 | end 42 | 43 | if ((sum == 0 || sum == 1) || (sum >= 4)) begin 44 | q[i] <= 0; 45 | end 46 | else if (sum == 3) begin 47 | q[i] <= 1; 48 | end 49 | end 50 | end 51 | end 52 | 53 | endmodule -------------------------------------------------------------------------------- /2_Circuits/120_ Fsm1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Asynchronous reset to state B 4 | input in, 5 | output out);// 6 | 7 | parameter A = 0, B = 1; 8 | reg state, next_state; 9 | 10 | always @(*) begin // This is a combinational always block 11 | // State transition logic 12 | case (state) 13 | A: next_state <= in ? A : B; 14 | B: next_state <= in ? B : A; 15 | endcase 16 | end 17 | 18 | always @(posedge clk, posedge areset) begin // This is a sequential always block 19 | // State flip-flops with asynchronous reset 20 | if (areset) begin 21 | state <= B; 22 | end 23 | else begin 24 | state <= next_state; 25 | end 26 | end 27 | 28 | // Output logic 29 | // assign out = (state == ...); 30 | assign out = (state == B); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /2_Circuits/121_ Fsm1s.v: -------------------------------------------------------------------------------- 1 | // Note the Verilog-1995 module declaration syntax here: 2 | module top_module(clk, reset, in, out); 3 | input clk; 4 | input reset; // Synchronous reset to state B 5 | input in; 6 | output out;// 7 | reg out; 8 | 9 | // Fill in state name declarations 10 | parameter A = 0, B = 1; 11 | 12 | reg present_state, next_state; 13 | 14 | always @(posedge clk) begin 15 | if (reset) begin 16 | // Fill in reset logic 17 | present_state <= B; 18 | end else begin 19 | present_state <= next_state; 20 | end 21 | end 22 | 23 | always @(*) begin 24 | case (present_state) 25 | A: next_state <= in ? A : B; 26 | B: next_state <= in ? B : A; 27 | endcase 28 | end 29 | 30 | assign out = (present_state == B); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /2_Circuits/122_ Fsm2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Asynchronous reset to OFF 4 | input j, 5 | input k, 6 | output out); // 7 | 8 | parameter OFF = 0, ON = 1; 9 | reg state, next_state; 10 | 11 | always @(*) begin 12 | // State transition logic 13 | case (state) 14 | ON: next_state <= k ? OFF : ON; 15 | OFF: next_state <= j ? ON : OFF; 16 | endcase 17 | end 18 | 19 | always @(posedge clk, posedge areset) begin 20 | // State flip-flops with asynchronous reset 21 | if (areset) begin 22 | state <= OFF; 23 | end 24 | else begin 25 | state <= next_state; 26 | end 27 | end 28 | 29 | // Output logic 30 | // assign out = (state == ...); 31 | assign out = (state == ON); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /2_Circuits/123_ Fsm2s.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, // Synchronous reset to OFF 4 | input j, 5 | input k, 6 | output out); // 7 | 8 | parameter OFF = 0, ON = 1; 9 | reg state, next_state; 10 | 11 | always @(*) begin 12 | // State transition logic 13 | case (state) 14 | ON: next_state <= k ? OFF : ON; 15 | OFF: next_state <= j ? ON : OFF; 16 | endcase 17 | end 18 | 19 | always @(posedge clk) begin 20 | // State flip-flops with synchronous reset 21 | if (reset) begin 22 | state <= OFF; 23 | end 24 | else begin 25 | state <= next_state; 26 | end 27 | end 28 | 29 | // Output logic 30 | // assign out = (state == ...); 31 | assign out = (state == ON); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /2_Circuits/124_ Fsm3comb.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | input [1:0] state, 4 | output [1:0] next_state, 5 | output out); // 6 | 7 | parameter A=0, B=1, C=2, D=3; 8 | 9 | // State transition logic: next_state = f(state, in) 10 | always @(*) begin 11 | case (state) 12 | A: next_state <= in ? B : A; 13 | B: next_state <= in ? B : C; 14 | C: next_state <= in ? D : A; 15 | D: next_state <= in ? B : C; 16 | endcase 17 | end 18 | 19 | // Output logic: out = f(state) for a Moore state machine 20 | assign out = (state == D); 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /2_Circuits/125_ Fsm3onehot.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | input [3:0] state, 4 | output [3:0] next_state, 5 | output out); // 6 | 7 | parameter A=0, B=1, C=2, D=3; 8 | 9 | // State transition logic: Derive an equation for each state flip-flop. 10 | assign next_state[A] = state[A] & (~in) | state[C] & (~in); 11 | assign next_state[B] = state[A] & in | state[B] & in | state[D] & in; 12 | assign next_state[C] = state[B] & (~in) | state[D] & (~in); 13 | assign next_state[D] = state[C] & (in); 14 | 15 | // Output logic: 16 | assign out = (state[D] == 1); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /2_Circuits/126_ Fsm3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input areset, 5 | output out); // 6 | 7 | reg [2:0] state, next_state; 8 | parameter A=1, B=2, C=3, D=4; 9 | // State transition logic 10 | always @(*) begin 11 | case (state) 12 | A: next_state <= in ? B : A; 13 | B: next_state <= in ? B : C; 14 | C: next_state <= in ? D : A; 15 | D: next_state <= in ? B : C; 16 | endcase 17 | end 18 | 19 | // State flip-flops with asynchronous reset 20 | always @(posedge clk or posedge areset) begin 21 | if(areset) begin 22 | state <= A; 23 | end else begin 24 | state <= next_state; 25 | end 26 | end 27 | 28 | // Output logic 29 | assign out = (state == D); 30 | endmodule -------------------------------------------------------------------------------- /2_Circuits/127_ Fsm3s.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, 5 | output out); // 6 | 7 | reg [2:0] state, next_state; 8 | parameter A=0, B=1, C=2, D=3; 9 | // State transition logic 10 | always @(*) begin 11 | case (state) 12 | A: next_state <= in ? B : A; 13 | B: next_state <= in ? B : C; 14 | C: next_state <= in ? D : A; 15 | D: next_state <= in ? B : C; 16 | endcase 17 | end 18 | 19 | // State flip-flops with synchronous reset 20 | always @(posedge clk) begin 21 | if(reset) begin 22 | state <= A; 23 | end else begin 24 | state <= next_state; 25 | end 26 | end 27 | 28 | // Output logic 29 | assign out = (state == D); 30 | endmodule -------------------------------------------------------------------------------- /2_Circuits/128_ece241 2013 q4.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input [3:1] s, 5 | output fr3, 6 | output fr2, 7 | output fr1, 8 | output dfr 9 | ); 10 | 11 | parameter A2 = 0, B1 = 1, B2 = 2, C1 = 3, C2 = 4, D1 = 5; 12 | reg [2:0] state, next; 13 | 14 | always @(posedge clk) begin 15 | if (reset) begin 16 | state <= A2; 17 | end 18 | else begin 19 | state <= next; 20 | end 21 | end 22 | 23 | always @(*) begin 24 | case (state) 25 | A2: next = s[1] ? B1 : A2; 26 | B1: next = s[2] ? C1 : (s[1] ? B1 : A2); 27 | B2: next = s[2] ? C1 : (s[1] ? B2 : A2); 28 | C1: next = s[3] ? D1 : (s[2] ? C1 : B2); 29 | C2: next = s[3] ? D1 : (s[2] ? C2 : B2); 30 | D1: next = s[3] ? D1 : C2; 31 | default: next = 3'bxxx; 32 | endcase 33 | end 34 | 35 | always @(*) begin 36 | case (state) 37 | A2: {fr3, fr2, fr1, dfr} = 4'b1111; 38 | B1: {fr3, fr2, fr1, dfr} = 4'b0110; 39 | B2: {fr3, fr2, fr1, dfr} = 4'b0111; 40 | C1: {fr3, fr2, fr1, dfr} = 4'b0010; 41 | C2: {fr3, fr2, fr1, dfr} = 4'b0011; 42 | D1: {fr3, fr2, fr1, dfr} = 4'b0000; 43 | default: {fr3, fr2, fr1, dfr} = 4'bxxxx; 44 | endcase 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /2_Circuits/129_Lemmings1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | output walk_left, 7 | output walk_right); // 8 | 9 | // parameter LEFT=0, RIGHT=1, ... 10 | parameter LEFT = 0, RIGHT = 1; 11 | reg state, next_state; 12 | 13 | always @(*) begin 14 | // State transition logic 15 | case (state) 16 | LEFT: next_state <= bump_left ? RIGHT : LEFT; 17 | RIGHT: next_state <= bump_right ? LEFT : RIGHT; 18 | endcase 19 | end 20 | 21 | always @(posedge clk, posedge areset) begin 22 | // State flip-flops with asynchronous reset 23 | if (areset) begin 24 | state <= LEFT; 25 | end 26 | else begin 27 | state <= next_state; 28 | end 29 | end 30 | 31 | // Output logic 32 | // assign walk_left = (state == ...); 33 | // assign walk_right = (state == ...); 34 | assign walk_left = (state == LEFT); 35 | assign walk_right = (state == RIGHT); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /2_Circuits/130_Lemmings2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | input ground, 7 | output walk_left, 8 | output walk_right, 9 | output aaah ); 10 | 11 | parameter LEFT = 0, RIGHT = 1, LEFT_aah = 2, RIGHT_aah = 3; 12 | reg [2:0] state, next_state; 13 | 14 | always @(posedge clk or posedge areset) begin 15 | if (areset) begin 16 | state <= LEFT; 17 | end 18 | else begin 19 | state <= next_state; 20 | end 21 | end 22 | 23 | always @(*) begin 24 | case (state) 25 | LEFT: begin 26 | if (ground) begin 27 | next_state <= bump_left ? RIGHT : LEFT; 28 | end 29 | else begin 30 | next_state <= LEFT_aah; 31 | end 32 | end 33 | RIGHT: begin 34 | if (ground) begin 35 | next_state <= bump_right ? LEFT : RIGHT; 36 | end 37 | else begin 38 | next_state <= RIGHT_aah; 39 | end 40 | end 41 | LEFT_aah: begin 42 | if (ground) begin 43 | next_state <= LEFT; 44 | end 45 | else begin 46 | next_state <= LEFT_aah; 47 | end 48 | end 49 | RIGHT_aah: begin 50 | if (ground) begin 51 | next_state <= RIGHT; 52 | end 53 | else begin 54 | next_state <= RIGHT_aah; 55 | end 56 | end 57 | endcase 58 | end 59 | 60 | assign walk_left = (state == LEFT); 61 | assign walk_right = (state == RIGHT); 62 | assign aaah = ((state == LEFT_aah) || (state == RIGHT_aah)); 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /2_Circuits/131_Lemmings3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | input ground, 7 | input dig, 8 | output walk_left, 9 | output walk_right, 10 | output aaah, 11 | output digging ); 12 | 13 | parameter left = 0, right = 1; 14 | parameter left_ground = 2, right_ground = 3; 15 | parameter left_dig = 4, right_dig = 5; 16 | 17 | reg [2:0] state, next_state; 18 | 19 | always @(posedge clk or posedge areset) begin 20 | if (areset) begin 21 | state <= left; 22 | end 23 | else begin 24 | state <= next_state; 25 | end 26 | end 27 | 28 | always @(*) begin 29 | case (state) 30 | left: begin 31 | if (ground) begin 32 | if (dig) begin 33 | next_state <= left_dig; 34 | end 35 | else begin 36 | next_state <= bump_left ? right : left; 37 | end 38 | end 39 | else begin 40 | next_state <= left_ground; 41 | end 42 | end 43 | right: begin 44 | if (ground) begin 45 | if (dig) begin 46 | next_state <= right_dig; 47 | end 48 | else begin 49 | next_state <= bump_right ? left : right; 50 | end 51 | end 52 | else begin 53 | next_state <= right_ground; 54 | end 55 | end 56 | left_dig: begin 57 | if (ground) begin 58 | next_state <= left_dig; 59 | end 60 | else begin 61 | next_state <= left_ground; 62 | end 63 | end 64 | right_dig: begin 65 | if (ground) begin 66 | next_state <= right_dig; 67 | end 68 | else begin 69 | next_state <= right_ground; 70 | end 71 | end 72 | left_ground: begin 73 | if (ground) begin 74 | next_state <= left; 75 | end 76 | else begin 77 | next_state <= left_ground; 78 | end 79 | end 80 | right_ground: begin 81 | if (ground) begin 82 | next_state <= right; 83 | end 84 | else begin 85 | next_state <= right_ground; 86 | end 87 | end 88 | endcase 89 | end 90 | 91 | assign walk_left = (state == left); 92 | assign walk_right = (state == right); 93 | assign aaah = ((state == left_ground) || (state == right_ground)); 94 | assign digging = ((state == left_dig) || (state == right_dig)); 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /2_Circuits/132_Lemmings4.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | input ground, 7 | input dig, 8 | output walk_left, 9 | output walk_right, 10 | output aaah, 11 | output digging ); 12 | 13 | parameter left=3'd0, right=3'd1, falll=3'd2, fallr=3'd3, digl=3'd4, digr=3'd5, splat=3'd6; 14 | reg [2:0] state, next_state; 15 | reg [31:0] count; 16 | 17 | always@(posedge clk or posedge areset) begin 18 | if(areset) 19 | state <= left; 20 | else if(state == falll || state == fallr) begin 21 | state <= next_state; 22 | count <= count + 1; 23 | end 24 | else begin 25 | state <= next_state; 26 | count <= 0; 27 | end 28 | end 29 | 30 | always@(*) begin 31 | case(state) 32 | left: begin 33 | if(~ground) next_state = falll; 34 | else if(dig) next_state = digl; 35 | else if(bump_left) next_state = right; 36 | else next_state = left; 37 | end 38 | right: begin 39 | if(~ground) next_state = fallr; 40 | else if(dig) next_state = digr; 41 | else if(bump_right) next_state = left; 42 | else next_state = right; 43 | end 44 | falll: begin 45 | if(ground) begin 46 | if(count>19) next_state = splat; 47 | else next_state = left; 48 | end 49 | else next_state = falll; 50 | end 51 | fallr: begin 52 | if(ground) begin 53 | if(count>19) next_state = splat; 54 | else next_state = right; 55 | end 56 | else next_state = fallr; 57 | end 58 | digl: begin 59 | if(ground) next_state = digl; 60 | else next_state = falll; 61 | end 62 | digr: begin 63 | if(ground) next_state = digr; 64 | else next_state = fallr; 65 | end 66 | splat: begin 67 | next_state = splat; 68 | end 69 | endcase 70 | end 71 | 72 | assign walk_left = (state == left); 73 | assign walk_right = (state == right); 74 | assign aaah = (state == falll || state == fallr); 75 | assign digging = (state == digl || state == digr); 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /2_Circuits/133_Fsm onehot.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | input [9:0] state, 4 | output [9:0] next_state, 5 | output out1, 6 | output out2); 7 | 8 | assign next_state[0] = ~in & (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]); 9 | assign next_state[1] = in & (state[0] | state[8] | state[9]); 10 | assign next_state[2] = in & state[1]; 11 | assign next_state[3] = in & state[2]; 12 | assign next_state[4] = in & state[3]; 13 | assign next_state[5] = in & state[4]; 14 | assign next_state[6] = in & state[5]; 15 | assign next_state[7] = in & (state[6] | state[7]); 16 | assign next_state[8] = ~in & state[5]; 17 | assign next_state[9] = ~in & state[6]; 18 | 19 | assign out1 = state[8] | state[9]; 20 | assign out2 = state[7] | state[9]; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /2_Circuits/134_Fsm ps2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input [7:0] in, 4 | input reset, // Synchronous reset 5 | output done); // 6 | 7 | parameter byte1 = 1, byte2 = 2, byte3 = 3, dn = 4; 8 | reg [3:0] state, next_state; 9 | 10 | // State transition logic (combinational) 11 | always @(*) begin 12 | case ({state, in[3]}) 13 | {byte1, 1'b0}: next_state = byte1; 14 | {byte1, 1'b1}: next_state = byte2; 15 | {byte2, 1'b0}: next_state = byte3; 16 | {byte2, 1'b1}: next_state = byte3; 17 | {byte3, 1'b0}: next_state = dn; 18 | {byte3, 1'b1}: next_state = dn; 19 | {dn, 1'b0}: next_state = byte1; 20 | {dn, 1'b1}: next_state = byte2; 21 | endcase 22 | end 23 | 24 | // State flip-flops (sequential) 25 | always @(posedge clk) begin 26 | if (reset) begin 27 | state <= byte1; 28 | end 29 | else begin 30 | state <= next_state; 31 | end 32 | end 33 | 34 | // Output logic 35 | assign done = (state == dn); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /2_Circuits/135_Fsm ps2data.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input [7:0] in, 4 | input reset, // Synchronous reset 5 | output [23:0] out_bytes, 6 | output done); // 7 | 8 | // FSM from fsm_ps2 9 | parameter b1 = 1, b2 = 2, b3 = 3, dn = 4; 10 | reg [2:0] state, next_state; 11 | reg [23:0] data; 12 | 13 | always @(*) begin 14 | case ({state, in[3]}) 15 | {b1, 1'b0}: next_state = b1; 16 | {b1, 1'b1}: next_state = b2; 17 | {b2, 1'b0}: next_state = b3; 18 | {b2, 1'b1}: next_state = b3; 19 | {b3, 1'b0}: next_state = dn; 20 | {b3, 1'b1}: next_state = dn; 21 | {dn, 1'b0}: next_state = b1; 22 | {dn, 1'b1}: next_state = b2; 23 | endcase 24 | end 25 | 26 | always @(posedge clk) begin 27 | if (reset) begin 28 | state <= b1; 29 | end 30 | else begin 31 | state <= next_state; 32 | end 33 | end 34 | 35 | assign done = (state == dn); 36 | 37 | // New: Datapath to store incoming bytes. 38 | always @(posedge clk) begin 39 | if (reset) begin 40 | data <= 24'd0; 41 | end 42 | else begin 43 | data[23:16] <= data[15:8]; 44 | data[15:8] <= data[7:0]; 45 | data[7:0] <= in; 46 | end 47 | end 48 | 49 | assign out_bytes = (done) ? data : 24'd0; 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /2_Circuits/136_Fsm serial.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, // Synchronous reset 5 | output done 6 | ); 7 | 8 | reg [3:0] i; 9 | parameter rc = 0, dn = 1, rd = 2, err = 3; 10 | reg [2:0] state, next_state; 11 | 12 | always @(*) begin 13 | case (state) 14 | rd: next_state <= in ? rd : rc; 15 | rc: begin 16 | if ((i == 8) & in) begin 17 | next_state <= dn; 18 | end 19 | else if ((i == 8) & (~in)) begin 20 | next_state <= err; 21 | end 22 | else begin 23 | next_state <= rc; 24 | end 25 | end 26 | dn: next_state <= in ? rd : rc; 27 | err: next_state <= in ? rd : err; 28 | endcase 29 | end 30 | 31 | always @(posedge clk) begin 32 | if (reset) begin 33 | state <= rd; 34 | i <= 0; 35 | end 36 | else begin 37 | if ((state == rc) && (i != 8)) begin 38 | i <= i + 1; 39 | end 40 | else if (state == err) begin 41 | i <= 0; 42 | end 43 | else if (state == dn) begin 44 | i <= 0; 45 | end 46 | state <= next_state; 47 | end 48 | end 49 | 50 | assign done = (state == dn); 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /2_Circuits/137_Fsm serialdata.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, // Synchronous reset 5 | output [7:0] out_byte, 6 | output done 7 | ); // 8 | 9 | // Use FSM from Fsm_serial 10 | reg [3:0] i; 11 | parameter rc = 0, rd = 1, dn = 2, err = 3; 12 | reg [2:0] state, next_state; 13 | reg [7:0] date; 14 | 15 | always @(*) begin 16 | case (state) 17 | rd: next_state <= in ? rd : rc; 18 | rc: begin 19 | if ((i == 8) & in) begin 20 | next_state <= dn; 21 | end 22 | else if ((i == 8) & (~in)) begin 23 | next_state <= err; 24 | end 25 | else begin 26 | next_state <= rc; 27 | date[i] <= in; 28 | end 29 | end 30 | dn: begin 31 | next_state <= in ? rd : rc; 32 | out_byte <= date; 33 | end 34 | err: next_state <= in ? rd : err; 35 | endcase 36 | end 37 | 38 | always @(posedge clk) begin 39 | if (reset) begin 40 | state <= rd; 41 | i <= 0; 42 | end 43 | else begin 44 | if ((state == rc) && (i != 8)) begin 45 | i <= i + 1; 46 | end 47 | else if ((state == dn)) begin 48 | i <= 0; 49 | end 50 | else if (state == err) begin 51 | i <= 0; 52 | end 53 | state <= next_state; 54 | end 55 | end 56 | 57 | // New: Datapath to latch input bits. 58 | assign done = (state == dn); 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /2_Circuits/138_Fsm serialdp.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, // Synchronous reset 5 | output [7:0] out_byte, 6 | output done 7 | ); // 8 | 9 | // Modify FSM and datapath from Fsm_serialdata 10 | parameter idle = 4'd0, start = 4'd1, trans0 = 4'd2,trans1 = 4'd3, trans2 = 4'd4, trans3 = 4'd5; 11 | parameter trans4 = 4'd6, trans5 = 4'd7, trans6 = 4'd8, trans7 = 4'd9, stop = 4'd10, err = 4'd11, pari = 4'd12; 12 | reg [3:0] state, next_state; 13 | reg [7:0] data; 14 | wire odd, reset_p; 15 | reg done_reg; 16 | 17 | always @(*) begin 18 | case (state) 19 | idle: next_state <= in ? idle : start; 20 | start: next_state <= trans0; 21 | trans0: next_state <= trans1; 22 | trans1: next_state <= trans2; 23 | trans2: next_state <= trans3; 24 | trans3: next_state <= trans4; 25 | trans4: next_state <= trans5; 26 | trans5: next_state <= trans6; 27 | trans6: next_state <= trans7; 28 | trans7: next_state <= pari; 29 | pari: next_state <= in ? idle : err; 30 | err: next_state <= in ? idle : err; 31 | endcase 32 | end 33 | 34 | always @(posedge clk) begin 35 | if (reset) begin 36 | state <= idle; 37 | end 38 | else begin 39 | state <= next_state; 40 | end 41 | end 42 | 43 | // New: Add parity checking. 44 | always @(posedge clk) begin 45 | if (reset) begin 46 | data <= 8'd0; 47 | reset_p <= 1'b1; 48 | done_reg <= 1'b0; 49 | end 50 | else begin 51 | if (next_state == trans0 || next_state == trans1 || next_state == trans2 || next_state == trans3 || next_state == trans4 || next_state == trans5 || next_state == trans6 || next_state == trans7) begin 52 | data <= {in, data[7:1]}; 53 | end 54 | else if (next_state == start) begin 55 | data <= 8'd0; 56 | reset_p <= 1'b0; 57 | done_reg <= 1'b0; 58 | end 59 | else if (next_state == idle) begin 60 | done_reg <= odd; 61 | end 62 | else if (next_state == pari) begin 63 | reset_p <= 1'b1; 64 | end 65 | end 66 | end 67 | 68 | assign done = done_reg; 69 | assign out_byte = done ? data : 8'd0; 70 | parity par_mod(clk, reset | reset_p, in, odd); 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /2_Circuits/139_Fsm hdlc.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input in, 5 | output disc, 6 | output flag, 7 | output err); 8 | 9 | parameter none=4'd0, one=4'd1, two=4'd2, three=4'd3, four=4'd4, five=4'd5, six=4'd6, error=4'd7, discard=4'd8, flagg=4'd9; 10 | reg [3:0] state, next_state; 11 | 12 | always@(*) begin 13 | case({state, in}) 14 | {none, 1'b0}: next_state = none; 15 | {none, 1'b1}: next_state = one; 16 | {one, 1'b0}: next_state = none; 17 | {one, 1'b1}: next_state = two; 18 | {two, 1'b0}: next_state = none; 19 | {two, 1'b1}: next_state = three; 20 | {three, 1'b0}: next_state = none; 21 | {three, 1'b1}: next_state = four; 22 | {four, 1'b0}: next_state = none; 23 | {four, 1'b1}: next_state = five; 24 | {five, 1'b0}: next_state = discard; 25 | {five, 1'b1}: next_state = six; 26 | {six, 1'b0}: next_state = flagg; 27 | {six, 1'b1}: next_state = error; 28 | {error, 1'b0}: next_state = none; 29 | {error, 1'b1}: next_state = error; 30 | {discard, 1'b0}:next_state = none; 31 | {discard, 1'b1}:next_state = one; 32 | {flagg, 1'b0}: next_state = none; 33 | {flagg, 1'b1}: next_state = one; 34 | endcase 35 | end 36 | 37 | always@(posedge clk) begin 38 | if(reset) 39 | state <= none; 40 | else 41 | state <= next_state; 42 | end 43 | 44 | assign disc = (state == discard); 45 | assign flag = (state == flagg); 46 | assign err = (state == error); 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /2_Circuits/140_ece241 2013 q.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input aresetn, // Asynchronous active-low reset 4 | input x, 5 | output z ); 6 | 7 | parameter start = 0, mid = 1, ends = 2; 8 | reg [2:0] state, next_state; 9 | 10 | always @(*) begin 11 | case (state) 12 | start: next_state = x ? mid : start; 13 | mid: next_state = x ? mid : ends; 14 | ends: next_state = x ? mid : start; 15 | endcase 16 | end 17 | 18 | always @(posedge clk or negedge aresetn) begin 19 | if (!aresetn) begin 20 | state <= start; 21 | end 22 | else begin 23 | state <= next_state; 24 | end 25 | end 26 | 27 | always @(*) begin 28 | case (state) 29 | start: z = 0; 30 | mid: z = 0; 31 | ends: z = x; 32 | endcase 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /2_Circuits/141_ece241 2014 q5a.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input areset, 4 | input x, 5 | output z 6 | ); 7 | 8 | parameter S0 = 0, S1 = 1, S2 = 2; 9 | reg [1:0] state; 10 | reg [1:0] next_state; 11 | 12 | always @(*) begin 13 | case(state) 14 | S0 : begin 15 | next_state = x ? S1 : S0; 16 | z = 1'b0; 17 | end 18 | 19 | S1 : begin 20 | next_state = x ? S2 : S1; 21 | z = 1'b1; 22 | end 23 | 24 | S2 : begin 25 | next_state = x ? S2 : S1; 26 | z = 1'b0; 27 | end 28 | default : begin 29 | next_state = S0; 30 | z = 1'b0; 31 | end 32 | endcase 33 | end 34 | 35 | always @(posedge clk or posedge areset) begin 36 | if(areset) 37 | state <= S0; 38 | else 39 | state <= next_state; 40 | end 41 | 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /2_Circuits/142_ece241 2014 q5b_high.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input areset, 4 | input x, 5 | output z 6 | ); 7 | localparam S0 = 0, S1 = 1; 8 | reg [1:0] state; 9 | reg [1:0] next_state; 10 | 11 | always @(*) begin 12 | next_state = 2'b0; 13 | case(1'b1) 14 | state[S0] : begin 15 | next_state[S1] = x ? 1'b1 : 1'b0; 16 | next_state[S0] = x ? 1'b0 : 1'b1; 17 | z = x; 18 | end 19 | 20 | state[S1] : begin 21 | next_state[S1] = 1'b1; 22 | next_state[S0] = 1'b0; 23 | z = ~x; 24 | end 25 | 26 | default : begin 27 | next_state[S0] = 1'b1; 28 | next_state[S1] = 1'b0; 29 | z = 1'b0; 30 | end 31 | endcase 32 | end 33 | 34 | always @(posedge clk or posedge areset) begin 35 | if(areset) begin 36 | state <= 2'b0; 37 | state[S0] <= 1'b1; 38 | end 39 | else 40 | state <= next_state; 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /2_Circuits/143_2014 q3fsm.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input s, 5 | input w, 6 | output z 7 | ); 8 | 9 | parameter A = 0, B = 1; 10 | reg [2:0] state, next_state; 11 | reg [2:0] w_new; 12 | reg [2:0] count; 13 | 14 | always @(*) begin 15 | case ({state, s}) 16 | // there will be a wrong message, if write like {A, 0} 17 | {A, 1'b0}: next_state = A; 18 | {A, 1'b1}: next_state = B; 19 | {B, 1'b0}: next_state = B; 20 | {B, 1'b1}: next_state = B; 21 | endcase 22 | end 23 | 24 | always @(posedge clk) begin 25 | if (reset) begin 26 | state <= A; 27 | end 28 | else begin 29 | state <= next_state; 30 | end 31 | end 32 | 33 | always @(posedge clk) begin 34 | if (reset) begin 35 | w_new <= 0; 36 | end 37 | else if (next_state == B) begin 38 | w_new <= {w_new[1:0], w}; 39 | end 40 | end 41 | 42 | always @(posedge clk) begin 43 | if (reset) begin 44 | count <= 0; 45 | end 46 | else if (next_state == B) begin 47 | if (count == 3) begin 48 | count <= 1; 49 | end 50 | else begin 51 | count <= count + 1; 52 | end 53 | end 54 | end 55 | 56 | assign z = (count == 1 && (w_new == 3'b011 || w_new == 3'b110 || w_new == 3'b101)); 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /2_Circuits/144_2014 q3bfsm.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input x, 5 | output z 6 | ); 7 | 8 | parameter a = 0, b = 1, c = 2, d = 3, e = 4; 9 | reg [2:0] state, next_state; 10 | 11 | always @(*) begin 12 | case (state) 13 | a: next_state = x ? b : a; 14 | b: next_state = x ? e : b; 15 | c: next_state = x ? b : c; 16 | d: next_state = x ? c : b; 17 | e: next_state = x ? e : d; 18 | endcase 19 | end 20 | 21 | always @(posedge clk) begin 22 | if (reset) begin 23 | state <= a; 24 | end 25 | else begin 26 | state <= next_state; 27 | end 28 | end 29 | 30 | assign z = (state == d || state == e); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /2_Circuits/145_2014 q3c.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [2:0] y, 4 | input x, 5 | output Y0, 6 | output z 7 | ); 8 | 9 | reg [2:0] Y; 10 | 11 | always@(*) begin 12 | case({y, x}) 13 | 4'b0000: Y = 3'b000; 14 | 4'b0001: Y = 3'b001; 15 | 4'b0010: Y = 3'b001; 16 | 4'b0011: Y = 3'b100; 17 | 4'b0100: Y = 3'b010; 18 | 4'b0101: Y = 3'b001; 19 | 4'b0110: Y = 3'b001; 20 | 4'b0111: Y = 3'b010; 21 | 4'b1000: Y = 3'b011; 22 | 4'b1001: Y = 3'b100; 23 | endcase 24 | end 25 | 26 | assign z = (y == 3'b011 || y == 3'b100); 27 | assign Y0 = Y[0]; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /2_Circuits/146_m2014 q6b.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:1] y, 3 | input w, 4 | output Y2); 5 | 6 | reg [3:1] Y; 7 | // A000 B001 C010 D011 E100 F101 8 | always @(*) begin 9 | case({y, w}) 10 | 4'b0000: Y = 3'b001; 11 | 4'b0001: Y = 3'b000; 12 | 4'b0010: Y = 3'b010; 13 | 4'b0011: Y = 3'b011; 14 | 4'b0100: Y = 3'b100; 15 | 4'b0101: Y = 3'b011; 16 | 4'b0110: Y = 3'b101; 17 | 4'b0111: Y = 3'b000; 18 | 4'b1000: Y = 3'b100; 19 | 4'b1001: Y = 3'b011; 20 | 4'b1010: Y = 3'b010; 21 | 4'b1011: Y = 3'b011; 22 | endcase 23 | end 24 | 25 | assign Y2 = Y[2]; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /2_Circuits/147_m2014 q6c.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [6:1] y, 3 | input w, 4 | output Y2, 5 | output Y4); 6 | 7 | assign Y2 = y[1] & (~w); 8 | assign Y4 = (y[2] & w) | (y[3] & w) | (y[5] & w) | (y[6] & w); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2_Circuits/148_m2014 q6.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // synchronous reset 4 | input w, 5 | output z); 6 | 7 | parameter a=3'b000, b=3'b001, c=3'b010, d=3'b011, e=3'b100, f=3'b101; 8 | reg [2:0] state, next_state; 9 | 10 | always@(*) begin 11 | case({state, w}) 12 | {a, 1'b0}: next_state = b; 13 | {a, 1'b1}: next_state = a; 14 | {b, 1'b0}: next_state = c; 15 | {b, 1'b1}: next_state = d; 16 | {c, 1'b0}: next_state = e; 17 | {c, 1'b1}: next_state = d; 18 | {d, 1'b0}: next_state = f; 19 | {d, 1'b1}: next_state = a; 20 | {e, 1'b0}: next_state = e; 21 | {e, 1'b1}: next_state = d; 22 | {f, 1'b0}: next_state = c; 23 | {f, 1'b1}: next_state = d; 24 | endcase 25 | end 26 | 27 | always@(posedge clk) begin 28 | if(reset) 29 | state <= a; 30 | else 31 | state <= next_state; 32 | end 33 | 34 | assign z = (state == e || state == f); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /2_Circuits/149_2012 q2fsm.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // synchronous reset 4 | input w, 5 | output z); 6 | 7 | parameter a=3'b000, b=3'b001, c=3'b010, d=3'b011, e=3'b100, f=3'b101; 8 | reg [2:0] state, next_state; 9 | 10 | always@(*) begin 11 | case({state, w}) 12 | {a, 1'b0}: next_state = a; 13 | {a, 1'b1}: next_state = b; 14 | {b, 1'b0}: next_state = d; 15 | {b, 1'b1}: next_state = c; 16 | {c, 1'b0}: next_state = d; 17 | {c, 1'b1}: next_state = e; 18 | {d, 1'b0}: next_state = a; 19 | {d, 1'b1}: next_state = f; 20 | {e, 1'b0}: next_state = d; 21 | {e, 1'b1}: next_state = e; 22 | {f, 1'b0}: next_state = d; 23 | {f, 1'b1}: next_state = c; 24 | endcase 25 | end 26 | 27 | always@(posedge clk) begin 28 | if(reset) 29 | state <= a; 30 | else 31 | state <= next_state; 32 | end 33 | 34 | assign z = (state == e || state == f); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /2_Circuits/150_2012 q2b.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [5:0] y, 3 | input w, 4 | output Y1, 5 | output Y3 6 | ); 7 | 8 | assign Y1 = y[0]&w; 9 | assign Y3 = y[1]&(~w) | y[2]&(~w) | y[4]&(~w) | y[5]&(~w); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2_Circuits/151_2013 q2afsm.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, // active-low synchronous reset 4 | input [3:1] r, // request 5 | output [3:1] g // grant 6 | ); 7 | 8 | parameter a=2'd0, b=2'd1, c=2'd2, d=2'd3; 9 | reg [1:0] state, next_state; 10 | 11 | always@(*) begin 12 | case(state) 13 | a: begin 14 | if(r[1]) next_state = b; 15 | else if(~r[1] & r[2]) next_state = c; 16 | else if(~r[1] & ~r[2] & r[3]) next_state = d; 17 | else next_state = a; 18 | end 19 | b: begin 20 | if(r[1]) next_state = b; 21 | else next_state = a; 22 | end 23 | c: begin 24 | if(r[2]) next_state = c; 25 | else next_state = a; 26 | end 27 | d: begin 28 | if(r[3]) next_state = d; 29 | else next_state = a; 30 | end 31 | endcase 32 | end 33 | 34 | always@(posedge clk) begin 35 | if(~resetn) 36 | state <= a; 37 | else 38 | state <= next_state; 39 | end 40 | 41 | assign g[1] = (state == b); 42 | assign g[2] = (state == c); 43 | assign g[3] = (state == d); 44 | 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /2_Circuits/152_2013 q2bfsm.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, // active-low synchronous reset 4 | input x, 5 | input y, 6 | output reg f, 7 | output reg g 8 | ); 9 | 10 | parameter A=4'd0, f1=4'd1, tmp0=4'd2, tmp1=4'd3, tmp2=4'd4, g1=4'd5, g1p=4'd6, tmp3=4'd7, g0p=4'd8; 11 | reg [3:0] state, next_state; 12 | 13 | always@(*) begin 14 | case(state) 15 | A: begin 16 | if(resetn) 17 | next_state = f1; 18 | else 19 | next_state = A; 20 | end 21 | f1: next_state = tmp0; 22 | tmp0: begin 23 | if(x) 24 | next_state = tmp1; 25 | else 26 | next_state = tmp0; 27 | end 28 | tmp1: begin 29 | if(~x) 30 | next_state = tmp2; 31 | else 32 | next_state = tmp1; 33 | end 34 | tmp2: begin 35 | if(x) 36 | next_state = g1; 37 | else 38 | next_state = tmp0; 39 | end 40 | g1: begin 41 | if(y) 42 | next_state = g1p; 43 | else 44 | next_state = tmp3; 45 | end 46 | tmp3: begin 47 | if(y) 48 | next_state = g1p; 49 | else 50 | next_state = g0p; 51 | end 52 | g1p: begin 53 | if(~resetn) 54 | next_state = A; 55 | else 56 | next_state = g1p; 57 | end 58 | g0p: begin 59 | if(~resetn) 60 | next_state = A; 61 | else 62 | next_state = g0p; 63 | end 64 | endcase 65 | end 66 | 67 | always@(posedge clk) begin 68 | if(~resetn) 69 | state <= A; 70 | else 71 | state <= next_state; 72 | end 73 | 74 | always@(posedge clk) begin 75 | case(next_state) 76 | f1: f <= 1'b1; 77 | g1, 78 | tmp3, 79 | g1p: g <= 1'b1; 80 | g0p: g <= 1'b0; 81 | default: begin 82 | f <= 1'b0; 83 | g <= 1'b0; 84 | end 85 | endcase 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /2_Circuits/153_review2015 count1k.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output [9:0] q); 5 | 6 | always @(posedge clk) begin 7 | if (reset) begin 8 | q <= 0; 9 | end 10 | else if (q == 999) begin 11 | q <= 0; 12 | end 13 | else begin 14 | q <= q + 1; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /2_Circuits/154_review2015 fancytimer.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input data, 5 | output [3:0] count, 6 | output counting, 7 | output done, 8 | input ack ); 9 | 10 | parameter idle = 0, s1 = 1, s2 = 2, s3 = 3, b0 = 4, b1 = 5; 11 | parameter b2 = 6, b3 = 7, counts = 8, waiting = 9; 12 | reg [3:0] state, next_state; 13 | reg [9:0] counter; 14 | 15 | always @(*) begin 16 | case (state) 17 | idle: next_state = data ? s1 : idle; 18 | s1: next_state = data ? s2 : idle; 19 | s2: next_state = data ? s2 : s3; 20 | s3: next_state = data ? b0 : idle; 21 | b0: next_state = b1; 22 | b1: next_state = b2; 23 | b2: next_state = b3; 24 | b3: next_state = counts; 25 | counts: next_state = (count == 0 && counter == 999) ? waiting : counts; 26 | waiting:next_state = ack ? idle : waiting; 27 | endcase 28 | end 29 | 30 | always @(posedge clk) begin 31 | if (reset) begin 32 | count <= 0; 33 | counter <= 0; 34 | end 35 | else begin 36 | case (state) 37 | b0: count[3] <= data; 38 | b1: count[2] <= data; 39 | b2: count[1] <= data; 40 | b3: count[0] <= data; 41 | counts: begin 42 | if (count >= 0) begin 43 | if (counter < 999) begin 44 | counter <= counter + 1; 45 | end 46 | else begin 47 | count <= count - 1; 48 | counter <= 0; 49 | end 50 | end 51 | end 52 | default: counter <= 0; 53 | endcase 54 | end 55 | end 56 | 57 | always @(posedge clk) begin 58 | if (reset) begin 59 | state <= idle; 60 | end 61 | else begin 62 | state <= next_state; 63 | end 64 | end 65 | 66 | assign counting = (state == counts); 67 | assign done = (state == waiting); 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /2_Circuits/155_review2015 fsmonehot.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input d, 3 | input done_counting, 4 | input ack, 5 | input [9:0] state, // 10-bit one-hot current state 6 | output B3_next, 7 | output S_next, 8 | output S1_next, 9 | output Count_next, 10 | output Wait_next, 11 | output done, 12 | output counting, 13 | output shift_ena 14 | ); // 15 | 16 | // You may use these parameters to access state bits using e.g., state[B2] instead of state[6]. 17 | parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9; 18 | 19 | assign B3_next = state[B2]; 20 | assign S_next = (state[S] & (~d)) || (state[S1] & (~d)) || (state[S110] & (~d)) || (state[Wait] & ack); 21 | assign S1_next = state[S] & d; 22 | assign Count_next = state[B3] || (state[Count] & (~done_counting)); 23 | assign Wait_next = (state[Count] & (done_counting)) || (state[Wait] & (~ack)); 24 | assign done = state[Wait]; 25 | assign counting = state[Count]; 26 | assign shift_ena = state[B0] || state[B1] || state[B2] || state[B3]; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /2_Circuits/156_review2015 shiftcount.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input shift_ena, 4 | input count_ena, 5 | input data, 6 | output [3:0] q); 7 | 8 | always @(posedge clk) begin 9 | if (shift_ena) begin 10 | q <= {q[2:0], data}; // an useful skill 11 | end 12 | else if (count_ena) begin 13 | q <= q - 1; 14 | end 15 | else begin 16 | q <= q; 17 | end 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2_Circuits/157_review2015 fsmseq.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input data, 5 | output start_shifting); 6 | 7 | parameter a = 0, b = 1, c = 2, d = 3, e = 4; 8 | reg [2:0] state, next_state; 9 | 10 | always @(*) begin 11 | case (state) 12 | a: next_state = data ? b : a; 13 | b: next_state = data ? c : a; 14 | c: next_state = data ? c : d; 15 | d: next_state = data ? e : a; 16 | e: next_state = data ? e : e; 17 | endcase 18 | end 19 | always @(posedge clk) begin 20 | if (reset) begin 21 | state <= a; 22 | end 23 | else begin 24 | state <= next_state; 25 | end 26 | end 27 | 28 | assign start_shifting = (state == e); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2_Circuits/158_review2015 fsmshift_high.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | output shift_ena); 5 | 6 | parameter c0=3'd0, c1=3'd1, c2=3'd2, c3=3'd3, c4=3'd4; 7 | reg [2:0] state, next_state; 8 | 9 | always@(*) begin 10 | case(state) 11 | c0: next_state = reset ? c1 : c0; 12 | c1: next_state = c2; 13 | c2: next_state = c3; 14 | c3: next_state = c4; 15 | c4: next_state = c0; 16 | endcase 17 | end 18 | 19 | always@(posedge clk) begin 20 | state <= next_state; 21 | end 22 | 23 | assign shift_ena = (state==c1 || state==c2 || state==c3 || state==c4); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /2_Circuits/159_review2015 fsm.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input data, 5 | output shift_ena, 6 | output counting, 7 | input done_counting, 8 | output done, 9 | input ack ); 10 | 11 | parameter idle=4'd0, s1=4'd1, s11=4'd2, s110=4'd3, b0=4'd4, b1=4'd5, b2=4'd6, b3=4'd7, count=4'd8, waiting=4'd9; 12 | reg [3:0] state, next_state; 13 | 14 | always@(*) begin 15 | case(state) 16 | idle: begin 17 | if(data==1'b0) 18 | next_state = idle; 19 | else 20 | next_state = s1; 21 | end 22 | s1: begin 23 | if(data==1'b0) 24 | next_state = idle; 25 | else 26 | next_state = s11; 27 | end 28 | s11: begin 29 | if(data==1'b0) 30 | next_state = s110; 31 | else 32 | next_state = s11; 33 | end 34 | s110: begin 35 | if(data==1'b0) 36 | next_state = idle; 37 | else 38 | next_state = b0; 39 | end 40 | b0: next_state = b1; 41 | b1: next_state = b2; 42 | b2: next_state = b3; 43 | b3: next_state = count; 44 | count: begin 45 | if(done_counting) 46 | next_state = waiting; 47 | else 48 | next_state = count; 49 | end 50 | waiting: begin 51 | if(ack) 52 | next_state = idle; 53 | else 54 | next_state = waiting; 55 | end 56 | endcase 57 | end 58 | 59 | always@(posedge clk) begin 60 | if(reset) 61 | state <= idle; 62 | else 63 | state <= next_state; 64 | end 65 | 66 | assign shift_ena = (state==b0 || state==b1|| state==b2 || state==b3); 67 | assign counting = (state==count); 68 | assign done = (state==waiting); 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/161_Bugs mux2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input sel, 3 | input [7:0] a, 4 | input [7:0] b, 5 | output [7:0] out ); 6 | 7 | assign out = sel ? a : b; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/162_Bugs nand3.v: -------------------------------------------------------------------------------- 1 | module top_module (input a, input b, input c, output out);// 2 | 3 | wire out_tmp; 4 | assign out = ~out_tmp; 5 | andgate inst1 ( out_tmp, a, b, c, 1, 1 ); 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/163_Bugs mux4.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [1:0] sel, 3 | input [7:0] a, 4 | input [7:0] b, 5 | input [7:0] c, 6 | input [7:0] d, 7 | output [7:0] out ); // 8 | 9 | wire [7:0] mux0, mux1; 10 | mux2 mux0_ins ( sel[0], a, b, mux0 ); 11 | mux2 mux1_ins ( sel[0], c, d, mux1 ); 12 | mux2 mux2_ins ( sel[1], mux0, mux1, out ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/164_Bugs addsubz.v: -------------------------------------------------------------------------------- 1 | // synthesis verilog_input_version verilog_2001 2 | module top_module ( 3 | input do_sub, 4 | input [7:0] a, 5 | input [7:0] b, 6 | output reg [7:0] out, 7 | output reg result_is_zero 8 | );// 9 | 10 | always @(*) begin 11 | case (do_sub) 12 | 0: out = a+b; 13 | 1: out = a-b; 14 | endcase 15 | 16 | if (out == 0) 17 | result_is_zero = 1; 18 | else 19 | result_is_zero = 0; 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/165_Bugs case.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] code, 3 | output reg [3:0] out, 4 | output reg valid = 1 5 | );// 6 | 7 | always @(*) 8 | case (code) 9 | 8'h45: begin 10 | out = 0; 11 | valid = 1; 12 | end 13 | 8'h16: begin 14 | out = 1; 15 | valid = 1; 16 | end 17 | 8'h1e: begin 18 | out = 2; 19 | valid = 1; 20 | end 21 | 8'h26: begin 22 | out = 3; 23 | valid = 1; 24 | end 25 | 8'h25: begin 26 | out = 4; 27 | valid = 1; 28 | end 29 | 8'h2e: begin 30 | out = 5; 31 | valid = 1; 32 | end 33 | 8'h36: begin 34 | out = 6; 35 | valid = 1; 36 | end 37 | 8'h3d: begin 38 | out = 7; 39 | valid = 1; 40 | end 41 | 8'h3e: begin 42 | out = 8; 43 | valid = 1; 44 | end 45 | 8'h46: begin 46 | out = 9; 47 | valid = 1; 48 | end 49 | default: begin 50 | out = 0; 51 | valid = 0; 52 | end 53 | endcase 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/166_Sim:circuit1.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | output q );// 5 | 6 | assign q = a && b; // Fix me 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/167_Sim:circuit2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output q );// 7 | 8 | reg [2:0] sum; 9 | assign sum = a + b + c + d; 10 | assign q = (sum == 1 || sum == 3) ? 0 : 1; // Fix me 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/168_Sim:circuit3.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output q );// 7 | 8 | assign q = (a || b) && (c || d); // Fix me 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/169_Sim:circuit4.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output q );// 7 | 8 | assign q = (b || c); // Fix me 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/170_Sim:circuit5.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:0] a, 3 | input [3:0] b, 4 | input [3:0] c, 5 | input [3:0] d, 6 | input [3:0] e, 7 | output [3:0] q ); 8 | 9 | always @ (*) begin 10 | case(c) 11 | 0: q = b; 12 | 1: q = e; 13 | 2: q = a; 14 | 3: q = d; 15 | default: q = 15; 16 | endcase 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/171_Sim:circuit6.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [2:0] a, 3 | output [15:0] q ); 4 | 5 | always @ (*) begin 6 | case(a) 7 | 0: q = 16'h1232; 8 | 1: q = 16'haee0; 9 | 2: q = 16'h27d4; 10 | 3: q = 16'h5a0e; 11 | 4: q = 16'h2066; 12 | 5: q = 16'h64ce; 13 | 6: q = 16'hc526; 14 | 7: q = 16'h2f19; 15 | endcase 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/172_Sim:circuit7.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input a, 4 | output q ); 5 | 6 | always @ (posedge clk) begin 7 | q <= ~a; 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/173_Sim:circuit8.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clock, 3 | input a, 4 | output p, 5 | output q ); 6 | 7 | always @ (*) begin 8 | if(clock == 1) begin 9 | p = a; 10 | end 11 | else begin 12 | q = p; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/174_Sim:circuit9.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input a, 4 | output [3:0] q 5 | ); 6 | 7 | always @ (posedge clk) begin 8 | if(a == 1) begin 9 | q = 4; 10 | end 11 | else begin 12 | q = (q < 6) ? (q + 1) : 0; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /3_Verification Reading simulations/175_Sim:circui10_high.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input a, 4 | input b, 5 | output q, 6 | output state 7 | ); 8 | 9 | always @ (posedge clk) begin 10 | if(a == b) 11 | state <= a; 12 | else 13 | state <= state; 14 | end 15 | 16 | assign q = (a == b) ? state : (~state); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /4_Verification Writing Testbenches/176_Tb:clock.v: -------------------------------------------------------------------------------- 1 | module top_module ( ); 2 | parameter time_period = 10; 3 | reg clock; 4 | initial begin 5 | clock = 0; 6 | end 7 | always begin 8 | #(time_period / 2) clock = ~clock; 9 | end 10 | dut dut1(clock); 11 | endmodule 12 | -------------------------------------------------------------------------------- /4_Verification Writing Testbenches/177_Tb:tb1.v: -------------------------------------------------------------------------------- 1 | module top_module ( output reg A, output reg B );// 2 | 3 | // generate input patterns here 4 | initial begin 5 | A = 0; 6 | B = 0; 7 | #10 A = 1; 8 | #5 B = 1; 9 | #5 A = 0; 10 | #20 B = 0; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /4_Verification Writing Testbenches/178_Tb:and.v: -------------------------------------------------------------------------------- 1 | module top_module(); 2 | reg [1:0] in; 3 | reg out; 4 | initial begin 5 | in = 2'b0; 6 | #10 in = 2'b01; 7 | #10 in = 2'b10; 8 | #10 in = 2'b11; 9 | end 10 | andgate gate1(in, out); 11 | endmodule 12 | -------------------------------------------------------------------------------- /4_Verification Writing Testbenches/179_Tb:tb2.v: -------------------------------------------------------------------------------- 1 | module top_module(); 2 | reg clk, in; 3 | reg [2:0] s; 4 | reg out; 5 | initial begin 6 | clk = 0; 7 | s = 2; 8 | in = 0; 9 | #10 s = 6; 10 | #10 begin 11 | s = 2; 12 | in = 1; 13 | end 14 | #10 begin 15 | s = 7; 16 | in = 0; 17 | end 18 | #10 begin 19 | s = 0; 20 | in = 1; 21 | end 22 | #30 in = 0; 23 | end 24 | always begin 25 | #5 clk = ~clk; 26 | end 27 | 28 | q7 q7_test(clk, in, s, out); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /4_Verification Writing Testbenches/180_Tb:tff.v: -------------------------------------------------------------------------------- 1 | module top_module (); 2 | reg clk, reset, t; 3 | reg q; 4 | initial begin 5 | clk = 0; 6 | reset = 0; 7 | t = 0; 8 | #15 reset = 1; 9 | #10 reset = 0; 10 | #10 t = 1; 11 | end 12 | always begin 13 | #5 clk = ~clk; 14 | end 15 | tff tff1(clk, reset, t, q); 16 | endmodule 17 | -------------------------------------------------------------------------------- /5_CS450/181_CS450_timer.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [9:0] data, 5 | output tc 6 | ); 7 | reg [9:0] counter; 8 | 9 | always@(posedge clk) begin 10 | if (load==1'b1) counter <= data; 11 | else counter <= (counter==10'b0)?counter:counter-1; 12 | end 13 | 14 | assign tc = (counter == 10'b0)?1'b1:1'b0; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /5_CS450/182_CS450_counter_2bc.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | input train_valid, 5 | input train_taken, 6 | output reg [1:0] state 7 | ); 8 | localparam SNT = 0, WNT = 1, WT = 2, ST = 3; 9 | wire [1:0] next_state; 10 | 11 | always@(*)begin 12 | if (train_valid) begin 13 | case(state) 14 | SNT: next_state = train_taken?WNT:SNT; 15 | WNT: next_state = train_taken?WT:SNT; 16 | WT: next_state = train_taken?ST:WNT; 17 | ST: next_state = train_taken?ST:WT; 18 | endcase 19 | end else begin 20 | case(state) 21 | SNT: next_state = SNT; 22 | WNT: next_state = WNT; 23 | WT: next_state = WT; 24 | ST: next_state = ST; 25 | endcase 26 | end 27 | end 28 | 29 | always@(posedge clk or posedge areset) begin 30 | if (areset) state <= WNT; 31 | else state <= next_state; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /5_CS450/183_CS450_history_shift.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | 5 | input predict_valid, 6 | input predict_taken, 7 | output reg [31:0] predict_history, 8 | 9 | input train_mispredicted, 10 | input train_taken, 11 | input [31:0] train_history 12 | ); 13 | always@(posedge clk or posedge areset) begin 14 | if (areset) predict_history <= 32'b0; 15 | else begin 16 | if (train_mispredicted) predict_history <= {train_history[30:0],train_taken}; 17 | else if (predict_valid) predict_history <= {predict_history[30:0],predict_taken}; 18 | end 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /5_CS450/184_CS450_gshare.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | 5 | input predict_valid, 6 | input [6:0] predict_pc, 7 | output predict_taken, 8 | output [6:0] predict_history, 9 | 10 | input train_valid, 11 | input train_taken, 12 | input train_mispredicted, 13 | input [6:0] train_history, 14 | input [6:0] train_pc 15 | ); 16 | reg [1:0] PHT[127:0]; 17 | 18 | always @(posedge clk, posedge areset) begin 19 | if (areset) begin 20 | predict_history <= 0; 21 | for (integer i=0; i<128; i=i+1) begin 22 | PHT[i] <= 2'b01; //initialize to WNT, checkout couter2bc example 23 | end 24 | end 25 | else begin 26 | if (train_valid) begin 27 | if (train_taken) PHT[train_history ^ train_pc] <= (PHT[train_history ^ train_pc] == 2'b11) ? 2'b11 : (PHT[train_history ^ train_pc] + 1); 28 | else PHT[train_history ^ train_pc] <= (PHT[train_history ^ train_pc] == 2'b00) ? 2'b00 : (PHT[train_history ^ train_pc] - 1); 29 | end 30 | if (train_valid && train_mispredicted) predict_history <= {train_history[6:0], train_taken}; 31 | else if (predict_valid) predict_history <= {predict_history[6:0], predict_taken}; 32 | end 33 | end 34 | assign predict_taken = PHT[predict_history ^ predict_pc][1];//"Not taken" is 0x while "taken" is 1x 35 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Verilog-Practice 2 | 3 | [![HitCount](https://hits.dwyl.com/xiaop1/Verilog-Practice.svg?style=flat-square)](http://hits.dwyl.com/xiaop1/Verilog-Practice) GitHub stars 4 | 5 | 6 | 7 | There are some [HDLBits website][1] practices. And all of them have been verified. I really hope that my practices can help you to realize how Verilog works. 8 | 9 | 2020.4.22 - 6:09:54: All of the problems are **done**. 10 | 11 | And there is my [blog][2]. 12 | 13 | At the end, life is fantastic bro. 14 | 15 | [1]: https://hdlbits.01xz.net/wiki/Main_Page 16 | [2]: https://blog.began.me 17 | 18 | ## Star History 19 | 20 | [![Star History Chart](https://api.star-history.com/svg?repos=xiaop1/Verilog-Practice&type=Date)](https://star-history.com/#xiaop1/Verilog-Practice&Date) 21 | --------------------------------------------------------------------------------