├── README.md ├── doc ├── AG10K │ ├── AG10K_FBGA256_LQFP144_Pinout_Release.xls │ ├── AG10K_guide.pdf │ ├── AGM_FPGA_AG6K_AG10K_Rev1.1.PDF │ └── Manual_remote.pdf ├── AG1280 │ ├── AG1280Q48_PINOUT.xls │ ├── AG1280Q48_V1.0.PDF │ └── MANUAL_AG1280.pdf ├── AGCPLD │ ├── AG_CPLD2K_Rev1_0 .pdf │ ├── AG_CPLD_Rev1_1.pdf │ ├── AG_CPLD_guide-2020.pdf │ └── AG_CPLD_guide.pdf ├── AgmPillFAQ.md └── MANUAL_Supra_6.2.pdf ├── fw ├── MegaPill │ ├── README.md │ ├── download.sh │ ├── mc8051_AG10KL144H_v22.11.02.7z │ └── mc8051_AG10KL144_v22.11.02.7z └── TB_AG1280 │ ├── Blink_AG1280_hybrid.hyb │ ├── Blink_AG1280_hybrid.prg │ ├── Blink_AG1280_sram.prg │ ├── README.MD │ └── download.sh ├── hdl ├── Blink_AG10KL144 │ ├── Blink.asf │ ├── Blink.post.asf │ ├── Blink.pre.asf │ ├── Blink.proj │ ├── Blink.qpf │ ├── Blink.qsf │ ├── Blink.sdc │ ├── af_batch.tcl │ ├── af_ip.tcl │ ├── af_map.tcl │ ├── af_quartus.tcl │ └── af_run.tcl ├── Blink_AG10KL144H │ ├── Blink.asf │ ├── Blink.post.asf │ ├── Blink.pre.asf │ ├── Blink.proj │ ├── Blink.qpf │ ├── Blink.qsf │ ├── Blink.sdc │ ├── af_batch.tcl │ ├── af_ip.tcl │ ├── af_map.tcl │ ├── af_quartus.tcl │ └── af_run.tcl ├── Blink_AG1280 │ ├── Blink_AG1280.asf │ ├── Blink_AG1280.post.asf │ ├── Blink_AG1280.pre.asf │ ├── Blink_AG1280.proj │ ├── Blink_AG1280.qpf │ ├── Blink_AG1280.qsf │ ├── Blink_AG1280.sdc │ ├── Blink_AG1280.v │ ├── PLL.ip │ ├── PLL.v │ ├── af_batch.tcl │ ├── af_ip.tcl │ ├── af_map.tcl │ ├── af_quartus.tcl │ ├── af_run.tcl │ ├── build.sh │ ├── common │ │ ├── DFFx2.v │ │ ├── PowerOnReset.v │ │ └── clkdivider.v │ └── download.sh ├── Blink_AG1280_INTOSC │ ├── Blink_AG1280.asf │ ├── Blink_AG1280.post.asf │ ├── Blink_AG1280.pre.asf │ ├── Blink_AG1280.proj │ ├── Blink_AG1280.qpf │ ├── Blink_AG1280.qsf │ ├── Blink_AG1280.sdc │ ├── Blink_AG1280.v │ ├── PLL.ip │ ├── PLL.v │ ├── af_batch.tcl │ ├── af_ip.tcl │ ├── af_map.tcl │ ├── af_quartus.tcl │ ├── af_run.tcl │ ├── build.sh │ ├── common │ │ ├── DFFx2.v │ │ ├── PowerOnReset.v │ │ └── clkdivider.v │ └── download.sh ├── Blink_AG256SL100 │ ├── Blink_AG256SL100.proj │ └── README.md ├── Blink_EP4CE10 │ ├── Blink.cdf │ ├── Blink.cof │ ├── Blink.qpf │ ├── Blink.qsf │ ├── Blink.sdc │ ├── Blink.v │ ├── common │ │ ├── DFFx2.v │ │ └── clkdivider.v │ └── ipcore_dir │ │ ├── PLL.ppf │ │ ├── PLL.qip │ │ └── PLL.v └── Blink_EPM240T100 │ ├── Blink_EPM240T100.qpf │ ├── Blink_EPM240T100.qsf │ ├── Blink_EPM240T100.v │ ├── IP │ ├── OSC_INT.qip │ ├── OSC_INT.v │ ├── UFM_SPI.qip │ └── UFM_SPI.v │ └── common │ ├── DFFx2.v │ ├── PowerOnReset.v │ ├── UART_RX.v │ ├── UART_TX.v │ ├── UART_To_Bus16.v │ ├── UART_To_Bus8.v │ ├── clkdivider.v │ └── debouncer.v ├── image ├── AgmPill_ASM.png ├── AgmPill_PINOUT.png ├── GreenPill.jpg ├── GreenPill_ASM.png ├── MegaPill.jpg └── MegaPill_ASM.png └── sch ├── AgmPill_v21.10.6_ASM.pdf ├── AgmPill_v21.10.6_SCH.pdf ├── GreenPill_v21.12.26.pdf └── MegaPill_v21.11.16.pdf /README.md: -------------------------------------------------------------------------------- 1 | # AgmPill 2 | 3 | AgmPill is a low cost FPGA/CPLD dev-board based on AG1280Q48. 4 | 5 | AG1280 family provides low cost, ultra-low power CPLDs, with density is 1280 Look-Up Tables(LUTs). 6 | The devices feature Embedded Block Memory (EBR), Distributed RAM, and Phase Locked Loops (PLLs). 7 | The devices are designed for ultra low power and cost while providing programmable solutions for a wide 8 | range of applications, especially in consumer and mobile device products. 9 | 10 | ## AgmPill Specification 11 | 12 | - dimension: 41x23mm. 13 | - 2x16 2.54mm PIN header, 20.32mm(800mil), 26 user IO. 14 | - 2x5 PIN standard USB-Blaster port. 15 | - 24MHz dedicated clock input on PIN_13. 16 | - 1280 LUTs. 17 | - 10 Kbits Distributed RAM. 18 | - 68 Kbits EBR SRAM. 19 | - 1xPLL 20 | - EDA Tool:Quartus and Supra. 21 | 22 | ## AgmPill Resource 23 | 24 | - [AgmPill Schematic](./sch/AgmPill_v21.10.6_SCH.pdf) 25 | - [AG1280Q48 Datasheet](./doc/AG1280/AG1280Q48_V1.0.PDF) 26 | - [AG1280Q48 PINOUT](./doc/AG1280/AG1280Q48_PINOUT.xls) 27 | - [AG1280Q48 MANUAL](./doc/AG1280/MANUAL_AG1280.pdf) 28 | - [A Blink Demo](./hdl/Blink_AG1280) 29 | - [Supra and Documents(Fetch Code: q59e)](http://pan.baidu.com/s/1eQxc6XG) 30 | - [FAQ Document](./doc/AgmPillFAQ.md) 31 | - [Purchase Link](https://item.taobao.com/item.htm?spm=a1z10.1-c.w4023-23472711792.7.7a435ad5EnKqe1&id=668471065760) 32 | 33 | ## AgmPill PINOUT 34 | 35 | ![AgmPill PINOUT](./image/AgmPill_PINOUT.png) 36 | 37 | ![AgmPill ASM](./image/AgmPill_ASM.png) 38 | 39 | # MegaPill 40 | 41 | If AgmPill can't satisfy your application, in others words, you need more LEs or IOs, you can try MegaPill, which is based on AG10KL144. 42 | 43 | ## MegaPill Specification 44 | 45 | - dimension: 70x50mm. 46 | - 2x40 2.54mm PIN header. 47 | - Builtin MicroUSB and USB-TTL serial port. 48 | - 2x5 PIN standard USB-Blaster port. 49 | - 24MHz dedicated clock input on PIN_25. 50 | - 10k LEs. 51 | - 414 Kbits EBR SRAM. 52 | - 2xPLL 53 | - EDA Tool:Quartus and Supra. 54 | 55 | ## MegaPill Resource 56 | 57 | - [MegaPill Schematic](./sch/MegaPill_v21.11.16.pdf) 58 | - [AG10KL144 Datasheet](./doc/AG10K/AGM_FPGA_AG6K_AG10K_Rev1.1.PDF) 59 | - [AG10KL144 PINOUT](./doc/AG10K/AG10K_FBGA256_LQFP144_Pinout_Release.xls) 60 | - [AG10KL144 MANUAL](./doc/AG10K/AG10K_guide.pdf) 61 | - [A Blink Demo](./hdl/Blink_AG10KL144) 62 | - [Supra Manual](./doc/MANUAL_Supra_6.2.pdf) 63 | 64 | ## MegaPill PINOUT 65 | 66 | ![MegaPill](./image/MegaPill.jpg) 67 | 68 | ![MegaPill](./image/MegaPill_ASM.png) 69 | 70 | # GreenPill 71 | 72 | If you are familiar with Altera Max II CPLD, you can try GreenPill, which is based on AG256SL100. AG256SL100 is pin2pin compatible with EPM240T100. 73 | Furthermore, GreenPill has a built-in USB-Blaster, you can download bitstream to the chip with a MicroUSB cable. 74 | 75 | ## GreenPill Specification 76 | 77 | - dimension: 70x50mm. 78 | - 2x40 2.54mm PIN header. 79 | - Builtin USB-Blaster. 80 | - 256 LUTs. 81 | - 256 Kbits UFM. 82 | - EDA Tool:Quartus and Supra. 83 | 84 | 85 | ## GreenPill Resource 86 | 87 | - [GreenPill Schematic](./sch/GreenPill_v21.12.26.pdf) 88 | - [AG256SL100 Datasheet](./doc/AGCPLD/AG_CPLD_Rev1_1.PDF) 89 | - [A Blink Demo](./hdl/Blink_AG256SL100) 90 | 91 | ## GreenPill PINOUT 92 | 93 | ![GreenPill](./image/GreenPill.jpg) 94 | 95 | ![GreenPill](./image/GreenPill_ASM.png) 96 | -------------------------------------------------------------------------------- /doc/AG10K/AG10K_FBGA256_LQFP144_Pinout_Release.xls: -------------------------------------------------------------------------------- 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检查AgmPill是否供电，合格的USB-Blaster不能给目标板供电，那个电源管脚是用来做电平检测的。可以使用我们提供的[测试固件和下载脚本](../fw/TB_AG1280)先测试。 17 | - 市面上有些USB-Blaster不具备AS下载功能，因为下载到FLASH要使用到DATAOUT这个信号，这些USB-Blaster无法烧写AgmPill的FLASH，使用我们的USB-Blaster没有这个问题。 18 | 19 | ## 芯片是否有可能锁死？ 20 | 21 | 有这种可能性，如果JTAG接口损坏，或者被占用，那么用户看到的结果就是“锁死了”，如果用户设计文件有未约束的管脚， 22 | Supra布局布线的时候有可能会将这些引脚分配到JTAG接口上，导致芯片“锁死”，解决方法参考[这篇文章](https://zhuanlan.zhihu.com/p/520269868) 23 | 建议设计中不要保留未约束的管脚。 24 | -------------------------------------------------------------------------------- /doc/MANUAL_Supra_6.2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/doc/MANUAL_Supra_6.2.pdf -------------------------------------------------------------------------------- /fw/MegaPill/README.md: -------------------------------------------------------------------------------- 1 | # 固件说明 2 | 3 | 本固件适用于MegaPill核心板，核心器件为AG10KL144或者AG10KL144H，P2P兼容EP4CE10E22。 4 | 5 | - mc8051_boot.prg，FPGA配置文件和MC8051核心固件同时写入FLASH，掉电存储。 6 | - mc8051_master.prg，固件写入FLASH，掉电存储。 7 | - mc8051_sram.prg固件写入SRAM，掉电丢失。 8 | 9 | -------------------------------------------------------------------------------- /fw/MegaPill/download.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | echo "setup envirenment variable..." 4 | . supra_vars.sh 5 | 6 | if [ $# -eq 1 ]; then 7 | case $1 in 8 | sram) 9 | echo "Program SRAM of AG10KL144" 10 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 mc8051_sram.prg" 11 | ;; 12 | flash) 13 | echo "Program FLASH of AG10KL144" 14 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 mc8051_master.prg" 15 | ;; 16 | boot) 17 | echo "Program FPGA bit_stream add MCU firmware to SPI FLASH" 18 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 mc8051_boot.prg" 19 | ;; 20 | esac 21 | else 22 | echo "Usage $0 [sram|flash|boot]" 23 | fi 24 | 25 | 26 | 27 | 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这个命令可以展开，展开以后是直接烧录： 22 | 23 | ``` 24 | af.exe -B -X "set blaster_id 0" -X "hybrid_write -device AG1280Q48 Blink_AG1280_hybrid.hyb" 25 | ``` 26 | 27 | ## 擦除FLASH 28 | 29 | ``` 30 | af.exe -B -X "set blaster_id 0" -X "set bitgen_usb_speed 3000" -X "exit [catch {erase_flash}]" 31 | ``` 32 | 33 | -------------------------------------------------------------------------------- /fw/TB_AG1280/download.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | echo "setup envirenment variable..." 4 | . supra_vars.sh 5 | 6 | if [ $# -eq 1 ]; then 7 | case $1 in 8 | sram) 9 | echo "Program SRAM of AG1280Q48" 10 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 Blink_AG1280_sram.prg" 11 | ;; 12 | flash) 13 | echo "Program FLASH of AG1280Q48" 14 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 Blink_AG1280_hybrid.prg" 15 | ;; 16 | erase) 17 | echo "Erase FLASH of AG1280Q48" 18 | af.exe -B -X "set blaster_id 0" -X "set bitgen_usb_speed 3000" -X "exit [catch {erase_flash}]" 19 | ;; 20 | esac 21 | else 22 | echo "Usage $0 [sram|flash|erase]" 23 | fi 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/Blink.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG10KL144/Blink.asf -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/Blink.post.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG10KL144/Blink.post.asf -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/Blink.pre.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG10KL144/Blink.pre.asf -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/Blink.proj: -------------------------------------------------------------------------------- 1 | [GuiMigrateSetupPage] 2 | fromDir=../Blink_EP4CE10 3 | design=Blink 4 | device=AG10KL144 5 | veFile= 6 | ipFiles= 7 | backwardCompatible=false 8 | modeGroup=false 9 | modeQuartus=true 10 | modeSynplicity=false 11 | modeNative=false 12 | 13 | [GuiMigrateRunPage] 14 | isMC=false 15 | count= 16 | jobs= 17 | seed= 18 | retry=0 19 | fitting=6 20 | fitter=4 21 | effort=3 22 | holdx=0 23 | skew=2 24 | skope=0 25 | preset=0 26 | adjust=0 27 | target=0 28 | tuning=0 29 | flow=0 30 | orgPlace=false 31 | quartusSdc=true 32 | probeForce=false 33 | probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2m\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xab\0\0\0\x1\0\0\0\0) 34 | probeCount=5 35 | probe0From= 36 | probe0Pad= 37 | probe1From= 38 | probe1Pad= 39 | probe2From= 40 | probe2Pad= 41 | probe3From= 42 | probe3Pad= 43 | probe4From= 44 | probe4Pad= 45 | 46 | [GuiProgramScreen] 47 | hardwareId=0 48 | prgFile=Blink_sram.prg 49 | eraseBox=false 50 | cable=UsbBlaster 51 | runAction=read 52 | eraseChip=true 53 | eraseFrom= 54 | eraseTo= 55 | binFile=m25p16.bin 56 | readFrom= 57 | readTo= 58 | 59 | [MainWindow] 60 | recentFile.0= 61 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/Blink.qpf: -------------------------------------------------------------------------------- 1 | #QUARTUS_VERSION = "11.1" 2 | PROJECT_REVISION = "Blink" 3 | 4 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/Blink.qsf: -------------------------------------------------------------------------------- 1 | set_global_assignment -name TOP_LEVEL_ENTITY Blink 2 | set_global_assignment -name FAMILY "Cyclone IV E" 3 | set_global_assignment -name DEVICE EP4CE10E22C8 4 | 5 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 6 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 7 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 8 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 9 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/Blink.sdc: -------------------------------------------------------------------------------- 1 | read_sdc -quiet "E:/echo/project/echo/Company/AGM/Blink_EP4CE10/Blink.sdc" 2 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/af_batch.tcl: -------------------------------------------------------------------------------- 1 | if {![info exist MODE ]} {set MODE QUARTUS} 2 | if {![info exists QUARTUS_SDC]} {set QUARTUS_SDC true} 3 | if {![info exist COUNT]} {set COUNT 6} 4 | if {![info exist JOBS ]} {set JOBS 1} 5 | 6 | if {![info exist SEEDS ]} {set SEEDS {0 0 0 0 666 888 }} 7 | if {![info exist EFFORTS ]} {set EFFORTS {highest highest highest highest high high }} 8 | if {![info exist FITTERS ]} {set FITTERS {hybrid hybrid hybrid hybrid hybrid hybrid }} 9 | if {![info exist FITTINGS]} {set FITTINGS {timing_more timing_more timing_more timing timing basic }} 10 | if {![info exist SKEWS ]} {set SKEWS {advanced advanced advanced advanced aggressive basic }} 11 | if {![info exist HOLDXS ]} {set HOLDXS {default default default default default default}} 12 | 13 | set bc_config "./bc_config.txt" 14 | if { [file exists $bc_config] } { 15 | alta::tcl_highlight "Using MC config $bc_config.\n" 16 | source "$bc_config" 17 | } 18 | 19 | ####################################################################### 20 | 21 | proc get_rand_value { values } { 22 | if {[llength $values] == 0} { return {} } 23 | return [lindex $values [expr {int(rand()*10000)%[llength $values]}]] 24 | } 25 | 26 | set results "bc_results" 27 | set summary "bc_summary.txt" 28 | file delete -force $results; file mkdir $results 29 | file delete $summary; print -nonewline "" >! $summary 30 | 31 | set is_parallel [expr $JOBS > 1] 32 | set is_color ""; set is_gui ""; set is_quiet "" 33 | if { $is_parallel } { 34 | set is_gui "--quiet" 35 | } else { 36 | if { [alta::tcl_is_color] } { set is_color "--color" } 37 | if { [alta::tcl_is_gui ] } { set is_gui "--gui" } 38 | } 39 | 40 | ####################################################################### 41 | 42 | set progs {} 43 | set titles {} 44 | for {set id 1} {$id <= $COUNT} {incr id} { 45 | set result_dir "$results/$id" 46 | file mkdir $result_dir 47 | 48 | set seed [get_rand_value $SEEDS ] 49 | set effort [get_rand_value $EFFORTS ] 50 | set skew [get_rand_value $SKEWS ] 51 | set fitter [get_rand_value $FITTERS ] 52 | set fitting [get_rand_value $FITTINGS] 53 | set holdx [get_rand_value $HOLDXS ] 54 | 55 | set prog [list [info nameofexec] $is_quiet $is_color $is_gui -B --batch --mode $MODE] 56 | alta::lconcat prog [list -X "set QUARTUS_SDC $QUARTUS_SDC"] 57 | alta::lconcat prog [list -X "set RESULT_DIR $result_dir"] 58 | if { $seed != "" } { 59 | alta::lconcat prog [list -X "set SEED $seed"] 60 | } 61 | if { $effort != "" } { 62 | alta::lconcat prog [list -X "set EFFORT $effort"] 63 | } 64 | if { $fitter != "" } { 65 | alta::lconcat prog [list -X "set FITTER $fitter"] 66 | } 67 | if { $fitting != "" } { 68 | alta::lconcat prog [list -X "set FITTING $fitting"] 69 | } 70 | if { $skew != "" } { 71 | alta::lconcat prog [list -X "set SKEW $skew"] 72 | } 73 | if { $holdx != "" } { 74 | alta::lconcat prog [list -X "set HOLDX $holdx"] 75 | } 76 | #alta::lconcat prog [list -F af_run.tcl] 77 | lappend progs $prog 78 | lappend titles "#$id $result_dir" 79 | } 80 | 81 | ####################################################################### 82 | 83 | if { $is_parallel } { 84 | set bg_progs {} 85 | foreach bg_prog $progs { 86 | lappend bg_progs [lappend bg_prog $is_quiet] 87 | } 88 | bg_exec_queue $titles $bg_progs $JOBS 89 | } 90 | 91 | ####################################################################### 92 | 93 | for {set id 1} {$id <= $COUNT} {incr id} { 94 | set result_dir "$results/$id" 95 | set prog [lindex $progs [expr $id-1]] 96 | set title [lindex $titles [expr $id-1]] 97 | if { ! $is_parallel } { 98 | puts $title 99 | puts $prog 100 | eval exec -ignorestderr $prog >&@ stdout 101 | } 102 | 103 | print "***************************************************************************\n" >> $summary 104 | print "$title\n" >> $summary 105 | cat "$result_dir/alta_db/fmax.rpt" >> $summary 106 | cat "$result_dir/alta_db/xfer.rpt" >> $summary 107 | print "" >> $summary 108 | } 109 | 110 | alta::tcl_highlight "Check $summary for result.\n" 111 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/af_ip.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set DESIGN "Blink" 3 | set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc } 4 | lappend IPLIST alta_rv32 5 | 6 | proc set_alta_partition {inst tag} { 7 | set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst] 8 | set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst] 9 | set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst] 10 | set section_id [string map { [ _ ] _ . _ | _} $inst_name] 11 | eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag" 12 | eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag" 13 | eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag" 14 | eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag" 15 | } 16 | 17 | load_package flow 18 | project_open $DESIGN 19 | 20 | set tag alta_auto 21 | if { [llength $IPLIST] > 0 } { 22 | eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag" 23 | eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag" 24 | eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag" 25 | eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -tag $tag" 26 | catch { execute_module -tool map } 27 | 28 | foreach ip $IPLIST { 29 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] { 30 | set_alta_partition $inst $tag 31 | } 32 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] { 33 | set_alta_partition $inst $tag 34 | } 35 | } 36 | } 37 | eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation" 38 | 39 | project_close 40 | 41 | exit 42 | 43 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/af_map.tcl: -------------------------------------------------------------------------------- 1 | map -import 2 | 3 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 4 | set TOP_MODULE "$DESIGN" 5 | } 6 | if { ! [info exists DESIGN] } { 7 | set DESIGN "Blink" 8 | } 9 | if { ! [info exists TOP_MODULE] } { 10 | set TOP_MODULE "Blink" 11 | } 12 | 13 | set verilogs { E:\\echo\\project\\echo\\Company\\AGM\\Blink_EP4CE10\\common\\DFFx2.v E:\\echo\\project\\echo\\Company\\AGM\\Blink_EP4CE10\\common\\clkdivider.v E:\\echo\\project\\echo\\Company\\AGM\\Blink_EP4CE10\\ipcore_dir\\PLL.v E:\\echo\\project\\echo\\Company\\AGM\\Blink_EP4CE10\\Blink.v } 14 | if { [ llength $verilogs ] == 0 } { 15 | set verilogs "E:/echo/project/echo/Company/AGM/Blink_EP4CE10/${DESIGN}.v" 16 | } 17 | foreach verilog $verilogs { 18 | read_verilog "$verilog" 19 | } 20 | 21 | read_verilog -sv -lib +/agm/rodina/cells_sim.v 22 | read_verilog -sv -lib +/agm/common/m9k_bb.v 23 | read_verilog -sv -lib +/agm/common/altpll_bb.v 24 | hierarchy -check -top ${TOP_MODULE} 25 | 26 | synth -run coarse -top ${DESIGN} 27 | 28 | map proc 29 | opt_expr 30 | opt_clean 31 | check 32 | opt 33 | 34 | wreduce 35 | alumacc 36 | share 37 | opt 38 | fsm 39 | opt -fast 40 | memory -nomap 41 | opt_clean 42 | 43 | memory_bram -rules +/agm/common/brams.txt 44 | techmap -map +/agm/common/brams_map.v 45 | 46 | opt -fast -mux_undef -undriven -fine -full 47 | memory_map 48 | opt -undriven -fine 49 | 50 | techmap -autoproc -map +/techmap.v -map +/agm/rodina/arith_map.v 51 | dffsr2dff 52 | dff2dffe -direct-match \$_DFF_* 53 | opt -full 54 | 55 | techmap -map +/agm/rodina/cells_map.v 56 | agm_dffeas 57 | opt -full 58 | 59 | clean -purge 60 | setundef -undriven -zero 61 | abc -markgroups -dff 62 | opt_expr -mux_undef -undriven -full 63 | opt_merge 64 | opt_rmdff 65 | opt_clean 66 | 67 | abc -lut 4 68 | clean 69 | 70 | techmap -map +/agm/rodina/cells_map.v 71 | dffinit -ff dffeas Q INIT 72 | clean -purge 73 | 74 | hierarchy -check 75 | check -noinit 76 | 77 | write_verilog -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm 78 | # exec sed -i "/\\\\\\\$paramod/s/\[$=\\]/_/g" ${DESIGN}.vqm 79 | 80 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/af_quartus.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set RETRY 0 3 | set DESIGN "Blink" 4 | 5 | if { [is_project_open] } { 6 | export_assignments 7 | } 8 | 9 | set is_compatible true 10 | if { $is_compatible } { 11 | cd E:/echo/project/echo/Company/AGM/Blink_EP4CE10 12 | qexec "[file join $::quartus(binpath) quartus_eda] $DESIGN --simulation --tool=modelsim --format=verilog" 13 | } else { 14 | set FITTER_EFFORTS {"STANDARD FIT" "STANDARD FIT" "FAST FIT" "FAST FIT" "FAST FIT"} 15 | set SEEDS [list [expr int(rand()*100)] \ 16 | [expr int(rand()*100)] \ 17 | [expr int(rand()*100)] \ 18 | [expr int(rand()*100)] \ 19 | [expr int(rand()*100)]] 20 | set PLACEMENT_EFFORTS [list [expr rand()*5+0.1] \ 21 | [expr rand()*5+0.1] \ 22 | [expr rand()*5+0.1] \ 23 | [expr rand()*5+0.1] \ 24 | [expr rand()*5+0.1]] 25 | set ROUTER_EFFORTS [list [expr rand()*5+0.25] \ 26 | [expr rand()*5+0.25] \ 27 | [expr rand()*5+0.25] \ 28 | [expr rand()*5+0.25] \ 29 | [expr rand()*5+0.25]] 30 | 31 | qexec "[file join $::quartus(binpath) quartus_sh] -t af_ip.tcl" 32 | 33 | load_package flow 34 | project_open $DESIGN 35 | 36 | set RETRY [expr $RETRY<[llength $FITTER_EFFORTS]?$RETRY:[llength $FITTER_EFFORTS]] 37 | for {set nn -1} {$nn < $RETRY} {incr nn} { 38 | if {$nn >= 0} { 39 | set_global_assignment -name FITTER_EFFORT \"[lindex $FITTER_EFFORTS $nn]\" 40 | set_global_assignment -name SEED [lindex $SEEDS $nn] 41 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER [lindex $PLACEMENT_EFFORTS $nn] 42 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER [lindex $ROUTER_EFFORTS $nn] 43 | } 44 | 45 | set code [catch {execute_flow -compile} msg] 46 | if { $code == 0 } { break } 47 | } 48 | } 49 | 50 | 51 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144/af_run.tcl: -------------------------------------------------------------------------------- 1 | set ALTA_SUPRA true 2 | set sh_continue_on_error false 3 | set sh_echo_on_source true 4 | set sh_quiet_on_source true 5 | set cc_critical_as_fatal true 6 | set rt_incremental_route true 7 | set ta_report_auto 1 8 | set ta_report_auto_constraints $ta_report_auto 9 | 10 | if { ! [info exists RESULT_DIR] } { 11 | set RESULT_DIR "." 12 | } elseif { ! [info exists alta_work] } { 13 | set alta_work "${RESULT_DIR}/alta_db" 14 | } 15 | if { ! [info exists DEVICE] } { 16 | set DEVICE "AG10KL144" 17 | } 18 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 19 | set TOP_MODULE "$DESIGN" 20 | } 21 | if { ! [info exists DESIGN] } { 22 | set DESIGN "Blink" 23 | } 24 | if { ! [info exists TOP_MODULE] } { 25 | set TOP_MODULE "Blink" 26 | } 27 | if { ! [info exists IP_FILES] } { 28 | set IP_FILES {} 29 | } 30 | if { ! [info exists VE_FILE] } { 31 | set VE_FILE "" 32 | } 33 | if { ! [info exists TIMING_DERATE] } { 34 | set TIMING_DERATE 1.000000 35 | } 36 | if { [info exists NO_ROUTE] && $NO_ROUTE } { 37 | set no_route "-no_route" 38 | } else { 39 | set no_route "" 40 | } 41 | if { ! [info exists RETRY] } { set RETRY 0 } 42 | if { ! [info exists SEED ] } { set SEED 666 } 43 | set seed_rand "" 44 | if { $SEED == 0 } { set seed_rand "-seed_rand" } 45 | if { [info exists QUARTUS_SDC] } { 46 | set sdc_remove_quartus_column_name $QUARTUS_SDC 47 | } 48 | if { ! [info exists ORG_PLACE] } { set ORG_PLACE false } 49 | if { ! [info exists MODE] } { set MODE "QUARTUS" } 50 | if { ! [info exists FLOW] } { set FLOW "ALL" } 51 | if { $FLOW == "PROBE" } { 52 | if { ! [info exists PROBE_FORCE] } { set PROBE_FORCE false } 53 | if { ! [info exists PREFIX] } { set PREFIX "probe_" } 54 | } 55 | if { ! [info exists PREFIX] } { 56 | set RESULT $DESIGN 57 | } else { 58 | set RESULT $PREFIX$DESIGN 59 | } 60 | if { $FLOW == "GEN" || $FLOW == "PACK" || $FLOW == "SKIP" } { set no_route "-no_route" } 61 | set RUN "run" 62 | if { $FLOW == "CHECK" } { 63 | set RUN "check" 64 | } elseif { $FLOW == "PROBE" } { 65 | set RUN "probe" 66 | } elseif { $FLOW == "GEN" } { 67 | set RUN "gen" 68 | } 69 | 70 | if { ! [info exists alta_logs] } { 71 | set alta_logs "${RESULT_DIR}/alta_logs" 72 | } 73 | file mkdir $alta_logs 74 | alta::begin_log_cmd "$alta_logs/${RUN}.log" "$alta_logs/${RUN}.err" 75 | alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n" 76 | alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n" 77 | 78 | set_seed_rand $SEED 79 | set ar_timing_derate ${TIMING_DERATE} 80 | 81 | date_time 82 | if { [file exists "./${DESIGN}.pre.asf"] } { 83 | alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n" 84 | source "./${DESIGN}.pre.asf" 85 | } 86 | 87 | eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000" 88 | foreach ip_file $IP_FILES { read_ip $ip_file; } 89 | 90 | set LOAD_DB false 91 | set LOAD_PLACE false 92 | set LOAD_ROUTE false 93 | if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } { 94 | set LOAD_DB true 95 | set LOAD_PLACE true 96 | set LOAD_ROUTE true 97 | } elseif { $FLOW == "R" || $FLOW == "ROUTE" } { 98 | set LOAD_DB true 99 | set LOAD_PLACE true 100 | } 101 | 102 | set ORIGINAL_QSF "E:/echo/project/echo/Company/AGM/Blink_EP4CE10/./Blink.qsf" 103 | set ORIGINAL_PIN "E:/echo/project/echo/Company/AGM/Blink_EP4CE10/out/Blink.pin" 104 | 105 | ################################################################################# 106 | 107 | if { $FLOW == "GEN" } { 108 | if { ! [info exists CONFIG_BITS] } { 109 | set CONFIG_BITS "${RESULT_DIR}/${DESIGN}.bin" 110 | } 111 | if { [llength $CONFIG_BITS] > 1 } { 112 | if { ! [info exists BOOT_BINARY] } { 113 | set BOOT_BINARY "${RESULT_DIR}/${DESIGN}_boot.bin" 114 | } 115 | if { ! [info exists CONFIG_ADDRESSES] } { 116 | set CONFIG_ADDRESSES "" 117 | } 118 | generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES 119 | } else { 120 | set CONFIG_ROOT [file rootname [lindex $CONFIG_BITS 0]] 121 | set SLAVE_RBF "${CONFIG_ROOT}_slave.rbf" 122 | set MASTER_BINARY "${CONFIG_ROOT}_master.bin" 123 | if { [file exists [lindex $CONFIG_BITS 0]] } { 124 | generate_binary -slave $SLAVE_RBF -inputs [lindex $CONFIG_BITS 0] -reverse 125 | generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0] 126 | } 127 | if { ! [info exists BOOT_BINARY] } { 128 | set BOOT_BINARY $MASTER_BINARY 129 | } 130 | } 131 | set PRG_FILE [file rootname $BOOT_BINARY].prg 132 | set AS_FILE [file rootname $BOOT_BINARY]_as.prg 133 | generate_programming_file $BOOT_BINARY -erase $ERASE \ 134 | -program $PROGRAM -verify $VERIFY -offset $OFFSET \ 135 | -prg $PRG_FILE -as $AS_FILE 136 | exit 137 | } 138 | 139 | if { $LOAD_DB } { 140 | load_db -top ${TOP_MODULE} 141 | set sdc "./${DESIGN}.adc" 142 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 143 | if { [file exists $sdc] } { read_sdc $sdc; } 144 | 145 | } elseif { $MODE == "QUARTUS" } { 146 | set verilog ${DESIGN}.vo 147 | set is_migrated false 148 | if { ! [file exists $verilog] } { 149 | set verilog "E:/echo/project/echo/Company/AGM/Blink_EP4CE10/simulation/modelsim/${DESIGN}.vo" 150 | set is_migrated true 151 | } 152 | if { ! [file exists $verilog] } { 153 | error "Can not find design verilog file $verilog" 154 | } 155 | alta::tcl_highlight "Using design verilog file $verilog.\n" 156 | set ret [read_design -top ${TOP_MODULE} -ve $VE_FILE -qsf $ORIGINAL_QSF $verilog -hierachy 1] 157 | if { !$ret } { exit -1; } 158 | 159 | set sdc "./${DESIGN}.adc" 160 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 161 | if { ! [file exists $sdc] } { 162 | alta::tcl_warn "Can not find design SDC file $sdc" 163 | } else { 164 | alta::tcl_highlight "Using design SDC file $sdc.\n" 165 | read_sdc $sdc 166 | } 167 | 168 | } elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { 169 | set db_gclk_assignment_level 2 170 | set verilog ${DESIGN}.vqm 171 | set is_migrated false 172 | if { ! [file exists $verilog] } { 173 | error "Can not find design verilog file $verilog" 174 | } 175 | 176 | set sdc "./${DESIGN}.adc" 177 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 178 | alta::tcl_highlight "Using design verilog file $verilog.\n" 179 | if { ! [file exists $sdc] } { 180 | alta::tcl_warn "Can not find design SDC file $sdc" 181 | set ret [read_design_and_pack -sdc $sdc -top ${TOP_MODULE} $verilog] 182 | } else { 183 | alta::tcl_highlight "Using design SDC file $sdc.\n" 184 | set ret [read_design_and_pack -top ${TOP_MODULE} $verilog] 185 | } 186 | if { !$ret } { exit -1; } 187 | 188 | } else { 189 | error "Unsupported mode $MODE" 190 | } 191 | 192 | if { [info exists FITTING] } { 193 | if { $FITTING == "Auto" } { set FITTING auto; } 194 | set_mode -fitting $FITTING 195 | } 196 | if { [info exists FITTER] } { 197 | if { $FITTER == "Auto" } { 198 | if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; } 199 | } 200 | if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; } 201 | set_mode -fitter $FITTER 202 | } 203 | if { [info exists EFFORT] } { set_mode -effort $EFFORT; } 204 | if { [info exists SKEW ] } { set_mode -skew $SKEW ; } 205 | if { [info exists SKOPE ] } { set_mode -skope $SKOPE ; } 206 | if { [info exists HOLDX ] } { set_mode -holdx $HOLDX; } 207 | if { [info exists TUNING] } { set_mode -tuning $TUNING; } 208 | if { [info exists TARGET] } { set_mode -target $TARGET; } 209 | if { [info exists PRESET] } { set_mode -preset $PRESET; } 210 | if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; } 211 | 212 | set alta_aqf $::alta_work/alta.aqf 213 | if { $LOAD_DB } { 214 | # Empty 215 | } elseif { true } { 216 | if { [file exists $VE_FILE] } { 217 | set ORIGINAL_PIN "" 218 | } elseif { ! [file exists $ORIGINAL_PIN] } { 219 | if { $is_migrated } { 220 | error "Can not find design PIN file $ORIGINAL_PIN, please compile design first" 221 | } 222 | set ORIGINAL_PIN "" 223 | } 224 | if { [file exists $ORIGINAL_QSF] } { 225 | alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf 226 | } elseif { $is_migrated } { 227 | error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first" 228 | } 229 | } 230 | if { [file exists "$alta_aqf"] } { 231 | alta::tcl_highlight "Using AQF file $alta_aqf.\n" 232 | source "$alta_aqf" 233 | } 234 | if { [file exists "./${DESIGN}.asf"] } { 235 | alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n" 236 | source "./${DESIGN}.asf" 237 | } 238 | 239 | if { $FLOW == "PROBE" } { 240 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 241 | if { !$ret } { exit -1 } 242 | 243 | set force "" 244 | if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" } 245 | eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}" 246 | 247 | } elseif { $FLOW == "CHECK" } { 248 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 249 | if { !$ret } { exit -1 } 250 | 251 | if { [file exists "./${DESIGN}.chk"] } { 252 | alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n" 253 | source "./${DESIGN}.chk" 254 | place_design -dry 255 | check_design -rule led_guide 256 | } else { 257 | error "Can not find design CHECK file ${DESIGN}.chk" 258 | } 259 | 260 | } else { 261 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io] 262 | if { !$ret } { exit -1 } 263 | if { $FLOW == "PACK" } { exit } 264 | 265 | set org_place "" 266 | set load_place "" 267 | set load_route "" 268 | set quiet "" 269 | if { $ORG_PLACE } { set org_place "-org_place" ; } 270 | if { $LOAD_PLACE } { set load_place "-load_place"; } 271 | if { $LOAD_ROUTE } { set load_route "-load_route"; } 272 | eval "place_and_route_design $org_place $load_place $load_route \ 273 | -retry $RETRY $seed_rand $quiet" 274 | } 275 | 276 | date_time 277 | if { $FLOW != "CHECK" } { 278 | if { $FLOW != "PROBE" } { 279 | #report_timing -verbose 1 -file $::alta_work/timing.rpt.gz 280 | report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz 281 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz 282 | report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz 283 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz 284 | 285 | set ta_report_auto_constraints 0 286 | report_timing -fmax -file $::alta_work/fmax.rpt 287 | report_timing -xfer -file $::alta_work/xfer.rpt 288 | set ta_report_auto_constraints $ta_report_auto 289 | 290 | #set ta_coverage_limit "0.95 0.90" 291 | set ta_dump_uncovered 1 292 | report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz 293 | #unset ta_coverage_limit 294 | unset ta_dump_uncovered 295 | 296 | 297 | if { ! [info exists rt_report_timing_fast] } { 298 | set rt_report_timing_fast false 299 | } 300 | if { $rt_report_timing_fast } { 301 | set_timing_corner fast 302 | route_delay -quiet 303 | report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz 304 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_fast_summary.rpt.gz 305 | report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz 306 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_fast_summary.rpt.gz 307 | set ta_report_auto_constraints 0 308 | report_timing -fmax -file $::alta_work/fmax_fast.rpt 309 | report_timing -xfer -file $::alta_work/xfer_fast.rpt 310 | set ta_report_auto_constraints $ta_report_auto 311 | } 312 | 313 | write_routed_design "${RESULT_DIR}/${RESULT}_routed.v" 314 | } 315 | 316 | bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin" 317 | bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg" 318 | bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf" 319 | generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \ 320 | -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse 321 | generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \ 322 | -inputs "${RESULT_DIR}/${RESULT}.bin" 323 | generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \ 324 | -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg" 325 | } 326 | 327 | if { [file exists "./${DESIGN}.post.asf"] } { 328 | alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n" 329 | source "./${DESIGN}.post.asf" 330 | } 331 | date_time 332 | exit 333 | 334 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/Blink.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG10KL144H/Blink.asf -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/Blink.post.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG10KL144H/Blink.post.asf -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/Blink.pre.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG10KL144H/Blink.pre.asf -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/Blink.proj: -------------------------------------------------------------------------------- 1 | [GuiMigrateSetupPage] 2 | fromDir=../Blink_EP4CE10 3 | design=Blink 4 | device=AG10KL144H 5 | veFile= 6 | ipFiles= 7 | backwardCompatible=false 8 | modeGroup=false 9 | modeQuartus=true 10 | modeSynplicity=false 11 | modeNative=false 12 | 13 | [GuiMigrateRunPage] 14 | isMC=false 15 | count= 16 | jobs= 17 | seed= 18 | retry=0 19 | fitting=6 20 | fitter=4 21 | effort=3 22 | holdx=0 23 | skew=2 24 | skope=0 25 | preset=0 26 | adjust=0 27 | target=0 28 | tuning=0 29 | flow=0 30 | orgPlace=false 31 | quartusSdc=true 32 | probeForce=false 33 | probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2m\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xab\0\0\0\x1\0\0\0\0) 34 | probeCount=5 35 | probe0From= 36 | probe0Pad= 37 | probe1From= 38 | probe1Pad= 39 | probe2From= 40 | probe2Pad= 41 | probe3From= 42 | probe3Pad= 43 | probe4From= 44 | probe4Pad= 45 | 46 | [GuiProgramScreen] 47 | hardwareId=0 48 | prgFile=Blink_master.prg 49 | eraseBox=false 50 | cable=0 51 | runAction=program 52 | eraseChip=true 53 | eraseFrom= 54 | eraseTo= 55 | binFile=m25p16.bin 56 | readFrom= 57 | readTo= 58 | blasterSpeed=70 59 | 60 | [MainWindow] 61 | recentFile.0= 62 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/Blink.qpf: -------------------------------------------------------------------------------- 1 | #QUARTUS_VERSION = "11.1" 2 | PROJECT_REVISION = "Blink" 3 | 4 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/Blink.qsf: -------------------------------------------------------------------------------- 1 | set_global_assignment -name TOP_LEVEL_ENTITY Blink 2 | set_global_assignment -name FAMILY "Cyclone IV E" 3 | set_global_assignment -name DEVICE "EP4CE10E22C8" 4 | 5 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 6 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 7 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 8 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 9 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/Blink.sdc: -------------------------------------------------------------------------------- 1 | read_sdc -quiet "E:/echo/git/github/xjtuecho/AgmPill/hdl/Blink_EP4CE10/Blink.sdc" 2 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/af_batch.tcl: -------------------------------------------------------------------------------- 1 | if {![info exist MODE ]} {set MODE QUARTUS} 2 | if {![info exists QUARTUS_SDC]} {set QUARTUS_SDC true} 3 | if {![info exist COUNT]} {set COUNT 6} 4 | if {![info exist JOBS ]} {set JOBS 1} 5 | 6 | if {![info exist SEEDS ]} {set SEEDS {0 0 0 0 666 888 }} 7 | if {![info exist EFFORTS ]} {set EFFORTS {highest highest highest highest high high }} 8 | if {![info exist FITTERS ]} {set FITTERS {hybrid hybrid hybrid hybrid hybrid hybrid }} 9 | if {![info exist FITTINGS]} {set FITTINGS {timing_more timing_more timing_more timing timing basic }} 10 | if {![info exist SKEWS ]} {set SKEWS {advanced advanced advanced advanced aggressive basic }} 11 | if {![info exist HOLDXS ]} {set HOLDXS {default default default default default default}} 12 | 13 | set bc_config "./bc_config.txt" 14 | if { [file exists $bc_config] } { 15 | alta::tcl_highlight "Using MC config $bc_config.\n" 16 | source "$bc_config" 17 | } 18 | 19 | ####################################################################### 20 | 21 | proc get_rand_value { values } { 22 | if {[llength $values] == 0} { return {} } 23 | return [lindex $values [expr {int(rand()*10000)%[llength $values]}]] 24 | } 25 | 26 | set results "bc_results" 27 | set summary "bc_summary.txt" 28 | file delete -force $results; file mkdir $results 29 | file delete $summary; print -nonewline "" >! $summary 30 | 31 | set is_parallel [expr $JOBS > 1] 32 | set is_color ""; set is_gui ""; set is_quiet "" 33 | if { $is_parallel } { 34 | set is_gui "--quiet" 35 | } else { 36 | if { [alta::tcl_is_color] } { set is_color "--color" } 37 | if { [alta::tcl_is_gui ] } { set is_gui "--gui" } 38 | } 39 | 40 | ####################################################################### 41 | 42 | set progs {} 43 | set titles {} 44 | for {set id 1} {$id <= $COUNT} {incr id} { 45 | set result_dir "$results/$id" 46 | file mkdir $result_dir 47 | 48 | set seed [get_rand_value $SEEDS ] 49 | set effort [get_rand_value $EFFORTS ] 50 | set skew [get_rand_value $SKEWS ] 51 | set fitter [get_rand_value $FITTERS ] 52 | set fitting [get_rand_value $FITTINGS] 53 | set holdx [get_rand_value $HOLDXS ] 54 | 55 | set prog [list [info nameofexec] $is_quiet $is_color $is_gui -B --batch --mode $MODE] 56 | alta::lconcat prog [list -X "set QUARTUS_SDC $QUARTUS_SDC"] 57 | alta::lconcat prog [list -X "set RESULT_DIR $result_dir"] 58 | if { $seed != "" } { 59 | alta::lconcat prog [list -X "set SEED $seed"] 60 | } 61 | if { $effort != "" } { 62 | alta::lconcat prog [list -X "set EFFORT $effort"] 63 | } 64 | if { $fitter != "" } { 65 | alta::lconcat prog [list -X "set FITTER $fitter"] 66 | } 67 | if { $fitting != "" } { 68 | alta::lconcat prog [list -X "set FITTING $fitting"] 69 | } 70 | if { $skew != "" } { 71 | alta::lconcat prog [list -X "set SKEW $skew"] 72 | } 73 | if { $holdx != "" } { 74 | alta::lconcat prog [list -X "set HOLDX $holdx"] 75 | } 76 | #alta::lconcat prog [list -F af_run.tcl] 77 | lappend progs $prog 78 | lappend titles "#$id $result_dir" 79 | } 80 | 81 | ####################################################################### 82 | 83 | if { $is_parallel } { 84 | set bg_progs {} 85 | foreach bg_prog $progs { 86 | lappend bg_progs [lappend bg_prog $is_quiet] 87 | } 88 | bg_exec_queue $titles $bg_progs $JOBS 89 | } 90 | 91 | ####################################################################### 92 | 93 | for {set id 1} {$id <= $COUNT} {incr id} { 94 | set result_dir "$results/$id" 95 | set prog [lindex $progs [expr $id-1]] 96 | set title [lindex $titles [expr $id-1]] 97 | if { ! $is_parallel } { 98 | puts $title 99 | puts $prog 100 | eval exec -ignorestderr $prog >&@ stdout 101 | } 102 | 103 | print "***************************************************************************\n" >> $summary 104 | print "$title\n" >> $summary 105 | cat "$result_dir/alta_db/fmax.rpt" >> $summary 106 | cat "$result_dir/alta_db/xfer.rpt" >> $summary 107 | print "" >> $summary 108 | } 109 | 110 | alta::tcl_highlight "Check $summary for result.\n" 111 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/af_ip.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set DESIGN "Blink" 3 | set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp } 4 | lappend IPLIST alta_rv32 5 | 6 | proc set_alta_partition {inst tag} { 7 | set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst] 8 | set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst] 9 | set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst] 10 | set section_id [string map { [ _ ] _ . _ | _} $inst_name] 11 | eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag" 12 | eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag" 13 | eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag" 14 | eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag" 15 | } 16 | 17 | load_package flow 18 | if { $DESIGN == "" } { 19 | set DESIGN $::quartus(args) 20 | } 21 | project_open $DESIGN 22 | 23 | set tag alta_auto 24 | if { [llength $IPLIST] > 0 } { 25 | # A Quartus bug saves PARTITION_HIERARCHY assignments without tag. Use section_id to remove them. 26 | set asgn_col [get_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag] 27 | foreach_in_collection part $asgn_col { 28 | set section_id [lindex $part 0] 29 | eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -section_id $section_id" 30 | } 31 | eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag" 32 | eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag" 33 | eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag" 34 | catch { execute_module -tool map } 35 | 36 | foreach ip $IPLIST { 37 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] { 38 | set_alta_partition $inst $tag 39 | } 40 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] { 41 | set_alta_partition $inst $tag 42 | } 43 | } 44 | } 45 | eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation" 46 | 47 | project_close 48 | 49 | exit 50 | 51 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/af_map.tcl: -------------------------------------------------------------------------------- 1 | map -import 2 | 3 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 4 | set TOP_MODULE "$DESIGN" 5 | } 6 | if { ! [info exists DESIGN] } { 7 | set DESIGN "Blink" 8 | } 9 | if { ! [info exists TOP_MODULE] } { 10 | set TOP_MODULE "Blink" 11 | } 12 | 13 | set verilogs { E:\\echo\\git\\github\\xjtuecho\\AgmPill\\hdl\\Blink_EP4CE10\\common\\DFFx2.v E:\\echo\\git\\github\\xjtuecho\\AgmPill\\hdl\\Blink_EP4CE10\\common\\clkdivider.v E:\\echo\\git\\github\\xjtuecho\\AgmPill\\hdl\\Blink_EP4CE10\\ipcore_dir\\PLL.v E:\\echo\\git\\github\\xjtuecho\\AgmPill\\hdl\\Blink_EP4CE10\\Blink.v } 14 | if { [ llength $verilogs ] == 0 } { 15 | set verilogs "E:/echo/git/github/xjtuecho/AgmPill/hdl/Blink_EP4CE10/${DESIGN}.v" 16 | } 17 | foreach verilog $verilogs { 18 | read_verilog "$verilog" 19 | } 20 | 21 | read_verilog -sv -lib +/agm/rodina/cells_sim.v 22 | read_verilog -sv -lib +/agm/common/m9k_bb.v 23 | read_verilog -sv -lib +/agm/common/altpll_bb.v 24 | hierarchy -check -top ${TOP_MODULE} 25 | 26 | synth -run coarse -top ${DESIGN} 27 | 28 | map proc 29 | opt_expr 30 | opt_clean 31 | check 32 | opt 33 | 34 | wreduce 35 | alumacc 36 | share 37 | opt 38 | fsm 39 | opt -fast 40 | memory -nomap 41 | opt_clean 42 | 43 | memory_bram -rules +/agm/common/brams.txt 44 | techmap -map +/agm/common/brams_map.v 45 | 46 | opt -fast -mux_undef -undriven -fine -full 47 | memory_map 48 | opt -undriven -fine 49 | 50 | techmap -autoproc -map +/techmap.v -map +/agm/rodina/arith_map.v 51 | dffsr2dff 52 | dff2dffe -direct-match \$_DFF_* 53 | opt -full 54 | 55 | techmap -map +/agm/rodina/cells_map.v 56 | agm_dffeas 57 | opt -full 58 | 59 | clean -purge 60 | setundef -undriven -zero 61 | abc -markgroups -dff 62 | opt_expr -mux_undef -undriven -full 63 | opt_merge 64 | opt_rmdff 65 | opt_clean 66 | 67 | abc -lut 4 68 | clean 69 | 70 | techmap -map +/agm/rodina/cells_map.v 71 | dffinit -ff dffeas Q INIT 72 | clean -purge 73 | 74 | hierarchy -check 75 | check -noinit 76 | 77 | write_verilog -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm 78 | # exec sed -i "/\\\\\\\$paramod/s/\[$=\\]/_/g" ${DESIGN}.vqm 79 | 80 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/af_quartus.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set RETRY 0 3 | set DESIGN "Blink" 4 | 5 | if { [is_project_open] } { 6 | export_assignments 7 | } 8 | 9 | set is_compatible true 10 | if { $is_compatible } { 11 | cd E:/echo/git/github/xjtuecho/AgmPill/hdl/Blink_EP4CE10 12 | qexec "[file join $::quartus(binpath) quartus_eda] $DESIGN --simulation --tool=modelsim --format=verilog" 13 | } else { 14 | set FITTER_EFFORTS {"STANDARD FIT" "STANDARD FIT" "FAST FIT" "FAST FIT" "FAST FIT"} 15 | set SEEDS [list [expr int(rand()*100)] \ 16 | [expr int(rand()*100)] \ 17 | [expr int(rand()*100)] \ 18 | [expr int(rand()*100)] \ 19 | [expr int(rand()*100)]] 20 | set PLACEMENT_EFFORTS [list [expr rand()*5+0.1] \ 21 | [expr rand()*5+0.1] \ 22 | [expr rand()*5+0.1] \ 23 | [expr rand()*5+0.1] \ 24 | [expr rand()*5+0.1]] 25 | set ROUTER_EFFORTS [list [expr rand()*5+0.25] \ 26 | [expr rand()*5+0.25] \ 27 | [expr rand()*5+0.25] \ 28 | [expr rand()*5+0.25] \ 29 | [expr rand()*5+0.25]] 30 | 31 | qexec "[file join $::quartus(binpath) quartus_sh] -t af_ip.tcl" 32 | 33 | load_package flow 34 | project_open $DESIGN 35 | 36 | set RETRY [expr $RETRY<[llength $FITTER_EFFORTS]?$RETRY:[llength $FITTER_EFFORTS]] 37 | for {set nn -1} {$nn < $RETRY} {incr nn} { 38 | if {$nn >= 0} { 39 | set_global_assignment -name FITTER_EFFORT \"[lindex $FITTER_EFFORTS $nn]\" 40 | set_global_assignment -name SEED [lindex $SEEDS $nn] 41 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER [lindex $PLACEMENT_EFFORTS $nn] 42 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER [lindex $ROUTER_EFFORTS $nn] 43 | } 44 | 45 | set code [catch {execute_flow -compile} msg] 46 | if { $code == 0 } { break } 47 | } 48 | } 49 | 50 | 51 | -------------------------------------------------------------------------------- /hdl/Blink_AG10KL144H/af_run.tcl: -------------------------------------------------------------------------------- 1 | set ALTA_SUPRA true 2 | set sh_continue_on_error false 3 | set sh_echo_on_source true 4 | set sh_quiet_on_source true 5 | set cc_critical_as_fatal true 6 | set rt_incremental_route true 7 | set ta_report_auto 1 8 | set ta_report_auto_constraints $ta_report_auto 9 | 10 | if { ! [info exists RESULT_DIR] } { 11 | set RESULT_DIR "." 12 | } elseif { ! [info exists alta_work] } { 13 | set alta_work "${RESULT_DIR}/alta_db" 14 | } 15 | if { ! [info exists DEVICE] } { 16 | set DEVICE "AG10KL144H" 17 | } 18 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 19 | set TOP_MODULE "$DESIGN" 20 | } 21 | if { ! [info exists DESIGN] } { 22 | set DESIGN "Blink" 23 | } 24 | if { ! [info exists TOP_MODULE] } { 25 | set TOP_MODULE "Blink" 26 | } 27 | if { ! [info exists IP_FILES] } { 28 | set IP_FILES {} 29 | } 30 | if { ! [info exists VE_FILE] } { 31 | set VE_FILE "" 32 | } 33 | if { ! [info exists TIMING_DERATE] } { 34 | set TIMING_DERATE 1.000000 35 | } 36 | if { [info exists NO_ROUTE] && $NO_ROUTE } { 37 | set no_route "-no_route" 38 | } else { 39 | set no_route "" 40 | } 41 | if { ! [info exists RETRY] } { set RETRY 0 } 42 | if { ! [info exists SEED ] } { set SEED 666 } 43 | set seed_rand "" 44 | if { $SEED == 0 } { set seed_rand "-seed_rand" } 45 | if { [info exists QUARTUS_SDC] } { 46 | set sdc_remove_quartus_column_name $QUARTUS_SDC 47 | } 48 | if { ! [info exists ORG_PLACE] } { set ORG_PLACE false } 49 | if { ! [info exists MODE] } { set MODE "QUARTUS" } 50 | if { ! [info exists FLOW] } { set FLOW "ALL" } 51 | if { $FLOW == "PROBE" } { 52 | if { ! [info exists PROBE_FORCE] } { set PROBE_FORCE false } 53 | if { ! [info exists PREFIX] } { set PREFIX "probe_" } 54 | } 55 | if { ! [info exists PREFIX] } { 56 | set RESULT $DESIGN 57 | } else { 58 | set RESULT $PREFIX$DESIGN 59 | } 60 | if { $FLOW == "GEN" || $FLOW == "PACK" || $FLOW == "LOAD" } { set no_route "-no_route" } 61 | set RUN "run" 62 | if { $FLOW == "CHECK" } { 63 | set RUN "check" 64 | } elseif { $FLOW == "PROBE" } { 65 | set RUN "probe" 66 | } elseif { $FLOW == "GEN" } { 67 | set RUN "gen" 68 | } 69 | 70 | if { ! [info exists alta_logs] } { 71 | set alta_logs "${RESULT_DIR}/alta_logs" 72 | } 73 | file mkdir $alta_logs 74 | alta::begin_log_cmd "$alta_logs/${RUN}.log" "$alta_logs/${RUN}.err" 75 | alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n" 76 | alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n" 77 | 78 | set_seed_rand $SEED 79 | set ar_timing_derate ${TIMING_DERATE} 80 | 81 | date_time 82 | if { [file exists "./${DESIGN}.pre.asf"] } { 83 | alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n" 84 | source "./${DESIGN}.pre.asf" 85 | } 86 | 87 | eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000" 88 | foreach ip_file $IP_FILES { read_ip $ip_file; } 89 | 90 | set LOAD_DB false 91 | set LOAD_PLACE false 92 | set LOAD_ROUTE false 93 | if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } { 94 | set LOAD_DB true 95 | set LOAD_PLACE true 96 | set LOAD_ROUTE true 97 | } elseif { $FLOW == "R" || $FLOW == "ROUTE" } { 98 | set LOAD_DB true 99 | set LOAD_PLACE true 100 | } 101 | 102 | set ORIGINAL_QSF "E:/echo/git/github/xjtuecho/AgmPill/hdl/Blink_EP4CE10/./Blink.qsf" 103 | set ORIGINAL_PIN "E:/echo/git/github/xjtuecho/AgmPill/hdl/Blink_EP4CE10/out/Blink.pin" 104 | 105 | ################################################################################# 106 | 107 | if { $FLOW == "GEN" } { 108 | if { ! [info exists CONFIG_BITS] } { 109 | set CONFIG_BITS "${RESULT_DIR}/${DESIGN}.bin" 110 | } 111 | if { [llength $CONFIG_BITS] > 1 } { 112 | if { ! [info exists BOOT_BINARY] } { 113 | set BOOT_BINARY "${RESULT_DIR}/${DESIGN}_boot.bin" 114 | } 115 | if { ! [info exists CONFIG_ADDRESSES] } { 116 | set CONFIG_ADDRESSES "" 117 | } 118 | generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES 119 | } else { 120 | set CONFIG_ROOT [file rootname [lindex $CONFIG_BITS 0]] 121 | set SLAVE_RBF "${CONFIG_ROOT}_slave.rbf" 122 | set MASTER_BINARY "${CONFIG_ROOT}_master.bin" 123 | if { [file exists [lindex $CONFIG_BITS 0]] } { 124 | generate_binary -slave $SLAVE_RBF -inputs [lindex $CONFIG_BITS 0] -reverse 125 | generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0] 126 | } 127 | if { ! [info exists BOOT_BINARY] } { 128 | set BOOT_BINARY $MASTER_BINARY 129 | } 130 | } 131 | set PRG_FILE [file rootname $BOOT_BINARY].prg 132 | set AS_FILE [file rootname $BOOT_BINARY]_as.prg 133 | generate_programming_file $BOOT_BINARY -erase $ERASE \ 134 | -program $PROGRAM -verify $VERIFY -offset $OFFSET \ 135 | -prg $PRG_FILE -as $AS_FILE 136 | exit 137 | } 138 | 139 | if { $LOAD_DB } { 140 | load_db -top ${TOP_MODULE} 141 | set sdc "./${DESIGN}.adc" 142 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 143 | if { [file exists $sdc] } { read_sdc $sdc; } 144 | 145 | } elseif { $MODE == "QUARTUS" } { 146 | set verilog ${DESIGN}.vo 147 | set is_migrated false 148 | if { ! [file exists $verilog] } { 149 | set verilog "E:/echo/git/github/xjtuecho/AgmPill/hdl/Blink_EP4CE10/simulation/modelsim/${DESIGN}.vo" 150 | set is_migrated true 151 | } 152 | if { ! [file exists $verilog] } { 153 | error "Can not find design verilog file $verilog" 154 | } 155 | alta::tcl_highlight "Using design verilog file $verilog.\n" 156 | set ret [read_design -top ${TOP_MODULE} -ve $VE_FILE -qsf $ORIGINAL_QSF $verilog -hierachy 1] 157 | if { !$ret } { exit -1; } 158 | 159 | set sdc "./${DESIGN}.adc" 160 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 161 | if { ! [file exists $sdc] } { 162 | alta::tcl_warn "Can not find design SDC file $sdc" 163 | } else { 164 | alta::tcl_highlight "Using design SDC file $sdc.\n" 165 | read_sdc $sdc 166 | } 167 | 168 | } elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { 169 | set db_gclk_assignment_level 2 170 | set verilog ${DESIGN}.vqm 171 | set is_migrated false 172 | if { ! [file exists $verilog] } { 173 | error "Can not find design verilog file $verilog" 174 | } 175 | 176 | set sdc "./${DESIGN}.adc" 177 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 178 | alta::tcl_highlight "Using design verilog file $verilog.\n" 179 | if { ! [file exists $sdc] } { 180 | alta::tcl_warn "Can not find design SDC file $sdc" 181 | set ret [read_design_and_pack -sdc $sdc -top ${TOP_MODULE} $verilog] 182 | } else { 183 | alta::tcl_highlight "Using design SDC file $sdc.\n" 184 | set ret [read_design_and_pack -top ${TOP_MODULE} $verilog] 185 | } 186 | if { !$ret } { exit -1; } 187 | 188 | } else { 189 | error "Unsupported mode $MODE" 190 | } 191 | 192 | if { $FLOW == "PACK" } { exit } 193 | 194 | if { [info exists FITTING] } { 195 | if { $FITTING == "Auto" } { set FITTING auto; } 196 | set_mode -fitting $FITTING 197 | } 198 | if { [info exists FITTER] } { 199 | if { $FITTER == "Auto" } { 200 | if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; } 201 | } 202 | if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; } 203 | set_mode -fitter $FITTER 204 | } 205 | if { [info exists EFFORT] } { set_mode -effort $EFFORT; } 206 | if { [info exists SKEW ] } { set_mode -skew $SKEW ; } 207 | if { [info exists SKOPE ] } { set_mode -skope $SKOPE ; } 208 | if { [info exists HOLDX ] } { set_mode -holdx $HOLDX; } 209 | if { [info exists TUNING] } { set_mode -tuning $TUNING; } 210 | if { [info exists TARGET] } { set_mode -target $TARGET; } 211 | if { [info exists PRESET] } { set_mode -preset $PRESET; } 212 | if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; } 213 | 214 | set alta_aqf $::alta_work/alta.aqf 215 | if { $LOAD_DB } { 216 | # Empty 217 | } elseif { true } { 218 | if { [file exists $VE_FILE] } { 219 | set ORIGINAL_PIN "" 220 | } elseif { ! [file exists $ORIGINAL_PIN] } { 221 | if { $is_migrated } { 222 | error "Can not find design PIN file $ORIGINAL_PIN, please compile design first" 223 | } 224 | set ORIGINAL_PIN "" 225 | } 226 | if { [file exists $ORIGINAL_QSF] } { 227 | alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf 228 | } elseif { $is_migrated } { 229 | error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first" 230 | } 231 | } 232 | if { [file exists "$alta_aqf"] } { 233 | alta::tcl_highlight "Using AQF file $alta_aqf.\n" 234 | source "$alta_aqf" 235 | } 236 | if { [file exists "./${DESIGN}.asf"] } { 237 | alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n" 238 | source "./${DESIGN}.asf" 239 | } 240 | 241 | if { $FLOW == "PROBE" } { 242 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 243 | if { !$ret } { exit -1 } 244 | 245 | set force "" 246 | if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" } 247 | eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}" 248 | 249 | } elseif { $FLOW == "CHECK" } { 250 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 251 | if { !$ret } { exit -1 } 252 | 253 | if { [file exists "./${DESIGN}.chk"] } { 254 | alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n" 255 | source "./${DESIGN}.chk" 256 | place_design -dry 257 | check_design -rule led_guide 258 | } else { 259 | error "Can not find design CHECK file ${DESIGN}.chk" 260 | } 261 | 262 | } else { 263 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io] 264 | if { !$ret } { exit -1 } 265 | 266 | set org_place "" 267 | set load_place "" 268 | set load_route "" 269 | set quiet "" 270 | if { $ORG_PLACE } { set org_place "-org_place" ; } 271 | if { $LOAD_PLACE } { set load_place "-load_place"; } 272 | if { $LOAD_ROUTE } { set load_route "-load_route"; } 273 | eval "place_and_route_design $org_place $load_place $load_route \ 274 | -retry $RETRY $seed_rand $quiet" 275 | } 276 | 277 | date_time 278 | if { $FLOW != "CHECK" } { 279 | if { $FLOW != "PROBE" } { 280 | #report_timing -verbose 1 -file $::alta_work/timing.rpt.gz 281 | report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz 282 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz 283 | report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz 284 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz 285 | 286 | set ta_report_auto_constraints 0 287 | report_timing -fmax -file $::alta_work/fmax.rpt 288 | report_timing -xfer -file $::alta_work/xfer.rpt 289 | set ta_report_auto_constraints $ta_report_auto 290 | 291 | #set ta_coverage_limit "0.95 0.90" 292 | set ta_dump_uncovered 1 293 | report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz 294 | #unset ta_coverage_limit 295 | unset ta_dump_uncovered 296 | 297 | 298 | if { ! [info exists rt_report_timing_fast] } { 299 | set rt_report_timing_fast false 300 | } 301 | if { $rt_report_timing_fast } { 302 | set_timing_corner fast 303 | route_delay -quiet 304 | report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz 305 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_fast_summary.rpt.gz 306 | report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz 307 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_fast_summary.rpt.gz 308 | set ta_report_auto_constraints 0 309 | report_timing -fmax -file $::alta_work/fmax_fast.rpt 310 | report_timing -xfer -file $::alta_work/xfer_fast.rpt 311 | set ta_report_auto_constraints $ta_report_auto 312 | } 313 | 314 | write_routed_design "${RESULT_DIR}/${RESULT}_routed.v" 315 | } 316 | 317 | bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin" 318 | bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg" 319 | bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf" 320 | generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \ 321 | -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse 322 | generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \ 323 | -inputs "${RESULT_DIR}/${RESULT}.bin" 324 | generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \ 325 | -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg" 326 | } 327 | 328 | if { [file exists "./${DESIGN}.post.asf"] } { 329 | alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n" 330 | source "./${DESIGN}.post.asf" 331 | } 332 | date_time 333 | exit 334 | 335 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.asf: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_13 -to CLK 2 | set_location_assignment PIN_12 -to KEY[1] 3 | set_location_assignment PIN_5 -to KEY[2] 4 | set_location_assignment PIN_6 -to LED[1] 5 | set_location_assignment PIN_9 -to LED[2] 6 | set_location_assignment PIN_1 -to CLKO[0] 7 | set_location_assignment PIN_2 -to CLKO[1] 8 | set_location_assignment PIN_3 -to CLKO[2] 9 | set_location_assignment PIN_4 -to BENCH_OUT 10 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.post.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG1280/Blink_AG1280.post.asf -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.pre.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG1280/Blink_AG1280.pre.asf -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.proj: -------------------------------------------------------------------------------- 1 | [GuiMigrateSetupPage] 2 | fromDir= 3 | design=Blink_AG1280 4 | device=AG1280Q48 5 | veFile= 6 | ipFiles=PLL.ip 7 | backwardCompatible=false 8 | modeGroup=false 9 | modeQuartus=true 10 | modeSynplicity=false 11 | modeNative=false 12 | 13 | [GuiMigrateRunPage] 14 | isMC=false 15 | count= 16 | jobs= 17 | seed= 18 | retry=0 19 | fitting=6 20 | fitter=4 21 | effort=3 22 | holdx=0 23 | skew=2 24 | skope=0 25 | preset=0 26 | adjust=0 27 | target=0 28 | tuning=0 29 | flow=0 30 | orgPlace=false 31 | quartusSdc=true 32 | probeForce=false 33 | probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2m\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xab\0\0\0\x1\0\0\0\0) 34 | probeCount=5 35 | probe0From= 36 | probe0Pad= 37 | probe1From= 38 | probe1Pad= 39 | probe2From= 40 | probe2Pad= 41 | probe3From= 42 | probe3Pad= 43 | probe4From= 44 | probe4Pad= 45 | 46 | [MainWindow] 47 | recentFile.0= 48 | 49 | [GuiIpPllScreen] 50 | module=PLL 51 | inputFreq=24 52 | type=1 53 | fbMode=0 54 | compMode=0 55 | output=1 56 | useDiff=false 57 | useExt=false 58 | output0Freq=24 59 | output0Phase= 60 | output0Duty= 61 | output1Freq=50 62 | output1Phase= 63 | output1Duty= 64 | output2Freq= 65 | output2Phase= 66 | output2Duty= 67 | output3Freq= 68 | output3Phase= 69 | output3Duty= 70 | output4Freq= 71 | output4Phase= 72 | output4Duty= 73 | output5Freq= 74 | output5Phase= 75 | output5Duty= 76 | output6Freq= 77 | output6Phase= 78 | output6Duty= 79 | output7Freq= 80 | output7Phase= 81 | output7Duty= 82 | output8Freq= 83 | output8Phase= 84 | output8Duty= 85 | output9Freq= 86 | output9Phase= 87 | output9Duty= 88 | output10Freq= 89 | output10Phase= 90 | output10Duty= 91 | output11Freq= 92 | output11Phase= 93 | output11Duty= 94 | output12Freq= 95 | output12Phase= 96 | output12Duty= 97 | output13Freq= 98 | output13Phase= 99 | output13Duty= 100 | output14Freq= 101 | output14Phase= 102 | output14Duty= 103 | output15Freq= 104 | output15Phase= 105 | output15Duty= 106 | output16Freq= 107 | output16Phase= 108 | output16Duty= 109 | output17Freq= 110 | output17Phase= 111 | output17Duty= 112 | output18Freq= 113 | output18Phase= 114 | output18Duty= 115 | output19Freq= 116 | output19Phase= 117 | output19Duty= 118 | output20Freq= 119 | output20Phase= 120 | output20Duty= 121 | output21Freq= 122 | output21Phase= 123 | output21Duty= 124 | output22Freq= 125 | output22Phase= 126 | output22Duty= 127 | output23Freq= 128 | output23Phase= 129 | output23Duty= 130 | output24Freq= 131 | output24Phase= 132 | output24Duty= 133 | output25Freq= 134 | output25Phase= 135 | output25Duty= 136 | output26Freq= 137 | output26Phase= 138 | output26Duty= 139 | output27Freq= 140 | output27Phase= 141 | output27Duty= 142 | output28Freq= 143 | output28Phase= 144 | output28Duty= 145 | output29Freq= 146 | output29Phase= 147 | output29Duty= 148 | output30Freq= 149 | output30Phase= 150 | output30Duty= 151 | output31Freq= 152 | output31Phase= 153 | output31Duty= 154 | 155 | [GuiRuleChkScreen] 156 | spiGroup=false 157 | phyGroup=false 158 | sdramGroup=false 159 | criticalInput= 160 | criticalOutput= 161 | spiSpi= 162 | phyOut= 163 | phyOCtrl= 164 | phyOClk= 165 | phyIn= 166 | phyICtrl= 167 | phyIClk= 168 | sdramMethod1=true 169 | sdramMethod2=false 170 | sdramData= 171 | sdramAddr= 172 | sdramCtrl= 173 | sdramClk= 174 | sdramClock= 175 | 176 | [GuiProgramScreen] 177 | hardwareId=0 178 | prgFile=Blink_AG1280_hybrid.prg 179 | eraseBox=false 180 | cable=UsbBlaster 181 | runAction=program 182 | eraseChip=true 183 | eraseFrom= 184 | eraseTo= 185 | binFile= 186 | readFrom= 187 | readTo= 188 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.qpf: -------------------------------------------------------------------------------- 1 | #QUARTUS_VERSION = "11.1" 2 | PROJECT_REVISION = "Blink_AG1280" 3 | 4 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version 21 | # Date created = 07:52:06 October 18, 2022 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Blink_AG1280_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | 40 | # Project-Wide Assignments 41 | # ======================== 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:37:04 JANUARY 04, 2013" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ./quartus_logs 46 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 47 | set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON 48 | set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON 49 | set_global_assignment -name VERILOG_FILE common/PowerOnReset.v 50 | set_global_assignment -name VERILOG_FILE common/DFFx2.v 51 | set_global_assignment -name VERILOG_FILE common/clkdivider.v 52 | set_global_assignment -name VERILOG_FILE .\\Blink_AG1280.v 53 | set_global_assignment -name VERILOG_FILE "D:\\EE\\FPGA\\AGM\\Supra-2022.06.b0-454528eb-win64-all\\etc\\arch\\rodinia\\alta_sim.v" 54 | set_global_assignment -name SDC_FILE .\\Blink_AG1280.sdc 55 | set_global_assignment -name SDC_FILE .\\Blink_AG1280_derate.sdc 56 | 57 | # Classic Timing Assignments 58 | # ========================== 59 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 60 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 61 | 62 | # Analysis & Synthesis Assignments 63 | # ================================ 64 | set_global_assignment -name TOP_LEVEL_ENTITY Blink_AG1280 65 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON 66 | set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON 67 | set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF 68 | set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0 69 | set_global_assignment -name MAX_RAM_BLOCKS_M4K 0 70 | set_global_assignment -name AUTO_ROM_RECOGNITION OFF 71 | set_global_assignment -name AUTO_RAM_RECOGNITION OFF 72 | set_global_assignment -name FAMILY "Cyclone IV E" 73 | 74 | # Fitter Assignments 75 | # ================== 76 | set_global_assignment -name DEVICE EP4CE75F29C8 77 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 78 | set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF 79 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" 80 | set_global_assignment -name FITTER_EFFORT "STANDARD FIT" 81 | set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM 82 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10 83 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10 84 | set_global_assignment -name ECO_OPTIMIZE_TIMING ON 85 | set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS 86 | set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS 87 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 88 | set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON 89 | set_global_assignment -name SEED 1 90 | set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF 91 | set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED 8 92 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON 93 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON 94 | set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA 95 | 96 | # EDA Netlist Writer Assignments 97 | # ============================== 98 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" 99 | 100 | # LogicLock Region Assignments 101 | # ============================ 102 | set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF 103 | 104 | # Power Estimation Assignments 105 | # ============================ 106 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 107 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 108 | 109 | # start EDA_TOOL_SETTINGS(eda_simulation) 110 | # --------------------------------------- 111 | 112 | # EDA Netlist Writer Assignments 113 | # ============================== 114 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 115 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 116 | set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation 117 | 118 | # end EDA_TOOL_SETTINGS(eda_simulation) 119 | # ------------------------------------- 120 | 121 | # -------------------------- 122 | # start ENTITY(Blink_AG1280) 123 | 124 | # start LOGICLOCK_REGION(core_logic) 125 | # ---------------------------------- 126 | 127 | # LogicLock Region Assignments 128 | # ============================ 129 | set_global_assignment -name LL_ENABLED ON -section_id core_logic 130 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id core_logic 131 | set_global_assignment -name LL_STATE LOCKED -section_id core_logic 132 | set_global_assignment -name LL_RESERVED OFF -section_id core_logic 133 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id core_logic 134 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id core_logic 135 | set_global_assignment -name LL_PR_REGION OFF -section_id core_logic 136 | set_global_assignment -name LL_WIDTH 13 -section_id core_logic 137 | set_global_assignment -name LL_HEIGHT 8 -section_id core_logic 138 | set_global_assignment -name LL_ORIGIN X1_Y1 -section_id core_logic 139 | set_global_assignment -name LL_MEMBER_OF core_logic -section_id core_logic 140 | 141 | # end LOGICLOCK_REGION(core_logic) 142 | # -------------------------------- 143 | 144 | # start LOGICLOCK_REGION(LOGIC_RESERVE_0) 145 | # --------------------------------------- 146 | 147 | # LogicLock Region Assignments 148 | # ============================ 149 | set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_0 150 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_0 151 | set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_0 152 | set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_0 153 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_0 154 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_0 155 | set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_0 156 | set_global_assignment -name LL_WIDTH 9 -section_id LOGIC_RESERVE_0 157 | set_global_assignment -name LL_HEIGHT 1 -section_id LOGIC_RESERVE_0 158 | set_global_assignment -name LL_ORIGIN X1_Y1 -section_id LOGIC_RESERVE_0 159 | 160 | # end LOGICLOCK_REGION(LOGIC_RESERVE_0) 161 | # ------------------------------------- 162 | 163 | # start LOGICLOCK_REGION(LOGIC_RESERVE_1) 164 | # --------------------------------------- 165 | 166 | # LogicLock Region Assignments 167 | # ============================ 168 | set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_1 169 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_1 170 | set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_1 171 | set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_1 172 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_1 173 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_1 174 | set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_1 175 | set_global_assignment -name LL_WIDTH 1 -section_id LOGIC_RESERVE_1 176 | set_global_assignment -name LL_HEIGHT 7 -section_id LOGIC_RESERVE_1 177 | set_global_assignment -name LL_ORIGIN X4_Y2 -section_id LOGIC_RESERVE_1 178 | 179 | # end LOGICLOCK_REGION(LOGIC_RESERVE_1) 180 | # ------------------------------------- 181 | 182 | # start LOGICLOCK_REGION(LOGIC_RESERVE_2) 183 | # --------------------------------------- 184 | 185 | # LogicLock Region Assignments 186 | # ============================ 187 | set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_2 188 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_2 189 | set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_2 190 | set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_2 191 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_2 192 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_2 193 | set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_2 194 | set_global_assignment -name LL_WIDTH 1 -section_id LOGIC_RESERVE_2 195 | set_global_assignment -name LL_HEIGHT 8 -section_id LOGIC_RESERVE_2 196 | set_global_assignment -name LL_ORIGIN X11_Y1 -section_id LOGIC_RESERVE_2 197 | 198 | # end LOGICLOCK_REGION(LOGIC_RESERVE_2) 199 | # ------------------------------------- 200 | 201 | # start DESIGN_PARTITION(Top) 202 | # --------------------------- 203 | 204 | # Incremental Compilation Assignments 205 | # =================================== 206 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 207 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 208 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 209 | 210 | # end DESIGN_PARTITION(Top) 211 | # ------------------------- 212 | 213 | # start DESIGN_PARTITION(p0_PLL_C9CB26FA) 214 | # --------------------------------------- 215 | 216 | # Incremental Compilation Assignments 217 | # =================================== 218 | set_global_assignment -name PARTITION_COLOR 52377 -section_id p0_PLL_C9CB26FA -tag alta_auto 219 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id p0_PLL_C9CB26FA -tag alta_auto 220 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id p0_PLL_C9CB26FA -tag alta_auto 221 | 222 | # end DESIGN_PARTITION(p0_PLL_C9CB26FA) 223 | # ------------------------------------- 224 | 225 | # end ENTITY(Blink_AG1280) 226 | # ------------------------ 227 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 228 | set_instance_assignment -name PARTITION_HIERARCHY p0_PLL_C9CB26FA -to "PLL:p0|alta_pllx:PLL_C9CB26FA" -section_id p0_PLL_C9CB26FA -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.sdc: -------------------------------------------------------------------------------- 1 | derive_pll_clocks -create_base_clocks 2 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/Blink_AG1280.v: -------------------------------------------------------------------------------- 1 | module Blink_AG1280( 2 | input CLK, 3 | 4 | input [2:1] KEY, 5 | output [2:1] LED, 6 | 7 | // Test Output 8 | output [2:0] CLKO, 9 | output BENCH_OUT 10 | ); 11 | 12 | wire locked, por; 13 | wire nRst = KEY[2] & locked | por; 14 | PowerOnReset por0(.iCLK(CLK), .oRESET(por)); 15 | wire CLK_24M, CLK_50M; 16 | PLL p0( 17 | .clkin(CLK), 18 | .clkfb(CLK_24M), 19 | .pllen(1'b1), 20 | .resetn(1'b1), 21 | .clkout0en(1'b1), 22 | .clkout1en(1'b1), 23 | .clkout2en(1'b0), 24 | .clkout3en(1'b0), 25 | .clkout0(CLK_24M), 26 | .clkout1(CLK_50M), 27 | .clkout2(), 28 | .clkout3(), 29 | .lock(locked)); 30 | 31 | wire CLK_1M, CLK_1k, CLK_1Hz; 32 | clkdivider #(.CNT_MAX(16'd50)) c0 (.clk(CLK_50M), .nRST(nRst), .clkout(CLK_1M)); 33 | clkdivider #(.CNT_MAX(16'd1000)) c1 (.clk(CLK_1M), .nRST(nRst), .clkout(CLK_1k)); 34 | clkdivider #(.CNT_MAX(16'd1000)) c2 (.clk(CLK_1k), .nRST(nRst), .clkout(CLK_1Hz)); 35 | 36 | assign CLKO[0] = CLK_1M; 37 | assign CLKO[1] = CLK_1k; 38 | assign CLKO[2] = CLK_1Hz; 39 | assign BENCH_OUT = CLK_1M; 40 | 41 | assign LED[1] = CLK_1Hz; 42 | assign LED[2] = ~KEY[1]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/PLL.ip: -------------------------------------------------------------------------------- 1 | IP PLL_C9CB26FA 2 | TYPE : alta_pllx; 3 | PARAMETER 4 | CLKIN_DIV : 6'h01 BITS; 5 | CLKFB_DIV : 6'h01 BITS; 6 | CLKDIV0_EN : 1'h1 BITS; 7 | CLKOUT0_DIV : 6'h18 BITS; 8 | CLKOUT0_DEL : 6'h00 BITS; 9 | CLKOUT0_PHASE : 3'h0 BITS; 10 | CLKDIV1_EN : 1'h1 BITS; 11 | CLKOUT1_DIV : 6'h0B BITS; 12 | CLKOUT1_DEL : 6'h00 BITS; 13 | CLKOUT1_PHASE : 3'h0 BITS; 14 | CLKDIV2_EN : 1'h0 BITS; 15 | CLKOUT2_DIV : 6'h3F BITS; 16 | CLKOUT2_DEL : 6'h00 BITS; 17 | CLKOUT2_PHASE : 3'h0 BITS; 18 | CLKDIV3_EN : 1'h0 BITS; 19 | CLKOUT3_DIV : 6'h3F BITS; 20 | CLKOUT3_DEL : 6'h00 BITS; 21 | CLKOUT3_PHASE : 3'h0 BITS; 22 | FEEDBACK_MODE : 1'b1 BITS; 23 | FEEDBACK_CLOCK : 2'b00 BITS; 24 | END_PARAMETER 25 | END_IP 26 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/PLL.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module PLL( 3 | input clkin, 4 | input clkfb, 5 | input pllen, 6 | input resetn, 7 | input clkout0en, 8 | input clkout1en, 9 | input clkout2en, 10 | input clkout3en, 11 | output clkout0, 12 | output clkout1, 13 | output clkout2, 14 | output clkout3, 15 | output lock 16 | ); 17 | 18 | 19 | alta_pllx PLL_C9CB26FA( 20 | .clkin(clkin), 21 | .clkfb(clkfb), 22 | .pllen(pllen), 23 | .resetn(resetn), 24 | .clkout0en(clkout0en), 25 | .clkout1en(clkout1en), 26 | .clkout2en(clkout2en), 27 | .clkout3en(clkout3en), 28 | .clkout0(PLL_clkout0), 29 | .clkout1(PLL_clkout1), 30 | .clkout2(PLL_clkout2), 31 | .clkout3(PLL_clkout3), 32 | .lock(PLL_lock) 33 | ); 34 | defparam PLL_C9CB26FA.CLKIN_DIV = 6'h01; 35 | defparam PLL_C9CB26FA.CLKFB_DIV = 6'h01; 36 | defparam PLL_C9CB26FA.CLKDIV0_EN = 1'h1; 37 | defparam PLL_C9CB26FA.CLKOUT0_DIV = 6'h18; 38 | defparam PLL_C9CB26FA.CLKOUT0_DEL = 6'h00; 39 | defparam PLL_C9CB26FA.CLKOUT0_PHASE = 3'h0; 40 | defparam PLL_C9CB26FA.CLKDIV1_EN = 1'h1; 41 | defparam PLL_C9CB26FA.CLKOUT1_DIV = 6'h0B; 42 | defparam PLL_C9CB26FA.CLKOUT1_DEL = 6'h00; 43 | defparam PLL_C9CB26FA.CLKOUT1_PHASE = 3'h0; 44 | defparam PLL_C9CB26FA.CLKDIV2_EN = 1'h0; 45 | defparam PLL_C9CB26FA.CLKOUT2_DIV = 6'h3F; 46 | defparam PLL_C9CB26FA.CLKOUT2_DEL = 6'h00; 47 | defparam PLL_C9CB26FA.CLKOUT2_PHASE = 3'h0; 48 | defparam PLL_C9CB26FA.CLKDIV3_EN = 1'h0; 49 | defparam PLL_C9CB26FA.CLKOUT3_DIV = 6'h3F; 50 | defparam PLL_C9CB26FA.CLKOUT3_DEL = 6'h00; 51 | defparam PLL_C9CB26FA.CLKOUT3_PHASE = 3'h0; 52 | defparam PLL_C9CB26FA.FEEDBACK_MODE = 1'b1; 53 | defparam PLL_C9CB26FA.FEEDBACK_CLOCK = 2'b00; 54 | 55 | assign clkout0 = PLL_clkout0; 56 | assign clkout1 = PLL_clkout1; 57 | assign clkout2 = PLL_clkout2; 58 | assign clkout3 = PLL_clkout3; 59 | assign lock = PLL_lock; 60 | 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/af_batch.tcl: -------------------------------------------------------------------------------- 1 | if {![info exist MODE ]} {set MODE QUARTUS} 2 | if {![info exists QUARTUS_SDC]} {set QUARTUS_SDC true} 3 | if {![info exist COUNT]} {set COUNT 6} 4 | if {![info exist JOBS ]} {set JOBS 1} 5 | 6 | if {![info exist SEEDS ]} {set SEEDS {0 0 0 0 666 888 }} 7 | if {![info exist EFFORTS ]} {set EFFORTS {highest highest highest highest high high }} 8 | if {![info exist FITTERS ]} {set FITTERS {hybrid hybrid hybrid hybrid hybrid hybrid }} 9 | if {![info exist FITTINGS]} {set FITTINGS {timing_more timing_more timing_more timing timing basic }} 10 | if {![info exist SKEWS ]} {set SKEWS {advanced advanced advanced advanced aggressive basic }} 11 | if {![info exist HOLDXS ]} {set HOLDXS {default default default default default default}} 12 | 13 | set bc_config "./bc_config.txt" 14 | if { [file exists $bc_config] } { 15 | alta::tcl_highlight "Using MC config $bc_config.\n" 16 | source "$bc_config" 17 | } 18 | 19 | ####################################################################### 20 | 21 | proc get_rand_value { values } { 22 | if {[llength $values] == 0} { return {} } 23 | return [lindex $values [expr {int(rand()*10000)%[llength $values]}]] 24 | } 25 | 26 | set results "bc_results" 27 | set summary "bc_summary.txt" 28 | file delete -force $results; file mkdir $results 29 | file delete $summary; print -nonewline "" >! $summary 30 | 31 | set is_parallel [expr $JOBS > 1] 32 | set is_color ""; set is_gui ""; set is_quiet "" 33 | if { $is_parallel } { 34 | set is_gui "--quiet" 35 | } else { 36 | if { [alta::tcl_is_color] } { set is_color "--color" } 37 | if { [alta::tcl_is_gui ] } { set is_gui "--gui" } 38 | } 39 | 40 | ####################################################################### 41 | 42 | set progs {} 43 | set titles {} 44 | for {set id 1} {$id <= $COUNT} {incr id} { 45 | set result_dir "$results/$id" 46 | file mkdir $result_dir 47 | 48 | set seed [get_rand_value $SEEDS ] 49 | set effort [get_rand_value $EFFORTS ] 50 | set skew [get_rand_value $SKEWS ] 51 | set fitter [get_rand_value $FITTERS ] 52 | set fitting [get_rand_value $FITTINGS] 53 | set holdx [get_rand_value $HOLDXS ] 54 | 55 | set prog [list [info nameofexec] $is_quiet $is_color $is_gui -B --batch --mode $MODE] 56 | alta::lconcat prog [list -X "set QUARTUS_SDC $QUARTUS_SDC"] 57 | alta::lconcat prog [list -X "set RESULT_DIR $result_dir"] 58 | if { $seed != "" } { 59 | alta::lconcat prog [list -X "set SEED $seed"] 60 | } 61 | if { $effort != "" } { 62 | alta::lconcat prog [list -X "set EFFORT $effort"] 63 | } 64 | if { $fitter != "" } { 65 | alta::lconcat prog [list -X "set FITTER $fitter"] 66 | } 67 | if { $fitting != "" } { 68 | alta::lconcat prog [list -X "set FITTING $fitting"] 69 | } 70 | if { $skew != "" } { 71 | alta::lconcat prog [list -X "set SKEW $skew"] 72 | } 73 | if { $holdx != "" } { 74 | alta::lconcat prog [list -X "set HOLDX $holdx"] 75 | } 76 | #alta::lconcat prog [list -F af_run.tcl] 77 | lappend progs $prog 78 | lappend titles "#$id $result_dir" 79 | } 80 | 81 | ####################################################################### 82 | 83 | if { $is_parallel } { 84 | set bg_progs {} 85 | foreach bg_prog $progs { 86 | lappend bg_progs [lappend bg_prog $is_quiet] 87 | } 88 | bg_exec_queue $titles $bg_progs $JOBS 89 | } 90 | 91 | ####################################################################### 92 | 93 | for {set id 1} {$id <= $COUNT} {incr id} { 94 | set result_dir "$results/$id" 95 | set prog [lindex $progs [expr $id-1]] 96 | set title [lindex $titles [expr $id-1]] 97 | if { ! $is_parallel } { 98 | puts $title 99 | puts $prog 100 | eval exec -ignorestderr $prog >&@ stdout 101 | } 102 | 103 | print "***************************************************************************\n" >> $summary 104 | print "$title\n" >> $summary 105 | cat "$result_dir/alta_db/fmax.rpt" >> $summary 106 | cat "$result_dir/alta_db/xfer.rpt" >> $summary 107 | print "" >> $summary 108 | } 109 | 110 | alta::tcl_highlight "Check $summary for result.\n" 111 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/af_ip.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set DESIGN "Blink_AG1280" 3 | set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp } 4 | lappend IPLIST alta_rv32 5 | 6 | proc set_alta_partition {inst tag} { 7 | set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst] 8 | set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst] 9 | set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst] 10 | set section_id [string map { [ _ ] _ . _ | _} $inst_name] 11 | eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag" 12 | eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag" 13 | eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag" 14 | eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag" 15 | } 16 | 17 | load_package flow 18 | if { $DESIGN == "" } { 19 | set DESIGN $::quartus(args) 20 | } 21 | project_open $DESIGN 22 | 23 | set tag alta_auto 24 | if { [llength $IPLIST] > 0 } { 25 | # A Quartus bug saves PARTITION_HIERARCHY assignments without tag. Use section_id to remove them. 26 | set asgn_col [get_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag] 27 | foreach_in_collection part $asgn_col { 28 | set section_id [lindex $part 0] 29 | eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -section_id $section_id" 30 | } 31 | eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag" 32 | eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag" 33 | eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag" 34 | catch { execute_module -tool map } 35 | 36 | foreach ip $IPLIST { 37 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] { 38 | set_alta_partition $inst $tag 39 | } 40 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] { 41 | set_alta_partition $inst $tag 42 | } 43 | } 44 | } 45 | eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation" 46 | 47 | project_close 48 | 49 | exit 50 | 51 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/af_map.tcl: -------------------------------------------------------------------------------- 1 | map -import 2 | 3 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 4 | set TOP_MODULE "$DESIGN" 5 | } 6 | if { ! [info exists DESIGN] } { 7 | set DESIGN "Blink_AG1280" 8 | } 9 | if { ! [info exists TOP_MODULE] } { 10 | set TOP_MODULE "Blink_AG1280" 11 | } 12 | 13 | set verilogs { .\\Blink_AG1280.v } 14 | if { [ llength $verilogs ] == 0 } { 15 | set verilogs "./${DESIGN}.v" 16 | } 17 | foreach verilog $verilogs { 18 | read_verilog "$verilog" 19 | } 20 | 21 | read_verilog -sv -lib +/agm/rodina/cells_sim.v 22 | read_verilog -sv -lib +/agm/common/m9k_bb.v 23 | read_verilog -sv -lib +/agm/common/altpll_bb.v 24 | hierarchy -check -top ${TOP_MODULE} 25 | 26 | synth -run coarse -top ${DESIGN} 27 | 28 | map proc 29 | opt_expr 30 | opt_clean 31 | check 32 | opt 33 | 34 | wreduce 35 | alumacc 36 | share 37 | opt 38 | fsm 39 | opt -fast 40 | memory -nomap 41 | opt_clean 42 | 43 | memory_bram -rules +/agm/common/brams.txt 44 | techmap -map +/agm/common/brams_map.v 45 | 46 | opt -fast -mux_undef -undriven -fine -full 47 | memory_map 48 | opt -undriven -fine 49 | 50 | techmap -autoproc -map +/techmap.v -map +/agm/rodina/arith_map.v 51 | dffsr2dff 52 | dff2dffe -direct-match \$_DFF_* 53 | opt -full 54 | 55 | techmap -map +/agm/rodina/cells_map.v 56 | agm_dffeas 57 | opt -full 58 | 59 | clean -purge 60 | setundef -undriven -zero 61 | abc -markgroups -dff 62 | opt_expr -mux_undef -undriven -full 63 | opt_merge 64 | opt_rmdff 65 | opt_clean 66 | 67 | abc -lut 4 68 | clean 69 | 70 | techmap -map +/agm/rodina/cells_map.v 71 | dffinit -ff dffeas Q INIT 72 | clean -purge 73 | 74 | hierarchy -check 75 | check -noinit 76 | 77 | write_verilog -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm 78 | # exec sed -i "/\\\\\\\$paramod/s/\[$=\\]/_/g" ${DESIGN}.vqm 79 | 80 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/af_quartus.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set RETRY 0 3 | set DESIGN "Blink_AG1280" 4 | 5 | if { [is_project_open] } { 6 | export_assignments 7 | } 8 | 9 | set is_compatible false 10 | if { $is_compatible } { 11 | cd 12 | qexec "[file join $::quartus(binpath) quartus_eda] $DESIGN --simulation --tool=modelsim --format=verilog" 13 | } else { 14 | set FITTER_EFFORTS {"STANDARD FIT" "STANDARD FIT" "FAST FIT" "FAST FIT" "FAST FIT"} 15 | set SEEDS [list [expr int(rand()*100)] \ 16 | [expr int(rand()*100)] \ 17 | [expr int(rand()*100)] \ 18 | [expr int(rand()*100)] \ 19 | [expr int(rand()*100)]] 20 | set PLACEMENT_EFFORTS [list [expr rand()*5+0.1] \ 21 | [expr rand()*5+0.1] \ 22 | [expr rand()*5+0.1] \ 23 | [expr rand()*5+0.1] \ 24 | [expr rand()*5+0.1]] 25 | set ROUTER_EFFORTS [list [expr rand()*5+0.25] \ 26 | [expr rand()*5+0.25] \ 27 | [expr rand()*5+0.25] \ 28 | [expr rand()*5+0.25] \ 29 | [expr rand()*5+0.25]] 30 | 31 | qexec "[file join $::quartus(binpath) quartus_sh] -t af_ip.tcl" 32 | 33 | load_package flow 34 | project_open $DESIGN 35 | 36 | set RETRY [expr $RETRY<[llength $FITTER_EFFORTS]?$RETRY:[llength $FITTER_EFFORTS]] 37 | for {set nn -1} {$nn < $RETRY} {incr nn} { 38 | if {$nn >= 0} { 39 | set_global_assignment -name FITTER_EFFORT \"[lindex $FITTER_EFFORTS $nn]\" 40 | set_global_assignment -name SEED [lindex $SEEDS $nn] 41 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER [lindex $PLACEMENT_EFFORTS $nn] 42 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER [lindex $ROUTER_EFFORTS $nn] 43 | } 44 | 45 | set code [catch {execute_flow -compile} msg] 46 | if { $code == 0 } { break } 47 | } 48 | } 49 | 50 | 51 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/af_run.tcl: -------------------------------------------------------------------------------- 1 | set ALTA_SUPRA true 2 | set sh_continue_on_error false 3 | set sh_echo_on_source true 4 | set sh_quiet_on_source true 5 | set cc_critical_as_fatal true 6 | set rt_incremental_route true 7 | set ta_report_auto 1 8 | set ta_report_auto_constraints $ta_report_auto 9 | 10 | if { ! [info exists RESULT_DIR] } { 11 | set RESULT_DIR "." 12 | } elseif { ! [info exists alta_work] } { 13 | set alta_work "${RESULT_DIR}/alta_db" 14 | } 15 | if { ! [info exists DEVICE] } { 16 | set DEVICE "AG1280Q48" 17 | } 18 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 19 | set TOP_MODULE "$DESIGN" 20 | } 21 | if { ! [info exists DESIGN] } { 22 | set DESIGN "Blink_AG1280" 23 | } 24 | if { ! [info exists TOP_MODULE] } { 25 | set TOP_MODULE "Blink_AG1280" 26 | } 27 | if { ! [info exists IP_FILES] } { 28 | set IP_FILES {"E:/echo/git/github/xjtuecho/AgmPill/hdl/Blink_AG1280/PLL.ip" } 29 | } 30 | if { ! [info exists VE_FILE] } { 31 | set VE_FILE "" 32 | } 33 | if { ! [info exists TIMING_DERATE] } { 34 | set TIMING_DERATE 1.000000 35 | } 36 | if { [info exists NO_ROUTE] && $NO_ROUTE } { 37 | set no_route "-no_route" 38 | } else { 39 | set no_route "" 40 | } 41 | if { ! [info exists RETRY] } { set RETRY 0 } 42 | if { ! [info exists SEED ] } { set SEED 666 } 43 | set seed_rand "" 44 | if { $SEED == 0 } { set seed_rand "-seed_rand" } 45 | if { [info exists QUARTUS_SDC] } { 46 | set sdc_remove_quartus_column_name $QUARTUS_SDC 47 | } 48 | if { ! [info exists ORG_PLACE] } { set ORG_PLACE false } 49 | if { ! [info exists MODE] } { set MODE "QUARTUS" } 50 | if { ! [info exists FLOW] } { set FLOW "ALL" } 51 | if { $FLOW == "PROBE" } { 52 | if { ! [info exists PROBE_FORCE] } { set PROBE_FORCE false } 53 | if { ! [info exists PREFIX] } { set PREFIX "probe_" } 54 | } 55 | if { ! [info exists PREFIX] } { 56 | set RESULT $DESIGN 57 | } else { 58 | set RESULT $PREFIX$DESIGN 59 | } 60 | if { $FLOW == "GEN" || $FLOW == "PACK" || $FLOW == "LOAD" } { set no_route "-no_route" } 61 | set RUN "run" 62 | if { $FLOW == "CHECK" } { 63 | set RUN "check" 64 | } elseif { $FLOW == "PROBE" } { 65 | set RUN "probe" 66 | } elseif { $FLOW == "GEN" } { 67 | set RUN "gen" 68 | } 69 | 70 | if { ! [info exists alta_logs] } { 71 | set alta_logs "${RESULT_DIR}/alta_logs" 72 | } 73 | file mkdir $alta_logs 74 | alta::begin_log_cmd "$alta_logs/${RUN}.log" "$alta_logs/${RUN}.err" 75 | alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n" 76 | alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n" 77 | 78 | set_seed_rand $SEED 79 | set ar_timing_derate ${TIMING_DERATE} 80 | 81 | date_time 82 | if { [file exists "./${DESIGN}.pre.asf"] } { 83 | alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n" 84 | source "./${DESIGN}.pre.asf" 85 | } 86 | 87 | eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000" 88 | foreach ip_file $IP_FILES { read_ip $ip_file; } 89 | 90 | set LOAD_DB false 91 | set LOAD_PLACE false 92 | set LOAD_ROUTE false 93 | if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } { 94 | set LOAD_DB true 95 | set LOAD_PLACE true 96 | set LOAD_ROUTE true 97 | } elseif { $FLOW == "R" || $FLOW == "ROUTE" } { 98 | set LOAD_DB true 99 | set LOAD_PLACE true 100 | } 101 | 102 | set ORIGINAL_QSF "" 103 | set ORIGINAL_PIN "" 104 | 105 | ################################################################################# 106 | 107 | if { $FLOW == "GEN" } { 108 | if { ! [info exists CONFIG_BITS] } { 109 | set CONFIG_BITS "${RESULT_DIR}/${DESIGN}.bin" 110 | } 111 | if { [llength $CONFIG_BITS] > 1 } { 112 | if { ! [info exists BOOT_BINARY] } { 113 | set BOOT_BINARY "${RESULT_DIR}/${DESIGN}_boot.bin" 114 | } 115 | if { ! [info exists CONFIG_ADDRESSES] } { 116 | set CONFIG_ADDRESSES "" 117 | } 118 | generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES 119 | } else { 120 | set CONFIG_ROOT [file rootname [lindex $CONFIG_BITS 0]] 121 | set SLAVE_RBF "${CONFIG_ROOT}_slave.rbf" 122 | set MASTER_BINARY "${CONFIG_ROOT}_master.bin" 123 | if { [file exists [lindex $CONFIG_BITS 0]] } { 124 | generate_binary -slave $SLAVE_RBF -inputs [lindex $CONFIG_BITS 0] -reverse 125 | generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0] 126 | } 127 | if { ! [info exists BOOT_BINARY] } { 128 | set BOOT_BINARY $MASTER_BINARY 129 | } 130 | } 131 | set PRG_FILE [file rootname $BOOT_BINARY].prg 132 | set AS_FILE [file rootname $BOOT_BINARY]_as.prg 133 | generate_programming_file $BOOT_BINARY -erase $ERASE \ 134 | -program $PROGRAM -verify $VERIFY -offset $OFFSET \ 135 | -prg $PRG_FILE -as $AS_FILE 136 | exit 137 | } 138 | 139 | if { $LOAD_DB } { 140 | load_db -top ${TOP_MODULE} 141 | set sdc "./${DESIGN}.adc" 142 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 143 | if { [file exists $sdc] } { read_sdc $sdc; } 144 | 145 | } elseif { $MODE == "QUARTUS" } { 146 | set verilog ${DESIGN}.vo 147 | set is_migrated false 148 | if { ! [file exists $verilog] } { 149 | set verilog "./simulation/modelsim/${DESIGN}.vo" 150 | set is_migrated true 151 | } 152 | if { ! [file exists $verilog] } { 153 | error "Can not find design verilog file $verilog" 154 | } 155 | alta::tcl_highlight "Using design verilog file $verilog.\n" 156 | set ret [read_design -top ${TOP_MODULE} -ve $VE_FILE -qsf $ORIGINAL_QSF $verilog -hierachy 1] 157 | if { !$ret } { exit -1; } 158 | 159 | set sdc "./${DESIGN}.adc" 160 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 161 | if { ! [file exists $sdc] } { 162 | alta::tcl_warn "Can not find design SDC file $sdc" 163 | } else { 164 | alta::tcl_highlight "Using design SDC file $sdc.\n" 165 | read_sdc $sdc 166 | } 167 | 168 | } elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { 169 | set db_gclk_assignment_level 2 170 | set verilog ${DESIGN}.vqm 171 | set is_migrated false 172 | if { ! [file exists $verilog] } { 173 | error "Can not find design verilog file $verilog" 174 | } 175 | 176 | set sdc "./${DESIGN}.adc" 177 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 178 | alta::tcl_highlight "Using design verilog file $verilog.\n" 179 | if { ! [file exists $sdc] } { 180 | alta::tcl_warn "Can not find design SDC file $sdc" 181 | set ret [read_design_and_pack -sdc $sdc -top ${TOP_MODULE} $verilog] 182 | } else { 183 | alta::tcl_highlight "Using design SDC file $sdc.\n" 184 | set ret [read_design_and_pack -top ${TOP_MODULE} $verilog] 185 | } 186 | if { !$ret } { exit -1; } 187 | 188 | } else { 189 | error "Unsupported mode $MODE" 190 | } 191 | 192 | if { $FLOW == "PACK" } { exit } 193 | 194 | if { [info exists FITTING] } { 195 | if { $FITTING == "Auto" } { set FITTING auto; } 196 | set_mode -fitting $FITTING 197 | } 198 | if { [info exists FITTER] } { 199 | if { $FITTER == "Auto" } { 200 | if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; } 201 | } 202 | if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; } 203 | set_mode -fitter $FITTER 204 | } 205 | if { [info exists EFFORT] } { set_mode -effort $EFFORT; } 206 | if { [info exists SKEW ] } { set_mode -skew $SKEW ; } 207 | if { [info exists SKOPE ] } { set_mode -skope $SKOPE ; } 208 | if { [info exists HOLDX ] } { set_mode -holdx $HOLDX; } 209 | if { [info exists TUNING] } { set_mode -tuning $TUNING; } 210 | if { [info exists TARGET] } { set_mode -target $TARGET; } 211 | if { [info exists PRESET] } { set_mode -preset $PRESET; } 212 | if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; } 213 | 214 | set alta_aqf $::alta_work/alta.aqf 215 | if { $LOAD_DB } { 216 | # Empty 217 | } elseif { false } { 218 | if { [file exists $VE_FILE] } { 219 | set ORIGINAL_PIN "" 220 | } elseif { ! [file exists $ORIGINAL_PIN] } { 221 | if { $is_migrated } { 222 | error "Can not find design PIN file $ORIGINAL_PIN, please compile design first" 223 | } 224 | set ORIGINAL_PIN "" 225 | } 226 | if { [file exists $ORIGINAL_QSF] } { 227 | alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf 228 | } elseif { $is_migrated } { 229 | error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first" 230 | } 231 | } 232 | if { [file exists "$alta_aqf"] } { 233 | alta::tcl_highlight "Using AQF file $alta_aqf.\n" 234 | source "$alta_aqf" 235 | } 236 | if { [file exists "./${DESIGN}.asf"] } { 237 | alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n" 238 | source "./${DESIGN}.asf" 239 | } 240 | 241 | if { $FLOW == "PROBE" } { 242 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 243 | if { !$ret } { exit -1 } 244 | 245 | set force "" 246 | if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" } 247 | eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}" 248 | 249 | } elseif { $FLOW == "CHECK" } { 250 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 251 | if { !$ret } { exit -1 } 252 | 253 | if { [file exists "./${DESIGN}.chk"] } { 254 | alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n" 255 | source "./${DESIGN}.chk" 256 | place_design -dry 257 | check_design -rule led_guide 258 | } else { 259 | error "Can not find design CHECK file ${DESIGN}.chk" 260 | } 261 | 262 | } else { 263 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io] 264 | if { !$ret } { exit -1 } 265 | 266 | set org_place "" 267 | set load_place "" 268 | set load_route "" 269 | set quiet "" 270 | if { $ORG_PLACE } { set org_place "-org_place" ; } 271 | if { $LOAD_PLACE } { set load_place "-load_place"; } 272 | if { $LOAD_ROUTE } { set load_route "-load_route"; } 273 | eval "place_and_route_design $org_place $load_place $load_route \ 274 | -retry $RETRY $seed_rand $quiet" 275 | } 276 | 277 | date_time 278 | if { $FLOW != "CHECK" } { 279 | if { $FLOW != "PROBE" } { 280 | #report_timing -verbose 1 -file $::alta_work/timing.rpt.gz 281 | report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz 282 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz 283 | report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz 284 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz 285 | 286 | set ta_report_auto_constraints 0 287 | report_timing -fmax -file $::alta_work/fmax.rpt 288 | report_timing -xfer -file $::alta_work/xfer.rpt 289 | set ta_report_auto_constraints $ta_report_auto 290 | 291 | #set ta_coverage_limit "0.95 0.90" 292 | set ta_dump_uncovered 1 293 | report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz 294 | #unset ta_coverage_limit 295 | unset ta_dump_uncovered 296 | 297 | 298 | if { ! [info exists rt_report_timing_fast] } { 299 | set rt_report_timing_fast false 300 | } 301 | if { $rt_report_timing_fast } { 302 | set_timing_corner fast 303 | route_delay -quiet 304 | report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz 305 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_fast_summary.rpt.gz 306 | report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz 307 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_fast_summary.rpt.gz 308 | set ta_report_auto_constraints 0 309 | report_timing -fmax -file $::alta_work/fmax_fast.rpt 310 | report_timing -xfer -file $::alta_work/xfer_fast.rpt 311 | set ta_report_auto_constraints $ta_report_auto 312 | } 313 | 314 | write_routed_design "${RESULT_DIR}/${RESULT}_routed.v" 315 | } 316 | 317 | bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin" 318 | bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg" 319 | bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf" 320 | generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \ 321 | -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse 322 | generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \ 323 | -inputs "${RESULT_DIR}/${RESULT}.bin" 324 | generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \ 325 | -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg" 326 | } 327 | 328 | if { [file exists "./${DESIGN}.post.asf"] } { 329 | alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n" 330 | source "./${DESIGN}.post.asf" 331 | } 332 | date_time 333 | exit 334 | 335 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | echo "setup envirenment variable..." 4 | #export PATH="/d/EE/FPGA/AGM/Supra-2022.06.b0-454528eb-win64-all/bin:$PATH" 5 | . supra_vars.sh 6 | 7 | af.exe -B --batch --mode QUARTUS -X "set QUARTUS_SDC true" -X "set FITTING timing_more" -X "set FITTER hybrid" -X "set EFFORT highest" -X "set HOLDX default" -X "set SKEW basic" 8 | 9 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280/common/DFFx2.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Author: Dong Xiao 2012.10.30 3 | */ 4 | 5 | module DFFx2 6 | ( 7 | input clk, 8 | input nRst, 9 | input D, 10 | output Q 11 | ); 12 | reg D1, D2; 13 | assign Q = D2; 14 | 15 | always @ ( posedge clk, negedge nRst ) begin 16 | if(!nRst) begin 17 | D1 <= 1'b0; 18 | D2 <= 1'b0; 19 | end 20 | else begin 21 | D1 <= D; 22 | D2 <= D1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_AG1280/common/PowerOnReset.v: -------------------------------------------------------------------------------- 1 | /** 2 | * power on reset 3 | * Author: Dong Xiao 4 | */ 5 | 6 | module PowerOnReset (input iCLK, output reg oRESET); 7 | 8 | reg [19:0] cnt; 9 | 10 | initial begin 11 | cnt <= 20'h00000; 12 | end 13 | 14 | always @(posedge iCLK) begin 15 | if(cnt != 20'hFFFFF) begin 16 | cnt <= cnt + 20'd1; 17 | oRESET <= 1'b0; 18 | end 19 | else 20 | oRESET <= 1'b1; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_AG1280/common/clkdivider.v: -------------------------------------------------------------------------------- 1 | /** 2 | * clkout = clk/CNT_MAX 3 | * CNT_MAX is even number. 4 | * Author: Dong Xiao 5 | */ 6 | 7 | `timescale 1 ns/ 1 ns 8 | 9 | module clkdivider #( parameter CNT_MAX = 16'd2 ) 10 | ( 11 | input clk, 12 | input nRST, 13 | output reg clkout 14 | ); 15 | reg [15:0] cnt; 16 | 17 | always @( posedge clk, negedge nRST ) begin 18 | if( !nRST ) begin 19 | cnt <= 16'd0; 20 | clkout <= 1'b0; 21 | end else begin 22 | if ( cnt < CNT_MAX/2-1 ) begin 23 | cnt <= cnt + 16'd1; 24 | end else begin 25 | cnt <= 16'd0; 26 | clkout <= ~clkout; 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_AG1280/download.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | echo "setup envirenment variable..." 4 | . supra_vars.sh 5 | 6 | if [ $# -eq 1 ]; then 7 | case $1 in 8 | sram) 9 | echo "Program SRAM of AG1280Q48" 10 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 Blink_AG1280_sram.prg" 11 | ;; 12 | flash) 13 | echo "Program FLASH of AG1280Q48" 14 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 Blink_AG1280_hybrid.prg" 15 | ;; 16 | erase) 17 | echo "Erase FLASH of AG1280Q48" 18 | af.exe -B -X "set blaster_id 0" -X "set bitgen_usb_speed 3000" -X "exit [catch {erase_flash}]" 19 | ;; 20 | esac 21 | else 22 | echo "Usage $0 [sram|flash|erase]" 23 | fi 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.asf: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_13 -to CLK 2 | set_location_assignment PIN_15 -to CLK1 3 | set_location_assignment PIN_12 -to KEY[1] 4 | set_location_assignment PIN_5 -to KEY[2] 5 | set_location_assignment PIN_6 -to LED[1] 6 | set_location_assignment PIN_9 -to LED[2] 7 | set_location_assignment PIN_1 -to CLKO[0] 8 | set_location_assignment PIN_2 -to CLKO[1] 9 | set_location_assignment PIN_3 -to CLKO[2] 10 | set_location_assignment PIN_4 -to BENCH_OUT 11 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.post.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG1280_INTOSC/Blink_AG1280.post.asf -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.pre.asf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/hdl/Blink_AG1280_INTOSC/Blink_AG1280.pre.asf -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.proj: -------------------------------------------------------------------------------- 1 | [GuiMigrateSetupPage] 2 | fromDir= 3 | design=Blink_AG1280 4 | device=AG1280Q48 5 | veFile= 6 | ipFiles=PLL.ip 7 | backwardCompatible=false 8 | modeGroup=false 9 | modeQuartus=true 10 | modeSynplicity=false 11 | modeNative=false 12 | 13 | [GuiMigrateRunPage] 14 | isMC=false 15 | count= 16 | jobs= 17 | seed= 18 | retry=0 19 | fitting=6 20 | fitter=4 21 | effort=3 22 | holdx=0 23 | skew=2 24 | skope=0 25 | preset=0 26 | adjust=0 27 | target=0 28 | tuning=0 29 | flow=0 30 | orgPlace=false 31 | quartusSdc=true 32 | probeForce=false 33 | probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2m\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xab\0\0\0\x1\0\0\0\0) 34 | probeCount=5 35 | probe0From= 36 | probe0Pad= 37 | probe1From= 38 | probe1Pad= 39 | probe2From= 40 | probe2Pad= 41 | probe3From= 42 | probe3Pad= 43 | probe4From= 44 | probe4Pad= 45 | 46 | [MainWindow] 47 | recentFile.0=PLL.v 48 | recentFile.1= 49 | 50 | [GuiIpPllScreen] 51 | module=PLL 52 | inputFreq=24 53 | type=1 54 | fbMode=1 55 | compMode=0 56 | output=1 57 | useDiff=false 58 | useExt=false 59 | output0Freq=24 60 | output0Phase= 61 | output0Duty= 62 | output1Freq=50 63 | output1Phase= 64 | output1Duty= 65 | output2Freq= 66 | output2Phase= 67 | output2Duty= 68 | output3Freq= 69 | output3Phase= 70 | output3Duty= 71 | output4Freq= 72 | output4Phase= 73 | output4Duty= 74 | output5Freq= 75 | output5Phase= 76 | output5Duty= 77 | output6Freq= 78 | output6Phase= 79 | output6Duty= 80 | output7Freq= 81 | output7Phase= 82 | output7Duty= 83 | output8Freq= 84 | output8Phase= 85 | output8Duty= 86 | output9Freq= 87 | output9Phase= 88 | output9Duty= 89 | output10Freq= 90 | output10Phase= 91 | output10Duty= 92 | output11Freq= 93 | output11Phase= 94 | output11Duty= 95 | output12Freq= 96 | output12Phase= 97 | output12Duty= 98 | output13Freq= 99 | output13Phase= 100 | output13Duty= 101 | output14Freq= 102 | output14Phase= 103 | output14Duty= 104 | output15Freq= 105 | output15Phase= 106 | output15Duty= 107 | output16Freq= 108 | output16Phase= 109 | output16Duty= 110 | output17Freq= 111 | output17Phase= 112 | output17Duty= 113 | output18Freq= 114 | output18Phase= 115 | output18Duty= 116 | output19Freq= 117 | output19Phase= 118 | output19Duty= 119 | output20Freq= 120 | output20Phase= 121 | output20Duty= 122 | output21Freq= 123 | output21Phase= 124 | output21Duty= 125 | output22Freq= 126 | output22Phase= 127 | output22Duty= 128 | output23Freq= 129 | output23Phase= 130 | output23Duty= 131 | output24Freq= 132 | output24Phase= 133 | output24Duty= 134 | output25Freq= 135 | output25Phase= 136 | output25Duty= 137 | output26Freq= 138 | output26Phase= 139 | output26Duty= 140 | output27Freq= 141 | output27Phase= 142 | output27Duty= 143 | output28Freq= 144 | output28Phase= 145 | output28Duty= 146 | output29Freq= 147 | output29Phase= 148 | output29Duty= 149 | output30Freq= 150 | output30Phase= 151 | output30Duty= 152 | output31Freq= 153 | output31Phase= 154 | output31Duty= 155 | 156 | [GuiRuleChkScreen] 157 | spiGroup=false 158 | phyGroup=false 159 | sdramGroup=false 160 | criticalInput= 161 | criticalOutput= 162 | spiSpi= 163 | phyOut= 164 | phyOCtrl= 165 | phyOClk= 166 | phyIn= 167 | phyICtrl= 168 | phyIClk= 169 | sdramMethod1=true 170 | sdramMethod2=false 171 | sdramData= 172 | sdramAddr= 173 | sdramCtrl= 174 | sdramClk= 175 | sdramClock= 176 | 177 | [GuiProgramScreen] 178 | hardwareId=0 179 | prgFile=Blink_AG1280_hybrid.prg 180 | eraseBox=false 181 | cable=UsbBlaster 182 | runAction=program 183 | eraseChip=true 184 | eraseFrom= 185 | eraseTo= 186 | binFile= 187 | readFrom= 188 | readTo= 189 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.qpf: -------------------------------------------------------------------------------- 1 | #QUARTUS_VERSION = "11.1" 2 | PROJECT_REVISION = "Blink_AG1280" 3 | 4 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version 21 | # Date created = 22:39:50 October 18, 2022 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Blink_AG1280_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | 40 | # Project-Wide Assignments 41 | # ======================== 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:37:04 JANUARY 04, 2013" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ./quartus_logs 46 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 47 | set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON 48 | set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON 49 | set_global_assignment -name VERILOG_FILE common/PowerOnReset.v 50 | set_global_assignment -name VERILOG_FILE common/DFFx2.v 51 | set_global_assignment -name VERILOG_FILE common/clkdivider.v 52 | set_global_assignment -name VERILOG_FILE .\\Blink_AG1280.v 53 | set_global_assignment -name VERILOG_FILE "D:\\EE\\FPGA\\AGM\\Supra-2022.06.b0-454528eb-win64-all\\etc\\arch\\rodinia\\alta_sim.v" 54 | set_global_assignment -name SDC_FILE .\\Blink_AG1280.sdc 55 | set_global_assignment -name SDC_FILE .\\Blink_AG1280_derate.sdc 56 | 57 | # Classic Timing Assignments 58 | # ========================== 59 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 60 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 61 | 62 | # Analysis & Synthesis Assignments 63 | # ================================ 64 | set_global_assignment -name FAMILY "Cyclone IV E" 65 | set_global_assignment -name TOP_LEVEL_ENTITY Blink_AG1280 66 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON 67 | set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON 68 | set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF 69 | set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0 70 | set_global_assignment -name MAX_RAM_BLOCKS_M4K 0 71 | set_global_assignment -name AUTO_ROM_RECOGNITION OFF 72 | set_global_assignment -name AUTO_RAM_RECOGNITION OFF 73 | 74 | # Fitter Assignments 75 | # ================== 76 | set_global_assignment -name DEVICE EP4CE75F29C8 77 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 78 | set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF 79 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" 80 | set_global_assignment -name FITTER_EFFORT "STANDARD FIT" 81 | set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM 82 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10 83 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10 84 | set_global_assignment -name ECO_OPTIMIZE_TIMING ON 85 | set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS 86 | set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS 87 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 88 | set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON 89 | set_global_assignment -name SEED 1 90 | set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF 91 | set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED 8 92 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON 93 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON 94 | set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA 95 | 96 | # EDA Netlist Writer Assignments 97 | # ============================== 98 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" 99 | 100 | # LogicLock Region Assignments 101 | # ============================ 102 | set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF 103 | 104 | # Power Estimation Assignments 105 | # ============================ 106 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 107 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 108 | 109 | # start EDA_TOOL_SETTINGS(eda_simulation) 110 | # --------------------------------------- 111 | 112 | # EDA Netlist Writer Assignments 113 | # ============================== 114 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 115 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 116 | set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation 117 | 118 | # end EDA_TOOL_SETTINGS(eda_simulation) 119 | # ------------------------------------- 120 | 121 | # -------------------------- 122 | # start ENTITY(Blink_AG1280) 123 | 124 | # start LOGICLOCK_REGION(core_logic) 125 | # ---------------------------------- 126 | 127 | # LogicLock Region Assignments 128 | # ============================ 129 | set_global_assignment -name LL_ENABLED ON -section_id core_logic 130 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id core_logic 131 | set_global_assignment -name LL_STATE LOCKED -section_id core_logic 132 | set_global_assignment -name LL_RESERVED OFF -section_id core_logic 133 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id core_logic 134 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id core_logic 135 | set_global_assignment -name LL_PR_REGION OFF -section_id core_logic 136 | set_global_assignment -name LL_WIDTH 13 -section_id core_logic 137 | set_global_assignment -name LL_HEIGHT 8 -section_id core_logic 138 | set_global_assignment -name LL_ORIGIN X1_Y1 -section_id core_logic 139 | set_global_assignment -name LL_MEMBER_OF core_logic -section_id core_logic 140 | 141 | # end LOGICLOCK_REGION(core_logic) 142 | # -------------------------------- 143 | 144 | # start LOGICLOCK_REGION(LOGIC_RESERVE_0) 145 | # --------------------------------------- 146 | 147 | # LogicLock Region Assignments 148 | # ============================ 149 | set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_0 150 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_0 151 | set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_0 152 | set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_0 153 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_0 154 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_0 155 | set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_0 156 | set_global_assignment -name LL_WIDTH 9 -section_id LOGIC_RESERVE_0 157 | set_global_assignment -name LL_HEIGHT 1 -section_id LOGIC_RESERVE_0 158 | set_global_assignment -name LL_ORIGIN X1_Y1 -section_id LOGIC_RESERVE_0 159 | 160 | # end LOGICLOCK_REGION(LOGIC_RESERVE_0) 161 | # ------------------------------------- 162 | 163 | # start LOGICLOCK_REGION(LOGIC_RESERVE_1) 164 | # --------------------------------------- 165 | 166 | # LogicLock Region Assignments 167 | # ============================ 168 | set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_1 169 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_1 170 | set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_1 171 | set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_1 172 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_1 173 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_1 174 | set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_1 175 | set_global_assignment -name LL_WIDTH 1 -section_id LOGIC_RESERVE_1 176 | set_global_assignment -name LL_HEIGHT 7 -section_id LOGIC_RESERVE_1 177 | set_global_assignment -name LL_ORIGIN X4_Y2 -section_id LOGIC_RESERVE_1 178 | 179 | # end LOGICLOCK_REGION(LOGIC_RESERVE_1) 180 | # ------------------------------------- 181 | 182 | # start LOGICLOCK_REGION(LOGIC_RESERVE_2) 183 | # --------------------------------------- 184 | 185 | # LogicLock Region Assignments 186 | # ============================ 187 | set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_2 188 | set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_2 189 | set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_2 190 | set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_2 191 | set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_2 192 | set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_2 193 | set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_2 194 | set_global_assignment -name LL_WIDTH 1 -section_id LOGIC_RESERVE_2 195 | set_global_assignment -name LL_HEIGHT 8 -section_id LOGIC_RESERVE_2 196 | set_global_assignment -name LL_ORIGIN X11_Y1 -section_id LOGIC_RESERVE_2 197 | 198 | # end LOGICLOCK_REGION(LOGIC_RESERVE_2) 199 | # ------------------------------------- 200 | 201 | # start DESIGN_PARTITION(Top) 202 | # --------------------------- 203 | 204 | # Incremental Compilation Assignments 205 | # =================================== 206 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 207 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 208 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 209 | 210 | # end DESIGN_PARTITION(Top) 211 | # ------------------------- 212 | 213 | # start DESIGN_PARTITION(p0_PLL_45DB2125) 214 | # --------------------------------------- 215 | 216 | # Incremental Compilation Assignments 217 | # =================================== 218 | set_global_assignment -name PARTITION_COLOR 52377 -section_id p0_PLL_45DB2125 -tag alta_auto 219 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id p0_PLL_45DB2125 -tag alta_auto 220 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id p0_PLL_45DB2125 -tag alta_auto 221 | 222 | # end DESIGN_PARTITION(p0_PLL_45DB2125) 223 | # ------------------------------------- 224 | 225 | # end ENTITY(Blink_AG1280) 226 | # ------------------------ 227 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 228 | set_instance_assignment -name PARTITION_HIERARCHY p0_PLL_45DB2125 -to "PLL:p0|alta_pllx:PLL_45DB2125" -section_id p0_PLL_45DB2125 -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.sdc: -------------------------------------------------------------------------------- 1 | derive_pll_clocks -create_base_clocks 2 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/Blink_AG1280.v: -------------------------------------------------------------------------------- 1 | module Blink_AG1280( 2 | input CLK, 3 | input CLK1, 4 | 5 | input [2:1] KEY, 6 | output [2:1] LED, 7 | 8 | // Test Output 9 | output [2:0] CLKO, 10 | output BENCH_OUT 11 | ); 12 | 13 | wire locked; 14 | wire nRst = KEY[2]; 15 | wire CLK_24M, CLK_50M; 16 | PLL p0( 17 | .clkin(CLK1), 18 | .clkfb(CLK_24M), 19 | .pllen(1'b1), 20 | .resetn(1'b1), 21 | .clkout0en(1'b1), 22 | .clkout1en(1'b1), 23 | .clkout2en(1'b0), 24 | .clkout3en(1'b0), 25 | .clkout0(CLK_24M), 26 | .clkout1(CLK_50M), 27 | .clkout2(), 28 | .clkout3(), 29 | .lock(locked)); 30 | 31 | wire CLK_1M, CLK_1k, CLK_1Hz; 32 | clkdivider #(.CNT_MAX(16'd50)) c0 (.clk(CLK_50M), .nRST(nRst), .clkout(CLK_1M)); 33 | clkdivider #(.CNT_MAX(16'd1000)) c1 (.clk(CLK_1M), .nRST(nRst), .clkout(CLK_1k)); 34 | clkdivider #(.CNT_MAX(16'd1000)) c2 (.clk(CLK_1k), .nRST(nRst), .clkout(CLK_1Hz)); 35 | 36 | assign CLKO[0] = CLK_1M; 37 | assign CLKO[1] = CLK_1k; 38 | assign CLKO[2] = CLK_1Hz; 39 | assign BENCH_OUT = CLK_1M; 40 | 41 | assign LED[1] = CLK_1Hz; 42 | assign LED[2] = ~KEY[1]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/PLL.ip: -------------------------------------------------------------------------------- 1 | IP PLL_45DB2125 2 | TYPE : alta_pllx; 3 | PARAMETER 4 | CLKIN_DIV : 6'h05 BITS; 5 | CLKFB_DIV : 6'h3F BITS; 6 | CLKDIV0_EN : 1'h1 BITS; 7 | CLKOUT0_DIV : 6'h0E BITS; 8 | CLKOUT0_DEL : 6'h00 BITS; 9 | CLKOUT0_PHASE : 3'h0 BITS; 10 | CLKDIV1_EN : 1'h1 BITS; 11 | CLKOUT1_DIV : 6'h06 BITS; 12 | CLKOUT1_DEL : 6'h00 BITS; 13 | CLKOUT1_PHASE : 3'h0 BITS; 14 | CLKDIV2_EN : 1'h0 BITS; 15 | CLKOUT2_DIV : 6'h3F BITS; 16 | CLKOUT2_DEL : 6'h00 BITS; 17 | CLKOUT2_PHASE : 3'h0 BITS; 18 | CLKDIV3_EN : 1'h0 BITS; 19 | CLKOUT3_DIV : 6'h3F BITS; 20 | CLKOUT3_DEL : 6'h00 BITS; 21 | CLKOUT3_PHASE : 3'h0 BITS; 22 | FEEDBACK_MODE : 1'b0 BITS; 23 | FEEDBACK_CLOCK : 2'b00 BITS; 24 | END_PARAMETER 25 | END_IP 26 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/PLL.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module PLL( 3 | input clkin, 4 | input clkfb, 5 | input pllen, 6 | input resetn, 7 | input clkout0en, 8 | input clkout1en, 9 | input clkout2en, 10 | input clkout3en, 11 | output clkout0, 12 | output clkout1, 13 | output clkout2, 14 | output clkout3, 15 | output lock 16 | ); 17 | 18 | 19 | alta_pllx PLL_45DB2125( 20 | .clkin(clkin), 21 | .clkfb(clkfb), 22 | .pllen(pllen), 23 | .resetn(resetn), 24 | .clkout0en(clkout0en), 25 | .clkout1en(clkout1en), 26 | .clkout2en(clkout2en), 27 | .clkout3en(clkout3en), 28 | .clkout0(PLL_clkout0), 29 | .clkout1(PLL_clkout1), 30 | .clkout2(PLL_clkout2), 31 | .clkout3(PLL_clkout3), 32 | .lock(PLL_lock) 33 | ); 34 | defparam PLL_45DB2125.CLKIN_DIV = 6'h05; 35 | defparam PLL_45DB2125.CLKFB_DIV = 6'h3F; 36 | defparam PLL_45DB2125.CLKDIV0_EN = 1'h1; 37 | defparam PLL_45DB2125.CLKOUT0_DIV = 6'h0E; 38 | defparam PLL_45DB2125.CLKOUT0_DEL = 6'h00; 39 | defparam PLL_45DB2125.CLKOUT0_PHASE = 3'h0; 40 | defparam PLL_45DB2125.CLKDIV1_EN = 1'h1; 41 | defparam PLL_45DB2125.CLKOUT1_DIV = 6'h06; 42 | defparam PLL_45DB2125.CLKOUT1_DEL = 6'h00; 43 | defparam PLL_45DB2125.CLKOUT1_PHASE = 3'h0; 44 | defparam PLL_45DB2125.CLKDIV2_EN = 1'h0; 45 | defparam PLL_45DB2125.CLKOUT2_DIV = 6'h3F; 46 | defparam PLL_45DB2125.CLKOUT2_DEL = 6'h00; 47 | defparam PLL_45DB2125.CLKOUT2_PHASE = 3'h0; 48 | defparam PLL_45DB2125.CLKDIV3_EN = 1'h0; 49 | defparam PLL_45DB2125.CLKOUT3_DIV = 6'h3F; 50 | defparam PLL_45DB2125.CLKOUT3_DEL = 6'h00; 51 | defparam PLL_45DB2125.CLKOUT3_PHASE = 3'h0; 52 | defparam PLL_45DB2125.FEEDBACK_MODE = 1'b0; 53 | defparam PLL_45DB2125.FEEDBACK_CLOCK = 2'b00; 54 | 55 | assign clkout0 = PLL_clkout0; 56 | assign clkout1 = PLL_clkout1; 57 | assign clkout2 = PLL_clkout2; 58 | assign clkout3 = PLL_clkout3; 59 | assign lock = PLL_lock; 60 | 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/af_batch.tcl: -------------------------------------------------------------------------------- 1 | if {![info exist MODE ]} {set MODE QUARTUS} 2 | if {![info exists QUARTUS_SDC]} {set QUARTUS_SDC true} 3 | if {![info exist COUNT]} {set COUNT 6} 4 | if {![info exist JOBS ]} {set JOBS 1} 5 | 6 | if {![info exist SEEDS ]} {set SEEDS {0 0 0 0 666 888 }} 7 | if {![info exist EFFORTS ]} {set EFFORTS {highest highest highest highest high high }} 8 | if {![info exist FITTERS ]} {set FITTERS {hybrid hybrid hybrid hybrid hybrid hybrid }} 9 | if {![info exist FITTINGS]} {set FITTINGS {timing_more timing_more timing_more timing timing basic }} 10 | if {![info exist SKEWS ]} {set SKEWS {advanced advanced advanced advanced aggressive basic }} 11 | if {![info exist HOLDXS ]} {set HOLDXS {default default default default default default}} 12 | 13 | set bc_config "./bc_config.txt" 14 | if { [file exists $bc_config] } { 15 | alta::tcl_highlight "Using MC config $bc_config.\n" 16 | source "$bc_config" 17 | } 18 | 19 | ####################################################################### 20 | 21 | proc get_rand_value { values } { 22 | if {[llength $values] == 0} { return {} } 23 | return [lindex $values [expr {int(rand()*10000)%[llength $values]}]] 24 | } 25 | 26 | set results "bc_results" 27 | set summary "bc_summary.txt" 28 | file delete -force $results; file mkdir $results 29 | file delete $summary; print -nonewline "" >! $summary 30 | 31 | set is_parallel [expr $JOBS > 1] 32 | set is_color ""; set is_gui ""; set is_quiet "" 33 | if { $is_parallel } { 34 | set is_gui "--quiet" 35 | } else { 36 | if { [alta::tcl_is_color] } { set is_color "--color" } 37 | if { [alta::tcl_is_gui ] } { set is_gui "--gui" } 38 | } 39 | 40 | ####################################################################### 41 | 42 | set progs {} 43 | set titles {} 44 | for {set id 1} {$id <= $COUNT} {incr id} { 45 | set result_dir "$results/$id" 46 | file mkdir $result_dir 47 | 48 | set seed [get_rand_value $SEEDS ] 49 | set effort [get_rand_value $EFFORTS ] 50 | set skew [get_rand_value $SKEWS ] 51 | set fitter [get_rand_value $FITTERS ] 52 | set fitting [get_rand_value $FITTINGS] 53 | set holdx [get_rand_value $HOLDXS ] 54 | 55 | set prog [list [info nameofexec] $is_quiet $is_color $is_gui -B --batch --mode $MODE] 56 | alta::lconcat prog [list -X "set QUARTUS_SDC $QUARTUS_SDC"] 57 | alta::lconcat prog [list -X "set RESULT_DIR $result_dir"] 58 | if { $seed != "" } { 59 | alta::lconcat prog [list -X "set SEED $seed"] 60 | } 61 | if { $effort != "" } { 62 | alta::lconcat prog [list -X "set EFFORT $effort"] 63 | } 64 | if { $fitter != "" } { 65 | alta::lconcat prog [list -X "set FITTER $fitter"] 66 | } 67 | if { $fitting != "" } { 68 | alta::lconcat prog [list -X "set FITTING $fitting"] 69 | } 70 | if { $skew != "" } { 71 | alta::lconcat prog [list -X "set SKEW $skew"] 72 | } 73 | if { $holdx != "" } { 74 | alta::lconcat prog [list -X "set HOLDX $holdx"] 75 | } 76 | #alta::lconcat prog [list -F af_run.tcl] 77 | lappend progs $prog 78 | lappend titles "#$id $result_dir" 79 | } 80 | 81 | ####################################################################### 82 | 83 | if { $is_parallel } { 84 | set bg_progs {} 85 | foreach bg_prog $progs { 86 | lappend bg_progs [lappend bg_prog $is_quiet] 87 | } 88 | bg_exec_queue $titles $bg_progs $JOBS 89 | } 90 | 91 | ####################################################################### 92 | 93 | for {set id 1} {$id <= $COUNT} {incr id} { 94 | set result_dir "$results/$id" 95 | set prog [lindex $progs [expr $id-1]] 96 | set title [lindex $titles [expr $id-1]] 97 | if { ! $is_parallel } { 98 | puts $title 99 | puts $prog 100 | eval exec -ignorestderr $prog >&@ stdout 101 | } 102 | 103 | print "***************************************************************************\n" >> $summary 104 | print "$title\n" >> $summary 105 | cat "$result_dir/alta_db/fmax.rpt" >> $summary 106 | cat "$result_dir/alta_db/xfer.rpt" >> $summary 107 | print "" >> $summary 108 | } 109 | 110 | alta::tcl_highlight "Check $summary for result.\n" 111 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/af_ip.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set DESIGN "Blink_AG1280" 3 | set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp } 4 | lappend IPLIST alta_rv32 5 | 6 | proc set_alta_partition {inst tag} { 7 | set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst] 8 | set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst] 9 | set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst] 10 | set section_id [string map { [ _ ] _ . _ | _} $inst_name] 11 | eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag" 12 | eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag" 13 | eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag" 14 | eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag" 15 | } 16 | 17 | load_package flow 18 | if { $DESIGN == "" } { 19 | set DESIGN $::quartus(args) 20 | } 21 | project_open $DESIGN 22 | 23 | set tag alta_auto 24 | if { [llength $IPLIST] > 0 } { 25 | # A Quartus bug saves PARTITION_HIERARCHY assignments without tag. Use section_id to remove them. 26 | set asgn_col [get_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag] 27 | foreach_in_collection part $asgn_col { 28 | set section_id [lindex $part 0] 29 | eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -section_id $section_id" 30 | } 31 | eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag" 32 | eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag" 33 | eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag" 34 | catch { execute_module -tool map } 35 | 36 | foreach ip $IPLIST { 37 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] { 38 | set_alta_partition $inst $tag 39 | } 40 | foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] { 41 | set_alta_partition $inst $tag 42 | } 43 | } 44 | } 45 | eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation" 46 | 47 | project_close 48 | 49 | exit 50 | 51 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/af_map.tcl: -------------------------------------------------------------------------------- 1 | map -import 2 | 3 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 4 | set TOP_MODULE "$DESIGN" 5 | } 6 | if { ! [info exists DESIGN] } { 7 | set DESIGN "Blink_AG1280" 8 | } 9 | if { ! [info exists TOP_MODULE] } { 10 | set TOP_MODULE "Blink_AG1280" 11 | } 12 | 13 | set verilogs { .\\Blink_AG1280.v } 14 | if { [ llength $verilogs ] == 0 } { 15 | set verilogs "./${DESIGN}.v" 16 | } 17 | foreach verilog $verilogs { 18 | read_verilog "$verilog" 19 | } 20 | 21 | read_verilog -sv -lib +/agm/rodina/cells_sim.v 22 | read_verilog -sv -lib +/agm/common/m9k_bb.v 23 | read_verilog -sv -lib +/agm/common/altpll_bb.v 24 | hierarchy -check -top ${TOP_MODULE} 25 | 26 | synth -run coarse -top ${DESIGN} 27 | 28 | map proc 29 | opt_expr 30 | opt_clean 31 | check 32 | opt 33 | 34 | wreduce 35 | alumacc 36 | share 37 | opt 38 | fsm 39 | opt -fast 40 | memory -nomap 41 | opt_clean 42 | 43 | memory_bram -rules +/agm/common/brams.txt 44 | techmap -map +/agm/common/brams_map.v 45 | 46 | opt -fast -mux_undef -undriven -fine -full 47 | memory_map 48 | opt -undriven -fine 49 | 50 | techmap -autoproc -map +/techmap.v -map +/agm/rodina/arith_map.v 51 | dffsr2dff 52 | dff2dffe -direct-match \$_DFF_* 53 | opt -full 54 | 55 | techmap -map +/agm/rodina/cells_map.v 56 | agm_dffeas 57 | opt -full 58 | 59 | clean -purge 60 | setundef -undriven -zero 61 | abc -markgroups -dff 62 | opt_expr -mux_undef -undriven -full 63 | opt_merge 64 | opt_rmdff 65 | opt_clean 66 | 67 | abc -lut 4 68 | clean 69 | 70 | techmap -map +/agm/rodina/cells_map.v 71 | dffinit -ff dffeas Q INIT 72 | clean -purge 73 | 74 | hierarchy -check 75 | check -noinit 76 | 77 | write_verilog -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm 78 | # exec sed -i "/\\\\\\\$paramod/s/\[$=\\]/_/g" ${DESIGN}.vqm 79 | 80 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/af_quartus.tcl: -------------------------------------------------------------------------------- 1 | set AGM_SUPRA true 2 | set RETRY 0 3 | set DESIGN "Blink_AG1280" 4 | 5 | if { [is_project_open] } { 6 | export_assignments 7 | } 8 | 9 | set is_compatible false 10 | if { $is_compatible } { 11 | cd 12 | qexec "[file join $::quartus(binpath) quartus_eda] $DESIGN --simulation --tool=modelsim --format=verilog" 13 | } else { 14 | set FITTER_EFFORTS {"STANDARD FIT" "STANDARD FIT" "FAST FIT" "FAST FIT" "FAST FIT"} 15 | set SEEDS [list [expr int(rand()*100)] \ 16 | [expr int(rand()*100)] \ 17 | [expr int(rand()*100)] \ 18 | [expr int(rand()*100)] \ 19 | [expr int(rand()*100)]] 20 | set PLACEMENT_EFFORTS [list [expr rand()*5+0.1] \ 21 | [expr rand()*5+0.1] \ 22 | [expr rand()*5+0.1] \ 23 | [expr rand()*5+0.1] \ 24 | [expr rand()*5+0.1]] 25 | set ROUTER_EFFORTS [list [expr rand()*5+0.25] \ 26 | [expr rand()*5+0.25] \ 27 | [expr rand()*5+0.25] \ 28 | [expr rand()*5+0.25] \ 29 | [expr rand()*5+0.25]] 30 | 31 | qexec "[file join $::quartus(binpath) quartus_sh] -t af_ip.tcl" 32 | 33 | load_package flow 34 | project_open $DESIGN 35 | 36 | set RETRY [expr $RETRY<[llength $FITTER_EFFORTS]?$RETRY:[llength $FITTER_EFFORTS]] 37 | for {set nn -1} {$nn < $RETRY} {incr nn} { 38 | if {$nn >= 0} { 39 | set_global_assignment -name FITTER_EFFORT \"[lindex $FITTER_EFFORTS $nn]\" 40 | set_global_assignment -name SEED [lindex $SEEDS $nn] 41 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER [lindex $PLACEMENT_EFFORTS $nn] 42 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER [lindex $ROUTER_EFFORTS $nn] 43 | } 44 | 45 | set code [catch {execute_flow -compile} msg] 46 | if { $code == 0 } { break } 47 | } 48 | } 49 | 50 | 51 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/af_run.tcl: -------------------------------------------------------------------------------- 1 | set ALTA_SUPRA true 2 | set sh_continue_on_error false 3 | set sh_echo_on_source true 4 | set sh_quiet_on_source true 5 | set cc_critical_as_fatal true 6 | set rt_incremental_route true 7 | set ta_report_auto 1 8 | set ta_report_auto_constraints $ta_report_auto 9 | 10 | if { ! [info exists RESULT_DIR] } { 11 | set RESULT_DIR "." 12 | } elseif { ! [info exists alta_work] } { 13 | set alta_work "${RESULT_DIR}/alta_db" 14 | } 15 | if { ! [info exists DEVICE] } { 16 | set DEVICE "AG1280Q48" 17 | } 18 | if { [info exists DESIGN] && ! [info exists TOP_MODULE] } { 19 | set TOP_MODULE "$DESIGN" 20 | } 21 | if { ! [info exists DESIGN] } { 22 | set DESIGN "Blink_AG1280" 23 | } 24 | if { ! [info exists TOP_MODULE] } { 25 | set TOP_MODULE "Blink_AG1280" 26 | } 27 | if { ! [info exists IP_FILES] } { 28 | set IP_FILES {"E:/echo/project/echo/Company/AGM/Blink_AG1280_INTOSC/PLL.ip" } 29 | } 30 | if { ! [info exists VE_FILE] } { 31 | set VE_FILE "" 32 | } 33 | if { ! [info exists TIMING_DERATE] } { 34 | set TIMING_DERATE 1.000000 35 | } 36 | if { [info exists NO_ROUTE] && $NO_ROUTE } { 37 | set no_route "-no_route" 38 | } else { 39 | set no_route "" 40 | } 41 | if { ! [info exists RETRY] } { set RETRY 0 } 42 | if { ! [info exists SEED ] } { set SEED 666 } 43 | set seed_rand "" 44 | if { $SEED == 0 } { set seed_rand "-seed_rand" } 45 | if { [info exists QUARTUS_SDC] } { 46 | set sdc_remove_quartus_column_name $QUARTUS_SDC 47 | } 48 | if { ! [info exists ORG_PLACE] } { set ORG_PLACE false } 49 | if { ! [info exists MODE] } { set MODE "QUARTUS" } 50 | if { ! [info exists FLOW] } { set FLOW "ALL" } 51 | if { $FLOW == "PROBE" } { 52 | if { ! [info exists PROBE_FORCE] } { set PROBE_FORCE false } 53 | if { ! [info exists PREFIX] } { set PREFIX "probe_" } 54 | } 55 | if { ! [info exists PREFIX] } { 56 | set RESULT $DESIGN 57 | } else { 58 | set RESULT $PREFIX$DESIGN 59 | } 60 | if { $FLOW == "GEN" || $FLOW == "PACK" || $FLOW == "LOAD" } { set no_route "-no_route" } 61 | set RUN "run" 62 | if { $FLOW == "CHECK" } { 63 | set RUN "check" 64 | } elseif { $FLOW == "PROBE" } { 65 | set RUN "probe" 66 | } elseif { $FLOW == "GEN" } { 67 | set RUN "gen" 68 | } 69 | 70 | if { ! [info exists alta_logs] } { 71 | set alta_logs "${RESULT_DIR}/alta_logs" 72 | } 73 | file mkdir $alta_logs 74 | alta::begin_log_cmd "$alta_logs/${RUN}.log" "$alta_logs/${RUN}.err" 75 | alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n" 76 | alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n" 77 | 78 | set_seed_rand $SEED 79 | set ar_timing_derate ${TIMING_DERATE} 80 | 81 | date_time 82 | if { [file exists "./${DESIGN}.pre.asf"] } { 83 | alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n" 84 | source "./${DESIGN}.pre.asf" 85 | } 86 | 87 | eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000" 88 | foreach ip_file $IP_FILES { read_ip $ip_file; } 89 | 90 | set LOAD_DB false 91 | set LOAD_PLACE false 92 | set LOAD_ROUTE false 93 | if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } { 94 | set LOAD_DB true 95 | set LOAD_PLACE true 96 | set LOAD_ROUTE true 97 | } elseif { $FLOW == "R" || $FLOW == "ROUTE" } { 98 | set LOAD_DB true 99 | set LOAD_PLACE true 100 | } 101 | 102 | set ORIGINAL_QSF "" 103 | set ORIGINAL_PIN "" 104 | 105 | ################################################################################# 106 | 107 | if { $FLOW == "GEN" } { 108 | if { ! [info exists CONFIG_BITS] } { 109 | set CONFIG_BITS "${RESULT_DIR}/${DESIGN}.bin" 110 | } 111 | if { [llength $CONFIG_BITS] > 1 } { 112 | if { ! [info exists BOOT_BINARY] } { 113 | set BOOT_BINARY "${RESULT_DIR}/${DESIGN}_boot.bin" 114 | } 115 | if { ! [info exists CONFIG_ADDRESSES] } { 116 | set CONFIG_ADDRESSES "" 117 | } 118 | generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES 119 | } else { 120 | set CONFIG_ROOT [file rootname [lindex $CONFIG_BITS 0]] 121 | set SLAVE_RBF "${CONFIG_ROOT}_slave.rbf" 122 | set MASTER_BINARY "${CONFIG_ROOT}_master.bin" 123 | if { [file exists [lindex $CONFIG_BITS 0]] } { 124 | generate_binary -slave $SLAVE_RBF -inputs [lindex $CONFIG_BITS 0] -reverse 125 | generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0] 126 | } 127 | if { ! [info exists BOOT_BINARY] } { 128 | set BOOT_BINARY $MASTER_BINARY 129 | } 130 | } 131 | set PRG_FILE [file rootname $BOOT_BINARY].prg 132 | set AS_FILE [file rootname $BOOT_BINARY]_as.prg 133 | generate_programming_file $BOOT_BINARY -erase $ERASE \ 134 | -program $PROGRAM -verify $VERIFY -offset $OFFSET \ 135 | -prg $PRG_FILE -as $AS_FILE 136 | exit 137 | } 138 | 139 | if { $LOAD_DB } { 140 | load_db -top ${TOP_MODULE} 141 | set sdc "./${DESIGN}.adc" 142 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 143 | if { [file exists $sdc] } { read_sdc $sdc; } 144 | 145 | } elseif { $MODE == "QUARTUS" } { 146 | set verilog ${DESIGN}.vo 147 | set is_migrated false 148 | if { ! [file exists $verilog] } { 149 | set verilog "./simulation/modelsim/${DESIGN}.vo" 150 | set is_migrated true 151 | } 152 | if { ! [file exists $verilog] } { 153 | error "Can not find design verilog file $verilog" 154 | } 155 | alta::tcl_highlight "Using design verilog file $verilog.\n" 156 | set ret [read_design -top ${TOP_MODULE} -ve $VE_FILE -qsf $ORIGINAL_QSF $verilog -hierachy 1] 157 | if { !$ret } { exit -1; } 158 | 159 | set sdc "./${DESIGN}.adc" 160 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 161 | if { ! [file exists $sdc] } { 162 | alta::tcl_warn "Can not find design SDC file $sdc" 163 | } else { 164 | alta::tcl_highlight "Using design SDC file $sdc.\n" 165 | read_sdc $sdc 166 | } 167 | 168 | } elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { 169 | set db_gclk_assignment_level 2 170 | set verilog ${DESIGN}.vqm 171 | set is_migrated false 172 | if { ! [file exists $verilog] } { 173 | error "Can not find design verilog file $verilog" 174 | } 175 | 176 | set sdc "./${DESIGN}.adc" 177 | if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; } 178 | alta::tcl_highlight "Using design verilog file $verilog.\n" 179 | if { ! [file exists $sdc] } { 180 | alta::tcl_warn "Can not find design SDC file $sdc" 181 | set ret [read_design_and_pack -sdc $sdc -top ${TOP_MODULE} $verilog] 182 | } else { 183 | alta::tcl_highlight "Using design SDC file $sdc.\n" 184 | set ret [read_design_and_pack -top ${TOP_MODULE} $verilog] 185 | } 186 | if { !$ret } { exit -1; } 187 | 188 | } else { 189 | error "Unsupported mode $MODE" 190 | } 191 | 192 | if { $FLOW == "PACK" } { exit } 193 | 194 | if { [info exists FITTING] } { 195 | if { $FITTING == "Auto" } { set FITTING auto; } 196 | set_mode -fitting $FITTING 197 | } 198 | if { [info exists FITTER] } { 199 | if { $FITTER == "Auto" } { 200 | if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; } 201 | } 202 | if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; } 203 | set_mode -fitter $FITTER 204 | } 205 | if { [info exists EFFORT] } { set_mode -effort $EFFORT; } 206 | if { [info exists SKEW ] } { set_mode -skew $SKEW ; } 207 | if { [info exists SKOPE ] } { set_mode -skope $SKOPE ; } 208 | if { [info exists HOLDX ] } { set_mode -holdx $HOLDX; } 209 | if { [info exists TUNING] } { set_mode -tuning $TUNING; } 210 | if { [info exists TARGET] } { set_mode -target $TARGET; } 211 | if { [info exists PRESET] } { set_mode -preset $PRESET; } 212 | if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; } 213 | 214 | set alta_aqf $::alta_work/alta.aqf 215 | if { $LOAD_DB } { 216 | # Empty 217 | } elseif { false } { 218 | if { [file exists $VE_FILE] } { 219 | set ORIGINAL_PIN "" 220 | } elseif { ! [file exists $ORIGINAL_PIN] } { 221 | if { $is_migrated } { 222 | error "Can not find design PIN file $ORIGINAL_PIN, please compile design first" 223 | } 224 | set ORIGINAL_PIN "" 225 | } 226 | if { [file exists $ORIGINAL_QSF] } { 227 | alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf 228 | } elseif { $is_migrated } { 229 | error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first" 230 | } 231 | } 232 | if { [file exists "$alta_aqf"] } { 233 | alta::tcl_highlight "Using AQF file $alta_aqf.\n" 234 | source "$alta_aqf" 235 | } 236 | if { [file exists "./${DESIGN}.asf"] } { 237 | alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n" 238 | source "./${DESIGN}.asf" 239 | } 240 | 241 | if { $FLOW == "PROBE" } { 242 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 243 | if { !$ret } { exit -1 } 244 | 245 | set force "" 246 | if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" } 247 | eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}" 248 | 249 | } elseif { $FLOW == "CHECK" } { 250 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk] 251 | if { !$ret } { exit -1 } 252 | 253 | if { [file exists "./${DESIGN}.chk"] } { 254 | alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n" 255 | source "./${DESIGN}.chk" 256 | place_design -dry 257 | check_design -rule led_guide 258 | } else { 259 | error "Can not find design CHECK file ${DESIGN}.chk" 260 | } 261 | 262 | } else { 263 | set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io] 264 | if { !$ret } { exit -1 } 265 | 266 | set org_place "" 267 | set load_place "" 268 | set load_route "" 269 | set quiet "" 270 | if { $ORG_PLACE } { set org_place "-org_place" ; } 271 | if { $LOAD_PLACE } { set load_place "-load_place"; } 272 | if { $LOAD_ROUTE } { set load_route "-load_route"; } 273 | eval "place_and_route_design $org_place $load_place $load_route \ 274 | -retry $RETRY $seed_rand $quiet" 275 | } 276 | 277 | date_time 278 | if { $FLOW != "CHECK" } { 279 | if { $FLOW != "PROBE" } { 280 | #report_timing -verbose 1 -file $::alta_work/timing.rpt.gz 281 | report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz 282 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz 283 | report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz 284 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz 285 | 286 | set ta_report_auto_constraints 0 287 | report_timing -fmax -file $::alta_work/fmax.rpt 288 | report_timing -xfer -file $::alta_work/xfer.rpt 289 | set ta_report_auto_constraints $ta_report_auto 290 | 291 | #set ta_coverage_limit "0.95 0.90" 292 | set ta_dump_uncovered 1 293 | report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz 294 | #unset ta_coverage_limit 295 | unset ta_dump_uncovered 296 | 297 | 298 | if { ! [info exists rt_report_timing_fast] } { 299 | set rt_report_timing_fast false 300 | } 301 | if { $rt_report_timing_fast } { 302 | set_timing_corner fast 303 | route_delay -quiet 304 | report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz 305 | report_timing -verbose 2 -setup -brief -file $::alta_work/setup_fast_summary.rpt.gz 306 | report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz 307 | report_timing -verbose 2 -hold -brief -file $::alta_work/hold_fast_summary.rpt.gz 308 | set ta_report_auto_constraints 0 309 | report_timing -fmax -file $::alta_work/fmax_fast.rpt 310 | report_timing -xfer -file $::alta_work/xfer_fast.rpt 311 | set ta_report_auto_constraints $ta_report_auto 312 | } 313 | 314 | write_routed_design "${RESULT_DIR}/${RESULT}_routed.v" 315 | } 316 | 317 | bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin" 318 | bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg" 319 | bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf" 320 | generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \ 321 | -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse 322 | generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \ 323 | -inputs "${RESULT_DIR}/${RESULT}.bin" 324 | generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \ 325 | -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg" 326 | } 327 | 328 | if { [file exists "./${DESIGN}.post.asf"] } { 329 | alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n" 330 | source "./${DESIGN}.post.asf" 331 | } 332 | date_time 333 | exit 334 | 335 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | echo "setup envirenment variable..." 4 | #export PATH="/d/EE/FPGA/AGM/Supra-2022.06.b0-454528eb-win64-all/bin:$PATH" 5 | . supra_vars.sh 6 | 7 | af.exe -B --batch --mode QUARTUS -X "set QUARTUS_SDC true" -X "set FITTING timing_more" -X "set FITTER hybrid" -X "set EFFORT highest" -X "set HOLDX default" -X "set SKEW basic" 8 | 9 | -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/common/DFFx2.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Author: Dong Xiao 2012.10.30 3 | */ 4 | 5 | module DFFx2 6 | ( 7 | input clk, 8 | input nRst, 9 | input D, 10 | output Q 11 | ); 12 | reg D1, D2; 13 | assign Q = D2; 14 | 15 | always @ ( posedge clk, negedge nRst ) begin 16 | if(!nRst) begin 17 | D1 <= 1'b0; 18 | D2 <= 1'b0; 19 | end 20 | else begin 21 | D1 <= D; 22 | D2 <= D1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/common/PowerOnReset.v: -------------------------------------------------------------------------------- 1 | /** 2 | * power on reset 3 | * Author: Dong Xiao 4 | */ 5 | 6 | module PowerOnReset (input iCLK, output reg oRESET); 7 | 8 | reg [19:0] cnt; 9 | 10 | initial begin 11 | cnt <= 20'h00000; 12 | end 13 | 14 | always @(posedge iCLK) begin 15 | if(cnt != 20'hFFFFF) begin 16 | cnt <= cnt + 20'd1; 17 | oRESET <= 1'b0; 18 | end 19 | else 20 | oRESET <= 1'b1; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/common/clkdivider.v: -------------------------------------------------------------------------------- 1 | /** 2 | * clkout = clk/CNT_MAX 3 | * CNT_MAX is even number. 4 | * Author: Dong Xiao 5 | */ 6 | 7 | `timescale 1 ns/ 1 ns 8 | 9 | module clkdivider #( parameter CNT_MAX = 16'd2 ) 10 | ( 11 | input clk, 12 | input nRST, 13 | output reg clkout 14 | ); 15 | reg [15:0] cnt; 16 | 17 | always @( posedge clk, negedge nRST ) begin 18 | if( !nRST ) begin 19 | cnt <= 16'd0; 20 | clkout <= 1'b0; 21 | end else begin 22 | if ( cnt < CNT_MAX/2-1 ) begin 23 | cnt <= cnt + 16'd1; 24 | end else begin 25 | cnt <= 16'd0; 26 | clkout <= ~clkout; 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_AG1280_INTOSC/download.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | echo "setup envirenment variable..." 4 | . supra_vars.sh 5 | 6 | if [ $# -eq 1 ]; then 7 | case $1 in 8 | sram) 9 | echo "Program SRAM of AG1280Q48" 10 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 Blink_AG1280_sram.prg" 11 | ;; 12 | flash) 13 | echo "Program FLASH of AG1280Q48" 14 | af.exe -B -X "set blaster_id 0" -X "source -progress 1000 Blink_AG1280_hybrid.prg" 15 | ;; 16 | erase) 17 | echo "Erase FLASH of AG1280Q48" 18 | af.exe -B -X "set blaster_id 0" -X "set bitgen_usb_speed 3000" -X "exit [catch {erase_flash}]" 19 | ;; 20 | esac 21 | else 22 | echo "Usage $0 [sram|flash|erase]" 23 | fi 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /hdl/Blink_AG256SL100/Blink_AG256SL100.proj: -------------------------------------------------------------------------------- 1 | [MainWindow] 2 | recentFile.0= 3 | 4 | [GuiMigrateSetupPage] 5 | fromDir=../Blink_EPM240T100 6 | design=Blink_EPM240T100 7 | device=AG256SL100 8 | veFile= 9 | ipFiles= 10 | backwardCompatible=false 11 | modeGroup=false 12 | modeQuartus=true 13 | modeSynplicity=false 14 | modeNative=false 15 | 16 | [GuiMigrateRunPage] 17 | isMC=false 18 | count= 19 | jobs= 20 | seed= 21 | retry=0 22 | fitting=6 23 | fitter=4 24 | effort=3 25 | holdx=0 26 | skew=2 27 | skope=0 28 | preset=0 29 | adjust=0 30 | target=0 31 | tuning=0 32 | flow=0 33 | orgPlace=false 34 | quartusSdc=true 35 | probeForce=false 36 | probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2m\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xab\0\0\0\x1\0\0\0\0) 37 | probeCount=5 38 | probe0From= 39 | probe0Pad= 40 | probe1From= 41 | probe1Pad= 42 | probe2From= 43 | probe2Pad= 44 | probe3From= 45 | probe3Pad= 46 | probe4From= 47 | probe4Pad= 48 | corner=0 49 | 50 | [GuiProgramScreen] 51 | hardwareId=0 52 | blasterSpeed=70 53 | prgFile=Blink_EPM240T100.prg 54 | eraseBox=false 55 | cable=0 56 | runAction=program 57 | eraseChip=true 58 | eraseFrom= 59 | eraseTo= 60 | binFile= 61 | readFrom= 62 | readTo= 63 | -------------------------------------------------------------------------------- /hdl/Blink_AG256SL100/README.md: -------------------------------------------------------------------------------- 1 | #使用方法 2 | 3 | AG256SL100芯片P2P兼容EPM245T100芯片，本工程需要配合[Blink_EPM240T100](../Blink_EPM240T100)工程使用。请按以下步骤操作： 4 | 5 | 1. 在Quartus中编译通过[Blink_EPM240T100](../Blink_EPM240T100)工程，做好管脚锁定等各种约束 6 | 2. 在Supra中使用菜单`File->Project->Open Project`打开本目录下的`Blink_AG256SL100.proj`文件 7 | 3. 打开菜单`Tools->Migrate`，检查各个选项，无误后点击`Next`按钮，此时如果没有在Quartus中编译`Blink_EPM240T100`工程会报错 8 | 4. 按照Supra软件的提示，使用Quartus打开**本目录下**的`Blink_EPM240T100.qpf`工程，并运行`af_quartus.tcl`脚本 9 | 这一步会综合工程，并生成`simulation\modelsim`目录下的网表文件供Supra后续布局布线用，因此不用关心Quartus中的器件类型 10 | 5. Supra中点击`Next`，点击`Finish`开始布局布线，等待结束即可 11 | 12 | 整个设计过程由前端的Quartus和后端的Supra共同完成，Quartus用来生成`simulation\modelsim`目录下的网表文件，Supra使用网表文件完成布局布线。 13 | 14 | 15 | -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/Blink.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 32-bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP4CE22F17) Path("./out/") File("Blink.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/Blink.cof: -------------------------------------------------------------------------------- 1 | 2 | 3 | EPCS16 4 | EP4CE6 5 | ./Blink.jic 6 | 1 7 | 1 8 | 7 9 | 10 | Page_0 11 | 1 12 | 13 | out/Blink.sof 14 | 15 | 16 | 5 17 | 0 18 | 19 | 1 20 | 21 | -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/Blink.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2007 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "13.0" 18 | DATE = "17:17:17 June 14, 2011" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "Blink" 24 | -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/Blink.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version 21 | # Date created = 09:27:45 November 30, 2021 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Blink_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | 40 | # Project-Wide Assignments 41 | # ======================== 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 43 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:17:44 DECEMBER 21,2019" 46 | set_global_assignment -name SMART_RECOMPILE ON 47 | set_global_assignment -name VERILOG_FILE common/DFFx2.v 48 | set_global_assignment -name VERILOG_FILE common/clkdivider.v 49 | set_global_assignment -name SDC_FILE Blink.sdc 50 | set_global_assignment -name VERILOG_FILE ipcore_dir/PLL.v 51 | set_global_assignment -name VERILOG_FILE Blink.v 52 | set_global_assignment -name QIP_FILE ipcore_dir/PLL.qip 53 | 54 | # Pin & Location Assignments 55 | # ========================== 56 | set_location_assignment PIN_25 -to CLK 57 | set_location_assignment PIN_77 -to LED[1] 58 | set_location_assignment PIN_76 -to LED[2] 59 | set_location_assignment PIN_98 -to KEY[1] 60 | set_location_assignment PIN_80 -to KEY[2] 61 | set_location_assignment PIN_13 -to M25_DI 62 | set_location_assignment PIN_12 -to M25_CLK 63 | set_location_assignment PIN_8 -to M25_NCS 64 | set_location_assignment PIN_6 -to M25_DO 65 | set_location_assignment PIN_11 -to UART_RX 66 | set_location_assignment PIN_10 -to UART_TX 67 | set_location_assignment PIN_23 -to UART_RTS 68 | set_location_assignment PIN_73 -to CLKO[2] 69 | set_location_assignment PIN_72 -to CLKO[1] 70 | set_location_assignment PIN_71 -to CLKO[0] 71 | 72 | # Classic Timing Assignments 73 | # ========================== 74 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 75 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 76 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON 77 | 78 | # Analysis & Synthesis Assignments 79 | # ================================ 80 | set_global_assignment -name FAMILY "Cyclone IV E" 81 | set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP 82 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 83 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 84 | set_global_assignment -name TOP_LEVEL_ENTITY Blink 85 | 86 | # Fitter Assignments 87 | # ================== 88 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 89 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 90 | set_global_assignment -name DEVICE EP4CE10E22C8 91 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 92 | set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" 93 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" 94 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" 95 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" 96 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" 97 | 98 | # EDA Netlist Writer Assignments 99 | # ============================== 100 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" 101 | 102 | # Assembler Assignments 103 | # ===================== 104 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 105 | 106 | # SignalTap II Assignments 107 | # ======================== 108 | set_global_assignment -name ENABLE_SIGNALTAP OFF 109 | 110 | # Power Estimation Assignments 111 | # ============================ 112 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 113 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 114 | 115 | # Advanced I/O Timing Assignments 116 | # =============================== 117 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 118 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 119 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 120 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 121 | 122 | # start EDA_TOOL_SETTINGS(eda_simulation) 123 | # --------------------------------------- 124 | 125 | # EDA Netlist Writer Assignments 126 | # ============================== 127 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 128 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 129 | set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation 130 | 131 | # end EDA_TOOL_SETTINGS(eda_simulation) 132 | # ------------------------------------- 133 | 134 | # ------------------- 135 | # start ENTITY(Blink) 136 | 137 | # Fitter Assignments 138 | # ================== 139 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY[1] 140 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY[2] 141 | 142 | # start DESIGN_PARTITION(Top) 143 | # --------------------------- 144 | 145 | # Incremental Compilation Assignments 146 | # =================================== 147 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 148 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 149 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 150 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 151 | 152 | # end DESIGN_PARTITION(Top) 153 | # ------------------------- 154 | 155 | # end ENTITY(Blink) 156 | # ----------------- -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/Blink.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************** 2 | # This .sdc file is created by Terasic Tool. 3 | # Users are recommended to modify this file to match users logic. 4 | #************************************************************** 5 | 6 | #************************************************************** 7 | # Create Clock 8 | #************************************************************** 9 | create_clock -period "20 ns" -name {CLK_50M} {CLK_50M} 10 | 11 | #************************************************************** 12 | # Create Generated Clock 13 | #************************************************************** 14 | derive_pll_clocks 15 | 16 | 17 | 18 | #************************************************************** 19 | # Set Clock Latency 20 | #************************************************************** 21 | 22 | 23 | 24 | #************************************************************** 25 | # Set Clock Uncertainty 26 | #************************************************************** 27 | derive_clock_uncertainty 28 | 29 | 30 | 31 | #************************************************************** 32 | # Set Input Delay 33 | #************************************************************** 34 | 35 | 36 | 37 | #************************************************************** 38 | # Set Output Delay 39 | #************************************************************** 40 | 41 | 42 | 43 | #************************************************************** 44 | # Set Clock Groups 45 | #************************************************************** 46 | 47 | 48 | 49 | #************************************************************** 50 | # Set False Path 51 | #************************************************************** 52 | 53 | 54 | 55 | #************************************************************** 56 | # Set Multicycle Path 57 | #************************************************************** 58 | 59 | 60 | 61 | #************************************************************** 62 | # Set Maximum Delay 63 | #************************************************************** 64 | 65 | 66 | 67 | #************************************************************** 68 | # Set Minimum Delay 69 | #************************************************************** 70 | 71 | 72 | 73 | #************************************************************** 74 | # Set Input Transition 75 | #************************************************************** 76 | 77 | 78 | 79 | #************************************************************** 80 | # Set Load 81 | #************************************************************** 82 | 83 | 84 | 85 | -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/Blink.v: -------------------------------------------------------------------------------- 1 | // MegaPill 2 | module Blink ( 3 | input CLK, // 24M Input CLK 4 | 5 | input [2:1] KEY, // Active Low 6 | output [2:1] LED, // Active Low 7 | 8 | // SPI FLASH 9 | output M25_CLK, 10 | output M25_NCS, 11 | output M25_DO, 12 | input M25_DI, 13 | 14 | // UART Port 15 | input UART_RTS, 16 | input UART_RX, 17 | output UART_TX, 18 | 19 | // Test Output 20 | output [2:0] CLKO 21 | ); 22 | wire inclk = CLK; 23 | reg [5:0] reset_init = 6'b0 /* synthesis syn_preserve = 1*/; 24 | wire init = reset_init[5]; 25 | always @ (posedge inclk) begin 26 | if (!init) begin 27 | reset_init <= reset_init + 1'b1; 28 | end 29 | end 30 | 31 | wire PLL_Locked; 32 | wire nRst = PLL_Locked; 33 | wire CLK_40M, CLK_1M, CLK_1k, CLK_1Hz; 34 | wire [2:1] KEYF; 35 | PLL p0( 36 | .areset(!init), 37 | .inclk0(CLK), 38 | .c0(CLK_40M), 39 | .c1(), 40 | .locked(PLL_Locked)); 41 | 42 | clkdivider #(.CNT_MAX(16'd40)) c0 (.clk(CLK_40M), .nRST(nRst), .clkout(CLK_1M)); 43 | clkdivider #(.CNT_MAX(16'd1000)) c1 (.clk(CLK_1M), .nRST(nRst), .clkout(CLK_1k)); 44 | clkdivider #(.CNT_MAX(16'd1000)) c2 (.clk(CLK_1k), .nRST(nRst), .clkout(CLK_1Hz)); 45 | 46 | assign CLKO[0] = CLK_1M; 47 | assign CLKO[1] = CLK_1k; 48 | assign CLKO[2] = CLK_1Hz; 49 | 50 | assign LED[1] = CLK_1Hz & KEYF[1]; 51 | assign LED[2] = ~CLK_1Hz & KEYF[2]; 52 | 53 | // ECHO UART data 54 | assign UART_TX = UART_RX; 55 | 56 | DFFx2 d1(.clk(CLK_40M), .nRst(nRst), .D(KEY[1]), .Q(KEYF[1])); 57 | DFFx2 d2(.clk(CLK_40M), .nRst(nRst), .D(KEY[2]), .Q(KEYF[2])); 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/common/DFFx2.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Author: Dong Xiao 2012.10.30 3 | */ 4 | 5 | module DFFx2 6 | ( 7 | input clk, 8 | input nRst, 9 | input D, 10 | output Q 11 | ); 12 | reg D1, D2; 13 | assign Q = D2; 14 | 15 | always @ ( posedge clk, negedge nRst ) begin 16 | if(!nRst) begin 17 | D1 <= 1'b0; 18 | D2 <= 1'b0; 19 | end 20 | else begin 21 | D1 <= D; 22 | D2 <= D1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/common/clkdivider.v: -------------------------------------------------------------------------------- 1 | /** 2 | * clkout = clk/CNT_MAX 3 | * CNT_MAX is even number. 4 | * Author: Dong Xiao 5 | */ 6 | 7 | `timescale 1 ns/ 1 ns 8 | 9 | module clkdivider #( parameter CNT_MAX = 16'd2 ) 10 | ( 11 | input clk, 12 | input nRST, 13 | output reg clkout 14 | ); 15 | reg [15:0] cnt; 16 | 17 | always @( posedge clk, negedge nRST ) begin 18 | if( !nRST ) begin 19 | cnt <= 16'd0; 20 | clkout <= 1'b0; 21 | end else begin 22 | if ( cnt < CNT_MAX/2-1 ) begin 23 | cnt <= cnt + 16'd1; 24 | end else begin 25 | cnt <= 16'd0; 26 | clkout <= ~clkout; 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/ipcore_dir/PLL.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /hdl/Blink_EP4CE10/ipcore_dir/PLL.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL.ppf"] 5 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/Blink_EPM240T100.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version 21 | # Date created = 09:56:27 October 03, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "09:56:27 October 03, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "Blink_EPM240T100" 31 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/Blink_EPM240T100.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version 21 | # Date created = 19:01:03 November 09, 2022 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Blink_EPM240T100_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | 40 | # Project-Wide Assignments 41 | # ======================== 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:56:27 OCTOBER 03, 2020" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name VERILOG_FILE common/debouncer.v 47 | set_global_assignment -name VERILOG_FILE common/UART_TX.v 48 | set_global_assignment -name VERILOG_FILE common/UART_RX.v 49 | set_global_assignment -name QIP_FILE IP/UFM_SPI.qip 50 | set_global_assignment -name VERILOG_FILE common/PowerOnReset.v 51 | set_global_assignment -name VERILOG_FILE common/DFFx2.v 52 | set_global_assignment -name VERILOG_FILE common/clkdivider.v 53 | set_global_assignment -name VERILOG_FILE Blink_EPM240T100.v 54 | 55 | # Pin & Location Assignments 56 | # ========================== 57 | set_location_assignment PIN_12 -to CLK 58 | set_location_assignment PIN_8 -to CLKO[2] 59 | set_location_assignment PIN_7 -to CLKO[1] 60 | set_location_assignment PIN_6 -to CLKO[0] 61 | set_location_assignment PIN_58 -to LED[4] 62 | set_location_assignment PIN_61 -to LED[3] 63 | set_location_assignment PIN_62 -to LED[2] 64 | set_location_assignment PIN_64 -to LED[1] 65 | set_location_assignment PIN_57 -to KEY[2] 66 | set_location_assignment PIN_66 -to KEY[1] 67 | set_location_assignment PIN_55 -to RXD 68 | set_location_assignment PIN_56 -to TXD 69 | set_location_assignment PIN_1 -to NCS 70 | set_location_assignment PIN_2 -to SCK 71 | set_location_assignment PIN_3 -to SI 72 | set_location_assignment PIN_4 -to SO 73 | 74 | # Classic Timing Assignments 75 | # ========================== 76 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 77 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 78 | 79 | # Analysis & Synthesis Assignments 80 | # ================================ 81 | set_global_assignment -name FAMILY "MAX II" 82 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 83 | set_global_assignment -name TOP_LEVEL_ENTITY Blink_EPM240T100 84 | 85 | # Fitter Assignments 86 | # ================== 87 | set_global_assignment -name DEVICE EPM240T100C5 88 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" 89 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 90 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 91 | 92 | # Assembler Assignments 93 | # ===================== 94 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 95 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" 96 | 97 | # ------------------------------ 98 | # start ENTITY(Blink_EPM240T100) 99 | 100 | # Fitter Assignments 101 | # ================== 102 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RXD 103 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY[2] 104 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY[1] 105 | 106 | # start DESIGN_PARTITION(Top) 107 | # --------------------------- 108 | 109 | # Incremental Compilation Assignments 110 | # =================================== 111 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 112 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 113 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 114 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 115 | 116 | # end DESIGN_PARTITION(Top) 117 | # ------------------------- 118 | 119 | # end ENTITY(Blink_EPM240T100) 120 | # ---------------------------- -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/Blink_EPM240T100.v: -------------------------------------------------------------------------------- 1 | module Blink_EPM240T100 ( 2 | input CLK, 3 | 4 | input RXD, 5 | output TXD, 6 | 7 | input NCS, 8 | input SCK, 9 | input SI, 10 | output SO, 11 | 12 | input [2:1] KEY, 13 | 14 | output [2:0] CLKO, 15 | output [4:1] LED 16 | ); 17 | 18 | wire nRst; 19 | PowerOnReset por0(.iCLK(CLK), .oRESET(nRst)); 20 | 21 | wire CLK_UFM, CLK_1M, CLK_1K, CLK_1Hz; 22 | clkdivider #(.CNT_MAX(16'd24)) c0 (.clk(CLK), .nRST(nRst), .clkout(CLK_1M)); 23 | clkdivider #(.CNT_MAX(16'd1000)) c1 (.clk(CLK_1M), .nRST(nRst), .clkout(CLK_1K)); 24 | clkdivider #(.CNT_MAX(16'd1000)) c2 (.clk(CLK_1K), .nRST(nRst), .clkout(CLK_1Hz)); 25 | 26 | // two key 27 | wire [2:1] key_o; 28 | debouncer d1(.clk(CLK), .rst_n(nRst), .key_i(KEY[1]), .key_o(key_o[1])); 29 | debouncer d2(.clk(CLK), .rst_n(nRst), .key_i(KEY[2]), .key_o(key_o[2])); 30 | 31 | reg [7:0] ctrl, TX_Byte; 32 | reg TX_DV; 33 | wire [7:0] RX_Byte; 34 | wire RX_DV, TX_Active; 35 | 36 | // 24e6/208 = 115384.6 37 | UART_RX #(.CLKS_PER_BIT(208)) r0( 38 | .i_Rst_L(nRst), 39 | .i_Clock(CLK), 40 | .i_RX_Serial(RXD), 41 | .o_RX_DV(RX_DV), 42 | .o_RX_Byte(RX_Byte) 43 | ); 44 | UART_TX #(.CLKS_PER_BIT(208)) t0( 45 | .i_Rst_L(nRst), 46 | .i_Clock(CLK), 47 | .i_TX_DV(TX_DV), 48 | .i_TX_Byte(TX_Byte), 49 | .o_TX_Active(TX_Active), 50 | .o_TX_Serial(TXD), 51 | .o_TX_Done(TX_Done) 52 | ); 53 | 54 | always @(posedge CLK, negedge nRst) begin 55 | if(~nRst) begin 56 | ctrl <= 8'h00; 57 | TX_Byte <= 8'h00; 58 | TX_DV <= 1'b0; 59 | end 60 | else begin 61 | if (RX_DV) begin 62 | ctrl <= RX_Byte; 63 | TX_Byte <= {2'b00, key_o[2:1], RX_Byte[3:0]}; 64 | TX_DV <= 1'b1; 65 | end 66 | else if(TX_Done) begin 67 | TX_DV <= 1'b0; 68 | end 69 | end 70 | end 71 | 72 | assign CLKO[2] = TX_Active; 73 | assign CLKO[1] = ctrl[5]; 74 | assign CLKO[0] = ctrl[4]; 75 | 76 | assign LED[4] = CLK_1Hz; 77 | assign LED[3] = ~CLK_1Hz; 78 | assign LED[2] = ctrl[1]; 79 | assign LED[1] = ctrl[0]; 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/IP/OSC_INT.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "MAX II/MAX V oscillator" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "OSC_INT.v"] 4 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/IP/OSC_INT.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %MAX II/MAX V oscillator% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTUFM_OSC 5 | 6 | // ============================================================ 7 | // File Name: OSC_INT.v 8 | // Megafunction Name(s): 9 | // ALTUFM_OSC 10 | // 11 | // Simulation Library Files(s): 12 | // maxii 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | //altufm_osc CBX_AUTO_BLACKBOX="ALL" OSC_FREQUENCY=180000 osc oscena DEVICE_FAMILY="MAX II" 37 | //VERSION_BEGIN 13.0 cbx_altufm_osc 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END 38 | // synthesis VERILOG_INPUT_VERSION VERILOG_2001 39 | // altera message_off 10463 40 | 41 | 42 | //synthesis_resources = maxii_ufm 1 43 | //synopsys translate_off 44 | `timescale 1 ps / 1 ps 45 | //synopsys translate_on 46 | module OSC_INT_altufm_osc_518 47 | ( 48 | osc, 49 | oscena) ; 50 | output osc; 51 | input oscena; 52 | 53 | wire wire_maxii_ufm_block1_osc; 54 | 55 | maxii_ufm maxii_ufm_block1 56 | ( 57 | .arclk(1'b0), 58 | .ardin(1'b0), 59 | .arshft(1'b0), 60 | .bgpbusy(), 61 | .busy(), 62 | .drclk(1'b0), 63 | .drdin(1'b0), 64 | .drdout(), 65 | .drshft(1'b1), 66 | .osc(wire_maxii_ufm_block1_osc), 67 | .oscena(oscena) 68 | `ifndef FORMAL_VERIFICATION 69 | // synopsys translate_off 70 | `endif 71 | , 72 | .erase(1'b0), 73 | .program(1'b0) 74 | `ifndef FORMAL_VERIFICATION 75 | // synopsys translate_on 76 | `endif 77 | // synopsys translate_off 78 | , 79 | .ctrl_bgpbusy(1'b0), 80 | .devclrn(1'b1), 81 | .devpor(1'b1), 82 | .sbdin(1'b0), 83 | .sbdout() 84 | // synopsys translate_on 85 | ); 86 | defparam 87 | maxii_ufm_block1.address_width = 9, 88 | maxii_ufm_block1.osc_sim_setting = 180000, 89 | maxii_ufm_block1.lpm_type = "maxii_ufm"; 90 | assign 91 | osc = wire_maxii_ufm_block1_osc; 92 | endmodule //OSC_INT_altufm_osc_518 93 | //VALID FILE 94 | 95 | 96 | // synopsys translate_off 97 | `timescale 1 ps / 1 ps 98 | // synopsys translate_on 99 | module OSC_INT ( 100 | oscena, 101 | osc); 102 | 103 | input oscena; 104 | output osc; 105 | 106 | wire sub_wire0; 107 | wire osc = sub_wire0; 108 | 109 | OSC_INT_altufm_osc_518 OSC_INT_altufm_osc_518_component ( 110 | .oscena (oscena), 111 | .osc (sub_wire0)); 112 | 113 | endmodule 114 | 115 | // ============================================================ 116 | // CNX file retrieval info 117 | // ============================================================ 118 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 119 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" 120 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED" 121 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 122 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_osc" 123 | // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" 124 | // Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc" 125 | // Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0 126 | // Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena" 127 | // Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0 128 | // Retrieval info: GEN_FILE: TYPE_NORMAL OSC_INT.v TRUE FALSE 129 | // Retrieval info: GEN_FILE: TYPE_NORMAL OSC_INT.qip TRUE FALSE 130 | // Retrieval info: GEN_FILE: TYPE_NORMAL OSC_INT.bsf FALSE TRUE 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL OSC_INT_inst.v FALSE TRUE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL OSC_INT_bb.v FALSE TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL OSC_INT.inc FALSE TRUE 134 | // Retrieval info: GEN_FILE: TYPE_NORMAL OSC_INT.cmp FALSE TRUE 135 | // Retrieval info: LIB_FILE: maxii 136 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/IP/UFM_SPI.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTUFM_SPI" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM_SPI.v"] 4 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/common/DFFx2.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Author: Dong Xiao 2012.10.30 3 | */ 4 | 5 | module DFFx2 6 | ( 7 | input clk, 8 | input nRst, 9 | input D, 10 | output Q 11 | ); 12 | reg D1, D2; 13 | assign Q = D2; 14 | 15 | always @ ( posedge clk, negedge nRst ) begin 16 | if(!nRst) begin 17 | D1 <= 1'b0; 18 | D2 <= 1'b0; 19 | end 20 | else begin 21 | D1 <= D; 22 | D2 <= D1; 23 | end 24 | end 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/common/PowerOnReset.v: -------------------------------------------------------------------------------- 1 | /** 2 | * power on reset 3 | * Author: Dong Xiao 4 | */ 5 | 6 | module PowerOnReset (input iCLK, output reg oRESET); 7 | 8 | reg [19:0] cnt; 9 | 10 | initial begin 11 | cnt <= 20'h00000; 12 | end 13 | 14 | always @(posedge iCLK) begin 15 | if(cnt != 20'hFFFFF) begin 16 | cnt <= cnt + 20'd1; 17 | oRESET <= 1'b0; 18 | end 19 | else 20 | oRESET <= 1'b1; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/common/UART_RX.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // Author: Russell Merrick 3 | ////////////////////////////////////////////////////////////////////// 4 | // Description: This file contains the UART Receiver. This receiver is 5 | // able to receive 8 bits of serial data, one start bit, one 6 | // stop bit, and no parity bit. When receive is complete 7 | // o_RX_DV will be driven high for one clock cycle. 8 | // 9 | // Parameters: Set Parameter CLKS_PER_BIT as follows: 10 | // CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART) 11 | // Example: 25 MHz Clock, 115200 baud UART 12 | // (25000000)/(115200) = 217 13 | ////////////////////////////////////////////////////////////////////////////// 14 | 15 | module UART_RX 16 | #(parameter CLKS_PER_BIT = 217) 17 | ( 18 | input i_Rst_L, 19 | input i_Clock, 20 | input i_RX_Serial, 21 | output reg o_RX_DV, 22 | output reg [7:0] o_RX_Byte 23 | ); 24 | 25 | localparam IDLE = 3'b000; 26 | localparam RX_START_BIT = 3'b001; 27 | localparam RX_DATA_BITS = 3'b010; 28 | localparam RX_STOP_BIT = 3'b011; 29 | localparam CLEANUP = 3'b100; 30 | 31 | reg [$clog2(CLKS_PER_BIT)-1:0] r_Clock_Count; 32 | reg [2:0] r_Bit_Index; //8 bits total 33 | reg [2:0] r_SM_Main; 34 | 35 | 36 | // Purpose: Control RX state machine 37 | always @(posedge i_Clock or negedge i_Rst_L) 38 | begin 39 | if (~i_Rst_L) 40 | begin 41 | r_SM_Main <= 3'b000; 42 | o_RX_DV <= 1'b0; 43 | end 44 | else 45 | begin 46 | case (r_SM_Main) 47 | IDLE : 48 | begin 49 | o_RX_DV <= 1'b0; 50 | r_Clock_Count <= 0; 51 | r_Bit_Index <= 0; 52 | 53 | if (i_RX_Serial == 1'b0) // Start bit detected 54 | r_SM_Main <= RX_START_BIT; 55 | else 56 | r_SM_Main <= IDLE; 57 | end 58 | 59 | // Check middle of start bit to make sure it's still low 60 | RX_START_BIT : 61 | begin 62 | if (r_Clock_Count == (CLKS_PER_BIT-1)/2) 63 | begin 64 | if (i_RX_Serial == 1'b0) 65 | begin 66 | r_Clock_Count <= 0; // reset counter, found the middle 67 | r_SM_Main <= RX_DATA_BITS; 68 | end 69 | else 70 | r_SM_Main <= IDLE; 71 | end 72 | else 73 | begin 74 | r_Clock_Count <= r_Clock_Count + 1; 75 | r_SM_Main <= RX_START_BIT; 76 | end 77 | end // case: RX_START_BIT 78 | 79 | 80 | // Wait CLKS_PER_BIT-1 clock cycles to sample serial data 81 | RX_DATA_BITS : 82 | begin 83 | if (r_Clock_Count < CLKS_PER_BIT-1) 84 | begin 85 | r_Clock_Count <= r_Clock_Count + 1; 86 | r_SM_Main <= RX_DATA_BITS; 87 | end 88 | else 89 | begin 90 | r_Clock_Count <= 0; 91 | o_RX_Byte[r_Bit_Index] <= i_RX_Serial; 92 | 93 | // Check if we have received all bits 94 | if (r_Bit_Index < 7) 95 | begin 96 | r_Bit_Index <= r_Bit_Index + 1; 97 | r_SM_Main <= RX_DATA_BITS; 98 | end 99 | else 100 | begin 101 | r_Bit_Index <= 0; 102 | r_SM_Main <= RX_STOP_BIT; 103 | end 104 | end 105 | end // case: RX_DATA_BITS 106 | 107 | 108 | // Receive Stop bit. Stop bit = 1 109 | RX_STOP_BIT : 110 | begin 111 | // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish 112 | if (r_Clock_Count < CLKS_PER_BIT-1) 113 | begin 114 | r_Clock_Count <= r_Clock_Count + 1; 115 | r_SM_Main <= RX_STOP_BIT; 116 | end 117 | else 118 | begin 119 | o_RX_DV <= 1'b1; 120 | r_Clock_Count <= 0; 121 | r_SM_Main <= CLEANUP; 122 | end 123 | end // case: RX_STOP_BIT 124 | 125 | 126 | // Stay here 1 clock 127 | CLEANUP : 128 | begin 129 | r_SM_Main <= IDLE; 130 | o_RX_DV <= 1'b0; 131 | end 132 | 133 | 134 | default : 135 | r_SM_Main <= IDLE; 136 | 137 | endcase 138 | end // else: !if(~i_Rst_L) 139 | end // always @ (posedge i_Clock or negedge i_Rst_L) 140 | 141 | endmodule // UART_RX 142 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/common/UART_TX.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // Author: Russell Merrick 3 | ////////////////////////////////////////////////////////////////////// 4 | // This file contains the UART Transmitter. This transmitter is able 5 | // to transmit 8 bits of serial data, one start bit, one stop bit, 6 | // and no parity bit. When transmit is complete o_Tx_done will be 7 | // driven high for one clock cycle. 8 | // 9 | // Set Parameter CLKS_PER_BIT as follows: 10 | // CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART) 11 | // Example: 25 MHz Clock, 115200 baud UART 12 | // (25000000)/(115200) = 217 13 | 14 | module UART_TX 15 | #(parameter CLKS_PER_BIT = 217) 16 | ( 17 | input i_Rst_L, 18 | input i_Clock, 19 | input i_TX_DV, 20 | input [7:0] i_TX_Byte, 21 | output reg o_TX_Active, 22 | output reg o_TX_Serial, 23 | output reg o_TX_Done 24 | ); 25 | 26 | localparam IDLE = 3'b000; 27 | localparam TX_START_BIT = 3'b001; 28 | localparam TX_DATA_BITS = 3'b010; 29 | localparam TX_STOP_BIT = 3'b011; 30 | localparam CLEANUP = 3'b100; 31 | 32 | reg [2:0] r_SM_Main; 33 | reg [$clog2(CLKS_PER_BIT):0] r_Clock_Count; 34 | reg [2:0] r_Bit_Index; 35 | reg [7:0] r_TX_Data; 36 | 37 | 38 | // Purpose: Control TX state machine 39 | always @(posedge i_Clock or negedge i_Rst_L) 40 | begin 41 | if (~i_Rst_L) 42 | begin 43 | r_SM_Main <= 3'b000; 44 | o_TX_Done <= 1'b0; 45 | end 46 | else 47 | begin 48 | case (r_SM_Main) 49 | IDLE : 50 | begin 51 | o_TX_Serial <= 1'b1; // Drive Line High for Idle 52 | o_TX_Done <= 1'b0; 53 | r_Clock_Count <= 0; 54 | r_Bit_Index <= 0; 55 | 56 | if (i_TX_DV == 1'b1) 57 | begin 58 | o_TX_Active <= 1'b1; 59 | r_TX_Data <= i_TX_Byte; 60 | r_SM_Main <= TX_START_BIT; 61 | end 62 | else 63 | r_SM_Main <= IDLE; 64 | end // case: IDLE 65 | 66 | 67 | // Send out Start Bit. Start bit = 0 68 | TX_START_BIT : 69 | begin 70 | o_TX_Serial <= 1'b0; 71 | 72 | // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish 73 | if (r_Clock_Count < CLKS_PER_BIT-1) 74 | begin 75 | r_Clock_Count <= r_Clock_Count + 1; 76 | r_SM_Main <= TX_START_BIT; 77 | end 78 | else 79 | begin 80 | r_Clock_Count <= 0; 81 | r_SM_Main <= TX_DATA_BITS; 82 | end 83 | end // case: TX_START_BIT 84 | 85 | 86 | // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish 87 | TX_DATA_BITS : 88 | begin 89 | o_TX_Serial <= r_TX_Data[r_Bit_Index]; 90 | 91 | if (r_Clock_Count < CLKS_PER_BIT-1) 92 | begin 93 | r_Clock_Count <= r_Clock_Count + 1; 94 | r_SM_Main <= TX_DATA_BITS; 95 | end 96 | else 97 | begin 98 | r_Clock_Count <= 0; 99 | 100 | // Check if we have sent out all bits 101 | if (r_Bit_Index < 7) 102 | begin 103 | r_Bit_Index <= r_Bit_Index + 1; 104 | r_SM_Main <= TX_DATA_BITS; 105 | end 106 | else 107 | begin 108 | r_Bit_Index <= 0; 109 | r_SM_Main <= TX_STOP_BIT; 110 | end 111 | end 112 | end // case: TX_DATA_BITS 113 | 114 | 115 | // Send out Stop bit. Stop bit = 1 116 | TX_STOP_BIT : 117 | begin 118 | o_TX_Serial <= 1'b1; 119 | 120 | // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish 121 | if (r_Clock_Count < CLKS_PER_BIT-1) 122 | begin 123 | r_Clock_Count <= r_Clock_Count + 1; 124 | r_SM_Main <= TX_STOP_BIT; 125 | end 126 | else 127 | begin 128 | o_TX_Done <= 1'b1; 129 | r_Clock_Count <= 0; 130 | r_SM_Main <= CLEANUP; 131 | o_TX_Active <= 1'b0; 132 | end 133 | end // case: TX_STOP_BIT 134 | 135 | 136 | // Stay here 1 clock 137 | CLEANUP : 138 | begin 139 | r_SM_Main <= IDLE; 140 | end 141 | 142 | 143 | default : 144 | r_SM_Main <= IDLE; 145 | 146 | endcase 147 | end // else: !if(~i_Rst_L) 148 | end // always @ (posedge i_Clock or negedge i_Rst_L) 149 | 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/common/UART_To_Bus8.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Engineer: Russell Merrick 3 | // Description: Creates an interface from a UART to the 8-bit wide Bus 4 | // Allows reading and writing of registers. 5 | // Module uses 8-bit read/write data, Addr uses byte-indexing 6 | // 7 | // Commands: 8 | // rd {4 Hex Digit Addr} {CR} 9 | // Will perform a Bus Read and report the data back. 10 | // wr {4 Hex Digit Addr} {4 Digit Hex Data} {CR} 11 | // Will perform a Bus Write of the input data. 12 | // e.g. 13 | // rd 14 {CR} reads from addr 0x14 14 | // wr 5A 6 {CR} writes 0x6 to addr 0x5A 15 | // 16 | // Note: This module will only assert ONE chip-select! If UART needs 17 | // to talk to multiple modules, chip-select decoding must be 18 | // done at a higher level. 19 | // 20 | // Parameters: CLKS_PER_BIT - Set to (Bus Clk Freq)/(UART Freq) 21 | // Example: 25 MHz Bus Clock, 115200 baud UART 22 | // (25000000)/(115200) = 217 23 | ////////////////////////////////////////////////////////////////////////////// 24 | 25 | 26 | module UART_To_Bus8 #(parameter CLKS_PER_BIT = 217) 27 | (input i_Bus_Rst_L, 28 | input i_Bus_Clk, 29 | output reg o_Bus_CS, 30 | output reg o_Bus_Wr_Rd_n, 31 | output reg [15:0] o_Bus_Addr8, 32 | output reg [7:0] o_Bus_Wr_Data, 33 | input [7:0] i_Bus_Rd_Data, 34 | input i_Bus_Rd_DV, 35 | // 36 | input i_UART_RX, 37 | output o_TX_Active, 38 | output o_TX_Data); 39 | 40 | // Put in a better location 41 | localparam ASCII_BS = 8'h8; 42 | localparam ASCII_LF = 8'hA; 43 | localparam ASCII_CR = 8'hD; 44 | localparam ASCII_Sp = 8'h20; 45 | localparam ASCII_Ep = 8'h21; 46 | localparam ASCII_0 = 8'h30; 47 | localparam ASCII_1 = 8'h31; 48 | localparam ASCII_2 = 8'h32; 49 | localparam ASCII_3 = 8'h33; 50 | localparam ASCII_4 = 8'h34; 51 | localparam ASCII_5 = 8'h35; 52 | localparam ASCII_6 = 8'h36; 53 | localparam ASCII_7 = 8'h37; 54 | localparam ASCII_8 = 8'h38; 55 | localparam ASCII_9 = 8'h39; 56 | localparam ASCII_a = 8'h61; 57 | localparam ASCII_b = 8'h62; 58 | localparam ASCII_c = 8'h63; 59 | localparam ASCII_d = 8'h64; 60 | localparam ASCII_e = 8'h65; 61 | localparam ASCII_f = 8'h66; 62 | localparam ASCII_g = 8'h67; 63 | localparam ASCII_h = 8'h68; 64 | localparam ASCII_i = 8'h69; 65 | localparam ASCII_j = 8'h6A; 66 | localparam ASCII_k = 8'h6B; 67 | localparam ASCII_l = 8'h6C; 68 | localparam ASCII_m = 8'h6D; 69 | localparam ASCII_n = 8'h6E; 70 | localparam ASCII_o = 8'h6F; 71 | localparam ASCII_p = 8'h70; 72 | localparam ASCII_q = 8'h71; 73 | localparam ASCII_r = 8'h72; 74 | localparam ASCII_s = 8'h73; 75 | localparam ASCII_t = 8'h74; 76 | localparam ASCII_u = 8'h75; 77 | localparam ASCII_v = 8'h76; 78 | localparam ASCII_w = 8'h77; 79 | localparam ASCII_x = 8'h78; 80 | localparam ASCII_y = 8'h79; 81 | localparam ASCII_z = 8'h7A; 82 | localparam ASCII_A = 8'h41; 83 | localparam ASCII_B = 8'h42; 84 | localparam ASCII_C = 8'h43; 85 | localparam ASCII_D = 8'h44; 86 | localparam ASCII_E = 8'h45; 87 | localparam ASCII_F = 8'h46; 88 | localparam ASCII_G = 8'h47; 89 | localparam ASCII_H = 8'h48; 90 | localparam ASCII_I = 8'h49; 91 | localparam ASCII_J = 8'h4A; 92 | localparam ASCII_K = 8'h4B; 93 | localparam ASCII_L = 8'h4C; 94 | localparam ASCII_M = 8'h4D; 95 | localparam ASCII_N = 8'h4E; 96 | localparam ASCII_O = 8'h4F; 97 | localparam ASCII_P = 8'h50; 98 | localparam ASCII_Q = 8'h51; 99 | localparam ASCII_R = 8'h52; 100 | localparam ASCII_S = 8'h53; 101 | localparam ASCII_T = 8'h54; 102 | localparam ASCII_U = 8'h55; 103 | localparam ASCII_V = 8'h56; 104 | localparam ASCII_W = 8'h57; 105 | localparam ASCII_X = 8'h58; 106 | localparam ASCII_Y = 8'h59; 107 | localparam ASCII_Z = 8'h5A; 108 | 109 | localparam CMD_MAX = 12; 110 | 111 | // State Machine States 112 | localparam IDLE = 3'b000; 113 | localparam TX_START = 3'b001; 114 | localparam TX_WAIT_READY = 3'b010; 115 | localparam TX_DONE = 3'b011; 116 | localparam TX_WAIT_DONE = 3'b100; 117 | 118 | reg [2:0] r_SM_Main; 119 | 120 | // TX/RX Command Signals 121 | reg [7:0] r_RX_Cmd_Array[0:CMD_MAX-1], r_TX_Cmd_Array[0:CMD_MAX-1]; 122 | reg r_RX_Cmd_Done; 123 | reg r_RX_Cmd_Rd, r_RX_Cmd_Wr; 124 | reg r_RX_Cmd_Error; 125 | reg [15:0] r_RX_Cmd_Addr; 126 | reg [7:0] r_RX_Cmd_Data; 127 | reg r_TX_Cmd_Start; 128 | reg [3:0] r_Temp_Index; 129 | 130 | 131 | reg [$clog2(CMD_MAX)-1:0] r_RX_Index; 132 | reg [$clog2(CMD_MAX)-1:0] r_TX_Index; 133 | reg [$clog2(CMD_MAX)-1:0] r_TX_Cmd_Length; 134 | reg [$clog2(CMD_MAX)-1:0] r_RX_Cmd_Length; 135 | 136 | // Low Level UART TX/RX Signals 137 | wire w_RX_DV; 138 | wire [7:0] w_RX_Byte; 139 | wire w_TX_Done; 140 | wire w_TX_Active; 141 | wire [7:0] w_TX_Byte_Mux; 142 | reg r_TX_DV; 143 | reg [7:0] r_TX_Byte; 144 | 145 | 146 | // Convert ASCII digit to Hex (upper and lowercase supported) 147 | // No error checking on invalid inputs. 148 | function [3:0] f_ASCII_To_Hex; 149 | input [7:0] i_ASCII; 150 | begin 151 | if (i_ASCII == ASCII_a || i_ASCII == ASCII_A) 152 | f_ASCII_To_Hex = 4'hA; 153 | else if (i_ASCII == ASCII_b || i_ASCII == ASCII_B) 154 | f_ASCII_To_Hex = 4'hB; 155 | else if (i_ASCII == ASCII_c || i_ASCII == ASCII_C) 156 | f_ASCII_To_Hex = 4'hC; 157 | else if (i_ASCII == ASCII_d || i_ASCII == ASCII_D) 158 | f_ASCII_To_Hex = 4'hD; 159 | else if (i_ASCII == ASCII_e || i_ASCII == ASCII_E) 160 | f_ASCII_To_Hex = 4'hE; 161 | else if (i_ASCII == ASCII_f || i_ASCII == ASCII_F) 162 | f_ASCII_To_Hex = 4'hF; 163 | else 164 | f_ASCII_To_Hex = i_ASCII[3:0]; 165 | end 166 | endfunction 167 | 168 | 169 | // Convert 4-bit Hex Digit to ASCII digit/letter (lowercase) 170 | function [7:0] f_Hex_To_ASCII; 171 | input [3:0] i_Hex; 172 | begin 173 | if (i_Hex == 4'hA) 174 | f_Hex_To_ASCII = ASCII_a; 175 | else if (i_Hex == 4'hB) 176 | f_Hex_To_ASCII = ASCII_b; 177 | else if (i_Hex == 4'hC) 178 | f_Hex_To_ASCII = ASCII_c; 179 | else if (i_Hex == 4'hD) 180 | f_Hex_To_ASCII = ASCII_d; 181 | else if (i_Hex == 4'hE) 182 | f_Hex_To_ASCII = ASCII_e; 183 | else if (i_Hex == 4'hF) 184 | f_Hex_To_ASCII = ASCII_f; 185 | else 186 | f_Hex_To_ASCII = {4'h3, i_Hex[3:0]}; 187 | end 188 | endfunction 189 | 190 | 191 | 192 | UART_RX #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_RX_Inst 193 | (.i_Rst_L(i_Bus_Rst_L), 194 | .i_Clock(i_Bus_Clk), 195 | .i_RX_Serial(i_UART_RX), 196 | .o_RX_DV(w_RX_DV), 197 | .o_RX_Byte(w_RX_Byte) 198 | ); 199 | 200 | UART_TX #(.CLKS_PER_BIT(CLKS_PER_BIT)) UART_TX_Inst 201 | (.i_Rst_L(i_Bus_Rst_L), 202 | .i_Clock(i_Bus_Clk), 203 | .i_TX_DV(r_TX_DV | w_RX_DV), 204 | .i_TX_Byte(w_TX_Byte_Mux), 205 | .o_TX_Active(w_TX_Active), 206 | .o_TX_Serial(o_TX_Data), 207 | .o_TX_Done(w_TX_Done) 208 | ); 209 | 210 | assign w_TX_Byte_Mux = w_RX_DV ? w_RX_Byte : r_TX_Byte; 211 | 212 | // Purpose: Buffer up a received command. Will assert done signal when an 213 | // ASCII line feed is received via the UART. 214 | always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) 215 | begin 216 | if (~i_Bus_Rst_L) 217 | begin 218 | r_RX_Index <= 0; 219 | end 220 | else 221 | begin 222 | r_RX_Cmd_Done <= 1'b0; // Default Assignment 223 | 224 | if (w_RX_DV == 1'b1) 225 | begin 226 | r_RX_Cmd_Array[r_RX_Index] <= w_RX_Byte; 227 | 228 | // See if most recently received command is CR (Command Done) 229 | if (w_RX_Byte == ASCII_CR) 230 | begin 231 | r_RX_Cmd_Done <= 1'b1; 232 | r_RX_Index <= 0; 233 | r_RX_Cmd_Length <= r_RX_Index; 234 | end 235 | 236 | // See if most recently received comamnd is Backspace 237 | // If so, move pointer backward 238 | else if (w_RX_Byte == ASCII_BS) 239 | r_RX_Index <= r_RX_Index - 1; 240 | 241 | // Normal Data 242 | else 243 | r_RX_Index <= r_RX_Index + 1; 244 | end // if (w_RX_DV == 1'b1) 245 | end // else: !if(~i_Bus_Rst_L) 246 | end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L) 247 | 248 | 249 | 250 | // Decode received command. Parses command and acts accordingly. 251 | always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) 252 | begin 253 | if (~i_Bus_Rst_L) 254 | begin 255 | r_RX_Cmd_Rd <= 1'b0; 256 | r_RX_Cmd_Wr <= 1'b0; 257 | r_RX_Cmd_Error <= 1'b0; 258 | end 259 | 260 | else 261 | begin 262 | // Default Assignments 263 | r_RX_Cmd_Rd <= 1'b0; 264 | r_RX_Cmd_Wr <= 1'b0; 265 | r_RX_Cmd_Error <= 1'b0; 266 | 267 | if (r_RX_Cmd_Done == 1'b1) 268 | begin 269 | 270 | // Decode Read Command 271 | if (r_RX_Cmd_Array[0] == ASCII_r && 272 | r_RX_Cmd_Array[1] == ASCII_d && 273 | r_RX_Cmd_Array[2] == ASCII_Sp) 274 | r_RX_Cmd_Rd <= 1'b1; 275 | 276 | // Decode Write Command 277 | else if (r_RX_Cmd_Array[0] == ASCII_w && 278 | r_RX_Cmd_Array[1] == ASCII_r && 279 | r_RX_Cmd_Array[2] == ASCII_Sp) 280 | r_RX_Cmd_Wr <= 1'b1; 281 | 282 | // Decode Failed, Erroneous Command 283 | else 284 | r_RX_Cmd_Error <= 1'b1; 285 | 286 | 287 | // Can parse addresses that are 1-4 digits long 288 | if (r_RX_Cmd_Array[4] == ASCII_Sp || r_RX_Cmd_Array[4] == ASCII_CR) 289 | begin 290 | r_Temp_Index = 5; 291 | r_RX_Cmd_Addr <= {12'h0, f_ASCII_To_Hex(r_RX_Cmd_Array[3])}; 292 | end 293 | else if (r_RX_Cmd_Array[5] == ASCII_Sp || r_RX_Cmd_Array[5] == ASCII_CR) 294 | begin 295 | r_Temp_Index = 6; 296 | r_RX_Cmd_Addr <= {8'h0, f_ASCII_To_Hex(r_RX_Cmd_Array[3]), 297 | f_ASCII_To_Hex(r_RX_Cmd_Array[4])}; 298 | end 299 | else if (r_RX_Cmd_Array[6] == ASCII_Sp || r_RX_Cmd_Array[6] == ASCII_CR) 300 | begin 301 | r_Temp_Index = 7; 302 | r_RX_Cmd_Addr <= {4'h0, f_ASCII_To_Hex(r_RX_Cmd_Array[3]), 303 | f_ASCII_To_Hex(r_RX_Cmd_Array[4]), 304 | f_ASCII_To_Hex(r_RX_Cmd_Array[5])}; 305 | end 306 | else 307 | begin 308 | r_Temp_Index = 8; 309 | r_RX_Cmd_Addr <= {f_ASCII_To_Hex(r_RX_Cmd_Array[3]), 310 | f_ASCII_To_Hex(r_RX_Cmd_Array[4]), 311 | f_ASCII_To_Hex(r_RX_Cmd_Array[5]), 312 | f_ASCII_To_Hex(r_RX_Cmd_Array[6])}; 313 | end 314 | 315 | // Process Data Part, can have 1 or 2 chars 316 | if ($unsigned(r_RX_Cmd_Length)-$unsigned(r_Temp_Index) == 2) 317 | r_RX_Cmd_Data <= {f_ASCII_To_Hex(r_RX_Cmd_Array[r_Temp_Index]), 318 | f_ASCII_To_Hex(r_RX_Cmd_Array[r_Temp_Index+1])}; 319 | 320 | else 321 | r_RX_Cmd_Data <= {4'h0, f_ASCII_To_Hex(r_RX_Cmd_Array[r_Temp_Index])}; 322 | 323 | 324 | end // if (r_RX_Cmd_Done == 1'b1) 325 | end // else: !if(~i_Bus_Rst_L) 326 | end // always @ (posege i_Bus_Clk or negedge i_Bus_Rst_L) 327 | 328 | 329 | // Perform a read or write to Bus based on cmd from UART 330 | always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) 331 | begin 332 | if (~i_Bus_Rst_L) 333 | begin 334 | o_Bus_CS <= 1'b0; 335 | end 336 | 337 | else 338 | begin 339 | o_Bus_Addr8 <= r_RX_Cmd_Addr; 340 | 341 | if (r_RX_Cmd_Rd == 1'b1) 342 | begin 343 | o_Bus_CS <= 1'b1; 344 | o_Bus_Wr_Rd_n <= 1'b0; 345 | end 346 | 347 | else if (r_RX_Cmd_Wr == 1'b1) 348 | begin 349 | o_Bus_CS <= 1'b1; 350 | o_Bus_Wr_Rd_n <= 1'b1; 351 | o_Bus_Wr_Data <= r_RX_Cmd_Data; 352 | end 353 | else 354 | begin 355 | o_Bus_CS <= 1'b0; 356 | end // else: !if(r_RX_Cmd_Wr == 1'b1) 357 | end // else: !if(~i_Bus_Rst_L) 358 | end // always @ (posege i_Bus_Clk or negedge i_Bus_Rst_L) 359 | 360 | 361 | // Form a command response to a Received Command 362 | always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) 363 | begin 364 | if (~i_Bus_Rst_L) 365 | begin 366 | r_TX_Cmd_Start <= 1'b0; 367 | end 368 | 369 | else 370 | begin 371 | r_TX_Cmd_Start <= 1'b0; 372 | 373 | // Erroneous Command Response 374 | if (r_RX_Cmd_Error == 1'b1) 375 | begin 376 | r_TX_Cmd_Array[0] <= ASCII_LF; 377 | r_TX_Cmd_Array[1] <= ASCII_e; 378 | r_TX_Cmd_Array[2] <= ASCII_r; 379 | r_TX_Cmd_Array[3] <= ASCII_r; 380 | r_TX_Cmd_Array[4] <= ASCII_Sp; 381 | r_TX_Cmd_Array[5] <= ASCII_CR; 382 | r_TX_Cmd_Array[6] <= ASCII_LF; 383 | r_TX_Cmd_Array[7] <= ASCII_LF; 384 | r_TX_Cmd_Length <= 8; 385 | r_TX_Cmd_Start <= 1'b1; 386 | end // if (r_RX_Cmd_Error == 1'b1) 387 | 388 | // Read Command Response 389 | else if (i_Bus_Rd_DV == 1'b1) 390 | begin 391 | r_TX_Cmd_Array[0] <= ASCII_LF; 392 | r_TX_Cmd_Array[1] <= ASCII_0; 393 | r_TX_Cmd_Array[2] <= ASCII_x; 394 | r_TX_Cmd_Array[3] <= f_Hex_To_ASCII(i_Bus_Rd_Data[7:4]); 395 | r_TX_Cmd_Array[4] <= f_Hex_To_ASCII(i_Bus_Rd_Data[3:0]); 396 | r_TX_Cmd_Array[5] <= ASCII_CR; 397 | r_TX_Cmd_Array[6] <= ASCII_LF; 398 | r_TX_Cmd_Array[7] <= ASCII_LF; 399 | r_TX_Cmd_Length <= 8; 400 | r_TX_Cmd_Start <= 1'b1; 401 | end // if (i_Bus_Rd_DV == 1'b1) 402 | 403 | // Write Command Response 404 | else if (r_RX_Cmd_Wr == 1'b1) 405 | begin 406 | r_TX_Cmd_Array[0] <= ASCII_CR; 407 | r_TX_Cmd_Array[1] <= ASCII_LF; 408 | r_TX_Cmd_Array[2] <= ASCII_LF; 409 | r_TX_Cmd_Length <= 3; 410 | r_TX_Cmd_Start <= 1'b1; 411 | end 412 | end // else: !if(~i_Bus_Rst_L) 413 | end // always @ (posege i_Bus_Clk or negedge i_Bus_Rst_L) 414 | 415 | 416 | // Simple State Machine to Transmit a command. 417 | always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) 418 | begin 419 | if (~i_Bus_Rst_L) 420 | begin 421 | r_SM_Main <= IDLE; 422 | r_TX_DV <= 1'b0; 423 | end 424 | 425 | else 426 | begin 427 | 428 | // Default Assignments 429 | r_TX_DV <= 1'b0; 430 | 431 | case (r_SM_Main) 432 | IDLE : 433 | begin 434 | r_TX_Index <= 0; 435 | if (r_TX_Cmd_Start == 1'b1) 436 | r_SM_Main <= TX_WAIT_READY; 437 | end 438 | 439 | TX_WAIT_READY : 440 | begin 441 | if (w_TX_Active == 1'b0) 442 | r_SM_Main <= TX_START; 443 | end 444 | 445 | TX_START : 446 | begin 447 | r_TX_DV <= 1'b1; 448 | r_TX_Byte <= r_TX_Cmd_Array[r_TX_Index]; 449 | r_SM_Main <= TX_WAIT_DONE; 450 | end 451 | 452 | TX_WAIT_DONE : 453 | begin 454 | if (w_TX_Done == 1'b1) 455 | begin 456 | if (r_TX_Index == r_TX_Cmd_Length-1) 457 | begin 458 | r_SM_Main <= TX_DONE; 459 | end 460 | else 461 | begin 462 | r_TX_Index <= r_TX_Index + 1; 463 | r_SM_Main <= TX_START; 464 | end 465 | end // if (w_TX_Done == 1'b1) 466 | end // case: TX_WAIT_DONE 467 | 468 | TX_DONE : 469 | r_SM_Main <= IDLE; 470 | 471 | default : 472 | r_SM_Main <= IDLE; 473 | 474 | endcase 475 | 476 | end // else: !if(~i_Bus_Rst_L) 477 | end // always @ (posege i_Bus_Clk or negedge i_Bus_Rst_L) 478 | 479 | 480 | assign o_TX_Active = w_TX_Active; 481 | 482 | endmodule // UART_To_Bus8 483 | -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/common/clkdivider.v: -------------------------------------------------------------------------------- 1 | /** 2 | * clkout = clk/CNT_MAX 3 | * CNT_MAX is even number. 4 | * Author: Dong Xiao 5 | */ 6 | 7 | `timescale 1 ns/ 1 ns 8 | 9 | module clkdivider #( parameter CNT_MAX = 16'd2 ) 10 | ( 11 | input clk, 12 | input nRST, 13 | output reg clkout 14 | ); 15 | reg [15:0] cnt; 16 | 17 | always @( posedge clk, negedge nRST ) begin 18 | if( !nRST ) begin 19 | cnt <= 16'd0; 20 | clkout <= 1'b0; 21 | end else begin 22 | if ( cnt < CNT_MAX/2-1 ) begin 23 | cnt <= cnt + 16'd1; 24 | end else begin 25 | cnt <= 16'd0; 26 | clkout <= ~clkout; 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /hdl/Blink_EPM240T100/common/debouncer.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Author: Dong Xiao 2012.04.21 3 | */ 4 | 5 | module debouncer #( parameter SAMPLE = 8'd30 ) 6 | ( 7 | input clk, 8 | input rst_n, 9 | input key_i, 10 | output reg key_o 11 | ); 12 | parameter IDLE = 3'b001; 13 | parameter JUGH = 3'b010; 14 | parameter JUGL = 3'b100; 15 | reg key; 16 | reg [7:0] cnt; 17 | reg [2:0] state; 18 | 19 | always @ ( posedge clk, negedge rst_n ) begin 20 | if(!rst_n) begin 21 | key <= 1'b0; 22 | end 23 | else begin 24 | key <= key_i; 25 | end 26 | end 27 | 28 | always @ ( posedge clk, negedge rst_n ) begin 29 | if(!rst_n) begin 30 | state <= IDLE; 31 | key_o <= 1'b0; 32 | end 33 | else begin 34 | case (state) 35 | IDLE: begin 36 | cnt <= 8'd0; 37 | if(key == 1'b0 && key_i == 1'b1) begin 38 | state <= JUGH; 39 | end 40 | else if(key == 1'b1 && key_i == 1'b0) begin 41 | state <= JUGL; 42 | end 43 | else begin 44 | state <= IDLE; 45 | end 46 | end 47 | JUGH: begin 48 | if(key_i == 1'b1) begin 49 | cnt <= cnt + 1'b1; 50 | if(cnt < SAMPLE) begin 51 | state <= JUGH; 52 | end 53 | else begin 54 | state <= IDLE; 55 | key_o <= key; 56 | end 57 | end 58 | else begin 59 | cnt <= 8'd0; 60 | state <= IDLE; 61 | end 62 | end 63 | JUGL: begin 64 | if(key_i == 1'b0) begin 65 | cnt <= cnt + 1'b1; 66 | if(cnt < SAMPLE) begin 67 | state <= JUGL; 68 | end 69 | else begin 70 | state <= IDLE; 71 | key_o <= key; 72 | end 73 | end 74 | else begin 75 | cnt <= 8'd0; 76 | state <= IDLE; 77 | end 78 | end 79 | default:; 80 | endcase 81 | end 82 | end 83 | 84 | endmodule -------------------------------------------------------------------------------- /image/AgmPill_ASM.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/image/AgmPill_ASM.png -------------------------------------------------------------------------------- /image/AgmPill_PINOUT.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/image/AgmPill_PINOUT.png -------------------------------------------------------------------------------- /image/GreenPill.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/image/GreenPill.jpg -------------------------------------------------------------------------------- /image/GreenPill_ASM.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/image/GreenPill_ASM.png -------------------------------------------------------------------------------- /image/MegaPill.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/image/MegaPill.jpg -------------------------------------------------------------------------------- /image/MegaPill_ASM.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/image/MegaPill_ASM.png -------------------------------------------------------------------------------- /sch/AgmPill_v21.10.6_ASM.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/sch/AgmPill_v21.10.6_ASM.pdf -------------------------------------------------------------------------------- /sch/AgmPill_v21.10.6_SCH.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/sch/AgmPill_v21.10.6_SCH.pdf -------------------------------------------------------------------------------- /sch/GreenPill_v21.12.26.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/sch/GreenPill_v21.12.26.pdf -------------------------------------------------------------------------------- /sch/MegaPill_v21.11.16.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xjtuecho/AgmPill/03d4c684df11743c59c6ccfa40bc12502e7e622f/sch/MegaPill_v21.11.16.pdf --------------------------------------------------------------------------------