├── .gitignore ├── .gitmodules ├── Makefile ├── README.md ├── config ├── 1_core.yaml ├── 2_cores.yaml ├── 4_cores.yaml ├── NPU.yaml ├── base.yaml ├── scripts │ ├── Makefile │ ├── gen_dts.py │ ├── gen_plic.py │ └── gen_soc_pkg.py └── sim.yaml ├── de ├── inc │ ├── axi_pkg.sv │ ├── dbg_pkg.sv │ ├── genesys2.svh │ ├── glb_def.svh │ ├── reg_intf.sv │ ├── reg_intf_pkg.sv │ ├── registers.svh │ ├── sy_axi.sv │ ├── sy_cache.svh │ ├── sy_mmu.svh │ ├── sy_ovall.svh │ ├── sy_pkg.sv │ ├── sy_ppl.svh │ ├── sy_soc_pkg.sv │ ├── tl_pkg.sv │ └── vc707.svh ├── ip │ ├── algebra │ │ ├── div64x64_d20_wrap.sv │ │ └── mul64x64_d3_wrap.sv │ ├── bootrom_fpga │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README.md │ │ ├── bootrom.h │ │ ├── bootrom.s │ │ ├── bootrom.sv │ │ ├── gen_rom.py │ │ ├── linker.lds │ │ ├── platform.h │ │ ├── src │ │ │ ├── dma.c │ │ │ ├── dma.h │ │ │ ├── main.c │ │ │ ├── sd.c │ │ │ ├── sd.h │ │ │ ├── smp.h │ │ │ ├── spi.c │ │ │ ├── spi.h │ │ │ ├── uart.c │ │ │ └── uart.h │ │ ├── startup.S │ │ └── sy.dts │ ├── bootrom_sim │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README.md │ │ ├── bootrom.h │ │ ├── bootrom.s │ │ ├── bootrom.sv │ │ ├── gen_rom.py │ │ ├── linker.lds │ │ ├── platform.h │ │ ├── src │ │ │ ├── main.c │ │ │ ├── smp.h │ │ │ ├── uart.c │ │ │ └── uart.h │ │ ├── startup.S │ │ └── sy.dts │ ├── sram │ │ ├── sdp_512x64sd1_wrap.sv │ │ ├── sdp_w512x64_r512x64_wrap.sv │ │ └── sim │ │ │ └── sdp_sram_with_strob.sv │ └── uart_sim │ │ ├── UART.sv │ │ ├── UART_rec.sv │ │ └── UART_send.sv ├── src │ ├── sy │ │ ├── sy_axi4_arbiter.sv │ │ ├── sy_bootrom.sv │ │ ├── sy_cache │ │ │ ├── sy_L1_cache.sv │ │ │ ├── sy_dcache.sv │ │ │ ├── sy_dcache │ │ │ │ ├── sy_dcache_ctrl.sv │ │ │ │ ├── sy_dcache_mem.sv │ │ │ │ ├── sy_dcache_missunit.sv │ │ │ │ └── sy_dcache_mshr.sv │ │ │ └── sy_icache.sv │ │ ├── sy_clint │ │ │ └── sy_clint.sv │ │ ├── sy_core.sv │ │ ├── sy_ddr.sv │ │ ├── sy_dma │ │ │ └── sy_dma.sv │ │ ├── sy_ethernet │ │ │ └── sy_ethernet.sv │ │ ├── sy_gpio.sv │ │ ├── sy_main_mem.sv │ │ ├── sy_mmu │ │ │ ├── cva6_mmu.sv │ │ │ ├── cva6_ptw.sv │ │ │ └── cva6_tlb.sv │ │ ├── sy_npu │ │ │ ├── sy_npu.sv │ │ │ ├── sy_npu_core.sv │ │ │ ├── sy_npu_mem.sv │ │ │ └── tl_c_trans_a.sv │ │ ├── sy_plic │ │ │ └── sy_plic.sv │ │ ├── sy_ppl │ │ │ ├── sy_ppl_csr.sv │ │ │ ├── sy_ppl_csr │ │ │ │ └── sy_ppl_csr_iq.sv │ │ │ ├── sy_ppl_csr_regfile.sv │ │ │ ├── sy_ppl_ctrl.sv │ │ │ ├── sy_ppl_dec.sv │ │ │ ├── sy_ppl_dec │ │ │ │ ├── sy_ppl_decoder.sv │ │ │ │ ├── sy_ppl_rename.sv │ │ │ │ └── sy_ppl_rename │ │ │ │ │ ├── sy_ppl_fl.sv │ │ │ │ │ ├── sy_ppl_fp_fl.sv │ │ │ │ │ ├── sy_ppl_fp_rat.sv │ │ │ │ │ └── sy_ppl_rat.sv │ │ │ ├── sy_ppl_dis.sv │ │ │ ├── sy_ppl_dis │ │ │ │ └── sy_ppl_reg_state.sv │ │ │ ├── sy_ppl_exu.sv │ │ │ ├── sy_ppl_exu │ │ │ │ ├── sy_ppl_alu.sv │ │ │ │ ├── sy_ppl_exu_iq.sv │ │ │ │ ├── sy_ppl_fpu.sv │ │ │ │ ├── sy_ppl_fpu │ │ │ │ │ └── fpu_warp.sv │ │ │ │ └── sy_ppl_mdu.sv │ │ │ ├── sy_ppl_fpr_file.sv │ │ │ ├── sy_ppl_fronted.sv │ │ │ ├── sy_ppl_fronted │ │ │ │ ├── sy_ppl_br_pred.sv │ │ │ │ ├── sy_ppl_br_pred │ │ │ │ │ ├── sy_ppl_bht.sv │ │ │ │ │ ├── sy_ppl_btb.sv │ │ │ │ │ ├── sy_ppl_qdec.sv │ │ │ │ │ └── sy_ppl_ras.sv │ │ │ │ ├── sy_ppl_compressed_dec.sv │ │ │ │ ├── sy_ppl_instr_buffer.sv │ │ │ │ └── sy_ppl_instr_realign.sv │ │ │ ├── sy_ppl_gpr_file.sv │ │ │ ├── sy_ppl_lsu.sv │ │ │ ├── sy_ppl_lsu │ │ │ │ ├── sy_ppl_lsu_atrans.sv │ │ │ │ ├── sy_ppl_lsu_ctrl.sv │ │ │ │ ├── sy_ppl_lsu_ctrl │ │ │ │ │ └── sy_ppl_lsu_sbuf.sv │ │ │ │ └── sy_ppl_lsu_iq.sv │ │ │ └── sy_ppl_rob.sv │ │ ├── sy_spi.sv │ │ ├── sy_tl │ │ │ ├── tl2amba │ │ │ │ ├── TL2APB.sv │ │ │ │ ├── TL2AXI4.sv │ │ │ │ ├── TL2Mem.sv │ │ │ │ └── TL2Reg.sv │ │ │ ├── tl_buffer │ │ │ │ ├── tl_buf.sv │ │ │ │ ├── tl_buffer.sv │ │ │ │ └── tl_identity.sv │ │ │ ├── tl_connect │ │ │ │ ├── tl_master_connect.sv │ │ │ │ ├── tl_slave2master.sv │ │ │ │ └── tl_slave_connect.sv │ │ │ ├── tl_intf.sv │ │ │ ├── tl_probe_ctrl.sv │ │ │ └── tl_xbar │ │ │ │ ├── tl_addr_router_A.sv │ │ │ │ ├── tl_addr_router_B.sv │ │ │ │ ├── tl_addr_router_C.sv │ │ │ │ ├── tl_addr_router_D.sv │ │ │ │ ├── tl_addr_router_E.sv │ │ │ │ ├── tl_arbiter.sv │ │ │ │ ├── tl_arbiter_A.sv │ │ │ │ ├── tl_arbiter_B.sv │ │ │ │ ├── tl_arbiter_C.sv │ │ │ │ ├── tl_arbiter_D.sv │ │ │ │ ├── tl_xbar.sv │ │ │ │ ├── tl_xbar_m2s.sv │ │ │ │ └── tl_xbar_s2m.sv │ │ ├── sy_tl_xbar.sv │ │ └── sy_uart.sv │ ├── sy_soc_fpga.sv │ ├── sy_soc_genesys2.sv │ ├── sy_soc_sim.sv │ └── sy_soc_vc707.sv └── utils │ ├── apb_to_reg.sv │ ├── fan_ctrl.sv │ ├── fifo_v1.sv │ ├── fifo_v2.sv │ ├── fifo_v3.sv │ ├── lzc.sv │ ├── oneHot2Int.sv │ ├── pulp_clock_gating.sv │ ├── rr_arb_tree.sv │ ├── rstgen.sv │ ├── rstgen_bypass.sv │ ├── sdp_bram_fifo.sv │ ├── spill_register.sv │ ├── stream_arbiter.sv │ ├── stream_arbiter_flushable.sv │ ├── sync.sv │ └── sync_wedge.sv ├── doc ├── SiYuan_FPGA_User_Guide.pdf ├── fpga_build_user_guide.md └── sim_user_guide.md ├── dv ├── simulation │ ├── makefile │ ├── run_regression.py │ └── run_tc ├── tb │ ├── axi_mem_benos.sv │ ├── axi_mem_dma.sv │ ├── axi_mem_linux.sv │ ├── axi_mem_riscv_tests.sv │ ├── tb_sy_benos.sv │ ├── tb_sy_dma.sv │ ├── tb_sy_linux.sv │ └── tb_sy_riscv_tests.sv ├── tests │ ├── benos_test_01 │ │ ├── Makefile │ │ ├── gen_verilog_data.py │ │ ├── include │ │ │ ├── asm │ │ │ │ └── csr.h │ │ │ ├── io.h │ │ │ └── uart.h │ │ ├── sbi │ │ │ ├── sbi_base.ld │ │ │ ├── sbi_boot.S │ │ │ ├── sbi_linker.ld │ │ │ ├── sbi_linker_payload.ld │ │ │ ├── sbi_main.c │ │ │ ├── sbi_payload │ │ │ └── sbi_payload.S │ │ └── src │ │ │ ├── boot.S │ │ │ ├── kernel.c │ │ │ ├── linker.ld │ │ │ └── uart.c │ ├── benos_test_02 │ │ ├── Makefile │ │ ├── gen_verilog_data.py │ │ ├── include │ │ │ ├── asm │ │ │ │ ├── asm-offsets.h │ │ │ │ ├── csr.h │ │ │ │ ├── ptregs.h │ │ │ │ ├── sbi.h │ │ │ │ └── types.h │ │ │ ├── io.h │ │ │ ├── memset.h │ │ │ ├── printk.h │ │ │ ├── string.h │ │ │ ├── type.h │ │ │ └── uart.h │ │ ├── lib │ │ │ ├── printk.c │ │ │ └── string.c │ │ ├── sbi │ │ │ ├── sbi_asm_offsets.h │ │ │ ├── sbi_base.ld │ │ │ ├── sbi_boot.S │ │ │ ├── sbi_entry.S │ │ │ ├── sbi_error.h │ │ │ ├── sbi_linker.ld │ │ │ ├── sbi_linker_payload.ld │ │ │ ├── sbi_main.c │ │ │ ├── sbi_payload.S │ │ │ ├── sbi_trap.c │ │ │ ├── sbi_trap.h │ │ │ ├── sbi_trap_regs.h │ │ │ └── uart.c │ │ ├── scripts │ │ │ └── kallsyms │ │ │ │ ├── kallsyms │ │ │ │ └── kallsyms.c │ │ └── src │ │ │ ├── asm_test.S │ │ │ ├── boot.S │ │ │ ├── entry.S │ │ │ ├── kallsyms.c │ │ │ ├── kernel.c │ │ │ ├── linker.ld │ │ │ ├── memset.S │ │ │ ├── memset.c │ │ │ ├── stacktrace.c │ │ │ ├── trap.c │ │ │ └── uart.c │ ├── benos_test_03 │ │ ├── Makefile │ │ ├── gen_verilog_data.py │ │ ├── include │ │ │ ├── asm │ │ │ │ ├── asm-offsets.h │ │ │ │ ├── clint.h │ │ │ │ ├── csr.h │ │ │ │ ├── irq.h │ │ │ │ ├── plic.h │ │ │ │ ├── ptregs.h │ │ │ │ ├── sbi.h │ │ │ │ ├── timer.h │ │ │ │ └── types.h │ │ │ ├── io.h │ │ │ ├── memset.h │ │ │ ├── printk.h │ │ │ ├── string.h │ │ │ ├── type.h │ │ │ └── uart.h │ │ ├── lib │ │ │ ├── printk.c │ │ │ └── string.c │ │ ├── sbi │ │ │ ├── sbi_asm_offsets.h │ │ │ ├── sbi_base.ld │ │ │ ├── sbi_boot.S │ │ │ ├── sbi_entry.S │ │ │ ├── sbi_error.h │ │ │ ├── sbi_linker.ld │ │ │ ├── sbi_linker_payload.ld │ │ │ ├── sbi_main.c │ │ │ ├── sbi_payload.S │ │ │ ├── sbi_timer.c │ │ │ ├── sbi_timer.h │ │ │ ├── sbi_trap.c │ │ │ ├── sbi_trap.h │ │ │ └── uart.c │ │ ├── scripts │ │ │ └── kallsyms │ │ │ │ ├── kallsyms │ │ │ │ └── kallsyms.c │ │ └── src │ │ │ ├── asm_test.S │ │ │ ├── boot.S │ │ │ ├── entry.S │ │ │ ├── kallsyms.c │ │ │ ├── kernel.c │ │ │ ├── linker.ld │ │ │ ├── memset.S │ │ │ ├── memset.c │ │ │ ├── plic.c │ │ │ ├── stacktrace.c │ │ │ ├── timer.c │ │ │ ├── trap.c │ │ │ └── uart.c │ ├── benos_test_04 │ │ ├── Makefile │ │ ├── gen_verilog_data.py │ │ ├── include │ │ │ ├── asm │ │ │ │ ├── asm-offsets.h │ │ │ │ ├── clint.h │ │ │ │ ├── csr.h │ │ │ │ ├── irq.h │ │ │ │ ├── memory.h │ │ │ │ ├── pgtable.h │ │ │ │ ├── pgtable_hwdef.h │ │ │ │ ├── pgtable_types.h │ │ │ │ ├── plic.h │ │ │ │ ├── ptregs.h │ │ │ │ ├── sbi.h │ │ │ │ ├── timer.h │ │ │ │ └── types.h │ │ │ ├── io.h │ │ │ ├── memset.h │ │ │ ├── mm.h │ │ │ ├── printk.h │ │ │ ├── string.h │ │ │ ├── type.h │ │ │ └── uart.h │ │ ├── lib │ │ │ ├── printk.c │ │ │ └── string.c │ │ ├── sbi │ │ │ ├── sbi_asm_offsets.h │ │ │ ├── sbi_base.ld │ │ │ ├── sbi_boot.S │ │ │ ├── sbi_entry.S │ │ │ ├── sbi_error.h │ │ │ ├── sbi_linker.ld │ │ │ ├── sbi_linker_payload.ld │ │ │ ├── sbi_main.c │ │ │ ├── sbi_payload.S │ │ │ ├── sbi_timer.c │ │ │ ├── sbi_timer.h │ │ │ ├── sbi_trap.c │ │ │ ├── sbi_trap.h │ │ │ └── uart.c │ │ ├── scripts │ │ │ └── kallsyms │ │ │ │ ├── kallsyms │ │ │ │ └── kallsyms.c │ │ └── src │ │ │ ├── asm_test.S │ │ │ ├── boot.S │ │ │ ├── entry.S │ │ │ ├── kallsyms.c │ │ │ ├── kernel.c │ │ │ ├── linker.ld │ │ │ ├── memset.S │ │ │ ├── memset.c │ │ │ ├── mmu.c │ │ │ ├── page_alloc.c │ │ │ ├── plic.c │ │ │ ├── stacktrace.c │ │ │ ├── timer.c │ │ │ ├── trap.c │ │ │ └── uart.c │ ├── benos_test_05 │ │ ├── Makefile │ │ ├── gen_verilog_data.py │ │ ├── include │ │ │ ├── asm │ │ │ │ ├── asm-offsets.h │ │ │ │ ├── clint.h │ │ │ │ ├── csr.h │ │ │ │ ├── irq.h │ │ │ │ ├── memory.h │ │ │ │ ├── pgtable.h │ │ │ │ ├── pgtable_hwdef.h │ │ │ │ ├── pgtable_types.h │ │ │ │ ├── plic.h │ │ │ │ ├── ptregs.h │ │ │ │ ├── sbi.h │ │ │ │ ├── timer.h │ │ │ │ └── types.h │ │ │ ├── io.h │ │ │ ├── memset.h │ │ │ ├── mm.h │ │ │ ├── printk.h │ │ │ ├── string.h │ │ │ ├── type.h │ │ │ └── uart.h │ │ ├── lib │ │ │ ├── printk.c │ │ │ └── string.c │ │ ├── sbi │ │ │ ├── sbi_asm_offsets.h │ │ │ ├── sbi_base.ld │ │ │ ├── sbi_boot.S │ │ │ ├── sbi_entry.S │ │ │ ├── sbi_error.h │ │ │ ├── sbi_linker.ld │ │ │ ├── sbi_linker_payload.ld │ │ │ ├── sbi_main.c │ │ │ ├── sbi_payload.S │ │ │ ├── sbi_timer.c │ │ │ ├── sbi_timer.h │ │ │ ├── sbi_trap.c │ │ │ ├── sbi_trap.h │ │ │ └── uart.c │ │ ├── scripts │ │ │ └── kallsyms │ │ │ │ ├── kallsyms │ │ │ │ └── kallsyms.c │ │ └── src │ │ │ ├── asm_test.S │ │ │ ├── boot.S │ │ │ ├── entry.S │ │ │ ├── kallsyms.c │ │ │ ├── kernel.c │ │ │ ├── linker.ld │ │ │ ├── memset.S │ │ │ ├── memset.c │ │ │ ├── mmu.c │ │ │ ├── page_alloc.c │ │ │ ├── plic.c │ │ │ ├── stacktrace.c │ │ │ ├── timer.c │ │ │ ├── trap.c │ │ │ └── uart.c │ ├── dma_test_01 │ │ ├── config.ld │ │ ├── gen_hex.py │ │ ├── gen_test_data.py │ │ ├── gen_verilog_data.py │ │ ├── include │ │ │ ├── dma.h │ │ │ ├── smp.h │ │ │ └── uart.h │ │ ├── makefile │ │ └── src │ │ │ ├── dma.c │ │ │ ├── main.c │ │ │ ├── start.S │ │ │ └── uart.c │ ├── gen_verilog_data.py │ ├── linux_test_01 │ │ ├── Makefile │ │ ├── bbl.bin │ │ ├── bin2fpga.py │ │ └── trans.py │ ├── makefile │ ├── riscv-tests │ │ ├── LICENSE │ │ ├── Makefile │ │ ├── Makefile.in │ │ ├── README.md │ │ ├── autom4te.cache │ │ │ ├── output.0 │ │ │ ├── requests │ │ │ └── traces.0 │ │ ├── benchmarks │ │ │ ├── Makefile │ │ │ ├── common │ │ │ │ ├── crt.S │ │ │ │ ├── syscalls.c │ │ │ │ ├── test.ld │ │ │ │ └── util.h │ │ │ ├── dhrystone │ │ │ │ ├── dhrystone.c │ │ │ │ ├── dhrystone.h │ │ │ │ └── dhrystone_main.c │ │ │ ├── median │ │ │ │ ├── dataset1.h │ │ │ │ ├── median.c │ │ │ │ ├── median.h │ │ │ │ ├── median_gendata.pl │ │ │ │ └── median_main.c │ │ │ ├── mm │ │ │ │ ├── common.h │ │ │ │ ├── gen.scala │ │ │ │ ├── mm.c │ │ │ │ ├── mm_main.c │ │ │ │ └── rb.h │ │ │ ├── mt-matmul │ │ │ │ ├── dataset.h │ │ │ │ ├── matmul.c │ │ │ │ ├── matmul_gendata.pl │ │ │ │ └── mt-matmul.c │ │ │ ├── mt-vvadd │ │ │ │ ├── dataset.h │ │ │ │ ├── mt-vvadd.c │ │ │ │ ├── vvadd.c │ │ │ │ └── vvadd_gendata.pl │ │ │ ├── multiply │ │ │ │ ├── dataset1.h │ │ │ │ ├── multiply.c │ │ │ │ ├── multiply.h │ │ │ │ ├── multiply_gendata.pl │ │ │ │ └── multiply_main.c │ │ │ ├── pmp │ │ │ │ └── pmp.c │ │ │ ├── qsort │ │ │ │ ├── dataset1.h │ │ │ │ ├── qsort_gendata.pl │ │ │ │ └── qsort_main.c │ │ │ ├── readme.txt │ │ │ ├── rsort │ │ │ │ ├── dataset1.h │ │ │ │ └── rsort.c │ │ │ ├── spmv │ │ │ │ ├── dataset1.h │ │ │ │ ├── spmv_gendata.scala │ │ │ │ └── spmv_main.c │ │ │ ├── towers │ │ │ │ └── towers_main.c │ │ │ └── vvadd │ │ │ │ ├── dataset1-large.h │ │ │ │ ├── dataset1.h │ │ │ │ ├── vvadd_gendata.pl │ │ │ │ └── vvadd_main.c │ │ ├── build │ │ │ ├── Makefile │ │ │ ├── config.log │ │ │ └── config.status │ │ ├── config.log │ │ ├── config.status │ │ ├── configure │ │ ├── configure.ac │ │ ├── debug │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── gdbserver.py │ │ │ ├── openocd.py │ │ │ ├── programs │ │ │ │ ├── checksum.c │ │ │ │ ├── debug.c │ │ │ │ ├── entry.S │ │ │ │ ├── infinite_loop.S │ │ │ │ ├── init.c │ │ │ │ ├── init.h │ │ │ │ ├── interrupt.c │ │ │ │ ├── mprv.S │ │ │ │ ├── multicore.c │ │ │ │ ├── priv.S │ │ │ │ ├── regs.S │ │ │ │ ├── step.S │ │ │ │ ├── tiny-malloc.c │ │ │ │ └── trigger.S │ │ │ ├── pylint.rc │ │ │ ├── requirements.txt │ │ │ ├── targets.py │ │ │ ├── targets │ │ │ │ ├── RISC-V │ │ │ │ │ ├── spike-1.cfg │ │ │ │ │ ├── spike-2.cfg │ │ │ │ │ ├── spike-rtos.cfg │ │ │ │ │ ├── spike32-2-rtos.py │ │ │ │ │ ├── spike32-2.py │ │ │ │ │ ├── spike32.lds │ │ │ │ │ ├── spike32.py │ │ │ │ │ ├── spike64-2-rtos.py │ │ │ │ │ ├── spike64-2.py │ │ │ │ │ ├── spike64.lds │ │ │ │ │ └── spike64.py │ │ │ │ └── SiFive │ │ │ │ │ ├── Freedom │ │ │ │ │ ├── E300.py │ │ │ │ │ ├── Freedom.cfg │ │ │ │ │ ├── Freedom.lds │ │ │ │ │ ├── U500.py │ │ │ │ │ └── U500Sim.py │ │ │ │ │ ├── HiFive1.cfg │ │ │ │ │ ├── HiFive1.lds │ │ │ │ │ └── HiFive1.py │ │ │ └── testlib.py │ │ ├── env │ │ │ ├── LICENSE │ │ │ ├── encoding.h │ │ │ ├── p │ │ │ │ ├── link.ld │ │ │ │ └── riscv_test.h │ │ │ ├── pm │ │ │ │ └── riscv_test.h │ │ │ ├── pt │ │ │ │ └── riscv_test.h │ │ │ └── v │ │ │ │ ├── entry.S │ │ │ │ ├── link.ld │ │ │ │ ├── riscv_test.h │ │ │ │ ├── string.c │ │ │ │ └── vm.c │ │ ├── isa │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── macros │ │ │ │ └── scalar │ │ │ │ │ └── test_macros.h │ │ │ ├── rv32mi │ │ │ │ ├── Makefrag │ │ │ │ ├── breakpoint.S │ │ │ │ ├── csr.S │ │ │ │ ├── illegal.S │ │ │ │ ├── ma_addr.S │ │ │ │ ├── ma_fetch.S │ │ │ │ ├── mcsr.S │ │ │ │ ├── sbreak.S │ │ │ │ ├── scall.S │ │ │ │ └── shamt.S │ │ │ ├── rv32si │ │ │ │ ├── Makefrag │ │ │ │ ├── csr.S │ │ │ │ ├── dirty.S │ │ │ │ ├── ma_fetch.S │ │ │ │ ├── sbreak.S │ │ │ │ ├── scall.S │ │ │ │ └── wfi.S │ │ │ ├── rv32ua │ │ │ │ ├── Makefrag │ │ │ │ ├── amoadd_w.S │ │ │ │ ├── amoand_w.S │ │ │ │ ├── amomax_w.S │ │ │ │ ├── amomaxu_w.S │ │ │ │ ├── amomin_w.S │ │ │ │ ├── amominu_w.S │ │ │ │ ├── amoor_w.S │ │ │ │ ├── amoswap_w.S │ │ │ │ ├── amoxor_w.S │ │ │ │ └── lrsc.S │ │ │ ├── rv32uc │ │ │ │ ├── Makefrag │ │ │ │ └── rvc.S │ │ │ ├── rv32ud │ │ │ │ ├── Makefrag │ │ │ │ ├── fadd.S │ │ │ │ ├── fclass.S │ │ │ │ ├── fcmp.S │ │ │ │ ├── fcvt.S │ │ │ │ ├── fcvt_w.S │ │ │ │ ├── fdiv.S │ │ │ │ ├── fmadd.S │ │ │ │ ├── fmin.S │ │ │ │ ├── ldst.S │ │ │ │ ├── move.S │ │ │ │ └── recoding.S │ │ │ ├── rv32uf │ │ │ │ ├── Makefrag │ │ │ │ ├── fadd.S │ │ │ │ ├── fclass.S │ │ │ │ ├── fcmp.S │ │ │ │ ├── fcvt.S │ │ │ │ ├── fcvt_w.S │ │ │ │ ├── fdiv.S │ │ │ │ ├── fmadd.S │ │ │ │ ├── fmin.S │ │ │ │ ├── ldst.S │ │ │ │ ├── move.S │ │ │ │ └── recoding.S │ │ │ ├── rv32ui │ │ │ │ ├── Makefrag │ │ │ │ ├── add.S │ │ │ │ ├── addi.S │ │ │ │ ├── and.S │ │ │ │ ├── andi.S │ │ │ │ ├── auipc.S │ │ │ │ ├── beq.S │ │ │ │ ├── bge.S │ │ │ │ ├── bgeu.S │ │ │ │ ├── blt.S │ │ │ │ ├── bltu.S │ │ │ │ ├── bne.S │ │ │ │ ├── fence_i.S │ │ │ │ ├── jal.S │ │ │ │ ├── jalr.S │ │ │ │ ├── lb.S │ │ │ │ ├── lbu.S │ │ │ │ ├── lh.S │ │ │ │ ├── lhu.S │ │ │ │ ├── lui.S │ │ │ │ ├── lw.S │ │ │ │ ├── or.S │ │ │ │ ├── ori.S │ │ │ │ ├── sb.S │ │ │ │ ├── sh.S │ │ │ │ ├── simple.S │ │ │ │ ├── sll.S │ │ │ │ ├── slli.S │ │ │ │ ├── slt.S │ │ │ │ ├── slti.S │ │ │ │ ├── sltiu.S │ │ │ │ ├── sltu.S │ │ │ │ ├── sra.S │ │ │ │ ├── srai.S │ │ │ │ ├── srl.S │ │ │ │ ├── srli.S │ │ │ │ ├── sub.S │ │ │ │ ├── sw.S │ │ │ │ ├── xor.S │ │ │ │ └── xori.S │ │ │ ├── rv32um │ │ │ │ ├── Makefrag │ │ │ │ ├── div.S │ │ │ │ ├── divu.S │ │ │ │ ├── mul.S │ │ │ │ ├── mulh.S │ │ │ │ ├── mulhsu.S │ │ │ │ ├── mulhu.S │ │ │ │ ├── rem.S │ │ │ │ └── remu.S │ │ │ ├── rv64mi │ │ │ │ ├── Makefrag │ │ │ │ ├── access.S │ │ │ │ ├── breakpoint.S │ │ │ │ ├── csr.S │ │ │ │ ├── illegal.S │ │ │ │ ├── ma_addr.S │ │ │ │ ├── ma_fetch.S │ │ │ │ ├── mcsr.S │ │ │ │ ├── sbreak.S │ │ │ │ └── scall.S │ │ │ ├── rv64si │ │ │ │ ├── Makefrag │ │ │ │ ├── csr.S │ │ │ │ ├── dirty.S │ │ │ │ ├── ma_fetch.S │ │ │ │ ├── sbreak.S │ │ │ │ ├── scall.S │ │ │ │ └── wfi.S │ │ │ ├── rv64ua │ │ │ │ ├── Makefrag │ │ │ │ ├── amoadd_d.S │ │ │ │ ├── amoadd_w.S │ │ │ │ ├── amoand_d.S │ │ │ │ ├── amoand_w.S │ │ │ │ ├── amomax_d.S │ │ │ │ ├── amomax_w.S │ │ │ │ ├── amomaxu_d.S │ │ │ │ ├── amomaxu_w.S │ │ │ │ ├── amomin_d.S │ │ │ │ ├── amomin_w.S │ │ │ │ ├── amominu_d.S │ │ │ │ ├── amominu_w.S │ │ │ │ ├── amoor_d.S │ │ │ │ ├── amoor_w.S │ │ │ │ ├── amoswap_d.S │ │ │ │ ├── amoswap_w.S │ │ │ │ ├── amoxor_d.S │ │ │ │ ├── amoxor_w.S │ │ │ │ └── lrsc.S │ │ │ ├── rv64uc │ │ │ │ ├── Makefrag │ │ │ │ └── rvc.S │ │ │ ├── rv64ud │ │ │ │ ├── Makefrag │ │ │ │ ├── fadd.S │ │ │ │ ├── fclass.S │ │ │ │ ├── fcmp.S │ │ │ │ ├── fcvt.S │ │ │ │ ├── fcvt_w.S │ │ │ │ ├── fdiv.S │ │ │ │ ├── fmadd.S │ │ │ │ ├── fmin.S │ │ │ │ ├── ldst.S │ │ │ │ ├── move.S │ │ │ │ ├── recoding.S │ │ │ │ └── structural.S │ │ │ ├── rv64uf │ │ │ │ ├── Makefrag │ │ │ │ ├── fadd.S │ │ │ │ ├── fclass.S │ │ │ │ ├── fcmp.S │ │ │ │ ├── fcvt.S │ │ │ │ ├── fcvt_w.S │ │ │ │ ├── fdiv.S │ │ │ │ ├── fmadd.S │ │ │ │ ├── fmin.S │ │ │ │ ├── ldst.S │ │ │ │ ├── move.S │ │ │ │ └── recoding.S │ │ │ ├── rv64ui │ │ │ │ ├── Makefrag │ │ │ │ ├── add.S │ │ │ │ ├── addi.S │ │ │ │ ├── addiw.S │ │ │ │ ├── addw.S │ │ │ │ ├── and.S │ │ │ │ ├── andi.S │ │ │ │ ├── auipc.S │ │ │ │ ├── beq.S │ │ │ │ ├── bge.S │ │ │ │ ├── bgeu.S │ │ │ │ ├── blt.S │ │ │ │ ├── bltu.S │ │ │ │ ├── bne.S │ │ │ │ ├── fence_i.S │ │ │ │ ├── jal.S │ │ │ │ ├── jalr.S │ │ │ │ ├── lb.S │ │ │ │ ├── lbu.S │ │ │ │ ├── ld.S │ │ │ │ ├── lh.S │ │ │ │ ├── lhu.S │ │ │ │ ├── lui.S │ │ │ │ ├── lw.S │ │ │ │ ├── lwu.S │ │ │ │ ├── or.S │ │ │ │ ├── ori.S │ │ │ │ ├── sb.S │ │ │ │ ├── sd.S │ │ │ │ ├── sh.S │ │ │ │ ├── simple.S │ │ │ │ ├── sll.S │ │ │ │ ├── slli.S │ │ │ │ ├── slliw.S │ │ │ │ ├── sllw.S │ │ │ │ ├── slt.S │ │ │ │ ├── slti.S │ │ │ │ ├── sltiu.S │ │ │ │ ├── sltu.S │ │ │ │ ├── sra.S │ │ │ │ ├── srai.S │ │ │ │ ├── sraiw.S │ │ │ │ ├── sraw.S │ │ │ │ ├── srl.S │ │ │ │ ├── srli.S │ │ │ │ ├── srliw.S │ │ │ │ ├── srlw.S │ │ │ │ ├── sub.S │ │ │ │ ├── subw.S │ │ │ │ ├── sw.S │ │ │ │ ├── xor.S │ │ │ │ └── xori.S │ │ │ └── rv64um │ │ │ │ ├── Makefrag │ │ │ │ ├── div.S │ │ │ │ ├── divu.S │ │ │ │ ├── divuw.S │ │ │ │ ├── divw.S │ │ │ │ ├── mul.S │ │ │ │ ├── mulh.S │ │ │ │ ├── mulhsu.S │ │ │ │ ├── mulhu.S │ │ │ │ ├── mulw.S │ │ │ │ ├── rem.S │ │ │ │ ├── remu.S │ │ │ │ ├── remuw.S │ │ │ │ └── remw.S │ │ └── mt │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── ad_matmul.c │ │ │ ├── ae_matmul.c │ │ │ ├── af_matmul.c │ │ │ ├── ag_matmul.c │ │ │ ├── ai_matmul.c │ │ │ ├── ak_matmul.c │ │ │ ├── al_matmul.c │ │ │ ├── am_matmul.c │ │ │ ├── an_matmul.c │ │ │ ├── ap_matmul.c │ │ │ ├── aq_matmul.c │ │ │ ├── ar_matmul.c │ │ │ ├── at_matmul.c │ │ │ ├── av_matmul.c │ │ │ ├── ay_matmul.c │ │ │ ├── az_matmul.c │ │ │ ├── bb_matmul.c │ │ │ ├── bc_matmul.c │ │ │ ├── bf_matmul.c │ │ │ ├── bh_matmul.c │ │ │ ├── bj_matmul.c │ │ │ ├── bk_matmul.c │ │ │ ├── bm_matmul.c │ │ │ ├── bo_matmul.c │ │ │ ├── br_matmul.c │ │ │ ├── bs_matmul.c │ │ │ ├── ce_matmul.c │ │ │ ├── cf_matmul.c │ │ │ ├── cg_matmul.c │ │ │ ├── ci_matmul.c │ │ │ ├── ck_matmul.c │ │ │ ├── cl_matmul.c │ │ │ ├── cm_matmul.c │ │ │ ├── cs_matmul.c │ │ │ ├── cv_matmul.c │ │ │ ├── cy_matmul.c │ │ │ ├── dc_matmul.c │ │ │ ├── df_matmul.c │ │ │ ├── dm_matmul.c │ │ │ ├── do_matmul.c │ │ │ ├── dr_matmul.c │ │ │ ├── ds_matmul.c │ │ │ ├── du_matmul.c │ │ │ ├── dv_matmul.c │ │ │ ├── vvadd0.c │ │ │ ├── vvadd1.c │ │ │ ├── vvadd2.c │ │ │ ├── vvadd3.c │ │ │ └── vvadd4.c │ └── riscv_test_list │ │ ├── rv64ua.txt │ │ ├── rv64uc.txt │ │ ├── rv64ud.txt │ │ ├── rv64uf.txt │ │ ├── rv64ui.txt │ │ └── rv64um.txt └── vc │ └── source_list.vc └── fpga ├── Makefile ├── xilinx_constraint ├── genesys2.xdc └── vc707.xdc ├── xilinx_ip ├── common.mk ├── div64x64_d20_s │ ├── Makefile │ └── tcl │ │ └── run.tcl ├── div64x64_d20_us │ ├── Makefile │ └── tcl │ │ └── run.tcl ├── sdp_512x64sd1 │ ├── Makefile │ └── tcl │ │ └── run.tcl ├── xlnx_axi_clock_converter │ ├── Makefile │ └── tcl │ │ └── run.tcl ├── xlnx_axi_dwidth_converter │ ├── Makefile │ └── tcl │ │ └── run.tcl ├── xlnx_axi_gpio │ ├── Makefile │ └── tcl │ │ └── run.tcl ├── xlnx_axi_quad_spi │ ├── Makefile │ └── tcl │ │ └── run.tcl ├── xlnx_clk_gen │ ├── Makefile │ └── tcl │ │ └── run.tcl └── xlnx_mig_7_ddr3 │ ├── Makefile │ ├── mig_genesys2.prj │ ├── mig_vc707.prj │ └── tcl │ └── run.tcl └── xilinx_scripts ├── add_sources.tcl ├── create_prj.tcl ├── prologue.tcl ├── run.tcl └── write_cfgmem.tcl /.gitignore: -------------------------------------------------------------------------------- 1 | ##ignore this file## 2 | dv/simulation/works 3 | fpga/build/* 4 | -------------------------------------------------------------------------------- /.gitmodules: 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