├── README.md ├── images ├── add_ip.png ├── connect.png ├── disconnect.png ├── lab1 │ ├── Fig1.png │ ├── Fig10.png │ ├── Fig11.png │ ├── Fig12.png │ ├── Fig13.png │ ├── Fig14.png │ ├── Fig15.png │ ├── Fig16-1.png │ ├── Fig16-2.png │ ├── Fig17.png │ ├── Fig18.png │ ├── Fig2.png │ ├── Fig3.png │ ├── Fig4.png │ ├── Fig5.png │ ├── Fig6.png │ ├── Fig7.png │ ├── Fig8.png │ └── Fig9.png ├── lab2 │ ├── Fig1.png │ ├── Fig10.png │ ├── Fig11.png │ ├── Fig12.png │ ├── Fig13.png │ ├── Fig14.png │ ├── Fig15.png │ ├── Fig16.png │ ├── Fig17.png │ ├── Fig18.png │ ├── Fig19-1.png │ ├── Fig19-2.png │ ├── Fig19-3.png │ ├── Fig2.png │ ├── Fig20.png │ ├── Fig21.png │ ├── Fig22.png │ ├── Fig23.png │ ├── Fig24.png │ ├── Fig3.png │ ├── Fig4.png │ ├── Fig5.png │ ├── Fig6.png │ ├── Fig7.png │ ├── Fig8.png │ ├── Fig9.png │ └── disconnect.png ├── lab3 │ ├── Fig1.png │ ├── Fig2.png │ ├── Fig3.png │ ├── Fig4.png │ ├── Fig5.png │ ├── Fig6.png │ └── Fig7.png ├── lab4 │ ├── Fig1.png │ ├── Fig10.png │ ├── Fig2.png │ ├── Fig3.png │ ├── Fig4.png │ ├── Fig5.png │ ├── Fig6.png │ ├── Fig7.png │ ├── Fig8.png │ └── Fig9.png ├── lab5 │ ├── Fig1.png │ ├── Fig10.png │ ├── Fig2.png │ ├── Fig3.png │ ├── Fig4.png │ ├── Fig5.png │ ├── Fig6.png │ ├── Fig7.png │ ├── Fig8-1.png │ └── Fig9.png ├── lab6 │ ├── Fig1.png │ ├── Fig10.png │ ├── Fig11.png │ ├── Fig2.png │ ├── Fig3.png │ ├── Fig4.png │ ├── Fig5.png │ ├── Fig6.png │ ├── Fig7.png │ ├── Fig8.png │ ├── Fig9.png │ └── FigSort.png ├── resume.png ├── terminal.png ├── validate.png └── zoom_in.png ├── lab1.md ├── lab2.md ├── lab3.md ├── lab4.md ├── lab5.md ├── lab6.md ├── slides ├── 01_Class_Intro.pdf ├── 11_Embedded_System_Design_Review.pdf ├── 11a_Lab1_Intro.pdf ├── 12_Advanced_Zynq_Architecture.pdf ├── 13_System_Debugging.pdf ├── 13a_Lab2_Intro.pdf ├── 14_Memory_Interfacing.pdf ├── 14a_Lab3_Intro.pdf ├── 15_Interrupts.pdf ├── 16_Low_Latency_High_Bandwidth.pdf ├── 16a_Lab4_Intro.pdf ├── 17_Configuration_and_Bootloading.pdf ├── 17a_Lab5_Intro.pdf ├── 18_Profiling_and_Performance_Improvement.pdf └── 18a_Lab6_Intro.pdf └── sources ├── lab1 └── lab1.c ├── lab2 ├── iladata.ila ├── lab2.c ├── lab2_pynqz1.xdc ├── lab2_pynqz2.xdc ├── lab2_user_logic.vhd ├── math_ip.v └── math_ip │ ├── component.xml │ ├── math_ip.data │ ├── constrs_1 │ │ └── fileset.xml │ ├── sim_1 │ │ └── fileset.xml │ ├── sources_1 │ │ └── fileset.xml │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ └── webtalk_pa.xml │ ├── math_ip.srcs │ └── sources_1 │ │ └── imports │ │ └── lab2 │ │ ├── lab2_user_logic.vhd │ │ └── math_ip.v │ ├── math_ip.xpr │ └── xgui │ └── math_ip_v1_0.tcl ├── lab3 └── lab3.c ├── lab4 └── lab4.c ├── lab5 ├── bit_files.bif ├── devcfg.c ├── devcfg.h ├── lab5_qspi.c ├── lab5_sd.c ├── load_elf.s ├── pynqz1 │ ├── QSPI │ │ ├── lab1.bin │ │ ├── lab3.bin │ │ └── lab5.zip │ └── SDCard │ │ ├── lab1.bin │ │ ├── lab1elf.bin │ │ ├── lab3.bin │ │ └── lab3elf.bin └── pynqz2 │ ├── QSPI │ ├── lab1.bin │ ├── lab3.bin │ └── lab5.zip │ └── SDCard │ ├── lab1.bin │ ├── lab1elf.bin │ ├── lab3.bin │ └── lab3elf.bin └── lab6 ├── fir.c ├── fir.h ├── fir_coef.dat ├── fir_ip ├── component.xml ├── fir_ip.data │ ├── constrs_1 │ │ └── fileset.xml │ ├── sim_1 │ │ └── fileset.xml │ ├── sources_1 │ │ └── fileset.xml │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ └── webtalk_pa.xml ├── fir_ip.filter ├── fir_ip.srcs │ └── sources_1 │ │ └── imports │ │ └── verilog │ │ ├── fir.v │ │ ├── fir_ap_rst_if.v │ │ ├── fir_c.v │ │ ├── fir_c_rom.dat │ │ ├── fir_io_if.v │ │ ├── fir_shift_reg.v │ │ ├── fir_shift_reg_ram.dat │ │ └── fir_top.v ├── fir_ip.xpr ├── fir_top_0 │ ├── fir_top_0.xci │ └── fir_top_0.xml ├── fir_top_0_0 │ ├── fir_top_0.xci │ └── fir_top_0.xml └── xgui │ └── fir_top_v1_0.tcl ├── lab6.c ├── lab6.h └── xfir_fir_io.h /README.md: -------------------------------------------------------------------------------- 1 | # Advanced Embedded System Design Flow on Zynq 2 | This workshop provides participants the necessary skills to develop complex embedded systems and enable them to improve their designs by using the tools available in Vivado. It also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system in the Zynq™ System on a Chip (SoC) 3 | 4 | The labs have been developed on a PC running Microsoft Windows 10 professional edition and using **Vivado 2018.2** version tools. 5 | 6 | ## Source Files Setup 7 | 8 | To use the source files for each of the labs in this workshop, you have to clone this repository from XUP Github. For that, do the following: 9 | 10 | git clone https://github.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq.git 11 | 12 | --- 13 | #### In the instructions for the labs; 14 | 15 | **{sources}** refers to C:\xup\adv\_embedded\2018\_2\_zynq\_sources. Copy the **sources** directory from the cloned directory as 2018\_2\_zynq\_sources under c:\xup\adv\_embedded OR you can download the source files for the labs from [here](https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-adv-embedded-design-zynq.html) 16 | 17 | **{labs}** refers to C:\xup\adv\_embedded\2018\_2\_zynq\_lab. It assumes that you will create the mentioned directory structure to carry out the labs of this workshop 18 | 19 | --- 20 | **NOTE** 21 | 22 | Board support for the PYNQ-Z1 and PYNQ-Z2 are not included in Vivado 2018.2 by default. The relevant files need to be extracted and saved to: 23 | 24 | {Vivado installation}\data\boards\board\_files\zynq 25 | 26 | These files can be downloaded from [board_files](https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-adv-embedded-design-zynq.html). 27 | 28 | --- 29 | 30 | ## Hardware Setup 31 | 32 | 33 | **PYNQ-Z2**: Connect the board to the PC using a micro USB cable. Make sure that a jumper is connected to JTAG (between JP1_1 and JP1_2) to use the board in the development mode. Also, make sure that another jumper is placed between J9\_2 and J9\_3 to select USB as a power source. 34 | 35 | **PYNQ-Z1**: Connect the board to the PC using a micro USB cable. Make sure that a jumper is connected to JTAG (between JP4\_1 and JP4\_2) to use the board in the development mode. Also, make sure that another jumper is placed between JP5\_2 and JP5\_3 to select USB as a power source. 36 | 37 | ## Labs Overview: 38 | 39 | ### Lab 1 40 | 41 | This lab guides you through the process of using Vivado and IP Integrator to create a complete Zynq ARM Cortex-A9 based processor system targeting either the PYNQ-Z1 or PYNQ-Z2 boards. You will use the Block Design feature of IP Integrator to configure the Zynq PS and add IP to create the hardware system, and SDK to create an application to verify the design functionality 42 |

43 | 44 |

45 |

46 |

47 | 48 | ### Lab 2 49 | Software and hardware interact with each other in an embedded system. The SDK includes System Debugger as a software debugging tool. The hardware analyzer tool has different types of cores that allow hardware debugging by providing access to internal signals without requiring the signals to be connected to package pins. These hardware debug cores may reside in the programmable logic (PL) portion of the device and can be configured with several modes that can monitor signals within the design. In this lab you will be introduced to the various debugging cores. 50 |

51 | 52 |

53 |

54 |

55 | 56 | ### Lab 3 57 | The Zynq device supports various types of memory including volatile (e.g. DDR3) and non-volatile (e.g. QSPI Flash). There are volatile and non-volatile hard memory controllers on the Zynq PS. The PL portion of the Zynq device has plenty of Block RAM (BRAM) which can be used by an IP without contending for external resources and creating performance bottleneck. This lab guides you through the process of extending the memory space in Zynq-based platform using available PL based BRAM resource. 58 |

59 | 60 |

61 |

62 |

63 | 64 | ### Lab 4 65 | In Zynq, multiple interconnections are available between the PS and PL sections with different performance levels for data transfer between the two subsystems. The General Purpose (GP) Master and Slave AXI interconnect used in the previous labs are intended for peripherals that do not have high bandwidth requirements. E.g. switches, leds, keyboard, mouse. There are four High Performance PS slave to PL master AXI interfaces available for peripherals that need higher bandwidth. E.g. Video and image processing applications. This lab guides you through the process of enabling a High Performance AXI slave port in the PS, adding an AXI central DMA (CDMA) controller, and performing Direct Memory Access (DMA) operations between various memories. 66 |

67 | 68 |

69 |

70 |

71 | 72 | ### Lab 5 73 | This lab guides you through creating a bootable system capable of booting from the SD card or the QSPI flash memory located on the board. It also demonstrates how different bitstreams can be loaded in the PL section after the board is booted up and the corresponding application can be executed. 74 |

75 | 76 |

77 |

78 |

79 | 80 | ### Lab 6 81 | This lab guides you through the process of profiling an application and analyzing the output. The application is then accelerated in hardware and profiled again to analyze the performance improvement. 82 |

83 | 84 |

85 |

86 |

87 | -------------------------------------------------------------------------------- /images/add_ip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/add_ip.png -------------------------------------------------------------------------------- /images/connect.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/connect.png -------------------------------------------------------------------------------- /images/disconnect.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/disconnect.png -------------------------------------------------------------------------------- /images/lab1/Fig1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig1.png -------------------------------------------------------------------------------- /images/lab1/Fig10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig10.png -------------------------------------------------------------------------------- /images/lab1/Fig11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig11.png -------------------------------------------------------------------------------- /images/lab1/Fig12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig12.png -------------------------------------------------------------------------------- /images/lab1/Fig13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig13.png -------------------------------------------------------------------------------- /images/lab1/Fig14.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig14.png -------------------------------------------------------------------------------- /images/lab1/Fig15.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig15.png -------------------------------------------------------------------------------- /images/lab1/Fig16-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig16-1.png -------------------------------------------------------------------------------- /images/lab1/Fig16-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig16-2.png -------------------------------------------------------------------------------- /images/lab1/Fig17.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig17.png -------------------------------------------------------------------------------- /images/lab1/Fig18.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig18.png -------------------------------------------------------------------------------- /images/lab1/Fig2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig2.png -------------------------------------------------------------------------------- /images/lab1/Fig3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig3.png -------------------------------------------------------------------------------- /images/lab1/Fig4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig4.png -------------------------------------------------------------------------------- /images/lab1/Fig5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig5.png -------------------------------------------------------------------------------- /images/lab1/Fig6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig6.png -------------------------------------------------------------------------------- /images/lab1/Fig7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig7.png -------------------------------------------------------------------------------- /images/lab1/Fig8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig8.png -------------------------------------------------------------------------------- /images/lab1/Fig9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab1/Fig9.png -------------------------------------------------------------------------------- /images/lab2/Fig1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig1.png -------------------------------------------------------------------------------- /images/lab2/Fig10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig10.png -------------------------------------------------------------------------------- /images/lab2/Fig11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig11.png -------------------------------------------------------------------------------- /images/lab2/Fig12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig12.png -------------------------------------------------------------------------------- /images/lab2/Fig13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig13.png -------------------------------------------------------------------------------- /images/lab2/Fig14.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig14.png -------------------------------------------------------------------------------- /images/lab2/Fig15.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig15.png -------------------------------------------------------------------------------- /images/lab2/Fig16.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig16.png -------------------------------------------------------------------------------- /images/lab2/Fig17.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig17.png -------------------------------------------------------------------------------- /images/lab2/Fig18.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig18.png -------------------------------------------------------------------------------- /images/lab2/Fig19-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig19-1.png -------------------------------------------------------------------------------- /images/lab2/Fig19-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig19-2.png -------------------------------------------------------------------------------- /images/lab2/Fig19-3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig19-3.png -------------------------------------------------------------------------------- /images/lab2/Fig2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig2.png -------------------------------------------------------------------------------- /images/lab2/Fig20.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig20.png -------------------------------------------------------------------------------- /images/lab2/Fig21.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig21.png -------------------------------------------------------------------------------- /images/lab2/Fig22.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig22.png -------------------------------------------------------------------------------- /images/lab2/Fig23.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig23.png -------------------------------------------------------------------------------- /images/lab2/Fig24.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig24.png -------------------------------------------------------------------------------- /images/lab2/Fig3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig3.png -------------------------------------------------------------------------------- /images/lab2/Fig4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig4.png -------------------------------------------------------------------------------- /images/lab2/Fig5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig5.png -------------------------------------------------------------------------------- /images/lab2/Fig6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig6.png -------------------------------------------------------------------------------- /images/lab2/Fig7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig7.png -------------------------------------------------------------------------------- /images/lab2/Fig8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig8.png -------------------------------------------------------------------------------- /images/lab2/Fig9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/Fig9.png -------------------------------------------------------------------------------- /images/lab2/disconnect.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab2/disconnect.png -------------------------------------------------------------------------------- /images/lab3/Fig1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab3/Fig1.png -------------------------------------------------------------------------------- /images/lab3/Fig2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab3/Fig2.png -------------------------------------------------------------------------------- /images/lab3/Fig3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab3/Fig3.png -------------------------------------------------------------------------------- /images/lab3/Fig4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab3/Fig4.png -------------------------------------------------------------------------------- /images/lab3/Fig5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab3/Fig5.png -------------------------------------------------------------------------------- /images/lab3/Fig6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab3/Fig6.png -------------------------------------------------------------------------------- /images/lab3/Fig7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab3/Fig7.png -------------------------------------------------------------------------------- /images/lab4/Fig1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig1.png -------------------------------------------------------------------------------- /images/lab4/Fig10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig10.png -------------------------------------------------------------------------------- /images/lab4/Fig2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig2.png -------------------------------------------------------------------------------- /images/lab4/Fig3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig3.png -------------------------------------------------------------------------------- /images/lab4/Fig4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig4.png -------------------------------------------------------------------------------- /images/lab4/Fig5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig5.png -------------------------------------------------------------------------------- /images/lab4/Fig6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig6.png -------------------------------------------------------------------------------- /images/lab4/Fig7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig7.png -------------------------------------------------------------------------------- /images/lab4/Fig8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig8.png -------------------------------------------------------------------------------- /images/lab4/Fig9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab4/Fig9.png -------------------------------------------------------------------------------- /images/lab5/Fig1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig1.png -------------------------------------------------------------------------------- /images/lab5/Fig10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig10.png -------------------------------------------------------------------------------- /images/lab5/Fig2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig2.png -------------------------------------------------------------------------------- /images/lab5/Fig3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig3.png -------------------------------------------------------------------------------- /images/lab5/Fig4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig4.png -------------------------------------------------------------------------------- /images/lab5/Fig5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig5.png -------------------------------------------------------------------------------- /images/lab5/Fig6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig6.png -------------------------------------------------------------------------------- /images/lab5/Fig7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig7.png -------------------------------------------------------------------------------- /images/lab5/Fig8-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig8-1.png -------------------------------------------------------------------------------- /images/lab5/Fig9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab5/Fig9.png -------------------------------------------------------------------------------- /images/lab6/Fig1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig1.png -------------------------------------------------------------------------------- /images/lab6/Fig10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig10.png -------------------------------------------------------------------------------- /images/lab6/Fig11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig11.png -------------------------------------------------------------------------------- /images/lab6/Fig2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig2.png -------------------------------------------------------------------------------- /images/lab6/Fig3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig3.png -------------------------------------------------------------------------------- /images/lab6/Fig4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig4.png -------------------------------------------------------------------------------- /images/lab6/Fig5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig5.png -------------------------------------------------------------------------------- /images/lab6/Fig6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig6.png -------------------------------------------------------------------------------- /images/lab6/Fig7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig7.png -------------------------------------------------------------------------------- /images/lab6/Fig8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig8.png -------------------------------------------------------------------------------- /images/lab6/Fig9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/Fig9.png -------------------------------------------------------------------------------- /images/lab6/FigSort.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/lab6/FigSort.png -------------------------------------------------------------------------------- /images/resume.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/resume.png -------------------------------------------------------------------------------- /images/terminal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/terminal.png -------------------------------------------------------------------------------- /images/validate.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/validate.png -------------------------------------------------------------------------------- /images/zoom_in.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/images/zoom_in.png -------------------------------------------------------------------------------- /lab1.md: -------------------------------------------------------------------------------- 1 | # Building a Complete Embedded System 2 | 3 | ## Objectives 4 | 5 | After completing this lab, you will be able to: 6 | 7 | * Create an embedded system design using Vivado and SDK flow 8 | * Configure the Processing System (PS) 9 | * Add Xilinx standard IP in the Programmable Logic (PL) section 10 | * Use SDK to build a software project and verify the design functionality in hardware. 11 | 12 | ## Steps 13 | 14 | ## Create a Vivado Project 15 | ### Launch Vivado and create an empty project targeting the PYNQ-Z1 or PYNQ-Z2 board, selecting Verilog as a target language 16 | 1. Open Vivado by selecting **Start > All Programs >** **Xilinx Design Tools** **> Vivado 2018.2 > Vivado 2018.2** 17 | 1. Click **Create Project** to start the wizard. You will see the _Create A New Vivado Project_ wizard page. Click **Next**. 18 | 1. Click the Browse button of the _Project Location_ field of the **New Project** form, browse to **{labs}** , and click **Select**. 19 | 1. Enter **lab1** in the _Project Name_ field. Make sure that the _Create Project Subdirectory_ box is checked. Click **Next**. 20 |

21 | 22 |

23 |

24 | Project Name Entry 25 |

26 | 1. Select the **RTL Project** option in the _Project Type_ form, and click **Next**. 27 | 1. Select **Verilog** as the _Target Language_ and _Simulation Language_ in the _Add Sources_ form, and click **Next**. 28 | 1. Click **Next** to skip adding constraints. 29 | 1. In the _Default Part_ form, click **Boards** filter. 30 | 1. Select **www.digilentinc.com** for the _PYNQ-Z1_ board, **tul.com.tw** for the _PYNQ-Z2_ board in the Vendor field, select _PYNQ-Z1__or pynq-z2_, and click **Next**. 31 |

32 | 33 |

34 |

35 | Board Selection (pynq-z2) 36 |

37 | 1. Click **Finish** to create an empty Vivado project. 38 | 39 | ### Creating the Hardware System Using IP Integrator 40 | 41 | 1. Create a block design in the Vivado project using IP Integrator to generate the ARM Cortex-A9 processor based hardware system. 42 | 1. In the Flow Navigator, click **Create Block Design** under IP Integrator. 43 | 1. Name the block **system** and click **OK**. 44 | 1. Click on the button. 45 | 1. Once the IP Catalog is open, type zy into the Search bar, and double click on the **ZYNQ7 Processing System** entry to add it to the design. 46 | 1. Click on **Run Block Automation** and click **OK** to automatically configure the board presets. 47 |

48 | 49 |

50 |

51 | Zynq Block Automation View (pynq-z2) 52 |

53 | 1. Double click on the Zynq block to open the _Customization_ window for the Zynq processing system. 54 | 55 | A block diagram of the Zynq PS should now be open, showing various configurable blocks of the Processing System. 56 | 57 | 1. At this stage, designer can click on various configurable blocks (highlighted in green) and change the system configuration. 58 |

59 | 60 |

61 |

62 | Zynq Processing System Configuration View (pynq-z2) 63 |

64 | #### Configure the I/O Peripherals block to only have UART 0 support. 65 | 1. Click on the _MIO Configuration_ panel to open its configuration form. 66 | 1. Expand the I/O Peripherals (and GPIO). 67 | 1. Deselect all the peripherals except _UART 0_ (Deselect ENET 0, USB 0, SD 0, and GPIO). 68 |

69 | 70 |

71 |

72 | Selecting only UART 0 Peripheral of PS 73 |

74 | 1. Click **OK**. 75 | 76 | The configuration form will close and the block diagram will be updated as shown below. 77 |

78 | 79 |

80 |

81 | ZYNQ7 Processing System configured block 82 |

83 | ### Add one instance of GPIO, name it _buttons_, and configure for the board. Connect the block to the Zynq. 84 | 85 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **AXI GPIO** in the catalog. 86 | 1. Double-click the **AXI GPIO** to add an instance of the core to the design. 87 | 1. Click on the **AXI GPIO** block to select it, and in the _Block properties_ tab, change the name to **buttons.** 88 | 1. Double click on the **AXI GPIO** block to open the customization window. Under _Board Interface_, for _GPIO_, click on **Custom** to view the drop down menu options, and select **btns 4Bits** for the PYNQ-Z2 or the PYNQ-Z1 board. 89 | 90 | As the board was selected during the project creation, and a board support package is available for these boards, Vivado has knowledge of available resources on the board. 91 | 92 | 1. Click the **IP Configuration** tab. Notice the GPIO Width is set to 4 (PYNQ-Z1 and PYNQ-Z2) and is greyed out. If a board support package was not available, the width of the IP could be configured here. 93 | 1. Click **OK** to finish configuring the GPIO and to close the _Re-Customize IP_ window. 94 | 1. Click on **Run Connection Automation** , and select **buttons** (which will include GPIO and S\_AXI) 95 | 96 | Click on **GPIO** and **S\_AXI** to check the default connections for these interfaces. 97 |

98 | 99 |

100 |

101 | Connection Automation for the GPIO (PYNQ-Z2) 102 |

103 | 1. Click **OK** to automatically connect the _S\_AXI_ interface to the Zynq _GP0_ port (through the AXI interconnect block), and the GPIO port to an external interface. 104 | 105 | Notice that after block automation has been run, two additional blocks that are required to connect the blocks, _Processor System Reset_, and _AXI Interconnect_ have automatically been added to the design. 106 | 107 | 1. Add another instance of GPIO, name the instance _leds_, configure it and connect it to the Zynq. 108 | 1. Add another instance of the _GPIO_ peripheral **.** 109 | 1. Change the name of the block to **leds.** 110 | 1. Double click on the _leds_ block, and select **leds 4bits** (PYNQ-Z1 and PYNQ-Z2) for the _GPIO_ interface and click **OK.** 111 | 1. Click on **Run Connection Automation** 112 | 1. Click **leds** , and check the connections for _GPIO_ and _S\_AXI_ as before 113 | 1. Click **OK** to automatically connect the interfaces as before. 114 | 115 | Notice that the AXI Interconnect block has the second master AXI (M01\_AXI) port added and connected to the S\_AXI of the leds. 116 | 117 | 1. Add another instance of GPIO, name the instance _switches_, configure it and connect it to the Zynq. 118 | 1. Add another instance of the _GPIO_ peripheral **.** 119 | 1. Change the name of the block to **switches.** 120 | 1. Double click on the _switches_ block, and select **sws 2bits** (PYNQ-Z1 and PYNQ-Z2) for the _GPIO_ interface and click **OK.** 121 | 1. Click on **Run Connection Automation** 122 | 1. Click **switches** , and check the connections for _GPIO_ and _S\_AXI_ as before 123 | 1. Click **OK** to automatically connect the interfaces as before. 124 | 125 | Notice that the AXI Interconnect block has the third master AXI (M02\_AXI) port added and connected to the S\_AXI of the leds. 126 | 127 | At this stage the design should look like as shown below. 128 |

129 | 130 |

131 |

132 | Completed design 133 |

134 | 1. Verify that the addresses are assigned to the two GPIO instances and validate the design for no errors. 135 | 1. Select the **Address Editor** tab and see that the addresses are assigned to the three GPIO instances. They should look like as follows. 136 |

137 | 138 |

139 |

140 | Assigned addresses 141 |

142 | The addresses should be in the 0x40000000 to 0xbfffffff range as the instances are connected to M\_AXI\_GP0 port of the processing system instance. 143 | 144 | 1. Select the _Diagram_ tab, and click on the ![alt tag](./images/validate.png) 145 | (Validate Design) button to make sure that there are no errors. 146 | 147 | Ignore warnings. 148 | 149 | 1. Select **File > Save Block Design** to save the design. 150 | 1. Since all IO pins are board-aware no additional user constraints are need. 151 | 152 | ### Generate the Bitstream 153 | 1. Create the top-level HDL of the embedded system. Add the provided constraints file and generate the bitstream. 154 | 1. In Vivado, select the _Sources_ tab, expand the _Design Sources,_ right-click the _system.bd_ and select **Create HDL Wrapper…** 155 |

156 | 157 |

158 |

159 | Selecting the system design to create the wrapper file 160 |

161 | 1. Click **OK** when prompted to allow Vivado to automatically manage this file. 162 | 163 | The wrapper file, _system\_wrapper.v_, is generated and added to the hierarchy. The wrapper file will be displayed in the Auxiliary pane. 164 |

165 | 166 |

167 |

168 | Design Hierarchy View 169 |

170 | 1. Click on the **Generate Bitstream** in the _Flow Navigator_ pane to synthesize and implement the design, and generate the bitstream. Click **Save** and **Yes** if prompted. Click **OK** to launch the runs. 171 | 1. When the bitstream generation is complete, click **Cancel**. 172 | 173 | ### Export the Design to the SDK 174 | #### Exporting the design and launch SDK 175 | 1. Export the hardware configuration by clicking **File > Export > Export Hardware** … Tick the box to include the bitstream and click **OK**. 176 |

177 | 178 |

179 |

180 | Exporting the hardware 181 |

182 | 1. Launch SDK by clicking **File > Launch SDK** and click **OK** 183 | 184 | (Launching SDK from Vivado will automatically load the SDK workspace associated with the current project. If launching SDK standalone, the workspace will need to be selected.) 185 | 186 | ## Generate an Application in SDK 187 | ### Generate a board support package project with default settings and default software project name. 188 | 189 | SDK should open and automatically create a hardware platform project based on the configuration exported from Vivado. A board support package and software application will be created and associated with this hardware platform. 190 | 191 | 1. Select **File** > **New** > **Board Support Package** 192 |

193 | 194 |

195 |

196 | Create BSP 197 |

198 | 1. Click **Finish** with the default settings selected (using the Standalone operating system). 199 | 200 | This will open the Software Platform Settings form showing the OS and libraries selections. 201 | 202 | 1. Click **OK** to accept the default settings as we want to create a **standalone\_bsp\_0** software platform project without any additional libraries. 203 | 1. The library generator will run in the background and will create the **xparameters.h** file in the **lab1.sdk\standalone\_bsp\_0\ps7\_cortexa9\_0\include** directory. 204 | 1. Create an empty application project, named lab1, and import the provided lab1.c file. 205 | 1. Select **File > New** > **Application Project.** 206 | 1. In the _Project Name_ field, enter **lab1** as the project name. 207 | 1. Select the _Use existing_ option in the _Board Support Package_ field and then click **Next.** 208 |

209 | 210 |

211 |

212 | Create a Blank Application Project 213 |

214 | 1. Select the **Empty Application** template and click **Finish.** 215 | 216 | The lab1 project will be created in the Project Explorer window of SDK. 217 | 218 | 1. Select **lab1 > src** directoryin the project view, right-click, and select **Import.** 219 | 1. Expand the **General** category and double-click on **File System.** 220 | 1. Browse to the **{sources}\lab1** folder. 221 | 1. Select the **lab1.c** source file and click **Finish.** 222 | 223 | A snippet of the source code is shown in the following figure. Note the greyed out code will be used in Lab5. The code reads from the switches, and writes to the LEDs. The BTN is read, and written to the LED. 224 |

225 | 226 |

227 |

228 | 229 |

230 |

231 | Snippet of Source Code 232 |

233 | ## Test in Hardware 234 | ### Connect and power up the board. Establish serial communications using the SDK's Terminal tab. Verify the design functionality. 235 | 1. Connect and power up the board. 236 | 1. Select the ![alt tag](./images/terminal.png) 237 | tab. If it is not visible then select **Window > Show view > Other > Terminal > Terminal**. 238 | 1. Click on ![alt tag](./images/connect.png) and select appropriate COM port (depending on your computer), and configure the terminal with the parameters as shown below. 239 |

240 | 241 |

242 |

243 | SDK Terminal Settings 244 |

245 | 1. Select **Xilinx** > **Program FPGA** and then click the **Program** button. 246 | 1. Make sure that the **SW0-1** are not set to "11". 247 | 1. Select the **lab1** project in the _Project Explorer_, right-click and select **Run As > Launch on Hardware(System Debugger)** to download the application, execute ps7\_init, and execute lab1.elf. 248 | 1. You should see the following output on the Terminal console. 249 |

250 | 251 |

252 |

253 | SDK Terminal Output 254 |

255 | 1. Press BTN0-BTN3 (PYNQ-Z1, PYNQ-Z2) and see the corresponding LED light up. 256 | 1. Set the two slide switches on PYNQ-Z1 or PYNQ-Z2 to the ON position to exit the program. 257 | 1. Close SDK and Vivado programs by selecting **File > Exit** in each program. 258 | 1. Turn OFF the power to the board. 259 | 260 | ## Conclusion 261 | 262 | In this lab, you created an ARM Cortex-A9 processor based embedded system using the Zynq device for the PYNQ-Z1/PYNQ-Z2 board. You instantiated the Xilinx standard GPIO IP to provide input and output functionality. 263 | 264 | You created the project in Vivado, created the hardware system using IPI, implemented the design in Vivado, exported the generated bitstream to the SDK, created a software application in the SDK, and verified the functionality in hardware after programming the PL section and running the application from the DDR memory. -------------------------------------------------------------------------------- /lab2.md: -------------------------------------------------------------------------------- 1 | # Debugging Using Hardware Analyzer 2 | 3 | ## Objectives 4 | After completing this lab, you will be able to: 5 | 6 | * Add a VIO core in the design 7 | * Use a VIO core to inject stimulus to the design and monitor the response 8 | * Mark nets as debug so AXI transactions can be monitored 9 | * Add an ILA core in Vivado 10 | * Perform hardware debugging using the hardware analyzer 11 | * Perform software debugging using the SDK 12 | 13 | ## Steps 14 | 15 | ## Open the Project 16 | ### Open the Vivado program. Open the lab1 project you created in the previous lab or use the lab1 project from the labsolution directory, and save the project as lab2. Set Project Settings to point to the IP repository provided in the sources directory. 17 | 18 | 1. Start Vivado if necessary and open either the lab1 project (lab1.xpr) you created in the previous lab or the lab1 project in the labsolutions directory using the **Open Project** link in the Getting Started page. 19 | 1. Select **File > Project > Save As …** to open the Save Project As dialog box. Enter lab2 as the project name. Make sure that the Create Project Subdirectory option is checked, the project directory path is {labs} and click **OK.** 20 | This will create the lab2 directory and save the project and associated directory with lab2 name 21 | 1. Click **Settings** in the _Flow Navigator_ pane. 22 | 1. Expand **IP** in the left pane of the _Project Settings_ form and select **Repository.** 23 | 1. Click on the _plus_ button of the IP Repositories panel, browse to **{sources}\lab2\math_ip** and click **Select.** 24 | The directory will be scanned and one IP will be detected and reported. 25 |

26 | 27 |

28 |

29 | Specify IP Repository 30 |

31 | 1. Click **OK** twice to close the window. 32 | 33 | ## Add the Custom IP 34 | ### Open the Block Design and add the custom IP to the system. 35 | 1. Click **Open Block Design** in the _Flow Navigator_ pane to open the block diagram. 36 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **math** in the catalog. 37 | 1. Double-click the **math\_ip\_v1\_0** to add an instance of the core to the design. 38 | 1. Click on **Run Connection Automation**, ensure math\_ip\_0 and S\_AXI are selected, and click **OK.** 39 | 40 | The _Math IP_ consists of a hierarchical design with the lower-level module performing the addition. The higher-level module includes the two slave registers. 41 |

42 | 43 |

44 |

45 | Custom Core's Main Functional Block 46 |

47 | ## Add the ILA and VIO Cores 48 | 49 | We want to connect the ILA core to the LED interface. Vivado prohibits connecting ILA cores to interfaces. In order to monitor the LED output signals, we need to convert the LED interface to simple output port. 50 | 51 | ### Disable LEDs interface. 52 | 1. Double-click the _leds_ instance to open its configuration form. 53 | 1. Click **Clear Board Parameters** and click **OK** to close the configuration form. 54 | 1. Select _leds\_4bit_ port and delete it. 55 | 1. Expand the _gpio_ interface of the **leds** instance to see the associate ports. 56 | ### Make the gpio\_io\_o port of the leds instance external and rename it as _leds_. 57 | 1. Move the mouse close to the end of the _gpio\_io\_o_ port, left-click to select (do not select the main GPIO port), and then right click and select **Make External**. 58 |

59 | 60 |

61 |

62 | Select the gpio_io_o port 63 |

64 | The port connector named gpio_io_o will be created and connected to the port. 65 | 66 | 1. Select the port _gpio\_io\_o_ and change its name to **leds** by typing it in the properties form. 67 | 1. Enable cross triggering between the PL and PS 68 | 1. Double click on the _Zynq_ block to open the configuration properties. 69 | 1. Click on PS-PL Configuration, and enable the _PS-PL Cross Trigger interface_. 70 | 1. Expand _PS-PL Cross Trigger interface > Input Cross Trigger_, and select **CPU0 DBG REQ** for _Cross Trigger Input 0._ 71 | 1. Similarly, expand Output Cross Trigger, and select **CPU0 DBG ACK** for _Cross Trigger Output 0_ and click **OK.** 72 |

73 | 74 |

75 |

76 | Enabling cross triggering in the Zynq processing system 77 |

78 | ### Add the ILA core and connect it to the LED output port. 79 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **ila** in the catalog. 80 | 1. Double-click on the **ILA (Integrated Logic Analyzer)** to add an instance of it. The _ila\_0_ instance will be added. 81 | 1. Double-click on the _ila\_0_ instance. 82 | 1. Select **Native** as the _Monitor type_. 83 | 1. Enable _Trigger Out Port_, and _Trigger In port._ 84 | 1. Select the **Probe Ports** tab, and set the **Probe Width** of _PROBE0_ to **4** and click **OK**. 85 | 1. Using the drawing tool, connect the **PROBE0** port of the _ila\_0_ instance to the **gpio\_io\_o** port of the _leds_ instance. 86 | 1. Connect the **clk** port of the _ila\_0_ instance to the **FCLK\_CLK0** port of the Zynq subsystem. 87 | 1. Connect **TRIGG\_IN** of the ILA to **TRIGGER\_OUT\_0** of the Zynq processing system, and **TRIG\_OUT** of the ILA to the **TRIGGER\_IN\_0**. 88 | ### Add the VIO core and connect it to the math\_ip ports. 89 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **vio** in the catalog. 90 | 1. Double-click on the **VIO (Virtual Input/Output)** to add an instance of it. 91 | 1. Double-click on the _vio_instance to open the configuration form. 92 | 1. In the _General Options_ tab, leave the _Input Probe Count_ set to **1** and set the _Output Probe Count_ to **3** 93 | 1. Select the _PROBE\_IN Ports_ tab and set the _PROBE\_IN0_ width to **9**. 94 | 1. Select the _PROBE\_OUT Ports_ tab and set _PROBE\_OUT0_ width to **1** , _PROBE\_OUT1_ width to **8** , and _PROBE\_OUT2_ width to **8**. 95 | 1. Click **OK**. 96 | 1. Connect the VIO ports to the math instance ports as follows: 97 | ``` 98 | PROBE_IN -> result 99 | PROBE_OUT0 -> sel 100 | PROBE_OUT1 -> ain_vio 101 | PROBE_OUT2 -> bin_vio 102 | ``` 103 | 1. Connect the **CLK** port of the _vio\_0_ to FCLK\_CKL0 net. 104 | 1. The block diagram should look similar to shown below. 105 |

106 | 107 |

108 |

109 | VIO added and connections made 110 |

111 | ### Mark Debug the S\_AXI connection between the AXI Interconnect and math\_0 instance. Validate the design. 112 | 1. Select the **S\_AXI** connection between the AXI Interconnect and the _math\_ip\_0_ instance **.** 113 | 1. Right-click and select **Debug** to monitor the AXI4Lite transactions. 114 | 115 | Notice that a system\_ila IP instance got added and the M03\_AXI <-> S\_AXI connection is connected to its SLOT\_0\_AXI interface. 116 | 117 | The block diagram should look as shown below. 118 |

119 | 120 |

121 |

122 | Block diagram of the design after marking AXI connection to the math_ip_0 instance for debugging 123 |

124 | 1. Click the **Run Connection Automation** link to see the form where you can select the desired channels to monitor. 125 | 1. Change _AXI Read Address_ and _AXI Read Data_ channels to **Data** since we will not trigger any signals of those channels. 126 | 127 | This saves resources being used by the design. 128 |

129 | 130 |

131 |

132 | Selecting channels for debugging 133 |

134 | 1. Select the _Diagram_ tab, and click on the ![alt tag](./images/validate.png) (Validate Design) button to make sure that there are no errors. 135 | 1. Verify that there are no unmapped addresses shown in the _Address Editor_ tab. 136 | ## Add Design Constraints and Generate Bitstream 137 | ### Add the provided lab2\_<board>.xdc from the sources\lab2 directory. Generate bitstream. 138 | 1. Right click in the _Sources_ panel, and select **Add Sources.** 139 | 1. Select _Add or Create Constraints_ and click **Next**. 140 | 1. Click the _Plus_ button then **Add Files**, browse to **{sources}\lab2\** and select **lab2\_pynz1.xdc,** or **lab2\_pynqz2.xdc** depending on the board you are using. 141 | 1. Click **OK** and then click **Finish.** 142 | 1. Click on the **Generate Bitstream** to run the implementation and bit generation processes. 143 | 1. Click **Save** to save the project (if prompted), **OK** to ignore the warning (if prompted), and **Yes** to launch Implementation (if prompted). Click **OK** to launch the runs. 144 | 1. When the bitstream generation process has completed successfully, click **Cancel**. 145 | ## Generate an Application in SDK 146 | ### Export the implemented design and launch SDK. 147 | 1. Export the hardware configuration by clicking **File > Export > Export Hardware…** , click the box to _Include Bitstream_ 148 | 1. Click **OK** to export and **Yes** to overwrite the previous project created by lab1. 149 | 1. Launch SDK by clicking **File > Launch SDK** and click **OK.** 150 | 1. Right-click on the **lab1** and **standalone\_bsp\_0** and **system\_wrapper\_hw\_platfrom\_0** projects in the Project Explorer view and select **close project**. 151 | ### Create an empty application project named lab2, and import the provided lab2.c file. 152 | 1. Select **File > New** > **Application Project.** 153 | 1. In the _Project Name_ field, enter **lab2** as the project name, leave all other settings to their default's and click **Next** (a new BSP will be created) **.** 154 | 1. Select the **Empty Application** template and click **Finish.** 155 | 156 | The lab2 project will be created in the Project Explorer window of the SDK. 157 | 158 | 1. Select **lab2 > src** in the project view, right-click, and select **Import.** 159 | 1. Expand the **General** category and double-click on **File System.** 160 | 1. Browse to the **{sources}\lab2** folder. 161 | 1. Select **lab2.c** and click **Finish.** 162 | 163 | A snippet of the part of the source code is shown in the following figure. It shows that two operands are written to the custom core, the result is read, and printed out. The write transaction will be used as a trigger condition in the Vivado Logic Analyzer. 164 |

165 | 166 |

167 |

168 | Source Code snippet 169 |

170 | 1. Right click on _lab2_, and select **Debug As > Debug Configurations** 171 | 1. Double click on Xilinx C/C++ application (System Debugger) to create a new configuration (_lab2 Debug will be created_), and in the _Target__Setup_ tab, check the **Enable Cross-Triggering** option **,** and click the Browse button. 172 |

173 | 174 |

175 |

176 | Enable cross triggering in the software environment 177 |

178 | 1. When the _Cross Trigger Breakpoints_ dialog box opens, click **Create** 179 | 1. Select the options as shown below and click **OK** to set up the cross-trigger condition for _Processor to Fabric_. 180 |

181 | 182 |

183 |

184 | Enabling CPU0 for request from PL 185 |

186 | 1. In the _Cross Trigger Breakpoints_ dialog box click **Create** again. 187 | 1. Select the options as shown below and click **OK** to set up the cross trigger condition for _Fabric to Processor_. 188 |

189 | 190 |

191 |

192 | Enabling CPU0 for request to PL 193 |

194 | 1. Click **OK** , then click **Apply,** then **Close** 195 | ## Test in Hardware 196 | ### Connect and power up the board. Download the bitstream into the target device. Start the debug session on lab2 project. Switch to the Debug perspective and establish serial communication. 197 | 1. Connect and power up the board. 198 | 1. Select **Xilinx** > **Program FPGA** and click **Program** 199 | 1. Select the **lab2** project in _Project Explorer_, right-click and select **Debug As > Launch on Hardware** (System Debugger) to download the application, execute ps7\_init. (If prompted, click **Yes** to switch to the Debug perspective.) The program execution starts and suspends at the entry point. 200 | 1. Select the ![alt tag](./images/terminal.png) tab. If it is not visible then select **Window > Show view > Terminal** tab. 201 | 1. Click on ![alt tag](./images/connect.png) and select the appropriate COM port (depending on your computer), and configure it as you did it in Lab 1. 202 | ### Start the hardware session from Vivado. 203 | 1. Switch to Vivado. 204 | 1. Click on **Open Hardware Manager** from the _Program and Debug_ group of the _Flow Navigator_ pane to invoke the analyzer. 205 | 1. Click on the **Open Target > Auto connect** to establish the connection with the board. 206 | 1. Select **Window > Debug Probes** 207 | 208 | The hardware session will open showing the **Debug Probes** tab in the **Console** view. 209 |

210 | 211 |

212 |

213 | Debug probes 214 |

215 | The hardware session status window also opens showing that the FPGA is programmed (we did it in SDK), there are three cores out of which the two ila cores are in the idle state. 216 |

217 | 218 |

219 |

220 | Hardware session status 221 |

222 | 1. Select the XC7Z020, and click on the **Run Trigger Immediate** button to see the signals in the waveform window. 223 |

224 | 225 |

226 |

227 | Opening the waveform window 228 |

229 | ### Setup trigger conditions to trigger on a write transaction (WSTRB) when the desired data (WDATA) of XXXX\_XX12 is written. The transaction takes place when WVALID and WREADY are equal to 1. 230 | 1. Click on the _hw\_ila\_2_ tab to select it. In the **Debug Probes** window, under _hw\_ila\_2_, drag and drop the **WDATA** signal to the _ILA Basic Trigger setup_ window **.** 231 | 1. Set the value to **XXXX\_XX12** (HEX) (the value written to the math\_0 instance at line 24 of the program). 232 | 1. Similarly, add **WREADY,**** WSTRB, **and** WVALID** signals to the _ILA Basic Trigger setup_ window. 233 | 1. Change the radix to binary for _WSTRB_, and change the value from **xxxx** to **xxx1** 234 | 1. Change the value of **WVALID** and **WREADY** to 1. 235 | 1. Set the trigger position of the _hw\_ila\_2_ to **512** in the _Settings – hw\_ila\_2_ 236 |

237 | 238 |

239 |

240 | Setting up the ILA 241 |

242 | 1. Similarly, set the trigger position in the _Settings __–__ hw\_ila\_1_ tab to **512**. 243 | 1. Select **hw\_ila\_2** in the _Hardware_ window and click on the **Run Trigger** button and observe that the _hw\_ila\_2_ core is armed and showing the status as **Waiting For Trigger**. 244 |

245 | 246 |

247 |

248 | Hardware analyzer running and in capture mode 249 |

250 | 1. Switch to SDK. 251 | 1. Near line 27 (right click in the margin and select _Show Line Numbers_ if necessary_),_ double click on the left border on the line where xil\_printf statement is (before the while (1) statement) is defined in the lab2.c window to set a breakpoint. 252 |

253 | 254 |

255 |

256 | Setting a breakpoint 257 |

258 | 1. Click on the **Resume** (![alt tag](./images/resume.png)) button to execute the program and stop at the breakpoint. 259 | 1. In the Vivado program, notice that the **hw\_ila\_2** status changed from _Waiting for Trigger_ to _Idle_, and the waveform window shows the triggered output (select the _hw\_ila\_data\_2.wcfg_ tab if necessary). 260 | 1. Move the cursor to closer to the trigger point and then click on the ![alt tag](./images/zoom_in.png) button to zoom at the cursor. Click on the **Zoom In** button couple of times to see the activity near the trigger point. Similarly, you can see other activities by scrolling to right as needed. 261 |

262 | 263 | 264 | 265 |

266 |

267 | Zoomed waveform view of the three AXI transactions 268 |

269 | Observe the following: 270 | 271 | Around the 512th sample WDATA being written is 0x012 at offset 0 (AWADDR=0x0). 272 | At the 536th sample, offset is 0x4 (AWADDR), and the data being written is 0x034. 273 | At the 559th sample, data is being read from the IP at the offset 0x0 (ARADDR), and at 561# st mark the result (0x46) is on the RDATA bus. 274 | 1. You also should see the following output in the SDK Terminal console. 275 |

276 | 277 |

278 |

279 | Terminal Output 280 |

281 | ### In Vivado, select the VIO Cores related from the Dashboard Options windows, set the vio\_1\_probe\_out0 so math\_ip's input can be controlled manually through the VIO core. Try entering various values for the two operands and observe the output on the math\_ip\_1\_result port in the Console pane. 282 | 1. Select the **hw\_vio\_1** core in the _Dashboard Options_ panel. 283 | 1. Click on the ![alt tag](./images/add_ip.png) button and select all signals to stimulate and monitoring. Change the **vio\_0\_probe\_out0** value to **1** so the math\_ip core input can be controlled via the VIO core. 284 |

285 | 286 |

287 |

288 | VIO probes 289 |

290 | 1. Change **vio\_0\_probe\_out1** value to **55** (in Hex), and similarly, **vio\_0\_probe\_out2** value to **44** (in Hex). Notice that for a brief moment a blue-colored up-arrow will appear in the Activity column and the result value changes to **099** (in Hex). 291 |

292 | 293 |

294 |

295 | Input stimuli through the VIO core's probes 296 |

297 | 1. Try a few other inputs and observe the outputs. 298 | 1. Once done, set the _vio\_0\_probe\_out0_ to **0** to isolate the vio interactions with the math\_ip core. 299 | ### Setup the ILA core (hw\_ila\_1) trigger condition to 0x2 for the PYNQ-Z1/PYNQ-Z2. Make sure that the switches on the board are not set at x3 (for PYNQ-Z1/PYNQ-Z2). Set the trigger equation to be ==, and arm the trigger. Click on the Resume button in the SDK to continue executing the program. Change the switches and observe that the hardware core triggers when the preset condition is met. 300 | 1. Select the **hw\_ila\_1** in the _Dashboard Options_ panel. 301 | 1. Add the LEDs to the _Basic Trigger Setup_, and set the trigger condition of the _hw\_ila\_1_ to trigger at LED output value equal to **0x5** for the PYNQ-Z1/PYNQ-Z2. 302 |

303 | 304 |

305 |

306 | Setting up Trigger for hw_ila_1 307 |

308 | 1. Ensure that the trigger position for the _hw\_ila\_1_ is set to **512**. 309 | 310 | Make sure that the switches are not set to 11 (PYNQ-Z1/PYNQ-Z2) as this is the exit pattern. 311 | 312 | 1. Right-click on the _hw\_ila\_1_ in the _hardware_ window, and arm the trigger by selecting **Run Trigger.** 313 | 314 | The hardware analyzer should be waiting for the trigger condition to occur. 315 | 316 | 1. In the SDK window, click on the _Resume_ button. 317 | 1. Press the push-buttons and see the corresponding LED turning ON and OFF. 318 | 1. When the condition is met, the waveform will be displayed. 319 |

320 | 321 |

322 |

323 | ILA waveform window after Trigger 324 |

325 | ### Cross trigger a debug session between the hardware and software 326 | 1. In Vivado, select _hw\_ila\_1_ 327 | 1. In the ILA properties, set the _Trigger mode_ to **BASIC\_OR\_TRIGG\_IN** , and the _TRIG\_OUT_ mode to **TRIGGER\_OR\_TRIG\_IN** 328 | 1. In SDK, in the C/C++ view, relaunch the software by right clicking on the lab2 project, and selecting _Debug As > Launch on Hardware (System Debugger)_. 329 | 330 | Click **OK** if prompted to reset the processor. 331 | The program will be loaded and the excution will suspend at the entry point 332 | 333 | 1. Arm the _hw\_ila\_1_ trigger. 334 | 1. In SDK continue execution of the software to the next breakpoint (line 27). 335 | 336 | When the next breakpoint in SDK is reached, return to Vivado and notice the ILA has triggered. 337 | 338 | ### Trigger the ILA and cause the software to halt 339 | 1. Click Step Over (F6) button twice to pass the current breakpoint 340 | 1. Arm the _hw\_ila\_1_ trigger 341 | 1. Resume the software (F8) until it enters the while loop 342 | 1. Verify it is executing by toggling the dip switches 343 | 1. In Vivado, arm the _hw\_ila\_1_ trigger 344 | 1. Press the push-buttons to 0x5, and notice that the application in SDK will break at some point (This point will be somewhere within the while loop) 345 | 1. Click on the **Resume** button 346 | 347 | The program will continue execution. Flip switches until it is _0x03_. 348 | 349 | 1. Click the Disconnect button (![alt tag](./images/disconnect.png)) in the SDK to terminate the execution. 350 | 1. Close the SDK by selecting **File > Exit**. 351 | 1. Close the hardware session by selecting **File > Close Hardware Manager**. Click **OK**. 352 | 1. Close Vivado program by selecting **File > Exit**. 353 | 1. Turn OFF the power on the board. 354 | 355 | ## Conclusion 356 | 357 | In this lab, you added a custom core with extra ports so you can debug the design using the VIO core. You instantiated the ILA and the VIO cores into the design. You used Mark Debug feature of Vivado to debug the AXI transactions on the custom peripheral. You then opened the hardware session from Vivado, setup various cores, and verified the design and core functionality using SDK and the hardware analyzer. 358 | 359 | . -------------------------------------------------------------------------------- /lab3.md: -------------------------------------------------------------------------------- 1 | # Extending Memory Space with Block RAM 2 | 3 | ## Objectives 4 | 5 | After completing this lab, you will be able to: 6 | 7 | * Add BRAM and connect it to the processing system's AXI master port 8 | * Execute the software application having data section in the BRAM 9 | 10 | ## Steps 11 | ## Open the Project 12 | ### Open the Vivado program. Open the _lab1_ project you created earlier or use the _lab1_ project from the labsolution directory, and save the project as _lab3_. 13 | 1. Start Vivado if necessary and open either the _lab1_ project (lab1.xpr) you created earlier or the lab1 project in the _labsolutions_ directory using the **Open Project** link in the Getting Started page. 14 | 1. Select **File > Project > Save As …** to open the _Save Project As_ dialog box. Enter **lab3** as the project name. Make sure that the _Create Project Subdirectory_ and _Import All Files to the New Project_ options are checked, the project directory path is **{labs}** and click **OK**. 15 | 16 | This will create the _lab3_ directory and save the project and associated directory with lab3 name. 17 | 18 | ## Configure the Processor to Enable M\_AXI\_GP1 19 | 1. Open the Block Design and enable the M\_AXI\_GP1 interface. 20 | 1. Click **Open Block Design** in the _Flow Navigator_ pane 21 | 1. Double-click on the _Zynq processing system_ instance to open its configuration form. 22 | 1. Select _PS-PL Configuration_ in the Page Navigator window in the left pane, expand _AXI Non Secure Enablement>GP Master AXI Interface_, and click on the check-box of the **M\_AXI GP1 Interface** to enable it. 23 | 1. Select _Clock Configuration_ in the Page Navigator window in the left pane, expand _PL Fabric Clocks_ on the right, and click on the check-box of the **FCLK\_CLK1** to enable it. 24 | 1. Enter the_Requested Frequency_for the **FCLK\_CLK1** as **140.00000** MHz. 25 | 1. Click **OK** to accept the settings and close the configuration form. 26 | 27 |

28 | 29 |

30 |

31 | M_AXI_GP1 interface enabled 32 |

33 | 34 | ## Extend with BRAM 35 | ### Add an AXI BRAM Controller instance with BRAM. 36 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **BRAM** in the catalog. 37 | 1. Double-click the **AXI BRAM Controller** to add an instance to the design. 38 | 1. Click on **Run Connection Automation** , and select **axi\_bram\_ctrl\_0** 39 | 1. Click on **BRAM\_PORTA** and **BRAM\_PORTB** check boxes. 40 | 1. Click **S\_AXI** , and change the _Master_ option to **/processing\_system7\_0/M\_AXI\_GP1**, change the Clock source for driving interconnect IP, Clock source for Master interface,_ and _Clock source for Salve interface_ to **/processing\_system7\_0/FCLK\_CLK1 (140 MHz)** as they all run in the same clock domain, and click **OK** 41 | 42 |

43 | 44 |

45 |

46 | Connecting AXI BRAM Controller to M_AXI_GP1 to run at faster clock speed 47 |

48 | 49 | Notice that an instance of AXI SmartConnect and Processor System Reset are added, and the M\_AXI\_GP1\_ ACLK is connected to FCLK\_CLK1. 50 | 51 |

52 | 53 |

54 |

55 | Clocking network connections 56 |

57 | 1. Double-click on the **axi\_bram\_ctrl\_0** instance to open the configuration form. 58 | 1. Set the _Data Width_ to **64**. 59 | 60 |

61 | 62 |

63 |

64 | Setting the BRAM controller data width to 64 65 |

66 | 1. Click **OK**. 67 | ### Using the Address Editor tab, set the BRAM controller size to 64KB. Validate the design. 68 | 1. Select the **Address Editor** tab and notice that the BRAM controller memory space is **8K**. 69 | 1. Click in the _Range_ column of the _axi\_bram\_ctrl\_0_ instance and set the size as **64K**. 70 | 71 |

72 | 73 |

74 |

75 | AXI BRAM space assignment 76 |

77 | 78 | Notice that the address range changed to 0x80000000-0x8000FFFF. This is in the M\_GP1 addressing space. 79 | 80 | 1. Select the _Diagram_ tab, and click on the ![alt tag](./images/validate.png) (Validate Design) button to make sure that there are no errors. 81 | ## Generate the Bitstream 82 | 1. Click on the **Generate Bitstream** to run the synthesis, implementation, and bit generation processes. 83 | 1. Click **Save** if prompted to save the project, and **Yes** to run the processes. Click **OK** to launch the runs. 84 | 1. When the bitstream generation process has completed successfully, click **Cancel**. 85 | ## Generate Applications in the SDK 86 | ### Export the implemented design, and start SDK 87 | 1. Export the hardware configuration by clicking **File > Export > Export Hardware…** 88 | 1. Click the box to _Include Bitstream_and click **OK** (Click _Yes_ if prompted to overwrite the previous module) 89 | 1. Launch SDK by clicking **File > Launch SDK** and click **OK** 90 | 1. Right-click on the **lab1** and **standalone\_bsp\_0** and **system\_wrapper\_hw\_platfrom\_0** projects in the Project Explorer view and select **close project**. 91 | ### Create an empty application project, named lab3, and import the provided lab3.c file. 92 | 1. Select **File > New** > **Application Project.** 93 | 1. In the _Project Name_ field, enter **lab3** as the project name. 94 | 1. Use the default settings to create a new BSP and click **Next.** 95 | 1. Select the **Empty Application** template and click **Finish.** 96 | 97 | The lab3 and lab3\_bsp projects will be created in the Project Explorer window of SDK. 98 | 99 | 1. Select **lab3 > src** directoryin the project view, right-click, and select **Import.** 100 | 1. Expand the **General** category and double-click on **File System.** 101 | 1. Browse to **{sources}\lab3** folder. 102 | 1. Select **lab3.c** and click **Finish.** 103 | 104 | A snippet of the source code is shown in the following figure. It shows that we write a pattern to the LED port and execute a software delay loop. Repeat for 16 times. It also shows the code (greyed) which will be used in Lab5. 105 | 106 |

107 | 108 |

109 |

110 | Source Code 111 |

112 | 113 | ## Test in Hardware 114 | ### Connect and power up the board. Establish the serial communication using the SDK Terminal tab. Program the FPGA. 115 | 1. Connect and power up the board. 116 | 1. In SDK, select **Xilinx > Program FPGA** and click the **Program** button to program the FPGA. 117 | 1. Select the ![alt tag](./images/terminal.png) tab. If it is not visible then select **Window > Show view > Terminal**. 118 | 1. Click on ![alt tag](./images/connect.png) to initiate the serial connection and select the appropriate COM port (depending on your computer). Configure it with 115200 baud rate. 119 | ### Run the lab3 application. 120 | 1. Select the **lab3** project in _Project Explorer_, right-click and select **Run As > Launch on Hardware (System Debugger).** Click **Yes** to terminate the previous run. 121 | 122 | The application (lab3.elf) will be downloaded into the target device, execute ps7\_init, and execute. 123 | 124 | 1. You should see the on-board LEDs changing patterns at roughly a one second delay rate. 125 | ### Modify the linker scipt to use the ps7\_ddr\_0 for the code and data sections, and the BRAM for the Heap and Stack segments. Change the loop limit from 99999999 to 999999. Execute the program. 126 | 1. Select the **lab3** application in the _Project Explorer_ view. 127 | 1. Right-click and select **Generate Linker Script**. 128 | 1. Change the _code_ and _Data_ sections to **ps7\_ddr\_0** and the _Heap and Stack_ segment memory to **axi\_bram\_ctrl\_0\_Mem0.** 129 | 1. Click the **Generate** button. 130 | 1. Click the **Yes** button to overwrite. 131 | 1. Change the loop limit from 99999999 to **9999999**. Save changes so the program recompiles. 132 | 1. Select the **lab3** project in _Project Explorer_, right-click and select **Run As > Launch on Hardware (System Debugger).** 133 | 134 | Click OK to terminate the exisiting run and relaunch if shown. 135 | 136 | 1. You should see the on-board LEDs changing patterns very slowly (about 5 seconds). 137 | 1. Change the loop limit from 9999999 to **999999**. Save changes so the program recompiles. 138 | 1. Select the **lab3** project in _Project Explorer_, right-click and select **Run As > Launch on Hardware (System Debugger).** 139 | 140 | Click Yes to terminate the existing run. 141 | 142 | 1. You should see the on-board LEDs changing patterns relatively faster (about 1 seconds). 143 | 1. Close the SDK program by selecting **File > Exit**. 144 | 1. Close the Vivado program by selecting **File > Exit.** 145 | 1. Turn OFF the power on the board. 146 | 147 | ## Conclusion 148 | 149 | This lab led you through adding BRAM memory in the PL section thereby extending the total memory space available to the PS. You have verified the functionality by creating an application, targeting the stack and heap sections to the added BRAM, and executing the application. 150 | -------------------------------------------------------------------------------- /lab4.md: -------------------------------------------------------------------------------- 1 | # Direct Memory Access using CDMA 2 | 3 | ## Objectives 4 | 5 | After completing this lab, you will be able to: 6 | 7 | * Enable a High Performance (HP) port of the processing system 8 | * Add and connect the CDMA controller in the programmable logic 9 | * Perform DMA operation between various memories 10 | 11 | ## Steps 12 | ## Open the Project 13 | ### Open the Vivado program. Open the _lab3_ project you created earlier or use the _lab3_ project from the labsolutions directory, and save the project as _lab4_. 14 | 1. Start Vivado if necessary and open either the lab3 project (lab3.xpr) you created earlier or the lab3 project in the labsolution directory using the **Open Project** link in the Getting Started page. 15 | 1. Select **File > Project > Save As …** to open the _Save Project As_ dialog box. Enter **lab4** as the project name. Make sure that the _Create Project Subdirectory_ option is checked, the project directory path is **{labs}** and click **OK**. 16 | 1. This will create the lab4 directory and save the project and associated directory with lab4 name. 17 | ## Configure the Processor to Enable S\_AXI\_HP0 18 | ### Open the Block Design and enable the S\_AXI\_HP0 interface 19 | 1. Click **Open Block Design** in the _Flow Navigator_ pane 20 | 1. Double-click on the _Zynq processing system_ instance to open its configuration form. 21 | 1. Select _PS-PL Configuration_ in the Page Navigator window in the left pane, expand _HP Slave AXI Interface_ on the right, and click on the check-box of the **S AXI HP0 Interface** to enable it, and click **OK** to close the Configuration window. 22 | ## Add CDMA and BRAM 23 | ### Instantiate the AXI central DMA controller. 24 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **Central** in the catalog. 25 | 1. Double-click the **AXI Central Direct Memory Access** to add an instance to the design. 26 | 1. Double-click on the _axi\_cdma\_0_ instance and uncheck the _Enable Scatter Gather_ option. 27 | 1. Change the _Write/Read Data Width_ to **64** and click **OK**. 28 | 29 | Note the burst size changes from 16 to 8. You can increase this up to 256 to improve the performance. Here we are using smallest number since the application allows small number of words transfer. 30 | 31 | ### Run connection automation 32 | 33 | Connection automation could be run on all unconnected ports simultaneously. For the purposes of this lab, each port will be connected separately so that the changes made by the automation process are easier to follow. 34 | 35 | 1. Click on **Run Connection Automation** and select **processing\_system7\_0/S\_AXI\_HP0** 36 | 1. Check that this port will be connected to the _/axi\_cdma\_0/M\_AXI_ port and click **OK**. 37 |

38 | 39 |

40 |

41 | Connection automation 42 |

43 | 1. Verify the CDMA connection through the AXI SmartConnect to the HP0 port 44 |

45 | 46 |

47 |

48 | Connecting AXI Central DMA controller to S_AXI_HP0 49 |

50 | Notice that an instance of AXI SmartConnect (axi_smc_1) is added, S_AXI_HP0 of the processing_system7_0 is connected to M00_AXI of the axi_smc_1, S00_AXI of the axi_smc_1 is connected to the m\_axi of the axi_cdma_0 instance. Also, m_axi_aclk of the axi_cdma_0 is connected to the net originating from FCLK_CLK0 of the processing_system7_0. 51 | 52 | 1. Click on **Run Connection Automation** again, and select **/axi\_cdma\_0** (which includes **S\_AXI\_LITE** ). 53 | 54 | Notice that the axi\_cdma\_0/M\_AXI port is no longer available to select. This is because it was connected to the processing system in the previous step. 55 | 56 | 1. Ensure /processing\_system7\_0/_M\_AXI\_GP0_ is selected in the drop-down button and click **OK**. 57 |

58 | 59 |

60 |

61 | CDMA connected 62 |

63 | ### Instantiate another BRAM Controller and a BRAM. 64 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **BRAM** in the catalog. 65 | 1. Double-click the **AXI BRAM Controller** to add an instance to the design. 66 | 1. Click on **Run Connection Automation** , and select **/axi\_bram\_ctrl\_1/S\_AXI** only. 67 | 1. For the _Master_ connection, _s_elect **axi\_cdma\_0/M\_AXI** from the dropdown box. 68 |

69 | 70 |

71 |

72 | BRAM connection automation 73 |

74 | 1. Click **OK** tomake the connection. 75 | 76 | Notice that another axi interface (M01\_AXI) is added to the axi\_smc\_1 instance and is connected to the S\_AXI interface of the axi\_bram\_ctrl\_1 instance. 77 |

78 | 79 |

80 |

81 | Connection between the new BRAM controller and the CDMA 82 |

83 | 1. Double-click the _axi\_bram\_ctrl\_1_ instance and change the _Number of BRAM Interface_ to **1**. 84 | 1. Change the _Data Width_ to **64** and click **OK**. 85 | 1. Double-click the _axi\_bram\_ctrl\_0_ instance and also change the _Number of BRAM Interface_ to **1**. Click **OK**. 86 | 1. Using the wire tool, connect the **BRAM\_PORTA** of the _axi\_bram\_ctrl\_1_ instance to the **BRAM\_PORTB** of the Block Memory Generator _axi\_bram\_ctrl\_0\_bram_ instance. 87 |

88 | 89 |

90 |

91 | Connect the second BRAM controller 92 |

93 | ### Connect the CDMA interrupt out port to the port of the processor. 94 | 1. Double-click on the _processing\_system7\_0 instance_ to open its configuration form. 95 | 1. Select _Interrupts_ in the Page Navigator window in the left pane, check the _Fabric Interrupts_ box. 96 | 1. Expand _Fabric Interrupts > PL-PS Interrupts Ports_, and click on the check-box of the **IRQ\_F2P**. 97 |

98 | 99 |

100 |

101 | Enabling the processor interrupt 102 |

103 | 1. Click **OK**. 104 | 1. Using wiring tool, connect the **cdma\_introut** to the **IRQ\_F2P** port. (Click on the _cdma\_introut_ port and drag to the _IRQ\_F2P_ port) 105 | ### Using the Address Editor tab, set the BRAM controller size to 64KB. Validate the design. 106 | 1. Select the **Address Editor** tab. 107 | 1. Expand the _axi\_cdma\_0> Data_ section, and change the memory size of _axi\_bram\_ctrl\_1_ to **64K**. 108 |

109 | 110 |

111 |

112 | Address space 113 |

114 | Figure 9. Address space 115 | 1. The design should look similar to the figure below. 116 |

117 | 118 |

119 |

120 | Completed design 121 |

122 | 1. Select the _Diagram_ tab, and click on the ![alt tag](./images/validate.png) (Validate Design) button to make sure that there are no errors. 123 | ## Generate the Bitstream 124 | 1. Click on the **Generate Bitstream** to run the synthesis, implementation, and bit generation processes. 125 | 1. Click **Save** to save the project, and **Yes** if prompted to run the processes. Click **OK** to launch the runs. 126 | 1. When the bitstream generation process has completed successfully, click **Cancel**. 127 | ## Generate an Application in the SDK 128 | ### Export the implemented design, and start SDK 129 | 1. Export the hardware configuration by clicking **File > Export > Export Hardware…** 130 | 1. Click the box to _Include Bitstream_and click **OK** (Click _Yes_ if prompted to overwrite a previous module) 131 | 1. Launch SDK by clicking **File > Launch SDK** and click **OK** 132 | 1. To clean the workspace, right-click on each open project except_system\_wrapper\_hw\_platform\_2_ and select close project. 133 | ### Create an empty application project, named lab4, and import the provided lab4.c file. 134 | 1. Select **File > New** > **Application Project.** 135 | 1. In the _Project Name_ field, enter **lab4** as the project name. 136 | 1. Leave the default settings to create a new _Board Support Package_ and click **Next.** 137 | 1. Select the **Empty Application** template and click **Finish.** 138 | 139 | The lab4 project will be created in the Project Explorer window of SDK. 140 | 141 | 1. Select **lab4 > src** in the project view, right-click, and select **Import.** 142 | 1. Expand the **General** category and double-click on **File System.** 143 | 1. Browse to the **{sources}\lab4** folder. 144 | 1. Select **lab4.c** and click **Finish.** 145 | ## Test in Hardware 146 | ### Connect and power up the board. Download the bitstream and program the FPGA. 147 | 1. Connect and power up the board. 148 | 1. In SDK, select **Xilinx > Program FPGA.** 149 | 1. Click the **Program** button to program the FPGA. 150 | ### Establish serial communication, and run the lab4 application from the DDR3 memory. 151 | 1. Connect the terminal by selecting the appropriate COM port and setting the Baud Rate to **115200**. 152 | 1. Run the **lab4** application **.** 153 | 154 | Follow the menu in the terminal emulator window and test transfers between various memories. 155 | 156 | 1. Select option 4 in the menu to complete the execution. 157 | 1. Close the SDK and Vivado programs by selecting **File > Exit** in each program. 158 | 1. Turn OFF the power on the board. 159 | 160 | ## Conclusion 161 | 162 | This lab led you through adding a CDMA controller to the PS so that you can perform DMA transfers between various memories. You used the high-performance port so DMA could be done between the BRAM residing in the PL section and DDR3 connected to the PS. You verified the design functionality by creating an application and executing it from the DDR3 memory. 163 | -------------------------------------------------------------------------------- /lab6.md: -------------------------------------------------------------------------------- 1 | # Profiling and Performance Tuning 2 | 3 | ## Objectives 4 | 5 | After completing this lab, you will be able to: 6 | 7 | * Setup the board support package (BSP) for profiling an application 8 | * Set the necessary compiler directive on an application to enable profiling 9 | * Setup the profiling parameters 10 | * Profile an application and analyze the output 11 | 12 | ## Steps 13 | ## Create a Vivado Project 14 | ### Launch Vivado and create an empty project, called lab6, targeting the PYNQ-Z1 or PYNQ-Z2 boards and using the Verilog language. 15 | 1. Open Vivado and create a new project new project call _lab6_ in the **{labs}** directory. 16 | 1. Select the **RTL Project** option in the _Project Type_ form, and click **Next**. 17 | 1. Select **Verilog** as the _Target Language_ in the _Add Sources_ form, and click **Next**. 18 | 1. Click **Next** two times. 19 | 1. In the _Default Part_ form, click on _Boards_ filter and Select **www.digilentinc.com** for the _PYNQ-Z1_ board, **tul.com.tw** for the _PYNQ-Z2_ board in the Vendor field, select _PYNQ-Z1__or pynq-z2_, and click **Next**. 20 | 1. Click **Finish** to create an empty Vivado project. 21 | ### Set the project settings to include provided fir\_top IP 22 | 1. Click **Settings** in the _Flow Navigator_ pane. 23 | 1. Expand **IP** in the left pane of the _Project Settings_ form. 24 | 1. Click Repository and using "minus" button remove entries, if any. 25 | 1. Click on the "plus" button, browse to **{sources}\lab6\** and click **Select**. 26 | 1. Click **OK**. 27 | 28 | The directory will be scanned and it will report one IP was detected. 29 | 30 | 1. Click **OK** twice. 31 | ## Creating the Hardware System Using IP Integrator 32 | ### Create a block design in the Vivado project using IP Integrator to generate the Zynq ARM Cortex-A9 processor based hardware system. 33 | 1. In the Flow Navigator, click **Create Block Design** under IP Integrator. 34 | 1. Name the block **system** and click **OK**. 35 | 1. Click on the ![alt tag](./images/add_ip.png) button. 36 | 1. Once the IP Catalog is open, type **zy** into the Search bar, and double click on **ZYNQ7 Processing System** entry to add it to the design. 37 | 1. Click _Run Block Automation_,and click **OK** to accept the default settings. 38 | 1. Double click on the Zynq block to open the _Customization_ window for the Zynq processing system. 39 | 40 | A block diagram of the Zynq should now be open, showing various configurable blocks of the Processing System. 41 | 42 | ### Configure the I/O Peripherals block to only have UART 0 support. 43 | 1. Click on the _MIO Configuration_ panel to open its configuration form. 44 | 1. Expand the _I/O Peripherals_ on the right. 45 | 1. Uncheck _ENET 0_, _USB 0_, and _SD 0_, _GPIO (GPIO MIO)_, leaving _UART 0_ selected. 46 | 1. Click **OK**. 47 | 48 |

49 | 50 |

51 |

52 | ZYNQ Processing System configured block 53 |

54 | 55 | ## Add FIR Core to the System 56 | ### Instantiate the provided FIR core twice naming the instances as fir\_left and fir\_right. Validate the design. 57 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **fir** in the catalog. 58 | 1. Double-click on the **fir\_top\_v1\_0** to add the IP instance to the system 59 | 1. Select the _fir\_top\_1_ instance and change its name to **fir\_left** in its property form. 60 | 1. Click the ![alt tag](./images/add_ip.png) button and search for **fir** in the catalog. 61 | 1. Double-click on the **fir\_top\_v1\_0** to add the IP instance to the system 62 | 1. Select the _fir\_top\_1_ instance and change its name to **fir\_right** in its property form. 63 | 1. Click on **Run Connection Automation** , and select **All Automation** to select _fir\_left_ and _fir\_right_ **.** 64 | 1. Click on _s\_axi\_fir\_io_ for both _fir\_left_ and _fir\_right_ and confirm that they will be automatically connected to the Zynq _M\_AXI\_GP0_ port 65 | 1. Click **OK** toconnect the two blocks to the _M\_AXI\_GP0_ 66 | 67 | The design should look similar to shown below: 68 | 69 |

70 | 71 |

72 |

73 | The completed design 74 |

75 | 76 | It is not necessary to connect the _interrupt_ signals of the _fir_ blocks. 77 | 78 | 1. Select the _Diagram_ tab, and click on the ![alt tag](./images/validate.png) (Validate Design) button to make sure that there are no errors. 79 | 80 | Ignore warnings. 81 | 82 | ## Generate the Bitstream 83 | ### Create the top-level HDL of the embedded system, and generate the bitstream. 84 | 1. In Vivado, select the _Sources_ tab, expand the _Design Sources,_ right-click the _system.bd_ and select **Create HDL Wrapper** and click **OK**. 85 | 1. Click on the **Generate Bitstream** in the _Flow Navigator_ pane to synthesize and implement the design, and generate the bitstream. 86 | 1. Click **Save** to save the design and **Yes** to run the necessary processes. Click **OK** to launch the runs. 87 | 1. When the bitstream generation process has completed click **Cancel.** 88 | ## Export the Design to the SDK 89 | ### Export the design to the SDK, create the software BSP using the standalone operating system and enable the profiling options. 90 | 1. Export the hardware configuration by clicking **File > Export > Export Hardware…** 91 | 1. Tick the box to _Include Bitstream_, and click **OK** 92 | 1. Launch SDK by clicking **File > Launch SDK** and click **OK** 93 | 1. In SDK, select **File** > **New** > **Board Support Package.** 94 | 1. Notice **Standalone\_bsp\_0** in the **Project name** field and click **Finish** with default settings. 95 | 96 | A Board Support Package Settings window will appear. 97 | 98 | 1. Select the **Overview > standalone** entry in the left pane, click on the drop-down arrow of the _enable\_sw\_intrusive\_profiling Value_ field and select **true**. 99 | 100 |

101 | 102 |

103 |

104 | Enable profiling in the board support package 105 |

106 | 107 | 1. Select the **Overview > drivers > cpu\_cortexa9** and add **–pg** in the _extra\_compiler\_flags__Value_ field. 108 | 109 |

110 | 111 |

112 |

113 | Adding profiling switch 114 |

115 | 116 | 1. Click **OK** to accept the settings and create the BSP. 117 | ## Create the Application 118 | ### Create the _lab6_ application using the provided lab6.c, fir.c, fir.h, fir\_coef.dat, and xfir\_fir\_io.h files. 119 | 1. Select **File** > **New** > **Application Project.** 120 | 1. Enter **lab6** as the project name, select the **Use existing** _standalone\_bsp\_0_ option, and click **Next**. 121 | 1. Select **Empty Application** in the _Available Templates_ pane and click **Finish**. 122 | 1. In the _lab6_ project, right click on the _src_ directory and select **Import.** 123 | 1. Expand the General folder and double-click on **File system,** and browse to the **{sources}\lab6** directory. 124 | 1. Select **fir\_coef.dat, fir.c, fir.h, lab6.c,** and **xfir\_fir\_io.h,** and click **Finish.** 125 | 126 | The program should compile successfully and generate the lab6.elf file. 127 | 128 | 1. Open the _lab6.c_ file and scroll to the main function at the bottom. Notice the following code: 129 | 130 |

131 | 132 |

133 |

134 | Source code snippet 135 |

136 | 137 | The function _fir\_software_( ) function is a software implementation of the FIR function. The _filter\_hw\_accel\_input_( ) function offloads the FIR function to the two FIR blocks that have been implemented in the PL. 138 | 139 | ## Run the Application and Profile 140 | ### Place the board into the JTAG boot up mode. Program the PL section and run the application using the user defined SW\_PROFILE symbol. 141 | 1. Place the board in the JTAG boot up mode. 142 | 1. Power ON the board. 143 | 1. Select **Xilinx > Program FPGA** and click on **Program**. 144 | 1. Right click on the _lab6 directory_, and select **C/C++ Build Settings**. 145 | 5. 146 | 1. Under the **ARM v7 gcc compiler** group, select the **Symbols** sub-group **,** click on the ![alt tag](./images/lab6/symbol.png) button to open the value entry form, enter **SW\_PROFILE** , and click **OK**. 147 | 148 | This will allow us to profile the software loop of the FIR application. 149 | 150 |

151 | 152 |

153 |

154 | Add user-defined symbol 155 |

156 | 157 | 1. Under the **ARM v7 gcc compiler** group, select the **Profiling** sub-group, then check the **Enable Profiling** box, and click **OK**. 158 | 159 |

160 | 161 |

162 |

163 | Compiler setting for enabling profiling 164 |

165 | 166 | 1. From the menu bar, Select **Run > Run Configurations…** and double click on _Xilinx C/C++ application (System Debugger)_ to create a new configuration. 167 | 1. Click on the newly created **lab6 Debug** configuration, and select the **Application** tab. 168 | 1. Click on the _Advance Options_ **Edit…** button. 169 | 1. Click on the _Enable Profiling (gprof)_ check box, enter **100000** (100 kHz) in the Sampling Frequency field, enter **0x10000000** in the scratch memory address field, and click **OK**. 170 | 171 |

172 | 173 |

174 |

175 | Profiling options 176 |

177 | 178 | 1. Click **Apply** and then click the **Run** button to download the application and execute it. 179 | 180 | The program will run. 181 | 182 | ### Analyze the results. 183 | 1. When execution is completed, the Gmon File Viewer dialog box will appear showing _lab6.elf_ as the corresponding binary file. Click **OK**. 184 | 1. Click on the **Sort samples per function** button (![alt tag](./images/lab6/FigSort.png)) 185 | ). 186 | 1. Click in the **%Time** column to sort in the descending order. 187 | 188 | Note that the fir\_software routine is called 60 times, 22 samples were taken during the profiling, and on an average of 3.333 (PYNQ-Z1) or 3.666 (PYNQ-Z2/PYNQ-Z2)microseconds were spent per call. 189 | 190 |

191 | 192 |

193 |

194 | Sorting results 195 |

196 | 197 | 1. Go back to the _Run Configuration_, and change the sampling frequency to **1000000** (1 MHz) and profile the application again. 198 | 1. When execution is completed, click **OK** and the gprof viewer will be updated. 199 | 1. Invoke **gprof** , select the **Sorts samples per function** output, and sort the **%Time** column. 200 | 201 | Notice that the output has better resolution and reports more functions and more samples per function calls. Note that the number of calls to the fir\_software function has not changed but the number of samples taken increased, and the average time spent per call is 5.250 (PYNQ-Z1) or 5.016 (PYNQ-Z2) microseconds in the figure below. 202 | 203 |

204 | 205 |

206 |

207 | Profiled results with 1 MHz sampling frequency 208 |

209 | 210 | At this stage, the designer of the system would decide if the FIR function should be ported to hardware. 211 | 212 | ### Profile the application using the hardware FIR filter IP by removing the user defined SW\_PROFILE symbol. 213 | 1. Select the _lab6_ application, right-click, and select **C/C++ Build Settings**. 214 | 1. Under the **ARM v7 gcc compiler** group, select the **Symbols** sub-group **,** select **SW\_PROFILE** , and delete it by clicking on the delete button. 215 | 216 | This will allow us to profile the hardware IP of the FIR application. 217 | 218 | 1. Click **Apply** , and then click **OK** 219 | 1. Select **Run > Run Configurations** and click the **Run** button to profile the application again and click **OK** when profiling completes. 220 | 221 | Notice that the output now shows filter\_hw\_accel\_input function call instead of the fir\_software function call. Note that the average time spent per call is much less as the filtering is done in the hardware instead of the software. 222 | 223 | 1. Close the SDK and Vivado programs by selecting **File > Exit** in each program. 224 | 1. Turn OFF the power on the board. 225 | 226 | ## Conclusion 227 | 228 | This lab led you through enabling the software BSP and the application settings for the profiling. You went through creating the hardware which included the hardware IP and was later profiled in the application. You analyzed the profiled application output. -------------------------------------------------------------------------------- /slides/01_Class_Intro.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/01_Class_Intro.pdf -------------------------------------------------------------------------------- /slides/11_Embedded_System_Design_Review.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/11_Embedded_System_Design_Review.pdf -------------------------------------------------------------------------------- /slides/11a_Lab1_Intro.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/11a_Lab1_Intro.pdf -------------------------------------------------------------------------------- /slides/12_Advanced_Zynq_Architecture.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/12_Advanced_Zynq_Architecture.pdf -------------------------------------------------------------------------------- /slides/13_System_Debugging.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/13_System_Debugging.pdf -------------------------------------------------------------------------------- /slides/13a_Lab2_Intro.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/13a_Lab2_Intro.pdf -------------------------------------------------------------------------------- /slides/14_Memory_Interfacing.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/14_Memory_Interfacing.pdf -------------------------------------------------------------------------------- /slides/14a_Lab3_Intro.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/14a_Lab3_Intro.pdf -------------------------------------------------------------------------------- /slides/15_Interrupts.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/15_Interrupts.pdf -------------------------------------------------------------------------------- /slides/16_Low_Latency_High_Bandwidth.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/16_Low_Latency_High_Bandwidth.pdf -------------------------------------------------------------------------------- /slides/16a_Lab4_Intro.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/16a_Lab4_Intro.pdf -------------------------------------------------------------------------------- /slides/17_Configuration_and_Bootloading.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/17_Configuration_and_Bootloading.pdf -------------------------------------------------------------------------------- /slides/17a_Lab5_Intro.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/17a_Lab5_Intro.pdf -------------------------------------------------------------------------------- /slides/18_Profiling_and_Performance_Improvement.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/18_Profiling_and_Performance_Improvement.pdf -------------------------------------------------------------------------------- /slides/18a_Lab6_Intro.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/slides/18a_Lab6_Intro.pdf -------------------------------------------------------------------------------- /sources/lab1/lab1.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include "xgpio.h" 3 | #ifdef MULTIBOOT 4 | #include "xdevcfg.h" 5 | #endif 6 | 7 | //==================================================== 8 | int main (void) 9 | { 10 | 11 | XGpio sws, leds, btns; 12 | int i, sws_check, btns_check; 13 | 14 | xil_printf("-- Start of the Program --\r\n"); 15 | 16 | // AXI GPIO switches Initialization 17 | XGpio_Initialize(&sws, XPAR_SWITCHES_DEVICE_ID); 18 | XGpio_SetDataDirection(&sws, 1, 0xffffffff); // input 19 | // AXI GPIO leds Initialization 20 | XGpio_Initialize(&leds, XPAR_LEDS_DEVICE_ID); 21 | XGpio_SetDataDirection(&leds, 1, 0); // output 22 | // AXI GPIO buttons Initialization 23 | XGpio_Initialize(&btns, XPAR_BUTTONS_DEVICE_ID); 24 | XGpio_SetDataDirection(&btns, 1, 0xffffffff); // input 25 | 26 | xil_printf("-- Press any of BTN0-BTN3 to see corresponding output on LEDs --\r\n"); 27 | xil_printf("-- Set slide switches to 0x03 to exit the program --\r\n"); 28 | 29 | while (1) 30 | { 31 | btns_check = XGpio_DiscreteRead(&btns, 1); 32 | XGpio_DiscreteWrite(&leds, 1, btns_check); 33 | sws_check = XGpio_DiscreteRead(&sws,1); 34 | if((sws_check & 0x03)==0x03) 35 | break; 36 | for (i=0; i<9999999; i++); // delay loop 37 | } 38 | xil_printf("-- End of Program --\r\n"); 39 | #ifdef MULTIBOOT 40 | // Driver Instantiations 41 | XDcfg XDcfg_0; 42 | u32 MultiBootReg = 0; 43 | #define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200) 44 | #define PS_RST_MASK 0x1 /* PS software reset */ 45 | #define SLCR_UNLOCK_OFFSET 0x08 46 | 47 | // Initialize Device Configuration Interface 48 | XDcfg_Config *Config = XDcfg_LookupConfig(XPAR_XDCFG_0_DEVICE_ID); 49 | XDcfg_CfgInitialize(&XDcfg_0, Config, Config->BaseAddr); 50 | 51 | MultiBootReg = 0; // Once done, boot the master image stored at 0xfc00_0000 52 | Xil_Out32(0xF8000000 + SLCR_UNLOCK_OFFSET, 0xDF0DDF0D); // unlock SLCR 53 | XDcfg_WriteReg(XDcfg_0.Config.BaseAddr, XDCFG_MULTIBOOT_ADDR_OFFSET, MultiBootReg); // write to multiboot reg 54 | // synchronize 55 | __asm__( 56 | "dsb\n\t" 57 | "isb" 58 | ); 59 | Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK); 60 | #endif 61 | return 0; 62 | } 63 | 64 | -------------------------------------------------------------------------------- /sources/lab2/iladata.ila: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab2/iladata.ila -------------------------------------------------------------------------------- /sources/lab2/lab2.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include "xgpio.h" 3 | #include "xil_io.h" 4 | 5 | //==================================================== 6 | int main (void) 7 | { 8 | 9 | XGpio sws, leds, btns; 10 | int i, sws_check, btns_check; 11 | 12 | xil_printf("-- Start of the Program --\r\n"); 13 | 14 | // AXI GPIO switches Initialization 15 | XGpio_Initialize(&sws, XPAR_SWITCHES_DEVICE_ID); 16 | XGpio_SetDataDirection(&sws, 1, 0xffffffff); // input 17 | // AXI GPIO leds Initialization 18 | XGpio_Initialize(&leds, XPAR_LEDS_DEVICE_ID); 19 | XGpio_SetDataDirection(&leds, 1, 0); // output 20 | // AXI GPIO buttons Initialization 21 | XGpio_Initialize(&btns, XPAR_BUTTONS_DEVICE_ID); 22 | XGpio_SetDataDirection(&btns, 1, 0xffffffff); // input 23 | 24 | Xil_Out32(XPAR_MATH_IP_0_BASEADDR, 0x12); 25 | Xil_Out32(XPAR_MATH_IP_0_BASEADDR+4, 0x34); 26 | i=Xil_In32(XPAR_MATH_IP_0_BASEADDR); 27 | xil_printf("result=%x\r\n",i); 28 | 29 | while (1) 30 | { 31 | btns_check = XGpio_DiscreteRead(&btns, 1); 32 | XGpio_DiscreteWrite(&leds, 1, btns_check); 33 | sws_check = XGpio_DiscreteRead(&sws,1); 34 | if((sws_check & 0x03)==0x03) 35 | break; 36 | for (i=0; i<9999999; i++); // delay loop 37 | } 38 | xil_printf("-- End of Program --\r\n"); 39 | 40 | return 0; 41 | } 42 | 43 | -------------------------------------------------------------------------------- /sources/lab2/lab2_pynqz1.xdc: -------------------------------------------------------------------------------- 1 | ######################################################## 2 | # LED constraints # 3 | ######################################################## 4 | 5 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}] 7 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}] 9 | 10 | set_property PACKAGE_PIN M14 [get_ports {leds[3]}] 11 | set_property PACKAGE_PIN N16 [get_ports {leds[2]}] 12 | set_property PACKAGE_PIN P14 [get_ports {leds[1]}] 13 | set_property PACKAGE_PIN R14 [get_ports {leds[0]}] 14 | -------------------------------------------------------------------------------- /sources/lab2/lab2_pynqz2.xdc: -------------------------------------------------------------------------------- 1 | ######################################################## 2 | # LED constraints # 3 | ######################################################## 4 | 5 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}] 7 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}] 9 | 10 | set_property PACKAGE_PIN M14 [get_ports {leds[3]}] 11 | set_property PACKAGE_PIN N16 [get_ports {leds[2]}] 12 | set_property PACKAGE_PIN P14 [get_ports {leds[1]}] 13 | set_property PACKAGE_PIN R14 [get_ports {leds[0]}] 14 | -------------------------------------------------------------------------------- /sources/lab2/lab2_user_logic.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Module Name: lab2_user_logic 3 | -- Description: 8 Bit Adder with vio input capabilities 4 | ---------------------------------------------------------------------------------- 5 | library IEEE; 6 | use IEEE.STD_LOGIC_1164.ALL; 7 | use ieee.std_logic_arith.all; 8 | use ieee.std_logic_unsigned.all; 9 | 10 | -- Uncomment the following library declaration if using 11 | -- arithmetic functions with Signed or Unsigned values 12 | use IEEE.NUMERIC_STD.ALL; 13 | 14 | -- Uncomment the following library declaration if instantiating 15 | -- any Xilinx primitives in this code. 16 | --library UNISIM; 17 | --use UNISIM.VComponents.all; 18 | 19 | entity lab2_user_logic is 20 | Port ( ain : in STD_LOGIC_VECTOR (7 downto 0); 21 | bin : in STD_LOGIC_VECTOR (7 downto 0); 22 | ain_vio : in STD_LOGIC_VECTOR (7 downto 0); 23 | bin_vio : in STD_LOGIC_VECTOR (7 downto 0); 24 | Clk : in STD_LOGIC; 25 | sel : in STD_LOGIC; 26 | Reset_n : in STD_LOGIC; 27 | result : out STD_LOGIC_VECTOR (8 downto 0)); 28 | end lab2_user_logic; 29 | 30 | architecture Behavioral of lab2_user_logic is 31 | 32 | signal ain_i : std_logic_vector (7 downto 0); 33 | signal bin_i : std_logic_vector (7 downto 0); 34 | 35 | begin 36 | 37 | ain_i <= ain_vio WHEN sel='1' ELSE ain; 38 | bin_i <= bin_vio WHEN sel='1' ELSE bin; 39 | 40 | ADD_PROC : process( Clk ) is 41 | begin 42 | 43 | if Clk'event and Clk = '1' then 44 | if Reset_n = '0' then 45 | result <= (others => '0'); 46 | else 47 | result <= ('0' & ain_i) +('0' & bin_i); 48 | end if; 49 | end if; 50 | 51 | end process ADD_PROC; 52 | 53 | end Behavioral; 54 | 55 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.data/constrs_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.data/sources_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.data/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464737263:31:00:00 3 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 4 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657268616e646c6572:31:00:00 5 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657277697a61726468616e646c6572:31:00:00 6 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 7 | eof:1067747294 8 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.data/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 |
11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 |
33 | 34 | 35 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.srcs/sources_1/imports/lab2/lab2_user_logic.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Module Name: lab2_user_logic 3 | -- Description: 8 Bit Adder with vio input capabilities 4 | ---------------------------------------------------------------------------------- 5 | library IEEE; 6 | use IEEE.STD_LOGIC_1164.ALL; 7 | use ieee.std_logic_arith.all; 8 | use ieee.std_logic_unsigned.all; 9 | 10 | -- Uncomment the following library declaration if using 11 | -- arithmetic functions with Signed or Unsigned values 12 | use IEEE.NUMERIC_STD.ALL; 13 | 14 | -- Uncomment the following library declaration if instantiating 15 | -- any Xilinx primitives in this code. 16 | --library UNISIM; 17 | --use UNISIM.VComponents.all; 18 | 19 | entity lab2_user_logic is 20 | Port ( ain : in STD_LOGIC_VECTOR (7 downto 0); 21 | bin : in STD_LOGIC_VECTOR (7 downto 0); 22 | ain_vio : in STD_LOGIC_VECTOR (7 downto 0); 23 | bin_vio : in STD_LOGIC_VECTOR (7 downto 0); 24 | Clk : in STD_LOGIC; 25 | sel : in STD_LOGIC; 26 | Reset_n : in STD_LOGIC; 27 | result : out STD_LOGIC_VECTOR (8 downto 0)); 28 | end lab2_user_logic; 29 | 30 | architecture Behavioral of lab2_user_logic is 31 | 32 | signal ain_i : std_logic_vector (7 downto 0); 33 | signal bin_i : std_logic_vector (7 downto 0); 34 | 35 | begin 36 | 37 | ain_i <= ain_vio WHEN sel='1' ELSE ain; 38 | bin_i <= bin_vio WHEN sel='1' ELSE bin; 39 | 40 | ADD_PROC : process( Clk ) is 41 | begin 42 | 43 | if Clk'event and Clk = '1' then 44 | if Reset_n = '0' then 45 | result <= (others => '0'); 46 | else 47 | result <= ('0' & ain_i) +('0' & bin_i); 48 | end if; 49 | end if; 50 | 51 | end process ADD_PROC; 52 | 53 | end Behavioral; 54 | 55 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/math_ip.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /sources/lab2/math_ip/xgui/math_ip_v1_0.tcl: -------------------------------------------------------------------------------- 1 | #Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ ipgui::add_param $IPINST -parent $Page0 -name Component_Name ] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /sources/lab3/lab3.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include "xgpio.h" 3 | #ifdef MULTIBOOT 4 | #include "xdevcfg.h" 5 | #endif 6 | //==================================================== 7 | int main (void) 8 | { 9 | XGpio leds; 10 | int j=0; 11 | int i; 12 | xil_printf("-- Start of the Program --\r\n"); 13 | XGpio_Initialize(&leds, XPAR_LEDS_DEVICE_ID); 14 | XGpio_SetDataDirection(&leds, 1, 0); // output 15 | for(j=0; j<16; j++) { 16 | XGpio_DiscreteWrite(&leds, 1, j); 17 | for (i=0; i<999999; i++); 18 | } 19 | xil_printf("End of the program\r\n"); 20 | #ifdef MULTIBOOT 21 | print("Loading master image\r\n"); 22 | // Driver Instantiations 23 | XDcfg XDcfg_0; 24 | u32 MultiBootReg = 0; 25 | #define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200) 26 | #define PS_RST_MASK 0x1 /* PS software reset */ 27 | #define SLCR_UNLOCK_OFFSET 0x08 28 | 29 | // Initialize Device Configuration Interface 30 | XDcfg_Config *Config = XDcfg_LookupConfig(XPAR_XDCFG_0_DEVICE_ID); 31 | XDcfg_CfgInitialize(&XDcfg_0, Config, Config->BaseAddr); 32 | 33 | MultiBootReg = 0; // Once done, boot the master image stored at 0xfc00_0000 34 | Xil_Out32(0xF8000000 + SLCR_UNLOCK_OFFSET, 0xDF0DDF0D); // unlock SLCR 35 | XDcfg_WriteReg(XDcfg_0.Config.BaseAddr, XDCFG_MULTIBOOT_ADDR_OFFSET, MultiBootReg); // write to multiboot reg 36 | // synchronize 37 | __asm__( 38 | "dsb\n\t" 39 | "isb" 40 | ); 41 | // Generate soft reset 42 | Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK); 43 | #endif 44 | return 0; 45 | } 46 | 47 | 48 | -------------------------------------------------------------------------------- /sources/lab4/lab4.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include 3 | #include "xuartps.h" // if PS uart is used 4 | #include "xscutimer.h" // if PS Timer is used 5 | #include "xaxicdma.h" // if CDMA is used 6 | #include "xscugic.h" // if PS GIC is used 7 | #include "xil_exception.h" // if interrupt is used 8 | #include "xil_cache.h" 9 | #include "xil_printf.h" 10 | #include "xil_types.h" 11 | 12 | 13 | 14 | #define RESET_LOOP_COUNT 10 // Number of times to check reset is done 15 | #define LENGTH 32768 // source and destination buffers lengths in number of bytes 16 | #define PROCESSOR_BRAM_MEMORY 0x80000000 // BRAM Port A mapped through 1st BRAM Controller accessed by CPU 17 | #define CDMA_BRAM_MEMORY 0xC0000000 // BRAM Port B mapped through 2nd BRAM Controller accessed by CDMA 18 | #define DDR_MEMORY 0x01000000 19 | #define TIMER_DEVICE_ID XPAR_SCUTIMER_DEVICE_ID 20 | #define TIMER_LOAD_VALUE 0xFFFFFFFF 21 | #define INTC_DEVICE_INT_ID XPAR_SCUGIC_SINGLE_DEVICE_ID 22 | 23 | volatile static int Done = 0; /* Dma transfer is done */ 24 | volatile static int Error = 0; /* Dma Bus Error occurs */ 25 | 26 | XUartPs Uart_PS; /* Instance of the UART Device */ 27 | XScuTimer Timer; /* Cortex A9 SCU Private Timer Instance */ 28 | XScuGic Gic; /* PS GIC */ 29 | 30 | int getNumber (){ 31 | 32 | uint8_t byte; 33 | uint8_t uartBuffer[16]; 34 | int validNumber; 35 | int digitIndex; 36 | int digit, number, sign; 37 | int c; 38 | 39 | while(1){ 40 | byte = 0x00; 41 | digit = 0; 42 | digitIndex = 0; 43 | number = 0; 44 | validNumber = TRUE; 45 | 46 | //get bytes from uart until RETURN is entered 47 | while(byte != 0x0d){ 48 | while (!XUartPs_IsReceiveData(STDIN_BASEADDRESS)); 49 | byte = XUartPs_ReadReg(STDIN_BASEADDRESS, 50 | XUARTPS_FIFO_OFFSET); 51 | uartBuffer[digitIndex] = byte; 52 | XUartPs_Send(&Uart_PS, &byte, 1); 53 | digitIndex++; 54 | } 55 | 56 | //calculate number from string of digits 57 | 58 | for(c = 0; c < (digitIndex - 1); c++){ 59 | if(c == 0){ 60 | //check if first byte is a "-" 61 | if(uartBuffer[c] == 0x2D){ 62 | sign = -1; 63 | digit = 0; 64 | } 65 | //check if first byte is a digit 66 | else if((uartBuffer[c] >> 4) == 0x03){ 67 | sign = 1; 68 | digit = (uartBuffer[c] & 0x0F); 69 | } 70 | else 71 | validNumber = FALSE; 72 | } 73 | else{ 74 | //check byte is a digit 75 | if((uartBuffer[c] >> 4) == 0x03){ 76 | digit = (uartBuffer[c] & 0x0F); 77 | } 78 | else 79 | validNumber = FALSE; 80 | } 81 | number = (number * 10) + digit; 82 | } 83 | number *= sign; 84 | if(validNumber == TRUE){ 85 | print("\r\n"); 86 | return number*4; //number of bytes 87 | } 88 | print("This is not a valid number.\n\r"); 89 | } 90 | } 91 | 92 | static void Example_CallBack(void *CallBackRef, u32 IrqMask, int *IgnorePtr) 93 | { 94 | 95 | if (IrqMask & XAXICDMA_XR_IRQ_ERROR_MASK) { 96 | Error = 1; 97 | } 98 | 99 | if (IrqMask & XAXICDMA_XR_IRQ_IOC_MASK) { 100 | Done = 1; 101 | } 102 | 103 | } 104 | 105 | int SetupIntrSystem(XScuGic *GicPtr, XAxiCdma *DmaPtr) 106 | { 107 | int Status; 108 | 109 | Xil_ExceptionInit(); 110 | 111 | // Connect the interrupt controller interrupt handler to the hardware 112 | // interrupt handling logic in the processor. 113 | Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, 114 | (Xil_ExceptionHandler)XScuGic_InterruptHandler, 115 | GicPtr); 116 | 117 | // Connect a device driver handler that will be called when an interrupt 118 | // for the device occurs, the device driver handler performs the specific 119 | // interrupt processing for the device 120 | 121 | Status = XScuGic_Connect(GicPtr, 122 | XPAR_FABRIC_AXI_CDMA_0_CDMA_INTROUT_INTR, 123 | (Xil_InterruptHandler)XAxiCdma_IntrHandler, 124 | (void *)DmaPtr); 125 | if (Status != XST_SUCCESS) 126 | return XST_FAILURE; 127 | 128 | // Enable the interrupt for the device 129 | XScuGic_Enable(GicPtr, XPAR_FABRIC_AXI_CDMA_0_CDMA_INTROUT_INTR); 130 | 131 | return XST_SUCCESS; 132 | } 133 | 134 | uint8_t menu(void) 135 | { 136 | uint8_t byte; 137 | 138 | /* 139 | print("Enter 1 for BRAM to BRAM transfer\r\n"); 140 | print("Enter 2 for BRAM to DDR3 transfer\r\n"); 141 | print("Enter 3 for DDR3 to BRAM transfer\r\n"); 142 | print("Enter 4 for DDR3 to DDR3 transfer\r\n"); 143 | print("Enter 5 to exit\r\n"); 144 | */ 145 | print("Enter 1 for BRAM to DDR3 transfer\r\n"); 146 | print("Enter 2 for DDR3 to BRAM transfer\r\n"); 147 | print("Enter 3 for DDR3 to DDR3 transfer\r\n"); 148 | print("Enter 4 to exit\r\n"); 149 | while (!XUartPs_IsReceiveData(STDIN_BASEADDRESS)); 150 | byte = XUartPs_ReadReg(STDIN_BASEADDRESS, 151 | XUARTPS_FIFO_OFFSET); 152 | XUartPs_Send(&Uart_PS, &byte, 1); 153 | return(byte); 154 | 155 | } 156 | int main (void) { 157 | 158 | uint8_t select; 159 | int i, CDMA_Status; 160 | int numofbytes; 161 | u8 * source, * destination; 162 | u8 * cdma_memory_source, * cdma_memory_destination; 163 | int32_t software_cycles, interrupt_cycles, polled_cycles; 164 | int test_done = 0; 165 | 166 | // UART related definitions 167 | int Status; 168 | XUartPs_Config *Config; 169 | 170 | // PS Timer related definitions 171 | volatile u32 CntValue1; 172 | XScuTimer_Config *ConfigPtr; 173 | XScuTimer *TimerInstancePtr = &Timer; 174 | 175 | // CDMA related definitions 176 | XAxiCdma xcdma; 177 | XAxiCdma_Config * CdmaCfgPtr; 178 | 179 | // PS Interrupt related definitions 180 | XScuGic_Config *GicConfig; 181 | 182 | // Initialize UART 183 | // Look up the configuration in the config table, then initialize it. 184 | Config = XUartPs_LookupConfig(XPAR_PS7_UART_0_DEVICE_ID); 185 | if (NULL == Config) { 186 | return XST_FAILURE; 187 | } 188 | 189 | Status = XUartPs_CfgInitialize(&Uart_PS, Config, Config->BaseAddress); 190 | if (Status != XST_SUCCESS) { 191 | return XST_FAILURE; 192 | } 193 | 194 | // Initialize timer counter 195 | ConfigPtr = XScuTimer_LookupConfig(TIMER_DEVICE_ID); 196 | 197 | Status = XScuTimer_CfgInitialize(TimerInstancePtr, ConfigPtr, 198 | ConfigPtr->BaseAddr); 199 | if (Status != XST_SUCCESS) { 200 | return XST_FAILURE; 201 | } 202 | 203 | // Initialize GIC 204 | GicConfig = XScuGic_LookupConfig(INTC_DEVICE_INT_ID); 205 | if (NULL == GicConfig) { 206 | xil_printf("XScuGic_LookupConfig(%d) failed\r\n", 207 | INTC_DEVICE_INT_ID); 208 | return XST_FAILURE; 209 | } 210 | 211 | Status = XScuGic_CfgInitialize(&Gic, GicConfig, 212 | GicConfig->CpuBaseAddress); 213 | if (Status != XST_SUCCESS) { 214 | xil_printf("XScuGic_CfgInitialize failed\r\n"); 215 | return XST_FAILURE; 216 | } 217 | 218 | // Disable DCache 219 | Xil_DCacheDisable(); 220 | 221 | // Set options for timer/counter 0 222 | // Load the timer counter register. 223 | XScuTimer_LoadTimer(TimerInstancePtr, TIMER_LOAD_VALUE); 224 | 225 | // Start the Scu Private Timer device. 226 | XScuTimer_Start(TimerInstancePtr); 227 | 228 | print("-- Simple DMA Design Example --\r\n"); 229 | 230 | // Get a snapshot of the timer counter value before it's started 231 | CntValue1 = XScuTimer_GetCounterValue(TimerInstancePtr); 232 | 233 | xil_printf("Above message printing took %d clock cycles\r\n", TIMER_LOAD_VALUE-CntValue1); 234 | 235 | // Setup DMA Controller 236 | CdmaCfgPtr = XAxiCdma_LookupConfig(XPAR_AXI_CDMA_0_DEVICE_ID); 237 | if (!CdmaCfgPtr) { 238 | return XST_FAILURE; 239 | } 240 | 241 | Status = XAxiCdma_CfgInitialize(&xcdma , CdmaCfgPtr, CdmaCfgPtr->BaseAddress); 242 | if (Status != XST_SUCCESS) { 243 | return XST_FAILURE; 244 | xil_printf("Status=%x\r\n",Status); 245 | } 246 | 247 | print("Central DMA Initialized\r\n"); 248 | 249 | print("Setting up interrupt system\r\n"); 250 | Status = SetupIntrSystem(&Gic, &xcdma); 251 | if (Status != XST_SUCCESS) { 252 | return XST_FAILURE; 253 | } 254 | 255 | Xil_ExceptionEnable(); 256 | 257 | print("Enter number of words you want to transfer between 1 and 8192\r\n"); 258 | numofbytes =0; 259 | do{ 260 | numofbytes = getNumber(); 261 | }while(numofbytes == 0); 262 | 263 | if(numofbytes > 32768) 264 | numofbytes = 32768; 265 | 266 | select = menu(); 267 | test_done = 0; 268 | while(test_done==0) 269 | { 270 | switch(select) 271 | { 272 | /* 273 | case '1' : 274 | source = PROCESSOR_BRAM_MEMORY; // for processor to access the memory 275 | cdma_memory_source = CDMA_BRAM_MEMORY; // for CDMA to access the memory 276 | destination = PROCESSOR_BRAM_MEMORY+LENGTH; 277 | cdma_memory_destination = CDMA_BRAM_MEMORY+LENGTH; // for CDMA to access the memory 278 | print("BRAM to BRAM transfer\r\n"); 279 | break; 280 | */ 281 | case '1' : 282 | // case '2' : 283 | source = (u8 *)PROCESSOR_BRAM_MEMORY; 284 | cdma_memory_source = (u8 *)CDMA_BRAM_MEMORY; 285 | destination = (u8 *)DDR_MEMORY; 286 | cdma_memory_destination = (u8 *)DDR_MEMORY; 287 | print("BRAM to DDR transfer\r\n"); 288 | break; 289 | case '2' : 290 | // case '3' : 291 | source = (u8 *)DDR_MEMORY; 292 | cdma_memory_source = (u8 *)DDR_MEMORY; 293 | destination = (u8 *)PROCESSOR_BRAM_MEMORY; 294 | cdma_memory_destination = (u8 *)CDMA_BRAM_MEMORY; // for CDMA to access the memory 295 | print("DDR to BRAM transfer\r\n"); 296 | break; 297 | case '3' : 298 | // case '4' : 299 | source = (u8 *)DDR_MEMORY; 300 | cdma_memory_source = (u8 *)DDR_MEMORY; 301 | destination = (u8 *)(DDR_MEMORY+LENGTH); 302 | cdma_memory_destination = (u8 *)(DDR_MEMORY+LENGTH); 303 | print("DDR to DDR transfer\r\n"); 304 | break; 305 | case '4' : 306 | // case '5' : 307 | test_done = 1; 308 | break; 309 | default : 310 | source = (u8 *)DDR_MEMORY; 311 | cdma_memory_source = (u8 *)DDR_MEMORY; 312 | destination = (u8 *)(DDR_MEMORY+LENGTH); 313 | cdma_memory_destination = (u8 *)(DDR_MEMORY+LENGTH); 314 | print("DDR to DDR transfer\r\n"); 315 | break; 316 | } 317 | if(test_done) 318 | break; 319 | 320 | // Initialize src memory 321 | for (i=0; i 9 | #include "devcfg.h" 10 | #include "xil_printf.h" 11 | 12 | 13 | /* 14 | * SLCR registers 15 | */ 16 | #define SLCR_LOCK 0xF8000004 /**< SLCR Write Protection Lock */ 17 | #define SLCR_UNLOCK 0xF8000008 /**< SLCR Write Protection Unlock */ 18 | #define FPGA_RST_CTRL 0xF8000240 /**< FPGA Software Reset Control */ 19 | #define LVL_SHFTR_EN 0xF8000900 /**< FPGA Level Shifters Enable */ 20 | 21 | #define SLCR_LOCK_VAL 0x767B 22 | #define SLCR_UNLOCK_VAL 0xDF0D 23 | 24 | 25 | XDcfg *XDcfg_Initialize(u16 DeviceId) 26 | { 27 | XDcfg *Instance = malloc(sizeof *Instance); 28 | XDcfg_Config *Config = XDcfg_LookupConfig(DeviceId); 29 | XDcfg_CfgInitialize(Instance, Config, Config->BaseAddr); 30 | 31 | return Instance; 32 | } 33 | 34 | int XDcfg_TransferBitfile(XDcfg *Instance, u32 StartAddress, u32 WordLength) 35 | { 36 | int Status; 37 | volatile u32 IntrStsReg = 0; 38 | 39 | // TODO : not working although suggested procedure per TRM 40 | // Disable AXI Interface and Output Level Shifters (Input Level Shifters are still enabled) 41 | // Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); 42 | // Xil_Out32(FPGA_RST_CTRL, 0xFFFFFFFF); 43 | // Xil_Out32(LVL_SHFTR_EN, 0xA); 44 | // Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL); 45 | 46 | // Clear DMA and PCAP Done Interrupts 47 | XDcfg_IntrClear(Instance, (XDCFG_IXR_DMA_DONE_MASK | XDCFG_IXR_D_P_DONE_MASK)); 48 | 49 | // Transfer bitstream from DDR into fabric in non secure mode 50 | Status = XDcfg_Transfer(Instance, (u32 *) StartAddress, WordLength, (u32 *) XDCFG_DMA_INVALID_ADDRESS, 0, XDCFG_NON_SECURE_PCAP_WRITE); 51 | if (Status != XST_SUCCESS) 52 | return Status; 53 | 54 | // Poll DMA Done Interrupt 55 | while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) != XDCFG_IXR_DMA_DONE_MASK) 56 | IntrStsReg = XDcfg_IntrGetStatus(Instance); 57 | 58 | // Poll PCAP Done Interrupt 59 | while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) != XDCFG_IXR_D_P_DONE_MASK) 60 | IntrStsReg = XDcfg_IntrGetStatus(Instance); 61 | 62 | // Enable AXI Interface and Input/Output Level Shifters 63 | // Xil_Out32(SLCR_UNLOCK, SLCR_UNLOCK_VAL); 64 | // Xil_Out32(LVL_SHFTR_EN, 0xF); 65 | // Xil_Out32(FPGA_RST_CTRL, 0x0); 66 | // Xil_Out32(SLCR_LOCK, SLCR_LOCK_VAL); 67 | 68 | return XST_SUCCESS; 69 | } 70 | -------------------------------------------------------------------------------- /sources/lab5/devcfg.h: -------------------------------------------------------------------------------- 1 | /* 2 | * devcfg.h 3 | * 4 | * Created on: Aug 15, 2012 5 | * Author: ckohn 6 | */ 7 | 8 | #ifndef DEVCFG_H_ 9 | #define DEVCFG_H_ 10 | 11 | 12 | #include "xdevcfg.h" 13 | 14 | 15 | XDcfg *XDcfg_Initialize(u16 DeviceId); 16 | int XDcfg_TransferBitfile(XDcfg *Instance, u32 StartAddress, u32 WordLength); 17 | 18 | 19 | #endif /* DEVCFG_H_ */ 20 | -------------------------------------------------------------------------------- /sources/lab5/lab5_qspi.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include 3 | #include 4 | #include 5 | #include "xil_cache.h" 6 | #include "xdevcfg.h" 7 | #include "xil_io.h" 8 | #include "xil_types.h" 9 | 10 | // Read function for STDIN 11 | extern char inbyte(void); 12 | 13 | #define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200) 14 | #define PS_RST_MASK 0x1 /* PS software reset */ 15 | #define SLCR_UNLOCK_OFFSET 0x8 16 | 17 | int main() 18 | { 19 | u32 MultiBootReg = 0; 20 | XDcfg XDcfg_0; 21 | 22 | // Initialize Device Configuration Interface 23 | XDcfg_Config *Config = XDcfg_LookupConfig(XPAR_XDCFG_0_DEVICE_ID); 24 | XDcfg_CfgInitialize(&XDcfg_0, Config, Config->BaseAddr); 25 | 26 | // Display Menu 27 | int Exit = 0; 28 | int OptionCurr; 29 | int OptionNext = 1; // start-up default 30 | while(Exit != 1) { 31 | do { 32 | print(" 1: Lab1\n\r"); 33 | print(" 2: Lab3\n\r"); 34 | print(" 0: Exit\n\r"); 35 | print("> "); 36 | 37 | OptionCurr = OptionNext; 38 | OptionNext = inbyte(); 39 | if (isalpha(OptionNext)) { 40 | OptionNext = toupper(OptionNext); 41 | } 42 | 43 | xil_printf("%c\n\r", OptionNext); 44 | } while (!isdigit(OptionNext)); 45 | 46 | if (OptionCurr == OptionNext) 47 | continue; 48 | 49 | switch (OptionNext) { 50 | case '0': 51 | Exit = 1; 52 | break; 53 | case '1': 54 | print("Loading Lab1 project\r\n"); 55 | MultiBootReg = 0x00400000/0x8000; // 0x00400000 is the base address where lab1.bin is stored 56 | Xil_Out32(0xF8000000 + SLCR_UNLOCK_OFFSET, 0xDF0DDF0D); // unlock SLCR 57 | XDcfg_WriteReg(XDcfg_0.Config.BaseAddr, XDCFG_MULTIBOOT_ADDR_OFFSET, MultiBootReg); // write to multiboot reg 58 | // synchronize 59 | __asm__( 60 | "dsb\n\t" 61 | "isb" 62 | ); 63 | // Generate soft reset 64 | Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK); 65 | break; 66 | case '2': 67 | print("Loading Lab3 project\r\n"); 68 | MultiBootReg = 0x00800000/0x8000; // 0x00800000 is the base address where lab3.bin is stored 69 | Xil_Out32(0xF8000000 + SLCR_UNLOCK_OFFSET, 0xDF0DDF0D); // unlock SLCR 70 | XDcfg_WriteReg(XDcfg_0.Config.BaseAddr, XDCFG_MULTIBOOT_ADDR_OFFSET, MultiBootReg); // write to multiboot reg 71 | // synchronize 72 | __asm__( 73 | "dsb\n\t" 74 | "isb" 75 | ); 76 | // Generate soft reset 77 | Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK); 78 | break; 79 | 80 | break; 81 | default: 82 | break; 83 | } 84 | } 85 | 86 | return 0; 87 | } 88 | 89 | -------------------------------------------------------------------------------- /sources/lab5/lab5_sd.c: -------------------------------------------------------------------------------- 1 | #include "xparameters.h" 2 | #include 3 | #include 4 | #include 5 | #include "xil_cache.h" 6 | #include "ff.h" 7 | #include "devcfg.h" 8 | #include "xil_io.h" 9 | #include "xil_types.h" 10 | 11 | // Parameters for Partial Reconfiguration 12 | #define BITFILE_ADDR 0x1200000 13 | #define LAB1_BITFILE_LEN 0x03dbb00 // BIN formatted BITfile length 14 | #define LAB3_BITFILE_LEN 0x03dbb00 15 | #define LAB1_ELFBIN_ADDR 0x00200000 // BIN formatted ELF address 16 | #define LAB3_ELFBIN_ADDR 0x00600000 17 | #define LAB1_ELFBINFILE_LEN 0x00008008 // BIN formatted ELF length 18 | #define LAB3_ELFBINFILE_LEN 0x00008008 19 | #define LAB1_ELF_EXEC_ADDR 0x002005b8 // ELF main() entry point 20 | #define LAB3_ELF_EXEC_ADDR 0x006005b8 21 | 22 | // Read function for STDIN 23 | extern char inbyte(void); 24 | 25 | static FATFS fatfs; 26 | 27 | // Driver Instantiations 28 | static XDcfg *XDcfg_0; 29 | 30 | // prototype for load_elf 31 | void load_elf(u32 loadaddress); 32 | 33 | int SD_Init() 34 | { 35 | FRESULT rc; 36 | 37 | rc = f_mount(&fatfs, "", 0); 38 | if (rc) { 39 | xil_printf(" ERROR : f_mount returned %d\r\n", rc); 40 | return XST_FAILURE; 41 | } 42 | 43 | return XST_SUCCESS; 44 | } 45 | 46 | int SD_LoadBitFile(char *FileName, u32 DestinationAddress, u32 ByteLength) 47 | { 48 | FIL fil; 49 | FRESULT rc; 50 | UINT br; 51 | 52 | rc = f_open(&fil, FileName, FA_READ); 53 | if (rc) { 54 | xil_printf(" ERROR : f_open returned %d\r\n", rc); 55 | return XST_FAILURE; 56 | } 57 | 58 | rc = f_lseek(&fil, 0); 59 | if (rc) { 60 | xil_printf(" ERROR : f_lseek returned %d\r\n", rc); 61 | return XST_FAILURE; 62 | } 63 | 64 | rc = f_read(&fil, (void*) DestinationAddress, ByteLength, &br); 65 | if (rc) { 66 | xil_printf(" ERROR : f_read returned %d\r\n", rc); 67 | return XST_FAILURE; 68 | } 69 | 70 | rc = f_close(&fil); 71 | if (rc) { 72 | xil_printf(" ERROR : f_close returned %d\r\n", rc); 73 | return XST_FAILURE; 74 | } 75 | 76 | return XST_SUCCESS; 77 | } 78 | 79 | int SD_ElfLoad(char *FileName, u32 DestinationAddress, u32 ByteLength) 80 | { 81 | FIL fil; 82 | FRESULT rc; 83 | UINT br; 84 | 85 | rc = f_open(&fil, FileName, FA_READ); 86 | if (rc) { 87 | xil_printf(" ERROR : f_open returned %d\r\n", rc); 88 | return XST_FAILURE; 89 | } 90 | 91 | rc = f_lseek(&fil, 0); 92 | if (rc) { 93 | xil_printf(" ERROR : f_lseek returned %d\r\n", rc); 94 | return XST_FAILURE; 95 | } 96 | 97 | rc = f_read(&fil, (void*) DestinationAddress, ByteLength, &br); 98 | if (rc) { 99 | xil_printf(" ERROR : f_read returned %d\r\n", rc); 100 | return XST_FAILURE; 101 | } 102 | 103 | rc = f_close(&fil); 104 | if (rc) { 105 | xil_printf(" ERROR : f_close returned %d\r\n", rc); 106 | return XST_FAILURE; 107 | } 108 | 109 | return XST_SUCCESS; 110 | } 111 | 112 | 113 | 114 | int main() 115 | { 116 | int Status; 117 | 118 | 119 | // Initialize SD controller and transfer partials to DDR 120 | SD_Init(); 121 | 122 | // Initialize Device Configuration Interface 123 | XDcfg_0 = XDcfg_Initialize(XPAR_XDCFG_0_DEVICE_ID); 124 | 125 | // Display Menu 126 | int Exit = 0; 127 | int OptionCurr; 128 | int OptionNext = 1; // start-up default 129 | while(Exit != 1) { 130 | do { 131 | print(" 1: Lab1\n\r"); 132 | print(" 2: Lab3\n\r"); 133 | print(" 0: Exit\n\r"); 134 | print("> "); 135 | 136 | OptionCurr = OptionNext; 137 | OptionNext = inbyte(); 138 | if (isalpha(OptionNext)) { 139 | OptionNext = toupper(OptionNext); 140 | } 141 | 142 | xil_printf("%c\n\r", OptionNext); 143 | } while (!isdigit(OptionNext)); 144 | 145 | if (OptionCurr == OptionNext) 146 | continue; 147 | 148 | switch (OptionNext) { 149 | case '0': 150 | Exit = 1; 151 | break; 152 | case '1': 153 | // Flush and disable Data Cache 154 | Xil_DCacheDisable(); 155 | xil_printf("Loading lab1 BIT file\n\r"); 156 | SD_LoadBitFile("lab1.bin", BITFILE_ADDR, (LAB1_BITFILE_LEN << 2)); 157 | // Invalidate and enable Data Cache 158 | Xil_DCacheEnable(); 159 | Xil_Out32(0xF8000008,0x0000DF0D); // Unlock devcfg.SLCR 160 | Xil_Out32(0xF8000900,0xA); // turn-off the level shifter 161 | Xil_Out32(0xF8000004,0x767B); // Lock devcfg.SLCR 162 | Status = XDcfg_TransferBitfile(XDcfg_0, BITFILE_ADDR, LAB1_BITFILE_LEN); 163 | if (Status != XST_SUCCESS) { 164 | xil_printf("Error : FPGA configuration failed!\n\r"); 165 | exit(EXIT_FAILURE); 166 | } 167 | xil_printf("Lab1.bin loaded!, executing its application.\n\r"); 168 | Xil_Out32(0xF8000008,0x0000DF0D); // Unlock devcfg.SLCR 169 | Xil_Out32(0xF8000900, 0xF); // turn-ON the level shifter 170 | Xil_Out32(0xF8000004,0x767B); // Lock devcfg.SLCR 171 | SD_ElfLoad("lab1elf.bin", LAB1_ELFBIN_ADDR, LAB1_ELFBINFILE_LEN); 172 | load_elf(LAB1_ELF_EXEC_ADDR); 173 | break; 174 | case '2': 175 | // Flush and disable Data Cache 176 | Xil_DCacheDisable(); 177 | xil_printf("Loading lab3 BIT file\n\r"); 178 | SD_LoadBitFile("lab3.bin", BITFILE_ADDR, (LAB3_BITFILE_LEN << 2)); 179 | // Invalidate and enable Data Cache 180 | Xil_DCacheEnable(); 181 | Xil_Out32(0xF8000008,0x0000DF0D); // Unlock devcfg.SLCR 182 | Xil_Out32(0xF8000900,0xA); // turn-off the level shifter 183 | Xil_Out32(0xF8000004,0x767B); // Lock devcfg.SLCR 184 | Status = XDcfg_TransferBitfile(XDcfg_0, BITFILE_ADDR, LAB3_BITFILE_LEN); 185 | if (Status != XST_SUCCESS) { 186 | xil_printf("Error : FPGA configuration failed!\n\r"); 187 | exit(EXIT_FAILURE); 188 | } 189 | xil_printf("Lab3.bin loaded!, executing its application.\n\r"); 190 | Xil_Out32(0xF8000008,0x0000DF0D); // Unlock devcfg.SLCR 191 | Xil_Out32(0xF8000900, 0xF); // turn-ON the level shifter 192 | Xil_Out32(0xF8000004,0x767B); // Lock devcfg.SLCR 193 | SD_ElfLoad("lab3elf.bin", LAB3_ELFBIN_ADDR, LAB3_ELFBINFILE_LEN); 194 | load_elf(LAB3_ELF_EXEC_ADDR); 195 | break; 196 | default: 197 | break; 198 | } 199 | } 200 | 201 | return 0; 202 | } 203 | 204 | -------------------------------------------------------------------------------- /sources/lab5/load_elf.s: -------------------------------------------------------------------------------- 1 | .global load_elf 2 | .type load_elf, %function 3 | load_elf: 4 | mov pc, r0 5 | 6 | 7 | -------------------------------------------------------------------------------- /sources/lab5/pynqz1/QSPI/lab1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz1/QSPI/lab1.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz1/QSPI/lab3.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz1/QSPI/lab3.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz1/QSPI/lab5.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz1/QSPI/lab5.zip -------------------------------------------------------------------------------- /sources/lab5/pynqz1/SDCard/lab1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz1/SDCard/lab1.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz1/SDCard/lab1elf.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz1/SDCard/lab1elf.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz1/SDCard/lab3.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz1/SDCard/lab3.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz1/SDCard/lab3elf.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz1/SDCard/lab3elf.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz2/QSPI/lab1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz2/QSPI/lab1.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz2/QSPI/lab3.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz2/QSPI/lab3.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz2/QSPI/lab5.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz2/QSPI/lab5.zip -------------------------------------------------------------------------------- /sources/lab5/pynqz2/SDCard/lab1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz2/SDCard/lab1.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz2/SDCard/lab1elf.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz2/SDCard/lab1elf.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz2/SDCard/lab3.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz2/SDCard/lab3.bin -------------------------------------------------------------------------------- /sources/lab5/pynqz2/SDCard/lab3elf.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab5/pynqz2/SDCard/lab3elf.bin -------------------------------------------------------------------------------- /sources/lab6/fir.c: -------------------------------------------------------------------------------- 1 | #include "fir.h" 2 | 3 | void fir_software ( 4 | data_t *y, 5 | data_t x 6 | ) { 7 | const coef_t c[N+1]={ 8 | #include "fir_coef.dat" 9 | }; 10 | 11 | 12 | static data_t shift_reg[N]; 13 | acc_t acc; 14 | int i; 15 | 16 | acc=(acc_t)shift_reg[N-1]*(acc_t)c[N]; 17 | loop: for (i=N-1;i>=0;i--) { 18 | acc+=(acc_t)shift_reg[i-1]*(acc_t)c[i]; 19 | shift_reg[i]=shift_reg[i-1]; 20 | } 21 | acc+=(acc_t)x*(acc_t)c[0]; 22 | shift_reg[0]=x; 23 | *y = acc>>15; 24 | } 25 | -------------------------------------------------------------------------------- /sources/lab6/fir.h: -------------------------------------------------------------------------------- 1 | #define N 50 2 | #define SAMPLES N+10 // just few more samples then number of taps 3 | typedef short coef_t; 4 | typedef short data_t; 5 | typedef long acc_t; 6 | -------------------------------------------------------------------------------- /sources/lab6/fir_coef.dat: -------------------------------------------------------------------------------- 1 | -448, 2 | -310, 3 | -373, 4 | -406, 5 | -396, 6 | -333, 7 | -209, 8 | -27, 9 | 207, 10 | 476, 11 | 758, 12 | 1025, 13 | 1248, 14 | 1397, 15 | 1447, 16 | 1382, 17 | 1195, 18 | 892, 19 | 490, 20 | 16, 21 | -490, 22 | -986, 23 | -1428, 24 | -1777, 25 | -2001, 26 | 30691, 27 | -2001, 28 | -1777, 29 | -1428, 30 | -986, 31 | -490, 32 | 16, 33 | 490, 34 | 892, 35 | 1195, 36 | 1382, 37 | 1447, 38 | 1397, 39 | 1248, 40 | 1025, 41 | 758, 42 | 476, 43 | 207, 44 | -27, 45 | -209, 46 | -333, 47 | -396, 48 | -406, 49 | -373, 50 | -310, 51 | -448 52 | 53 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.data/constrs_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.data/sources_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 110 | 111 | 112 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.data/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00 3 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657268616e646c6572:33:00:00 4 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657277697a61726468616e646c6572:31:00:00 5 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 6 | eof:1615681915 7 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:2 3 | eof: 4 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.data/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 |
11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
32 | 33 | 34 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.filter: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xupgit/Advanced-Embedded-System-Design-Flow-on-Zynq/52c766722897b0635d7df68a9a36e1ba011bd7a9/sources/lab6/fir_ip/fir_ip.filter -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2012.4 4 | // Copyright (C) 2012 Xilinx Inc. All rights reserved. 5 | // 6 | // =========================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | 10 | (* CORE_GENERATION_INFO="fir,hls_ip_2012_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.660000,HLS_SYN_LAT=55,HLS_SYN_TPT=none,HLS_SYN_MEM=2,HLS_SYN_DSP=1,HLS_SYN_FF=125,HLS_SYN_LUT=166}" *) 11 | 12 | module fir ( 13 | ap_clk, 14 | ap_rst, 15 | ap_start, 16 | ap_done, 17 | ap_idle, 18 | ap_ready, 19 | y, 20 | y_ap_vld, 21 | x 22 | ); 23 | 24 | input ap_clk; 25 | input ap_rst; 26 | input ap_start; 27 | output ap_done; 28 | output ap_idle; 29 | output ap_ready; 30 | output [15:0] y; 31 | output y_ap_vld; 32 | input [15:0] x; 33 | 34 | reg ap_done; 35 | reg ap_idle; 36 | reg ap_ready; 37 | reg y_ap_vld; 38 | reg [1:0] ap_CS_fsm = 2'b00; 39 | reg [5:0] shift_reg_address0; 40 | reg shift_reg_ce0; 41 | reg shift_reg_we0; 42 | wire [15:0] shift_reg_d0; 43 | wire [15:0] shift_reg_q0; 44 | wire [5:0] shift_reg_address1; 45 | reg shift_reg_ce1; 46 | reg shift_reg_we1; 47 | wire [15:0] shift_reg_d1; 48 | wire [5:0] c_address0; 49 | reg c_ce0; 50 | wire [15:0] c_q0; 51 | reg [5:0] indvar_reg_113; 52 | reg [36:0] acc_1_reg_124; 53 | wire [36:0] acc_cast_fu_168_p1; 54 | wire [0:0] exitcond2_fu_172_p2; 55 | reg [0:0] exitcond2_reg_300; 56 | reg ap_reg_ppiten_pp0_it0 = 1'b0; 57 | reg ap_reg_ppiten_pp0_it1 = 1'b0; 58 | reg ap_reg_ppiten_pp0_it2 = 1'b0; 59 | reg [0:0] ap_reg_ppstg_exitcond2_reg_300_pp0_it1; 60 | wire [5:0] indvar_next_fu_178_p2; 61 | wire [31:0] i_cast_fu_205_p1; 62 | reg [31:0] i_cast_reg_309; 63 | reg [15:0] shift_reg_load_1_reg_324; 64 | reg [15:0] c_load_reg_329; 65 | wire [37:0] acc_1_cast8_fu_210_p1; 66 | reg [37:0] acc_1_cast8_reg_334; 67 | wire [36:0] acc_3_fu_230_p2; 68 | wire [31:0] tmp1_cast_fu_194_p1; 69 | wire [24:0] tmp_cast4_fu_138_p1; 70 | wire [24:0] p_shl_fu_142_p2; 71 | wire [21:0] tmp_cast_fu_134_p1; 72 | wire [21:0] p_shl1_fu_152_p2; 73 | wire [25:0] acc_fu_162_p0; 74 | wire [25:0] acc_fu_162_p1; 75 | wire [25:0] acc_fu_162_p2; 76 | wire [6:0] indvar_cast_fu_184_p1; 77 | wire [6:0] tmp1_fu_188_p2; 78 | wire [5:0] i_fu_199_p2; 79 | wire [15:0] tmp_s_fu_220_p0; 80 | wire [15:0] tmp_s_fu_220_p1; 81 | wire [31:0] tmp_s_fu_220_p2; 82 | wire [36:0] acc_3_fu_230_p0; 83 | wire [24:0] tmp_2_cast6_fu_239_p1; 84 | wire [24:0] p_shl2_fu_242_p2; 85 | wire [21:0] tmp_2_cast_fu_236_p1; 86 | wire [21:0] p_shl4_fu_252_p2; 87 | wire [25:0] tmp_3_fu_262_p0; 88 | wire [25:0] tmp_3_fu_262_p1; 89 | wire [25:0] tmp_3_fu_262_p2; 90 | wire [37:0] acc_2_fu_272_p1; 91 | wire [37:0] acc_2_fu_272_p2; 92 | reg [1:0] ap_NS_fsm; 93 | parameter ap_const_logic_1 = 1'b1; 94 | parameter ap_const_logic_0 = 1'b0; 95 | parameter ap_ST_st1_fsm_0 = 2'b00; 96 | parameter ap_ST_st2_fsm_1 = 2'b01; 97 | parameter ap_ST_pp0_stg0_fsm_2 = 2'b10; 98 | parameter ap_ST_st6_fsm_3 = 2'b11; 99 | parameter ap_const_lv1_0 = 1'b0; 100 | parameter ap_const_lv6_0 = 6'b000000; 101 | parameter ap_const_lv6_31 = 6'b110001; 102 | parameter ap_const_lv25_9 = 25'b0000000000000000000001001; 103 | parameter ap_const_lv22_6 = 22'b0000000000000000000110; 104 | parameter ap_const_lv6_32 = 6'b110010; 105 | parameter ap_const_lv6_1 = 6'b000001; 106 | parameter ap_const_lv7_30 = 7'b0110000; 107 | parameter ap_const_lv32_F = 32'b00000000000000000000000000001111; 108 | parameter ap_const_lv32_1E = 32'b00000000000000000000000000011110; 109 | parameter ap_true = 1'b1; 110 | 111 | 112 | fir_shift_reg #( 113 | .DataWidth( 16 ), 114 | .AddressRange( 50 ), 115 | .AddressWidth( 6 )) 116 | shift_reg_U( 117 | .clk( ap_clk ), 118 | .reset( ap_rst ), 119 | .address0( shift_reg_address0 ), 120 | .ce0( shift_reg_ce0 ), 121 | .we0( shift_reg_we0 ), 122 | .d0( shift_reg_d0 ), 123 | .q0( shift_reg_q0 ), 124 | .address1( shift_reg_address1 ), 125 | .ce1( shift_reg_ce1 ), 126 | .we1( shift_reg_we1 ), 127 | .d1( shift_reg_d1 ) 128 | ); 129 | 130 | fir_c #( 131 | .DataWidth( 16 ), 132 | .AddressRange( 51 ), 133 | .AddressWidth( 6 )) 134 | c_U( 135 | .clk( ap_clk ), 136 | .reset( ap_rst ), 137 | .address0( c_address0 ), 138 | .ce0( c_ce0 ), 139 | .q0( c_q0 ) 140 | ); 141 | 142 | 143 | 144 | /// the current state (ap_CS_fsm) of the state machine. /// 145 | always @ (posedge ap_clk) 146 | begin : ap_ret_ap_CS_fsm 147 | if (ap_rst == 1'b1) begin 148 | ap_CS_fsm <= ap_ST_st1_fsm_0; 149 | end else begin 150 | ap_CS_fsm <= ap_NS_fsm; 151 | end 152 | end 153 | 154 | /// ap_reg_ppiten_pp0_it0 assign process. /// 155 | always @ (posedge ap_clk) 156 | begin : ap_ret_ap_reg_ppiten_pp0_it0 157 | if (ap_rst == 1'b1) begin 158 | ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; 159 | end else begin 160 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(exitcond2_fu_172_p2 == ap_const_lv1_0))) begin 161 | ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; 162 | end else if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin 163 | ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; 164 | end 165 | end 166 | end 167 | 168 | /// ap_reg_ppiten_pp0_it1 assign process. /// 169 | always @ (posedge ap_clk) 170 | begin : ap_ret_ap_reg_ppiten_pp0_it1 171 | if (ap_rst == 1'b1) begin 172 | ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; 173 | end else begin 174 | if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin 175 | ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; 176 | end else if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin 177 | ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; 178 | end 179 | end 180 | end 181 | 182 | /// ap_reg_ppiten_pp0_it2 assign process. /// 183 | always @ (posedge ap_clk) 184 | begin : ap_ret_ap_reg_ppiten_pp0_it2 185 | if (ap_rst == 1'b1) begin 186 | ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; 187 | end else begin 188 | if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin 189 | ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; 190 | end else if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin 191 | ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; 192 | end 193 | end 194 | end 195 | 196 | /// assign process. /// 197 | always @(posedge ap_clk) 198 | begin 199 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2))) begin 200 | acc_1_cast8_reg_334[0] <= acc_1_cast8_fu_210_p1[0]; 201 | acc_1_cast8_reg_334[1] <= acc_1_cast8_fu_210_p1[1]; 202 | acc_1_cast8_reg_334[2] <= acc_1_cast8_fu_210_p1[2]; 203 | acc_1_cast8_reg_334[3] <= acc_1_cast8_fu_210_p1[3]; 204 | acc_1_cast8_reg_334[4] <= acc_1_cast8_fu_210_p1[4]; 205 | acc_1_cast8_reg_334[5] <= acc_1_cast8_fu_210_p1[5]; 206 | acc_1_cast8_reg_334[6] <= acc_1_cast8_fu_210_p1[6]; 207 | acc_1_cast8_reg_334[7] <= acc_1_cast8_fu_210_p1[7]; 208 | acc_1_cast8_reg_334[8] <= acc_1_cast8_fu_210_p1[8]; 209 | acc_1_cast8_reg_334[9] <= acc_1_cast8_fu_210_p1[9]; 210 | acc_1_cast8_reg_334[10] <= acc_1_cast8_fu_210_p1[10]; 211 | acc_1_cast8_reg_334[11] <= acc_1_cast8_fu_210_p1[11]; 212 | acc_1_cast8_reg_334[12] <= acc_1_cast8_fu_210_p1[12]; 213 | acc_1_cast8_reg_334[13] <= acc_1_cast8_fu_210_p1[13]; 214 | acc_1_cast8_reg_334[14] <= acc_1_cast8_fu_210_p1[14]; 215 | acc_1_cast8_reg_334[15] <= acc_1_cast8_fu_210_p1[15]; 216 | acc_1_cast8_reg_334[16] <= acc_1_cast8_fu_210_p1[16]; 217 | acc_1_cast8_reg_334[17] <= acc_1_cast8_fu_210_p1[17]; 218 | acc_1_cast8_reg_334[18] <= acc_1_cast8_fu_210_p1[18]; 219 | acc_1_cast8_reg_334[19] <= acc_1_cast8_fu_210_p1[19]; 220 | acc_1_cast8_reg_334[20] <= acc_1_cast8_fu_210_p1[20]; 221 | acc_1_cast8_reg_334[21] <= acc_1_cast8_fu_210_p1[21]; 222 | acc_1_cast8_reg_334[22] <= acc_1_cast8_fu_210_p1[22]; 223 | acc_1_cast8_reg_334[23] <= acc_1_cast8_fu_210_p1[23]; 224 | acc_1_cast8_reg_334[24] <= acc_1_cast8_fu_210_p1[24]; 225 | acc_1_cast8_reg_334[25] <= acc_1_cast8_fu_210_p1[25]; 226 | acc_1_cast8_reg_334[26] <= acc_1_cast8_fu_210_p1[26]; 227 | acc_1_cast8_reg_334[27] <= acc_1_cast8_fu_210_p1[27]; 228 | acc_1_cast8_reg_334[28] <= acc_1_cast8_fu_210_p1[28]; 229 | acc_1_cast8_reg_334[29] <= acc_1_cast8_fu_210_p1[29]; 230 | acc_1_cast8_reg_334[30] <= acc_1_cast8_fu_210_p1[30]; 231 | acc_1_cast8_reg_334[31] <= acc_1_cast8_fu_210_p1[31]; 232 | acc_1_cast8_reg_334[32] <= acc_1_cast8_fu_210_p1[32]; 233 | acc_1_cast8_reg_334[33] <= acc_1_cast8_fu_210_p1[33]; 234 | acc_1_cast8_reg_334[34] <= acc_1_cast8_fu_210_p1[34]; 235 | acc_1_cast8_reg_334[35] <= acc_1_cast8_fu_210_p1[35]; 236 | acc_1_cast8_reg_334[36] <= acc_1_cast8_fu_210_p1[36]; 237 | end 238 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (ap_reg_ppstg_exitcond2_reg_300_pp0_it1 == ap_const_lv1_0))) begin 239 | acc_1_reg_124 <= acc_3_fu_230_p2; 240 | end else if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin 241 | acc_1_reg_124 <= acc_cast_fu_168_p1; 242 | end 243 | if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin 244 | ap_reg_ppstg_exitcond2_reg_300_pp0_it1 <= exitcond2_reg_300; 245 | end 246 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_300 == ap_const_lv1_0))) begin 247 | c_load_reg_329 <= c_q0; 248 | end 249 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin 250 | exitcond2_reg_300 <= exitcond2_fu_172_p2; 251 | end 252 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond2_fu_172_p2 == ap_const_lv1_0))) begin 253 | i_cast_reg_309[0] <= i_cast_fu_205_p1[0]; 254 | i_cast_reg_309[1] <= i_cast_fu_205_p1[1]; 255 | i_cast_reg_309[2] <= i_cast_fu_205_p1[2]; 256 | i_cast_reg_309[3] <= i_cast_fu_205_p1[3]; 257 | i_cast_reg_309[4] <= i_cast_fu_205_p1[4]; 258 | i_cast_reg_309[5] <= i_cast_fu_205_p1[5]; 259 | end 260 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond2_fu_172_p2 == ap_const_lv1_0))) begin 261 | indvar_reg_113 <= indvar_next_fu_178_p2; 262 | end else if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin 263 | indvar_reg_113 <= ap_const_lv6_0; 264 | end 265 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_300 == ap_const_lv1_0))) begin 266 | shift_reg_load_1_reg_324 <= shift_reg_q0; 267 | end 268 | end 269 | 270 | /// the next state (ap_NS_fsm) of the state machine. /// 271 | always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2) 272 | begin 273 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin 274 | ap_NS_fsm = ap_ST_st6_fsm_3; 275 | end else if ((ap_ST_st6_fsm_3 == ap_CS_fsm)) begin 276 | ap_NS_fsm = ap_ST_st1_fsm_0; 277 | end else if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin 278 | ap_NS_fsm = ap_ST_pp0_stg0_fsm_2; 279 | end else if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin 280 | ap_NS_fsm = ap_ST_st2_fsm_1; 281 | end else begin 282 | ap_NS_fsm = ap_CS_fsm; 283 | end 284 | end 285 | 286 | /// ap_done assign process. /// 287 | always @ (ap_CS_fsm) 288 | begin 289 | if ((ap_ST_st6_fsm_3 == ap_CS_fsm)) begin 290 | ap_done = ap_const_logic_1; 291 | end else begin 292 | ap_done = ap_const_logic_0; 293 | end 294 | end 295 | 296 | /// ap_idle assign process. /// 297 | always @ (ap_start or ap_CS_fsm) 298 | begin 299 | if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin 300 | ap_idle = ap_const_logic_1; 301 | end else begin 302 | ap_idle = ap_const_logic_0; 303 | end 304 | end 305 | 306 | /// ap_ready assign process. /// 307 | always @ (ap_CS_fsm) 308 | begin 309 | if ((ap_ST_st6_fsm_3 == ap_CS_fsm)) begin 310 | ap_ready = ap_const_logic_1; 311 | end else begin 312 | ap_ready = ap_const_logic_0; 313 | end 314 | end 315 | 316 | /// c_ce0 assign process. /// 317 | always @ (ap_CS_fsm or exitcond2_fu_172_p2 or ap_reg_ppiten_pp0_it0) 318 | begin 319 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond2_fu_172_p2 == ap_const_lv1_0))) begin 320 | c_ce0 = ap_const_logic_1; 321 | end else begin 322 | c_ce0 = ap_const_logic_0; 323 | end 324 | end 325 | 326 | /// shift_reg_address0 assign process. /// 327 | always @ (ap_start or ap_CS_fsm or exitcond2_fu_172_p2 or ap_reg_ppiten_pp0_it0 or tmp1_cast_fu_194_p1) 328 | begin 329 | if ((ap_ST_st6_fsm_3 == ap_CS_fsm)) begin 330 | shift_reg_address0 = ap_const_lv6_0; 331 | end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond2_fu_172_p2 == ap_const_lv1_0))) begin 332 | shift_reg_address0 = tmp1_cast_fu_194_p1; 333 | end else if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin 334 | shift_reg_address0 = ap_const_lv6_31; 335 | end else begin 336 | shift_reg_address0 = ap_const_lv6_31; 337 | end 338 | end 339 | 340 | /// shift_reg_ce0 assign process. /// 341 | always @ (ap_start or ap_CS_fsm or exitcond2_fu_172_p2 or ap_reg_ppiten_pp0_it0) 342 | begin 343 | if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond2_fu_172_p2 == ap_const_lv1_0)) | (ap_ST_st6_fsm_3 == ap_CS_fsm) | ((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0)))) begin 344 | shift_reg_ce0 = ap_const_logic_1; 345 | end else begin 346 | shift_reg_ce0 = ap_const_logic_0; 347 | end 348 | end 349 | 350 | /// shift_reg_ce1 assign process. /// 351 | always @ (ap_CS_fsm or exitcond2_reg_300 or ap_reg_ppiten_pp0_it1) 352 | begin 353 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_300 == ap_const_lv1_0))) begin 354 | shift_reg_ce1 = ap_const_logic_1; 355 | end else begin 356 | shift_reg_ce1 = ap_const_logic_0; 357 | end 358 | end 359 | 360 | /// shift_reg_we0 assign process. /// 361 | always @ (ap_CS_fsm) 362 | begin 363 | if ((ap_ST_st6_fsm_3 == ap_CS_fsm)) begin 364 | shift_reg_we0 = ap_const_logic_1; 365 | end else begin 366 | shift_reg_we0 = ap_const_logic_0; 367 | end 368 | end 369 | 370 | /// shift_reg_we1 assign process. /// 371 | always @ (ap_CS_fsm or exitcond2_reg_300 or ap_reg_ppiten_pp0_it1) 372 | begin 373 | if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond2_reg_300 == ap_const_lv1_0))) begin 374 | shift_reg_we1 = ap_const_logic_1; 375 | end else begin 376 | shift_reg_we1 = ap_const_logic_0; 377 | end 378 | end 379 | 380 | /// y_ap_vld assign process. /// 381 | always @ (ap_CS_fsm) 382 | begin 383 | if ((ap_ST_st6_fsm_3 == ap_CS_fsm)) begin 384 | y_ap_vld = ap_const_logic_1; 385 | end else begin 386 | y_ap_vld = ap_const_logic_0; 387 | end 388 | end 389 | assign acc_1_cast8_fu_210_p1 = $unsigned(acc_1_reg_124); 390 | assign acc_2_fu_272_p1 = $signed(tmp_3_fu_262_p2); 391 | assign acc_2_fu_272_p2 = (acc_1_cast8_reg_334 + acc_2_fu_272_p1); 392 | assign acc_3_fu_230_p0 = $signed(tmp_s_fu_220_p2); 393 | assign acc_3_fu_230_p2 = (acc_3_fu_230_p0 + acc_1_reg_124); 394 | assign acc_cast_fu_168_p1 = $signed(acc_fu_162_p2); 395 | assign acc_fu_162_p0 = $signed(p_shl1_fu_152_p2); 396 | assign acc_fu_162_p1 = $signed(p_shl_fu_142_p2); 397 | assign acc_fu_162_p2 = (acc_fu_162_p0 - acc_fu_162_p1); 398 | assign c_address0 = i_cast_fu_205_p1; 399 | assign exitcond2_fu_172_p2 = (indvar_reg_113 == ap_const_lv6_32? 1'b1: 1'b0); 400 | assign i_cast_fu_205_p1 = $unsigned(i_fu_199_p2); 401 | assign i_fu_199_p2 = (ap_const_lv6_31 - indvar_reg_113); 402 | assign indvar_cast_fu_184_p1 = $unsigned(indvar_reg_113); 403 | assign indvar_next_fu_178_p2 = (indvar_reg_113 + ap_const_lv6_1); 404 | assign p_shl1_fu_152_p2 = tmp_cast_fu_134_p1 << ap_const_lv22_6; 405 | assign p_shl2_fu_242_p2 = tmp_2_cast6_fu_239_p1 << ap_const_lv25_9; 406 | assign p_shl4_fu_252_p2 = tmp_2_cast_fu_236_p1 << ap_const_lv22_6; 407 | assign p_shl_fu_142_p2 = tmp_cast4_fu_138_p1 << ap_const_lv25_9; 408 | assign shift_reg_address1 = i_cast_reg_309; 409 | assign shift_reg_d0 = x; 410 | assign shift_reg_d1 = shift_reg_q0; 411 | assign tmp1_cast_fu_194_p1 = $signed(tmp1_fu_188_p2); 412 | assign tmp1_fu_188_p2 = (ap_const_lv7_30 - indvar_cast_fu_184_p1); 413 | assign tmp_2_cast6_fu_239_p1 = $unsigned(x); 414 | assign tmp_2_cast_fu_236_p1 = $unsigned(x); 415 | assign tmp_3_fu_262_p0 = $signed(p_shl4_fu_252_p2); 416 | assign tmp_3_fu_262_p1 = $signed(p_shl2_fu_242_p2); 417 | assign tmp_3_fu_262_p2 = (tmp_3_fu_262_p0 - tmp_3_fu_262_p1); 418 | assign tmp_cast4_fu_138_p1 = $unsigned(shift_reg_q0); 419 | assign tmp_cast_fu_134_p1 = $unsigned(shift_reg_q0); 420 | assign tmp_s_fu_220_p0 = c_load_reg_329; 421 | assign tmp_s_fu_220_p1 = shift_reg_load_1_reg_324; 422 | assign tmp_s_fu_220_p2 = ($signed(tmp_s_fu_220_p0) * $signed(tmp_s_fu_220_p1)); 423 | assign y = {{acc_2_fu_272_p2[ap_const_lv32_1E : ap_const_lv32_F]}}; 424 | always @ (posedge ap_clk) 425 | begin 426 | i_cast_reg_309[31:6] <= 26'b00000000000000000000000000; 427 | acc_1_cast8_reg_334[37] <= 1'b0; 428 | end 429 | 430 | 431 | 432 | endmodule //fir 433 | 434 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir_ap_rst_if.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2012.4 4 | // Copyright (C) 2012 Xilinx Inc. All rights reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1ns/1ps 9 | 10 | module fir_ap_rst_if 11 | #(parameter 12 | RESET_ACTIVE_LOW = 0 13 | )( 14 | input wire din, 15 | output wire dout 16 | ); 17 | 18 | assign dout = (RESET_ACTIVE_LOW == 1)? ~din : din; 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir_c.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2012.4 4 | // Copyright (C) 2012 Xilinx Inc. All rights reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | module fir_c_rom ( 10 | addr0, ce0, q0, clk); 11 | 12 | parameter DWIDTH = 16; 13 | parameter AWIDTH = 6; 14 | parameter MEM_SIZE = 51; 15 | 16 | input[AWIDTH-1:0] addr0; 17 | input ce0; 18 | output reg[DWIDTH-1:0] q0; 19 | input clk; 20 | 21 | reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; 22 | 23 | initial begin 24 | $readmemh("./fir_c_rom.dat", ram); 25 | end 26 | 27 | 28 | 29 | always @(posedge clk) 30 | begin 31 | if (ce0) 32 | begin 33 | q0 <= ram[addr0]; 34 | end 35 | end 36 | 37 | 38 | 39 | endmodule 40 | 41 | 42 | `timescale 1 ns / 1 ps 43 | module fir_c( 44 | reset, 45 | clk, 46 | address0, 47 | ce0, 48 | q0); 49 | 50 | parameter DataWidth = 32'd16; 51 | parameter AddressRange = 32'd51; 52 | parameter AddressWidth = 32'd6; 53 | input reset; 54 | input clk; 55 | input[AddressWidth - 1:0] address0; 56 | input ce0; 57 | output[DataWidth - 1:0] q0; 58 | 59 | 60 | 61 | fir_c_rom fir_c_rom_U( 62 | .clk( clk ), 63 | .addr0( address0 ), 64 | .ce0( ce0 ), 65 | .q0( q0 )); 66 | 67 | endmodule 68 | 69 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir_c_rom.dat: -------------------------------------------------------------------------------- 1 | FE40 2 | FECA 3 | FE8B 4 | FE6A 5 | FE74 6 | FEB3 7 | FF2F 8 | FFE5 9 | 00CF 10 | 01DC 11 | 02F6 12 | 0401 13 | 04E0 14 | 0575 15 | 05A7 16 | 0566 17 | 04AB 18 | 037C 19 | 01EA 20 | 0010 21 | FE16 22 | FC26 23 | FA6C 24 | F90F 25 | F82F 26 | 77E3 27 | F82F 28 | F90F 29 | FA6C 30 | FC26 31 | FE16 32 | 0010 33 | 01EA 34 | 037C 35 | 04AB 36 | 0566 37 | 05A7 38 | 0575 39 | 04E0 40 | 0401 41 | 02F6 42 | 01DC 43 | 00CF 44 | FFE5 45 | FF2F 46 | FEB3 47 | FE74 48 | FE6A 49 | FE8B 50 | FECA 51 | FE40 52 | 53 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir_io_if.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2012.4 4 | // Copyright (C) 2012 Xilinx Inc. All rights reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1ns/1ps 9 | module fir_io_if 10 | #(parameter 11 | C_ADDR_WIDTH = 32, 12 | C_DATA_WIDTH = 32 13 | )( 14 | // axi4 lite slave signals 15 | input wire ACLK, 16 | input wire ARESETN, 17 | input wire [C_ADDR_WIDTH-1:0] AWADDR, 18 | input wire AWVALID, 19 | output wire AWREADY, 20 | input wire [C_DATA_WIDTH-1:0] WDATA, 21 | input wire [C_DATA_WIDTH/8-1:0] WSTRB, 22 | input wire WVALID, 23 | output wire WREADY, 24 | output wire [1:0] BRESP, 25 | output wire BVALID, 26 | input wire BREADY, 27 | input wire [C_ADDR_WIDTH-1:0] ARADDR, 28 | input wire ARVALID, 29 | output wire ARREADY, 30 | output wire [C_DATA_WIDTH-1:0] RDATA, 31 | output wire [1:0] RRESP, 32 | output wire RVALID, 33 | input wire RREADY, 34 | output wire interrupt, 35 | // user signals 36 | input wire [15:0] O_y, 37 | input wire O_y_ap_vld, 38 | output wire [15:0] I_x, 39 | output wire I_ap_start, 40 | input wire O_ap_ready, 41 | input wire O_ap_done, 42 | input wire O_ap_idle 43 | ); 44 | //------------------------Address Info------------------- 45 | // 0x00 : Control signals 46 | // bit 0 - ap_start (Read/Write/COH) 47 | // bit 1 - ap_done (Read/COR) 48 | // bit 2 - ap_idle (Read) 49 | // bit 3 - ap_ready (Read) 50 | // bit 7 - auto_restart (Read/Write) 51 | // others - reserved 52 | // 0x04 : Global Interrupt Enable Register 53 | // bit 0 - Global Interrupt Enable (Read/Write) 54 | // others - reserved 55 | // 0x08 : IP Interrupt Enable Register (Read/Write) 56 | // bit 0 - Channel 0 (ap_done) 57 | // bit 1 - Channel 1 (ap_ready) 58 | // others - reserved 59 | // 0x0c : IP Interrupt Status Register (Read/TOW) 60 | // bit 0 - Channel 0 (ap_done) 61 | // bit 1 - Channel 1 (ap_ready) 62 | // others - reserved 63 | // 0x10 : Control signal of y 64 | // bit 0 - y_ap_vld (Read/COR) 65 | // others - reserved 66 | // 0x14 : Data signal of y 67 | // bit 15~0 - y[15:0] (Read) 68 | // others - reserved 69 | // 0x18 : reserved 70 | // 0x1c : Data signal of x 71 | // bit 15~0 - x[15:0] (Read/Write) 72 | // others - reserved 73 | // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) 74 | 75 | //------------------------Parameter---------------------- 76 | // address bits 77 | localparam 78 | ADDR_BITS = 5; 79 | 80 | // address 81 | localparam 82 | ADDR_AP_CTRL = 5'h00, 83 | ADDR_GIE = 5'h04, 84 | ADDR_IER = 5'h08, 85 | ADDR_ISR = 5'h0c, 86 | ADDR_Y_CTRL = 5'h10, 87 | ADDR_Y_DATA_0 = 5'h14, 88 | ADDR_X_CTRL = 5'h18, 89 | ADDR_X_DATA_0 = 5'h1c; 90 | 91 | // axi write fsm 92 | localparam 93 | WRIDLE = 2'd0, 94 | WRDATA = 2'd1, 95 | WRRESP = 2'd2; 96 | 97 | // axi read fsm 98 | localparam 99 | RDIDLE = 2'd0, 100 | RDDATA = 2'd1; 101 | 102 | //------------------------Local signal------------------- 103 | // axi write 104 | reg [1:0] wstate; 105 | reg [1:0] wnext; 106 | reg [ADDR_BITS-1:0] waddr; 107 | wire [31:0] wmask; 108 | wire aw_hs; 109 | wire w_hs; 110 | // axi read 111 | reg [1:0] rstate; 112 | reg [1:0] rnext; 113 | reg [31:0] rdata; 114 | wire ar_hs; 115 | wire [ADDR_BITS-1:0] raddr; 116 | // internal registers 117 | wire ap_idle; 118 | reg ap_done; 119 | wire ap_ready; 120 | reg ap_start; 121 | reg auto_restart; 122 | reg gie; 123 | reg [1:0] ier; 124 | reg [1:0] isr; 125 | wire [15:0] _y; 126 | reg _y_ap_vld; 127 | reg [15:0] _x; 128 | 129 | //------------------------Body--------------------------- 130 | //++++++++++++++++++++++++axi write++++++++++++++++++++++ 131 | assign AWREADY = (wstate == WRIDLE); 132 | assign WREADY = (wstate == WRDATA); 133 | assign BRESP = 2'b00; // OKAY 134 | assign BVALID = (wstate == WRRESP); 135 | assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} }; 136 | assign aw_hs = AWVALID & AWREADY; 137 | assign w_hs = WVALID & WREADY; 138 | 139 | // wstate 140 | always @(posedge ACLK) begin 141 | if (~ARESETN) 142 | wstate <= WRIDLE; 143 | else 144 | wstate <= wnext; 145 | end 146 | 147 | // wnext 148 | always @(*) begin 149 | case (wstate) 150 | WRIDLE: 151 | if (AWVALID) 152 | wnext = WRDATA; 153 | else 154 | wnext = WRIDLE; 155 | WRDATA: 156 | if (WVALID) 157 | wnext = WRRESP; 158 | else 159 | wnext = WRDATA; 160 | WRRESP: 161 | if (BREADY) 162 | wnext = WRIDLE; 163 | else 164 | wnext = WRRESP; 165 | default: 166 | wnext = WRIDLE; 167 | endcase 168 | end 169 | 170 | // waddr 171 | always @(posedge ACLK) begin 172 | if (aw_hs) 173 | waddr <= AWADDR[ADDR_BITS-1:0]; 174 | end 175 | //+++++++++++++++++++++++++++++++++++++++++++++++++++++++ 176 | 177 | //++++++++++++++++++++++++axi read+++++++++++++++++++++++ 178 | assign ARREADY = (rstate == RDIDLE); 179 | assign RDATA = rdata; 180 | assign RRESP = 2'b00; // OKAY 181 | assign RVALID = (rstate == RDDATA); 182 | assign ar_hs = ARVALID & ARREADY; 183 | assign raddr = ARADDR[ADDR_BITS-1:0]; 184 | 185 | // rstate 186 | always @(posedge ACLK) begin 187 | if (~ARESETN) 188 | rstate <= RDIDLE; 189 | else 190 | rstate <= rnext; 191 | end 192 | 193 | // rnext 194 | always @(*) begin 195 | case (rstate) 196 | RDIDLE: 197 | if (ARVALID) 198 | rnext = RDDATA; 199 | else 200 | rnext = RDIDLE; 201 | RDDATA: 202 | if (RREADY) 203 | rnext = RDIDLE; 204 | else 205 | rnext = RDDATA; 206 | default: 207 | rnext = RDIDLE; 208 | endcase 209 | end 210 | 211 | // rdata 212 | always @(posedge ACLK) begin 213 | if (ar_hs) begin 214 | rdata <= 1'b0; 215 | case (raddr) 216 | ADDR_AP_CTRL: begin 217 | rdata[0] <= ap_start; 218 | rdata[1] <= ap_done; 219 | rdata[2] <= ap_idle; 220 | rdata[3] <= ap_ready; 221 | rdata[7] <= auto_restart; 222 | end 223 | ADDR_GIE: begin 224 | rdata <= gie; 225 | end 226 | ADDR_IER: begin 227 | rdata <= ier; 228 | end 229 | ADDR_ISR: begin 230 | rdata <= isr; 231 | end 232 | ADDR_Y_CTRL: begin 233 | rdata[0] <= _y_ap_vld; 234 | end 235 | ADDR_Y_DATA_0: begin 236 | rdata <= _y[15:0]; 237 | end 238 | ADDR_X_DATA_0: begin 239 | rdata <= _x[15:0]; 240 | end 241 | endcase 242 | end 243 | end 244 | //+++++++++++++++++++++++++++++++++++++++++++++++++++++++ 245 | 246 | //++++++++++++++++++++++++internal registers+++++++++++++ 247 | assign interrupt = gie & (|isr); 248 | assign I_ap_start = ap_start; 249 | assign ap_idle = O_ap_idle; 250 | assign ap_ready = O_ap_ready; 251 | assign _y = O_y; 252 | assign I_x = _x; 253 | 254 | // ap_start 255 | always @(posedge ACLK) begin 256 | if (~ARESETN) 257 | ap_start <= 1'b0; 258 | else if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0]) 259 | ap_start <= 1'b1; 260 | else if (O_ap_ready) 261 | ap_start <= auto_restart; // clear on handshake/auto restart 262 | end 263 | 264 | // ap_done 265 | always @(posedge ACLK) begin 266 | if (~ARESETN) 267 | ap_done <= 1'b0; 268 | else if (O_ap_done) 269 | ap_done <= 1'b1; 270 | else if (ar_hs && raddr == ADDR_AP_CTRL) 271 | ap_done <= 1'b0; // clear on read 272 | end 273 | 274 | // auto_restart 275 | always @(posedge ACLK) begin 276 | if (~ARESETN) 277 | auto_restart <= 1'b0; 278 | else if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0]) 279 | auto_restart <= WDATA[7]; 280 | end 281 | 282 | // gie 283 | always @(posedge ACLK) begin 284 | if (~ARESETN) 285 | gie <= 1'b0; 286 | else if (w_hs && waddr == ADDR_GIE && WSTRB[0]) 287 | gie <= WDATA[0]; 288 | end 289 | 290 | // ier 291 | always @(posedge ACLK) begin 292 | if (~ARESETN) 293 | ier <= 1'b0; 294 | else if (w_hs && waddr == ADDR_IER && WSTRB[0]) 295 | ier <= WDATA[1:0]; 296 | end 297 | 298 | // isr[0] 299 | always @(posedge ACLK) begin 300 | if (~ARESETN) 301 | isr[0] <= 1'b0; 302 | else if (ier[0] & O_ap_done) 303 | isr[0] <= 1'b1; 304 | else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) 305 | isr[0] <= isr[0] ^ WDATA[0]; // toggle on write 306 | end 307 | 308 | // isr[1] 309 | always @(posedge ACLK) begin 310 | if (~ARESETN) 311 | isr[1] <= 1'b0; 312 | else if (ier[1] & O_ap_ready) 313 | isr[1] <= 1'b1; 314 | else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) 315 | isr[1] <= isr[1] ^ WDATA[1]; // toggle on write 316 | end 317 | 318 | // _y_ap_vld 319 | always @(posedge ACLK) begin 320 | if (~ARESETN) 321 | _y_ap_vld <= 1'b0; 322 | else if (O_y_ap_vld) 323 | _y_ap_vld <= 1'b1; 324 | else if (ar_hs && raddr == ADDR_Y_CTRL) 325 | _y_ap_vld <= 1'b0; // clear on read 326 | end 327 | 328 | // _x[15:0] 329 | always @(posedge ACLK) begin 330 | if (w_hs && waddr == ADDR_X_DATA_0) 331 | _x[15:0] <= (WDATA[31:0] & wmask) | (_x[15:0] & ~wmask); 332 | end 333 | 334 | //+++++++++++++++++++++++++++++++++++++++++++++++++++++++ 335 | 336 | endmodule 337 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir_shift_reg.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2012.4 4 | // Copyright (C) 2012 Xilinx Inc. All rights reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | module fir_shift_reg_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk); 10 | 11 | parameter DWIDTH = 16; 12 | parameter AWIDTH = 6; 13 | parameter MEM_SIZE = 50; 14 | 15 | input[AWIDTH-1:0] addr0; 16 | input ce0; 17 | input[DWIDTH-1:0] d0; 18 | input we0; 19 | output reg[DWIDTH-1:0] q0; 20 | input[AWIDTH-1:0] addr1; 21 | input ce1; 22 | input[DWIDTH-1:0] d1; 23 | input we1; 24 | input clk; 25 | 26 | (* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; 27 | 28 | initial begin 29 | $readmemh("./fir_shift_reg_ram.dat", ram); 30 | end 31 | 32 | 33 | 34 | always @(posedge clk) 35 | begin 36 | if (ce0) 37 | begin 38 | if (we0) 39 | begin 40 | ram[addr0] <= d0; 41 | q0 <= d0; 42 | end 43 | else 44 | q0 <= ram[addr0]; 45 | end 46 | end 47 | 48 | 49 | always @(posedge clk) 50 | begin 51 | if (ce1) 52 | begin 53 | if (we1) 54 | begin 55 | ram[addr1] <= d1; 56 | end 57 | end 58 | end 59 | 60 | 61 | endmodule 62 | 63 | 64 | `timescale 1 ns / 1 ps 65 | module fir_shift_reg( 66 | reset, 67 | clk, 68 | address0, 69 | ce0, 70 | we0, 71 | d0, 72 | q0, 73 | address1, 74 | ce1, 75 | we1, 76 | d1); 77 | 78 | parameter DataWidth = 32'd16; 79 | parameter AddressRange = 32'd50; 80 | parameter AddressWidth = 32'd6; 81 | input reset; 82 | input clk; 83 | input[AddressWidth - 1:0] address0; 84 | input ce0; 85 | input we0; 86 | input[DataWidth - 1:0] d0; 87 | output[DataWidth - 1:0] q0; 88 | input[AddressWidth - 1:0] address1; 89 | input ce1; 90 | input we1; 91 | input[DataWidth - 1:0] d1; 92 | 93 | 94 | 95 | fir_shift_reg_ram fir_shift_reg_ram_U( 96 | .clk( clk ), 97 | .addr0( address0 ), 98 | .ce0( ce0 ), 99 | .d0( d0 ), 100 | .we0( we0 ), 101 | .q0( q0 ), 102 | .addr1( address1 ), 103 | .ce1( ce1 ), 104 | .d1( d1 ), 105 | .we1( we1 )); 106 | 107 | endmodule 108 | 109 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir_shift_reg_ram.dat: -------------------------------------------------------------------------------- 1 | 0000 2 | 0000 3 | 0000 4 | 0000 5 | 0000 6 | 0000 7 | 0000 8 | 0000 9 | 0000 10 | 0000 11 | 0000 12 | 0000 13 | 0000 14 | 0000 15 | 0000 16 | 0000 17 | 0000 18 | 0000 19 | 0000 20 | 0000 21 | 0000 22 | 0000 23 | 0000 24 | 0000 25 | 0000 26 | 0000 27 | 0000 28 | 0000 29 | 0000 30 | 0000 31 | 0000 32 | 0000 33 | 0000 34 | 0000 35 | 0000 36 | 0000 37 | 0000 38 | 0000 39 | 0000 40 | 0000 41 | 0000 42 | 0000 43 | 0000 44 | 0000 45 | 0000 46 | 0000 47 | 0000 48 | 0000 49 | 0000 50 | 0000 51 | 52 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.srcs/sources_1/imports/verilog/fir_top.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2012.4 4 | // Copyright (C) 2012 Xilinx Inc. All rights reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | module fir_top ( 10 | s_axi_fir_io_AWADDR, 11 | s_axi_fir_io_AWVALID, 12 | s_axi_fir_io_AWREADY, 13 | s_axi_fir_io_WDATA, 14 | s_axi_fir_io_WSTRB, 15 | s_axi_fir_io_WVALID, 16 | s_axi_fir_io_WREADY, 17 | s_axi_fir_io_BRESP, 18 | s_axi_fir_io_BVALID, 19 | s_axi_fir_io_BREADY, 20 | s_axi_fir_io_ARADDR, 21 | s_axi_fir_io_ARVALID, 22 | s_axi_fir_io_ARREADY, 23 | s_axi_fir_io_RDATA, 24 | s_axi_fir_io_RRESP, 25 | s_axi_fir_io_RVALID, 26 | s_axi_fir_io_RREADY, 27 | interrupt, 28 | aresetn, 29 | aclk 30 | ); 31 | 32 | parameter C_S_AXI_FIR_IO_ADDR_WIDTH = 32; 33 | parameter C_S_AXI_FIR_IO_DATA_WIDTH = 32; 34 | parameter RESET_ACTIVE_LOW = 1; 35 | 36 | input [C_S_AXI_FIR_IO_ADDR_WIDTH - 1:0] s_axi_fir_io_AWADDR ; 37 | input s_axi_fir_io_AWVALID ; 38 | output s_axi_fir_io_AWREADY ; 39 | input [C_S_AXI_FIR_IO_DATA_WIDTH - 1:0] s_axi_fir_io_WDATA ; 40 | input [C_S_AXI_FIR_IO_DATA_WIDTH/8 - 1:0] s_axi_fir_io_WSTRB ; 41 | input s_axi_fir_io_WVALID ; 42 | output s_axi_fir_io_WREADY ; 43 | output [2 - 1:0] s_axi_fir_io_BRESP ; 44 | output s_axi_fir_io_BVALID ; 45 | input s_axi_fir_io_BREADY ; 46 | input [C_S_AXI_FIR_IO_ADDR_WIDTH - 1:0] s_axi_fir_io_ARADDR ; 47 | input s_axi_fir_io_ARVALID ; 48 | output s_axi_fir_io_ARREADY ; 49 | output [C_S_AXI_FIR_IO_DATA_WIDTH - 1:0] s_axi_fir_io_RDATA ; 50 | output [2 - 1:0] s_axi_fir_io_RRESP ; 51 | output s_axi_fir_io_RVALID ; 52 | input s_axi_fir_io_RREADY ; 53 | output interrupt ; 54 | 55 | input aresetn ; 56 | 57 | input aclk ; 58 | 59 | 60 | wire [C_S_AXI_FIR_IO_ADDR_WIDTH - 1:0] s_axi_fir_io_AWADDR; 61 | wire s_axi_fir_io_AWVALID; 62 | wire s_axi_fir_io_AWREADY; 63 | wire [C_S_AXI_FIR_IO_DATA_WIDTH - 1:0] s_axi_fir_io_WDATA; 64 | wire [C_S_AXI_FIR_IO_DATA_WIDTH/8 - 1:0] s_axi_fir_io_WSTRB; 65 | wire s_axi_fir_io_WVALID; 66 | wire s_axi_fir_io_WREADY; 67 | wire [2 - 1:0] s_axi_fir_io_BRESP; 68 | wire s_axi_fir_io_BVALID; 69 | wire s_axi_fir_io_BREADY; 70 | wire [C_S_AXI_FIR_IO_ADDR_WIDTH - 1:0] s_axi_fir_io_ARADDR; 71 | wire s_axi_fir_io_ARVALID; 72 | wire s_axi_fir_io_ARREADY; 73 | wire [C_S_AXI_FIR_IO_DATA_WIDTH - 1:0] s_axi_fir_io_RDATA; 74 | wire [2 - 1:0] s_axi_fir_io_RRESP; 75 | wire s_axi_fir_io_RVALID; 76 | wire s_axi_fir_io_RREADY; 77 | wire interrupt; 78 | 79 | wire aresetn; 80 | 81 | 82 | wire [16 - 1:0] sig_fir_y; 83 | wire sig_fir_y_ap_vld; 84 | wire [16 - 1:0] sig_fir_x; 85 | wire sig_fir_ap_start; 86 | wire sig_fir_ap_ready; 87 | wire sig_fir_ap_done; 88 | wire sig_fir_ap_idle; 89 | 90 | wire sig_fir_ap_rst; 91 | 92 | 93 | 94 | 95 | fir fir_U( 96 | .y(sig_fir_y), 97 | .y_ap_vld(sig_fir_y_ap_vld), 98 | .x(sig_fir_x), 99 | .ap_start(sig_fir_ap_start), 100 | .ap_ready(sig_fir_ap_ready), 101 | .ap_done(sig_fir_ap_done), 102 | .ap_idle(sig_fir_ap_idle), 103 | .ap_rst(sig_fir_ap_rst), 104 | .ap_clk(aclk) 105 | ); 106 | 107 | fir_io_if #( 108 | .C_ADDR_WIDTH(C_S_AXI_FIR_IO_ADDR_WIDTH), 109 | .C_DATA_WIDTH(C_S_AXI_FIR_IO_DATA_WIDTH)) 110 | fir_io_if_U( 111 | .ACLK(aclk), 112 | .ARESETN(aresetn), 113 | .O_y(sig_fir_y), 114 | .O_y_ap_vld(sig_fir_y_ap_vld), 115 | .I_x(sig_fir_x), 116 | .I_ap_start(sig_fir_ap_start), 117 | .O_ap_ready(sig_fir_ap_ready), 118 | .O_ap_done(sig_fir_ap_done), 119 | .O_ap_idle(sig_fir_ap_idle), 120 | .AWADDR(s_axi_fir_io_AWADDR), 121 | .AWVALID(s_axi_fir_io_AWVALID), 122 | .AWREADY(s_axi_fir_io_AWREADY), 123 | .WDATA(s_axi_fir_io_WDATA), 124 | .WSTRB(s_axi_fir_io_WSTRB), 125 | .WVALID(s_axi_fir_io_WVALID), 126 | .WREADY(s_axi_fir_io_WREADY), 127 | .BRESP(s_axi_fir_io_BRESP), 128 | .BVALID(s_axi_fir_io_BVALID), 129 | .BREADY(s_axi_fir_io_BREADY), 130 | .ARADDR(s_axi_fir_io_ARADDR), 131 | .ARVALID(s_axi_fir_io_ARVALID), 132 | .ARREADY(s_axi_fir_io_ARREADY), 133 | .RDATA(s_axi_fir_io_RDATA), 134 | .RRESP(s_axi_fir_io_RRESP), 135 | .RVALID(s_axi_fir_io_RVALID), 136 | .RREADY(s_axi_fir_io_RREADY), 137 | .interrupt(interrupt)); 138 | 139 | fir_ap_rst_if #( 140 | .RESET_ACTIVE_LOW(RESET_ACTIVE_LOW)) 141 | ap_rst_if_U( 142 | .dout(sig_fir_ap_rst), 143 | .din(aresetn)); 144 | 145 | endmodule 146 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_ip.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_top_0/fir_top_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | fir_top_0 10 | 11 | 12 | 1 13 | 32 14 | 32 15 | fir_top_0 16 | 32 17 | 32 18 | 1 19 | virtex7 20 | xc7vx485t 21 | ffg1157 22 | -1 23 | C 24 | 25 | VERILOG 26 | TRUE 27 | TRUE 28 | 29 | TRUE 30 | 2013.2 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/fir_top_0_0/fir_top_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | fir_top_0 10 | 11 | 12 | 1 13 | 32 14 | 32 15 | fir_top_0 16 | 16 17 | 32 18 | 1 19 | virtex7 20 | xc7vx485t 21 | ffg1157 22 | -1 23 | C 24 | 25 | VERILOG 26 | TRUE 27 | TRUE 28 | .. 29 | TRUE 30 | 2013.2 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /sources/lab6/fir_ip/xgui/fir_top_v1_0.tcl: -------------------------------------------------------------------------------- 1 | #Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ ipgui::add_param $IPINST -parent $Page0 -name Component_Name ] 5 | set RESET_ACTIVE_LOW [ipgui::add_param $IPINST -parent $Page0 -name RESET_ACTIVE_LOW] 6 | set C_S_AXI_FIR_IO_DATA_WIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_S_AXI_FIR_IO_DATA_WIDTH] 7 | set C_S_AXI_FIR_IO_ADDR_WIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_S_AXI_FIR_IO_ADDR_WIDTH] 8 | } 9 | 10 | proc update_PARAM_VALUE.RESET_ACTIVE_LOW { PARAM_VALUE.RESET_ACTIVE_LOW } { 11 | # Procedure called to update RESET_ACTIVE_LOW when any of the dependent parameters in the arguments change 12 | } 13 | 14 | proc validate_PARAM_VALUE.RESET_ACTIVE_LOW { PARAM_VALUE.RESET_ACTIVE_LOW } { 15 | # Procedure called to validate RESET_ACTIVE_LOW 16 | return true 17 | } 18 | 19 | proc update_PARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH { PARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH } { 20 | # Procedure called to update C_S_AXI_FIR_IO_DATA_WIDTH when any of the dependent parameters in the arguments change 21 | } 22 | 23 | proc validate_PARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH { PARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH } { 24 | # Procedure called to validate C_S_AXI_FIR_IO_DATA_WIDTH 25 | return true 26 | } 27 | 28 | proc update_PARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH } { 29 | # Procedure called to update C_S_AXI_FIR_IO_ADDR_WIDTH when any of the dependent parameters in the arguments change 30 | } 31 | 32 | proc validate_PARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH } { 33 | # Procedure called to validate C_S_AXI_FIR_IO_ADDR_WIDTH 34 | return true 35 | } 36 | 37 | 38 | proc update_MODELPARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH PARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH } { 39 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 40 | set_property value [get_property value ${PARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_FIR_IO_ADDR_WIDTH} 41 | } 42 | 43 | proc update_MODELPARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH PARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH } { 44 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 45 | set_property value [get_property value ${PARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_FIR_IO_DATA_WIDTH} 46 | } 47 | 48 | proc update_MODELPARAM_VALUE.RESET_ACTIVE_LOW { MODELPARAM_VALUE.RESET_ACTIVE_LOW PARAM_VALUE.RESET_ACTIVE_LOW } { 49 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 50 | set_property value [get_property value ${PARAM_VALUE.RESET_ACTIVE_LOW}] ${MODELPARAM_VALUE.RESET_ACTIVE_LOW} 51 | } 52 | 53 | -------------------------------------------------------------------------------- /sources/lab6/lab6.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include "xuartps.h" 8 | #include "fir.h" 9 | #include "xfir_fir_io.h" 10 | 11 | void fir_software (short *y, short x); 12 | 13 | typedef short Xint16; 14 | typedef long Xint32; 15 | 16 | void filter_hw_accel_input(short * Sample_L_out, short Sample_L_in) 17 | { 18 | 19 | xil_printf("input sample: %d\r\n",Sample_L_in); 20 | Xil_Out32(XPAR_FIR_LEFT_BASEADDR+XFIR_FIR_IO_ADDR_X_DATA, Sample_L_in); // send left channel sample 21 | Xil_Out32(XPAR_FIR_LEFT_BASEADDR+XFIR_FIR_IO_ADDR_AP_CTRL, 0x1); // pulse ap_start left channel 22 | Xil_Out32(XPAR_FIR_LEFT_BASEADDR+XFIR_FIR_IO_ADDR_AP_CTRL, 0x0); 23 | while(1){ 24 | if(Xil_In32(XPAR_FIR_LEFT_BASEADDR+XFIR_FIR_IO_ADDR_Y_CTRL)) 25 | break; 26 | else 27 | continue; 28 | } 29 | *Sample_L_out = Xil_In32(XPAR_FIR_LEFT_BASEADDR+XFIR_FIR_IO_ADDR_Y_DATA); 30 | xil_printf("output sample: %d\r\n",*Sample_L_out); 31 | } 32 | 33 | int main(void) 34 | { 35 | short signal, output; 36 | 37 | int i; 38 | for (i=0;i