├── Chapter_10 ├── LCD_1602 │ ├── LCD_1602.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── LCD_1602.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── LCD_1602.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ └── LCD_1602.v │ └── LCD_1602.xpr └── OLED │ ├── OLED.cache │ ├── ip │ │ ├── 07063c77 │ │ │ ├── 07063c77.xci │ │ │ └── i_ila.dcp │ │ ├── 456c2918 │ │ │ ├── 456c2918.xci │ │ │ └── i_xsdbm.dcp │ │ ├── 66fae767 │ │ │ ├── 66fae767.xci │ │ │ └── i_ila.dcp │ │ ├── 76458b5c │ │ │ ├── 76458b5c.xci │ │ │ └── i_xsdbm.dcp │ │ └── 83b65077 │ │ │ ├── 83b65077.xci │ │ │ └── i_ila.dcp │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf │ ├── OLED.hw │ ├── OLED.lpr │ └── hw_1 │ │ ├── hw.xml │ │ ├── wave │ │ ├── hw_ila_data_1 │ │ │ ├── hw_ila_data_1.wcfg │ │ │ └── hw_ila_data_1.wdb │ │ └── hw_ila_data_2 │ │ │ ├── hw_ila_data_2.wcfg │ │ │ └── hw_ila_data_2.wdb │ │ └── xc7a35t_0 │ │ └── dashboard │ │ ├── hw_ila_1.xml │ │ └── hw_ila_2.xml │ ├── OLED.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_20.xml │ │ ├── vrs_config_21.xml │ │ ├── vrs_config_22.xml │ │ ├── vrs_config_23.xml │ │ ├── vrs_config_24.xml │ │ ├── vrs_config_25.xml │ │ ├── vrs_config_26.xml │ │ ├── vrs_config_27.xml │ │ ├── vrs_config_28.xml │ │ ├── vrs_config_29.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_30.xml │ │ ├── vrs_config_31.xml │ │ ├── vrs_config_32.xml │ │ ├── vrs_config_33.xml │ │ ├── vrs_config_34.xml │ │ ├── vrs_config_35.xml │ │ ├── vrs_config_36.xml │ │ ├── vrs_config_37.xml │ │ ├── vrs_config_38.xml │ │ ├── vrs_config_39.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_40.xml │ │ ├── vrs_config_41.xml │ │ ├── vrs_config_42.xml │ │ ├── vrs_config_43.xml │ │ ├── vrs_config_44.xml │ │ ├── vrs_config_45.xml │ │ ├── vrs_config_46.xml │ │ ├── vrs_config_47.xml │ │ ├── vrs_config_48.xml │ │ ├── vrs_config_49.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_50.xml │ │ ├── vrs_config_51.xml │ │ ├── vrs_config_52.xml │ │ ├── vrs_config_53.xml │ │ ├── vrs_config_54.xml │ │ ├── vrs_config_55.xml │ │ ├── vrs_config_56.xml │ │ ├── vrs_config_57.xml │ │ ├── vrs_config_58.xml │ │ ├── vrs_config_59.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_60.xml │ │ ├── vrs_config_61.xml │ │ ├── vrs_config_62.xml │ │ ├── vrs_config_63.xml │ │ ├── vrs_config_64.xml │ │ ├── vrs_config_65.xml │ │ ├── vrs_config_66.xml │ │ ├── vrs_config_67.xml │ │ ├── vrs_config_68.xml │ │ ├── vrs_config_69.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_70.xml │ │ ├── vrs_config_71.xml │ │ ├── vrs_config_72.xml │ │ ├── vrs_config_73.xml │ │ ├── vrs_config_74.xml │ │ ├── vrs_config_75.xml │ │ ├── vrs_config_76.xml │ │ ├── vrs_config_77.xml │ │ ├── vrs_config_78.xml │ │ ├── vrs_config_79.xml │ │ ├── vrs_config_8.xml │ │ ├── vrs_config_80.xml │ │ ├── vrs_config_81.xml │ │ ├── vrs_config_82.xml │ │ ├── vrs_config_83.xml │ │ ├── vrs_config_84.xml │ │ ├── vrs_config_85.xml │ │ ├── vrs_config_86.xml │ │ ├── vrs_config_87.xml │ │ ├── vrs_config_88.xml │ │ ├── vrs_config_89.xml │ │ ├── vrs_config_9.xml │ │ ├── vrs_config_90.xml │ │ ├── vrs_config_91.xml │ │ ├── vrs_config_92.xml │ │ ├── vrs_config_93.xml │ │ └── vrs_config_94.xml │ ├── impl_1 │ │ ├── init_design.pb │ │ ├── oled_top_43412.backup.vdi │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── vivado_43412.backup.jou │ │ └── write_bitstream.pb │ ├── impl_2 │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── runme.log │ │ ├── vivado_55544.backup.jou │ │ └── write_bitstream.pb │ └── synth_2 │ │ └── runme.log │ ├── OLED.sim │ └── sim_1 │ │ ├── behav │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── tb.tcl │ │ ├── tb_behav.wdb │ │ ├── tb_vlog.prj │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ │ ├── tb_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsimk.exe │ │ │ │ └── xsimkernel.log │ │ │ ├── xil_defaultlib │ │ │ │ ├── glbl.sdb │ │ │ │ ├── oled_clear.sdb │ │ │ │ ├── oled_init.sdb │ │ │ │ ├── oled_top.sdb │ │ │ │ ├── oled_write_data.sdb │ │ │ │ ├── spi_master.sdb │ │ │ │ └── tb.sdb │ │ │ └── xsim.svtype │ │ └── xvlog.pb │ │ └── synth │ │ └── func │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── glbl.v │ │ ├── tb_func_synth.v │ │ ├── tb_vlog.prj │ │ ├── xsim.dir │ │ ├── xil_defaultlib │ │ │ ├── glbl.sdb │ │ │ ├── oled_init.sdb │ │ │ ├── oled_top.sdb │ │ │ ├── oled_write_data.sdb │ │ │ ├── spi_master.sdb │ │ │ └── tb.sdb │ │ └── xsim.svtype │ │ └── xvlog.pb │ ├── OLED.srcs │ ├── component.xml │ ├── component.xml~ │ ├── constrs_1 │ │ └── new │ │ │ └── PIN.xdc │ ├── sim_1 │ │ └── new │ │ │ └── tb.v │ ├── sources_1 │ │ └── new │ │ │ ├── oled.v │ │ │ ├── oled_clear.v │ │ │ ├── oled_top.v │ │ │ ├── oled_write_data.v │ │ │ └── spi_master.v │ └── xgui │ │ └── oled_top_v1_0.tcl │ ├── OLED.xpr │ └── src │ ├── PIN.xdc │ ├── oled.v │ ├── oled_clear.v │ ├── oled_top.v │ ├── oled_write_data.v │ └── spi_master.v ├── Chapter_11 └── VGA │ ├── IP │ ├── XUP_vga_1.0.zip │ └── XUP_vga_1.0 │ │ ├── component.xml │ │ ├── vga.v │ │ └── xgui │ │ └── vga_v1_0.tcl │ ├── VGA.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── VGA.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ └── vrs_config_7.xml │ ├── impl_1 │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── runme.log │ │ └── write_bitstream.pb │ └── synth_1 │ │ └── runme.log │ ├── VGA.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── pin.xdc │ └── sources_1 │ │ ├── ip │ │ └── vga_0 │ │ │ ├── vga_0.dcp │ │ │ ├── vga_0.xci │ │ │ ├── vga_0.xml │ │ │ ├── vga_0_funcsim.v │ │ │ ├── vga_0_funcsim.vhdl │ │ │ ├── vga_0_stub.v │ │ │ └── vga_0_stub.vhdl │ │ └── new │ │ ├── vga.v │ │ └── vga_char.v │ └── VGA.xpr ├── Chapter_12 └── Digital_camera │ ├── digital_camera.cache │ ├── ip │ │ ├── 07063c77 │ │ │ ├── 07063c77.xci │ │ │ └── i_ila.dcp │ │ ├── 456c2918 │ │ │ ├── 456c2918.xci │ │ │ └── i_xsdbm.dcp │ │ ├── 4c4a9684 │ │ │ ├── 4c4a9684.xci │ │ │ └── i_ila.dcp │ │ ├── 646eb2f6 │ │ │ ├── 646eb2f6.xci │ │ │ └── i_ila.dcp │ │ ├── 76458b5c │ │ │ ├── 76458b5c.xci │ │ │ └── i_xsdbm.dcp │ │ ├── 83b65077 │ │ │ ├── 83b65077.xci │ │ │ └── i_ila.dcp │ │ ├── 86f5b0bb │ │ │ ├── 86f5b0bb.xci │ │ │ └── i_ila.dcp │ │ └── c8fafa84 │ │ │ ├── c8fafa84.xci │ │ │ └── i_ila.dcp │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── digital_camera.hw │ └── hw_1 │ │ ├── hw.xml │ │ ├── wave │ │ ├── hw_ila_data_1 │ │ │ ├── hw_ila_data_1.wcfg │ │ │ └── hw_ila_data_1.wdb │ │ └── hw_ila_data_2 │ │ │ ├── hw_ila_data_2.wcfg │ │ │ └── hw_ila_data_2.wdb │ │ └── xc7a35t_0 │ │ └── dashboard │ │ ├── hw_ila_1.xml │ │ └── hw_ila_2.xml │ ├── digital_camera.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_20.xml │ │ ├── vrs_config_21.xml │ │ ├── vrs_config_22.xml │ │ ├── vrs_config_23.xml │ │ ├── vrs_config_24.xml │ │ ├── vrs_config_25.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ ├── impl_1 │ │ ├── debug_nets.ltx │ │ ├── design_1_26252.backup.vdi │ │ ├── design_1_28848.backup.vdi │ │ ├── vivado_26252.backup.jou │ │ ├── vivado_28848.backup.jou │ │ └── vivado_40880.backup.jou │ └── synth_1 │ │ └── runme.log │ ├── digital_camera.srcs │ └── sources_1 │ │ └── ip │ │ ├── IICctrl_0 │ │ ├── IICctrl_0.dcp │ │ ├── IICctrl_0.xci │ │ ├── IICctrl_0.xml │ │ ├── IICctrl_0_funcsim.v │ │ ├── IICctrl_0_funcsim.vhdl │ │ ├── IICctrl_0_stub.v │ │ └── IICctrl_0_stub.vhdl │ │ ├── blk_mem_gen_0 │ │ ├── blk_mem_gen_0.dcp │ │ ├── blk_mem_gen_0.xci │ │ ├── blk_mem_gen_0.xml │ │ ├── blk_mem_gen_0_funcsim.v │ │ ├── blk_mem_gen_0_funcsim.vhdl │ │ ├── blk_mem_gen_0_stub.v │ │ └── blk_mem_gen_0_stub.vhdl │ │ ├── cam_ov7670_ov7725_0 │ │ ├── cam_ov7670_ov7725_0.dcp │ │ ├── cam_ov7670_ov7725_0.xci │ │ ├── cam_ov7670_ov7725_0.xml │ │ ├── cam_ov7670_ov7725_0_funcsim.v │ │ ├── cam_ov7670_ov7725_0_funcsim.vhdl │ │ ├── cam_ov7670_ov7725_0_stub.v │ │ └── cam_ov7670_ov7725_0_stub.vhdl │ │ ├── clk_wiz_0 │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0.xci │ │ ├── clk_wiz_0.xml │ │ ├── clk_wiz_0_funcsim.v │ │ ├── clk_wiz_0_funcsim.vhdl │ │ ├── clk_wiz_0_stub.v │ │ └── clk_wiz_0_stub.vhdl │ │ ├── ov7725_regData_0 │ │ ├── ov7725_regData_0.dcp │ │ ├── ov7725_regData_0.xci │ │ ├── ov7725_regData_0.xml │ │ ├── ov7725_regData_0_funcsim.v │ │ ├── ov7725_regData_0_funcsim.vhdl │ │ ├── ov7725_regData_0_stub.v │ │ └── ov7725_regData_0_stub.vhdl │ │ ├── ram_read_0 │ │ ├── ram_read_0.dcp │ │ ├── ram_read_0.xci │ │ ├── ram_read_0.xml │ │ ├── ram_read_0_funcsim.v │ │ ├── ram_read_0_funcsim.vhdl │ │ ├── ram_read_0_stub.v │ │ └── ram_read_0_stub.vhdl │ │ └── vga_0 │ │ ├── vga_0.dcp │ │ ├── vga_0.xci │ │ ├── vga_0.xml │ │ ├── vga_0_funcsim.v │ │ ├── vga_0_funcsim.vhdl │ │ ├── vga_0_stub.v │ │ └── vga_0_stub.vhdl │ ├── digital_camera.tcl │ ├── digital_camera.xpr │ └── files │ ├── Constraint │ └── cam_bram_vga.xdc │ ├── HDL_source │ ├── IP_Catalog │ │ ├── XUP_IICctrl_1.0.zip │ │ ├── XUP_IICctrl_1.0 │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── iic_tb.v │ │ │ ├── sources_1 │ │ │ │ └── imports │ │ │ │ │ └── src │ │ │ │ │ ├── I2C_Controller.v │ │ │ │ │ └── IICctrl.v │ │ │ └── xgui │ │ │ │ └── IICctrl_v1_0.tcl │ │ ├── XUP_cam_ov7670_ov7725_1.0.zip │ │ ├── XUP_cam_ov7670_ov7725_1.0 │ │ │ ├── cam_ov7670_ov7725.v │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ │ └── cam_ov7670_ov7725_v1_0.tcl │ │ ├── XUP_ov7725_regData_1.0.zip │ │ ├── XUP_ov7725_regData_1.0 │ │ │ ├── component.xml │ │ │ ├── ov7725_regData.v │ │ │ └── xgui │ │ │ │ └── ov7725_regData_v1_0.tcl │ │ ├── XUP_ram_read_1.0.zip │ │ ├── XUP_ram_read_1.0 │ │ │ ├── component.xml │ │ │ ├── ram_read.v │ │ │ └── xgui │ │ │ │ └── ram_read_v1_0.tcl │ │ ├── XUP_vga_1.0.zip │ │ └── XUP_vga_1.0 │ │ │ └── vga_1.0 │ │ │ ├── component.xml │ │ │ ├── doc │ │ │ └── readme.txt │ │ │ ├── gui │ │ │ └── vga_v1_0.gtcl │ │ │ ├── misc │ │ │ ├── Thumbs.db │ │ │ └── xup.png │ │ │ ├── src │ │ │ └── vga.v │ │ │ └── xgui │ │ │ ├── vga_v1_0.tcl │ │ │ └── vga_v1_0.tcl~ │ └── design_1.v │ └── digital_camera.tcl ├── Chapter_13 ├── Digital_Clock │ ├── Digital_Clock_Design.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── Digital_Clock_Design.hw │ │ └── hw_1 │ │ │ └── hw.xml │ ├── Digital_Clock_Design.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ └── vrs_config_4.xml │ │ ├── impl_1 │ │ │ ├── init_design.pb │ │ │ ├── opt_design.pb │ │ │ ├── place_design.pb │ │ │ ├── route_design.pb │ │ │ ├── runme.log │ │ │ └── write_bitstream.pb │ │ └── synth_1 │ │ │ └── runme.log │ ├── Digital_Clock_Design.srcs │ │ ├── constrs_1 │ │ │ └── imports │ │ │ │ └── Constraint │ │ │ │ └── Digital_Clock.xdc │ │ └── sources_1 │ │ │ ├── bd │ │ │ └── Digital_Clock │ │ │ │ ├── Digital_Clock.bd │ │ │ │ ├── Digital_Clock.bxml │ │ │ │ ├── hdl │ │ │ │ └── Digital_Clock_wrapper.v │ │ │ │ ├── ip │ │ │ │ ├── Digital_Clock_clk_div_1_0 │ │ │ │ │ ├── Digital_Clock_clk_div_1_0.xci │ │ │ │ │ └── Digital_Clock_clk_div_1_0.xml │ │ │ │ ├── Digital_Clock_clk_wiz_0_0 │ │ │ │ │ ├── Digital_Clock_clk_wiz_0_0.xci │ │ │ │ │ └── Digital_Clock_clk_wiz_0_0.xml │ │ │ │ ├── Digital_Clock_decimal_counter_0_0 │ │ │ │ │ ├── Digital_Clock_decimal_counter_0_0.xci │ │ │ │ │ └── Digital_Clock_decimal_counter_0_0.xml │ │ │ │ ├── Digital_Clock_decimal_counter_1_0 │ │ │ │ │ ├── Digital_Clock_decimal_counter_1_0.xci │ │ │ │ │ └── Digital_Clock_decimal_counter_1_0.xml │ │ │ │ ├── Digital_Clock_decimal_counter_2_0 │ │ │ │ │ ├── Digital_Clock_decimal_counter_2_0.xci │ │ │ │ │ └── Digital_Clock_decimal_counter_2_0.xml │ │ │ │ ├── Digital_Clock_decimal_counter_3_0 │ │ │ │ │ ├── Digital_Clock_decimal_counter_3_0.xci │ │ │ │ │ └── Digital_Clock_decimal_counter_3_0.xml │ │ │ │ ├── Digital_Clock_four_2_input_and_gate_0_0 │ │ │ │ │ ├── Digital_Clock_four_2_input_and_gate_0_0.xci │ │ │ │ │ └── Digital_Clock_four_2_input_and_gate_0_0.xml │ │ │ │ ├── Digital_Clock_seg7decimal_0_0 │ │ │ │ │ ├── Digital_Clock_seg7decimal_0_0.xci │ │ │ │ │ └── Digital_Clock_seg7decimal_0_0.xml │ │ │ │ └── Digital_Clock_xlconcat_0_0 │ │ │ │ │ ├── Digital_Clock_xlconcat_0_0.xci │ │ │ │ │ └── Digital_Clock_xlconcat_0_0.xml │ │ │ │ └── ui │ │ │ │ └── bd_66a9ddc7.ui │ │ │ ├── imports │ │ │ └── hdl │ │ │ │ └── Digital_Clock_wrapper.v │ │ │ └── ipshared │ │ │ └── xilinx.com │ │ │ ├── clk_div_v1_0 │ │ │ └── 9423c250 │ │ │ │ └── clk_div.v │ │ │ ├── decimal_counter_v1_0 │ │ │ └── 3750c69a │ │ │ │ └── decimal_counter.v │ │ │ ├── four_2_input_and_gate_v1_0 │ │ │ └── ee0e8530 │ │ │ │ └── four_2_input_and_gate.v │ │ │ ├── seg7decimal_v1_0 │ │ │ └── a7f128b3 │ │ │ │ └── sources_1 │ │ │ │ └── new │ │ │ │ └── seg7decimal.v │ │ │ └── xlconcat_v2_1 │ │ │ └── 21a398c4 │ │ │ └── xlconcat.v │ ├── Digital_Clock_Design.xpr │ └── IP_Catalog │ │ ├── XUP_74LS08_1.0.zip │ │ ├── XUP_74LS08_1.0 │ │ ├── component.xml │ │ ├── four_2_input_and_gate.v │ │ └── xgui │ │ │ └── four_2_input_and_gate_v1_0.tcl │ │ ├── xup_74LS90_1.0.zip │ │ ├── xup_74LS90_1.0 │ │ ├── component.xml │ │ ├── decimal_counter.v │ │ └── xgui │ │ │ └── decimal_counter_v1_0.tcl │ │ ├── xup_clk_div_1.0.zip │ │ ├── xup_clk_div_1.0 │ │ ├── clk_div.v │ │ ├── component.xml │ │ └── xgui │ │ │ └── clk_div_v1_0.tcl │ │ ├── xup_seg7decimal_1.0.zip │ │ └── xup_seg7decimal_1.0 │ │ ├── component.xml │ │ ├── sim_1 │ │ └── new │ │ │ └── seg7decimal_tb.v │ │ ├── sources_1 │ │ └── new │ │ │ └── seg7decimal.v │ │ └── xgui │ │ └── seg7decimal_v1_0.tcl └── Timing_analyzation │ ├── Timing_analyzation.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf │ ├── Timing_analyzation.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ ├── impl_1 │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ └── runme.log │ └── synth_1 │ │ ├── runme.log │ │ └── vivado.pb │ ├── Timing_analyzation.sim │ └── sim_1 │ │ └── impl │ │ └── timing │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── tb.tcl │ │ ├── tb_time_impl.sdf │ │ ├── tb_time_impl.v │ │ ├── tb_time_impl.wdb │ │ ├── tb_vlog.prj │ │ ├── timing_analyze_time_impl.wdb │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── tb_time_impl │ │ │ ├── Compile_Options.txt │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── timing_analyze_time_impl │ │ │ ├── xsim.mem │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── xil_defaultlib │ │ │ ├── glbl.sdb │ │ │ ├── tb.sdb │ │ │ └── timing_analyze.sdb │ │ └── xsim.svtype │ │ └── xvlog.pb │ ├── Timing_analyzation.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── clock.xdc │ ├── sim_1 │ │ └── new │ │ │ └── tb.v │ └── sources_1 │ │ └── new │ │ └── timing_analyze.v │ └── Timing_analyzation.xpr ├── Chapter_14 └── RISC │ ├── IPCatalog │ ├── ALU │ │ └── ALU.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── ALU_TB.sv │ │ │ ├── sources_1 │ │ │ └── new │ │ │ │ ├── ALU.v │ │ │ │ ├── LOGIC.v │ │ │ │ ├── MATH.v │ │ │ │ └── SHIFT.v │ │ │ └── xgui │ │ │ └── ALU32_v1_0.tcl │ ├── CONTROL_UNIT │ │ └── CONTROL_UNIT.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── CONTROL_UNIT_TB.sv │ │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── CONTROL_UNIT.v │ │ │ └── xgui │ │ │ └── CONTROL_UNIT_v1_0.tcl │ ├── DATAPATH │ │ └── DATAPATH.srcs │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── ADDSUB32.v │ │ │ ├── DATAPATH.v │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ └── DATAPATH_v1_0.tcl │ ├── DATA_MEM │ │ └── DATA_MEM.srcs │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── DATA_MEM.v │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ └── DATA_MEM_v1_0.tcl │ ├── INST_MEM │ │ └── INST_MEM.srcs │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── INST_MEM.v │ │ │ ├── component.xml │ │ │ └── xgui │ │ │ └── INST_MEM_v1_0.tcl │ ├── KEY2INST │ │ └── KEY2INST.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── KEY2INST_TB.sv │ │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── KEY2INST.v │ │ │ └── xgui │ │ │ └── KEY2INST_v1_0.tcl │ ├── REGFILE │ │ └── REGFILE.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── REGFILE_TB.sv │ │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── REGFILE.v │ │ │ └── xgui │ │ │ └── REGFILE_v1_0.tcl │ └── SHOW_ON_LED │ │ └── SHOW_ON_LED.srcs │ │ └── sources_1 │ │ └── new │ │ ├── SHOW_ON_LED.v │ │ ├── component.xml │ │ └── xgui │ │ └── SHOW_ON_LED_v1_0.tcl │ ├── MIPS_CPU.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── MIPS_CPU.hw │ └── hw_1 │ │ └── hw.xml │ ├── MIPS_CPU.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ └── vrs_config_5.xml │ └── impl_1 │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── runme.log │ │ └── write_bitstream.pb │ ├── MIPS_CPU.srcs │ ├── constrs_1 │ │ └── imports │ │ │ └── Constraint │ │ │ └── MIPS_CPU.xdc │ └── sources_1 │ │ ├── bd │ │ └── MIPS_CPU │ │ │ ├── MIPS_CPU.bd │ │ │ ├── MIPS_CPU.bxml │ │ │ ├── hdl │ │ │ └── MIPS_CPU_wrapper.v │ │ │ ├── ip │ │ │ ├── MIPS_CPU_ALU32_0_0 │ │ │ │ ├── MIPS_CPU_ALU32_0_0.xci │ │ │ │ └── MIPS_CPU_ALU32_0_0.xml │ │ │ ├── MIPS_CPU_CONTROL_UNIT_0_0 │ │ │ │ ├── MIPS_CPU_CONTROL_UNIT_0_0.xci │ │ │ │ └── MIPS_CPU_CONTROL_UNIT_0_0.xml │ │ │ ├── MIPS_CPU_DATAPATH_0_0 │ │ │ │ ├── MIPS_CPU_DATAPATH_0_0.xci │ │ │ │ └── MIPS_CPU_DATAPATH_0_0.xml │ │ │ ├── MIPS_CPU_DATA_MEM_0_0 │ │ │ │ ├── MIPS_CPU_DATA_MEM_0_0.xci │ │ │ │ └── MIPS_CPU_DATA_MEM_0_0.xml │ │ │ ├── MIPS_CPU_KEY2INST_0_0 │ │ │ │ ├── MIPS_CPU_KEY2INST_0_0.xci │ │ │ │ └── MIPS_CPU_KEY2INST_0_0.xml │ │ │ ├── MIPS_CPU_REGFILE_0_0 │ │ │ │ ├── MIPS_CPU_REGFILE_0_0.xci │ │ │ │ └── MIPS_CPU_REGFILE_0_0.xml │ │ │ ├── MIPS_CPU_SHOW_ON_LED_0_0 │ │ │ │ ├── MIPS_CPU_SHOW_ON_LED_0_0.xci │ │ │ │ └── MIPS_CPU_SHOW_ON_LED_0_0.xml │ │ │ └── MIPS_CPU_clk_wiz_0_0 │ │ │ │ ├── MIPS_CPU_clk_wiz_0_0.xci │ │ │ │ └── MIPS_CPU_clk_wiz_0_0.xml │ │ │ └── ui │ │ │ └── bd_a462dba8.ui │ │ ├── imports │ │ └── hdl │ │ │ └── MIPS_CPU_wrapper.v │ │ └── ipshared │ │ └── dtysky │ │ ├── ALU32_v1_0 │ │ └── 074d7300 │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── ALU.v │ │ │ ├── LOGIC.v │ │ │ ├── MATH.v │ │ │ └── SHIFT.v │ │ ├── CONTROL_UNIT_v1_0 │ │ └── ff97bbaf │ │ │ └── sources_1 │ │ │ └── new │ │ │ └── CONTROL_UNIT.v │ │ ├── DATAPATH_v1_2 │ │ └── 37ca0665 │ │ │ └── DATAPATH.v │ │ ├── DATA_MEM_v1_0 │ │ └── fc23e26c │ │ │ └── DATA_MEM.v │ │ ├── KEY2INST_v1_0 │ │ └── 95ad72f6 │ │ │ └── sources_1 │ │ │ └── new │ │ │ └── KEY2INST.v │ │ ├── REGFILE_v1_0 │ │ └── 98f17ae9 │ │ │ └── sources_1 │ │ │ └── new │ │ │ └── REGFILE.v │ │ └── SHOW_ON_LED_v1_0 │ │ └── e457e91a │ │ └── SHOW_ON_LED.v │ ├── MIPS_CPU.xpr │ ├── vivado.jou │ └── vivado.log ├── Chapter_15 ├── FIR_HLS │ ├── fir.c │ ├── fir.h │ ├── fir_test.c │ ├── out.gold.dat │ ├── run_hls.tcl │ └── vivado_hls.log ├── HLS_doc │ ├── ug871-vivado-high-level-synthesis-tutorial.pdf │ ├── ug902-vivado-high-level-synthesis.pdf │ └── xapp890.zip └── vivado_hls.log ├── Chapter_16 └── Ball_Tracking │ ├── Basys3_BallTrack.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── Basys3_BallTrack.hw │ └── hw_1 │ │ ├── hw.xml │ │ └── xc7a35t_0 │ │ └── dashboard │ │ ├── hw_ila_1.xml │ │ └── hw_ila_2.xml │ ├── Basys3_BallTrack.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ └── vrs_config_8.xml │ ├── impl_1 │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── runme.log │ │ └── write_bitstream.pb │ └── synth_1 │ │ └── runme.log │ ├── Basys3_BallTrack.srcs │ ├── constrs_1 │ │ └── imports │ │ │ └── Constraint │ │ │ └── B3_Balltrack.xdc │ └── sources_1 │ │ ├── bd │ │ └── design_1 │ │ │ ├── design_1.bd │ │ │ ├── design_1.bxml │ │ │ ├── design_1_ooc.xdc │ │ │ ├── hdl │ │ │ ├── design_1.v │ │ │ └── design_1_wrapper.v │ │ │ ├── hw_handoff │ │ │ ├── design_1.hwh │ │ │ └── design_1_bd.tcl │ │ │ ├── ip │ │ │ ├── design_1_IICctrl_0_0 │ │ │ │ ├── design_1_IICctrl_0_0.xci │ │ │ │ ├── design_1_IICctrl_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_IICctrl_0_0.v │ │ │ ├── design_1_PWM_gen_0_0 │ │ │ │ ├── design_1_PWM_gen_0_0.xci │ │ │ │ ├── design_1_PWM_gen_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_PWM_gen_0_0.v │ │ │ ├── design_1_PWM_gen_1_0 │ │ │ │ ├── design_1_PWM_gen_1_0.xci │ │ │ │ ├── design_1_PWM_gen_1_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_PWM_gen_1_0.v │ │ │ ├── design_1_blk_mem_gen_0_0 │ │ │ │ ├── design_1_blk_mem_gen_0_0.xci │ │ │ │ ├── design_1_blk_mem_gen_0_0.xml │ │ │ │ ├── design_1_blk_mem_gen_0_0_ooc.xdc │ │ │ │ └── synth │ │ │ │ │ └── design_1_blk_mem_gen_0_0.vhd │ │ │ ├── design_1_cam_ov7670_ov7725_0_0 │ │ │ │ ├── design_1_cam_ov7670_ov7725_0_0.xci │ │ │ │ ├── design_1_cam_ov7670_ov7725_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_cam_ov7670_ov7725_0_0.v │ │ │ ├── design_1_clk_wiz_0_0 │ │ │ │ ├── design_1_clk_wiz_0_0.v │ │ │ │ ├── design_1_clk_wiz_0_0.xci │ │ │ │ ├── design_1_clk_wiz_0_0.xdc │ │ │ │ ├── design_1_clk_wiz_0_0.xml │ │ │ │ ├── design_1_clk_wiz_0_0_board.xdc │ │ │ │ ├── design_1_clk_wiz_0_0_clk_wiz.v │ │ │ │ └── design_1_clk_wiz_0_0_ooc.xdc │ │ │ ├── design_1_colorDetect_0_0 │ │ │ │ ├── design_1_colorDetect_0_0.xci │ │ │ │ ├── design_1_colorDetect_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_colorDetect_0_0.v │ │ │ ├── design_1_debounce_0_0 │ │ │ │ ├── design_1_debounce_0_0.xci │ │ │ │ ├── design_1_debounce_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_debounce_0_0.v │ │ │ ├── design_1_dilate_0_0 │ │ │ │ ├── design_1_dilate_0_0.xci │ │ │ │ ├── design_1_dilate_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_dilate_0_0.v │ │ │ ├── design_1_erode_0_0 │ │ │ │ ├── design_1_erode_0_0.xci │ │ │ │ ├── design_1_erode_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_erode_0_0.v │ │ │ ├── design_1_move_en_0_0 │ │ │ │ ├── design_1_move_en_0_0.xci │ │ │ │ ├── design_1_move_en_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_move_en_0_0.v │ │ │ ├── design_1_move_en_1_0 │ │ │ │ ├── design_1_move_en_1_0.xci │ │ │ │ ├── design_1_move_en_1_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_move_en_1_0.v │ │ │ ├── design_1_ov7725_regData_0_0 │ │ │ │ ├── design_1_ov7725_regData_0_0.xci │ │ │ │ ├── design_1_ov7725_regData_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_ov7725_regData_0_0.v │ │ │ ├── design_1_ram_read_0_0 │ │ │ │ ├── design_1_ram_read_0_0.xci │ │ │ │ ├── design_1_ram_read_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_ram_read_0_0.v │ │ │ ├── design_1_region_cut_0_0 │ │ │ │ ├── design_1_region_cut_0_0.xci │ │ │ │ ├── design_1_region_cut_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_region_cut_0_0.v │ │ │ ├── design_1_rgb2hsv_top_0_0 │ │ │ │ ├── design_1_rgb2hsv_top_0_0.xci │ │ │ │ ├── design_1_rgb2hsv_top_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_rgb2hsv_top_0_0.v │ │ │ ├── design_1_rgb565_rgb888_0_0 │ │ │ │ ├── design_1_rgb565_rgb888_0_0.xci │ │ │ │ ├── design_1_rgb565_rgb888_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_rgb565_rgb888_0_0.v │ │ │ ├── design_1_rgb888_rgb565_0_0 │ │ │ │ ├── design_1_rgb888_rgb565_0_0.xci │ │ │ │ ├── design_1_rgb888_rgb565_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_rgb888_rgb565_0_0.v │ │ │ ├── design_1_servo_ctrl_0_0 │ │ │ │ ├── design_1_servo_ctrl_0_0.xci │ │ │ │ ├── design_1_servo_ctrl_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_servo_ctrl_0_0.v │ │ │ ├── design_1_vga_0_0 │ │ │ │ ├── design_1_vga_0_0.xci │ │ │ │ ├── design_1_vga_0_0.xml │ │ │ │ └── synth │ │ │ │ │ └── design_1_vga_0_0.v │ │ │ ├── design_1_xadc_0_0 │ │ │ │ ├── design_1_xadc_0_0.xci │ │ │ │ ├── design_1_xadc_0_0.xml │ │ │ │ ├── ip │ │ │ │ │ └── xadc_wiz_0 │ │ │ │ │ │ ├── xadc_wiz_0.v │ │ │ │ │ │ ├── xadc_wiz_0.xci │ │ │ │ │ │ ├── xadc_wiz_0.xdc │ │ │ │ │ │ ├── xadc_wiz_0.xml │ │ │ │ │ │ └── xadc_wiz_0_ooc.xdc │ │ │ │ └── synth │ │ │ │ │ └── design_1_xadc_0_0.v │ │ │ └── design_1_xlconstant_0_0 │ │ │ │ ├── design_1_xlconstant_0_0.xci │ │ │ │ ├── design_1_xlconstant_0_0.xml │ │ │ │ └── sim │ │ │ │ └── design_1_xlconstant_0_0.v │ │ │ └── ui │ │ │ └── bd_1f5defd0.ui │ │ ├── imports │ │ └── hdl │ │ │ └── design_1_wrapper.v │ │ └── ipshared │ │ └── xilinx.com │ │ ├── IICctrl_v1_0 │ │ └── 6647e60a │ │ │ └── sources_1 │ │ │ └── imports │ │ │ └── src │ │ │ ├── I2C_Controller.v │ │ │ └── IICctrl.v │ │ ├── PWM_gen_v1_0 │ │ └── d255dbd9 │ │ │ └── sources_1 │ │ │ └── new │ │ │ └── PWM_gen.v │ │ ├── blk_mem_gen_v8_2 │ │ └── 38e122e0 │ │ │ └── hdl │ │ │ ├── blk_mem_gen_v8_2.vhd │ │ │ └── blk_mem_gen_v8_2_vhsyn_rfs.vhd │ │ ├── cam_ov7670_ov7725_v1_0 │ │ └── 582a8f8b │ │ │ └── cam_ov7670_ov7725.v │ │ ├── colorDetect_v1_0 │ │ └── 85fe1c07 │ │ │ ├── BW.v │ │ │ ├── center.v │ │ │ ├── colorDetect.v │ │ │ ├── new │ │ │ └── weight_cal.v │ │ │ └── render.v │ │ ├── debounce_v1_0 │ │ └── d86dd21c │ │ │ └── sources_1 │ │ │ └── new │ │ │ └── debounce.v │ │ ├── dilate_v1_0 │ │ └── 6bb2fbbc │ │ │ └── dilate.v │ │ ├── erode_v1_0 │ │ └── 5a138dcf │ │ │ └── erode.v │ │ ├── move_en_v1_0 │ │ └── 835a17c9 │ │ │ └── move_en.v │ │ ├── ov7725_regData_v1_0 │ │ └── 4367a5ed │ │ │ └── ov7725_regData.v │ │ ├── ram_read_v1_0 │ │ └── f389a5e2 │ │ │ └── ram_read.v │ │ ├── region_cut_v1_0 │ │ └── c1f7ec3e │ │ │ └── region_cut.v │ │ ├── rgb2hsv_top_v1_0 │ │ └── 2f640eb5 │ │ │ └── rgb2hsv_top.v │ │ ├── rgb565_rgb888_v1_0 │ │ └── 61bec671 │ │ │ └── rgb565_rgb888.v │ │ ├── rgb888_rgb565_v1_0 │ │ └── 46b53b97 │ │ │ └── rgb888_rgb565.v │ │ ├── servo_ctrl_v1_0 │ │ └── ab98f566 │ │ │ ├── imports │ │ │ └── servo_ip │ │ │ │ ├── pwm_gen_x.v │ │ │ │ └── pwm_gen_y.v │ │ │ └── new │ │ │ └── servo_ctrl.v │ │ ├── vga_v1_0 │ │ └── 4793d6e9 │ │ │ └── vga.v │ │ ├── xadc_v1_0 │ │ └── eb84d9bf │ │ │ └── new │ │ │ └── xadc.v │ │ └── xlconstant_v1_1 │ │ └── 36911fd5 │ │ └── xlconstant.v │ ├── Basys3_BallTrack.xpr │ └── IP_Catalog │ ├── XUP_ColorDetect_V1.0.zip │ ├── XUP_ColorDetect_V1.0 │ └── XUP_ColorDetect_V1.0 │ │ ├── BW.v │ │ ├── center.v │ │ ├── colorDetect.v │ │ ├── component.xml │ │ ├── new │ │ └── weight_cal.v │ │ ├── render.v │ │ └── xgui │ │ └── colorDetect_v1_0.tcl │ ├── XUP_Dilate_V1.0.zip │ ├── XUP_Dilate_V1.0 │ └── XUP_Dilate_V1.0 │ │ ├── component.xml │ │ ├── dilate.v │ │ └── xgui │ │ └── dilate_v1_0.tcl │ ├── XUP_Erode_V1.0.zip │ ├── XUP_Erode_V1.0 │ └── XUP_Erode_V1.0 │ │ ├── component.xml │ │ ├── erode.v │ │ └── xgui │ │ └── erode_v1_0.tcl │ ├── XUP_IICctrl_1.0.zip │ ├── XUP_IICctrl_1.0 │ ├── component.xml │ ├── sim_1 │ │ └── new │ │ │ └── iic_tb.v │ ├── sources_1 │ │ └── imports │ │ │ └── src │ │ │ ├── I2C_Controller.v │ │ │ └── IICctrl.v │ └── xgui │ │ └── IICctrl_v1_0.tcl │ ├── XUP_PWM_gen_1.0.zip │ ├── XUP_PWM_gen_1.0 │ ├── component.xml │ ├── sim_1 │ │ └── new │ │ │ └── pwm_tb.v │ ├── sources_1 │ │ └── new │ │ │ └── PWM_gen.v │ └── xgui │ │ └── PWM_gen_v1_0.tcl │ ├── XUP_RGB16_24_V1.0.zip │ ├── XUP_RGB16_24_V1.0 │ └── XUP_RGB16_24_V1.0 │ │ ├── component.xml │ │ ├── rgb565_rgb888.v │ │ └── xgui │ │ └── rgb565_rgb888_v1_0.tcl │ ├── XUP_RGB24_16_V1.0.zip │ ├── XUP_RGB24_16_V1.0 │ └── XUP_RGB24_16_V1.0 │ │ ├── component.xml │ │ ├── rgb888_rgb565.v │ │ └── xgui │ │ └── rgb888_rgb565_v1_0.tcl │ ├── XUP_cam_ov7670_ov7725_1.0.zip │ ├── XUP_cam_ov7670_ov7725_1.0 │ ├── cam_ov7670_ov7725.v │ ├── component.xml │ └── xgui │ │ └── cam_ov7670_ov7725_v1_0.tcl │ ├── XUP_debounce_1.0.zip │ ├── XUP_debounce_1.0 │ ├── component.xml │ ├── sim_1 │ │ └── new │ │ │ └── debounce_tb.v │ ├── sources_1 │ │ └── new │ │ │ └── debounce.v │ └── xgui │ │ └── debounce_v1_0.tcl │ ├── XUP_move_en_1.0.zip │ ├── XUP_move_en_1.0 │ ├── component.xml │ ├── move_en.v │ └── xgui │ │ └── move_en_v1_0.tcl │ ├── XUP_ov7725_regData_1.0.zip │ ├── XUP_ov7725_regData_1.0 │ ├── component.xml │ ├── ov7725_regData.v │ └── xgui │ │ └── ov7725_regData_v1_0.tcl │ ├── XUP_ram_read_1.0.zip │ ├── XUP_ram_read_1.0 │ ├── component.xml │ ├── ram_read.v │ └── xgui │ │ └── ram_read_v1_0.tcl │ ├── XUP_region_cut_1.0.zip │ ├── XUP_region_cut_1.0 │ ├── component.xml │ ├── region_cut.v │ └── xgui │ │ └── region_cut_v1_0.tcl │ ├── XUP_servo_ctrl_1.0.zip │ ├── XUP_servo_ctrl_1.0 │ ├── component.xml │ ├── imports │ │ └── servo_ip │ │ │ ├── pwm_gen_x.v │ │ │ └── pwm_gen_y.v │ ├── new │ │ └── servo_ctrl.v │ └── xgui │ │ └── servo_ctrl_v1_0.tcl │ ├── XUP_vga_1.0.zip │ ├── XUP_vga_1.0 │ ├── component.xml │ ├── vga.v │ └── xgui │ │ └── vga_v1_0.tcl │ ├── XUP_xadc_1.0.zip │ ├── XUP_xadc_1.0 │ ├── component.xml │ ├── ip │ │ └── xadc_wiz_0 │ │ │ ├── design.txt │ │ │ ├── doc │ │ │ └── xadc_wiz_v3_3_changelog.txt │ │ │ ├── xadc_wiz_0.dcp │ │ │ ├── xadc_wiz_0.v │ │ │ ├── xadc_wiz_0.veo │ │ │ ├── xadc_wiz_0.vho │ │ │ ├── xadc_wiz_0.xci │ │ │ ├── xadc_wiz_0.xdc │ │ │ ├── xadc_wiz_0.xml │ │ │ ├── xadc_wiz_0 │ │ │ └── simulation │ │ │ │ └── timing │ │ │ │ └── design.txt │ │ │ ├── xadc_wiz_0_ooc.xdc │ │ │ ├── xadc_wiz_0_sim_netlist.v │ │ │ ├── xadc_wiz_0_sim_netlist.vhdl │ │ │ ├── xadc_wiz_0_stub.v │ │ │ └── xadc_wiz_0_stub.vhdl │ ├── new │ │ └── xadc.v │ └── xgui │ │ └── xadc_v1_0.tcl │ ├── xup_rgb2hsv_top_1.0.zip │ └── xup_rgb2hsv_top_1.0 │ ├── component.xml │ ├── rgb2hsv_top.v │ └── xgui │ └── rgb2hsv_top_v1_0.tcl ├── Chapter_2 ├── andDemo │ └── andDemo.v └── fullAdder │ ├── fullAdder.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── fullAdder.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ └── vrs_config_3.xml │ └── synth_1 │ │ └── runme.log │ ├── fullAdder.srcs │ └── sources_1 │ │ └── new │ │ ├── fullAdder.v │ │ └── top.v │ ├── fullAdder.v │ └── fullAdder.xpr ├── Chapter_3 ├── Loop_Statement │ ├── Loop_Statement.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── Loop_Statement.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_10.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ ├── vrs_config_7.xml │ │ │ ├── vrs_config_8.xml │ │ │ └── vrs_config_9.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── Loop_Statement.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── mult_for.v │ │ │ ├── mult_repeat.v │ │ │ └── mult_while.v │ └── Loop_Statement.xpr ├── and_block_assign │ ├── and_block_assign.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── and_block_assign.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── and_block_assign.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ └── and_block_assign.v │ └── and_block_assign.xpr ├── conditional statement │ ├── conditional statement.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── conditional statement.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ └── vrs_config_4.xml │ │ └── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── prio_encoder_casez.dcp │ │ │ ├── prio_encoder_casez.tcl │ │ │ ├── prio_encoder_casez.vds │ │ │ ├── prio_encoder_casez_utilization_synth.pb │ │ │ ├── prio_encoder_casez_utilization_synth.rpt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── conditional statement.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── decoder_2_4_case.v │ │ │ ├── prio_encoder_case.v │ │ │ ├── prio_encoder_casez.v │ │ │ └── prio_encoder_if.v │ └── conditional statement.xpr ├── constant_parameter │ ├── constant_parameter.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── constant_parameter.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ └── vrs_config_5.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── constant_parameter.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── adder_carry_hard_lit.v │ │ │ ├── adder_carry_loacl_par.v │ │ │ ├── adder_carry_para.v │ │ │ └── adder_insta.v │ └── constant_parameter.xpr ├── eq1_always │ ├── eq1_always.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── eq1_always.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── eq1_always.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ └── eq1_always.v │ └── eq1_always.xpr └── example │ ├── example.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── example.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ └── synth_1 │ │ └── runme.log │ ├── example.srcs │ └── sources_1 │ │ └── new │ │ ├── bin_bcd4.v │ │ ├── bin_bcd8.v │ │ ├── comp_1.v │ │ ├── comp_N.v │ │ ├── decode_3_8.v │ │ ├── encode_8_3.v │ │ ├── hex_7seg.v │ │ ├── mux41_case.v │ │ ├── mux41_if.v │ │ └── prio_encode_8_3.v │ ├── example.xpr │ ├── vivado.jou │ └── vivado.log ├── Chapter_4 ├── example │ ├── example.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── example.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ └── vrs_config_7.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── example.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── glbl.v │ │ │ ├── scan_led_hex_disp_test_vlog.prj │ │ │ └── xvlog.pb │ ├── example.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── scan_led_disp.v │ │ │ ├── scan_led_hex_disp.v │ │ │ └── scan_led_hex_disp_test.v │ └── example.xpr ├── example_2 │ ├── example_2.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── example_2.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ └── vrs_config_5.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── example_2.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── scan_led_hex_disp.v │ │ │ ├── stop_watch.v │ │ │ └── stop_watch_test.v │ └── example_2.xpr └── sequential logic │ ├── sequential logic.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── sequential logic.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ └── synth_1 │ │ └── runme.log │ ├── sequential logic.srcs │ └── sources_1 │ │ └── new │ │ ├── counter_mod_m.v │ │ ├── counter_sim_bin_N.v │ │ ├── counter_univ_bin_N.v │ │ ├── dff.v │ │ ├── dff_reset.v │ │ ├── dff_reset_en_1seg.v │ │ ├── dff_reset_en_2seg.v │ │ ├── latch_1.v │ │ ├── latch_reset_1.v │ │ ├── latch_reset_2.v │ │ ├── reg_1.v │ │ ├── reg_N.v │ │ ├── reg_file.v │ │ ├── shift_reg8.v │ │ └── univ_shift_reg.v │ └── sequential logic.xpr ├── Chapter_5 ├── FSM │ ├── FSM.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── FSM.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ └── vrs_config_2.xml │ │ └── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── fsm_eg_2_seg.dcp │ │ │ ├── fsm_eg_2_seg.tcl │ │ │ ├── fsm_eg_2_seg.vds │ │ │ ├── fsm_eg_2_seg_utilization_synth.pb │ │ │ ├── fsm_eg_2_seg_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.log │ │ │ ├── runme.sh │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── FSM.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── fsm_eg_2_seg.v │ │ │ └── fsm_eg_mult_seg.v │ └── FSM.xpr ├── example_1 │ ├── example_1.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── example_1.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ └── vrs_config_2.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── example_1.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── seg_det_moore.v │ │ │ └── seq_det_mealy.v │ └── example_1.xpr ├── example_2 │ ├── example_2.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── example_2.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ └── vrs_config_6.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── example_2.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── adc0809.v │ │ │ └── adc0809_2.v │ └── example_2.xpr └── example_3 │ ├── example_3.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── example_3.runs │ ├── .jobs │ │ └── vrs_config_1.xml │ └── synth_1 │ │ └── runme.log │ ├── example_3.srcs │ └── sources_1 │ │ └── new │ │ └── db_fsm.v │ └── example_3.xpr ├── Chapter_7 ├── 74LS00 │ ├── 74LS00.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── 74LS00.runs │ │ └── .jobs │ │ │ └── vrs_config_1.xml │ ├── 74LS00.srcs │ │ └── sources_1 │ │ │ ├── ip │ │ │ └── four_2_input_nand_gate_0 │ │ │ │ ├── four_2_input_nand_gate_0.xci │ │ │ │ └── four_2_input_nand_gate_0.xml │ │ │ └── new │ │ │ ├── component.xml │ │ │ ├── four_2_input_nand.v │ │ │ ├── xgui │ │ │ └── four_2_input_nand_gate_v1_0.tcl │ │ │ └── xilinx.com_XUP_four_2_input_nand_gate_1.0.zip │ └── 74LS00.xpr ├── and_gate.v ├── ip_repo │ ├── and_gate_AXI4_1.0 │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── drivers │ │ │ └── and_gate_AXI4_v1_0 │ │ │ │ ├── data │ │ │ │ ├── and_gate_AXI4.mdd │ │ │ │ └── and_gate_AXI4.tcl │ │ │ │ └── src │ │ │ │ ├── Makefile │ │ │ │ ├── and_gate_AXI4.c │ │ │ │ ├── and_gate_AXI4.h │ │ │ │ └── and_gate_AXI4_selftest.c │ │ ├── example_designs │ │ │ ├── bfm_design │ │ │ │ ├── and_gate_AXI4_v1_0_tb.v │ │ │ │ └── design.tcl │ │ │ └── debug_hw_design │ │ │ │ ├── and_gate_AXI4_v1_0_hw_test.tcl │ │ │ │ └── design.tcl │ │ ├── hdl │ │ │ ├── and_gate_AXI4_v1_0.v │ │ │ └── and_gate_AXI4_v1_0_S00_AXI.v │ │ └── xgui │ │ │ └── and_gate_AXI4_v1_0.tcl │ ├── edit_and_gate_AXI4_v1_0.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ └── webtalk_pa.xml │ ├── edit_and_gate_AXI4_v1_0.hw │ │ └── edit_and_gate_AXI4_v1_0.lpr │ └── edit_and_gate_AXI4_v1_0.xpr └── ip_repo_new │ ├── and_gate_1.0.zip │ └── and_gate_1.0 │ ├── Package_IP_new.srcs │ ├── sim_1 │ │ └── new │ │ │ └── and_gate_tb.v │ └── sources_1 │ │ └── new │ │ └── and_gate.v │ ├── component.xml │ └── xgui │ └── and_gate_v1_0.tcl ├── Chapter_8 ├── I2C │ ├── I2C.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── I2C.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── elaborate.bat │ │ │ ├── elaborate.log │ │ │ ├── glbl.v │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── tb.tcl │ │ │ ├── tb_behav.wdb │ │ │ ├── tb_vlog.prj │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── tb_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsimk.exe │ │ │ │ └── xsimkernel.log │ │ │ ├── xil_defaultlib │ │ │ │ ├── glbl.sdb │ │ │ │ └── tb.sdb │ │ │ └── xsim.svtype │ │ │ └── xvlog.pb │ ├── I2C.srcs │ │ └── sim_1 │ │ │ └── new │ │ │ └── tb.v │ └── I2C.xpr ├── SPI │ ├── SPI.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── SPI.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ └── vrs_config_2.xml │ │ └── synth_1 │ │ │ └── runme.log │ ├── SPI.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── elaborate.bat │ │ │ ├── elaborate.log │ │ │ ├── glbl.v │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── tb.tcl │ │ │ ├── tb_behav.wdb │ │ │ ├── tb_vlog.prj │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── tb_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsimk.exe │ │ │ │ └── xsimkernel.log │ │ │ ├── xil_defaultlib │ │ │ │ ├── glbl.sdb │ │ │ │ ├── spi_master.sdb │ │ │ │ └── tb.sdb │ │ │ └── xsim.svtype │ │ │ └── xvlog.pb │ ├── SPI.srcs │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── tb.v │ │ └── sources_1 │ │ │ └── new │ │ │ └── spi_master.v │ ├── SPI.xpr │ └── readme.txt ├── ps2_keyboard │ ├── ps2_keyboard.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ └── webtalk_pa.xml │ ├── ps2_keyboard.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ └── ps2_keyboard.v │ └── ps2_keyboard.xpr └── uart │ ├── uart.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── uart.runs │ ├── .jobs │ │ └── vrs_config_1.xml │ └── synth_1 │ │ └── runme.log │ ├── uart.srcs │ └── sources_1 │ │ └── new │ │ ├── clk_div.v │ │ ├── uart_rx.v │ │ ├── uart_top.v │ │ └── uart_tx.v │ └── uart.xpr ├── Chapter_9 ├── DDR2 │ ├── DDR2.cache │ │ ├── ip │ │ │ ├── 20745493 │ │ │ │ ├── 20745493.xci │ │ │ │ └── i_xsdbm.dcp │ │ │ └── c40b3d83 │ │ │ │ ├── c40b3d83.xci │ │ │ │ └── i_ila.dcp │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── DDR2.hw │ │ └── hw_1 │ │ │ ├── hw.xml │ │ │ ├── wave │ │ │ └── hw_ila_data_1 │ │ │ │ ├── hw_ila_data_1.wcfg │ │ │ │ └── hw_ila_data_1.wdb │ │ │ └── xc7a100t_0 │ │ │ └── dashboard │ │ │ └── hw_ila_1.xml │ ├── DDR2.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_2.xml │ │ │ └── vrs_config_3.xml │ │ ├── impl_1 │ │ │ ├── debug_nets.ltx │ │ │ ├── init_design.pb │ │ │ ├── opt_design.pb │ │ │ ├── place_design.pb │ │ │ ├── route_design.pb │ │ │ ├── runme.log │ │ │ └── write_bitstream.pb │ │ └── synth_1 │ │ │ └── runme.log │ ├── DDR2.srcs │ │ ├── constrs_1 │ │ │ └── imports │ │ │ │ └── Constraint │ │ │ │ └── ddr.xdc │ │ └── sources_1 │ │ │ ├── imports │ │ │ └── HDL_source │ │ │ │ ├── example_top.v │ │ │ │ └── user_ddr.v │ │ │ └── ip │ │ │ ├── clk_wiz_0 │ │ │ ├── clk_wiz_0.xci │ │ │ └── clk_wiz_0.xml │ │ │ └── mig_7series_0 │ │ │ ├── mig_7series_0.veo │ │ │ ├── mig_7series_0.xci │ │ │ ├── mig_7series_0.xml │ │ │ ├── mig_7series_0 │ │ │ ├── datasheet.txt │ │ │ ├── docs │ │ │ │ └── phy_only_support_readme.txt │ │ │ ├── example_design │ │ │ │ ├── log.txt │ │ │ │ ├── par │ │ │ │ │ ├── example_top.xdc │ │ │ │ │ └── readme.txt │ │ │ │ ├── rtl │ │ │ │ │ ├── example_top.v │ │ │ │ │ └── traffic_gen │ │ │ │ │ │ ├── mig_7series_v2_3_afifo.v │ │ │ │ │ │ ├── mig_7series_v2_3_cmd_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_cmd_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_data_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_init_mem_pattern_ctr.v │ │ │ │ │ │ ├── mig_7series_v2_3_memc_flow_vcontrol.v │ │ │ │ │ │ ├── mig_7series_v2_3_memc_traffic_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_rd_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_read_data_path.v │ │ │ │ │ │ ├── mig_7series_v2_3_read_posted_fifo.v │ │ │ │ │ │ ├── mig_7series_v2_3_s7ven_data_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_tg_prbs_gen.v │ │ │ │ │ │ ├── mig_7series_v2_3_tg_status.v │ │ │ │ │ │ ├── mig_7series_v2_3_traffic_gen_top.v │ │ │ │ │ │ ├── mig_7series_v2_3_vio_init_pattern_bram.v │ │ │ │ │ │ ├── mig_7series_v2_3_wr_data_gen.v │ │ │ │ │ │ └── mig_7series_v2_3_write_data_path.v │ │ │ │ └── sim │ │ │ │ │ ├── ddr2_model.v │ │ │ │ │ ├── ddr2_model_parameters.vh │ │ │ │ │ ├── ies_run.sh │ │ │ │ │ ├── readme.txt │ │ │ │ │ ├── sim.do │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── vcs_run.sh │ │ │ │ │ ├── wiredly.v │ │ │ │ │ ├── xsim_files.prj │ │ │ │ │ ├── xsim_options.tcl │ │ │ │ │ └── xsim_run.bat │ │ │ ├── mig.prj │ │ │ └── user_design │ │ │ │ ├── constraints │ │ │ │ ├── mig_7series_0.xdc │ │ │ │ └── mig_7series_0_ooc.xdc │ │ │ │ ├── log.txt │ │ │ │ └── rtl │ │ │ │ ├── clocking │ │ │ │ ├── mig_7series_v2_3_clk_ibuf.v │ │ │ │ ├── mig_7series_v2_3_infrastructure.v │ │ │ │ ├── mig_7series_v2_3_iodelay_ctrl.v │ │ │ │ └── mig_7series_v2_3_tempmon.v │ │ │ │ ├── controller │ │ │ │ ├── mig_7series_v2_3_arb_mux.v │ │ │ │ ├── mig_7series_v2_3_arb_row_col.v │ │ │ │ ├── mig_7series_v2_3_arb_select.v │ │ │ │ ├── mig_7series_v2_3_bank_cntrl.v │ │ │ │ ├── mig_7series_v2_3_bank_common.v │ │ │ │ ├── mig_7series_v2_3_bank_compare.v │ │ │ │ ├── mig_7series_v2_3_bank_mach.v │ │ │ │ ├── mig_7series_v2_3_bank_queue.v │ │ │ │ ├── mig_7series_v2_3_bank_state.v │ │ │ │ ├── mig_7series_v2_3_col_mach.v │ │ │ │ ├── mig_7series_v2_3_mc.v │ │ │ │ ├── mig_7series_v2_3_rank_cntrl.v │ │ │ │ ├── mig_7series_v2_3_rank_common.v │ │ │ │ ├── mig_7series_v2_3_rank_mach.v │ │ │ │ └── mig_7series_v2_3_round_robin_arb.v │ │ │ │ ├── ecc │ │ │ │ ├── mig_7series_v2_3_ecc_buf.v │ │ │ │ ├── mig_7series_v2_3_ecc_dec_fix.v │ │ │ │ ├── mig_7series_v2_3_ecc_gen.v │ │ │ │ ├── mig_7series_v2_3_ecc_merge_enc.v │ │ │ │ └── mig_7series_v2_3_fi_xor.v │ │ │ │ ├── ip_top │ │ │ │ ├── mig_7series_v2_3_mem_intfc.v │ │ │ │ └── mig_7series_v2_3_memc_ui_top_std.v │ │ │ │ ├── mig_7series_0.v │ │ │ │ ├── mig_7series_0_mig.v │ │ │ │ ├── mig_7series_0_mig_sim.v │ │ │ │ ├── phy │ │ │ │ ├── mig_7series_v2_3_ddr_byte_group_io.v │ │ │ │ ├── mig_7series_v2_3_ddr_byte_lane.v │ │ │ │ ├── mig_7series_v2_3_ddr_calib_top.v │ │ │ │ ├── mig_7series_v2_3_ddr_if_post_fifo.v │ │ │ │ ├── mig_7series_v2_3_ddr_mc_phy.v │ │ │ │ ├── mig_7series_v2_3_ddr_mc_phy_wrapper.v │ │ │ │ ├── mig_7series_v2_3_ddr_of_pre_fifo.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_4lanes.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_dqs_found_cal.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_dqs_found_cal_hr.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_init.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ocd_cntlr.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ocd_data.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ocd_edge.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ocd_lim.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ocd_mux.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_ocd_samp.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_oclkdelay_cal.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_prbs_rdlvl.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_rdlvl.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_tempmon.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_top.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_wrcal.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_wrlvl.v │ │ │ │ ├── mig_7series_v2_3_ddr_phy_wrlvl_off_delay.v │ │ │ │ ├── mig_7series_v2_3_ddr_prbs_gen.v │ │ │ │ ├── mig_7series_v2_3_poc_cc.v │ │ │ │ ├── mig_7series_v2_3_poc_edge_store.v │ │ │ │ ├── mig_7series_v2_3_poc_meta.v │ │ │ │ ├── mig_7series_v2_3_poc_pd.v │ │ │ │ ├── mig_7series_v2_3_poc_tap_base.v │ │ │ │ └── mig_7series_v2_3_poc_top.v │ │ │ │ └── ui │ │ │ │ ├── mig_7series_v2_3_ui_cmd.v │ │ │ │ ├── mig_7series_v2_3_ui_rd_data.v │ │ │ │ ├── mig_7series_v2_3_ui_top.v │ │ │ │ └── mig_7series_v2_3_ui_wr_data.v │ │ │ ├── mig_7series_0_xmdf.tcl │ │ │ ├── mig_a.prj │ │ │ ├── tcl.log │ │ │ ├── xil_txt.in │ │ │ └── xil_txt.out │ └── DDR2.xpr ├── fifo │ ├── fifo.cache │ │ └── wt │ │ │ ├── java_command_handlers.wdf │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── fifo.runs │ │ ├── .jobs │ │ │ └── vrs_config_1.xml │ │ └── fifo_generator_0_synth_1 │ │ │ └── vivado.pb │ ├── fifo.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ ├── compile.bat │ │ │ ├── compile.log │ │ │ ├── elaborate.bat │ │ │ ├── elaborate.log │ │ │ ├── glbl.v │ │ │ ├── simulate.bat │ │ │ ├── simulate.log │ │ │ ├── tb.tcl │ │ │ ├── tb_behav.wdb │ │ │ ├── tb_vhdl.prj │ │ │ ├── tb_vlog.prj │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── fifo_generator_v12_0 │ │ │ │ ├── axi_reg_slice.vdb │ │ │ │ ├── bin_cntr.vdb │ │ │ │ ├── bram_fifo_rstlogic.vdb │ │ │ │ ├── bram_sync_reg.vdb │ │ │ │ ├── builtin_extdepth.vdb │ │ │ │ ├── builtin_extdepth_low_latency.vdb │ │ │ │ ├── builtin_extdepth_v6.vdb │ │ │ │ ├── builtin_prim.vdb │ │ │ │ ├── builtin_prim_v6.vdb │ │ │ │ ├── builtin_top.vdb │ │ │ │ ├── builtin_top_v6.vdb │ │ │ │ ├── clk_x_pntrs_builtin.vdb │ │ │ │ ├── delay.vdb │ │ │ │ ├── fifo_generator_top.vdb │ │ │ │ ├── fifo_generator_v12_0.vdb │ │ │ │ ├── fifo_generator_v12_0_axic_reg_slice.vdb │ │ │ │ ├── fifo_generator_v12_0_bhv_as.vdb │ │ │ │ ├── fifo_generator_v12_0_bhv_preload0.vdb │ │ │ │ ├── fifo_generator_v12_0_bhv_ss.vdb │ │ │ │ ├── fifo_generator_v12_0_builtin.vdb │ │ │ │ ├── fifo_generator_v12_0_conv.vdb │ │ │ │ ├── fifo_generator_v12_0_pkg.vdb │ │ │ │ ├── fifo_generator_v12_0_synth.vdb │ │ │ │ ├── fifo_generator_vhdl_beh.vdb │ │ │ │ ├── input_blk.vdb │ │ │ │ ├── logic_builtin.vdb │ │ │ │ ├── output_blk.vdb │ │ │ │ ├── rd_pe_as.vdb │ │ │ │ ├── rd_pe_ss.vdb │ │ │ │ ├── reset_blk_ramfifo.vdb │ │ │ │ ├── reset_builtin.vdb │ │ │ │ ├── shft_ram.vdb │ │ │ │ ├── shft_wrapper.vdb │ │ │ │ ├── synchronizer_ff.vdb │ │ │ │ ├── wr_pf_as.vdb │ │ │ │ └── wr_pf_ss.vdb │ │ │ ├── tb_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsimk.exe │ │ │ │ └── xsimkernel.log │ │ │ ├── xil_defaultlib │ │ │ │ ├── fifo_generator_0.vdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── tb.sdb │ │ │ │ └── top.sdb │ │ │ └── xsim.svtype │ │ │ ├── xvhdl.pb │ │ │ └── xvlog.pb │ ├── fifo.srcs │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── tb.v │ │ └── sources_1 │ │ │ ├── ip │ │ │ └── fifo_generator_0 │ │ │ │ ├── fifo_generator_0.dcp │ │ │ │ ├── fifo_generator_0.xci │ │ │ │ ├── fifo_generator_0.xml │ │ │ │ ├── fifo_generator_0_funcsim.v │ │ │ │ ├── fifo_generator_0_funcsim.vhdl │ │ │ │ ├── fifo_generator_0_stub.v │ │ │ │ └── fifo_generator_0_stub.vhdl │ │ │ └── new │ │ │ └── top.v │ └── fifo.xpr └── ram │ ├── ram.cache │ └── wt │ │ ├── java_command_handlers.wdf │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml │ ├── ram.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ └── vrs_config_2.xml │ └── synth_1 │ │ └── runme.log │ ├── ram.srcs │ └── sources_1 │ │ └── new │ │ ├── xilinx_dual_port_ram_async.v │ │ └── xilinx_one_port_ram_sync.v │ └── ram.xpr ├── README.md ├── board_constarints ├── Basys3 │ ├── Cahpter_11 │ │ └── VGA │ │ │ └── pin.xdc │ ├── Chapter_10 │ │ └── OLED │ │ │ └── PIN.xdc │ ├── Chapter_12 │ │ └── Digital_camera │ │ │ └── cam_bram_vga.xdc │ ├── Chapter_13 │ │ └── Digital_Clock │ │ │ └── Digital_Clock.xdc │ ├── Chapter_14 │ │ └── RISC │ │ │ └── MIPS_CPU.xdc │ ├── Chapter_16 │ │ └── Ball_tracking │ │ │ └── Balltrack.xdc │ └── Chapter_9 │ │ └── DDR │ │ └── ddr.xdc └── EGO1 │ ├── Chapter_10 │ ├── OLED │ │ └── PIN.xdc │ └── lcd_1602 │ │ └── LCD1602.xdc │ ├── Chapter_11 │ └── top.xdc │ ├── Chapter_12 │ └── Digital_camera │ │ └── cam_bram_vga.xdc │ ├── Chapter_13 │ └── Digital_Clock │ │ └── Digital_Clock.xdc │ ├── Chapter_14 │ └── MIPS_CPU.xdc │ ├── Chapter_16 │ └── Balltrack.xdc │ └── Chapter_8 │ ├── ps2_keyboard │ ├── PS2.xdc │ └── 实验说明.txt │ └── uart │ └── UART.xdc └── introduction.txt /Chapter_10/LCD_1602/LCD_1602.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 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