├── .gitignore ├── .gitattributes ├── doc └── README.pdf ├── src ├── mips_computer.qws ├── shiftleft.vhd ├── beqctrl.vhd ├── signext.vhd ├── jmpmerge.vhd ├── mux2_sl.vhd ├── mux2.vhd ├── intvec.vhd ├── outputctrl.vhd ├── mux4.vhd ├── ioselector.vhd ├── flopr.vhd ├── resetwav.vhd ├── flopenr.vhd ├── uart_clk.vhd ├── clkslower.vhd ├── memory.vhd ├── alu.vhd ├── regfile.vhd ├── aludec.vhd ├── readinput.vhd ├── mips_computer.qpf ├── iomemory.vhd ├── resetwav.bsf ├── sl2.bsf ├── clkslower.bsf ├── signext.bsf ├── intvec.bsf ├── outputctrl.bsf ├── jmpmerge.bsf ├── aludec.bsf ├── .gitignore ├── mux2_sl.bsf ├── beqctrl.bsf ├── uart_clk.bsf ├── ioselector.bsf ├── digtube.vhd ├── mux2.bsf ├── dmem.bsf ├── flopenr.bsf ├── imem.bsf ├── iomemory.bsf ├── uart_rx.vhd ├── readinput.bsf ├── digtube.bsf ├── regfile.bsf ├── imem.vhd ├── mips_fpga.vhd ├── fsm.vhd ├── mips_fpga.bsf ├── fsm.bsf ├── mips_computer.qsf ├── datapath.bsf ├── mips_computer.vhd ├── mips_computer.bsf ├── datapath.vhd ├── mips_fpga.bdf └── mips_computer.bdf ├── README.md └── LICENSE /.gitignore: -------------------------------------------------------------------------------- 1 | /x/* 2 | /doc/*.doc 3 | /doc/*.docx 4 | /doc/*.tmp -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /doc/README.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xz-liu/mips-computer/HEAD/doc/README.pdf -------------------------------------------------------------------------------- /src/mips_computer.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xz-liu/mips-computer/HEAD/src/mips_computer.qws -------------------------------------------------------------------------------- /src/shiftleft.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | entity sl2 is -- shift left by 2 3 | port(a: in STD_LOGIC_VECTOR(31 downto 0); 4 | y: out STD_LOGIC_VECTOR(31 downto 0)); 5 | end; 6 | architecture behave of sl2 is 7 | begin 8 | y <= a(29 downto 0) & "00"; 9 | end; -------------------------------------------------------------------------------- /src/beqctrl.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | 3 | entity beqctrl is -- two-input multiplexer 4 | port(zero,branch,pcwrite:in std_logic; 5 | pcen :out std_logic 6 | ); 7 | end; 8 | architecture behave of beqctrl is 9 | begin 10 | pcen<=(zero and branch) or pcwrite; 11 | end; -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # mips_computer 2 | 3 | A `simple` computer based on the design in "Digital Design and Computer Architecture - 2nd Edition" 4 | 5 | ## instructions supported 6 | 7 | add 8 | sub 9 | and 10 | or 11 | xor 12 | slt 13 | addi 14 | beq 15 | lw 16 | sw 17 | j -------------------------------------------------------------------------------- /src/signext.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | entity signext is -- sign extender 3 | port(a: in STD_LOGIC_VECTOR(15 downto 0); 4 | y: out STD_LOGIC_VECTOR(31 downto 0)); 5 | end; 6 | architecture behave of signext is 7 | begin 8 | y <= X"ffff" & a when a(15)='1' else X"0000" & a; 9 | end; -------------------------------------------------------------------------------- /src/jmpmerge.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | 3 | entity jmpmerge is -- merge pc 4 | port(instr: in STD_LOGIC_VECTOR(25 downto 0); 5 | pchi: in STD_LOGIC_VECTOR(3 downto 0); 6 | y: out STD_LOGIC_VECTOR(31 downto 0)); 7 | end; 8 | architecture behave of jmpmerge is 9 | begin 10 | y<= pchi & instr & "00"; 11 | end; -------------------------------------------------------------------------------- /src/mux2_sl.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.numeric_std.all ; 4 | 5 | entity mux2_sl is 6 | port ( 7 | d0,d1:in std_logic; 8 | s:in std_logic ; 9 | y:out std_logic 10 | ) ; 11 | end mux2_sl ; 12 | 13 | architecture arch of mux2_sl is 14 | 15 | begin 16 | y <= d1 when s = '1' else d0; 17 | end architecture ; -------------------------------------------------------------------------------- /src/mux2.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | entity mux2 is -- two-input multiplexer 3 | generic(width: integer := 32); 4 | port(d0, d1: in STD_LOGIC_VECTOR(width-1 downto 0); 5 | s: in STD_LOGIC; 6 | y: out STD_LOGIC_VECTOR(width-1 downto 0)); 7 | end; 8 | architecture behave of mux2 is 9 | begin 10 | y <= d1 when s = '1' else d0; 11 | end; -------------------------------------------------------------------------------- /src/intvec.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | use IEEE.STD_LOGIC_ARITH.all; 3 | use IEEE.STD_LOGIC_UNSIGNED.all; 4 | entity intvec is -- two-input multiplexer 5 | generic(width: integer := 32; int:integer:=0); 6 | port(y: out STD_LOGIC_VECTOR(width-1 downto 0)); 7 | end; 8 | architecture behave of intvec is 9 | begin 10 | y<=conv_std_logic_vector(int,width); 11 | end; -------------------------------------------------------------------------------- /src/outputctrl.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.numeric_std.all ; 4 | 5 | entity outputctrl is 6 | port ( 7 | adr:in std_logic_vector(31 downto 0) ; 8 | wi:in std_logic; 9 | we :out std_logic 10 | ) ; 11 | end outputctrl ; 12 | 13 | architecture arch of outputctrl is 14 | 15 | begin 16 | we<='1'when((wi='1') and (adr >= x"FFFF0000")) 17 | else '0'; 18 | end architecture ; -------------------------------------------------------------------------------- /src/mux4.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | entity mux4 is -- four-input multiplexer 3 | generic(width: integer := 32); 4 | port(d0, d1,d2,d3: in STD_LOGIC_VECTOR(width-1 downto 0); 5 | s: in STD_LOGIC_VECTOR(1 downto 0); 6 | y: out STD_LOGIC_VECTOR(width-1 downto 0)); 7 | end; 8 | architecture behave of mux4 is 9 | begin 10 | with s select 11 | y <= d0 when "00", 12 | d1 when "01", 13 | d2 when "10", 14 | d3 when "11"; 15 | end; -------------------------------------------------------------------------------- /src/ioselector.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.numeric_std.all ; 4 | 5 | entity ioselector is 6 | port ( 7 | adr :in std_logic_vector(31 downto 0) ; 8 | wd1,wd2 :in std_logic_vector(31 downto 0) ; 9 | wdf :out std_logic_vector(31 downto 0) 10 | ) ; 11 | end ioselector ; 12 | 13 | architecture arch of ioselector is 14 | 15 | begin 16 | wdf<= wd1 when ((adr and x"FFFF0000") = x"00000000") 17 | else wd2; 18 | end architecture ; -------------------------------------------------------------------------------- /src/flopr.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | use IEEE.STD_LOGIC_ARITH.all; 3 | entity flopr is -- flip-flop with synchronous reset 4 | generic (width: integer:=32); 5 | port(clk, reset: in STD_LOGIC; 6 | d: in STD_LOGIC_VECTOR(width-1 downto 0); 7 | q: out STD_LOGIC_VECTOR(width-1 downto 0)); 8 | end; 9 | architecture asynchronous of flopr is 10 | begin 11 | process(clk, reset) begin 12 | if reset='1' then 13 | q <= (others => '0'); 14 | elsif rising_edge(clk) then 15 | q <= d; 16 | end if; 17 | end process; 18 | end; -------------------------------------------------------------------------------- /src/resetwav.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.numeric_std.all ; 4 | 5 | entity resetwav is 6 | port ( 7 | clock:in std_logic; 8 | rst:out std_logic 9 | ) ; 10 | end resetwav ; 11 | 12 | architecture arch of resetwav is 13 | shared variable reset:std_logic:='1'; 14 | begin 15 | proc : process( clock ) 16 | begin 17 | if(rising_edge(clock))then 18 | if(reset ='1')then 19 | rst<='1'; 20 | reset:='0'; 21 | else 22 | rst<='0'; 23 | end if; 24 | end if; 25 | end process ; -- proc 26 | end architecture ; -------------------------------------------------------------------------------- /src/flopenr.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | use IEEE.STD_LOGIC_ARITH.all; 3 | entity flopenr is -- flip-flop with synchronous reset & enable 4 | generic (width: integer:=32); 5 | port(clk, reset, en: in STD_LOGIC; 6 | d: in STD_LOGIC_VECTOR(width-1 downto 0); 7 | q: out STD_LOGIC_VECTOR(width-1 downto 0)); 8 | end; 9 | architecture asynchronous of flopenr is 10 | begin 11 | process(clk, reset) begin 12 | if reset = '1' then 13 | q <= (others => '0'); 14 | elsif rising_edge(clk) then 15 | if(en = '1') then 16 | q <= d; 17 | end if; 18 | end if; 19 | end process; 20 | end; -------------------------------------------------------------------------------- /src/uart_clk.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity uart_clk is 5 | port( clk_50m: in std_logic; 6 | clr: in std_logic; 7 | bps_start: in std_logic; 8 | clk_bps: out std_logic); 9 | end uart_clk; 10 | 11 | architecture uart_clk_arch of uart_clk is 12 | shared variable count: integer range 0 to 5208 := 0; 13 | begin 14 | process(clk_50m, clr) 15 | begin 16 | if(clr = '1') then 17 | count := 0; 18 | elsif(rising_edge(clk_50m)) then 19 | if((count = 5208) or (bps_start = '0')) then 20 | count := 0; 21 | else 22 | count := count + 1; 23 | end if; 24 | end if; 25 | end process; 26 | clk_bps <= '1' when count = 2604 else '0'; 27 | end uart_clk_arch; -------------------------------------------------------------------------------- /src/clkslower.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.numeric_std.all ; 4 | 5 | entity clkslower is 6 | port ( 7 | clkIN:in std_logic; 8 | clkOUT:out std_logic 9 | ) ; 10 | end clkslower ; 11 | 12 | architecture arch of clkslower is 13 | shared variable clk_cnt:integer:=0; 14 | signal clk_o:std_logic:='0'; 15 | constant clk_max:integer:=50;--5000000; 16 | begin 17 | proc : process( all ) 18 | begin 19 | if(rising_edge(clkIN))then 20 | if(clk_cnt=clk_max)then 21 | clk_cnt:=0; 22 | clk_o<='1'; 23 | else 24 | clk_o<='0'; 25 | clk_cnt:=clk_cnt+1; 26 | end if; 27 | end if; 28 | end process ; -- proc 29 | clkOUT<=clkIN; 30 | end architecture ; -------------------------------------------------------------------------------- /src/memory.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all; 3 | use IEEE.NUMERIC_STD.all; 4 | entity dmem is -- data memory 5 | port(clk, we: in STD_LOGIC; 6 | a, wd: in STD_LOGIC_VECTOR (31 downto 0); 7 | rd: out STD_LOGIC_VECTOR (31 downto 0)); 8 | end; 9 | architecture behave of dmem is 10 | signal sel :natural; 11 | begin 12 | sel<= to_integer(unsigned(a(7 downto 2))); 13 | process(clk,a) is 14 | type ramtype is array (63 downto 0) of 15 | STD_LOGIC_VECTOR(31 downto 0); 16 | variable mem: ramtype; 17 | begin 18 | -- read or write memory 19 | if rising_edge(clk) then 20 | if (we='1') then mem (sel):= wd; 21 | end if; 22 | end if; 23 | rd <= mem (sel); 24 | end process; 25 | end; -------------------------------------------------------------------------------- /src/alu.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.numeric_std.all ; 4 | use ieee.std_logic_unsigned.all; 5 | 6 | entity alu is 7 | port(a, b: in STD_LOGIC_VECTOR(31 downto 0); 8 | alucontrol: in STD_LOGIC_VECTOR(2 downto 0); 9 | result: buffer STD_LOGIC_VECTOR(31 downto 0); 10 | zero: out STD_LOGIC); 11 | end alu ; 12 | 13 | architecture arch of alu is 14 | function bool_to_slv(X : boolean) 15 | return STD_LOGIC_VECTOR is 16 | begin 17 | if X then 18 | return (x"00000001"); 19 | else 20 | return (x"00000000"); 21 | end if; 22 | end bool_to_slv; 23 | begin 24 | with alucontrol select 25 | result <= a + b when "010", 26 | a - b when "110", 27 | a and b when "000", 28 | a or b when "001", 29 | a xor b when "011", 30 | bool_to_slv(a < b) when "111" , 31 | a when others; 32 | zero<= '1' when result =x"00000000" else '0'; 33 | end architecture ; -------------------------------------------------------------------------------- /src/regfile.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.std_logic_arith.all; 4 | use ieee.std_logic_unsigned.all; 5 | 6 | entity regfile is 7 | port ( 8 | clk :in std_logic; 9 | we3 :in std_logic; 10 | ra1,ra2,wa3 :in std_logic_vector(4 downto 0); 11 | wd3 :in std_logic_vector(31 downto 0); 12 | rd1,rd2 :out std_logic_vector(31 downto 0) 13 | ) ; 14 | end regfile ; 15 | 16 | architecture arch of regfile is 17 | type reg_file is array(31 downto 0) 18 | of std_logic_vector(31 downto 0); 19 | signal reg:reg_file; 20 | begin 21 | process(clk) begin 22 | if rising_edge(clk) then 23 | if we3='1' then 24 | reg(conv_integer(wa3))<=wd3; 25 | end if; 26 | end if; 27 | end process; 28 | process(ra1,ra2)begin 29 | if(conv_integer(ra1)=0)then rd1<= x"00000000"; 30 | else rd1<=reg(conv_integer(ra1)); 31 | end if; 32 | if(conv_integer(ra2)=0)then rd2<= x"00000000"; 33 | else rd2<=reg(conv_integer(ra2)); 34 | end if; 35 | end process; 36 | end architecture ; -------------------------------------------------------------------------------- /src/aludec.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | entity aludec is -- ALU control decoder 3 | port(funct: in STD_LOGIC_VECTOR(5 downto 0); 4 | aluop: in STD_LOGIC_VECTOR(1 downto 0); 5 | alucontrol: out STD_LOGIC_VECTOR(2 downto 0)); 6 | end; 7 | architecture behave of aludec is 8 | begin 9 | process(all) begin 10 | case aluop is 11 | when "00" => alucontrol <= "010"; -- add (for 1w/sw/addi) 12 | when "01" => alucontrol <= "110"; -- sub (for beq) 13 | when others => 14 | case funct is -- R-type instructions 15 | when "100000" => alucontrol <= "010"; -- add 16 | when "100010" => alucontrol <= "110"; -- sub 17 | when "100100" => alucontrol <= "000"; -- and 18 | when "100101" => alucontrol <= "001"; -- or 19 | when "101010" => alucontrol <= "111"; -- slt 20 | when "100110" => alucontrol <= "011"; -- xor 21 | when others => alucontrol <= "---"; -- ??? 22 | end case; 23 | end case; 24 | end process; 25 | end; -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 joker 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /src/readinput.vhd: -------------------------------------------------------------------------------- 1 | library ieee ; 2 | use ieee.std_logic_1164.all ; 3 | use ieee.numeric_std.all ; 4 | 5 | entity readinput is 6 | port (clk:in std_logic; 7 | a,b,c,d :in std_logic ; 8 | we :out std_logic; 9 | inputvec:out std_logic_vector(3 downto 0) 10 | ) ; 11 | end readinput ; 12 | 13 | architecture arch of readinput is 14 | signal before:std_logic_vector(3 downto 0):="0000"; 15 | signal current:std_logic_vector(3 downto 0):="0000"; 16 | signal w:std_logic:='0'; 17 | begin 18 | process(all) is 19 | variable clk_mul:integer:=0; 20 | constant clk_max:integer:=5; 21 | begin 22 | if(rising_edge(clk))then 23 | current(3)<=a; 24 | current(2)<=b; 25 | current(1)<=c; 26 | current(0)<=d; 27 | if (clk_mul=0) then 28 | clk_mul:=clk_max; 29 | before<=current; 30 | else 31 | clk_mul:=clk_mul-1; 32 | end if ; 33 | -- if((a&b&c&d)=before)then 34 | -- if(clk_mul=0)then 35 | -- w<='0'; 36 | -- else clk_mul:=clk_mul-1; 37 | -- end if; 38 | -- else 39 | -- clk_mul:=15; 40 | -- w<='1'; 41 | -- before<=current; 42 | -- end if; 43 | end if; 44 | end process; 45 | inputvec<=before; 46 | we<='1'; 47 | end; -------------------------------------------------------------------------------- /src/mips_computer.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 21 | # Date created = 00:43:44 June 29, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "00:43:44 June 29, 2018" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "mips_computer" 31 | -------------------------------------------------------------------------------- /src/iomemory.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all; 3 | use IEEE.NUMERIC_STD.all; 4 | use IEEE.std_logic_arith.conv_std_logic_vector; 5 | entity iomemory is -- io buffer memory 6 | port(clk,wr:in std_logic; 7 | a: in STD_LOGIC_VECTOR(31 downto 0); 8 | a8:in std_logic_vector(7 downto 0) ; 9 | w8:in std_logic_vector(7 downto 0) ; 10 | rd: out STD_LOGIC_VECTOR(31 downto 0)); 11 | end; 12 | architecture behave of iomemory is 13 | function minus_ffff ( 14 | org : in std_logic_vector) 15 | return std_logic_vector is 16 | begin 17 | return org and x"0000ffff" ; 18 | end function minus_ffff; 19 | type ramtype is array (63 downto 0) of 20 | STD_LOGIC_VECTOR(7 downto 0); 21 | shared variable mem:ramtype; 22 | begin 23 | process(all) is 24 | variable top_val:integer:=0; 25 | begin 26 | if(rising_edge(clk)) then 27 | if(wr='1')then 28 | mem(to_integer(unsigned(a8))):=w8; 29 | end if; 30 | end if; 31 | end process; 32 | rd <=mem(to_integer(unsigned(minus_ffff(a)))) 33 | &mem(to_integer(unsigned(minus_ffff(a)))+1) 34 | &mem(to_integer(unsigned(minus_ffff(a)))+2) 35 | &mem(to_integer(unsigned(minus_ffff(a)))+3) 36 | when ((a and x"ffff0000")/=x"00000000") 37 | else x"01010101"; 38 | 39 | 40 | end; -------------------------------------------------------------------------------- /src/resetwav.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 152 96) 24 | (text "resetwav" (rect 5 0 41 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 20 12)(font "Arial" )) 30 | (text "clock" (rect 21 27 41 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 136 32) 35 | (output) 36 | (text "rst" (rect 0 0 10 12)(font "Arial" )) 37 | (text "rst" (rect 105 27 115 39)(font "Arial" )) 38 | (line (pt 136 32)(pt 120 32)(line_width 1)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 120 64)(line_width 1)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /src/sl2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 176 96) 24 | (text "sl2" (rect 5 0 15 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "a[31..0]" (rect 0 0 28 12)(font "Arial" )) 30 | (text "a[31..0]" (rect 21 27 49 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 160 32) 35 | (output) 36 | (text "y[31..0]" (rect 0 0 29 12)(font "Arial" )) 37 | (text "y[31..0]" (rect 110 27 139 39)(font "Arial" )) 38 | (line (pt 160 32)(pt 144 32)(line_width 3)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 144 64)(line_width 1)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /src/clkslower.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 168 96) 24 | (text "clkslower" (rect 5 0 40 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clkIN" (rect 0 0 20 12)(font "Arial" )) 30 | (text "clkIN" (rect 21 27 41 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 152 32) 35 | (output) 36 | (text "clkOUT" (rect 0 0 30 12)(font "Arial" )) 37 | (text "clkOUT" (rect 101 27 131 39)(font "Arial" )) 38 | (line (pt 152 32)(pt 136 32)(line_width 1)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 136 64)(line_width 1)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /src/signext.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 176 96) 24 | (text "signext" (rect 5 0 32 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "a[15..0]" (rect 0 0 28 12)(font "Arial" )) 30 | (text "a[15..0]" (rect 21 27 49 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 160 32) 35 | (output) 36 | (text "y[31..0]" (rect 0 0 29 12)(font "Arial" )) 37 | (text "y[31..0]" (rect 110 27 139 39)(font "Arial" )) 38 | (line (pt 160 32)(pt 144 32)(line_width 3)) 39 | ) 40 | (drawing 41 | (rectangle (rect 16 16 144 64)(line_width 1)) 42 | ) 43 | ) 44 | -------------------------------------------------------------------------------- /src/intvec.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 168 96) 24 | (text "intvec" (rect 5 0 28 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 152 32) 28 | (output) 29 | (text "y[width-1..0]" (rect 0 0 46 12)(font "Arial" )) 30 | (text "y[width-1..0]" (rect 85 27 131 39)(font "Arial" )) 31 | (line (pt 152 32)(pt 136 32)(line_width 3)) 32 | ) 33 | (parameter 34 | "width" 35 | "32" 36 | "" 37 | (type "PARAMETER_SIGNED_DEC") ) 38 | (parameter 39 | "int" 40 | "0" 41 | "" 42 | (type "PARAMETER_SIGNED_DEC") ) 43 | (drawing 44 | (rectangle (rect 16 16 136 64)(line_width 1)) 45 | ) 46 | (annotation_block (parameter)(rect 168 -64 268 16)) 47 | ) 48 | -------------------------------------------------------------------------------- /src/outputctrl.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 168 96) 24 | (text "outputctrl" (rect 5 0 40 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "adr[31..0]" (rect 0 0 36 12)(font "Arial" )) 30 | (text "adr[31..0]" (rect 21 27 57 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "wi" (rect 0 0 7 12)(font "Arial" )) 37 | (text "wi" (rect 21 43 28 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 152 32) 42 | (output) 43 | (text "we" (rect 0 0 10 12)(font "Arial" )) 44 | (text "we" (rect 121 27 131 39)(font "Arial" )) 45 | (line (pt 152 32)(pt 136 32)(line_width 1)) 46 | ) 47 | (drawing 48 | (rectangle (rect 16 16 136 64)(line_width 1)) 49 | ) 50 | ) 51 | -------------------------------------------------------------------------------- /src/jmpmerge.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 192 96) 24 | (text "jmpmerge" (rect 5 0 45 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "instr[25..0]" (rect 0 0 41 12)(font "Arial" )) 30 | (text "instr[25..0]" (rect 21 27 62 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "pchi[3..0]" (rect 0 0 35 12)(font "Arial" )) 37 | (text "pchi[3..0]" (rect 21 43 56 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 176 32) 42 | (output) 43 | (text "y[31..0]" (rect 0 0 29 12)(font "Arial" )) 44 | (text "y[31..0]" (rect 126 27 155 39)(font "Arial" )) 45 | (line (pt 176 32)(pt 160 32)(line_width 3)) 46 | ) 47 | (drawing 48 | (rectangle (rect 16 16 160 64)(line_width 1)) 49 | ) 50 | ) 51 | -------------------------------------------------------------------------------- /src/aludec.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 216 96) 24 | (text "aludec" (rect 5 0 29 12)(font "Arial" )) 25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "funct[5..0]" (rect 0 0 40 12)(font "Arial" )) 30 | (text "funct[5..0]" (rect 21 27 61 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "aluop[1..0]" (rect 0 0 38 12)(font "Arial" )) 37 | (text "aluop[1..0]" (rect 21 43 59 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 200 32) 42 | (output) 43 | (text "alucontrol[2..0]" (rect 0 0 56 12)(font "Arial" )) 44 | (text "alucontrol[2..0]" (rect 123 27 179 39)(font "Arial" )) 45 | (line (pt 200 32)(pt 184 32)(line_width 3)) 46 | ) 47 | (drawing 48 | (rectangle (rect 16 16 184 64)(line_width 1)) 49 | ) 50 | ) 51 | -------------------------------------------------------------------------------- /src/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | # Created by https://www.gitignore.io/api/alteraquartusii 3 | 4 | ### AlteraQuartusII ### 5 | ##list taken from http://www.alterawiki.com/wiki/Version_Control (01.10.2015) 6 | 7 | ######### Quartus II source files 8 | 9 | # project files: 10 | ### project_name.qpf Quartus II project file 11 | ### project_name.qsf Quartus constraint file (lists the hardware constraints defined for a project, from the used chip and pinout to timing constraints) 12 | ### project_name.qws Quartus Window Settings ? (the configuration of the Quartus gui for the project, may be omitted) 13 | 14 | # top level source files: 15 | ### project_name.bdf Block diagram / Schematic file (top level schematic file, there may be many nested files) 16 | ### project_name.vhd VHDL file (top level VHDL file) 17 | ### project_name.v Verilog file (top level Verilog file) 18 | 19 | # component source files: 20 | ### component_name.bsf Block Symbol file (component symbol file) 21 | ### component_name.vhd VHDL file (top level VHDL file) 22 | ### component_name.v Verilog file (top level Verilog file) 23 | 24 | # SOPC builder project source files (SOPC builder creates many VHDL or Verilog files, that you do not need to store) 25 | ### sopc_project_name.ptf the list and configuration of components selected in the SOPC gui 26 | ### sopc_project_name.bsf Block Symbol file (SOPC component symbol file, especially if you modified it) 27 | 28 | # Board Description (if you created your own board, the list is incomplete!) 29 | ### board_name/class.ptf 30 | 31 | # software source files: 32 | ### tbd 33 | 34 | ######## Quartus II binary files 35 | 36 | # hardware binary files 37 | ### project_name.sof SRAM Object File 38 | 39 | # software binary files 40 | ### tbd 41 | 42 | /* 43 | !/*.gitignore 44 | ## 45 | !*.qpf 46 | !*.qsf 47 | !*.qws 48 | ## 49 | !*.bdf 50 | !*.vhd 51 | !*.v 52 | ## 53 | !*.ptf 54 | !*.bsf 55 | ## 56 | !**/class.ptf 57 | ## 58 | !*.tbd 59 | ## 60 | !*.sof 61 | ## 62 | ## tbd 63 | 64 | !*.tcl 65 | 66 | 67 | # End of https://www.gitignore.io/api/alteraquartusii 68 | -------------------------------------------------------------------------------- /src/mux2_sl.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 136 128) 24 | (text "mux2_sl" (rect 5 0 39 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "d0" (rect 0 0 9 12)(font "Arial" )) 30 | (text "d0" (rect 21 27 30 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "d1" (rect 0 0 8 12)(font "Arial" )) 37 | (text "d1" (rect 21 43 29 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "s" (rect 0 0 4 12)(font "Arial" )) 44 | (text "s" (rect 21 59 25 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 120 32) 49 | (output) 50 | (text "y" (rect 0 0 5 12)(font "Arial" )) 51 | (text "y" (rect 94 27 99 39)(font "Arial" )) 52 | (line (pt 120 32)(pt 104 32)(line_width 1)) 53 | ) 54 | (drawing 55 | (rectangle (rect 16 16 104 96)(line_width 1)) 56 | ) 57 | ) 58 | -------------------------------------------------------------------------------- /src/beqctrl.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 160 128) 24 | (text "beqctrl" (rect 5 0 30 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "zero" (rect 0 0 16 12)(font "Arial" )) 30 | (text "zero" (rect 21 27 37 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "branch" (rect 0 0 27 12)(font "Arial" )) 37 | (text "branch" (rect 21 43 48 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "pcwrite" (rect 0 0 27 12)(font "Arial" )) 44 | (text "pcwrite" (rect 21 59 48 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 144 32) 49 | (output) 50 | (text "pcen" (rect 0 0 18 12)(font "Arial" )) 51 | (text "pcen" (rect 105 27 123 39)(font "Arial" )) 52 | (line (pt 144 32)(pt 128 32)(line_width 1)) 53 | ) 54 | (drawing 55 | (rectangle (rect 16 16 128 96)(line_width 1)) 56 | ) 57 | ) 58 | -------------------------------------------------------------------------------- /src/uart_clk.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 184 128) 24 | (text "uart_clk" (rect 5 0 36 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50m" (rect 0 0 34 12)(font "Arial" )) 30 | (text "clk_50m" (rect 21 27 55 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clr" (rect 0 0 9 12)(font "Arial" )) 37 | (text "clr" (rect 21 43 30 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "bps_start" (rect 0 0 37 12)(font "Arial" )) 44 | (text "bps_start" (rect 21 59 58 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 168 32) 49 | (output) 50 | (text "clk_bps" (rect 0 0 30 12)(font "Arial" )) 51 | (text "clk_bps" (rect 117 27 147 39)(font "Arial" )) 52 | (line (pt 168 32)(pt 152 32)(line_width 1)) 53 | ) 54 | (drawing 55 | (rectangle (rect 16 16 152 96)(line_width 1)) 56 | ) 57 | ) 58 | -------------------------------------------------------------------------------- /src/ioselector.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 192 128) 24 | (text "ioselector" (rect 5 0 41 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "adr[31..0]" (rect 0 0 36 12)(font "Arial" )) 30 | (text "adr[31..0]" (rect 21 27 57 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "wd1[31..0]" (rect 0 0 37 12)(font "Arial" )) 37 | (text "wd1[31..0]" (rect 21 43 58 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "wd2[31..0]" (rect 0 0 38 12)(font "Arial" )) 44 | (text "wd2[31..0]" (rect 21 59 59 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 176 32) 49 | (output) 50 | (text "wdf[31..0]" (rect 0 0 37 12)(font "Arial" )) 51 | (text "wdf[31..0]" (rect 118 27 155 39)(font "Arial" )) 52 | (line (pt 176 32)(pt 160 32)(line_width 3)) 53 | ) 54 | (drawing 55 | (rectangle (rect 16 16 160 96)(line_width 1)) 56 | ) 57 | ) 58 | -------------------------------------------------------------------------------- /src/digtube.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity digtube is 5 | generic (wid : integer := 4); 6 | port( 7 | clk, reset, en : in std_logic; 8 | data : in std_logic_vector(wid*4-1 downto 0); 9 | dt_sel : out std_logic_vector(wid-1 downto 0); 10 | dt_data : out std_logic_vector(7 downto 0) 11 | ); 12 | end digtube; 13 | 14 | architecture arch of digtube is 15 | 16 | function decode (code : std_logic_vector--; l : integer; r : integer 17 | ) 18 | return std_logic_vector is 19 | begin 20 | case code is 21 | when "0000" => return "00000011";--0 22 | when "0001" => return "10011111"; 23 | when "0010" => return "00100101"; 24 | when "0011" => return "00001101"; 25 | when "0100" => return "10011001";--4 26 | when "0101" => return "01001001"; 27 | when "0110" => return "01000001"; 28 | when "0111" => return "00011111"; 29 | when "1000" => return "00000001";--8 30 | when "1001" => return "00011001"; 31 | when "1010" => return "00010001"; 32 | when "1011" => return "11000001"; 33 | when "1100" => return "01100011";--c 34 | when "1101" => return "10000101"; 35 | when "1110" => return "01100001"; 36 | when "1111" => return "01110001"; 37 | when others => return "11111110"; 38 | end case; 39 | end function decode; 40 | 41 | type dtarr is array (wid-1 downto 0) of std_logic_vector(7 downto 0); 42 | signal dt_arr : dtarr; 43 | 44 | begin 45 | 46 | process (en, reset) is 47 | begin 48 | if reset = '1' then 49 | for i in wid-1 downto 0 loop 50 | dt_arr(i) <= "00000011"; 51 | end loop; 52 | elsif en = '1' then 53 | 54 | for i in wid-1 downto 0 loop 55 | dt_arr(i) <= decode(data(3 + i*4 downto i*4)); 56 | end loop; 57 | 58 | end if; 59 | end process; 60 | 61 | process (clk) is 62 | variable ff : integer range -1 to wid := 0; 63 | variable counter : integer range 0 to 2500; 64 | begin 65 | 66 | if rising_edge(clk) then 67 | counter := counter + 1; 68 | if counter = 2500 then 69 | counter := 0; 70 | for i in wid-1 downto 0 loop 71 | if i = ff then dt_sel(i) <= '0'; 72 | else dt_sel(i) <= '1'; 73 | end if; 74 | end loop; 75 | 76 | if ff = wid then ff := -1; 77 | else dt_data <= dt_arr(ff); 78 | end if; 79 | ff := ff + 1; 80 | end if; 81 | end if; 82 | end process; 83 | end; -------------------------------------------------------------------------------- /src/mux2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 216 128) 24 | (text "mux2" (rect 5 0 27 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "d0[width-1..0]" (rect 0 0 49 12)(font "Arial" )) 30 | (text "d0[width-1..0]" (rect 21 27 70 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "d1[width-1..0]" (rect 0 0 48 12)(font "Arial" )) 37 | (text "d1[width-1..0]" (rect 21 43 69 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "s" (rect 0 0 4 12)(font "Arial" )) 44 | (text "s" (rect 21 59 25 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 200 32) 49 | (output) 50 | (text "y[width-1..0]" (rect 0 0 46 12)(font "Arial" )) 51 | (text "y[width-1..0]" (rect 133 27 179 39)(font "Arial" )) 52 | (line (pt 200 32)(pt 184 32)(line_width 3)) 53 | ) 54 | (parameter 55 | "width" 56 | "32" 57 | "" 58 | (type "PARAMETER_SIGNED_DEC") ) 59 | (drawing 60 | (rectangle (rect 16 16 184 96)(line_width 1)) 61 | ) 62 | (annotation_block (parameter)(rect 216 -64 316 16)) 63 | ) 64 | -------------------------------------------------------------------------------- /src/dmem.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 184 128) 24 | (text "dmem" (rect 5 0 30 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "we" (rect 0 0 10 12)(font "Arial" )) 37 | (text "we" (rect 21 43 31 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "a[31..0]" (rect 0 0 28 12)(font "Arial" )) 44 | (text "a[31..0]" (rect 21 59 49 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "wd[31..0]" (rect 0 0 34 12)(font "Arial" )) 51 | (text "wd[31..0]" (rect 21 75 55 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 168 32) 56 | (output) 57 | (text "rd[31..0]" (rect 0 0 31 12)(font "Arial" )) 58 | (text "rd[31..0]" (rect 116 27 147 39)(font "Arial" )) 59 | (line (pt 168 32)(pt 152 32)(line_width 3)) 60 | ) 61 | (drawing 62 | (rectangle (rect 16 16 152 96)(line_width 1)) 63 | ) 64 | ) 65 | -------------------------------------------------------------------------------- /src/flopenr.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 208 128) 24 | (text "flopenr" (rect 5 0 32 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "reset" (rect 0 0 20 12)(font "Arial" )) 37 | (text "reset" (rect 21 43 41 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "en" (rect 0 0 9 12)(font "Arial" )) 44 | (text "en" (rect 21 59 30 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "d[width-1..0]" (rect 0 0 44 12)(font "Arial" )) 51 | (text "d[width-1..0]" (rect 21 75 65 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 192 32) 56 | (output) 57 | (text "q[width-1..0]" (rect 0 0 44 12)(font "Arial" )) 58 | (text "q[width-1..0]" (rect 127 27 171 39)(font "Arial" )) 59 | (line (pt 192 32)(pt 176 32)(line_width 3)) 60 | ) 61 | (parameter 62 | "width" 63 | "32" 64 | "" 65 | (type "PARAMETER_SIGNED_DEC") ) 66 | (drawing 67 | (rectangle (rect 16 16 176 96)(line_width 1)) 68 | ) 69 | (annotation_block (parameter)(rect 208 -64 308 16)) 70 | ) 71 | -------------------------------------------------------------------------------- /src/imem.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 184 160) 24 | (text "imem" (rect 5 0 27 12)(font "Arial" )) 25 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "reset" (rect 0 0 20 12)(font "Arial" )) 37 | (text "reset" (rect 21 43 41 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "we" (rect 0 0 10 12)(font "Arial" )) 44 | (text "we" (rect 21 59 31 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "a[31..0]" (rect 0 0 28 12)(font "Arial" )) 51 | (text "a[31..0]" (rect 21 75 49 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "wd[31..0]" (rect 0 0 34 12)(font "Arial" )) 58 | (text "wd[31..0]" (rect 21 91 55 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 3)) 60 | ) 61 | (port 62 | (pt 168 32) 63 | (output) 64 | (text "rd[31..0]" (rect 0 0 31 12)(font "Arial" )) 65 | (text "rd[31..0]" (rect 116 27 147 39)(font "Arial" )) 66 | (line (pt 168 32)(pt 152 32)(line_width 3)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 152 128)(line_width 1)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /src/iomemory.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 176 160) 24 | (text "iomemory" (rect 5 0 46 12)(font "Arial" )) 25 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "wr" (rect 0 0 9 12)(font "Arial" )) 37 | (text "wr" (rect 21 43 30 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "a[31..0]" (rect 0 0 28 12)(font "Arial" )) 44 | (text "a[31..0]" (rect 21 59 49 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "a8[7..0]" (rect 0 0 29 12)(font "Arial" )) 51 | (text "a8[7..0]" (rect 21 75 50 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "w8[7..0]" (rect 0 0 30 12)(font "Arial" )) 58 | (text "w8[7..0]" (rect 21 91 51 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 3)) 60 | ) 61 | (port 62 | (pt 160 32) 63 | (output) 64 | (text "rd[31..0]" (rect 0 0 31 12)(font "Arial" )) 65 | (text "rd[31..0]" (rect 108 27 139 39)(font "Arial" )) 66 | (line (pt 160 32)(pt 144 32)(line_width 3)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 144 128)(line_width 1)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /src/uart_rx.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity uart_rx is 5 | port( clk_50m: in std_logic; 6 | clr: in std_logic; 7 | clk_bps: in std_logic; 8 | rxd: in std_logic; 9 | bps_start: out std_logic; 10 | wr: out std_logic := '0'; 11 | addr: out std_logic_vector(7 downto 0); 12 | ram_in: out std_logic_vector(7 downto 0)); 13 | end uart_rx; 14 | 15 | architecture uart_rx_arch of uart_rx is 16 | signal temp: std_logic_vector(3 downto 0) := "0000"; 17 | signal rx_active: std_logic; 18 | signal num: integer range 0 to 9 := 0; 19 | shared variable count: integer range 0 to 10000000 := 0; 20 | begin 21 | process(clk_50m, clr) 22 | begin 23 | if(clr = '1') then 24 | temp <= "0000"; 25 | elsif(rising_edge(clk_50m)) then 26 | temp <= temp(2 downto 0) & rxd; 27 | end if; 28 | end process; 29 | rx_active <= '1' when temp = "1100" else '0'; 30 | process(clk_50m, clr) 31 | begin 32 | if(clr = '1') then 33 | bps_start <= '0'; 34 | elsif(rising_edge(clk_50m)) then 35 | if(rx_active = '1') then 36 | bps_start <= '1'; 37 | elsif((clk_bps = '1') and (num = 9)) then 38 | bps_start <= '0'; 39 | end if; 40 | end if; 41 | end process; 42 | process(clk_50m, clr) 43 | begin 44 | if(clr = '1') then 45 | num <= 0; 46 | count := 0; 47 | addr <= x"00"; 48 | ram_in <= x"00"; 49 | elsif(rising_edge(clk_50m)) then 50 | if(clk_bps = '1') then 51 | if(num = 9) then 52 | num <= 0; 53 | else 54 | num <= num + 1; 55 | end if; 56 | if(count <= 9) then 57 | case num is 58 | when 1 => addr(0) <= rxd; 59 | when 2 => addr(1) <= rxd; 60 | when 3 => addr(2) <= rxd; 61 | when 4 => addr(3) <= rxd; 62 | when 5 => addr(4) <= rxd; 63 | when 6 => addr(5) <= rxd; 64 | when 7 => addr(6) <= rxd; 65 | when 8 => addr(7) <= rxd; 66 | when others => null; 67 | end case; 68 | elsif(count <= 19) then 69 | case num is 70 | when 1 => ram_in(0) <= rxd; 71 | when 2 => ram_in(1) <= rxd; 72 | when 3 => ram_in(2) <= rxd; 73 | when 4 => ram_in(3) <= rxd; 74 | when 5 => ram_in(4) <= rxd; 75 | when 6 => ram_in(5) <= rxd; 76 | when 7 => ram_in(6) <= rxd; 77 | when 8 => ram_in(7) <= rxd; 78 | when others => null; 79 | end case; 80 | end if; 81 | count := count + 1; 82 | end if; 83 | if(count >= 20) then 84 | count := count + 1; 85 | end if; 86 | if(count = 10000000) then 87 | count := 0; 88 | end if; 89 | end if; 90 | end process; 91 | wr <= '1' when (count > 20) and (count < 10000000) else '0'; 92 | end uart_rx_arch; -------------------------------------------------------------------------------- /src/readinput.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 184 160) 24 | (text "readinput" (rect 5 0 40 12)(font "Arial" )) 25 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "a" (rect 0 0 4 12)(font "Arial" )) 37 | (text "a" (rect 21 43 25 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "b" (rect 0 0 4 12)(font "Arial" )) 44 | (text "b" (rect 21 59 25 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "c" (rect 0 0 4 12)(font "Arial" )) 51 | (text "c" (rect 21 75 25 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "d" (rect 0 0 4 12)(font "Arial" )) 58 | (text "d" (rect 21 91 25 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 1)) 60 | ) 61 | (port 62 | (pt 168 32) 63 | (output) 64 | (text "we" (rect 0 0 10 12)(font "Arial" )) 65 | (text "we" (rect 137 27 147 39)(font "Arial" )) 66 | (line (pt 168 32)(pt 152 32)(line_width 1)) 67 | ) 68 | (port 69 | (pt 168 48) 70 | (output) 71 | (text "inputvec[3..0]" (rect 0 0 53 12)(font "Arial" )) 72 | (text "inputvec[3..0]" (rect 94 43 147 55)(font "Arial" )) 73 | (line (pt 168 48)(pt 152 48)(line_width 3)) 74 | ) 75 | (drawing 76 | (rectangle (rect 16 16 152 128)(line_width 1)) 77 | ) 78 | ) 79 | -------------------------------------------------------------------------------- /src/digtube.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 232 128) 24 | (text "digtube" (rect 5 0 32 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "reset" (rect 0 0 20 12)(font "Arial" )) 37 | (text "reset" (rect 21 43 41 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "en" (rect 0 0 9 12)(font "Arial" )) 44 | (text "en" (rect 21 59 30 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "data[wid*4-1..0]" (rect 0 0 55 12)(font "Arial" )) 51 | (text "data[wid*4-1..0]" (rect 21 75 76 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 216 32) 56 | (output) 57 | (text "dt_sel[wid-1..0]" (rect 0 0 56 12)(font "Arial" )) 58 | (text "dt_sel[wid-1..0]" (rect 139 27 195 39)(font "Arial" )) 59 | (line (pt 216 32)(pt 200 32)(line_width 3)) 60 | ) 61 | (port 62 | (pt 216 48) 63 | (output) 64 | (text "dt_data[7..0]" (rect 0 0 49 12)(font "Arial" )) 65 | (text "dt_data[7..0]" (rect 146 43 195 55)(font "Arial" )) 66 | (line (pt 216 48)(pt 200 48)(line_width 3)) 67 | ) 68 | (parameter 69 | "wid" 70 | "4" 71 | "" 72 | (type "PARAMETER_SIGNED_DEC") ) 73 | (drawing 74 | (rectangle (rect 16 16 200 96)(line_width 1)) 75 | ) 76 | (annotation_block (parameter)(rect 232 -64 332 16)) 77 | ) 78 | -------------------------------------------------------------------------------- /src/regfile.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 192 160) 24 | (text "regfile" (rect 5 0 28 12)(font "Arial" )) 25 | (text "inst" (rect 8 128 20 140)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "we3" (rect 0 0 15 12)(font "Arial" )) 37 | (text "we3" (rect 21 43 36 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "ra1[4..0]" (rect 0 0 33 12)(font "Arial" )) 44 | (text "ra1[4..0]" (rect 21 59 54 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "ra2[4..0]" (rect 0 0 34 12)(font "Arial" )) 51 | (text "ra2[4..0]" (rect 21 75 55 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "wa3[4..0]" (rect 0 0 36 12)(font "Arial" )) 58 | (text "wa3[4..0]" (rect 21 91 57 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 3)) 60 | ) 61 | (port 62 | (pt 0 112) 63 | (input) 64 | (text "wd3[31..0]" (rect 0 0 38 12)(font "Arial" )) 65 | (text "wd3[31..0]" (rect 21 107 59 119)(font "Arial" )) 66 | (line (pt 0 112)(pt 16 112)(line_width 3)) 67 | ) 68 | (port 69 | (pt 176 32) 70 | (output) 71 | (text "rd1[31..0]" (rect 0 0 35 12)(font "Arial" )) 72 | (text "rd1[31..0]" (rect 120 27 155 39)(font "Arial" )) 73 | (line (pt 176 32)(pt 160 32)(line_width 3)) 74 | ) 75 | (port 76 | (pt 176 48) 77 | (output) 78 | (text "rd2[31..0]" (rect 0 0 36 12)(font "Arial" )) 79 | (text "rd2[31..0]" (rect 119 43 155 55)(font "Arial" )) 80 | (line (pt 176 48)(pt 160 48)(line_width 3)) 81 | ) 82 | (drawing 83 | (rectangle (rect 16 16 160 128)(line_width 1)) 84 | ) 85 | ) 86 | -------------------------------------------------------------------------------- /src/imem.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all; 3 | use IEEE.NUMERIC_STD.all; 4 | use IEEE.std_logic_arith.conv_std_logic_vector; 5 | entity imem is -- instruction/data memory 6 | port(clk,reset,we:in std_logic; 7 | a: in STD_LOGIC_VECTOR(31 downto 0); 8 | wd: in STD_LOGIC_VECTOR(31 downto 0); 9 | rd: out STD_LOGIC_VECTOR(31 downto 0)); 10 | end; 11 | architecture behave of imem is 12 | type ramtype is array (127 downto 0) of 13 | STD_LOGIC_VECTOR(7 downto 0); 14 | shared variable mem:ramtype; 15 | begin 16 | process(all) is 17 | variable init: boolean :=true; 18 | begin 19 | if(reset='1')then 20 | mem(0):= "10001100";--lw $1,60($0) 21 | mem(1):= "00000001"; 22 | mem(2):= "00000000"; 23 | mem(3):= "00111100"; 24 | mem(4):= "00100000";--addi $2,$1,4 25 | mem(5):= "00100010"; 26 | mem(6):= "00000000"; 27 | mem(7):= "00000100"; 28 | mem(8):= "00100000";--addi $3,$2,4 29 | mem(9):= "01000011"; 30 | mem(10):= "00000000"; 31 | mem(11):= "00000100"; 32 | mem(12):= "10001100";--lw $1,0($1) 33 | mem(13):= "00100001"; 34 | mem(14):= "00000000"; 35 | mem(15):= "00000000"; 36 | mem(16):= "10001100";--lw $2,0($2) 37 | mem(17):= "01000010"; 38 | mem(18):= "00000000"; 39 | mem(19):= "00000000"; 40 | mem(20):= "10001100";--lw $3,0($3) 41 | mem(21):= "01100011"; 42 | mem(22):= "00000000"; 43 | mem(23):= "00000000"; 44 | mem(24):= "00100000";--addi $4,$0,0 45 | mem(25):= "00000100"; 46 | mem(26):= "00000000"; 47 | mem(27):= "00000000"; 48 | mem(28):= "00010000";--beq $4,$3 add_pos 49 | mem(29):= "10000011"; 50 | mem(30):= "00000000"; 51 | mem(31):= "00000010"; 52 | mem(32):= "00100000";--addi $4,$0,1 53 | mem(33):= "00000100"; 54 | mem(34):= "00000000"; 55 | mem(35):= "00000001"; 56 | mem(36):= "00010000";--beq $4,$3 sub_pos 57 | mem(37):= "10000011"; 58 | mem(38):= "00000000"; 59 | mem(39):= "00000010"; 60 | mem(40):= "00000000";--add $5,$1,$2 61 | mem(41):= "00100010"; 62 | mem(42):= "00101000"; 63 | mem(43):= "00100000"; 64 | mem(44):= "00010000";--beq $0,$0 sav_pos 65 | mem(45):= "00000000"; 66 | mem(46):= "00000000"; 67 | mem(47):= "00000001"; 68 | mem(48):= "00000000";--sub $5,$1,$2 69 | mem(49):= "00100010"; 70 | mem(50):= "00101000"; 71 | mem(51):= "00100010"; 72 | mem(52):= "10101100";--sw $5,64($0) 73 | mem(53):= "00000101"; 74 | mem(54):= "00000000"; 75 | mem(55):= "01000000"; 76 | mem(56):= "00001000";--j 0 77 | mem(57):= "00000000"; 78 | mem(58):= "00000000"; 79 | mem(59):= "00000000"; 80 | mem(60):= "11111111";--ffff0001 81 | mem(61):= "11111111"; 82 | mem(62):= "00000000"; 83 | mem(63):= "00000001"; 84 | elsif(rising_edge(clk)) then 85 | if(we='1') then 86 | mem(to_integer(unsigned(a))+0) :=wd(31 downto 24); 87 | mem(to_integer(unsigned(a))+1) :=wd(23 downto 16); 88 | mem(to_integer(unsigned(a))+2) :=wd(15 downto 8); 89 | mem(to_integer(unsigned(a))+3) :=wd(7 downto 0); 90 | end if; 91 | end if; 92 | end process; 93 | rd <=mem(to_integer(unsigned(a))) 94 | &mem(to_integer(unsigned(a))+1) 95 | &mem(to_integer(unsigned(a))+2) 96 | &mem(to_integer(unsigned(a))+3) 97 | when ((a and x"ffff0000")=x"00000000") 98 | else x"01010101"; 99 | 100 | 101 | end; -------------------------------------------------------------------------------- /src/mips_fpga.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | 15 | -- PROGRAM "Quartus Prime" 16 | -- VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" 17 | -- CREATED "Mon Jul 02 20:50:46 2018" 18 | 19 | LIBRARY ieee; 20 | USE ieee.std_logic_1164.all; 21 | 22 | LIBRARY work; 23 | 24 | ENTITY mips_fpga IS 25 | PORT 26 | ( 27 | clk : IN STD_LOGIC; 28 | reset : IN STD_LOGIC; 29 | clk_dt : IN STD_LOGIC; 30 | data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 31 | sel : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 32 | state : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 33 | ); 34 | END mips_fpga; 35 | 36 | ARCHITECTURE bdf_type OF mips_fpga IS 37 | 38 | COMPONENT digtube 39 | GENERIC (wid : INTEGER 40 | ); 41 | PORT( clk, reset, en : in std_logic; 42 | data : in std_logic_vector(wid*4-1 downto 0); 43 | dt_sel : out std_logic_vector(wid-1 downto 0); 44 | dt_data : out std_logic_vector(7 downto 0) 45 | ); 46 | END COMPONENT; 47 | 48 | COMPONENT mips_computer 49 | PORT(clk : IN STD_LOGIC; 50 | reset : IN STD_LOGIC; 51 | MemtoReg : OUT STD_LOGIC; 52 | RegDst : OUT STD_LOGIC; 53 | IorD : OUT STD_LOGIC; 54 | ALUSrcA : OUT STD_LOGIC; 55 | IRWrite : OUT STD_LOGIC; 56 | MemWrite : OUT STD_LOGIC; 57 | PCWrite : OUT STD_LOGIC; 58 | Branch : OUT STD_LOGIC; 59 | RegWrite : OUT STD_LOGIC; 60 | ADR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 61 | ALUControl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); 62 | ALUOP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 63 | ALUOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 64 | ALUSrcB : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 65 | Funct : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 66 | Instr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 67 | Op : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 68 | PC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 69 | PCJump : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 70 | PCSrc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 71 | RDCLK : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 72 | ReadData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 73 | RFRD1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 74 | RFRD2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 75 | StateNow : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 76 | WriteData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 77 | WriteReg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 78 | ); 79 | END COMPONENT; 80 | 81 | SIGNAL WD : STD_LOGIC_VECTOR(31 DOWNTO 0); 82 | SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; 83 | SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; 84 | 85 | 86 | BEGIN 87 | 88 | 89 | 90 | b2v_dt : digtube 91 | GENERIC MAP(wid => 6 92 | ) 93 | PORT MAP(clk => clk_dt, 94 | reset => SYNTHESIZED_WIRE_3, 95 | en => SYNTHESIZED_WIRE_1, 96 | data => WD(23 DOWNTO 0), 97 | dt_data => data, 98 | dt_sel => sel); 99 | 100 | 101 | SYNTHESIZED_WIRE_3 <= NOT(reset); 102 | 103 | 104 | 105 | b2v_inst1 : mips_computer 106 | PORT MAP(clk => clk, 107 | reset => SYNTHESIZED_WIRE_3, 108 | MemWrite => SYNTHESIZED_WIRE_1, 109 | StateNow => state, 110 | WriteData => WD); 111 | 112 | 113 | END bdf_type; -------------------------------------------------------------------------------- /src/fsm.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; use IEEE.STD_LOGIC_1164.all; 2 | 3 | entity fsm is -- finite state machine 4 | port(clk,reset :in std_logic; 5 | Opcode :in std_logic_vector(5 downto 0); 6 | MemtoReg,RegDst :out std_logic; 7 | IorD :out std_logic; 8 | ALUSrcB,PCSrc :out std_logic_vector(1 downto 0); 9 | AluSrcA,IRWrite :out std_logic; 10 | MemWrite,PCWrite:out std_logic; 11 | Branch,RegWrite :out std_logic; 12 | ALUOp :out std_logic_vector(1 downto 0); 13 | StateNow :out std_logic_vector(3 downto 0) 14 | ); 15 | end; 16 | architecture behave of fsm is 17 | type StateType is( 18 | S_FECTH, 19 | S_DECODE, 20 | S_MEMADR, 21 | S_MEMREAD, 22 | S_MEMWRITEBACK, 23 | S_MEMWRITE, 24 | S_EXECUTE, 25 | S_ALUWRITEBACK, 26 | S_BRANCH, 27 | S_ADDIEXEC, 28 | S_ADDIWRITEBACK, 29 | S_JUMP 30 | ); 31 | 32 | constant OP_RTYPE :std_logic_vector(5 downto 0):="000000"; 33 | constant OP_LW :std_logic_vector(5 downto 0):="100011"; 34 | constant OP_SW :std_logic_vector(5 downto 0):="101011"; 35 | constant OP_BEQ :std_logic_vector(5 downto 0):="000100"; 36 | constant OP_ADDI :std_logic_vector(5 downto 0):="001000"; 37 | constant OP_J :std_logic_vector(5 downto 0):="000010"; 38 | 39 | signal state,nextState:StateType; 40 | begin 41 | process(all) is 42 | begin 43 | if(reset='1') then 44 | state<= S_FECTH; 45 | elsif rising_edge(clk) then 46 | state<=nextState; 47 | end if; 48 | end process; 49 | nextState <= S_DECODE when(state=S_FECTH) else 50 | S_MEMADR when((state=S_DECODE)and((Opcode=OP_LW)or(Opcode=OP_SW))) else 51 | S_BRANCH when((state=S_DECODE) and(Opcode=OP_BEQ)) else 52 | S_ADDIEXEC when((state=S_DECODE) and(Opcode=OP_ADDI)) else 53 | S_JUMP when((state=S_DECODE) and(Opcode=OP_J)) else 54 | S_MEMREAD when((state=S_MEMADR) and(Opcode=OP_LW))else 55 | S_MEMWRITE when((state=S_MEMADR) and(Opcode=OP_SW)) else 56 | S_MEMWRITEBACK when(state=S_MEMREAD) else 57 | S_ALUWRITEBACK when(state=S_EXECUTE) else 58 | S_ADDIWRITEBACK when(state=S_ADDIEXEC) else 59 | S_FECTH when((state=S_MEMWRITEBACK) 60 | or(state=S_MEMWRITE) 61 | or(state=S_ALUWRITEBACK) 62 | or(state=S_BRANCH) 63 | or(state=S_ADDIWRITEBACK) 64 | or(state=S_JUMP))else 65 | S_EXECUTE; 66 | with state select 67 | IorD <= '1' when S_MEMREAD|S_MEMWRITE, 68 | '0' when others; 69 | with state select 70 | AluSrcA <= '1' when S_EXECUTE|S_BRANCH|S_ADDIEXEC|S_MEMADR, 71 | '0' when others; 72 | with state select 73 | RegDst <= '1' when S_ALUWRITEBACK, 74 | '0' when others; 75 | with state select 76 | MemtoReg<= '1' when S_MEMWRITEBACK, 77 | '0' when others; 78 | with state select 79 | ALUSrcB <= "01" when S_FECTH, 80 | "10" when S_ADDIEXEC|S_MEMADR, 81 | "11" when S_DECODE, 82 | "00" when others; 83 | with state select 84 | ALUOp <= "01" when S_BRANCH, 85 | "10" when S_EXECUTE, 86 | "00" when others; 87 | with state select 88 | PCSrc <= "01" when S_BRANCH, 89 | "10" when S_JUMP, 90 | "00" when others; 91 | with state select 92 | IRWrite <= '1' when S_FECTH, 93 | '0' when others; 94 | with state select 95 | PCWrite <= '1' when S_FECTH|S_JUMP, 96 | '0' when others; 97 | with state select 98 | Branch <= '1' when S_BRANCH, 99 | '0' when others; 100 | with state select 101 | MemWrite<= '1' when S_MEMWRITE, 102 | '0' when others; 103 | with state select 104 | RegWrite<= '1' when S_MEMWRITEBACK|S_ALUWRITEBACK|S_ADDIWRITEBACK, 105 | '0' when others; 106 | with state select StateNow<= 107 | x"0" when S_FECTH, 108 | x"1" when S_DECODE, 109 | x"2" when S_MEMADR, 110 | x"3" when S_MEMREAD, 111 | x"4" when S_MEMWRITEBACK, 112 | x"5" when S_MEMWRITE, 113 | x"6" when S_EXECUTE, 114 | x"7" when S_ALUWRITEBACK, 115 | x"8" when S_BRANCH, 116 | x"9" when S_ADDIEXEC, 117 | x"A" when S_ADDIWRITEBACK, 118 | x"B" when S_JUMP; 119 | end; -------------------------------------------------------------------------------- /src/mips_fpga.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 184 224) 24 | (text "mips_fpga" (rect 5 0 47 12)(font "Arial" )) 25 | (text "inst" (rect 8 192 20 204)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_dt" (rect 0 0 23 12)(font "Arial" )) 30 | (text "clk_dt" (rect 21 27 44 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "a" (rect 0 0 4 12)(font "Arial" )) 37 | (text "a" (rect 21 43 25 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "b" (rect 0 0 4 12)(font "Arial" )) 44 | (text "b" (rect 21 59 25 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "c" (rect 0 0 4 12)(font "Arial" )) 51 | (text "c" (rect 21 75 25 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "d" (rect 0 0 4 12)(font "Arial" )) 58 | (text "d" (rect 21 91 25 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 1)) 60 | ) 61 | (port 62 | (pt 168 32) 63 | (output) 64 | (text "memwrite" (rect 0 0 38 12)(font "Arial" )) 65 | (text "memwrite" (rect 109 27 147 39)(font "Arial" )) 66 | (line (pt 168 32)(pt 152 32)(line_width 1)) 67 | ) 68 | (port 69 | (pt 168 48) 70 | (output) 71 | (text "btnWe" (rect 0 0 27 12)(font "Arial" )) 72 | (text "btnWe" (rect 120 43 147 55)(font "Arial" )) 73 | (line (pt 168 48)(pt 152 48)(line_width 1)) 74 | ) 75 | (port 76 | (pt 168 64) 77 | (output) 78 | (text "adr[31..0]" (rect 0 0 36 12)(font "Arial" )) 79 | (text "adr[31..0]" (rect 111 59 147 71)(font "Arial" )) 80 | (line (pt 168 64)(pt 152 64)(line_width 3)) 81 | ) 82 | (port 83 | (pt 168 80) 84 | (output) 85 | (text "data[7..0]" (rect 0 0 36 12)(font "Arial" )) 86 | (text "data[7..0]" (rect 111 75 147 87)(font "Arial" )) 87 | (line (pt 168 80)(pt 152 80)(line_width 3)) 88 | ) 89 | (port 90 | (pt 168 96) 91 | (output) 92 | (text "pc[15..0]" (rect 0 0 33 12)(font "Arial" )) 93 | (text "pc[15..0]" (rect 114 91 147 103)(font "Arial" )) 94 | (line (pt 168 96)(pt 152 96)(line_width 3)) 95 | ) 96 | (port 97 | (pt 168 112) 98 | (output) 99 | (text "rdata[31..0]" (rect 0 0 43 12)(font "Arial" )) 100 | (text "rdata[31..0]" (rect 104 107 147 119)(font "Arial" )) 101 | (line (pt 168 112)(pt 152 112)(line_width 3)) 102 | ) 103 | (port 104 | (pt 168 128) 105 | (output) 106 | (text "rdio[31..0]" (rect 0 0 37 12)(font "Arial" )) 107 | (text "rdio[31..0]" (rect 110 123 147 135)(font "Arial" )) 108 | (line (pt 168 128)(pt 152 128)(line_width 3)) 109 | ) 110 | (port 111 | (pt 168 144) 112 | (output) 113 | (text "sel[5..0]" (rect 0 0 30 12)(font "Arial" )) 114 | (text "sel[5..0]" (rect 117 139 147 151)(font "Arial" )) 115 | (line (pt 168 144)(pt 152 144)(line_width 3)) 116 | ) 117 | (port 118 | (pt 168 160) 119 | (output) 120 | (text "state[3..0]" (rect 0 0 38 12)(font "Arial" )) 121 | (text "state[3..0]" (rect 109 155 147 167)(font "Arial" )) 122 | (line (pt 168 160)(pt 152 160)(line_width 3)) 123 | ) 124 | (port 125 | (pt 168 176) 126 | (output) 127 | (text "wdata[31..0]" (rect 0 0 46 12)(font "Arial" )) 128 | (text "wdata[31..0]" (rect 101 171 147 183)(font "Arial" )) 129 | (line (pt 168 176)(pt 152 176)(line_width 3)) 130 | ) 131 | (drawing 132 | (rectangle (rect 16 16 152 192)(line_width 1)) 133 | ) 134 | ) 135 | -------------------------------------------------------------------------------- /src/fsm.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 232 288) 24 | (text "fsm" (rect 5 0 21 12)(font "Arial" )) 25 | (text "inst" (rect 8 256 20 268)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "reset" (rect 0 0 20 12)(font "Arial" )) 37 | (text "reset" (rect 21 43 41 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "Opcode[5..0]" (rect 0 0 50 12)(font "Arial" )) 44 | (text "Opcode[5..0]" (rect 21 59 71 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 216 32) 49 | (output) 50 | (text "MemtoReg" (rect 0 0 46 12)(font "Arial" )) 51 | (text "MemtoReg" (rect 149 27 195 39)(font "Arial" )) 52 | (line (pt 216 32)(pt 200 32)(line_width 1)) 53 | ) 54 | (port 55 | (pt 216 48) 56 | (output) 57 | (text "RegDst" (rect 0 0 31 12)(font "Arial" )) 58 | (text "RegDst" (rect 164 43 195 55)(font "Arial" )) 59 | (line (pt 216 48)(pt 200 48)(line_width 1)) 60 | ) 61 | (port 62 | (pt 216 64) 63 | (output) 64 | (text "IorD" (rect 0 0 17 12)(font "Arial" )) 65 | (text "IorD" (rect 178 59 195 71)(font "Arial" )) 66 | (line (pt 216 64)(pt 200 64)(line_width 1)) 67 | ) 68 | (port 69 | (pt 216 80) 70 | (output) 71 | (text "ALUSrcB[1..0]" (rect 0 0 60 12)(font "Arial" )) 72 | (text "ALUSrcB[1..0]" (rect 135 75 195 87)(font "Arial" )) 73 | (line (pt 216 80)(pt 200 80)(line_width 3)) 74 | ) 75 | (port 76 | (pt 216 96) 77 | (output) 78 | (text "PCSrc[1..0]" (rect 0 0 46 12)(font "Arial" )) 79 | (text "PCSrc[1..0]" (rect 149 91 195 103)(font "Arial" )) 80 | (line (pt 216 96)(pt 200 96)(line_width 3)) 81 | ) 82 | (port 83 | (pt 216 112) 84 | (output) 85 | (text "AluSrcA" (rect 0 0 36 12)(font "Arial" )) 86 | (text "AluSrcA" (rect 159 107 195 119)(font "Arial" )) 87 | (line (pt 216 112)(pt 200 112)(line_width 1)) 88 | ) 89 | (port 90 | (pt 216 128) 91 | (output) 92 | (text "IRWrite" (rect 0 0 33 12)(font "Arial" )) 93 | (text "IRWrite" (rect 162 123 195 135)(font "Arial" )) 94 | (line (pt 216 128)(pt 200 128)(line_width 1)) 95 | ) 96 | (port 97 | (pt 216 144) 98 | (output) 99 | (text "MemWrite" (rect 0 0 43 12)(font "Arial" )) 100 | (text "MemWrite" (rect 152 139 195 151)(font "Arial" )) 101 | (line (pt 216 144)(pt 200 144)(line_width 1)) 102 | ) 103 | (port 104 | (pt 216 160) 105 | (output) 106 | (text "PCWrite" (rect 0 0 35 12)(font "Arial" )) 107 | (text "PCWrite" (rect 160 155 195 167)(font "Arial" )) 108 | (line (pt 216 160)(pt 200 160)(line_width 1)) 109 | ) 110 | (port 111 | (pt 216 176) 112 | (output) 113 | (text "Branch" (rect 0 0 28 12)(font "Arial" )) 114 | (text "Branch" (rect 167 171 195 183)(font "Arial" )) 115 | (line (pt 216 176)(pt 200 176)(line_width 1)) 116 | ) 117 | (port 118 | (pt 216 192) 119 | (output) 120 | (text "RegWrite" (rect 0 0 40 12)(font "Arial" )) 121 | (text "RegWrite" (rect 155 187 195 199)(font "Arial" )) 122 | (line (pt 216 192)(pt 200 192)(line_width 1)) 123 | ) 124 | (port 125 | (pt 216 208) 126 | (output) 127 | (text "ALUOp[1..0]" (rect 0 0 51 12)(font "Arial" )) 128 | (text "ALUOp[1..0]" (rect 144 203 195 215)(font "Arial" )) 129 | (line (pt 216 208)(pt 200 208)(line_width 3)) 130 | ) 131 | (port 132 | (pt 216 224) 133 | (output) 134 | (text "StateNow[3..0]" (rect 0 0 57 12)(font "Arial" )) 135 | (text "StateNow[3..0]" (rect 138 219 195 231)(font "Arial" )) 136 | (line (pt 216 224)(pt 200 224)(line_width 3)) 137 | ) 138 | (drawing 139 | (rectangle (rect 16 16 200 256)(line_width 1)) 140 | ) 141 | ) 142 | -------------------------------------------------------------------------------- /src/mips_computer.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 21 | # Date created = 00:43:44 June 29, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # mips_computer_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV E" 40 | set_global_assignment -name DEVICE EP4CE6F17C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY mips_fpga 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:43:44 JUNE 29, 2018" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 49 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" 50 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 51 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation 52 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 53 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 54 | set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 55 | set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF 56 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 57 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 58 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 59 | set_location_assignment PIN_N16 -to data[6] 60 | set_location_assignment PIN_R14 -to data[7] 61 | set_location_assignment PIN_P16 -to data[5] 62 | set_location_assignment PIN_T15 -to data[4] 63 | set_location_assignment PIN_P15 -to data[3] 64 | set_location_assignment PIN_N12 -to data[2] 65 | set_location_assignment PIN_N15 -to data[1] 66 | set_location_assignment PIN_R16 -to data[0] 67 | set_location_assignment PIN_M11 -to sel[0] 68 | set_location_assignment PIN_P11 -to sel[1] 69 | set_location_assignment PIN_N11 -to sel[2] 70 | set_location_assignment PIN_M10 -to sel[3] 71 | set_location_assignment PIN_P9 -to sel[4] 72 | set_location_assignment PIN_N9 -to sel[5] 73 | set_location_assignment PIN_N13 -to reset 74 | set_location_assignment PIN_M15 -to clk 75 | set_location_assignment PIN_E1 -to clk_dt 76 | set_location_assignment PIN_E10 -to state[3] 77 | set_location_assignment PIN_F9 -to state[2] 78 | set_location_assignment PIN_C9 -to state[1] 79 | set_location_assignment PIN_D9 -to state[0] 80 | set_global_assignment -name SMART_RECOMPILE OFF 81 | set_location_assignment PIN_M2 -to rxd 82 | set_global_assignment -name VHDL_FILE clkslower.vhd 83 | set_global_assignment -name VHDL_FILE ioselector.vhd 84 | set_global_assignment -name VHDL_FILE iomemory.vhd 85 | set_global_assignment -name VHDL_FILE mux2_sl.vhd 86 | set_global_assignment -name BDF_FILE datapath.bdf 87 | set_global_assignment -name BDF_FILE mips_fpga.bdf 88 | set_global_assignment -name BDF_FILE mips_computer.bdf 89 | set_global_assignment -name VHDL_FILE uart_rx.vhd 90 | set_global_assignment -name VHDL_FILE uart_clk.vhd 91 | set_global_assignment -name VHDL_FILE notgate.vhd 92 | set_global_assignment -name VHDL_FILE digtube.vhd 93 | set_global_assignment -name VHDL_FILE aludec.vhd 94 | set_global_assignment -name VHDL_FILE fsm.vhd 95 | set_global_assignment -name VHDL_FILE beqctrl.vhd 96 | set_global_assignment -name VHDL_FILE jmpmerge.vhd 97 | set_global_assignment -name VHDL_FILE intvec.vhd 98 | set_global_assignment -name VHDL_FILE mux4.vhd 99 | set_global_assignment -name VHDL_FILE signext.vhd 100 | set_global_assignment -name VHDL_FILE shiftleft.vhd 101 | set_global_assignment -name VHDL_FILE regfile.vhd 102 | set_global_assignment -name VHDL_FILE mux2.vhd 103 | set_global_assignment -name VHDL_FILE memory.vhd 104 | set_global_assignment -name VHDL_FILE imem.vhd 105 | set_global_assignment -name VHDL_FILE flopr.vhd 106 | set_global_assignment -name VHDL_FILE flopenr.vhd 107 | set_global_assignment -name VHDL_FILE alu.vhd 108 | set_global_assignment -name VHDL_FILE adder.vhd 109 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /src/datapath.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 248 288) 24 | (text "datapath" (rect 5 0 38 12)(font "Arial" )) 25 | (text "inst" (rect 8 256 20 268)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) 30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "IorD" (rect 0 0 17 12)(font "Arial" )) 37 | (text "IorD" (rect 21 43 38 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "RegDst" (rect 0 0 31 12)(font "Arial" )) 44 | (text "RegDst" (rect 21 59 52 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "RegWrite" (rect 0 0 40 12)(font "Arial" )) 51 | (text "RegWrite" (rect 21 75 61 87)(font "Arial" )) 52 | (line (pt 0 80)(pt 16 80)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 96) 56 | (input) 57 | (text "ALUSrcA" (rect 0 0 43 12)(font "Arial" )) 58 | (text "ALUSrcA" (rect 21 91 64 103)(font "Arial" )) 59 | (line (pt 0 96)(pt 16 96)(line_width 1)) 60 | ) 61 | (port 62 | (pt 0 112) 63 | (input) 64 | (text "Branch" (rect 0 0 28 12)(font "Arial" )) 65 | (text "Branch" (rect 21 107 49 119)(font "Arial" )) 66 | (line (pt 0 112)(pt 16 112)(line_width 1)) 67 | ) 68 | (port 69 | (pt 0 128) 70 | (input) 71 | (text "PCWrite" (rect 0 0 35 12)(font "Arial" )) 72 | (text "PCWrite" (rect 21 123 56 135)(font "Arial" )) 73 | (line (pt 0 128)(pt 16 128)(line_width 1)) 74 | ) 75 | (port 76 | (pt 0 144) 77 | (input) 78 | (text "IRWrite" (rect 0 0 33 12)(font "Arial" )) 79 | (text "IRWrite" (rect 21 139 54 151)(font "Arial" )) 80 | (line (pt 0 144)(pt 16 144)(line_width 1)) 81 | ) 82 | (port 83 | (pt 0 160) 84 | (input) 85 | (text "reset" (rect 0 0 20 12)(font "Arial" )) 86 | (text "reset" (rect 21 155 41 167)(font "Arial" )) 87 | (line (pt 0 160)(pt 16 160)(line_width 1)) 88 | ) 89 | (port 90 | (pt 0 176) 91 | (input) 92 | (text "MemtoReg" (rect 0 0 46 12)(font "Arial" )) 93 | (text "MemtoReg" (rect 21 171 67 183)(font "Arial" )) 94 | (line (pt 0 176)(pt 16 176)(line_width 1)) 95 | ) 96 | (port 97 | (pt 0 192) 98 | (input) 99 | (text "ALUControl[2..0]" (rect 0 0 69 12)(font "Arial" )) 100 | (text "ALUControl[2..0]" (rect 21 187 90 199)(font "Arial" )) 101 | (line (pt 0 192)(pt 16 192)(line_width 3)) 102 | ) 103 | (port 104 | (pt 0 208) 105 | (input) 106 | (text "AluSrcB[1..0]" (rect 0 0 53 12)(font "Arial" )) 107 | (text "AluSrcB[1..0]" (rect 21 203 74 215)(font "Arial" )) 108 | (line (pt 0 208)(pt 16 208)(line_width 3)) 109 | ) 110 | (port 111 | (pt 0 224) 112 | (input) 113 | (text "PCSrc[1..0]" (rect 0 0 46 12)(font "Arial" )) 114 | (text "PCSrc[1..0]" (rect 21 219 67 231)(font "Arial" )) 115 | (line (pt 0 224)(pt 16 224)(line_width 3)) 116 | ) 117 | (port 118 | (pt 0 240) 119 | (input) 120 | (text "ReadData[31..0]" (rect 0 0 64 12)(font "Arial" )) 121 | (text "ReadData[31..0]" (rect 21 235 85 247)(font "Arial" )) 122 | (line (pt 0 240)(pt 16 240)(line_width 3)) 123 | ) 124 | (port 125 | (pt 232 32) 126 | (output) 127 | (text "Adr[31..0]" (rect 0 0 40 12)(font "Arial" )) 128 | (text "Adr[31..0]" (rect 171 27 211 39)(font "Arial" )) 129 | (line (pt 232 32)(pt 216 32)(line_width 3)) 130 | ) 131 | (port 132 | (pt 232 48) 133 | (output) 134 | (text "ALUOut[31..0]" (rect 0 0 59 12)(font "Arial" )) 135 | (text "ALUOut[31..0]" (rect 152 43 211 55)(font "Arial" )) 136 | (line (pt 232 48)(pt 216 48)(line_width 3)) 137 | ) 138 | (port 139 | (pt 232 64) 140 | (output) 141 | (text "Funct[5..0]" (rect 0 0 42 12)(font "Arial" )) 142 | (text "Funct[5..0]" (rect 169 59 211 71)(font "Arial" )) 143 | (line (pt 232 64)(pt 216 64)(line_width 3)) 144 | ) 145 | (port 146 | (pt 232 80) 147 | (output) 148 | (text "Instr[31..0]" (rect 0 0 41 12)(font "Arial" )) 149 | (text "Instr[31..0]" (rect 170 75 211 87)(font "Arial" )) 150 | (line (pt 232 80)(pt 216 80)(line_width 3)) 151 | ) 152 | (port 153 | (pt 232 96) 154 | (output) 155 | (text "Op[5..0]" (rect 0 0 31 12)(font "Arial" )) 156 | (text "Op[5..0]" (rect 180 91 211 103)(font "Arial" )) 157 | (line (pt 232 96)(pt 216 96)(line_width 3)) 158 | ) 159 | (port 160 | (pt 232 112) 161 | (output) 162 | (text "pc[31..0]" (rect 0 0 33 12)(font "Arial" )) 163 | (text "pc[31..0]" (rect 178 107 211 119)(font "Arial" )) 164 | (line (pt 232 112)(pt 216 112)(line_width 3)) 165 | ) 166 | (port 167 | (pt 232 128) 168 | (output) 169 | (text "PCJump[31..0]" (rect 0 0 59 12)(font "Arial" )) 170 | (text "PCJump[31..0]" (rect 152 123 211 135)(font "Arial" )) 171 | (line (pt 232 128)(pt 216 128)(line_width 3)) 172 | ) 173 | (port 174 | (pt 232 144) 175 | (output) 176 | (text "RDCLK[31..0]" (rect 0 0 59 12)(font "Arial" )) 177 | (text "RDCLK[31..0]" (rect 152 139 211 151)(font "Arial" )) 178 | (line (pt 232 144)(pt 216 144)(line_width 3)) 179 | ) 180 | (port 181 | (pt 232 160) 182 | (output) 183 | (text "RFRD1[31..0]" (rect 0 0 56 12)(font "Arial" )) 184 | (text "RFRD1[31..0]" (rect 155 155 211 167)(font "Arial" )) 185 | (line (pt 232 160)(pt 216 160)(line_width 3)) 186 | ) 187 | (port 188 | (pt 232 176) 189 | (output) 190 | (text "RFRD2[31..0]" (rect 0 0 57 12)(font "Arial" )) 191 | (text "RFRD2[31..0]" (rect 154 171 211 183)(font "Arial" )) 192 | (line (pt 232 176)(pt 216 176)(line_width 3)) 193 | ) 194 | (port 195 | (pt 232 192) 196 | (output) 197 | (text "WriteData[31..0]" (rect 0 0 64 12)(font "Arial" )) 198 | (text "WriteData[31..0]" (rect 147 187 211 199)(font "Arial" )) 199 | (line (pt 232 192)(pt 216 192)(line_width 3)) 200 | ) 201 | (port 202 | (pt 232 208) 203 | (output) 204 | (text "WriteReg[31..0]" (rect 0 0 63 12)(font "Arial" )) 205 | (text "WriteReg[31..0]" (rect 148 203 211 215)(font "Arial" )) 206 | (line (pt 232 208)(pt 216 208)(line_width 3)) 207 | ) 208 | (drawing 209 | (rectangle (rect 16 16 216 256)(line_width 1)) 210 | ) 211 | ) 212 | -------------------------------------------------------------------------------- /src/mips_computer.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | 15 | -- PROGRAM "Quartus Prime" 16 | -- VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" 17 | -- CREATED "Mon Jul 02 21:10:23 2018" 18 | 19 | LIBRARY ieee; 20 | USE ieee.std_logic_1164.all; 21 | 22 | LIBRARY work; 23 | 24 | ENTITY mips_computer IS 25 | PORT 26 | ( 27 | clk : IN STD_LOGIC; 28 | reset : IN STD_LOGIC; 29 | MemtoReg : OUT STD_LOGIC; 30 | RegDst : OUT STD_LOGIC; 31 | IorD : OUT STD_LOGIC; 32 | ALUSrcA : OUT STD_LOGIC; 33 | IRWrite : OUT STD_LOGIC; 34 | MemWrite : OUT STD_LOGIC; 35 | PCWrite : OUT STD_LOGIC; 36 | Branch : OUT STD_LOGIC; 37 | RegWrite : OUT STD_LOGIC; 38 | ADR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 39 | ALUControl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); 40 | ALUOP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 41 | ALUOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 42 | ALUSrcB : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 43 | Funct : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 44 | Instr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 45 | Op : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 46 | PC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 47 | PCJump : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 48 | PCSrc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 49 | RDCLK : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 50 | ReadData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 51 | RFRD1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 52 | RFRD2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 53 | StateNow : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 54 | WriteData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 55 | WriteReg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 56 | ); 57 | END mips_computer; 58 | 59 | ARCHITECTURE bdf_type OF mips_computer IS 60 | 61 | COMPONENT fsm 62 | PORT(clk : IN STD_LOGIC; 63 | reset : IN STD_LOGIC; 64 | Opcode : IN STD_LOGIC_VECTOR(5 DOWNTO 0); 65 | MemtoReg : OUT STD_LOGIC; 66 | RegDst : OUT STD_LOGIC; 67 | IorD : OUT STD_LOGIC; 68 | AluSrcA : OUT STD_LOGIC; 69 | IRWrite : OUT STD_LOGIC; 70 | MemWrite : OUT STD_LOGIC; 71 | PCWrite : OUT STD_LOGIC; 72 | Branch : OUT STD_LOGIC; 73 | RegWrite : OUT STD_LOGIC; 74 | ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 75 | ALUSrcB : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 76 | PCSrc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); 77 | StateNow : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 78 | ); 79 | END COMPONENT; 80 | 81 | COMPONENT imem 82 | PORT(clk : IN STD_LOGIC; 83 | reset : IN STD_LOGIC; 84 | we : IN STD_LOGIC; 85 | a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 86 | wd : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 87 | rd : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 88 | ); 89 | END COMPONENT; 90 | 91 | COMPONENT aludec 92 | PORT(aluop : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 93 | funct : IN STD_LOGIC_VECTOR(5 DOWNTO 0); 94 | alucontrol : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) 95 | ); 96 | END COMPONENT; 97 | 98 | COMPONENT datapath 99 | PORT(clk : IN STD_LOGIC; 100 | IorD : IN STD_LOGIC; 101 | RegDst : IN STD_LOGIC; 102 | RegWrite : IN STD_LOGIC; 103 | ALUSrcA : IN STD_LOGIC; 104 | Branch : IN STD_LOGIC; 105 | PCWrite : IN STD_LOGIC; 106 | IRWrite : IN STD_LOGIC; 107 | reset : IN STD_LOGIC; 108 | MemtoReg : IN STD_LOGIC; 109 | ALUControl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 110 | AluSrcB : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 111 | PCSrc : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 112 | ReadData : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 113 | Adr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 114 | ALUOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 115 | Funct : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 116 | Instr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 117 | Op : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 118 | pc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 119 | PCJump : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 120 | RDCLK : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 121 | RFRD1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 122 | RFRD2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 123 | WriteData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 124 | WriteReg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 125 | ); 126 | END COMPONENT; 127 | 128 | SIGNAL adr_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 129 | SIGNAL alucontrol_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(2 DOWNTO 0); 130 | SIGNAL aluop_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(1 DOWNTO 0); 131 | SIGNAL alusrca_ALTERA_SYNTHESIZED : STD_LOGIC; 132 | SIGNAL alusrcb_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(1 DOWNTO 0); 133 | SIGNAL branch_ALTERA_SYNTHESIZED : STD_LOGIC; 134 | SIGNAL funct_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(5 DOWNTO 0); 135 | SIGNAL iord_ALTERA_SYNTHESIZED : STD_LOGIC; 136 | SIGNAL irwrite_ALTERA_SYNTHESIZED : STD_LOGIC; 137 | SIGNAL memtoreg_ALTERA_SYNTHESIZED : STD_LOGIC; 138 | SIGNAL memwrite_ALTERA_SYNTHESIZED : STD_LOGIC; 139 | SIGNAL op_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(5 DOWNTO 0); 140 | SIGNAL pcsrc_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(1 DOWNTO 0); 141 | SIGNAL pcwrite_ALTERA_SYNTHESIZED : STD_LOGIC; 142 | SIGNAL readdata_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 143 | SIGNAL regdst_ALTERA_SYNTHESIZED : STD_LOGIC; 144 | SIGNAL regwrite_ALTERA_SYNTHESIZED : STD_LOGIC; 145 | SIGNAL writedata_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 146 | 147 | 148 | BEGIN 149 | 150 | 151 | 152 | b2v_inst : fsm 153 | PORT MAP(clk => clk, 154 | reset => reset, 155 | Opcode => op_ALTERA_SYNTHESIZED, 156 | MemtoReg => memtoreg_ALTERA_SYNTHESIZED, 157 | RegDst => regdst_ALTERA_SYNTHESIZED, 158 | IorD => iord_ALTERA_SYNTHESIZED, 159 | AluSrcA => alusrca_ALTERA_SYNTHESIZED, 160 | IRWrite => irwrite_ALTERA_SYNTHESIZED, 161 | MemWrite => memwrite_ALTERA_SYNTHESIZED, 162 | PCWrite => pcwrite_ALTERA_SYNTHESIZED, 163 | Branch => branch_ALTERA_SYNTHESIZED, 164 | RegWrite => regwrite_ALTERA_SYNTHESIZED, 165 | ALUOp => aluop_ALTERA_SYNTHESIZED, 166 | ALUSrcB => alusrcb_ALTERA_SYNTHESIZED, 167 | PCSrc => pcsrc_ALTERA_SYNTHESIZED, 168 | StateNow => StateNow); 169 | 170 | 171 | b2v_inst1 : imem 172 | PORT MAP(clk => clk, 173 | reset => reset, 174 | we => memwrite_ALTERA_SYNTHESIZED, 175 | a => adr_ALTERA_SYNTHESIZED, 176 | wd => writedata_ALTERA_SYNTHESIZED, 177 | rd => readdata_ALTERA_SYNTHESIZED); 178 | 179 | 180 | b2v_inst3 : aludec 181 | PORT MAP(aluop => aluop_ALTERA_SYNTHESIZED, 182 | funct => funct_ALTERA_SYNTHESIZED, 183 | alucontrol => alucontrol_ALTERA_SYNTHESIZED); 184 | 185 | 186 | b2v_inst9 : datapath 187 | PORT MAP(clk => clk, 188 | IorD => iord_ALTERA_SYNTHESIZED, 189 | RegDst => regdst_ALTERA_SYNTHESIZED, 190 | RegWrite => regwrite_ALTERA_SYNTHESIZED, 191 | ALUSrcA => alusrca_ALTERA_SYNTHESIZED, 192 | Branch => branch_ALTERA_SYNTHESIZED, 193 | PCWrite => pcwrite_ALTERA_SYNTHESIZED, 194 | IRWrite => irwrite_ALTERA_SYNTHESIZED, 195 | reset => reset, 196 | MemtoReg => memtoreg_ALTERA_SYNTHESIZED, 197 | ALUControl => alucontrol_ALTERA_SYNTHESIZED, 198 | AluSrcB => alusrcb_ALTERA_SYNTHESIZED, 199 | PCSrc => pcsrc_ALTERA_SYNTHESIZED, 200 | ReadData => readdata_ALTERA_SYNTHESIZED, 201 | Adr => adr_ALTERA_SYNTHESIZED, 202 | ALUOut => ALUOut, 203 | Funct => funct_ALTERA_SYNTHESIZED, 204 | Instr => Instr, 205 | Op => op_ALTERA_SYNTHESIZED, 206 | pc => PC, 207 | PCJump => PCJump, 208 | RDCLK => RDCLK, 209 | RFRD1 => RFRD1, 210 | RFRD2 => RFRD2, 211 | WriteData => writedata_ALTERA_SYNTHESIZED, 212 | WriteReg => WriteReg); 213 | 214 | MemtoReg <= memtoreg_ALTERA_SYNTHESIZED; 215 | RegDst <= regdst_ALTERA_SYNTHESIZED; 216 | IorD <= iord_ALTERA_SYNTHESIZED; 217 | ALUSrcA <= alusrca_ALTERA_SYNTHESIZED; 218 | IRWrite <= irwrite_ALTERA_SYNTHESIZED; 219 | MemWrite <= memwrite_ALTERA_SYNTHESIZED; 220 | PCWrite <= pcwrite_ALTERA_SYNTHESIZED; 221 | Branch <= branch_ALTERA_SYNTHESIZED; 222 | RegWrite <= regwrite_ALTERA_SYNTHESIZED; 223 | ADR <= adr_ALTERA_SYNTHESIZED; 224 | ALUControl <= alucontrol_ALTERA_SYNTHESIZED; 225 | ALUOP <= aluop_ALTERA_SYNTHESIZED; 226 | ALUSrcB <= alusrcb_ALTERA_SYNTHESIZED; 227 | Funct <= funct_ALTERA_SYNTHESIZED; 228 | Op <= op_ALTERA_SYNTHESIZED; 229 | PCSrc <= pcsrc_ALTERA_SYNTHESIZED; 230 | ReadData <= readdata_ALTERA_SYNTHESIZED; 231 | WriteData <= writedata_ALTERA_SYNTHESIZED; 232 | 233 | END bdf_type; -------------------------------------------------------------------------------- /src/mips_computer.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 16 16 248 496) 24 | (text "mips_computer" (rect 5 0 114 20)(font "Intel Clear" (font_size 8))) 25 | (text "inst" (rect 8 457 31 476)(font "Intel Clear" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clk_50m" (rect 0 0 60 20)(font "Intel Clear" (font_size 8))) 30 | (text "clk_50m" (rect 21 27 81 47)(font "Intel Clear" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clk" (rect 0 0 20 20)(font "Intel Clear" (font_size 8))) 37 | (text "clk" (rect 21 43 41 63)(font "Intel Clear" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "reset" (rect 0 0 35 20)(font "Intel Clear" (font_size 8))) 44 | (text "reset" (rect 21 59 56 79)(font "Intel Clear" (font_size 8))) 45 | (line (pt 0 64)(pt 16 64)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "rxd" (rect 0 0 22 20)(font "Intel Clear" (font_size 8))) 51 | (text "rxd" (rect 21 75 43 95)(font "Intel Clear" (font_size 8))) 52 | (line (pt 0 80)(pt 16 80)) 53 | ) 54 | (port 55 | (pt 232 32) 56 | (output) 57 | (text "ADR[31..0]" (rect 0 0 74 20)(font "Intel Clear" (font_size 8))) 58 | (text "ADR[31..0]" (rect 137 27 211 47)(font "Intel Clear" (font_size 8))) 59 | (line (pt 232 32)(pt 216 32)(line_width 3)) 60 | ) 61 | (port 62 | (pt 232 48) 63 | (output) 64 | (text "ALUOut[31..0]" (rect 0 0 100 20)(font "Intel Clear" (font_size 8))) 65 | (text "ALUOut[31..0]" (rect 111 43 211 63)(font "Intel Clear" (font_size 8))) 66 | (line (pt 232 48)(pt 216 48)(line_width 3)) 67 | ) 68 | (port 69 | (pt 232 64) 70 | (output) 71 | (text "Funct[5..0]" (rect 0 0 75 20)(font "Intel Clear" (font_size 8))) 72 | (text "Funct[5..0]" (rect 136 59 211 79)(font "Intel Clear" (font_size 8))) 73 | (line (pt 232 64)(pt 216 64)(line_width 3)) 74 | ) 75 | (port 76 | (pt 232 80) 77 | (output) 78 | (text "Instr[31..0]" (rect 0 0 77 20)(font "Intel Clear" (font_size 8))) 79 | (text "Instr[31..0]" (rect 134 75 211 95)(font "Intel Clear" (font_size 8))) 80 | (line (pt 232 80)(pt 216 80)(line_width 3)) 81 | ) 82 | (port 83 | (pt 232 96) 84 | (output) 85 | (text "Op[5..0]" (rect 0 0 56 20)(font "Intel Clear" (font_size 8))) 86 | (text "Op[5..0]" (rect 155 91 211 111)(font "Intel Clear" (font_size 8))) 87 | (line (pt 232 96)(pt 216 96)(line_width 3)) 88 | ) 89 | (port 90 | (pt 232 112) 91 | (output) 92 | (text "PC[31..0]" (rect 0 0 63 20)(font "Intel Clear" (font_size 8))) 93 | (text "PC[31..0]" (rect 148 107 211 127)(font "Intel Clear" (font_size 8))) 94 | (line (pt 232 112)(pt 216 112)(line_width 3)) 95 | ) 96 | (port 97 | (pt 232 128) 98 | (output) 99 | (text "PCJump[31..0]" (rect 0 0 103 20)(font "Intel Clear" (font_size 8))) 100 | (text "PCJump[31..0]" (rect 108 123 211 143)(font "Intel Clear" (font_size 8))) 101 | (line (pt 232 128)(pt 216 128)(line_width 3)) 102 | ) 103 | (port 104 | (pt 232 144) 105 | (output) 106 | (text "RDCLK[31..0]" (rect 0 0 92 20)(font "Intel Clear" (font_size 8))) 107 | (text "RDCLK[31..0]" (rect 119 139 211 159)(font "Intel Clear" (font_size 8))) 108 | (line (pt 232 144)(pt 216 144)(line_width 3)) 109 | ) 110 | (port 111 | (pt 232 160) 112 | (output) 113 | (text "RFRD1[31..0]" (rect 0 0 92 20)(font "Intel Clear" (font_size 8))) 114 | (text "RFRD1[31..0]" (rect 119 155 211 175)(font "Intel Clear" (font_size 8))) 115 | (line (pt 232 160)(pt 216 160)(line_width 3)) 116 | ) 117 | (port 118 | (pt 232 176) 119 | (output) 120 | (text "RFRD2[31..0]" (rect 0 0 92 20)(font "Intel Clear" (font_size 8))) 121 | (text "RFRD2[31..0]" (rect 119 171 211 191)(font "Intel Clear" (font_size 8))) 122 | (line (pt 232 176)(pt 216 176)(line_width 3)) 123 | ) 124 | (port 125 | (pt 232 192) 126 | (output) 127 | (text "WriteData[31..0]" (rect 0 0 115 20)(font "Intel Clear" (font_size 8))) 128 | (text "WriteData[31..0]" (rect 96 187 211 207)(font "Intel Clear" (font_size 8))) 129 | (line (pt 232 192)(pt 216 192)(line_width 3)) 130 | ) 131 | (port 132 | (pt 232 208) 133 | (output) 134 | (text "WriteReg[31..0]" (rect 0 0 108 20)(font "Intel Clear" (font_size 8))) 135 | (text "WriteReg[31..0]" (rect 103 203 211 223)(font "Intel Clear" (font_size 8))) 136 | (line (pt 232 208)(pt 216 208)(line_width 3)) 137 | ) 138 | (port 139 | (pt 232 224) 140 | (output) 141 | (text "ReadData[31..0]" (rect 0 0 113 20)(font "Intel Clear" (font_size 8))) 142 | (text "ReadData[31..0]" (rect 98 219 211 239)(font "Intel Clear" (font_size 8))) 143 | (line (pt 232 224)(pt 216 224)(line_width 3)) 144 | ) 145 | (port 146 | (pt 232 240) 147 | (output) 148 | (text "MemtoReg" (rect 0 0 75 20)(font "Intel Clear" (font_size 8))) 149 | (text "MemtoReg" (rect 136 235 211 255)(font "Intel Clear" (font_size 8))) 150 | (line (pt 232 240)(pt 216 240)) 151 | ) 152 | (port 153 | (pt 232 256) 154 | (output) 155 | (text "RegDst" (rect 0 0 49 20)(font "Intel Clear" (font_size 8))) 156 | (text "RegDst" (rect 162 251 211 271)(font "Intel Clear" (font_size 8))) 157 | (line (pt 232 256)(pt 216 256)) 158 | ) 159 | (port 160 | (pt 232 272) 161 | (output) 162 | (text "IorD" (rect 0 0 30 20)(font "Intel Clear" (font_size 8))) 163 | (text "IorD" (rect 181 267 211 287)(font "Intel Clear" (font_size 8))) 164 | (line (pt 232 272)(pt 216 272)) 165 | ) 166 | (port 167 | (pt 232 288) 168 | (output) 169 | (text "ALUSrcB[1..0]" (rect 0 0 95 20)(font "Intel Clear" (font_size 8))) 170 | (text "ALUSrcB[1..0]" (rect 116 283 211 303)(font "Intel Clear" (font_size 8))) 171 | (line (pt 232 288)(pt 216 288)(line_width 3)) 172 | ) 173 | (port 174 | (pt 232 304) 175 | (output) 176 | (text "PCSrc[1..0]" (rect 0 0 76 20)(font "Intel Clear" (font_size 8))) 177 | (text "PCSrc[1..0]" (rect 135 299 211 319)(font "Intel Clear" (font_size 8))) 178 | (line (pt 232 304)(pt 216 304)(line_width 3)) 179 | ) 180 | (port 181 | (pt 232 320) 182 | (output) 183 | (text "ALUSrcA" (rect 0 0 60 20)(font "Intel Clear" (font_size 8))) 184 | (text "ALUSrcA" (rect 151 315 211 335)(font "Intel Clear" (font_size 8))) 185 | (line (pt 232 320)(pt 216 320)) 186 | ) 187 | (port 188 | (pt 232 336) 189 | (output) 190 | (text "IRWrite" (rect 0 0 51 20)(font "Intel Clear" (font_size 8))) 191 | (text "IRWrite" (rect 160 331 211 351)(font "Intel Clear" (font_size 8))) 192 | (line (pt 232 336)(pt 216 336)) 193 | ) 194 | (port 195 | (pt 232 352) 196 | (output) 197 | (text "MemWrite" (rect 0 0 71 20)(font "Intel Clear" (font_size 8))) 198 | (text "MemWrite" (rect 140 347 211 367)(font "Intel Clear" (font_size 8))) 199 | (line (pt 232 352)(pt 216 352)) 200 | ) 201 | (port 202 | (pt 232 368) 203 | (output) 204 | (text "PCWrite" (rect 0 0 56 20)(font "Intel Clear" (font_size 8))) 205 | (text "PCWrite" (rect 155 363 211 383)(font "Intel Clear" (font_size 8))) 206 | (line (pt 232 368)(pt 216 368)) 207 | ) 208 | (port 209 | (pt 232 384) 210 | (output) 211 | (text "Branch" (rect 0 0 49 20)(font "Intel Clear" (font_size 8))) 212 | (text "Branch" (rect 162 379 211 399)(font "Intel Clear" (font_size 8))) 213 | (line (pt 232 384)(pt 216 384)) 214 | ) 215 | (port 216 | (pt 232 400) 217 | (output) 218 | (text "RegWrite" (rect 0 0 63 20)(font "Intel Clear" (font_size 8))) 219 | (text "RegWrite" (rect 148 395 211 415)(font "Intel Clear" (font_size 8))) 220 | (line (pt 232 400)(pt 216 400)) 221 | ) 222 | (port 223 | (pt 232 416) 224 | (output) 225 | (text "ALUOP[1..0]" (rect 0 0 84 20)(font "Intel Clear" (font_size 8))) 226 | (text "ALUOP[1..0]" (rect 127 411 211 431)(font "Intel Clear" (font_size 8))) 227 | (line (pt 232 416)(pt 216 416)(line_width 3)) 228 | ) 229 | (port 230 | (pt 232 432) 231 | (output) 232 | (text "StateNow[3..0]" (rect 0 0 105 20)(font "Intel Clear" (font_size 8))) 233 | (text "StateNow[3..0]" (rect 106 427 211 447)(font "Intel Clear" (font_size 8))) 234 | (line (pt 232 432)(pt 216 432)(line_width 3)) 235 | ) 236 | (port 237 | (pt 232 448) 238 | (output) 239 | (text "ALUControl[2..0]" (rect 0 0 118 20)(font "Intel Clear" (font_size 8))) 240 | (text "ALUControl[2..0]" (rect 93 443 211 463)(font "Intel Clear" (font_size 8))) 241 | (line (pt 232 448)(pt 216 448)(line_width 3)) 242 | ) 243 | (drawing 244 | (rectangle (rect 16 16 216 464)) 245 | ) 246 | ) 247 | -------------------------------------------------------------------------------- /src/datapath.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | 15 | -- PROGRAM "Quartus Prime" 16 | -- VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" 17 | -- CREATED "Sun Jul 01 04:28:55 2018" 18 | 19 | LIBRARY ieee; 20 | USE ieee.std_logic_1164.all; 21 | 22 | LIBRARY work; 23 | 24 | ENTITY datapath IS 25 | PORT 26 | ( 27 | clk : IN STD_LOGIC; 28 | IorD : IN STD_LOGIC; 29 | RegDst : IN STD_LOGIC; 30 | RegWrite : IN STD_LOGIC; 31 | ALUSrcA : IN STD_LOGIC; 32 | Branch : IN STD_LOGIC; 33 | PCWrite : IN STD_LOGIC; 34 | IRWrite : IN STD_LOGIC; 35 | reset : IN STD_LOGIC; 36 | MemtoReg : IN STD_LOGIC; 37 | ALUControl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 38 | AluSrcB : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 39 | PCSrc : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 40 | ReadData : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 41 | Adr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 42 | ALUOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 43 | Funct : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 44 | Instr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 45 | Op : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); 46 | pc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 47 | PCJump : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 48 | RDCLK : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 49 | RFRD1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 50 | RFRD2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 51 | WriteData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 52 | WriteReg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 53 | ); 54 | END datapath; 55 | 56 | ARCHITECTURE bdf_type OF datapath IS 57 | 58 | COMPONENT flopenr 59 | GENERIC (width : INTEGER 60 | ); 61 | PORT(clk : IN STD_LOGIC; 62 | reset : IN STD_LOGIC; 63 | en : IN STD_LOGIC; 64 | d : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 65 | q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0) 66 | ); 67 | END COMPONENT; 68 | 69 | COMPONENT signext 70 | PORT(a : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 71 | y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 72 | ); 73 | END COMPONENT; 74 | 75 | COMPONENT mux2 76 | GENERIC (width : INTEGER 77 | ); 78 | PORT(s : IN STD_LOGIC; 79 | d0 : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 80 | d1 : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 81 | y : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0) 82 | ); 83 | END COMPONENT; 84 | 85 | COMPONENT flopr 86 | GENERIC (width : INTEGER 87 | ); 88 | PORT(clk : IN STD_LOGIC; 89 | reset : IN STD_LOGIC; 90 | d : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 91 | q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0) 92 | ); 93 | END COMPONENT; 94 | 95 | COMPONENT regfile 96 | PORT(clk : IN STD_LOGIC; 97 | we3 : IN STD_LOGIC; 98 | ra1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); 99 | ra2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); 100 | wa3 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); 101 | wd3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 102 | rd1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 103 | rd2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 104 | ); 105 | END COMPONENT; 106 | 107 | COMPONENT mux4 108 | GENERIC (width : INTEGER 109 | ); 110 | PORT(d0 : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 111 | d1 : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 112 | d2 : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 113 | d3 : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); 114 | s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 115 | y : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0) 116 | ); 117 | END COMPONENT; 118 | 119 | COMPONENT sl2 120 | PORT(a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 121 | y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 122 | ); 123 | END COMPONENT; 124 | 125 | COMPONENT intvec 126 | GENERIC (int : INTEGER; 127 | width : INTEGER 128 | ); 129 | PORT( y : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0) 130 | ); 131 | END COMPONENT; 132 | 133 | COMPONENT alu 134 | PORT(a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 135 | alucontrol : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 136 | b : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 137 | zero : OUT STD_LOGIC; 138 | result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 139 | ); 140 | END COMPONENT; 141 | 142 | COMPONENT jmpmerge 143 | PORT(instr : IN STD_LOGIC_VECTOR(25 DOWNTO 0); 144 | pchi : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 145 | y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 146 | ); 147 | END COMPONENT; 148 | 149 | COMPONENT beqctrl 150 | PORT(zero : IN STD_LOGIC; 151 | branch : IN STD_LOGIC; 152 | pcwrite : IN STD_LOGIC; 153 | pcen : OUT STD_LOGIC 154 | ); 155 | END COMPONENT; 156 | 157 | SIGNAL ALUOut_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 158 | SIGNAL ALUResult : STD_LOGIC_VECTOR(31 DOWNTO 0); 159 | SIGNAL Instr_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 160 | SIGNAL pc_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 161 | SIGNAL PCAdr : STD_LOGIC_VECTOR(31 DOWNTO 0); 162 | SIGNAL PCEn : STD_LOGIC; 163 | SIGNAL PCJump_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 164 | SIGNAL pcNxt : STD_LOGIC_VECTOR(31 DOWNTO 0); 165 | SIGNAL RDCLK_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 166 | SIGNAL RFRD_ALTERA_SYNTHESIZED1 : STD_LOGIC_VECTOR(31 DOWNTO 0); 167 | SIGNAL RFRD_ALTERA_SYNTHESIZED2 : STD_LOGIC_VECTOR(31 DOWNTO 0); 168 | SIGNAL SrcA : STD_LOGIC_VECTOR(31 DOWNTO 0); 169 | SIGNAL WD : STD_LOGIC_VECTOR(31 DOWNTO 0); 170 | SIGNAL WriteReg_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(31 DOWNTO 0); 171 | SIGNAL Zero : STD_LOGIC; 172 | SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(4 DOWNTO 0); 173 | SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); 174 | SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); 175 | SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC_VECTOR(31 DOWNTO 0); 176 | SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC_VECTOR(31 DOWNTO 0); 177 | SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC_VECTOR(31 DOWNTO 0); 178 | SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC_VECTOR(31 DOWNTO 0); 179 | 180 | 181 | BEGIN 182 | 183 | 184 | 185 | b2v_inst : flopenr 186 | GENERIC MAP(width => 32 187 | ) 188 | PORT MAP(clk => clk, 189 | reset => reset, 190 | en => PCEn, 191 | d => pcNxt, 192 | q => pc_ALTERA_SYNTHESIZED); 193 | 194 | 195 | b2v_inst1 : signext 196 | PORT MAP(a => Instr_ALTERA_SYNTHESIZED(15 DOWNTO 0), 197 | y => SYNTHESIZED_WIRE_8); 198 | 199 | 200 | b2v_inst11 : mux2 201 | GENERIC MAP(width => 32 202 | ) 203 | PORT MAP(s => IorD, 204 | d0 => pc_ALTERA_SYNTHESIZED, 205 | d1 => ALUOut_ALTERA_SYNTHESIZED, 206 | y => PCAdr); 207 | 208 | 209 | b2v_inst12 : flopenr 210 | GENERIC MAP(width => 32 211 | ) 212 | PORT MAP(clk => clk, 213 | reset => reset, 214 | en => IRWrite, 215 | d => ReadData, 216 | q => Instr_ALTERA_SYNTHESIZED); 217 | 218 | 219 | b2v_inst14 : regfile 220 | PORT MAP(clk => clk, 221 | we3 => RegWrite, 222 | ra1 => Instr_ALTERA_SYNTHESIZED(25 DOWNTO 21), 223 | ra2 => Instr_ALTERA_SYNTHESIZED(20 DOWNTO 16), 224 | wa3 => SYNTHESIZED_WIRE_0, 225 | wd3 => WriteReg_ALTERA_SYNTHESIZED, 226 | rd1 => RFRD_ALTERA_SYNTHESIZED1, 227 | rd2 => RFRD_ALTERA_SYNTHESIZED2); 228 | 229 | 230 | b2v_inst15 : mux2 231 | GENERIC MAP(width => 5 232 | ) 233 | PORT MAP(s => RegDst, 234 | d0 => Instr_ALTERA_SYNTHESIZED(20 DOWNTO 16), 235 | d1 => Instr_ALTERA_SYNTHESIZED(15 DOWNTO 11), 236 | y => SYNTHESIZED_WIRE_0); 237 | 238 | 239 | b2v_inst16 : mux2 240 | GENERIC MAP(width => 32 241 | ) 242 | PORT MAP(s => MemtoReg, 243 | d0 => ALUOut_ALTERA_SYNTHESIZED, 244 | d1 => RDCLK_ALTERA_SYNTHESIZED, 245 | y => WriteReg_ALTERA_SYNTHESIZED); 246 | 247 | 248 | b2v_inst17 : flopr 249 | GENERIC MAP(width => 32 250 | ) 251 | PORT MAP(clk => clk, 252 | reset => reset, 253 | d => RFRD_ALTERA_SYNTHESIZED2, 254 | q => WD); 255 | 256 | 257 | b2v_inst18 : flopr 258 | GENERIC MAP(width => 32 259 | ) 260 | PORT MAP(clk => clk, 261 | reset => reset, 262 | d => RFRD_ALTERA_SYNTHESIZED1, 263 | q => SYNTHESIZED_WIRE_1); 264 | 265 | 266 | b2v_inst19 : mux2 267 | GENERIC MAP(width => 32 268 | ) 269 | PORT MAP(s => ALUSrcA, 270 | d0 => pc_ALTERA_SYNTHESIZED, 271 | d1 => SYNTHESIZED_WIRE_1, 272 | y => SrcA); 273 | 274 | 275 | b2v_inst2 : mux4 276 | GENERIC MAP(width => 32 277 | ) 278 | PORT MAP(d0 => WD, 279 | d1 => SYNTHESIZED_WIRE_2, 280 | d2 => SYNTHESIZED_WIRE_8, 281 | d3 => SYNTHESIZED_WIRE_4, 282 | s => AluSrcB, 283 | y => SYNTHESIZED_WIRE_6); 284 | 285 | 286 | b2v_inst20 : flopr 287 | GENERIC MAP(width => 32 288 | ) 289 | PORT MAP(clk => clk, 290 | reset => reset, 291 | d => ALUResult, 292 | q => ALUOut_ALTERA_SYNTHESIZED); 293 | 294 | 295 | b2v_inst21 : flopr 296 | GENERIC MAP(width => 32 297 | ) 298 | PORT MAP(clk => clk, 299 | reset => reset, 300 | d => ReadData, 301 | q => RDCLK_ALTERA_SYNTHESIZED); 302 | 303 | 304 | b2v_inst3 : sl2 305 | PORT MAP(a => SYNTHESIZED_WIRE_8, 306 | y => SYNTHESIZED_WIRE_4); 307 | 308 | 309 | b2v_inst4 : intvec 310 | GENERIC MAP(int => 4, 311 | width => 32 312 | ) 313 | PORT MAP( y => SYNTHESIZED_WIRE_2); 314 | 315 | 316 | b2v_inst5 : alu 317 | PORT MAP(a => SrcA, 318 | alucontrol => ALUControl, 319 | b => SYNTHESIZED_WIRE_6, 320 | zero => Zero, 321 | result => ALUResult); 322 | 323 | 324 | b2v_inst6 : mux4 325 | GENERIC MAP(width => 32 326 | ) 327 | PORT MAP(d0 => ALUResult, 328 | d1 => ALUOut_ALTERA_SYNTHESIZED, 329 | d2 => PCJump_ALTERA_SYNTHESIZED, 330 | d3 => SYNTHESIZED_WIRE_7, 331 | s => PCSrc, 332 | y => pcNxt); 333 | 334 | 335 | b2v_inst7 : jmpmerge 336 | PORT MAP(instr => Instr_ALTERA_SYNTHESIZED(25 DOWNTO 0), 337 | pchi => pc_ALTERA_SYNTHESIZED(31 DOWNTO 28), 338 | y => PCJump_ALTERA_SYNTHESIZED); 339 | 340 | 341 | b2v_inst8 : beqctrl 342 | PORT MAP(zero => Zero, 343 | branch => Branch, 344 | pcwrite => PCWrite, 345 | pcen => PCEn); 346 | 347 | 348 | b2v_inst9 : intvec 349 | GENERIC MAP(int => 0, 350 | width => 32 351 | ) 352 | PORT MAP( y => SYNTHESIZED_WIRE_7); 353 | 354 | Adr <= PCAdr; 355 | ALUOut <= ALUOut_ALTERA_SYNTHESIZED; 356 | Funct(5 DOWNTO 0) <= Instr_ALTERA_SYNTHESIZED(5 DOWNTO 0); 357 | Instr <= Instr_ALTERA_SYNTHESIZED; 358 | Op(5 DOWNTO 0) <= Instr_ALTERA_SYNTHESIZED(31 DOWNTO 26); 359 | pc <= pc_ALTERA_SYNTHESIZED; 360 | PCJump <= PCJump_ALTERA_SYNTHESIZED; 361 | RDCLK <= RDCLK_ALTERA_SYNTHESIZED; 362 | RFRD1 <= RFRD_ALTERA_SYNTHESIZED1; 363 | RFRD2 <= RFRD_ALTERA_SYNTHESIZED2; 364 | WriteData <= WD; 365 | WriteReg <= WriteReg_ALTERA_SYNTHESIZED; 366 | 367 | END bdf_type; -------------------------------------------------------------------------------- /src/mips_fpga.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect -192 288 -24 304) 25 | (text "INPUT" (rect 125 0 161 13)(font "Arial" (font_size 6))) 26 | (text "reset" (rect 5 0 35 19)(font "Intel Clear" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 152 20)(font "Arial" (font_size 6))) 37 | (annotation_block (location)(rect -192 216 -120 256)) 38 | ) 39 | (pin 40 | (input) 41 | (rect -192 304 -24 320) 42 | (text "INPUT" (rect 125 0 161 13)(font "Arial" (font_size 6))) 43 | (text "rxd" (rect 5 0 23 15)(font "Arial" )) 44 | (pt 168 8) 45 | (drawing 46 | (line (pt 84 12)(pt 109 12)) 47 | (line (pt 84 4)(pt 109 4)) 48 | (line (pt 113 8)(pt 168 8)) 49 | (line (pt 84 12)(pt 84 4)) 50 | (line (pt 109 4)(pt 113 8)) 51 | (line (pt 109 12)(pt 113 8)) 52 | ) 53 | (text "VCC" (rect 128 7 152 20)(font "Arial" (font_size 6))) 54 | (annotation_block (location)(rect -192 320 -128 344)) 55 | ) 56 | (pin 57 | (input) 58 | (rect -184 464 -16 480) 59 | (text "INPUT" (rect 7 0 43 13)(font "Arial" (font_size 6))) 60 | (text "clk_dt" (rect 126 0 163 15)(font "Arial" )) 61 | (pt 0 8) 62 | (drawing 63 | (line (pt 84 12)(pt 59 12)) 64 | (line (pt 84 4)(pt 59 4)) 65 | (line (pt 55 8)(pt 0 8)) 66 | (line (pt 84 12)(pt 84 4)) 67 | (line (pt 59 4)(pt 55 8)) 68 | (line (pt 59 12)(pt 55 8)) 69 | ) 70 | (flipy) 71 | (text "VCC" (rect 16 7 40 20)(font "Arial" (font_size 6))) 72 | (annotation_block (location)(rect -80 432 -16 456)) 73 | ) 74 | (pin 75 | (output) 76 | (rect 304 824 480 840) 77 | (text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6))) 78 | (text "data[7..0]" (rect 90 0 150 19)(font "Intel Clear" )) 79 | (pt 0 8) 80 | (drawing 81 | (line (pt 0 8)(pt 52 8)) 82 | (line (pt 52 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(line (pt 52 4)(pt 78 4)) 117 | (line (pt 52 12)(pt 78 12)) 118 | (line (pt 52 12)(pt 52 4)) 119 | (line (pt 78 4)(pt 82 8)) 120 | (line (pt 82 8)(pt 78 12)) 121 | (line (pt 78 12)(pt 82 8)) 122 | ) 123 | (annotation_block (location)(rect 536 656 600 760)) 124 | ) 125 | (symbol 126 | (rect -24 280 24 312) 127 | (text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6))) 128 | (text "inst" (rect 3 21 26 36)(font "Arial" )) 129 | (port 130 | (pt 0 16) 131 | (input) 132 | (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) 133 | (text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible)) 134 | (line (pt 0 16)(pt 13 16)) 135 | ) 136 | (port 137 | (pt 48 16) 138 | (output) 139 | (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) 140 | (text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible)) 141 | (line (pt 39 16)(pt 48 16)) 142 | ) 143 | (drawing 144 | (line (pt 13 25)(pt 13 7)) 145 | (line (pt 13 7)(pt 31 16)) 146 | (line (pt 13 25)(pt 31 16)) 147 | (circle (rect 31 12 39 20)) 148 | ) 149 | ) 150 | (symbol 151 | (rect 88 784 304 896) 152 | (text "digtube" (rect 5 0 53 15)(font "Arial" )) 153 | (text "dt" (rect 8 96 19 111)(font "Arial" )) 154 | (port 155 | (pt 0 32) 156 | (input) 157 | (text "clk" (rect 0 0 17 15)(font "Arial" )) 158 | (text "clk" (rect 21 27 38 42)(font "Arial" )) 159 | (line (pt 0 32)(pt 16 32)) 160 | ) 161 | (port 162 | (pt 0 48) 163 | (input) 164 | (text "reset" (rect 0 0 33 15)(font "Arial" )) 165 | (text "reset" (rect 21 43 54 58)(font "Arial" )) 166 | (line (pt 0 48)(pt 16 48)) 167 | ) 168 | (port 169 | (pt 0 64) 170 | (input) 171 | (text "en" (rect 0 0 16 15)(font "Arial" )) 172 | (text "en" (rect 21 59 37 74)(font "Arial" )) 173 | (line (pt 0 64)(pt 16 64)) 174 | ) 175 | (port 176 | (pt 0 80) 177 | (input) 178 | (text "data[wid*4-1..0]" (rect 0 0 100 15)(font "Arial" )) 179 | (text "data[wid*4-1..0]" (rect 21 75 121 90)(font "Arial" )) 180 | (line (pt 0 80)(pt 16 80)(line_width 3)) 181 | ) 182 | (port 183 | (pt 216 32) 184 | (output) 185 | (text "dt_sel[wid-1..0]" (rect 0 0 97 15)(font "Arial" )) 186 | (text "dt_sel[wid-1..0]" (rect 113 27 210 42)(font "Arial" )) 187 | (line (pt 216 32)(pt 200 32)(line_width 3)) 188 | ) 189 | (port 190 | (pt 216 48) 191 | (output) 192 | (text "dt_data[7..0]" (rect 0 0 79 15)(font "Arial" )) 193 | (text "dt_data[7..0]" (rect 129 43 208 58)(font "Arial" )) 194 | (line (pt 216 48)(pt 200 48)(line_width 3)) 195 | ) 196 | (parameter 197 | "wid" 198 | "6" 199 | "" 200 | (type "PARAMETER_SIGNED_DEC") ) 201 | (drawing 202 | (rectangle (rect 16 16 200 96)) 203 | ) 204 | (annotation_block (parameter)(rect 88 744 286 784)) 205 | ) 206 | (symbol 207 | (rect 88 232 320 712) 208 | (text "mips_computer" (rect 5 0 114 20)(font "Intel Clear" (font_size 8))) 209 | (text "inst3" (rect 8 457 39 476)(font "Intel Clear" )) 210 | (port 211 | (pt 0 32) 212 | (input) 213 | (text "clk_50m" (rect 0 0 60 20)(font "Intel Clear" (font_size 8))) 214 | (text "clk_50m" (rect 21 27 81 47)(font "Intel Clear" (font_size 8))) 215 | (line (pt 0 32)(pt 16 32)) 216 | ) 217 | (port 218 | (pt 0 48) 219 | (input) 220 | (text "clk" (rect 0 0 20 20)(font "Intel Clear" (font_size 8))) 221 | (text "clk" (rect 21 43 41 63)(font "Intel Clear" (font_size 8))) 222 | (line (pt 0 48)(pt 16 48)) 223 | ) 224 | (port 225 | (pt 0 64) 226 | (input) 227 | (text "reset" (rect 0 0 35 20)(font "Intel Clear" (font_size 8))) 228 | (text "reset" (rect 21 59 56 79)(font "Intel Clear" (font_size 8))) 229 | (line (pt 0 64)(pt 16 64)) 230 | ) 231 | (port 232 | (pt 0 80) 233 | (input) 234 | (text "rxd" (rect 0 0 22 20)(font "Intel Clear" (font_size 8))) 235 | (text "rxd" (rect 21 75 43 95)(font "Intel Clear" (font_size 8))) 236 | (line (pt 0 80)(pt 16 80)) 237 | ) 238 | (port 239 | (pt 232 32) 240 | (output) 241 | (text "ADR[31..0]" (rect 0 0 74 20)(font "Intel Clear" (font_size 8))) 242 | (text "ADR[31..0]" (rect 137 27 211 47)(font "Intel Clear" (font_size 8))) 243 | (line (pt 232 32)(pt 216 32)(line_width 3)) 244 | ) 245 | (port 246 | (pt 232 48) 247 | (output) 248 | (text "ALUOut[31..0]" (rect 0 0 100 20)(font "Intel Clear" (font_size 8))) 249 | (text "ALUOut[31..0]" (rect 111 43 211 63)(font "Intel Clear" (font_size 8))) 250 | (line (pt 232 48)(pt 216 48)(line_width 3)) 251 | ) 252 | (port 253 | (pt 232 64) 254 | (output) 255 | (text "Funct[5..0]" (rect 0 0 75 20)(font "Intel Clear" (font_size 8))) 256 | (text "Funct[5..0]" (rect 136 59 211 79)(font "Intel Clear" (font_size 8))) 257 | (line (pt 232 64)(pt 216 64)(line_width 3)) 258 | ) 259 | (port 260 | (pt 232 80) 261 | (output) 262 | (text "Instr[31..0]" (rect 0 0 77 20)(font "Intel Clear" (font_size 8))) 263 | (text "Instr[31..0]" (rect 134 75 211 95)(font "Intel Clear" (font_size 8))) 264 | (line (pt 232 80)(pt 216 80)(line_width 3)) 265 | ) 266 | (port 267 | (pt 232 96) 268 | (output) 269 | (text "Op[5..0]" (rect 0 0 56 20)(font "Intel Clear" (font_size 8))) 270 | (text "Op[5..0]" (rect 155 91 211 111)(font "Intel Clear" (font_size 8))) 271 | (line (pt 232 96)(pt 216 96)(line_width 3)) 272 | ) 273 | (port 274 | (pt 232 112) 275 | (output) 276 | (text "PC[31..0]" (rect 0 0 63 20)(font "Intel Clear" (font_size 8))) 277 | (text "PC[31..0]" (rect 148 107 211 127)(font "Intel Clear" (font_size 8))) 278 | (line (pt 232 112)(pt 216 112)(line_width 3)) 279 | ) 280 | (port 281 | (pt 232 128) 282 | (output) 283 | (text "PCJump[31..0]" (rect 0 0 103 20)(font "Intel Clear" (font_size 8))) 284 | (text "PCJump[31..0]" (rect 108 123 211 143)(font "Intel Clear" (font_size 8))) 285 | (line (pt 232 128)(pt 216 128)(line_width 3)) 286 | ) 287 | (port 288 | (pt 232 144) 289 | (output) 290 | (text "RDCLK[31..0]" (rect 0 0 92 20)(font "Intel Clear" (font_size 8))) 291 | (text "RDCLK[31..0]" (rect 119 139 211 159)(font "Intel Clear" (font_size 8))) 292 | (line (pt 232 144)(pt 216 144)(line_width 3)) 293 | ) 294 | (port 295 | (pt 232 160) 296 | (output) 297 | (text "RFRD1[31..0]" (rect 0 0 92 20)(font "Intel Clear" (font_size 8))) 298 | (text "RFRD1[31..0]" (rect 119 155 211 175)(font "Intel Clear" (font_size 8))) 299 | (line (pt 232 160)(pt 216 160)(line_width 3)) 300 | ) 301 | (port 302 | (pt 232 176) 303 | (output) 304 | (text "RFRD2[31..0]" (rect 0 0 92 20)(font "Intel Clear" (font_size 8))) 305 | (text "RFRD2[31..0]" (rect 119 171 211 191)(font "Intel Clear" (font_size 8))) 306 | (line (pt 232 176)(pt 216 176)(line_width 3)) 307 | ) 308 | (port 309 | (pt 232 192) 310 | (output) 311 | (text "WriteData[31..0]" (rect 0 0 115 20)(font "Intel Clear" (font_size 8))) 312 | (text "WriteData[31..0]" (rect 96 187 211 207)(font "Intel Clear" (font_size 8))) 313 | (line (pt 232 192)(pt 216 192)(line_width 3)) 314 | ) 315 | (port 316 | (pt 232 208) 317 | (output) 318 | (text "WriteReg[31..0]" (rect 0 0 108 20)(font "Intel Clear" (font_size 8))) 319 | (text "WriteReg[31..0]" (rect 103 203 211 223)(font "Intel Clear" (font_size 8))) 320 | (line (pt 232 208)(pt 216 208)(line_width 3)) 321 | ) 322 | (port 323 | (pt 232 224) 324 | (output) 325 | (text "ReadData[31..0]" (rect 0 0 113 20)(font "Intel Clear" (font_size 8))) 326 | (text "ReadData[31..0]" (rect 98 219 211 239)(font "Intel Clear" (font_size 8))) 327 | (line (pt 232 224)(pt 216 224)(line_width 3)) 328 | ) 329 | (port 330 | (pt 232 240) 331 | (output) 332 | (text "MemtoReg" (rect 0 0 75 20)(font "Intel Clear" (font_size 8))) 333 | (text "MemtoReg" (rect 136 235 211 255)(font "Intel Clear" (font_size 8))) 334 | (line (pt 232 240)(pt 216 240)) 335 | ) 336 | (port 337 | (pt 232 256) 338 | (output) 339 | (text "RegDst" (rect 0 0 49 20)(font "Intel Clear" (font_size 8))) 340 | (text "RegDst" (rect 162 251 211 271)(font "Intel Clear" (font_size 8))) 341 | (line (pt 232 256)(pt 216 256)) 342 | ) 343 | (port 344 | (pt 232 272) 345 | (output) 346 | (text "IorD" (rect 0 0 30 20)(font "Intel Clear" (font_size 8))) 347 | (text "IorD" (rect 181 267 211 287)(font "Intel Clear" (font_size 8))) 348 | (line (pt 232 272)(pt 216 272)) 349 | ) 350 | (port 351 | (pt 232 288) 352 | (output) 353 | (text "ALUSrcB[1..0]" (rect 0 0 95 20)(font "Intel Clear" (font_size 8))) 354 | (text "ALUSrcB[1..0]" (rect 116 283 211 303)(font "Intel Clear" (font_size 8))) 355 | (line (pt 232 288)(pt 216 288)(line_width 3)) 356 | ) 357 | (port 358 | (pt 232 304) 359 | (output) 360 | (text "PCSrc[1..0]" (rect 0 0 76 20)(font "Intel Clear" (font_size 8))) 361 | (text "PCSrc[1..0]" (rect 135 299 211 319)(font "Intel Clear" (font_size 8))) 362 | (line (pt 232 304)(pt 216 304)(line_width 3)) 363 | ) 364 | (port 365 | (pt 232 320) 366 | (output) 367 | (text "ALUSrcA" (rect 0 0 60 20)(font "Intel Clear" (font_size 8))) 368 | (text "ALUSrcA" (rect 151 315 211 335)(font "Intel Clear" (font_size 8))) 369 | (line (pt 232 320)(pt 216 320)) 370 | ) 371 | (port 372 | (pt 232 336) 373 | (output) 374 | (text "IRWrite" (rect 0 0 51 20)(font "Intel Clear" (font_size 8))) 375 | (text "IRWrite" (rect 160 331 211 351)(font "Intel Clear" (font_size 8))) 376 | (line (pt 232 336)(pt 216 336)) 377 | ) 378 | (port 379 | (pt 232 352) 380 | (output) 381 | (text "MemWrite" (rect 0 0 71 20)(font "Intel Clear" (font_size 8))) 382 | (text "MemWrite" (rect 140 347 211 367)(font "Intel Clear" (font_size 8))) 383 | (line (pt 232 352)(pt 216 352)) 384 | ) 385 | (port 386 | (pt 232 368) 387 | (output) 388 | (text "PCWrite" (rect 0 0 56 20)(font "Intel Clear" (font_size 8))) 389 | (text "PCWrite" (rect 155 363 211 383)(font "Intel Clear" (font_size 8))) 390 | (line (pt 232 368)(pt 216 368)) 391 | ) 392 | (port 393 | (pt 232 384) 394 | (output) 395 | (text "Branch" (rect 0 0 49 20)(font "Intel Clear" (font_size 8))) 396 | (text "Branch" (rect 162 379 211 399)(font "Intel Clear" (font_size 8))) 397 | (line (pt 232 384)(pt 216 384)) 398 | ) 399 | (port 400 | (pt 232 400) 401 | (output) 402 | (text "RegWrite" (rect 0 0 63 20)(font "Intel Clear" (font_size 8))) 403 | (text "RegWrite" (rect 148 395 211 415)(font "Intel Clear" (font_size 8))) 404 | (line (pt 232 400)(pt 216 400)) 405 | ) 406 | (port 407 | (pt 232 416) 408 | (output) 409 | (text "ALUOP[1..0]" (rect 0 0 84 20)(font "Intel Clear" (font_size 8))) 410 | (text "ALUOP[1..0]" (rect 127 411 211 431)(font "Intel Clear" (font_size 8))) 411 | (line (pt 232 416)(pt 216 416)(line_width 3)) 412 | ) 413 | (port 414 | (pt 232 432) 415 | (output) 416 | (text "StateNow[3..0]" (rect 0 0 105 20)(font "Intel Clear" (font_size 8))) 417 | (text "StateNow[3..0]" (rect 106 427 211 447)(font "Intel Clear" (font_size 8))) 418 | (line (pt 232 432)(pt 216 432)(line_width 3)) 419 | ) 420 | (port 421 | (pt 232 448) 422 | (output) 423 | (text "ALUControl[2..0]" (rect 0 0 118 20)(font "Intel Clear" (font_size 8))) 424 | (text "ALUControl[2..0]" (rect 93 443 211 463)(font "Intel Clear" (font_size 8))) 425 | (line (pt 232 448)(pt 216 448)(line_width 3)) 426 | ) 427 | (drawing 428 | (rectangle (rect 16 16 216 464)) 429 | ) 430 | ) 431 | (connector 432 | (pt 72 848) 433 | (pt 72 912) 434 | ) 435 | (connector 436 | (pt 72 848) 437 | (pt 88 848) 438 | ) 439 | (connector 440 | (pt 88 864) 441 | (pt 80 864) 442 | (bus) 443 | ) 444 | (connector 445 | (pt 80 864) 446 | (pt 80 904) 447 | (bus) 448 | ) 449 | (connector 450 | (text "WD[23..0]" (rect 436 888 499 907)(font "Intel Clear" )) 451 | (pt 80 904) 452 | (pt 496 904) 453 | (bus) 454 | ) 455 | (connector 456 | (pt 72 832) 457 | (pt 72 296) 458 | ) 459 | (connector 460 | (pt 72 832) 461 | (pt 88 832) 462 | ) 463 | (connector 464 | (pt 24 296) 465 | (pt 72 296) 466 | ) 467 | (connector 468 | (pt 72 296) 469 | (pt 88 296) 470 | ) 471 | (connector 472 | (pt 320 680) 473 | (pt 512 680) 474 | (bus) 475 | ) 476 | (connector 477 | (pt 320 472) 478 | (pt 512 472) 479 | ) 480 | (connector 481 | (pt 320 488) 482 | (pt 512 488) 483 | ) 484 | (connector 485 | (pt 320 504) 486 | (pt 512 504) 487 | ) 488 | (connector 489 | (pt 320 552) 490 | (pt 512 552) 491 | ) 492 | (connector 493 | (pt 320 568) 494 | (pt 512 568) 495 | ) 496 | (connector 497 | (pt 320 600) 498 | (pt 512 600) 499 | ) 500 | (connector 501 | (pt 320 616) 502 | (pt 512 616) 503 | ) 504 | (connector 505 | (pt 320 632) 506 | (pt 512 632) 507 | ) 508 | (connector 509 | (pt 320 520) 510 | (pt 512 520) 511 | (bus) 512 | ) 513 | (connector 514 | (pt 320 264) 515 | (pt 512 264) 516 | (bus) 517 | ) 518 | (connector 519 | (pt 320 280) 520 | (pt 512 280) 521 | (bus) 522 | ) 523 | (connector 524 | (pt 320 536) 525 | (pt 512 536) 526 | (bus) 527 | ) 528 | (connector 529 | (pt 320 296) 530 | (pt 512 296) 531 | (bus) 532 | ) 533 | (connector 534 | (pt 320 312) 535 | (pt 512 312) 536 | (bus) 537 | ) 538 | (connector 539 | (pt 320 344) 540 | (pt 512 344) 541 | (bus) 542 | ) 543 | (connector 544 | (pt 320 360) 545 | (pt 512 360) 546 | (bus) 547 | ) 548 | (connector 549 | (pt 320 328) 550 | (pt 512 328) 551 | (bus) 552 | ) 553 | (connector 554 | (pt 320 376) 555 | (pt 512 376) 556 | (bus) 557 | ) 558 | (connector 559 | (pt 320 392) 560 | (pt 512 392) 561 | (bus) 562 | ) 563 | (connector 564 | (pt 320 440) 565 | (pt 512 440) 566 | (bus) 567 | ) 568 | (connector 569 | (pt 320 408) 570 | (pt 512 408) 571 | (bus) 572 | ) 573 | (connector 574 | (pt 320 456) 575 | (pt 512 456) 576 | (bus) 577 | ) 578 | (connector 579 | (pt 320 648) 580 | (pt 512 648) 581 | (bus) 582 | ) 583 | (connector 584 | (text "state[3..0]" (rect 328 648 391 667)(font "Intel Clear" )) 585 | (pt 320 664) 586 | (pt 512 664) 587 | (bus) 588 | ) 589 | (connector 590 | (pt -24 312) 591 | (pt 88 312) 592 | ) 593 | (connector 594 | (text "memwrite" (rect 440 904 503 923)(font "Intel Clear" )) 595 | (pt 504 912) 596 | (pt 72 912) 597 | ) 598 | (connector 599 | (text "memwrite" (rect 323 568 386 587)(font "Intel Clear" )) 600 | (pt 320 584) 601 | (pt 512 584) 602 | ) 603 | (connector 604 | (text "WD[31..0]" (rect 324 408 387 427)(font "Intel Clear" )) 605 | (pt 320 424) 606 | (pt 512 424) 607 | (bus) 608 | ) 609 | (connector 610 | (pt -192 816) 611 | (pt 88 816) 612 | ) 613 | (connector 614 | (pt -192 280) 615 | (pt 88 280) 616 | ) 617 | (connector 618 | (pt 88 264) 619 | (pt -192 264) 620 | ) 621 | (connector 622 | (pt -192 264) 623 | (pt -192 280) 624 | ) 625 | (connector 626 | (pt -184 472) 627 | (pt -192 472) 628 | ) 629 | (connector 630 | (pt -192 280) 631 | (pt -192 472) 632 | ) 633 | (connector 634 | (pt -192 472) 635 | (pt -192 816) 636 | ) 637 | (junction (pt 72 296)) 638 | (junction (pt -192 472)) 639 | (junction (pt -192 280)) 640 | -------------------------------------------------------------------------------- /src/mips_computer.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 432 184 600 200) 25 | (text "INPUT" (rect 125 0 161 13)(font "Arial" (font_size 6))) 26 | (text "clk" (rect 5 0 22 15)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 152 20)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (input) 40 | (rect 432 216 600 232) 41 | (text "INPUT" (rect 125 0 161 13)(font "Arial" (font_size 6))) 42 | (text "reset" (rect 5 0 35 19)(font "Intel Clear" )) 43 | (pt 168 8) 44 | (drawing 45 | (line (pt 84 12)(pt 109 12)) 46 | (line (pt 84 4)(pt 109 4)) 47 | (line (pt 113 8)(pt 168 8)) 48 | (line (pt 84 12)(pt 84 4)) 49 | (line (pt 109 4)(pt 113 8)) 50 | (line (pt 109 12)(pt 113 8)) 51 | ) 52 | (text "VCC" (rect 128 7 152 20)(font "Arial" (font_size 6))) 53 | ) 54 | (pin 55 | (input) 56 | (rect 432 248 600 264) 57 | (text "INPUT" (rect 125 0 161 13)(font "Arial" (font_size 6))) 58 | (text "rxd" (rect 5 0 23 15)(font "Arial" )) 59 | (pt 168 8) 60 | (drawing 61 | (line (pt 84 12)(pt 109 12)) 62 | (line (pt 84 4)(pt 109 4)) 63 | (line (pt 113 8)(pt 168 8)) 64 | (line (pt 84 12)(pt 84 4)) 65 | (line (pt 109 4)(pt 113 8)) 66 | (line (pt 109 12)(pt 113 8)) 67 | ) 68 | (text "VCC" (rect 128 7 152 20)(font "Arial" (font_size 6))) 69 | ) 70 | (pin 71 | (input) 72 | (rect 432 152 600 168) 73 | (text "INPUT" (rect 125 0 161 13)(font "Arial" (font_size 6))) 74 | (text "clk_50m" (rect 5 0 60 15)(font "Arial" )) 75 | (pt 168 8) 76 | (drawing 77 | (line (pt 84 12)(pt 109 12)) 78 | (line (pt 84 4)(pt 109 4)) 79 | (line (pt 113 8)(pt 168 8)) 80 | (line (pt 84 12)(pt 84 4)) 81 | (line (pt 109 4)(pt 113 8)) 82 | (line (pt 109 12)(pt 113 8)) 83 | ) 84 | (text "VCC" (rect 128 7 152 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(line (pt 0 64)(pt 16 64)(line_width 3)) 1031 | ) 1032 | (port 1033 | (pt 176 32) 1034 | (output) 1035 | (text "wdf[31..0]" (rect 0 0 61 15)(font "Arial" )) 1036 | (text "wdf[31..0]" (rect 104 27 165 42)(font "Arial" )) 1037 | (line (pt 176 32)(pt 160 32)(line_width 3)) 1038 | ) 1039 | (drawing 1040 | (rectangle (rect 16 16 160 96)) 1041 | ) 1042 | ) 1043 | (symbol 1044 | (rect 1288 808 1448 952) 1045 | (text "iomemory" (rect 5 0 69 15)(font "Arial" )) 1046 | (text "inst14" (rect 8 128 48 147)(font "Intel Clear" )) 1047 | (port 1048 | (pt 0 32) 1049 | (input) 1050 | (text "clk" (rect 0 0 17 15)(font "Arial" )) 1051 | (text "clk" (rect 21 27 38 42)(font "Arial" )) 1052 | (line (pt 0 32)(pt 16 32)) 1053 | ) 1054 | (port 1055 | (pt 0 48) 1056 | (input) 1057 | (text "wr" (rect 0 0 15 15)(font "Arial" )) 1058 | (text "wr" (rect 21 43 36 58)(font "Arial" )) 1059 | (line (pt 0 48)(pt 16 48)) 1060 | ) 1061 | (port 1062 | (pt 0 64) 1063 | (input) 1064 | (text "a[31..0]" (rect 0 0 47 15)(font "Arial" )) 1065 | (text "a[31..0]" (rect 21 59 68 74)(font "Arial" )) 1066 | (line (pt 0 64)(pt 16 64)(line_width 3)) 1067 | ) 1068 | (port 1069 | (pt 0 80) 1070 | (input) 1071 | (text "a8[7..0]" (rect 0 0 47 15)(font "Arial" )) 1072 | (text "a8[7..0]" (rect 21 75 68 90)(font "Arial" )) 1073 | (line (pt 0 80)(pt 16 80)(line_width 3)) 1074 | ) 1075 | (port 1076 | (pt 0 96) 1077 | (input) 1078 | (text "w8[7..0]" (rect 0 0 49 15)(font "Arial" )) 1079 | (text "w8[7..0]" (rect 21 91 70 106)(font "Arial" )) 1080 | (line (pt 0 96)(pt 16 96)(line_width 3)) 1081 | ) 1082 | (port 1083 | (pt 160 32) 1084 | (output) 1085 | (text "rd[31..0]" (rect 0 0 51 15)(font "Arial" )) 1086 | (text "rd[31..0]" (rect 96 27 147 42)(font "Arial" )) 1087 | (line (pt 160 32)(pt 144 32)(line_width 3)) 1088 | ) 1089 | (drawing 1090 | (rectangle (rect 16 16 144 128)) 1091 | ) 1092 | ) 1093 | (connector 1094 | (text "memwrite" (rect 240 608 303 627)(font "Intel Clear" )) 1095 | (pt 432 624) 1096 | (pt 232 624) 1097 | ) 1098 | (connector 1099 | (text "clk" (rect 241 736 258 755)(font "Intel Clear" )) 1100 | (pt 432 752) 1101 | (pt 232 752) 1102 | ) 1103 | (connector 1104 | (text "reset" (rect 242 752 272 771)(font "Intel Clear" )) 1105 | (pt 232 768) 1106 | (pt 432 768) 1107 | ) 1108 | (connector 1109 | (text "memtoreg" (rect 659 736 725 755)(font "Intel Clear" )) 1110 | (pt 848 752) 1111 | (pt 648 752) 1112 | ) 1113 | (connector 1114 | (text "regdst" (rect 661 752 701 771)(font "Intel Clear" )) 1115 | (pt 848 768) 1116 | (pt 648 768) 1117 | ) 1118 | (connector 1119 | (text "iord" (rect 660 768 684 787)(font "Intel Clear" )) 1120 | (pt 848 784) 1121 | (pt 648 784) 1122 | ) 1123 | (connector 1124 | (text "alusrca" (rect 656 816 700 835)(font "Intel Clear" )) 1125 | (pt 848 832) 1126 | (pt 648 832) 1127 | ) 1128 | (connector 1129 | (text "irwrite" (rect 657 832 695 851)(font "Intel Clear" )) 1130 | (pt 848 848) 1131 | (pt 648 848) 1132 | ) 1133 | (connector 1134 | (text "memwrite" (rect 657 848 720 867)(font "Intel Clear" )) 1135 | (pt 648 864) 1136 | (pt 848 864) 1137 | ) 1138 | (connector 1139 | (text "pcwrite" (rect 659 864 705 883)(font "Intel Clear" )) 1140 | (pt 848 880) 1141 | (pt 648 880) 1142 | ) 1143 | (connector 1144 | (text "branch" (rect 657 880 700 899)(font "Intel Clear" )) 1145 | (pt 848 896) 1146 | (pt 648 896) 1147 | ) 1148 | (connector 1149 | (text "regwrite" (rect 659 896 709 915)(font "Intel Clear" )) 1150 | (pt 848 912) 1151 | (pt 648 912) 1152 | ) 1153 | (connector 1154 | (text "writedata[31..0]" (rect 237 640 336 659)(font "Intel Clear" )) 1155 | (pt 432 656) 1156 | (pt 232 656) 1157 | (bus) 1158 | ) 1159 | (connector 1160 | (text "funct[5..0]" (rect 301 1024 367 1043)(font "Intel Clear" )) 1161 | (pt 432 1040) 1162 | (pt 296 1040) 1163 | (bus) 1164 | ) 1165 | (connector 1166 | (text "aluop[1..0]" (rect 305 1040 373 1059)(font "Intel Clear" )) 1167 | (pt 432 1056) 1168 | (pt 296 1056) 1169 | (bus) 1170 | ) 1171 | (connector 1172 | (text "op[5..0]" (rect 240 768 289 787)(font "Intel Clear" )) 1173 | (pt 432 784) 1174 | (pt 232 784) 1175 | (bus) 1176 | ) 1177 | (connector 1178 | (text "alusrcb[1..0]" (rect 656 784 735 803)(font "Intel Clear" )) 1179 | (pt 648 800) 1180 | (pt 848 800) 1181 | (bus) 1182 | ) 1183 | (connector 1184 | (text "pcsrc[1..0]" (rect 656 800 723 819)(font "Intel Clear" )) 1185 | (pt 648 816) 1186 | (pt 848 816) 1187 | (bus) 1188 | ) 1189 | (connector 1190 | (text "aluop[1..0]" (rect 657 912 725 931)(font "Intel Clear" )) 1191 | (pt 648 928) 1192 | (pt 848 928) 1193 | (bus) 1194 | ) 1195 | (connector 1196 | (text "alucontrol[2..0]" (rect 645 1024 741 1043)(font "Intel Clear" )) 1197 | (pt 632 1040) 1198 | (pt 832 1040) 1199 | (bus) 1200 | ) 1201 | (connector 1202 | (text "adr[31..0]" (rect 240 624 301 643)(font "Intel Clear" )) 1203 | (pt 432 640) 1204 | (pt 232 640) 1205 | (bus) 1206 | ) 1207 | (connector 1208 | (text "adr[31..0]" (rect 670 288 731 307)(font "Intel Clear" )) 1209 | (pt 664 304) 1210 | (pt 872 304) 1211 | (bus) 1212 | ) 1213 | (connector 1214 | (text "aluout[31..0]" (rect 672 304 753 323)(font "Intel Clear" )) 1215 | (pt 664 320) 1216 | (pt 872 320) 1217 | (bus) 1218 | ) 1219 | (connector 1220 | (text "funct[5..0]" (rect 671 320 737 339)(font "Intel Clear" )) 1221 | (pt 664 336) 1222 | (pt 872 336) 1223 | (bus) 1224 | ) 1225 | (connector 1226 | (text "op[5..0]" (rect 672 352 721 371)(font "Intel Clear" )) 1227 | (pt 664 368) 1228 | (pt 872 368) 1229 | (bus) 1230 | ) 1231 | (connector 1232 | (text "pc[31..0]" (rect 674 368 730 387)(font "Intel Clear" )) 1233 | (pt 664 384) 1234 | (pt 872 384) 1235 | (bus) 1236 | ) 1237 | (connector 1238 | (text "writedata[31..0]" (rect 672 448 771 467)(font "Intel Clear" )) 1239 | (pt 664 464) 1240 | (pt 872 464) 1241 | (bus) 1242 | ) 1243 | (connector 1244 | (pt 664 480) 1245 | (pt 872 480) 1246 | (bus) 1247 | ) 1248 | (connector 1249 | (pt 664 352) 1250 | (pt 872 352) 1251 | (bus) 1252 | ) 1253 | (connector 1254 | (pt 664 432) 1255 | (pt 872 432) 1256 | (bus) 1257 | ) 1258 | (connector 1259 | (pt 664 448) 1260 | (pt 872 448) 1261 | (bus) 1262 | ) 1263 | (connector 1264 | (pt 648 944) 1265 | (pt 848 944) 1266 | (bus) 1267 | ) 1268 | (connector 1269 | (pt 664 416) 1270 | (pt 872 416) 1271 | (bus) 1272 | ) 1273 | (connector 1274 | (text "clk" (rect 239 288 256 307)(font "Intel Clear" )) 1275 | (pt 232 304) 1276 | (pt 432 304) 1277 | ) 1278 | (connector 1279 | (text "iord" (rect 236 304 260 323)(font "Intel Clear" )) 1280 | (pt 232 320) 1281 | (pt 432 320) 1282 | ) 1283 | (connector 1284 | (text "regdst" (rect 234 320 274 339)(font "Intel Clear" )) 1285 | (pt 232 336) 1286 | (pt 432 336) 1287 | ) 1288 | (connector 1289 | (text "regwrite" (rect 237 336 287 355)(font "Intel Clear" )) 1290 | (pt 232 352) 1291 | (pt 432 352) 1292 | ) 1293 | (connector 1294 | (text "alusrca" (rect 235 352 279 371)(font "Intel Clear" )) 1295 | (pt 232 368) 1296 | (pt 432 368) 1297 | ) 1298 | (connector 1299 | (text "branch" (rect 235 368 278 387)(font "Intel Clear" )) 1300 | (pt 232 384) 1301 | (pt 432 384) 1302 | ) 1303 | (connector 1304 | (text "pcwrite" (rect 235 384 281 403)(font "Intel Clear" )) 1305 | (pt 232 400) 1306 | (pt 432 400) 1307 | ) 1308 | (connector 1309 | (text "irwrite" (rect 239 400 277 419)(font "Intel Clear" )) 1310 | (pt 232 416) 1311 | (pt 432 416) 1312 | ) 1313 | (connector 1314 | (text "reset" (rect 239 416 269 435)(font "Intel Clear" )) 1315 | (pt 232 432) 1316 | (pt 432 432) 1317 | ) 1318 | (connector 1319 | (text "memtoreg" (rect 238 432 304 451)(font "Intel Clear" )) 1320 | (pt 232 448) 1321 | (pt 432 448) 1322 | ) 1323 | (connector 1324 | (text "alucontrol[2..0]" (rect 234 448 330 467)(font "Intel Clear" )) 1325 | (pt 232 464) 1326 | (pt 432 464) 1327 | (bus) 1328 | ) 1329 | (connector 1330 | (text "alusrcb[1..0]" (rect 238 464 317 483)(font "Intel Clear" )) 1331 | (pt 232 480) 1332 | (pt 432 480) 1333 | (bus) 1334 | ) 1335 | (connector 1336 | (text "pcsrc[1..0]" (rect 237 480 304 499)(font "Intel Clear" )) 1337 | (pt 232 496) 1338 | (pt 432 496) 1339 | (bus) 1340 | ) 1341 | (connector 1342 | (text "readdata[31..0]" (rect 240 496 335 515)(font "Intel Clear" )) 1343 | (pt 232 512) 1344 | (pt 432 512) 1345 | (bus) 1346 | ) 1347 | (connector 1348 | (pt 664 400) 1349 | (pt 872 400) 1350 | (bus) 1351 | ) 1352 | (connector 1353 | (text "reset" (rect 242 592 272 611)(font "Intel Clear" )) 1354 | (pt 232 608) 1355 | (pt 432 608) 1356 | ) 1357 | (connector 1358 | (text "reset" (rect 1098 584 1128 603)(font "Intel Clear" )) 1359 | (pt 1088 600) 1360 | (pt 1288 600) 1361 | ) 1362 | (connector 1363 | (text "bps_start" (rect 1482 696 1541 715)(font "Intel Clear" )) 1364 | (pt 1472 712) 1365 | (pt 1672 712) 1366 | ) 1367 | (connector 1368 | (text "bps_start" (rect 1098 600 1157 619)(font "Intel Clear" )) 1369 | (pt 1088 616) 1370 | (pt 1288 616) 1371 | ) 1372 | (connector 1373 | (text "clk_bps" (rect 1466 568 1514 587)(font "Intel Clear" )) 1374 | (pt 1456 584) 1375 | (pt 1656 584) 1376 | ) 1377 | (connector 1378 | (text "clk_bps" (rect 1098 728 1146 747)(font "Intel Clear" )) 1379 | (pt 1088 744) 1380 | (pt 1288 744) 1381 | ) 1382 | (connector 1383 | (text "reset" (rect 1098 712 1128 731)(font "Intel Clear" )) 1384 | (pt 1088 728) 1385 | (pt 1288 728) 1386 | ) 1387 | (connector 1388 | (text "rxd" (rect 1096 744 1116 763)(font "Intel Clear" )) 1389 | (pt 1288 760) 1390 | (pt 1088 760) 1391 | ) 1392 | (connector 1393 | (text "uart_wr" (rect 1480 712 1527 731)(font "Intel Clear" )) 1394 | (pt 1472 728) 1395 | (pt 1672 728) 1396 | ) 1397 | (connector 1398 | (text "uart_addr[7..0]" (rect 1481 728 1574 747)(font "Intel Clear" )) 1399 | (pt 1472 744) 1400 | (pt 1672 744) 1401 | (bus) 1402 | ) 1403 | (connector 1404 | (text "uart_data[7..0]" (rect 1481 744 1573 763)(font "Intel Clear" )) 1405 | (pt 1472 760) 1406 | (pt 1672 760) 1407 | (bus) 1408 | ) 1409 | (connector 1410 | (text "clk_50m" (rect 1095 568 1149 587)(font "Intel Clear" )) 1411 | (pt 1088 584) 1412 | (pt 1288 584) 1413 | ) 1414 | (connector 1415 | (text "clk_50m" (rect 1095 696 1149 715)(font "Intel Clear" )) 1416 | (pt 1088 712) 1417 | (pt 1288 712) 1418 | ) 1419 | (connector 1420 | (text "clk" (rect 242 576 259 595)(font "Intel Clear" )) 1421 | (pt 232 592) 1422 | (pt 432 592) 1423 | ) 1424 | (connector 1425 | (text "adr[31..0]" (rect 1096 856 1157 875)(font "Intel Clear" )) 1426 | (pt 1288 872) 1427 | (pt 1088 872) 1428 | (bus) 1429 | ) 1430 | (connector 1431 | (text "ioread[31..0]" (rect 1456 824 1536 843)(font "Intel Clear" )) 1432 | (pt 1448 840) 1433 | (pt 1648 840) 1434 | (bus) 1435 | ) 1436 | (connector 1437 | (text "ioread[31..0]" (rect 1096 472 1176 491)(font "Intel Clear" )) 1438 | (pt 1088 488) 1439 | (pt 1288 488) 1440 | (bus) 1441 | ) 1442 | (connector 1443 | (text "adr[31..0]" (rect 1096 440 1157 459)(font "Intel Clear" )) 1444 | (pt 1288 456) 1445 | (pt 1088 456) 1446 | (bus) 1447 | ) 1448 | (connector 1449 | (text "memread[31..0]" (rect 608 576 709 595)(font "Intel Clear" )) 1450 | (pt 600 592) 1451 | (pt 800 592) 1452 | (bus) 1453 | ) 1454 | (connector 1455 | (text "memread[31..0]" (rect 1096 456 1197 475)(font "Intel Clear" )) 1456 | (pt 1088 472) 1457 | (pt 1288 472) 1458 | (bus) 1459 | ) 1460 | (connector 1461 | (text "readdata[31..0]" (rect 1465 440 1560 459)(font "Intel Clear" )) 1462 | (pt 1464 456) 1463 | (pt 1608 456) 1464 | (bus) 1465 | ) 1466 | (connector 1467 | (text "uart_wr" (rect 1096 840 1143 859)(font "Intel Clear" )) 1468 | (pt 1088 856) 1469 | (pt 1288 856) 1470 | ) 1471 | (connector 1472 | (text "uart_addr[7..0]" (rect 1097 872 1190 891)(font "Intel Clear" )) 1473 | (pt 1088 888) 1474 | (pt 1288 888) 1475 | (bus) 1476 | ) 1477 | (connector 1478 | (text "uart_data[7..0]" (rect 1097 888 1189 907)(font "Intel Clear" )) 1479 | (pt 1088 904) 1480 | (pt 1288 904) 1481 | (bus) 1482 | ) 1483 | (connector 1484 | (text "clk_50m" (rect 1095 824 1149 843)(font "Intel Clear" )) 1485 | (pt 1088 840) 1486 | (pt 1288 840) 1487 | ) 1488 | --------------------------------------------------------------------------------