├── subcircuits ├── 2_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 2_bit_dac.sub │ ├── 2_bit_dac.cir.out │ ├── switch.sub │ ├── 2_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ └── 2_bit_dac_Previous_Values.xml ├── 3_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 3_bit_dac.sub │ ├── 2_bit_dac.sub │ ├── 3_bit_dac.cir.out │ ├── 2_bit_dac.cir.out │ ├── 3_bit_dac.cir │ ├── switch.sub │ ├── 2_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ ├── 2_bit_dac_Previous_Values.xml │ └── 3_bit_dac_Previous_Values.xml ├── 4_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 3_bit_dac.sub │ ├── 4_bit_dac.sub │ ├── 2_bit_dac.sub │ ├── 3_bit_dac.cir.out │ ├── 4_bit_dac.cir.out │ ├── 2_bit_dac.cir.out │ ├── 3_bit_dac.cir │ ├── 4_bit_dac.cir │ ├── switch.sub │ ├── 2_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ ├── 2_bit_dac_Previous_Values.xml │ ├── 3_bit_dac_Previous_Values.xml │ └── 4_bit_dac_Previous_Values.xml ├── 5_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 3_bit_dac.sub │ ├── 4_bit_dac.sub │ ├── 5_bit_dac.sub │ ├── 2_bit_dac.sub │ ├── 3_bit_dac.cir.out │ ├── 4_bit_dac.cir.out │ ├── 5_bit_dac.cir.out │ ├── 2_bit_dac.cir.out │ ├── 3_bit_dac.cir │ ├── 4_bit_dac.cir │ ├── switch.sub │ ├── 5_bit_dac.cir │ ├── 2_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ ├── 2_bit_dac_Previous_Values.xml │ ├── 3_bit_dac_Previous_Values.xml │ ├── 4_bit_dac_Previous_Values.xml │ └── 5_bit_dac_Previous_Values.xml ├── 6_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 3_bit_dac.sub │ ├── 4_bit_dac.sub │ ├── 5_bit_dac.sub │ ├── 2_bit_dac.sub │ ├── 3_bit_dac.cir.out │ ├── 6_bit_dac.sub │ ├── 4_bit_dac.cir.out │ ├── 5_bit_dac.cir.out │ ├── 2_bit_dac.cir.out │ ├── 3_bit_dac.cir │ ├── 6_bit_dac.cir.out │ ├── 4_bit_dac.cir │ ├── switch.sub │ ├── 5_bit_dac.cir │ ├── 2_bit_dac.cir │ ├── 6_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ ├── 2_bit_dac_Previous_Values.xml │ ├── 3_bit_dac_Previous_Values.xml │ ├── 4_bit_dac_Previous_Values.xml │ ├── 5_bit_dac_Previous_Values.xml │ └── 6_bit_dac_Previous_Values.xml ├── 7_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 3_bit_dac.sub │ ├── 4_bit_dac.sub │ ├── 5_bit_dac.sub │ ├── 2_bit_dac.sub │ ├── 3_bit_dac.cir.out │ ├── 6_bit_dac.sub │ ├── 4_bit_dac.cir.out │ ├── 7_bit_dac.sub │ ├── 5_bit_dac.cir.out │ ├── 2_bit_dac.cir.out │ ├── 3_bit_dac.cir │ ├── 6_bit_dac.cir.out │ ├── 4_bit_dac.cir │ ├── 7_bit_dac.cir.out │ ├── switch.sub │ ├── 5_bit_dac.cir │ ├── 2_bit_dac.cir │ ├── 6_bit_dac.cir │ ├── 7_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ ├── 2_bit_dac_Previous_Values.xml │ ├── 3_bit_dac_Previous_Values.xml │ ├── 4_bit_dac_Previous_Values.xml │ ├── 5_bit_dac_Previous_Values.xml │ ├── 6_bit_dac_Previous_Values.xml │ └── 7_bit_dac_Previous_Values.xml ├── 8_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 3_bit_dac.sub │ ├── 4_bit_dac.sub │ ├── 5_bit_dac.sub │ ├── 2_bit_dac.sub │ ├── 3_bit_dac.cir.out │ ├── 6_bit_dac.sub │ ├── 4_bit_dac.cir.out │ ├── 7_bit_dac.sub │ ├── 5_bit_dac.cir.out │ ├── 2_bit_dac.cir.out │ ├── 8_bit_dac.sub │ ├── 3_bit_dac.cir │ ├── 6_bit_dac.cir.out │ ├── 4_bit_dac.cir │ ├── 7_bit_dac.cir.out │ ├── switch.sub │ ├── 5_bit_dac.cir │ ├── 8_bit_dac.cir.out │ ├── 2_bit_dac.cir │ ├── 6_bit_dac.cir │ ├── 7_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ ├── 8_bit_dac.cir │ ├── 2_bit_dac_Previous_Values.xml │ ├── 3_bit_dac_Previous_Values.xml │ ├── 4_bit_dac_Previous_Values.xml │ ├── 5_bit_dac_Previous_Values.xml │ ├── 6_bit_dac_Previous_Values.xml │ ├── 7_bit_dac_Previous_Values.xml │ └── 8_bit_dac_Previous_Values.xml ├── 9_bit_dac │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── 3_bit_dac.sub │ ├── 4_bit_dac.sub │ ├── 5_bit_dac.sub │ ├── 2_bit_dac.sub │ ├── 3_bit_dac.cir.out │ ├── 6_bit_dac.sub │ ├── 4_bit_dac.cir.out │ ├── 7_bit_dac.sub │ ├── 5_bit_dac.cir.out │ ├── 2_bit_dac.cir.out │ ├── 8_bit_dac.sub │ ├── 3_bit_dac.cir │ ├── 6_bit_dac.cir.out │ ├── 9_bit_dac.sub │ ├── 4_bit_dac.cir │ ├── 7_bit_dac.cir.out │ ├── switch.sub │ ├── 5_bit_dac.cir │ ├── 8_bit_dac.cir.out │ ├── 2_bit_dac.cir │ ├── 6_bit_dac.cir │ ├── 9_bit_dac.cir.out │ ├── 7_bit_dac.cir │ ├── switch.cir.out │ ├── switch.cir │ ├── 8_bit_dac.cir │ ├── 9_bit_dac.cir │ └── 2_bit_dac_Previous_Values.xml ├── switch │ ├── analysis │ ├── NMOS-5um.lib │ ├── PMOS-5um.lib │ ├── switch.sub │ ├── switch.cir.out │ └── switch.cir ├── 4-bitDAC.png ├── 10_bit_dac.png ├── 2-Bit_DAC.png ├── 3-bit_DAC.png ├── 5_bit_dac.png ├── 6_bit_dac.png ├── 7_bit_dac.png ├── 8_bit_dac.png ├── 9_bit_dac.png ├── overview of design.png ├── An overview of 10-Bit PotDAC.png └── readme.md ├── Pre-Layout and Simulation ├── analysis ├── 10_bit_dac.proj ├── DNL(LSB).png ├── INL(LSB).png ├── Switch - prelayout.JPG ├── prelayout - output waveform.png ├── NMOS-5um.lib ├── PMOS-5um.lib ├── b3v32check.log ├── 3_bit_dac.sub ├── SourceDetails.txt ├── 4_bit_dac.sub ├── 5_bit_dac.sub ├── 2_bit_dac.sub ├── 3_bit_dac.cir.out ├── 6_bit_dac.sub ├── 4_bit_dac.cir.out ├── 7_bit_dac.sub ├── 5_bit_dac.cir.out ├── 2_bit_dac.cir.out ├── 8_bit_dac.sub ├── 3_bit_dac.cir ├── 6_bit_dac.cir.out ├── 9_bit_dac.sub ├── 7_bit_dac.cir.out ├── 4_bit_dac.cir ├── switch.sub ├── 5_bit_dac.cir ├── 8_bit_dac.cir.out ├── 2_bit_dac.cir ├── 6_bit_dac.cir ├── 9_bit_dac.cir.out ├── 7_bit_dac.cir ├── switch.cir.out ├── switch.cir ├── 8_bit_dac.cir ├── 9_bit_dac.cir ├── 10_bit_dac.cir └── 2_bit_dac_Previous_Values.xml ├── Libraries ├── osu180nm.log └── readme.md ├── potentiometricDAC_IP.pdf └── Layout and Simulation ├── 3BitDac.log ├── LayoutImages ├── readme.md ├── 10.JPG ├── 2.JPG ├── 3.JPG ├── 4.JPG ├── 5.JPG ├── 6.JPG ├── 7.JPG ├── 8.JPG ├── 9.JPG ├── sw.JPG ├── resistor.JPG └── capacitor.JPG ├── osu180nm.log ├── Layout.png ├── OutputWaveform.png ├── DNL(LSB)-postLayout.png ├── INL(LSB)-postLayout.png ├── Output Waveform with 3nF capacitor-ngspice.png ├── Output Waveform with 3nF capacitor2-ngspice.png ├── b3v32check.log ├── capacitor2.spice ├── 2BitDac.log ├── capacitor2.mag ├── resistor.mag ├── capacitor2.ext ├── resistor.ext ├── toPasteInEnd.txt └── 3BitDac.mag /subcircuits/2_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-03 0e-03 0e-00 -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-00 0e-00 0e-00 -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-00 0e-00 0e-00 -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-03 0e-03 0e-00 -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-00 0e-00 0e-00 -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-00 0e-00 0e-00 -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-00 0e-00 0e-00 -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-00 0e-00 0e-00 -------------------------------------------------------------------------------- /subcircuits/switch/analysis: -------------------------------------------------------------------------------- 1 | .tran 0e-03 0e-03 0e-00 -------------------------------------------------------------------------------- /Pre-Layout and Simulation/analysis: -------------------------------------------------------------------------------- 1 | .tran 0.1e-03 102.4e-03 0e-00 -------------------------------------------------------------------------------- /Pre-Layout and Simulation/10_bit_dac.proj: -------------------------------------------------------------------------------- 1 | schematicFile 10_bit_dac.sch 2 | -------------------------------------------------------------------------------- /Libraries/osu180nm.log: -------------------------------------------------------------------------------- 1 | Circuit: tech 2 | 3 | Fatal Error: Unknown subcircuit called in: 4 | xp 5 | -------------------------------------------------------------------------------- /potentiometricDAC_IP.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/potentiometricDAC_IP.pdf -------------------------------------------------------------------------------- /subcircuits/4-bitDAC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/4-bitDAC.png -------------------------------------------------------------------------------- /Layout and Simulation/3BitDac.log: -------------------------------------------------------------------------------- 1 | Circuit: * SPICE3 file created from 3BitDac.ext - technology: scmos 2 | 3 | -------------------------------------------------------------------------------- /subcircuits/10_bit_dac.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/10_bit_dac.png -------------------------------------------------------------------------------- /subcircuits/2-Bit_DAC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/2-Bit_DAC.png -------------------------------------------------------------------------------- /subcircuits/3-bit_DAC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/3-bit_DAC.png -------------------------------------------------------------------------------- /subcircuits/5_bit_dac.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/5_bit_dac.png -------------------------------------------------------------------------------- /subcircuits/6_bit_dac.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/6_bit_dac.png -------------------------------------------------------------------------------- /subcircuits/7_bit_dac.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/7_bit_dac.png -------------------------------------------------------------------------------- /subcircuits/8_bit_dac.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/8_bit_dac.png -------------------------------------------------------------------------------- /subcircuits/9_bit_dac.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/9_bit_dac.png -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/readme.md: -------------------------------------------------------------------------------- 1 | Here are the layout images of all the subcircuits and elements used. 2 | -------------------------------------------------------------------------------- /Layout and Simulation/osu180nm.log: -------------------------------------------------------------------------------- 1 | Circuit: tech 2 | 3 | Fatal Error: Unknown subcircuit called in: 4 | xp 5 | -------------------------------------------------------------------------------- /Layout and Simulation/Layout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/Layout.png -------------------------------------------------------------------------------- /subcircuits/overview of design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/overview of design.png -------------------------------------------------------------------------------- /Libraries/readme.md: -------------------------------------------------------------------------------- 1 | These libraries are used in this project. Use these to simulate. 2 | Keep them in the User Libraries section. 3 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/DNL(LSB).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Pre-Layout and Simulation/DNL(LSB).png -------------------------------------------------------------------------------- /Pre-Layout and Simulation/INL(LSB).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Pre-Layout and Simulation/INL(LSB).png -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/10.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/10.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/2.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/2.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/3.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/3.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/4.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/4.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/5.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/5.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/6.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/6.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/7.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/7.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/8.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/8.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/9.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/9.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/sw.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/sw.JPG -------------------------------------------------------------------------------- /Layout and Simulation/OutputWaveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/OutputWaveform.png -------------------------------------------------------------------------------- /subcircuits/An overview of 10-Bit PotDAC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/subcircuits/An overview of 10-Bit PotDAC.png -------------------------------------------------------------------------------- /Layout and Simulation/DNL(LSB)-postLayout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/DNL(LSB)-postLayout.png -------------------------------------------------------------------------------- /Layout and Simulation/INL(LSB)-postLayout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/INL(LSB)-postLayout.png -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/resistor.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/resistor.JPG -------------------------------------------------------------------------------- /Layout and Simulation/LayoutImages/capacitor.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/LayoutImages/capacitor.JPG -------------------------------------------------------------------------------- /Pre-Layout and Simulation/Switch - prelayout.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Pre-Layout and Simulation/Switch - prelayout.JPG -------------------------------------------------------------------------------- /subcircuits/readme.md: -------------------------------------------------------------------------------- 1 | Here we have all the subcircuits used to make a 10-bit digital to analog converter for the pre-layout stage which are built using eSim. 2 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/prelayout - output waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Pre-Layout and Simulation/prelayout - output waveform.png -------------------------------------------------------------------------------- /Layout and Simulation/Output Waveform with 3nF capacitor-ngspice.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/Output Waveform with 3nF capacitor-ngspice.png -------------------------------------------------------------------------------- /Layout and Simulation/Output Waveform with 3nF capacitor2-ngspice.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/xzlashutosh/avsddac_3v3/HEAD/Layout and Simulation/Output Waveform with 3nF capacitor2-ngspice.png -------------------------------------------------------------------------------- /Layout and Simulation/b3v32check.log: -------------------------------------------------------------------------------- 1 | BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4) 2 | Parameter Checking. 3 | Model = pfet 4 | W = 1e-06, L = 2e-07, M = 1 5 | Warning: Pd = 0 is less than W. 6 | -------------------------------------------------------------------------------- /Layout and Simulation/capacitor2.spice: -------------------------------------------------------------------------------- 1 | * SPICE3 file created from capacitor2.ext - technology: scmos 2 | 3 | .option scale=0.1u 4 | 5 | C0 gnd a_n41_n3# 3283700.000000fF 6 | C1 a_n41_n3# w_n1073741817_n1073741817# 21.59fF 7 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/switch/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/switch/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/NMOS-5um.lib: -------------------------------------------------------------------------------- 1 | * 5um technology 2 | 3 | .model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 4 | + Level=1 5 | + Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/b3v32check.log: -------------------------------------------------------------------------------- 1 | BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4) 2 | Parameter Checking. 3 | Model = x3:pfet 4 | W = 4e-06, L = 1.8e-07, M = 1 5 | Warning: Pd = 0 is less than W. 6 | Warning: Ps = 0 is less than W. 7 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/PMOS-5um.lib: -------------------------------------------------------------------------------- 1 | *5um technology 2 | 3 | .model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 4 | + Level=1 5 | + Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) 6 | -------------------------------------------------------------------------------- /Layout and Simulation/2BitDac.log: -------------------------------------------------------------------------------- 1 | Circuit: * SPICE3 file created from 2BitDacNew.ext - technology: scmos 2 | 3 | Ignoring BSIM parameter XL 4 | Ignoring BSIM parameter XW 5 | Ignoring BSIM parameter XL 6 | Ignoring BSIM parameter XW 7 | Fatal Error: Run: Missing node(s). 8 | -------------------------------------------------------------------------------- /Layout and Simulation/capacitor2.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech scmos 3 | timestamp 1599096684 4 | << polysilicon >> 5 | rect -41 117 138 122 6 | rect -41 92 -36 117 7 | rect -18 92 138 117 8 | rect -41 87 138 92 9 | rect 105 77 138 87 10 | rect -41 42 138 77 11 | rect -41 32 -8 42 12 | rect -41 -3 102 32 13 | << polycontact >> 14 | rect -36 92 -18 117 15 | << metal1 >> 16 | rect -105 100 -36 112 17 | << glass >> 18 | rect -58 -12 219 150 19 | << labels >> 20 | rlabel glass 170 124 170 124 1 gnd! 21 | << end >> 22 | -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/3_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 3_bit_dac 2 | .subckt 3_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 4 | .include switch.sub 5 | .include 2_bit_dac.sub 6 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 7 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 8 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 9 | * Control Statements 10 | 11 | .ends 3_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/SourceDetails.txt: -------------------------------------------------------------------------------- 1 | #### The source details are - 2 | 3 | v1 - PULSE(0 1.8 0.1m 60p 60p 0.1m 0.2m) 4 | 5 | v2 - PULSE(0 1.8 0.2m 60p 60p 0.2m 0.4m) 6 | 7 | v3 - PULSE(0 1.8 0.4m 60p 60p 0.4m 0.8m) 8 | 9 | v4 - PULSE(0 1.8 0.8m 60p 60p 0.8m 1.6m) 10 | 11 | v5 - PULSE(0 1.8 1.6m 60p 60p 1.6m 3.2m) 12 | 13 | v6 - PULSE(0 1.8 3.2m 60p 60p 3.2m 6.4m) 14 | 15 | v7 - PULSE(0 1.8 6.4m 60p 60p 6.4m 12.8m) 16 | 17 | v8 - PULSE(0 1.8 12.8m 60p 60p 12.8m 25.6m) 18 | 19 | v10 - PULSE(0 1.8 25.6m 60p 60p 25.6m 51.2m) 20 | 21 | v11 - PULSE(0 1.8 51.2m 60p 60p 51.2m 102.4m) 22 | -------------------------------------------------------------------------------- /Layout and Simulation/resistor.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech scmos 3 | timestamp 1598617915 4 | << polycontact >> 5 | rect -8 6 -3 10 6 | rect 9 -6 14 -2 7 | << pseudo_rpoly >> 8 | rect -9 10 15 11 9 | rect -9 6 -8 10 10 | rect -3 8 15 10 11 | rect -9 3 12 6 12 | rect -9 -4 -8 3 13 | rect 14 1 15 8 14 | rect -6 -2 15 1 15 | rect -9 -6 9 -4 16 | rect 14 -6 15 -2 17 | rect -9 -7 15 -6 18 | << rpoly >> 19 | rect -3 6 14 8 20 | rect 12 3 14 6 21 | rect -8 1 14 3 22 | rect -8 -2 -6 1 23 | rect -8 -4 9 -2 24 | << labels >> 25 | rlabel polycontact 12 -4 12 -4 8 b 26 | rlabel polycontact -6 8 -6 8 4 a 27 | << end >> 28 | -------------------------------------------------------------------------------- /Layout and Simulation/capacitor2.ext: -------------------------------------------------------------------------------- 1 | timestamp 1599096684 2 | version 8.1 3 | tech scmos 4 | style TSMC0.18um(tsmc18)from:t11b 5 | scale 1000 1 10 6 | resistclasses 6700 7500 929000 929000 1 7700 7700 80 80 80 70 70 40 7 | node "gnd!" 0 0 -58 -12 glass 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 | node "a_n41_n3#" 117 21586.9 -41 -3 p 0 0 0 0 0 0 0 0 0 0 18195 1120 0 0 1278 224 0 0 0 0 0 0 0 0 0 0 9 | substrate "w_n1073741817_n1073741817#" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 | device devcap None -58 -12 -57 -11 3.2837e+06 "gnd!" 0 0 "a_n41_n3#" 2 0 11 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/4_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 4_bit_dac 2 | .subckt 4_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 4 | .include switch.sub 5 | .include 3_bit_dac.sub 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 8 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 9 | * Control Statements 10 | 11 | .ends 4_bit_dac -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/4_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 4_bit_dac 2 | .subckt 4_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 4 | .include switch.sub 5 | .include 3_bit_dac.sub 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 8 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 9 | * Control Statements 10 | 11 | .ends 4_bit_dac -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/4_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 4_bit_dac 2 | .subckt 4_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 4 | .include switch.sub 5 | .include 3_bit_dac.sub 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 8 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 9 | * Control Statements 10 | 11 | .ends 4_bit_dac -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/4_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 4_bit_dac 2 | .subckt 4_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 4 | .include switch.sub 5 | .include 3_bit_dac.sub 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 8 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 9 | * Control Statements 10 | 11 | .ends 4_bit_dac -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/4_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 4_bit_dac 2 | .subckt 4_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 4 | .include switch.sub 5 | .include 3_bit_dac.sub 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 8 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 9 | * Control Statements 10 | 11 | .ends 4_bit_dac -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/4_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 4_bit_dac 2 | .subckt 4_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 4 | .include switch.sub 5 | .include 3_bit_dac.sub 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 8 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 9 | * Control Statements 10 | 11 | .ends 4_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/4_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 4_bit_dac 2 | .subckt 4_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 4 | .include switch.sub 5 | .include 3_bit_dac.sub 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 8 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 9 | * Control Statements 10 | 11 | .ends 4_bit_dac -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/5_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 5_bit_dac 2 | .subckt 5_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 4 | .include 4_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 9 | * Control Statements 10 | 11 | .ends 5_bit_dac -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/5_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 5_bit_dac 2 | .subckt 5_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 4 | .include 4_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 9 | * Control Statements 10 | 11 | .ends 5_bit_dac -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/5_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 5_bit_dac 2 | .subckt 5_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 4 | .include 4_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 9 | * Control Statements 10 | 11 | .ends 5_bit_dac -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/5_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 5_bit_dac 2 | .subckt 5_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 4 | .include 4_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 9 | * Control Statements 10 | 11 | .ends 5_bit_dac -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/5_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 5_bit_dac 2 | .subckt 5_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 4 | .include 4_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 9 | * Control Statements 10 | 11 | .ends 5_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/5_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 5_bit_dac 2 | .subckt 5_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 4 | .include 4_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 9 | * Control Statements 10 | 11 | .ends 5_bit_dac -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/2_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 2_bit_dac 2 | .subckt 2_bit_dac net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 4 | .include switch.sub 5 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 6 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 7 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 8 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 9 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 10 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 11 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 12 | * Control Statements 13 | 14 | .ends 2_bit_dac -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/3_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 2_bit_dac.sub 5 | x1 net-_u1-pad3_ net-_x1-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad5_ 2_bit_dac 6 | x2 net-_x1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_x2-pad5_ 2_bit_dac 7 | x3 net-_u1-pad5_ net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad6_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/6_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 6_bit_dac 2 | .subckt 6_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 4 | .include 5_bit_dac.sub 5 | .include switch.sub 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 8 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 9 | * Control Statements 10 | 11 | .ends 6_bit_dac -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/6_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 6_bit_dac 2 | .subckt 6_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 4 | .include 5_bit_dac.sub 5 | .include switch.sub 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 8 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 9 | * Control Statements 10 | 11 | .ends 6_bit_dac -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/6_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 6_bit_dac 2 | .subckt 6_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 4 | .include 5_bit_dac.sub 5 | .include switch.sub 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 8 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 9 | * Control Statements 10 | 11 | .ends 6_bit_dac -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/6_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 6_bit_dac 2 | .subckt 6_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 4 | .include 5_bit_dac.sub 5 | .include switch.sub 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 8 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 9 | * Control Statements 10 | 11 | .ends 6_bit_dac -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/6_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 6_bit_dac 2 | .subckt 6_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 4 | .include 5_bit_dac.sub 5 | .include switch.sub 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 8 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 9 | * Control Statements 10 | 11 | .ends 6_bit_dac -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/4_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 3_bit_dac.sub 5 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 7 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/4_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 3_bit_dac.sub 5 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 7 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/4_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 3_bit_dac.sub 5 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 7 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/4_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 3_bit_dac.sub 5 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 7 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/4_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 3_bit_dac.sub 5 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 7 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/4_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 3_bit_dac.sub 5 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 7 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/4_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 3_bit_dac.sub 5 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_x2-pad6_ 3_bit_dac 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad3_ net-_x1-pad6_ 3_bit_dac 7 | x3 net-_u1-pad6_ net-_x1-pad6_ net-_x2-pad6_ net-_u1-pad7_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Layout and Simulation/resistor.ext: -------------------------------------------------------------------------------- 1 | timestamp 1598617915 2 | version 8.1 3 | tech scmos 4 | style TSMC0.18um(tsmc18)from:t11b 5 | scale 1000 1 10 6 | resistclasses 6700 7500 929000 929000 1 7700 7700 80 80 80 70 70 40 7 | node "b" 8 75.144 9 -6 pc 0 0 0 0 0 0 0 0 0 0 20 16 0 0 20 18 0 0 0 0 0 0 0 0 0 0 8 | node "a" 8 75.144 -8 6 pc 0 0 0 0 0 0 0 0 0 0 20 16 0 0 20 18 0 0 0 0 0 0 0 0 0 0 9 | node "a_n9_n7#" 223 412.796 -9 -7 prp 0 0 0 0 0 0 0 0 0 0 124 124 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 | substrate "w_n1073741817_n1073741817#" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 | cap "a" "a_n9_n7#" 40.02 12 | cap "a_n9_n7#" "b" 40.02 13 | device devres polyResistor -8 -4 -7 -3 62 2 "a_n9_n7#" 124 0 "a" 2 0 "b" 2 0 14 | -------------------------------------------------------------------------------- /Layout and Simulation/toPasteInEnd.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | valpha R_in10 Gnd 3.3 4 | vbeta Vdd Gnd 3.3 5 | vzero D0 Gnd pulse(0 1.8 0.1m 60p 60p 0.1m 0.2m) 6 | vone D1 Gnd pulse(0 1.8 0.2m 60p 60p 0.2m 0.4m) 7 | vtwo D2 Gnd pulse(0 1.8 0.4m 60p 60p 0.4m 0.8m) 8 | vthree D3 Gnd pulse(0 1.8 0.8m 60p 60p 0.8m 1.6m) 9 | vfour D4 Gnd pulse (0 1.8 1.6m 60p 60p 1.6m 3.2m) 10 | vfive D5 Gnd pulse (0 1.8 3.2m 60p 60p 3.2m 6.4m) 11 | vsix D6 Gnd pulse (0 1.8 6.4m 60p 60p 6.4m 12.8m) 12 | vseven D7 Gnd pulse (0 1.8 12.8m 60p 60p 12.8m 25.6m) 13 | veight D8 Gnd pulse (0 1.8 25.6m 60p 60p 25.6m 51.2m) 14 | vnine D9 Gnd pulse (0 1.8 51.2m 60p 60p 51.2m 102.4m) 15 | .tran 0.01m 102.4m 16 | .control 17 | run 18 | 19 | plot V(V_out10) V(D0) 20 | 21 | .endc 22 | .end 23 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/7_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 7_bit_dac 2 | .subckt 7_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 4 | .include 6_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 9 | * Control Statements 10 | 11 | .ends 7_bit_dac -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/7_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 7_bit_dac 2 | .subckt 7_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 4 | .include 6_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 9 | * Control Statements 10 | 11 | .ends 7_bit_dac -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/7_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 7_bit_dac 2 | .subckt 7_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 4 | .include 6_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 9 | * Control Statements 10 | 11 | .ends 7_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/7_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 7_bit_dac 2 | .subckt 7_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 4 | .include 6_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 9 | * Control Statements 10 | 11 | .ends 7_bit_dac -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/5_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | .include 4_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port 9 | .tran 0e-03 0e-03 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/5_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | .include 4_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port 9 | .tran 0e-03 0e-03 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/5_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | .include 4_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port 9 | .tran 0e-03 0e-03 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/5_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | .include 4_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port 9 | .tran 0e-03 0e-03 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/5_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | .include 4_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port 9 | .tran 0e-03 0e-03 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/5_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | .include 4_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad7_ net-_x1-pad7_ net-_x2-pad7_ net-_u1-pad8_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_x1-pad7_ 4_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad7_ 4_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port 9 | .tran 0e-03 0e-03 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/2_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | .include switch.sub 4 | r1 net-_r1-pad1_ net-_r1-pad2_ 250 5 | r2 net-_r2-pad1_ net-_r1-pad1_ 250 6 | r3 net-_r3-pad1_ net-_r2-pad1_ 250 7 | r4 net-_r4-pad1_ net-_r3-pad1_ 250 8 | x1 net-_u1-pad3_ net-_r1-pad1_ net-_r2-pad1_ net-_x1-pad4_ switch 9 | x2 net-_u1-pad3_ net-_r3-pad1_ net-_r4-pad1_ net-_x2-pad4_ switch 10 | x3 net-_u1-pad4_ net-_x1-pad4_ net-_x2-pad4_ net-_u1-pad5_ switch 11 | * u1 net-_r1-pad2_ net-_r4-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port 12 | .tran 0e-03 0e-03 0e-00 13 | 14 | * Control Statements 15 | .control 16 | run 17 | print allv > plot_data_v.txt 18 | print alli > plot_data_i.txt 19 | .endc 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/8_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 8_bit_dac 2 | .subckt 8_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\8_bit_dac\8_bit_dac.cir 4 | .include 7_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad10_ net-_x1-pad10_ net-_x2-pad10_ net-_u1-pad11_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad8_ net-_u1-pad7_ net-_x1-pad10_ 7_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad8_ net-_u1-pad9_ net-_u1-pad7_ net-_x2-pad10_ 7_bit_dac 9 | * Control Statements 10 | 11 | .ends 8_bit_dac -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/8_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 8_bit_dac 2 | .subckt 8_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\8_bit_dac\8_bit_dac.cir 4 | .include 7_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad10_ net-_x1-pad10_ net-_x2-pad10_ net-_u1-pad11_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad8_ net-_u1-pad7_ net-_x1-pad10_ 7_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad8_ net-_u1-pad9_ net-_u1-pad7_ net-_x2-pad10_ 7_bit_dac 9 | * Control Statements 10 | 11 | .ends 8_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/8_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 8_bit_dac 2 | .subckt 8_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\8_bit_dac\8_bit_dac.cir 4 | .include 7_bit_dac.sub 5 | .include switch.sub 6 | x3 net-_u1-pad10_ net-_x1-pad10_ net-_x2-pad10_ net-_u1-pad11_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad8_ net-_u1-pad7_ net-_x1-pad10_ 7_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad8_ net-_u1-pad9_ net-_u1-pad7_ net-_x2-pad10_ 7_bit_dac 9 | * Control Statements 10 | 11 | .ends 8_bit_dac -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/6_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | .include 5_bit_dac.sub 4 | .include switch.sub 5 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 7 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/6_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | .include 5_bit_dac.sub 4 | .include switch.sub 5 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 7 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/6_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | .include 5_bit_dac.sub 4 | .include switch.sub 5 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 7 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/6_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | .include 5_bit_dac.sub 4 | .include switch.sub 5 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 7 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/3_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dac\3_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:51 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad3_ Net-_X1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad5_ 2_bit_dac 10 | X2 Net-_X1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X2-Pad5_ 2_bit_dac 11 | X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad6_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/6_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | .include 5_bit_dac.sub 4 | .include switch.sub 5 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad5_ net-_x1-pad8_ 5_bit_dac 6 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x2-pad8_ 5_bit_dac 7 | x3 net-_u1-pad8_ net-_x1-pad8_ net-_x2-pad8_ net-_u1-pad9_ switch 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/9_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 9_bit_dac 2 | .subckt 9_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\9_bit_dac\9_bit_dac.cir 4 | .include switch.sub 5 | .include 8_bit_dac.sub 6 | x3 net-_u1-pad11_ net-_x1-pad11_ net-_x2-pad11_ net-_u1-pad12_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_x1-pad9_ net-_u1-pad8_ net-_x1-pad11_ 8_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_x1-pad9_ net-_u1-pad10_ net-_u1-pad8_ net-_x2-pad11_ 8_bit_dac 9 | * Control Statements 10 | 11 | .ends 9_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/9_bit_dac.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit 9_bit_dac 2 | .subckt 9_bit_dac net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\9_bit_dac\9_bit_dac.cir 4 | .include switch.sub 5 | .include 8_bit_dac.sub 6 | x3 net-_u1-pad11_ net-_x1-pad11_ net-_x2-pad11_ net-_u1-pad12_ switch 7 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_x1-pad9_ net-_u1-pad8_ net-_x1-pad11_ 8_bit_dac 8 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_x1-pad9_ net-_u1-pad10_ net-_u1-pad8_ net-_x2-pad11_ 8_bit_dac 9 | * Control Statements 10 | 11 | .ends 9_bit_dac -------------------------------------------------------------------------------- /Pre-Layout and Simulation/7_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | .include 6_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/4_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:06 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_X2-Pad6_ 3_bit_dac 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_X1-Pad6_ 3_bit_dac 11 | X3 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_X2-Pad6_ Net-_U1-Pad7_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/4_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:06 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_X2-Pad6_ 3_bit_dac 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_X1-Pad6_ 3_bit_dac 11 | X3 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_X2-Pad6_ Net-_U1-Pad7_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/4_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:06 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_X2-Pad6_ 3_bit_dac 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_X1-Pad6_ 3_bit_dac 11 | X3 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_X2-Pad6_ Net-_U1-Pad7_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/4_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:06 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_X2-Pad6_ 3_bit_dac 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_X1-Pad6_ 3_bit_dac 11 | X3 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_X2-Pad6_ Net-_U1-Pad7_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/7_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | .include 6_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/4_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:06 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_X2-Pad6_ 3_bit_dac 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_X1-Pad6_ 3_bit_dac 11 | X3 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_X2-Pad6_ Net-_U1-Pad7_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/7_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | .include 6_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/4_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:06 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_X2-Pad6_ 3_bit_dac 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_X1-Pad6_ 3_bit_dac 11 | X3 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_X2-Pad6_ Net-_U1-Pad7_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/7_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | .include 6_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad9_ net-_x1-pad9_ net-_x2-pad9_ net-_u1-pad10_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ net-_x1-pad7_ net-_u1-pad6_ net-_x1-pad9_ 6_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad7_ net-_u1-pad8_ net-_u1-pad6_ net-_x2-pad9_ 6_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/4_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dac\4_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:06 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_X2-Pad6_ 3_bit_dac 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_X1-Pad6_ 3_bit_dac 11 | X3 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_X2-Pad6_ Net-_U1-Pad7_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/switch/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /Pre-Layout and Simulation/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/switch.sub: -------------------------------------------------------------------------------- 1 | * Subcircuit switch 2 | .subckt switch /digital_input /vin_1 /vin_2 /vout 3 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 4 | .include nmos_180nm.lib 5 | .include pmos_180nm.lib 6 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 7 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 8 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 9 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | * Control Statements 16 | 17 | .ends switch -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/5_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:22 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_X2-Pad7_ Net-_U1-Pad8_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad7_ 4_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_X1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad4_ Net-_X2-Pad7_ 4_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/5_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:22 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_X2-Pad7_ Net-_U1-Pad8_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad7_ 4_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_X1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad4_ Net-_X2-Pad7_ 4_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/5_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:22 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_X2-Pad7_ Net-_U1-Pad8_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad7_ 4_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_X1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad4_ Net-_X2-Pad7_ 4_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/5_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:22 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_X2-Pad7_ Net-_U1-Pad8_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad7_ 4_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_X1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad4_ Net-_X2-Pad7_ 4_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/5_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:22 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_X2-Pad7_ Net-_U1-Pad8_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad7_ 4_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_X1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad4_ Net-_X2-Pad7_ 4_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/5_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dac\5_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:22 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_X2-Pad7_ Net-_U1-Pad8_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad7_ 4_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_X1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad4_ Net-_X2-Pad7_ 4_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/8_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\8_bit_dac\8_bit_dac.cir 2 | 3 | .include 7_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad10_ net-_x1-pad10_ net-_x2-pad10_ net-_u1-pad11_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad8_ net-_u1-pad7_ net-_x1-pad10_ 7_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad8_ net-_u1-pad9_ net-_u1-pad7_ net-_x2-pad10_ 7_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/8_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\8_bit_dac\8_bit_dac.cir 2 | 3 | .include 7_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad10_ net-_x1-pad10_ net-_x2-pad10_ net-_u1-pad11_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad8_ net-_u1-pad7_ net-_x1-pad10_ 7_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad8_ net-_u1-pad9_ net-_u1-pad7_ net-_x2-pad10_ 7_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/8_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\8_bit_dac\8_bit_dac.cir 2 | 3 | .include 7_bit_dac.sub 4 | .include switch.sub 5 | x3 net-_u1-pad10_ net-_x1-pad10_ net-_x2-pad10_ net-_u1-pad11_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad8_ net-_u1-pad7_ net-_x1-pad10_ 7_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_x1-pad8_ net-_u1-pad9_ net-_u1-pad7_ net-_x2-pad10_ 7_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/6_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:50 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_U1-Pad5_ Net-_X1-Pad8_ 5_bit_dac 10 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_X2-Pad8_ 5_bit_dac 11 | X3 Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_X2-Pad8_ Net-_U1-Pad9_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/6_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:50 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_U1-Pad5_ Net-_X1-Pad8_ 5_bit_dac 10 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_X2-Pad8_ 5_bit_dac 11 | X3 Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_X2-Pad8_ Net-_U1-Pad9_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/6_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:50 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_U1-Pad5_ Net-_X1-Pad8_ 5_bit_dac 10 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_X2-Pad8_ 5_bit_dac 11 | X3 Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_X2-Pad8_ Net-_U1-Pad9_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/6_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:50 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_U1-Pad5_ Net-_X1-Pad8_ 5_bit_dac 10 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_X2-Pad8_ 5_bit_dac 11 | X3 Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_X2-Pad8_ Net-_U1-Pad9_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/6_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dac\6_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:24:50 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_U1-Pad5_ Net-_X1-Pad8_ 5_bit_dac 10 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_X2-Pad8_ 5_bit_dac 11 | X3 Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_X2-Pad8_ Net-_U1-Pad9_ switch 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/9_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\9_bit_dac\9_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 8_bit_dac.sub 5 | x3 net-_u1-pad11_ net-_x1-pad11_ net-_x2-pad11_ net-_u1-pad12_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_x1-pad9_ net-_u1-pad8_ net-_x1-pad11_ 8_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_x1-pad9_ net-_u1-pad10_ net-_u1-pad8_ net-_x2-pad11_ 8_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/9_bit_dac.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\9_bit_dac\9_bit_dac.cir 2 | 3 | .include switch.sub 4 | .include 8_bit_dac.sub 5 | x3 net-_u1-pad11_ net-_x1-pad11_ net-_x2-pad11_ net-_u1-pad12_ switch 6 | x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_x1-pad9_ net-_u1-pad8_ net-_x1-pad11_ 8_bit_dac 7 | x2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_x1-pad9_ net-_u1-pad10_ net-_u1-pad8_ net-_x2-pad11_ 8_bit_dac 8 | * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port 9 | .tran 0e-00 0e-00 0e-00 10 | 11 | * Control Statements 12 | .control 13 | run 14 | print allv > plot_data_v.txt 15 | print alli > plot_data_i.txt 16 | .endc 17 | .end 18 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/2_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dac\2_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:23:08 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 250 10 | R2 Net-_R2-Pad1_ Net-_R1-Pad1_ 250 11 | R3 Net-_R3-Pad1_ Net-_R2-Pad1_ 250 12 | R4 Net-_R4-Pad1_ Net-_R3-Pad1_ 250 13 | X1 Net-_U1-Pad3_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_X1-Pad4_ switch 14 | X2 Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_R4-Pad1_ Net-_X2-Pad4_ switch 15 | X3 Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad5_ switch 16 | U1 Net-_R1-Pad2_ Net-_R4-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT 17 | 18 | .end 19 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/7_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:10 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad9_ Net-_X1-Pad9_ Net-_X2-Pad9_ Net-_U1-Pad10_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_U1-Pad6_ Net-_X1-Pad9_ 6_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_X2-Pad9_ 6_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/7_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:10 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad9_ Net-_X1-Pad9_ Net-_X2-Pad9_ Net-_U1-Pad10_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_U1-Pad6_ Net-_X1-Pad9_ 6_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_X2-Pad9_ 6_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/7_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:10 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad9_ Net-_X1-Pad9_ Net-_X2-Pad9_ Net-_U1-Pad10_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_U1-Pad6_ Net-_X1-Pad9_ 6_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_X2-Pad9_ 6_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/switch/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/7_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\7_bit_dac\7_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:10 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad9_ Net-_X1-Pad9_ Net-_X2-Pad9_ Net-_U1-Pad10_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_X1-Pad7_ Net-_U1-Pad6_ Net-_X1-Pad9_ 6_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_X2-Pad9_ 6_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/switch.cir.out: -------------------------------------------------------------------------------- 1 | * d:\8.softwares\esim\fossee\esim\library\subcircuitlibrary\switch\switch.cir 2 | 3 | .include nmos_180nm.lib 4 | .include pmos_180nm.lib 5 | m2 net-_m1-pad1_ /digital_input net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 6 | m4 /vout net-_m1-pad1_ /vin_1 /vin_1 pfet W=4000n L=180n M=1 7 | m1 net-_m1-pad1_ /digital_input gnd gnd nfet W=1800n L=180n M=1 8 | m3 /vout net-_m1-pad1_ /vin_2 gnd nfet W=1800n L=180n M=1 9 | * u1 /digital_input /vin_1 /vin_2 /vout port 10 | v1 net-_m2-pad3_ gnd 3.3 11 | m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ pfet W=4000n L=180n M=1 12 | m5 net-_m5-pad1_ net-_m1-pad1_ gnd gnd nfet W=1800n L=180n M=1 13 | m7 /vin_1 net-_m5-pad1_ /vout gnd nfet W=1800n L=180n M=1 14 | m8 /vout net-_m5-pad1_ /vin_2 /vout pfet W=4000n L=180n M=1 15 | .tran 0e-03 0e-03 0e-00 16 | 17 | * Control Statements 18 | .control 19 | run 20 | print allv > plot_data_v.txt 21 | print alli > plot_data_i.txt 22 | .endc 23 | .end 24 | -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/switch/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/8_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\8_bit_dac\8_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:28 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad10_ Net-_X1-Pad10_ Net-_X2-Pad10_ Net-_U1-Pad11_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_U1-Pad7_ Net-_X1-Pad10_ 7_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_X1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad7_ Net-_X2-Pad10_ 7_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/8_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\8_bit_dac\8_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:28 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad10_ Net-_X1-Pad10_ Net-_X2-Pad10_ Net-_U1-Pad11_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_U1-Pad7_ Net-_X1-Pad10_ 7_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_X1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad7_ Net-_X2-Pad10_ 7_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/8_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\8_bit_dac\8_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:28 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad10_ Net-_X1-Pad10_ Net-_X2-Pad10_ Net-_U1-Pad11_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X1-Pad8_ Net-_U1-Pad7_ Net-_X1-Pad10_ 7_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_X1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad7_ Net-_X2-Pad10_ 7_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/switch.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switch\switch.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:22:46 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | M2 Net-_M1-Pad1_ /digital_input Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 10 | M4 /Vout Net-_M1-Pad1_ /Vin_1 /Vin_1 eSim_MOS_P 11 | M1 Net-_M1-Pad1_ /digital_input GND GND eSim_MOS_N 12 | M3 /Vout Net-_M1-Pad1_ /Vin_2 GND eSim_MOS_N 13 | U1 /digital_input /Vin_1 /Vin_2 /Vout PORT 14 | v1 Net-_M2-Pad3_ GND 3.3 15 | M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P 16 | M5 Net-_M5-Pad1_ Net-_M1-Pad1_ GND GND eSim_MOS_N 17 | M7 /Vin_1 Net-_M5-Pad1_ /Vout GND eSim_MOS_N 18 | M8 /Vout Net-_M5-Pad1_ /Vin_2 /Vout eSim_MOS_P 19 | 20 | .end 21 | -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/9_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\9_bit_dac\9_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:43 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad11_ Net-_X1-Pad11_ Net-_X2-Pad11_ Net-_U1-Pad12_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_X1-Pad9_ Net-_U1-Pad8_ Net-_X1-Pad11_ 8_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_X1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad8_ Net-_X2-Pad11_ 8_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/9_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\9_bit_dac\9_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 11:25:43 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | X3 Net-_U1-Pad11_ Net-_X1-Pad11_ Net-_X2-Pad11_ Net-_U1-Pad12_ switch 10 | X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_X1-Pad9_ Net-_U1-Pad8_ Net-_X1-Pad11_ 8_bit_dac 11 | X2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_X1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad8_ Net-_X2-Pad11_ 8_bit_dac 12 | U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT 13 | 14 | .end 15 | -------------------------------------------------------------------------------- /Pre-Layout and Simulation/10_bit_dac.cir: -------------------------------------------------------------------------------- 1 | * D:\DAC\esim-DAC\10_bit_dac\10_bit_dac.cir 2 | 3 | * EESchema Netlist Version 1.1 (Spice format) creation date: 08/22/20 13:05:10 4 | 5 | * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N 6 | * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 7 | 8 | * Sheet Name: / 9 | v9 Net-_X1-Pad9_ GND 3.3 10 | X3 Net-_X3-Pad1_ Net-_X1-Pad12_ Net-_X2-Pad12_ Vout switch 11 | v1 Net-_X1-Pad1_ GND pulse 12 | v2 Net-_X1-Pad2_ GND pulse 13 | v3 Net-_X1-Pad3_ GND pulse 14 | v4 Net-_X1-Pad4_ GND pulse 15 | v5 Net-_X1-Pad5_ GND pulse 16 | v11 Net-_X3-Pad1_ GND pulse 17 | U1 Vout plot_v1 18 | v6 Net-_X1-Pad6_ GND pulse 19 | v7 Net-_X1-Pad7_ GND pulse 20 | v8 Net-_X1-Pad8_ GND pulse 21 | v10 Net-_X1-Pad11_ GND pulse 22 | X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_X1-Pad6_ Net-_X1-Pad7_ Net-_X1-Pad8_ Net-_X1-Pad9_ Net-_X1-Pad10_ Net-_X1-Pad11_ Net-_X1-Pad12_ 9_bit_dac 23 | X2 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_X1-Pad6_ Net-_X1-Pad7_ Net-_X1-Pad8_ Net-_X1-Pad10_ GND Net-_X1-Pad11_ Net-_X2-Pad12_ 9_bit_dac 24 | C1 Vout GND 5000p 25 | 26 | .end 27 | -------------------------------------------------------------------------------- /Layout and Simulation/3BitDac.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech scmos 3 | timestamp 1599268620 4 | << metal1 >> 5 | rect -7 210 -2 216 6 | rect 272 95 286 98 7 | rect 283 49 286 95 8 | rect 212 45 286 49 9 | rect 212 37 215 45 10 | rect -9 14 13 20 11 | rect 157 1 162 5 12 | rect 272 4 283 7 13 | rect 209 -38 212 -22 14 | rect 209 -42 290 -38 15 | rect 287 -94 290 -42 16 | rect 270 -97 290 -94 17 | rect 7 -182 11 -178 18 | << metal3 >> 19 | rect 17 202 21 210 20 | rect 152 150 156 159 21 | rect 136 92 154 97 22 | rect 16 49 20 56 23 | rect 16 5 19 49 24 | rect 136 -30 140 92 25 | rect 136 -34 154 -30 26 | rect 150 -43 154 -34 27 | << metal5 >> 28 | rect 80 94 101 99 29 | rect 96 88 133 94 30 | rect 96 1 101 88 31 | rect 128 62 133 88 32 | rect 128 59 170 62 33 | rect 166 49 170 59 34 | rect 166 48 180 49 35 | rect 166 45 188 48 36 | rect 176 44 188 45 37 | << metal6 >> 38 | rect 24 -87 33 14 39 | rect 175 -37 181 -32 40 | rect 160 -44 181 -37 41 | rect 160 -140 165 -44 42 | use 2BitDac 2BitDac_0 43 | timestamp 1599268620 44 | transform 1 0 -61 0 1 183 45 | box 52 -171 333 27 46 | use switchNew switchNew_0 47 | timestamp 1599222484 48 | transform 1 0 85 0 1 -35 49 | box 69 -1 187 81 50 | use 2BitDac 2BitDac_1 51 | timestamp 1599268620 52 | transform 1 0 -63 0 1 -9 53 | box 52 -171 333 27 54 | << labels >> 55 | rlabel metal1 283 4 283 7 7 V_out3 56 | rlabel metal1 -7 216 -2 216 5 R_in3 57 | rlabel metal1 7 -182 11 -182 1 R_out3 58 | << end >> 59 | -------------------------------------------------------------------------------- /subcircuits/2_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/9_bit_dac/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /Pre-Layout and Simulation/2_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/3_bit_dac/3_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/3_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/4_bit_dac/4_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/3_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/4_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/5_bit_dac/5_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/3_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/4_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/5_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/6_bit_dac/6_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/3_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/4_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/5_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/6_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/7_bit_dac/7_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/3_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\2_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/4_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/5_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecmsms -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/6_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/7_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\6_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec -------------------------------------------------------------------------------- /subcircuits/8_bit_dac/8_bit_dac_Previous_Values.xml: -------------------------------------------------------------------------------- 1 | D:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\switchD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\7_bit_dacD:\8.Softwares\eSim\FOSSEE\eSim\library\SubcircuitLibrary\7_bit_dactruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec --------------------------------------------------------------------------------