├── 1 Getting Started ├── 1.1 step_one.v └── 1.2 output_zero.v ├── 2 Verilog Language ├── 2.1 Basics │ ├── 2.1.1 simple_wire.v │ ├── 2.1.2 four_wires.v │ ├── 2.1.3 inverter.v │ ├── 2.1.4 and_gate.v │ ├── 2.1.5 nor_gate.v │ ├── 2.1.6 xnor_gate.v │ ├── 2.1.7 declaring_wires.v │ └── 2.1.8 7458_chip.v ├── 2.2 Vectors │ ├── 2.2.1 vectors.v │ ├── 2.2.2 vectors_in_more_detail.v │ ├── 2.2.3 vector_part_select.v │ ├── 2.2.4 bitwise_operators.v │ ├── 2.2.5 four-input_gates.v │ ├── 2.2.6 vector_concatenation_operator.v │ ├── 2.2.7 vector_reversal_1.v │ ├── 2.2.8 replication_operator.v │ └── 2.2.9 more_replication.v ├── 2.3 Modules Hierachy │ ├── 2.3.1 module.v │ ├── 2.3.2 module_pos.v │ ├── 2.3.3 module_name.v │ ├── 2.3.4 module_shift.v │ ├── 2.3.5 module_shift8.v │ ├── 2.3.6 module_add.v │ ├── 2.3.7 module_fadd.v │ ├── 2.3.8 module_cseladd.v │ └── 2.3.9 module_addsub.v ├── 2.4 Procedures │ ├── 2.4.1 alwaysblock1.v │ ├── 2.4.2 alwaysblock2.v │ ├── 2.4.3 always_if.v │ ├── 2.4.4 always_if2.v │ ├── 2.4.5 always_case.v │ ├── 2.4.6 always_case2.v │ ├── 2.4.7 always_casez.v │ └── 2.4.8 always_nolatches.v └── 2.5 More Verilog Features │ ├── 2.5.1 conditional.v │ ├── 2.5.2 reduction.v │ ├── 2.5.3 gate100.v │ ├── 2.5.4 vector100r.v │ ├── 2.5.5 popcount255.v │ ├── 2.5.6 adder100i.v │ └── 2.5.7 bcdadd100.v ├── 3 Circuit ├── 3.1 Combinational Logic │ ├── 3.1.1 Basic Gates │ │ ├── 3.1.1.1 wire.v │ │ ├── 3.1.1.10 simple circuit A.v │ │ ├── 3.1.1.11 simple circuit B.v │ │ ├── 3.1.1.12 combine circuits A and B.v │ │ ├── 3.1.1.13 ring or vibrate.v │ │ ├── 3.1.1.14 thermostat.v │ │ ├── 3.1.1.15 3-bit population count.v │ │ ├── 3.1.1.16 gates and vectors.v │ │ ├── 3.1.1.17 even longer vectors.v │ │ ├── 3.1.1.2 gnd.v │ │ ├── 3.1.1.3 another gate.v │ │ ├── 3.1.1.4 two gates.v │ │ ├── 3.1.1.5 more logic gates.v │ │ ├── 3.1.1.6 7420 chip.v │ │ ├── 3.1.1.8 truth tables.v │ │ └── 3.1.1.9 two-bit equality.v │ ├── 3.1.2 Multiplexers │ │ ├── 3.1.2.1 2-to-1 multiplexer.v │ │ ├── 3.1.2.2 2-to-1 bus multiplexer.v │ │ ├── 3.1.2.3 9-to-1 multiplexer.v │ │ ├── 3.1.2.4 256-to-1 4-bit multiplexer.v │ │ └── 3.1.2.4 256-to-1 multiplexer.v │ ├── 3.1.3 Arithmetic Circuits │ │ ├── 3.1.3.1 half adder.v │ │ ├── 3.1.3.2 full adder.v │ │ ├── 3.1.3.3 3-bit binary adder.v │ │ ├── 3.1.3.4 adder.v │ │ ├── 3.1.3.5 signed addition overflow.v │ │ ├── 3.1.3.6 100-bit binary adder.v │ │ └── 3.1.3.7 4-digit BCD adder.v │ └── 3.1.4 Karnaugh Map to Circuit │ │ ├── 3.1.4.1 kmap1.v │ │ ├── 3.1.4.2 kmap2.v │ │ ├── 3.1.4.3 kmap3.v │ │ ├── 3.1.4.4 kmap4.v │ │ ├── 3.1.4.5 minimum SOP and POS.v │ │ ├── 3.1.4.6 kmap5.v │ │ ├── 3.1.4.7 kmap6.v │ │ └── 3.1.4.8 kmap with a multiplexer.v ├── 3.2 Sequential Logic │ ├── 3.2.1 Latches and Flip-Flops │ │ ├── 3.2.1.1 DFF.v │ │ ├── 3.2.1.10 DFF_gate.v │ │ ├── 3.2.1.11 MUX and DFF.v │ │ ├── 3.2.1.12 MUX and DFF n.v │ │ ├── 3.2.1.13 DFFs and Gates.v │ │ ├── 3.2.1.14 Truth Table.v │ │ ├── 3.2.1.15 Edge Detector.v │ │ ├── 3.2.1.16 Dual Edge Detector.v │ │ ├── 3.2.1.17 Dual-edge triggered FF.v │ │ ├── 3.2.1.17 Edge Capture.v │ │ ├── 3.2.1.2 8-bit DFF.v │ │ ├── 3.2.1.3 DFF_reset.v │ │ ├── 3.2.1.4 DFF_reset2.v │ │ ├── 3.2.1.5 DFF_areset.v │ │ ├── 3.2.1.6 DFF_byteEnable.v │ │ ├── 3.2.1.7 D Latch.v │ │ ├── 3.2.1.8 DFF_ar.v │ │ └── 3.2.1.9 DFF_r.v │ ├── 3.2.2 Counters │ │ ├── 3.2.2.1 4-bit BC.v │ │ ├── 3.2.2.2 decade counter.v │ │ ├── 3.2.2.3 decade counter2.v │ │ ├── 3.2.2.4 counter 1-to-12.v │ │ ├── 3.2.2.5 slow decade counter.v │ │ ├── 3.2.2.6 counter 1000.v │ │ ├── 3.2.2.7 4-digit decimal counter.v │ │ └── 3.2.2.8 12-hour clock.v │ ├── 3.2.3 Shift Registers │ │ ├── 3.2.3.1 4-bit SR.v │ │ ├── 3.2.3.2 left_right rotator.v │ │ ├── 3.2.3.3 left_right_arithmetic_shift.v │ │ ├── 3.2.3.4 5-bit LFSR.v │ │ ├── 3.2.3.5 3-bit LFSR.v │ │ ├── 3.2.3.6 32-bit LFSR.v │ │ ├── 3.2.3.7 Shift Register 1.v │ │ ├── 3.2.3.8 Shift Register 2.v │ │ └── 3.2.3.9 3-input LUT.v │ ├── 3.2.4 More Circuits │ │ ├── 3.2.4.1 Rule 90.v │ │ ├── 3.2.4.2 Rule 110.v │ │ └── 3.2.4.3 Conway's Game of Life.v │ └── 3.2.5 Finite State Machines │ │ ├── 3.2.5.1 FSM1_ar.v │ │ ├── 3.2.5.10 Lemmings 1.v │ │ ├── 3.2.5.11 Lemmings 2.v │ │ ├── 3.2.5.12 Lemmings 3.v │ │ ├── 3.2.5.13 Lemmings 4.v │ │ ├── 3.2.5.14 One-hot FSM.v │ │ ├── 3.2.5.15 PS2 packet parser.v │ │ ├── 3.2.5.16 PS2 packet parser and datapath.v │ │ ├── 3.2.5.17 serial receiver.v │ │ ├── 3.2.5.18 serial receiver and datapath.v │ │ ├── 3.2.5.19 serial receiver with parity checking.v │ │ ├── 3.2.5.2 FSM1_r.v │ │ ├── 3.2.5.20 sequence recognition.v │ │ ├── 3.2.5.21 Q8 Mealy FSM.v │ │ ├── 3.2.5.22 Q5a serial 2s complementer Moore.v │ │ ├── 3.2.5.23 Q5b serial 2s complementer Mealy.v │ │ ├── 3.2.5.24 Q3a FSM4.v │ │ ├── 3.2.5.25 Q3b FSM5.v │ │ ├── 3.2.5.26 Q3c FSM logic.v │ │ ├── 3.2.5.27 Q6b FSM next-state logic.v │ │ ├── 3.2.5.28 Q6c FSM one-hot next-state logic.v │ │ ├── 3.2.5.29 Q6 FSM7.v │ │ ├── 3.2.5.3 FSM2_ar.v │ │ ├── 3.2.5.30 Q2a FSM8.v │ │ ├── 3.2.5.31 Q2b one-hot FSM equations.v │ │ └── 3.2.5.32 Q2a FSM9.v └── 3.3 Building Larger Circuits │ ├── 3.3.1 counter with period 1000.v │ ├── 3.3.2 4-bit SR and down counter.v │ ├── 3.3.3 FSM 1101 sequence recognizer.v │ ├── 3.3.4 FSM Enable SR.v │ ├── 3.3.5 FSM Complete FSM.v │ ├── 3.3.6 Complete Timer.v │ └── 3.3.7 One-hot logic equations.v ├── 4 Verification Reading Simulations ├── 4.1 Finding bugs in code │ ├── 4.1.1 MUX1.v │ ├── 4.1.2 NAND.v │ ├── 4.1.3 MUX2.v │ ├── 4.1.4 Add_SUB.v │ └── 4.1.5 Case statement.v └── 4.2 Build a circuit from a simulation waveform │ ├── 4.2.1 Combinational Circuit 1.v │ ├── 4.2.10 Sequential circuit 7.v │ ├── 4.2.2 Combinational Circuit 2.v │ ├── 4.2.3 Combinational Circuit 3.v │ ├── 4.2.4 Combinational circuit 4.v │ ├── 4.2.5 Combinational Circuit 5.v │ ├── 4.2.6 Combinational Circuit 6.v │ ├── 4.2.7 Sequential circuit 7.v │ ├── 4.2.8 Sequential circuit 7.v │ └── 4.2.9 Sequential circuit 7.v ├── 5 Verification Writing Testbenches ├── 5.1 Clock.v ├── 5.2 Testbench1.v ├── 5.3 AND Gate.v ├── 5.4 Testbench2.v └── 5.5 TFF.v ├── README.md └── Tips.md /1 Getting Started/1.1 step_one.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/1 Getting Started/1.1 step_one.v -------------------------------------------------------------------------------- /1 Getting Started/1.2 output_zero.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/1 Getting Started/1.2 output_zero.v -------------------------------------------------------------------------------- /2 Verilog Language/2.1 Basics/2.1.1 simple_wire.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/2 Verilog Language/2.1 Basics/2.1.1 simple_wire.v -------------------------------------------------------------------------------- /2 Verilog Language/2.1 Basics/2.1.2 four_wires.v: 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vector_part_select.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/2 Verilog Language/2.2 Vectors/2.2.3 vector_part_select.v -------------------------------------------------------------------------------- /2 Verilog Language/2.2 Vectors/2.2.4 bitwise_operators.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/2 Verilog Language/2.2 Vectors/2.2.4 bitwise_operators.v -------------------------------------------------------------------------------- /2 Verilog Language/2.2 Vectors/2.2.5 four-input_gates.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/2 Verilog Language/2.2 Vectors/2.2.5 four-input_gates.v -------------------------------------------------------------------------------- /2 Verilog Language/2.2 Vectors/2.2.6 vector_concatenation_operator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/2 Verilog Language/2.2 Vectors/2.2.6 vector_concatenation_operator.v -------------------------------------------------------------------------------- /2 Verilog Language/2.2 Vectors/2.2.7 vector_reversal_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/2 Verilog Language/2.2 Vectors/2.2.7 vector_reversal_1.v -------------------------------------------------------------------------------- /2 Verilog Language/2.2 Vectors/2.2.8 replication_operator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/y-C-x/HDLBits_Solution/HEAD/2 Verilog Language/2.2 Vectors/2.2.8 replication_operator.v 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