├── README.md ├── rtl ├── alu.v ├── array.vh ├── cache.v ├── cpu.v ├── csr.v ├── csr_def.vh ├── decode.v ├── defines.vh ├── div.v ├── encode.v ├── forward.v ├── gpr.v ├── hazard.v ├── lsu.v ├── mem.v ├── mul.v ├── mux.v ├── pc.v ├── pipeline_regs.v ├── ram.v ├── rom.v ├── rvc.v ├── rvc_def.vh ├── testbench.v └── top.v ├── sim ├── Makefile └── sim_main.cpp └── test ├── device ├── rv32i_m │ ├── C │ │ └── Makefile.include │ ├── I │ │ └── Makefile.include │ ├── M │ │ └── Makefile.include │ ├── Zifencei │ │ └── Makefile.include │ └── privilege │ │ └── Makefile.include └── rv64i_m │ ├── C │ └── Makefile.include │ ├── I │ └── Makefile.include │ ├── M │ └── Makefile.include │ ├── Zifencei │ └── Makefile.include │ └── privilege │ └── Makefile.include ├── link.ld └── model_test.h /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yang-le/riscv_cpu/HEAD/README.md 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