├── cmsis ├── .readme.md ├── core_cmFunc.h └── core_cmInstr.h ├── rtty ├── .readme.md ├── Debug │ ├── .readme.md │ ├── bin │ │ └── .readme.md │ └── obj │ │ ├── .readme.md │ │ ├── fun.o │ │ ├── init.o │ │ ├── main.o │ │ ├── misc.o │ │ ├── f_rtty.o │ │ ├── syscalls.o │ │ ├── stm32f10x_adc.o │ │ ├── stm32f10x_dma.o │ │ ├── stm32f10x_flash.o │ │ ├── stm32f10x_gpio.o │ │ ├── stm32f10x_pwr.o │ │ ├── stm32f10x_rcc.o │ │ ├── stm32f10x_spi.o │ │ ├── stm32f10x_tim.o │ │ ├── stm32f10x_usart.o │ │ ├── system_stm32f10x.o │ │ ├── startup_stm32f10x_md_vl.o │ │ ├── history.xml │ │ └── dependencies.xml └── rtty.elf.xcodeproj │ ├── .readme.md │ └── project.pbxproj ├── stm_lib ├── .readme.md ├── inc │ ├── .readme.md │ ├── stm32f10x_pwr.h │ ├── misc.h │ ├── stm32f10x_usart.h │ ├── stm32f10x_spi.h │ └── stm32f10x_gpio.h └── src │ ├── .readme.md │ ├── stm32f10x_flash.c │ ├── stm32f10x_usart.c │ ├── misc.c │ └── stm32f10x_pwr.c ├── cmsis_boot ├── .readme.md ├── startup │ ├── .readme.md │ └── startup_stm32f10x_md_vl.c ├── stm32f10x.h ├── system_stm32f10x.h └── stm32f10x_conf.h ├── syscalls ├── .readme.md └── syscalls.c ├── f_rtty.h ├── init.h ├── rtty.comemgui ├── README.md ├── fun.h ├── f_rtty.c ├── rtty.comarker ├── fun.c ├── rtty.coproj ├── init.c └── main.c /cmsis/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /rtty/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /stm_lib/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /cmsis_boot/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /rtty/Debug/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /stm_lib/inc/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /stm_lib/src/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /syscalls/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /rtty/Debug/bin/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /rtty/Debug/obj/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /cmsis_boot/startup/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /rtty/rtty.elf.xcodeproj/.readme.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /f_rtty.h: -------------------------------------------------------------------------------- 1 | unsigned char send_rtty( char *znak); 2 | -------------------------------------------------------------------------------- /cmsis_boot/stm32f10x.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/cmsis_boot/stm32f10x.h -------------------------------------------------------------------------------- /rtty/Debug/obj/fun.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/fun.o -------------------------------------------------------------------------------- /rtty/Debug/obj/init.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/init.o -------------------------------------------------------------------------------- /rtty/Debug/obj/main.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/main.o -------------------------------------------------------------------------------- /rtty/Debug/obj/misc.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/misc.o -------------------------------------------------------------------------------- /rtty/Debug/obj/f_rtty.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/f_rtty.o -------------------------------------------------------------------------------- /rtty/Debug/obj/syscalls.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/syscalls.o -------------------------------------------------------------------------------- /stm_lib/src/stm32f10x_flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/stm_lib/src/stm32f10x_flash.c -------------------------------------------------------------------------------- /stm_lib/src/stm32f10x_usart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/stm_lib/src/stm32f10x_usart.c -------------------------------------------------------------------------------- /init.h: -------------------------------------------------------------------------------- 1 | __IO uint16_t ADCVal[2]; 2 | void NVIC_Conf(void); 3 | void RCC_Conf(void); 4 | void init_port(void); 5 | -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_adc.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_adc.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_dma.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_dma.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_flash.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_flash.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_gpio.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_gpio.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_pwr.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_pwr.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_rcc.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_rcc.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_spi.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_spi.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_tim.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_tim.o -------------------------------------------------------------------------------- /rtty/Debug/obj/stm32f10x_usart.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/stm32f10x_usart.o -------------------------------------------------------------------------------- /rtty/Debug/obj/system_stm32f10x.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/system_stm32f10x.o -------------------------------------------------------------------------------- /rtty/Debug/obj/startup_stm32f10x_md_vl.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yanosik/STM32_RTTY/HEAD/rtty/Debug/obj/startup_stm32f10x_md_vl.o -------------------------------------------------------------------------------- /rtty.comemgui: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32_RTTY 2 | STM32 & SI4032 rtty test 3 | 4 | Use: 5 | https://www.wyzbee.com/download/Utilities/Software/CoIDE-1.7.8.exe 6 | 7 | And: 8 | https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q3-update/+download/gcc-arm-none-eabi-5_4-2016q3-20160926-win32.exe 9 | 10 | Have a nice day ;) 11 | -------------------------------------------------------------------------------- /fun.h: -------------------------------------------------------------------------------- 1 | int HexCharToInt(char ch); 2 | void print( char* s); 3 | void sendtogps(char* s, unsigned char cun); 4 | void send_hex(unsigned char data); 5 | uint8_t spi_sendrecv(uint16_t byte); 6 | unsigned char czytaj_GPS(unsigned char pos,unsigned char len, char *source, char * destination); 7 | uint16_t gps_CRC16_checksum (char *string); 8 | int srednia (int dana); 9 | -------------------------------------------------------------------------------- /f_rtty.c: -------------------------------------------------------------------------------- 1 | volatile unsigned char nr_bit =0; 2 | 3 | unsigned char send_rtty(char *znak) 4 | { 5 | nr_bit++; 6 | if (nr_bit ==1) 7 | { 8 | return 0; 9 | } 10 | if (nr_bit >1 && nr_bit <10) 11 | { 12 | if ((*(znak) >> (nr_bit-2)) & 0x01) 13 | { 14 | return 1; 15 | } 16 | else 17 | { 18 | return 0; 19 | } 20 | } 21 | 22 | if (nr_bit == 10) 23 | { 24 | return 1; 25 | } 26 | if (nr_bit == 11) 27 | { 28 | return 1; 29 | } 30 | 31 | nr_bit =0; 32 | return 2; 33 | 34 | } 35 | ; 36 | -------------------------------------------------------------------------------- /rtty.comarker: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /cmsis_boot/system_stm32f10x.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /** @addtogroup CMSIS 23 | * @{ 24 | */ 25 | 26 | /** @addtogroup stm32f10x_system 27 | * @{ 28 | */ 29 | 30 | /** 31 | * @brief Define to prevent recursive inclusion 32 | */ 33 | #ifndef __SYSTEM_STM32F10X_H 34 | #define __SYSTEM_STM32F10X_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /** @addtogroup STM32F10x_System_Includes 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | 49 | /** @addtogroup STM32F10x_System_Exported_types 50 | * @{ 51 | */ 52 | 53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /syscalls/syscalls.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//***** 2 | * @file stdio.c 3 | * @brief Implementation of newlib syscall 4 | ********************************************************************************/ 5 | 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | #undef errno 12 | extern int errno; 13 | extern int _end; 14 | 15 | /*This function is used for handle heap option*/ 16 | __attribute__ ((used)) 17 | caddr_t _sbrk ( int incr ) 18 | { 19 | static unsigned char *heap = NULL; 20 | unsigned char *prev_heap; 21 | 22 | if (heap == NULL) { 23 | heap = (unsigned char *)&_end; 24 | } 25 | prev_heap = heap; 26 | 27 | heap += incr; 28 | 29 | return (caddr_t) prev_heap; 30 | } 31 | 32 | __attribute__ ((used)) 33 | int link(char *old, char *new) 34 | { 35 | return -1; 36 | } 37 | 38 | __attribute__ ((used)) 39 | int _close(int file) 40 | { 41 | return -1; 42 | } 43 | 44 | __attribute__ ((used)) 45 | int _fstat(int file, struct stat *st) 46 | { 47 | st->st_mode = S_IFCHR; 48 | return 0; 49 | } 50 | 51 | __attribute__ ((used)) 52 | int _isatty(int file) 53 | { 54 | return 1; 55 | } 56 | 57 | __attribute__ ((used)) 58 | int _lseek(int file, int ptr, int dir) 59 | { 60 | return 0; 61 | } 62 | 63 | /*Low layer read(input) function*/ 64 | __attribute__ ((used)) 65 | int _read(int file, char *ptr, int len) 66 | { 67 | 68 | #if 0 69 | //user code example 70 | int i; 71 | (void)file; 72 | 73 | for(i = 0; i < len; i++) 74 | { 75 | // UART_GetChar is user's basic input function 76 | *ptr++ = UART_GetChar(); 77 | } 78 | 79 | #endif 80 | 81 | return len; 82 | } 83 | 84 | 85 | /*Low layer write(output) function*/ 86 | __attribute__ ((used)) 87 | int _write(int file, char *ptr, int len) 88 | { 89 | 90 | #if 0 91 | //user code example 92 | 93 | int i; 94 | (void)file; 95 | 96 | for(i = 0; i < len; i++) 97 | { 98 | // UART_PutChar is user's basic output function 99 | UART_PutChar(*ptr++); 100 | } 101 | #endif 102 | 103 | return len; 104 | } 105 | 106 | __attribute__ ((used)) 107 | void abort(void) 108 | { 109 | /* Abort called */ 110 | while(1); 111 | } 112 | 113 | /* --------------------------------- End Of File ------------------------------ */ 114 | -------------------------------------------------------------------------------- /cmsis_boot/stm32f10x_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file RTC/Calendar/stm32f10x_conf.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F10x_CONF_H 23 | #define __STM32F10x_CONF_H 24 | 25 | /* Includes ------------------------------------------------------------------*/ 26 | /* Uncomment the line below to enable peripheral header file inclusion */ 27 | /* #include "stm32f10x_adc.h" */ 28 | /* #include "stm32f10x_bkp.h" */ 29 | /* #include "stm32f10x_can.h" */ 30 | /* #include "stm32f10x_cec.h" */ 31 | /* #include "stm32f10x_crc.h" */ 32 | /* #include "stm32f10x_dac.h" */ 33 | /* #include "stm32f10x_dbgmcu.h" */ 34 | /* #include "stm32f10x_dma.h" */ 35 | /* #include "stm32f10x_exti.h" */ 36 | /* #include "stm32f10x_flash.h" */ 37 | /* #include "stm32f10x_fsmc.h" */ 38 | /* #include "stm32f10x_gpio.h" */ 39 | /* #include "stm32f10x_i2c.h" */ 40 | /* #include "stm32f10x_iwdg.h" */ 41 | /* #include "stm32f10x_pwr.h" */ 42 | /* #include "stm32f10x_rcc.h" */ 43 | /* #include "stm32f10x_rtc.h" */ 44 | /* #include "stm32f10x_sdio.h" */ 45 | /* #include "stm32f10x_spi.h" */ 46 | /* #include "stm32f10x_tim.h" */ 47 | /* #include "stm32f10x_usart.h" */ 48 | /* #include "stm32f10x_wwdg.h" */ 49 | /* #include "misc.h" */ /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 50 | 51 | 52 | /* Exported types ------------------------------------------------------------*/ 53 | /* Exported constants --------------------------------------------------------*/ 54 | /* Uncomment the line below to expanse the "assert_param" macro in the 55 | Standard Peripheral Library drivers code */ 56 | /* #define USE_FULL_ASSERT 1 */ 57 | 58 | /* Exported macro ------------------------------------------------------------*/ 59 | #ifdef USE_FULL_ASSERT 60 | 61 | /** 62 | * @brief The assert_param macro is used for function's parameters check. 63 | * @param expr: If expr is false, it calls assert_failed function 64 | * which reports the name of the source file and the source 65 | * line number of the call that failed. 66 | * If expr is true, it returns no value. 67 | * @retval None 68 | */ 69 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 70 | /* Exported functions ------------------------------------------------------- */ 71 | void assert_failed(uint8_t* file, uint32_t line); 72 | #else 73 | #define assert_param(expr) ((void)0) 74 | #endif /* USE_FULL_ASSERT */ 75 | 76 | #endif /* __STM32F10x_CONF_H */ 77 | 78 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 79 | -------------------------------------------------------------------------------- /rtty/Debug/obj/history.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | -------------------------------------------------------------------------------- /fun.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | const char ascii[] = "0123456789ABCDEF"; 5 | int srednia_u[5]={0,0,0,0,0}; 6 | 7 | int HexCharToInt(char ch) 8 | { 9 | if (ch < 48 || (ch > 57 && ch < 65) || ch > 70) return 0; 10 | return (ch < 58) ? ch - 48 : ch - 55; 11 | } 12 | 13 | void print( char* s) 14 | { 15 | while (*s) 16 | { 17 | while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET) 18 | { 19 | } 20 | USART_SendData(USART3, *(s++)); 21 | } 22 | } 23 | 24 | void sendtogps(char* s, unsigned char cun) 25 | { 26 | unsigned char CK_A=0; 27 | unsigned char CK_B=0; 28 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) 29 | { 30 | } 31 | USART_SendData(USART1, *(s++)); 32 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) 33 | { 34 | } 35 | USART_SendData(USART1, *(s++)); 36 | cun--; 37 | cun--; 38 | while (cun-- != 0) 39 | { 40 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) 41 | { 42 | } 43 | CK_A += *(s); 44 | CK_B += CK_A; 45 | USART_SendData(USART1, *(s++)); 46 | } 47 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) 48 | { 49 | } 50 | USART_SendData(USART1, CK_A); 51 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) 52 | { 53 | } 54 | USART_SendData(USART1, CK_B); 55 | } 56 | 57 | void send_hex(unsigned char data) 58 | { 59 | while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET) 60 | { 61 | } 62 | USART_SendData(USART3, ascii[data >> 4 ]); 63 | while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET) 64 | { 65 | } 66 | USART_SendData(USART3, ascii[data & 0x0f ]); 67 | } 68 | 69 | uint8_t spi_sendrecv(uint16_t byte) 70 | { 71 | GPIO_ResetBits(GPIOC, GPIO_Pin_13); 72 | // wait for tx buffer 73 | while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET); 74 | SPI_I2S_SendData(SPI2, byte); 75 | 76 | // wait for data in rx buffer 77 | while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET); 78 | GPIO_SetBits(GPIOC, GPIO_Pin_13); 79 | return SPI_I2S_ReceiveData(SPI2); 80 | } 81 | 82 | unsigned char czytaj_GPS(unsigned char pos,unsigned char len, char *source, char * destination) 83 | { 84 | char *wyn; 85 | char pet = 0; 86 | wyn=source; 87 | while( pos-- !=0) 88 | { 89 | while (*(wyn++) != ','); 90 | } 91 | if (*(wyn) == 0) 92 | { 93 | return 0; 94 | } 95 | else 96 | { 97 | while((*(wyn) !=',') && (*(wyn) != 0)&& (len-- !=0)) 98 | { 99 | *(destination++) = *(wyn++); 100 | pet = 1; 101 | } 102 | if (pet == 0) 103 | { 104 | return 0; 105 | } 106 | *(destination) = 0; 107 | } 108 | return 1; 109 | } 110 | 111 | uint16_t gps_CRC16_checksum (char *string) 112 | { 113 | uint16_t crc = 0xffff; 114 | char i; 115 | while (*(string) != 0) 116 | { 117 | crc = crc ^ (*(string++) << 8); 118 | for (i=0; i<8; i++) 119 | { 120 | if (crc & 0x8000) 121 | crc = (crc << 1) ^ 0x1021; 122 | else 123 | crc <<= 1; 124 | } 125 | } 126 | return crc; 127 | } 128 | 129 | int srednia (int dana) 130 | { 131 | volatile char nr_pom=0; 132 | volatile char first=1; 133 | char i; 134 | int sr=0; 135 | if(first) 136 | { 137 | for (i=0; i<5; i++) 138 | { 139 | srednia_u[i] = dana; 140 | } 141 | first =0; 142 | 143 | } 144 | srednia_u[nr_pom] = dana; 145 | if (++nr_pom >4) 146 | { 147 | nr_pom=0; 148 | } 149 | for (i=0; i<5; i++) 150 | { 151 | sr += srednia_u[i]; 152 | } 153 | sr = sr/5; 154 | return sr; 155 | } 156 | -------------------------------------------------------------------------------- /stm_lib/inc/stm32f10x_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_PWR_H 25 | #define __STM32F10x_PWR_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup PWR 39 | * @{ 40 | */ 41 | 42 | /** @defgroup PWR_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup PWR_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup PVD_detection_level 55 | * @{ 56 | */ 57 | 58 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 59 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 60 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 61 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 62 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 63 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 64 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 65 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 66 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ 67 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ 68 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ 69 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup Regulator_state_is_STOP_mode 75 | * @{ 76 | */ 77 | 78 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 79 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 80 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 81 | ((REGULATOR) == PWR_Regulator_LowPower)) 82 | /** 83 | * @} 84 | */ 85 | 86 | /** @defgroup STOP_mode_entry 87 | * @{ 88 | */ 89 | 90 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 91 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 92 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** @defgroup PWR_Flag 99 | * @{ 100 | */ 101 | 102 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 103 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 104 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 105 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 106 | ((FLAG) == PWR_FLAG_PVDO)) 107 | 108 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /** @defgroup PWR_Exported_Macros 118 | * @{ 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @defgroup PWR_Exported_Functions 126 | * @{ 127 | */ 128 | 129 | void PWR_DeInit(void); 130 | void PWR_BackupAccessCmd(FunctionalState NewState); 131 | void PWR_PVDCmd(FunctionalState NewState); 132 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 133 | void PWR_WakeUpPinCmd(FunctionalState NewState); 134 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 135 | void PWR_EnterSTANDBYMode(void); 136 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 137 | void PWR_ClearFlag(uint32_t PWR_FLAG); 138 | 139 | #ifdef __cplusplus 140 | } 141 | #endif 142 | 143 | #endif /* __STM32F10x_PWR_H */ 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 157 | -------------------------------------------------------------------------------- /rtty/Debug/obj/dependencies.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | -------------------------------------------------------------------------------- /stm_lib/src/misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes ------------------------------------------------------------------*/ 24 | #include "misc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup MISC 31 | * @brief MISC driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup MISC_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup MISC_Private_Defines 44 | * @{ 45 | */ 46 | 47 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 48 | /** 49 | * @} 50 | */ 51 | 52 | /** @defgroup MISC_Private_Macros 53 | * @{ 54 | */ 55 | 56 | /** 57 | * @} 58 | */ 59 | 60 | /** @defgroup MISC_Private_Variables 61 | * @{ 62 | */ 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup MISC_Private_FunctionPrototypes 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup MISC_Private_Functions 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @brief Configures the priority grouping: pre-emption priority and subpriority. 82 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 83 | * This parameter can be one of the following values: 84 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority 85 | * 4 bits for subpriority 86 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority 87 | * 3 bits for subpriority 88 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority 89 | * 2 bits for subpriority 90 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority 91 | * 1 bits for subpriority 92 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority 93 | * 0 bits for subpriority 94 | * @retval None 95 | */ 96 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 97 | { 98 | /* Check the parameters */ 99 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); 100 | 101 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ 102 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 103 | } 104 | 105 | /** 106 | * @brief Initializes the NVIC peripheral according to the specified 107 | * parameters in the NVIC_InitStruct. 108 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 109 | * the configuration information for the specified NVIC peripheral. 110 | * @retval None 111 | */ 112 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 113 | { 114 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 115 | 116 | /* Check the parameters */ 117 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 118 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); 119 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); 120 | 121 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 122 | { 123 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 124 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 125 | tmppre = (0x4 - tmppriority); 126 | tmpsub = tmpsub >> tmppriority; 127 | 128 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 129 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 130 | tmppriority = tmppriority << 0x04; 131 | 132 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 133 | 134 | /* Enable the Selected IRQ Channels --------------------------------------*/ 135 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 136 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 137 | } 138 | else 139 | { 140 | /* Disable the Selected IRQ Channels -------------------------------------*/ 141 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 143 | } 144 | } 145 | 146 | /** 147 | * @brief Sets the vector table location and Offset. 148 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. 149 | * This parameter can be one of the following values: 150 | * @arg NVIC_VectTab_RAM 151 | * @arg NVIC_VectTab_FLASH 152 | * @param Offset: Vector Table base offset field. This value must be a multiple 153 | * of 0x200. 154 | * @retval None 155 | */ 156 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) 157 | { 158 | /* Check the parameters */ 159 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); 160 | assert_param(IS_NVIC_OFFSET(Offset)); 161 | 162 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 163 | } 164 | 165 | /** 166 | * @brief Selects the condition for the system to enter low power mode. 167 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 168 | * This parameter can be one of the following values: 169 | * @arg NVIC_LP_SEVONPEND 170 | * @arg NVIC_LP_SLEEPDEEP 171 | * @arg NVIC_LP_SLEEPONEXIT 172 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. 173 | * @retval None 174 | */ 175 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 176 | { 177 | /* Check the parameters */ 178 | assert_param(IS_NVIC_LP(LowPowerMode)); 179 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 180 | 181 | if (NewState != DISABLE) 182 | { 183 | SCB->SCR |= LowPowerMode; 184 | } 185 | else 186 | { 187 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 188 | } 189 | } 190 | 191 | /** 192 | * @brief Configures the SysTick clock source. 193 | * @param SysTick_CLKSource: specifies the SysTick clock source. 194 | * This parameter can be one of the following values: 195 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 196 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 197 | * @retval None 198 | */ 199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 200 | { 201 | /* Check the parameters */ 202 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 203 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 204 | { 205 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 206 | } 207 | else 208 | { 209 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 210 | } 211 | } 212 | 213 | /** 214 | * @} 215 | */ 216 | 217 | /** 218 | * @} 219 | */ 220 | 221 | /** 222 | * @} 223 | */ 224 | 225 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 226 | -------------------------------------------------------------------------------- /rtty.coproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 21 | 22 | 50 | 51 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | -------------------------------------------------------------------------------- /init.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include "init.h" 12 | SPI_InitTypeDef SPI_InitStructure; 13 | USART_InitTypeDef USART_InitStructure; 14 | GPIO_InitTypeDef GPIO_Conf; 15 | ADC_InitTypeDef ADC_InitStructure; 16 | DMA_InitTypeDef DMA_InitStructure; 17 | #define ADC1_DR_Address ((uint32_t)0x4001244C) 18 | 19 | void NVIC_Conf(void) 20 | { 21 | #ifdef VECT_TAB_RAM 22 | NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); 23 | #else // VECT_TAB_FLASH 24 | NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); 25 | #endif 26 | } 27 | 28 | void RCC_Conf(void) 29 | { 30 | ErrorStatus HSEStartUpStatus; 31 | RCC_DeInit(); 32 | RCC_HSEConfig(RCC_HSE_ON); 33 | HSEStartUpStatus = RCC_WaitForHSEStartUp(); 34 | if(HSEStartUpStatus == SUCCESS) 35 | { 36 | FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); 37 | FLASH_SetLatency(FLASH_Latency_2); 38 | RCC_HCLKConfig(RCC_SYSCLK_Div4); 39 | RCC_PCLK2Config(RCC_HCLK_Div4); 40 | RCC_PCLK1Config(RCC_HCLK_Div2); 41 | RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE); 42 | while(RCC_GetSYSCLKSource() != 0x04); 43 | } 44 | } 45 | 46 | void init_port(void) 47 | { 48 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 49 | GPIO_Conf.GPIO_Pin = GPIO_Pin_12; 50 | GPIO_Conf.GPIO_Mode = GPIO_Mode_Out_PP; 51 | GPIO_Conf.GPIO_Speed = GPIO_Speed_10MHz; 52 | GPIO_Init(GPIOA, &GPIO_Conf); 53 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); 54 | GPIO_Conf.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 ;//| GPIO_Pin_10; 55 | GPIO_Conf.GPIO_Mode = GPIO_Mode_Out_PP; 56 | GPIO_Conf.GPIO_Speed = GPIO_Speed_10MHz; 57 | GPIO_Init(GPIOB, &GPIO_Conf); 58 | TIM_TimeBaseInitTypeDef TIM2_TimeBaseInitStruct; 59 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2,ENABLE); 60 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2,DISABLE); 61 | TIM2_TimeBaseInitStruct.TIM_Prescaler = 1000; 62 | TIM2_TimeBaseInitStruct.TIM_CounterMode = TIM_CounterMode_Up; 63 | TIM2_TimeBaseInitStruct.TIM_Period = 6; 64 | TIM2_TimeBaseInitStruct.TIM_ClockDivision = TIM_CKD_DIV1; 65 | TIM2_TimeBaseInitStruct.TIM_RepetitionCounter = 0; 66 | TIM_TimeBaseInit(TIM2,&TIM2_TimeBaseInitStruct); 67 | TIM_ClearITPendingBit(TIM2,TIM_IT_Update); 68 | TIM_ITConfig(TIM2,TIM_IT_Update,ENABLE); 69 | NVIC_InitTypeDef NVIC_InitStructure; //create NVIC structure 70 | NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; 71 | NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; 72 | NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; 73 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 74 | NVIC_Init(&NVIC_InitStructure); 75 | TIM_Cmd(TIM2,ENABLE); 76 | GPIO_Conf.GPIO_Pin = GPIO_Pin_13 |GPIO_Pin_15; 77 | GPIO_Conf.GPIO_Mode = GPIO_Mode_AF_PP; 78 | GPIO_Conf.GPIO_Speed = GPIO_Speed_10MHz; 79 | GPIO_Init(GPIOB, &GPIO_Conf); 80 | GPIO_Conf.GPIO_Pin = GPIO_Pin_14; 81 | GPIO_Conf.GPIO_Mode = GPIO_Mode_IN_FLOATING; 82 | GPIO_Init(GPIOB, &GPIO_Conf); 83 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); 84 | GPIO_Conf.GPIO_Pin = GPIO_Pin_13; 85 | GPIO_Conf.GPIO_Mode = GPIO_Mode_Out_PP; 86 | GPIO_Conf.GPIO_Speed = GPIO_Speed_10MHz; 87 | GPIO_Init(GPIOC,&GPIO_Conf); 88 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); 89 | SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; 90 | SPI_InitStructure.SPI_Mode = SPI_Mode_Master; 91 | SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; 92 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; 93 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; 94 | SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16; 95 | SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; 96 | SPI_InitStructure.SPI_CRCPolynomial = 7; 97 | SPI_Init(SPI2, &SPI_InitStructure); 98 | SPI_SSOutputCmd(SPI2, ENABLE); 99 | SPI_Cmd(SPI2, ENABLE); 100 | SPI_InitStructure.SPI_Mode = SPI_Mode_Master; 101 | SPI_Init(SPI2, &SPI_InitStructure); 102 | GPIO_Conf.GPIO_Pin = GPIO_Pin_9; 103 | GPIO_Conf.GPIO_Mode = GPIO_Mode_AF_PP; 104 | GPIO_Conf.GPIO_Speed = GPIO_Speed_10MHz; 105 | GPIO_Init(GPIOA, &GPIO_Conf); 106 | GPIO_Conf.GPIO_Pin = GPIO_Pin_10; 107 | GPIO_Conf.GPIO_Mode = GPIO_Mode_IN_FLOATING; 108 | GPIO_Init(GPIOA, &GPIO_Conf); 109 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);// | RCC_APB2Periph_AFIO, ENABLE); 110 | USART_InitStructure.USART_BaudRate = 9600; //0x9c4; 111 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 112 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 113 | USART_InitStructure.USART_Parity = USART_Parity_No; 114 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 115 | USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; 116 | USART_Init(USART1, &USART_InitStructure); 117 | USART_Cmd(USART1, ENABLE); 118 | USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); 119 | NVIC_EnableIRQ(USART1_IRQn); 120 | GPIO_Conf.GPIO_Pin = GPIO_Pin_10; 121 | GPIO_Conf.GPIO_Mode = GPIO_Mode_AF_PP; 122 | GPIO_Conf.GPIO_Speed = GPIO_Speed_10MHz; 123 | GPIO_Init(GPIOB, &GPIO_Conf); 124 | GPIO_Conf.GPIO_Pin = GPIO_Pin_11; 125 | GPIO_Conf.GPIO_Mode = GPIO_Mode_IN_FLOATING; 126 | GPIO_Init(GPIOB, &GPIO_Conf); 127 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);// | RCC_APB2Periph_AFIO, ENABLE); 128 | USART_InitStructure.USART_BaudRate = 19200; //0x9c4; 129 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 130 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 131 | USART_InitStructure.USART_Parity = USART_Parity_No; 132 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 133 | USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; 134 | USART_Init(USART3, &USART_InitStructure); 135 | USART_Cmd(USART3, ENABLE); 136 | RCC_AHBPeriphClockCmd ( RCC_AHBPeriph_DMA1 , ENABLE ) ; 137 | DMA_DeInit(DMA1_Channel1); 138 | DMA_InitStructure.DMA_BufferSize = 2; 139 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; 140 | DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; 141 | DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) &ADCVal; 142 | ADC_DMACmd(ADC1, ENABLE); 143 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; 144 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 145 | DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; 146 | DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address; 147 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; 148 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 149 | DMA_InitStructure.DMA_Priority = DMA_Priority_High; 150 | DMA_Init(DMA1_Channel1, &DMA_InitStructure); 151 | DMA_Cmd(DMA1_Channel1, ENABLE); 152 | GPIO_Conf.GPIO_Mode = GPIO_Mode_AIN; 153 | GPIO_Conf.GPIO_Pin = GPIO_Pin_6 ; // that's ADC1 (PA5 on STM32) 154 | GPIO_Init(GPIOA, &GPIO_Conf); 155 | GPIO_Conf.GPIO_Mode = GPIO_Mode_AIN; 156 | GPIO_Conf.GPIO_Pin = GPIO_Pin_5 ; // that's ADC1 (PA3 on STM32) 157 | GPIO_Init(GPIOA, &GPIO_Conf); 158 | RCC_ADCCLKConfig (RCC_PCLK2_Div2); 159 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); 160 | ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; 161 | ADC_InitStructure.ADC_ScanConvMode = ENABLE; 162 | ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; // we work in continuous sampling mode 163 | ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; 164 | ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; 165 | ADC_InitStructure.ADC_NbrOfChannel = 2; 166 | ADC_Init ( ADC1, &ADC_InitStructure); //set config of ADC1 167 | ADC_RegularChannelConfig(ADC1,ADC_Channel_5, 1,ADC_SampleTime_28Cycles5); // define regular conversion config 168 | ADC_RegularChannelConfig(ADC1,ADC_Channel_6, 2,ADC_SampleTime_28Cycles5); // define regular conversion config 169 | ADC_DMACmd(ADC1, ENABLE); 170 | ADC_Cmd (ADC1,ENABLE); //enable ADC 171 | ADC_ResetCalibration(ADC1); // Reset previous calibration 172 | while(ADC_GetResetCalibrationStatus(ADC1)); 173 | ADC_StartCalibration(ADC1); // Start new calibration (ADC must be off at that time) 174 | while(ADC_GetCalibrationStatus(ADC1)); 175 | ADC_SoftwareStartConvCmd(ADC1, ENABLE); // start conversion (will be endless as we are in continuous mode) 176 | } 177 | -------------------------------------------------------------------------------- /stm_lib/inc/misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __MISC_H 25 | #define __MISC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup MISC 39 | * @{ 40 | */ 41 | 42 | /** @defgroup MISC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief NVIC Init Structure definition 48 | */ 49 | 50 | typedef struct 51 | { 52 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 53 | This parameter can be a value of @ref IRQn_Type 54 | (For the complete STM32 Devices IRQ Channels list, please 55 | refer to stm32f10x.h file) */ 56 | 57 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel 58 | specified in NVIC_IRQChannel. This parameter can be a value 59 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 60 | 61 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified 62 | in NVIC_IRQChannel. This parameter can be a value 63 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 64 | 65 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 66 | will be enabled or disabled. 67 | This parameter can be set either to ENABLE or DISABLE */ 68 | } NVIC_InitTypeDef; 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup NVIC_Priority_Table 75 | * @{ 76 | */ 77 | 78 | /** 79 | @code 80 | The table below gives the allowed values of the pre-emption priority and subpriority according 81 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function 82 | ============================================================================================================================ 83 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description 84 | ============================================================================================================================ 85 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority 86 | | | | 4 bits for subpriority 87 | ---------------------------------------------------------------------------------------------------------------------------- 88 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority 89 | | | | 3 bits for subpriority 90 | ---------------------------------------------------------------------------------------------------------------------------- 91 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority 92 | | | | 2 bits for subpriority 93 | ---------------------------------------------------------------------------------------------------------------------------- 94 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority 95 | | | | 1 bits for subpriority 96 | ---------------------------------------------------------------------------------------------------------------------------- 97 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority 98 | | | | 0 bits for subpriority 99 | ============================================================================================================================ 100 | @endcode 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** @defgroup MISC_Exported_Constants 108 | * @{ 109 | */ 110 | 111 | /** @defgroup Vector_Table_Base 112 | * @{ 113 | */ 114 | 115 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000) 116 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) 117 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ 118 | ((VECTTAB) == NVIC_VectTab_FLASH)) 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup System_Low_Power 124 | * @{ 125 | */ 126 | 127 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 128 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 129 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 130 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 131 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 132 | ((LP) == NVIC_LP_SLEEPONEXIT)) 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup Preemption_Priority_Group 138 | * @{ 139 | */ 140 | 141 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 142 | 4 bits for subpriority */ 143 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 144 | 3 bits for subpriority */ 145 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 146 | 2 bits for subpriority */ 147 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 148 | 1 bits for subpriority */ 149 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 150 | 0 bits for subpriority */ 151 | 152 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 153 | ((GROUP) == NVIC_PriorityGroup_1) || \ 154 | ((GROUP) == NVIC_PriorityGroup_2) || \ 155 | ((GROUP) == NVIC_PriorityGroup_3) || \ 156 | ((GROUP) == NVIC_PriorityGroup_4)) 157 | 158 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 159 | 160 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 161 | 162 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | /** @defgroup SysTick_clock_source 169 | * @{ 170 | */ 171 | 172 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 173 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 174 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 175 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 176 | /** 177 | * @} 178 | */ 179 | 180 | /** 181 | * @} 182 | */ 183 | 184 | /** @defgroup MISC_Exported_Macros 185 | * @{ 186 | */ 187 | 188 | /** 189 | * @} 190 | */ 191 | 192 | /** @defgroup MISC_Exported_Functions 193 | * @{ 194 | */ 195 | 196 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 197 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 198 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); 199 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 200 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 201 | 202 | #ifdef __cplusplus 203 | } 204 | #endif 205 | 206 | #endif /* __MISC_H */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /** 217 | * @} 218 | */ 219 | 220 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 221 | -------------------------------------------------------------------------------- /stm_lib/src/stm32f10x_pwr.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the PWR firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_pwr.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup PWR 31 | * @brief PWR driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup PWR_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup PWR_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* --------- PWR registers bit address in the alias region ---------- */ 48 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 49 | 50 | /* --- CR Register ---*/ 51 | 52 | /* Alias word address of DBP bit */ 53 | #define CR_OFFSET (PWR_OFFSET + 0x00) 54 | #define DBP_BitNumber 0x08 55 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 56 | 57 | /* Alias word address of PVDE bit */ 58 | #define PVDE_BitNumber 0x04 59 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 60 | 61 | /* --- CSR Register ---*/ 62 | 63 | /* Alias word address of EWUP bit */ 64 | #define CSR_OFFSET (PWR_OFFSET + 0x04) 65 | #define EWUP_BitNumber 0x08 66 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 67 | 68 | /* ------------------ PWR registers bit mask ------------------------ */ 69 | 70 | /* CR register bit mask */ 71 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) 72 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) 73 | 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @defgroup PWR_Private_Macros 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @defgroup PWR_Private_Variables 88 | * @{ 89 | */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup PWR_Private_FunctionPrototypes 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup PWR_Private_Functions 104 | * @{ 105 | */ 106 | 107 | /** 108 | * @brief Deinitializes the PWR peripheral registers to their default reset values. 109 | * @param None 110 | * @retval None 111 | */ 112 | void PWR_DeInit(void) 113 | { 114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 115 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 116 | } 117 | 118 | /** 119 | * @brief Enables or disables access to the RTC and backup registers. 120 | * @param NewState: new state of the access to the RTC and backup registers. 121 | * This parameter can be: ENABLE or DISABLE. 122 | * @retval None 123 | */ 124 | void PWR_BackupAccessCmd(FunctionalState NewState) 125 | { 126 | /* Check the parameters */ 127 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 128 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 129 | } 130 | 131 | /** 132 | * @brief Enables or disables the Power Voltage Detector(PVD). 133 | * @param NewState: new state of the PVD. 134 | * This parameter can be: ENABLE or DISABLE. 135 | * @retval None 136 | */ 137 | void PWR_PVDCmd(FunctionalState NewState) 138 | { 139 | /* Check the parameters */ 140 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 141 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 142 | } 143 | 144 | /** 145 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 146 | * @param PWR_PVDLevel: specifies the PVD detection level 147 | * This parameter can be one of the following values: 148 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 149 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 150 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 151 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 152 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 153 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 154 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 155 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 156 | * @retval None 157 | */ 158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 159 | { 160 | uint32_t tmpreg = 0; 161 | /* Check the parameters */ 162 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 163 | tmpreg = PWR->CR; 164 | /* Clear PLS[7:5] bits */ 165 | tmpreg &= CR_PLS_MASK; 166 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 167 | tmpreg |= PWR_PVDLevel; 168 | /* Store the new value */ 169 | PWR->CR = tmpreg; 170 | } 171 | 172 | /** 173 | * @brief Enables or disables the WakeUp Pin functionality. 174 | * @param NewState: new state of the WakeUp Pin functionality. 175 | * This parameter can be: ENABLE or DISABLE. 176 | * @retval None 177 | */ 178 | void PWR_WakeUpPinCmd(FunctionalState NewState) 179 | { 180 | /* Check the parameters */ 181 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 182 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 183 | } 184 | 185 | /** 186 | * @brief Enters STOP mode. 187 | * @param PWR_Regulator: specifies the regulator state in STOP mode. 188 | * This parameter can be one of the following values: 189 | * @arg PWR_Regulator_ON: STOP mode with regulator ON 190 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 191 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 192 | * This parameter can be one of the following values: 193 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 194 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 195 | * @retval None 196 | */ 197 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 198 | { 199 | uint32_t tmpreg = 0; 200 | /* Check the parameters */ 201 | assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 202 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 203 | 204 | /* Select the regulator state in STOP mode ---------------------------------*/ 205 | tmpreg = PWR->CR; 206 | /* Clear PDDS and LPDS bits */ 207 | tmpreg &= CR_DS_MASK; 208 | /* Set LPDS bit according to PWR_Regulator value */ 209 | tmpreg |= PWR_Regulator; 210 | /* Store the new value */ 211 | PWR->CR = tmpreg; 212 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 213 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 214 | 215 | /* Select STOP mode entry --------------------------------------------------*/ 216 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 217 | { 218 | /* Request Wait For Interrupt */ 219 | __WFI(); 220 | } 221 | else 222 | { 223 | /* Request Wait For Event */ 224 | __WFE(); 225 | } 226 | 227 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ 228 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 229 | } 230 | 231 | /** 232 | * @brief Enters STANDBY mode. 233 | * @param None 234 | * @retval None 235 | */ 236 | void PWR_EnterSTANDBYMode(void) 237 | { 238 | /* Clear Wake-up flag */ 239 | PWR->CR |= PWR_CR_CWUF; 240 | /* Select STANDBY mode */ 241 | PWR->CR |= PWR_CR_PDDS; 242 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 243 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 244 | /* This option is used to ensure that store operations are completed */ 245 | #if defined ( __CC_ARM ) 246 | __force_stores(); 247 | #endif 248 | /* Request Wait For Interrupt */ 249 | __WFI(); 250 | } 251 | 252 | /** 253 | * @brief Checks whether the specified PWR flag is set or not. 254 | * @param PWR_FLAG: specifies the flag to check. 255 | * This parameter can be one of the following values: 256 | * @arg PWR_FLAG_WU: Wake Up flag 257 | * @arg PWR_FLAG_SB: StandBy flag 258 | * @arg PWR_FLAG_PVDO: PVD Output 259 | * @retval The new state of PWR_FLAG (SET or RESET). 260 | */ 261 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 262 | { 263 | FlagStatus bitstatus = RESET; 264 | /* Check the parameters */ 265 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 266 | 267 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 268 | { 269 | bitstatus = SET; 270 | } 271 | else 272 | { 273 | bitstatus = RESET; 274 | } 275 | /* Return the flag status */ 276 | return bitstatus; 277 | } 278 | 279 | /** 280 | * @brief Clears the PWR's pending flags. 281 | * @param PWR_FLAG: specifies the flag to clear. 282 | * This parameter can be one of the following values: 283 | * @arg PWR_FLAG_WU: Wake Up flag 284 | * @arg PWR_FLAG_SB: StandBy flag 285 | * @retval None 286 | */ 287 | void PWR_ClearFlag(uint32_t PWR_FLAG) 288 | { 289 | /* Check the parameters */ 290 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 291 | 292 | PWR->CR |= PWR_FLAG << 2; 293 | } 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /** 304 | * @} 305 | */ 306 | 307 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 308 | -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | // STM32F100 and SI4032 RTTY transmitter 2 | // released under GPL v.2 by anonymous developer 3 | // enjoy and have a nice day 4 | // ver 1.5a 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include "stdlib.h" 13 | #include "misc.h" 14 | #include 15 | #include "f_rtty.h" 16 | #include "init.h" 17 | #include "fun.h" 18 | 19 | //**************config************** 20 | char callsign[15]={"NO1LIC-1"}; // put your callsign here 21 | 22 | //************band select****************** 23 | #define fb 1 24 | #define fbsel 1 25 | //fb fbsel 0 1 26 | // 0 208,0000 415,9992 27 | // 1 216,6675 433,3325 28 | // 2 225,3342 450,6658 29 | 30 | //*************frequency******************** 31 | #define freq 434.150 //Mhz middle frequency 32 | //***************************************************** 33 | 34 | //********* power definition************************** 35 | #define Smoc 0 // PWR 0...7 0- MIN ... 7 - MAX 36 | //*************************************************** 37 | 38 | //********** frame delay in msec********** 39 | #define tx_delay 100 // 2500 ~2,5 w polu flaga wpisywany jest tx_delay/1000 modulo 16 czyl;i dla 16000 bedzie 0 póki co. 40 | 41 | //**************end config************** 42 | 43 | //************ do not touch bellow this line;) ********************* 44 | #define gen_div 3 //Stała nie zmieniac 45 | #define gen ((26.0/gen_div) *(fbsel+1)) //26 ->26MHZ kwarc napedzajacy nadajnik 46 | #define fc (((freq/gen) - fb - 24) * 64000) 47 | 48 | ///////////////////////////// test mode ///////////// 49 | unsigned char test =0; // 0 - normal, 1 - short frame only cunter, height, flag 50 | 51 | #define WR 0x8000 52 | #define gps_RMC_dlugosc 5 53 | #define gps_RMC_dlugosc_len 10 54 | #define gps_RMC_dlugosc_kier 6 55 | #define gps_RMC_dlugosc_kier_len 1 56 | #define gps_RMC_szerokosc 3 57 | #define gps_RMC_szerokosc_len 9 58 | #define gps_RMC_szerokosc_kier 4 59 | #define gps_RMC_szerokosc_kier_len 1 60 | #define gps_RMC_status 2 61 | #define gps_RMC_status_len 1 62 | #define gps_RMC_data 9 63 | #define gps_RMC_data_len 6 64 | #define gps_RMC_czas 1 65 | #define gps_RMC_czas_len 6 66 | #define gps_RMC_predkosc 7 67 | #define gps_RMC_predkosc_len 5 68 | #define gps_RMC_kierunek 8 69 | #define gps_RMC_kierunek_len 5 70 | #define gps_GGA_wysokosc 9 71 | #define gps_GGA_wysokosc_len 5 //* 72 | #define gps_GGA_use_sat 7 73 | #define gps_GGA_use_sat_len 2 //* 74 | #define gps_VTG_predkosc 7 75 | #define gps_VTG_predkosc_len 5 76 | #define GREEN GPIO_Pin_7 77 | #define RED GPIO_Pin_8 78 | #define GPS_START '$' 79 | #define GPS_STOP 0x0a // LF 80 | #define OFF GPIO_Pin_12 81 | unsigned int send_cun; //frame counter 82 | char czas[7]={"000000"}; 83 | char status[2]={'N'}; 84 | char dlugosc[14]={"0.00000"}; 85 | char dlugosc_kier = 0;//'W'; 86 | char szerokosc[13]={"0.00000"}; 87 | char szerokosc_kier = 0;// 'S';s 88 | char wysokosc[6]={"0"}; 89 | char predkosc[6]={"0"}; 90 | char kierunek[6]={"0"}; 91 | char temperatura; 92 | char FixOk =0; 93 | int napiecie; 94 | unsigned int czest; 95 | float fdlugosc=0; 96 | float fszerokosc=0; 97 | float deg = 0; 98 | float fbuf=0; 99 | char use_sat[3]={'0'}; 100 | char flaga= ((((tx_delay/1000) & 0x0f)<< 3) | Smoc); 101 | int32_t CRC_rtty=0x12ab; //checksum 102 | char buf[512]; 103 | char buf_rtty[200]; 104 | char menu[] = "$$$$$$STM32 RTTY tracker by Blasiu, enjoy and see you on the HUB... \n\r"; 105 | char init_trx[] = "\n\rPowering up TX\n\r"; 106 | char powitanie[]= "greetings from earth"; 107 | unsigned char pun = 0; 108 | unsigned int cun =10; 109 | char temp; 110 | unsigned char dev = 0; 111 | unsigned char tx_on =0; 112 | unsigned int tx_on_delay; 113 | unsigned char tx_enable=0; 114 | char send_rtty_status=0; 115 | unsigned char cun_rtty =0; 116 | char *rtty_buf; 117 | unsigned char GPS_temp; 118 | char GPS_buf[200]; 119 | char *wsk_GPS_buf; 120 | char GPS_rec = 0; 121 | char new_GPS_msg = 0; 122 | unsigned char crc_GPS = 0; 123 | char crc_GPS_start =0 ; 124 | char crc_GPS_rec = 0; 125 | char crc_GPS_cun=0; 126 | char confGPSNAV[]= {0xB5, 0x62, 0x06, 0x24, 0x24, 0x00, 0xFF, 0xFF, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x05, 0x00, 0xFA, 0x00, 0xFA, 0x00, 0x64, 0x00, 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 127 | char GPSon[] = {0xB5, 0x62, 0x02, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x4C, 0x37}; 128 | char GPSoff[] = {0xB5, 0x62, 0x02, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00};//, 0x4D, 0x3B}; 129 | char GPS_ZDA_OFF[]={0xb5, 0x62, 0x06,0x01, 0x08, 0x00, 0xf0, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 130 | char GPS_GLL_OFF[]={0xb5, 0x62, 0x06,0x01, 0x08, 0x00, 0xf0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 131 | char GPS_GSA_OFF[]={0xb5, 0x62, 0x06,0x01, 0x08, 0x00, 0xf0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 132 | char GPS_GSV_OFF[]={0xb5, 0x62, 0x06,0x01, 0x08, 0x00, 0xf0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 133 | int Button=0; 134 | unsigned char cun_off = 0; 135 | unsigned char bOFF=0; 136 | unsigned char bCheckKay=0; 137 | unsigned char GPSConf=0; 138 | 139 | void USART1_IRQHandler(void) 140 | { 141 | if ((USART1->SR & USART_FLAG_RXNE) != (u16)RESET) 142 | { 143 | 144 | GPS_temp = USART_ReceiveData(USART1); 145 | USART_SendData(USART3, GPS_temp); 146 | if (GPS_temp == '*') 147 | { 148 | crc_GPS_start = 0; 149 | crc_GPS_cun = 0; 150 | crc_GPS_rec = 0; 151 | } 152 | if (crc_GPS_start) 153 | { 154 | crc_GPS ^= GPS_temp; 155 | } 156 | else 157 | { 158 | if (GPS_rec) 159 | { 160 | if (crc_GPS_cun < 3 && crc_GPS_cun > 0 ) 161 | { 162 | crc_GPS_rec *= 16; 163 | crc_GPS_rec += HexCharToInt(GPS_temp); 164 | } 165 | crc_GPS_cun++; 166 | } 167 | 168 | } 169 | if(GPS_temp == GPS_START) 170 | { 171 | wsk_GPS_buf = GPS_buf; 172 | GPS_rec = 1; 173 | crc_GPS=0; 174 | crc_GPS_start =1; 175 | } 176 | if (GPS_rec) 177 | { 178 | *(wsk_GPS_buf++) = GPS_temp; 179 | } 180 | 181 | if(GPS_temp == GPS_STOP) 182 | { 183 | GPS_rec = 0; 184 | *(wsk_GPS_buf) = 0x00; 185 | 186 | if(crc_GPS_rec == crc_GPS) 187 | { 188 | new_GPS_msg =1; 189 | GPS_rec = 0; 190 | } 191 | } 192 | } 193 | } 194 | 195 | void TIM2_IRQHandler(void){ 196 | if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET) 197 | { 198 | TIM_ClearITPendingBit(TIM2, TIM_IT_Update); 199 | } 200 | if (tx_on && ++cun_rtty ==17) 201 | { 202 | cun_rtty = 0; 203 | send_rtty_status = send_rtty(rtty_buf); 204 | if (send_rtty_status ==2) 205 | { 206 | GPIO_SetBits(GPIOB, RED); 207 | if (*(++rtty_buf) == 0) 208 | { 209 | tx_on=0; 210 | tx_on_delay =tx_delay ;//2500; 211 | tx_enable=0; 212 | temp = spi_sendrecv(0x0740 | WR); 213 | } 214 | } 215 | if (send_rtty_status ==1) 216 | { 217 | temp = spi_sendrecv(0x7302 | WR); 218 | GPIO_SetBits(GPIOB, RED); 219 | } 220 | if (send_rtty_status ==0) 221 | { 222 | temp = spi_sendrecv(0x7300 | WR); 223 | GPIO_ResetBits(GPIOB, RED); 224 | } 225 | } 226 | if(!tx_on && --tx_on_delay == 0) 227 | { 228 | tx_enable=1; 229 | tx_on_delay--; 230 | } 231 | if(--cun == 0 ) 232 | { 233 | cun_off++; 234 | if (pun) 235 | { 236 | GPIO_ResetBits(GPIOB, GREEN); 237 | pun =0; 238 | } 239 | else 240 | { 241 | if (flaga & 0x80) 242 | { 243 | GPIO_SetBits(GPIOB, GREEN); 244 | } 245 | pun = 1; 246 | } 247 | cun = 200; 248 | } 249 | bCheckKay =1; 250 | } 251 | 252 | int main(void) 253 | { 254 | #ifdef DEBUG 255 | debug(); 256 | #endif 257 | RCC_Conf(); 258 | NVIC_Conf(); 259 | init_port(); 260 | 261 | wsk_GPS_buf = GPS_buf; 262 | 263 | 264 | GPIO_SetBits(GPIOB, RED); 265 | USART_SendData(USART3, 0xc); 266 | print(menu); 267 | temp = spi_sendrecv(0x02ff); 268 | //send_hex(temp); 269 | 270 | temp = spi_sendrecv(0x03ff); 271 | temp = spi_sendrecv(0x04ff); 272 | temp = spi_sendrecv(0x0780 | WR); 273 | print(init_trx); 274 | // programowanie czestotliwosci nadawania 275 | napiecie = fc; 276 | temp = spi_sendrecv(0x7561 | WR); 277 | temp = spi_sendrecv(0x7600 | (((uint16_t)fc>>8) & 0x00ff) | WR); 278 | temp = spi_sendrecv(0x7700 | ( (uint16_t)fc & 0x00ff) | WR); 279 | 280 | // Programowanie mocy nadajnika 281 | temp = spi_sendrecv(0x6D00 | (Smoc & 0x0007) | WR); 282 | temp = spi_sendrecv(0x7100 | WR); 283 | temp = spi_sendrecv(0x8708); 284 | temp = spi_sendrecv(0x02ff); 285 | temp = spi_sendrecv(0x75ff); 286 | temp = spi_sendrecv(0x76ff); 287 | temp = spi_sendrecv(0x77ff); 288 | temp = spi_sendrecv(0x1220 | WR); 289 | temp = spi_sendrecv(0x1300 | WR); 290 | temp = spi_sendrecv(0x1200 | WR); 291 | temp = spi_sendrecv(0x0f80 | WR); 292 | rtty_buf = buf_rtty; 293 | tx_on = 0; 294 | tx_enable =1; 295 | //tx_enable =0; 296 | Button = ADCVal[1]; 297 | 298 | while(1) 299 | { 300 | if (status[0] == 'A') 301 | { 302 | flaga |= 0x80; 303 | } 304 | else 305 | { 306 | flaga &= ~0x80; 307 | } 308 | 309 | 310 | 311 | if (tx_on == 0 && tx_enable) 312 | { 313 | temperatura = spi_sendrecv(0x11ff); //odczyt ADC 314 | temp = spi_sendrecv(0x0f80 |WR); 315 | temperatura = -64 +( temperatura *5 /10) -16; 316 | napiecie = srednia(ADCVal[0]*600/4096); 317 | 318 | fdlugosc = atof(dlugosc); 319 | deg = (int)(fdlugosc/100); 320 | fbuf = fdlugosc -(deg * 100); 321 | fdlugosc = deg + fbuf/60; 322 | if (dlugosc_kier == 'W') 323 | { 324 | fdlugosc *= -1; 325 | } 326 | fszerokosc = atof(szerokosc); 327 | deg = (int)(fszerokosc/100); 328 | fbuf = fszerokosc -(deg * 100); 329 | fszerokosc = deg + fbuf/60; 330 | if (szerokosc_kier == 'S') 331 | { 332 | fszerokosc *= -1; 333 | } 334 | if (test) 335 | { 336 | sprintf(buf_rtty,"$$$$$$$%d,%d,%02x",send_cun,atoi(wysokosc),flaga); 337 | } 338 | else 339 | { 340 | sprintf(buf_rtty,"$$$$$$$%s,%d,%s,%.5f,%.5f,%d,%d,%s,%d,%d,%d,%02x",callsign,send_cun,czas,fszerokosc,fdlugosc,atoi(wysokosc),atoi(predkosc),kierunek,temperatura,napiecie,atoi(use_sat),flaga); 341 | } 342 | CRC_rtty=0xffff; //napiecie flaga 343 | CRC_rtty=gps_CRC16_checksum(buf_rtty+7); 344 | sprintf(buf_rtty,"%s*%04X\n",buf_rtty,CRC_rtty & 0xffff); 345 | rtty_buf = buf_rtty; 346 | tx_on = 1; 347 | temp = spi_sendrecv(0x0748 | WR); 348 | send_cun++; 349 | } 350 | 351 | if (new_GPS_msg) 352 | { 353 | //print(GPS_buf); 354 | new_GPS_msg = 0; 355 | if (strncmp(GPS_buf,"$GPRMC",6) == 0) 356 | { 357 | if (czytaj_GPS(gps_RMC_czas,gps_RMC_czas_len,GPS_buf,czas) == 0) 358 | { 359 | strcpy(czas,"000000"); 360 | } 361 | 362 | if (czytaj_GPS(gps_RMC_kierunek,gps_RMC_kierunek_len,GPS_buf,kierunek) == 0) 363 | { 364 | strcpy(kierunek,"0"); 365 | } 366 | if (czytaj_GPS(gps_RMC_szerokosc,gps_RMC_szerokosc_len,GPS_buf,szerokosc) == 0) 367 | { 368 | strcpy(szerokosc,"0.00000"); 369 | } 370 | 371 | if (czytaj_GPS(gps_RMC_szerokosc_kier,gps_RMC_szerokosc_kier_len,GPS_buf,&szerokosc_kier) == 0) 372 | { 373 | szerokosc_kier=0; 374 | } 375 | 376 | if (czytaj_GPS(gps_RMC_dlugosc,gps_RMC_dlugosc_len,GPS_buf,dlugosc) == 0) 377 | { 378 | strcpy(dlugosc,"0.00000"); 379 | } 380 | 381 | if (czytaj_GPS(gps_RMC_dlugosc_kier,gps_RMC_dlugosc_kier_len,GPS_buf,&dlugosc_kier) == 0) 382 | { 383 | dlugosc_kier=0; 384 | } 385 | 386 | 387 | if (czytaj_GPS(gps_RMC_status,gps_RMC_status_len,GPS_buf,status) == 0) 388 | { 389 | strcpy(status,"-"); 390 | } 391 | 392 | 393 | } 394 | if (strncmp(GPS_buf,"$GPGGA",6) == 0) 395 | { 396 | if (czytaj_GPS(gps_GGA_wysokosc,gps_GGA_wysokosc_len,GPS_buf,wysokosc) == 0) 397 | { 398 | strcpy(wysokosc,"0"); 399 | } 400 | if (czytaj_GPS(gps_GGA_use_sat,gps_GGA_use_sat_len,GPS_buf,use_sat) == 0) 401 | { 402 | strcpy(use_sat,"0"); 403 | } 404 | 405 | } 406 | 407 | if (strncmp(GPS_buf,"$GPVTG",6) == 0) 408 | { 409 | if (czytaj_GPS(gps_VTG_predkosc,gps_VTG_predkosc_len,GPS_buf,predkosc) == 0) 410 | { 411 | strcpy(predkosc,"0"); 412 | } 413 | } 414 | if(strncmp(GPS_buf,"$GPZDA",6 )== 0 ) 415 | { 416 | switch (GPSConf) 417 | { 418 | case 0: 419 | sendtogps(confGPSNAV, sizeof(confGPSNAV)/sizeof(uint8_t)); 420 | break; 421 | case 1: 422 | sendtogps(GPS_GSV_OFF,sizeof(GPS_GSV_OFF)/sizeof(uint8_t)); 423 | break; 424 | case 2: 425 | sendtogps(GPS_GSA_OFF,sizeof(GPS_GSA_OFF)/sizeof(uint8_t)); 426 | break; 427 | case 3: 428 | sendtogps(GPS_GLL_OFF,sizeof(GPS_GLL_OFF)/sizeof(uint8_t)); 429 | break; 430 | case 4: 431 | sendtogps(GPS_ZDA_OFF,sizeof(GPS_ZDA_OFF)/sizeof(uint8_t)); 432 | break; 433 | } 434 | GPSConf++; 435 | } 436 | } 437 | 438 | } 439 | } 440 | 441 | #ifdef DEBUG 442 | void assert_failed(uint8_t* file, uint32_t line) 443 | { 444 | while (1); 445 | } 446 | #endif 447 | -------------------------------------------------------------------------------- /cmsis_boot/startup/startup_stm32f10x_md_vl.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_md_vl.c 4 | * @author Coocox 5 | * @version V1.0 6 | * @date 3/4/2011 7 | * @brief STM32F10x Medium Density Value Line Devices Startup code. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the vector table entries with the exceptions ISR address 11 | * - Initialize data and bss 12 | * - Setup the microcontroller system. 13 | * - Call the application's entry point. 14 | * After Reset the Cortex-M3 processor is in Thread mode, 15 | * priority is Privileged, and the Stack is set to Main. 16 | ******************************************************************************* 17 | */ 18 | 19 | 20 | /*----------Stack Configuration-----------------------------------------------*/ 21 | #define STACK_SIZE 0x00000100 /*!< The Stack size suggest using even number */ 22 | __attribute__ ((section(".co_stack"))) 23 | unsigned long pulStack[STACK_SIZE]; 24 | 25 | 26 | /*----------Macro definition--------------------------------------------------*/ 27 | #define WEAK __attribute__ ((weak)) 28 | 29 | 30 | /*----------Declaration of the default fault handlers-------------------------*/ 31 | /* System exception vector handler */ 32 | __attribute__ ((used)) 33 | void WEAK Reset_Handler(void); 34 | void WEAK NMI_Handler(void); 35 | void WEAK HardFault_Handler(void); 36 | void WEAK MemManage_Handler(void); 37 | void WEAK BusFault_Handler(void); 38 | void WEAK UsageFault_Handler(void); 39 | void WEAK SVC_Handler(void); 40 | void WEAK DebugMon_Handler(void); 41 | void WEAK PendSV_Handler(void); 42 | void WEAK SysTick_Handler(void); 43 | void WEAK WWDG_IRQHandler(void); 44 | void WEAK PVD_IRQHandler(void); 45 | void WEAK TAMPER_IRQHandler(void); 46 | void WEAK RTC_IRQHandler(void); 47 | void WEAK FLASH_IRQHandler(void); 48 | void WEAK RCC_IRQHandler(void); 49 | void WEAK EXTI0_IRQHandler(void); 50 | void WEAK EXTI1_IRQHandler(void); 51 | void WEAK EXTI2_IRQHandler(void); 52 | void WEAK EXTI3_IRQHandler(void); 53 | void WEAK EXTI4_IRQHandler(void); 54 | void WEAK DMA1_Channel1_IRQHandler(void); 55 | void WEAK DMA1_Channel2_IRQHandler(void); 56 | void WEAK DMA1_Channel3_IRQHandler(void); 57 | void WEAK DMA1_Channel4_IRQHandler(void); 58 | void WEAK DMA1_Channel5_IRQHandler(void); 59 | void WEAK DMA1_Channel6_IRQHandler(void); 60 | void WEAK DMA1_Channel7_IRQHandler(void); 61 | void WEAK ADC1_IRQHandler(void); 62 | void WEAK EXTI9_5_IRQHandler(void); 63 | void WEAK TIM1_BRK_TIM15_IRQHandler(void); 64 | void WEAK TIM1_UP_TIM16_IRQHandler(void); 65 | void WEAK TIM1_TRG_COM_TIM17_IRQHandler(void); 66 | void WEAK TIM1_CC_IRQHandler(void); 67 | void WEAK TIM2_IRQHandler(void); 68 | void WEAK TIM3_IRQHandler(void); 69 | void WEAK TIM4_IRQHandler(void); 70 | void WEAK I2C1_EV_IRQHandler(void); 71 | void WEAK I2C1_ER_IRQHandler(void); 72 | void WEAK I2C2_EV_IRQHandler(void); 73 | void WEAK I2C2_ER_IRQHandler(void); 74 | void WEAK SPI1_IRQHandler(void); 75 | void WEAK SPI2_IRQHandler(void); 76 | void WEAK USART1_IRQHandler(void); 77 | void WEAK USART2_IRQHandler(void); 78 | void WEAK USART3_IRQHandler(void); 79 | void WEAK EXTI15_10_IRQHandler(void); 80 | void WEAK RTCAlarm_IRQHandler(void); 81 | void WEAK CEC_IRQHandler(void); 82 | void WEAK TIM6_DAC_IRQHandler(void); 83 | void WEAK TIM7_IRQHandler(void); 84 | 85 | /*----------Symbols defined in linker script----------------------------------*/ 86 | extern unsigned long _sidata; /*!< Start address for the initialization 87 | values of the .data section. */ 88 | extern unsigned long _sdata; /*!< Start address for the .data section */ 89 | extern unsigned long _edata; /*!< End address for the .data section */ 90 | extern unsigned long _sbss; /*!< Start address for the .bss section */ 91 | extern unsigned long _ebss; /*!< End address for the .bss section */ 92 | extern void _eram; /*!< End address for ram */ 93 | 94 | 95 | /*----------Function prototypes-----------------------------------------------*/ 96 | extern int main(void); /*!< The entry point for the application. */ 97 | extern void SystemInit(void); /*!< Setup the microcontroller system(CMSIS) */ 98 | void Default_Reset_Handler(void); /*!< Default reset handler */ 99 | static void Default_Handler(void); /*!< Default exception handler */ 100 | 101 | 102 | /** 103 | *@brief The minimal vector table for a Cortex M3. Note that the proper constructs 104 | * must be placed on this to ensure that it ends up at physical address 105 | * 0x00000000. 106 | */ 107 | __attribute__ ((used,section(".isr_vector"))) 108 | void (* const g_pfnVectors[])(void) = 109 | { 110 | /*----------Core Exceptions-------------------------------------------------*/ 111 | (void *)&pulStack[STACK_SIZE], /*!< The initial stack pointer */ 112 | Reset_Handler, /*!< Reset Handler */ 113 | NMI_Handler, /*!< NMI Handler */ 114 | HardFault_Handler, /*!< Hard Fault Handler */ 115 | MemManage_Handler, /*!< MPU Fault Handler */ 116 | BusFault_Handler, /*!< Bus Fault Handler */ 117 | UsageFault_Handler, /*!< Usage Fault Handler */ 118 | 0,0,0,0, /*!< Reserved */ 119 | SVC_Handler, /*!< SVCall Handler */ 120 | DebugMon_Handler, /*!< Debug Monitor Handler */ 121 | 0, /*!< Reserved */ 122 | PendSV_Handler, /*!< PendSV Handler */ 123 | SysTick_Handler, /*!< SysTick Handler */ 124 | 125 | /*----------External Exceptions---------------------------------------------*/ 126 | WWDG_IRQHandler, /*!< 0: Window Watchdog */ 127 | PVD_IRQHandler, /*!< 1: PVD through EXTI Line detect */ 128 | TAMPER_IRQHandler, /*!< 2: Tamper */ 129 | RTC_IRQHandler, /*!< 3: RTC */ 130 | FLASH_IRQHandler, /*!< 4: Flash */ 131 | RCC_IRQHandler, /*!< 5: RCC */ 132 | EXTI0_IRQHandler, /*!< 6: EXTI Line 0 */ 133 | EXTI1_IRQHandler, /*!< 7: EXTI Line 1 */ 134 | EXTI2_IRQHandler, /*!< 8: EXTI Line 2 */ 135 | EXTI3_IRQHandler, /*!< 9: EXTI Line 3 */ 136 | EXTI4_IRQHandler, /*!< 10: EXTI Line 4 */ 137 | DMA1_Channel1_IRQHandler, /*!< 11: DMA1 Channel 1 */ 138 | DMA1_Channel2_IRQHandler, /*!< 12: DMA1 Channel 2 */ 139 | DMA1_Channel3_IRQHandler, /*!< 13: DMA1 Channel 3 */ 140 | DMA1_Channel4_IRQHandler, /*!< 14: DMA1 Channel 4 */ 141 | DMA1_Channel5_IRQHandler, /*!< 15: DMA1 Channel 5 */ 142 | DMA1_Channel6_IRQHandler, /*!< 16: DMA1 Channel 6 */ 143 | DMA1_Channel7_IRQHandler, /*!< 17: DMA1 Channel 7 */ 144 | ADC1_IRQHandler, /*!< 18: ADC1 */ 145 | 0, /*!< 19: USB High Priority or CAN1 TX */ 146 | 0, /*!< 20: USB Low Priority or CAN1 RX0 */ 147 | 0, /*!< 21: CAN1 RX1 */ 148 | 0, /*!< 22: CAN1 SCE */ 149 | EXTI9_5_IRQHandler, /*!< 23: EXTI Line 9..5 */ 150 | TIM1_BRK_TIM15_IRQHandler, /*!< 24: TIM1 Break and TIM15 */ 151 | TIM1_UP_TIM16_IRQHandler, /*!< 25: TIM1 Update and TIM16 */ 152 | TIM1_TRG_COM_TIM17_IRQHandler,/*!< 26: TIM1 Trigger and Commutation and TIM17 */ 153 | TIM1_CC_IRQHandler, /*!< 27: TIM1 Capture Compare */ 154 | TIM2_IRQHandler, /*!< 28: TIM2 */ 155 | TIM3_IRQHandler, /*!< 29: TIM3 */ 156 | TIM4_IRQHandler, /*!< 30: TIM4 */ 157 | I2C1_EV_IRQHandler, /*!< 31: I2C1 Event */ 158 | I2C1_ER_IRQHandler, /*!< 32: I2C1 Error */ 159 | I2C2_EV_IRQHandler, /*!< 33: I2C2 Event */ 160 | I2C2_ER_IRQHandler, /*!< 34: I2C2 Error */ 161 | SPI1_IRQHandler, /*!< 35: SPI1 */ 162 | SPI2_IRQHandler, /*!< 36: SPI2 */ 163 | USART1_IRQHandler, /*!< 37: USART1 */ 164 | USART2_IRQHandler, /*!< 38: USART2 */ 165 | USART3_IRQHandler, /*!< 39: USART3 */ 166 | EXTI15_10_IRQHandler, /*!< 40: EXTI Line 15..10 */ 167 | RTCAlarm_IRQHandler, /*!< 41: RTC Alarm through EXTI Line */ 168 | CEC_IRQHandler, /*!< 42: HDMI-CEC */ 169 | 0,0,0,0,0,0, /*!< Reserved */ 170 | 0,0,0,0,0, /*!< Reserved */ 171 | TIM6_DAC_IRQHandler, /*!< 54: TIM6 and DAC underrun */ 172 | TIM7_IRQHandler, /*!< 55: TIM7 */ 173 | (void *)0xF108F85F /*!< Boot in RAM mode */ 174 | }; 175 | 176 | 177 | /** 178 | * @brief This is the code that gets called when the processor first 179 | * starts execution following a reset event. Only the absolutely 180 | * necessary set is performed, after which the application 181 | * supplied main() routine is called. 182 | * @param None 183 | * @retval None 184 | */ 185 | void Default_Reset_Handler(void) 186 | { 187 | /* Initialize data and bss */ 188 | unsigned long *pulSrc, *pulDest; 189 | 190 | /* Copy the data segment initializers from flash to SRAM */ 191 | pulSrc = &_sidata; 192 | 193 | for(pulDest = &_sdata; pulDest < &_edata; ) 194 | { 195 | *(pulDest++) = *(pulSrc++); 196 | } 197 | 198 | /* Zero fill the bss segment. This is done with inline assembly since this 199 | will clear the value of pulDest if it is not kept in a register. */ 200 | __asm(" ldr r0, =_sbss\n" 201 | " ldr r1, =_ebss\n" 202 | " mov r2, #0\n" 203 | " .thumb_func\n" 204 | " zero_loop:\n" 205 | " cmp r0, r1\n" 206 | " it lt\n" 207 | " strlt r2, [r0], #4\n" 208 | " blt zero_loop"); 209 | 210 | /* Setup the microcontroller system. */ 211 | //SystemInit(); 212 | 213 | /* Call the application's entry point.*/ 214 | main(); 215 | } 216 | 217 | /** 218 | *@brief Provide weak aliases for each Exception handler to the Default_Handler. 219 | * As they are weak aliases, any function with the same name will override 220 | * this definition. 221 | */ 222 | #pragma weak Reset_Handler = Default_Reset_Handler 223 | #pragma weak NMI_Handler = Default_Handler 224 | #pragma weak HardFault_Handler = Default_Handler 225 | #pragma weak MemManage_Handler = Default_Handler 226 | #pragma weak BusFault_Handler = Default_Handler 227 | #pragma weak UsageFault_Handler = Default_Handler 228 | #pragma weak SVC_Handler = Default_Handler 229 | #pragma weak DebugMon_Handler = Default_Handler 230 | #pragma weak PendSV_Handler = Default_Handler 231 | #pragma weak SysTick_Handler = Default_Handler 232 | #pragma weak WWDG_IRQHandler = Default_Handler 233 | #pragma weak PVD_IRQHandler = Default_Handler 234 | #pragma weak TAMPER_IRQHandler = Default_Handler 235 | #pragma weak RTC_IRQHandler = Default_Handler 236 | #pragma weak FLASH_IRQHandler = Default_Handler 237 | #pragma weak RCC_IRQHandler = Default_Handler 238 | #pragma weak EXTI0_IRQHandler = Default_Handler 239 | #pragma weak EXTI1_IRQHandler = Default_Handler 240 | #pragma weak EXTI2_IRQHandler = Default_Handler 241 | #pragma weak EXTI3_IRQHandler = Default_Handler 242 | #pragma weak EXTI4_IRQHandler = Default_Handler 243 | #pragma weak DMA1_Channel1_IRQHandler = Default_Handler 244 | #pragma weak DMA1_Channel2_IRQHandler = Default_Handler 245 | #pragma weak DMA1_Channel3_IRQHandler = Default_Handler 246 | #pragma weak DMA1_Channel4_IRQHandler = Default_Handler 247 | #pragma weak DMA1_Channel5_IRQHandler = Default_Handler 248 | #pragma weak DMA1_Channel6_IRQHandler = Default_Handler 249 | #pragma weak DMA1_Channel7_IRQHandler = Default_Handler 250 | #pragma weak ADC1_IRQHandler = Default_Handler 251 | #pragma weak EXTI9_5_IRQHandler = Default_Handler 252 | #pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler 253 | #pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler 254 | #pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler 255 | #pragma weak TIM1_CC_IRQHandler = Default_Handler 256 | #pragma weak TIM2_IRQHandler = Default_Handler 257 | #pragma weak TIM3_IRQHandler = Default_Handler 258 | #pragma weak TIM4_IRQHandler = Default_Handler 259 | #pragma weak I2C1_EV_IRQHandler = Default_Handler 260 | #pragma weak I2C1_ER_IRQHandler = Default_Handler 261 | #pragma weak I2C2_EV_IRQHandler = Default_Handler 262 | #pragma weak I2C2_ER_IRQHandler = Default_Handler 263 | #pragma weak SPI1_IRQHandler = Default_Handler 264 | #pragma weak SPI2_IRQHandler = Default_Handler 265 | #pragma weak USART1_IRQHandler = Default_Handler 266 | #pragma weak USART2_IRQHandler = Default_Handler 267 | #pragma weak USART3_IRQHandler = Default_Handler 268 | #pragma weak EXTI15_10_IRQHandler = Default_Handler 269 | #pragma weak RTCAlarm_IRQHandler = Default_Handler 270 | #pragma weak CEC_IRQHandler = Default_Handler 271 | #pragma weak TIM6_DAC_IRQHandler = Default_Handler 272 | #pragma weak TIM7_IRQHandler = Default_Handler 273 | 274 | /** 275 | * @brief This is the code that gets called when the processor receives an 276 | * unexpected interrupt. This simply enters an infinite loop, 277 | * preserving the system state for examination by a debugger. 278 | * @param None 279 | * @retval None 280 | */ 281 | static void Default_Handler(void) 282 | { 283 | /* Go into an infinite loop. */ 284 | while (1) 285 | { 286 | } 287 | } 288 | 289 | /*********************** (C) COPYRIGHT 2011 Coocox ************END OF FILE*****/ 290 | -------------------------------------------------------------------------------- /rtty/rtty.elf.xcodeproj/project.pbxproj: -------------------------------------------------------------------------------- 1 | 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-------------------------------------------------------------------------------- /stm_lib/inc/stm32f10x_usart.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_usart.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the USART 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_USART_H 25 | #define __STM32F10x_USART_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup USART 39 | * @{ 40 | */ 41 | 42 | /** @defgroup USART_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief USART Init Structure definition 48 | */ 49 | 50 | typedef struct 51 | { 52 | uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. 53 | The baud rate is computed using the following formula: 54 | - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) 55 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ 56 | 57 | uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. 58 | This parameter can be a value of @ref USART_Word_Length */ 59 | 60 | uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. 61 | This parameter can be a value of @ref USART_Stop_Bits */ 62 | 63 | uint16_t USART_Parity; /*!< Specifies the parity mode. 64 | This parameter can be a value of @ref USART_Parity 65 | @note When parity is enabled, the computed parity is inserted 66 | at the MSB position of the transmitted data (9th bit when 67 | the word length is set to 9 data bits; 8th bit when the 68 | word length is set to 8 data bits). */ 69 | 70 | uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. 71 | This parameter can be a value of @ref USART_Mode */ 72 | 73 | uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled 74 | or disabled. 75 | This parameter can be a value of @ref USART_Hardware_Flow_Control */ 76 | } USART_InitTypeDef; 77 | 78 | /** 79 | * @brief USART Clock Init Structure definition 80 | */ 81 | 82 | typedef struct 83 | { 84 | 85 | uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. 86 | This parameter can be a value of @ref USART_Clock */ 87 | 88 | uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. 89 | This parameter can be a value of @ref USART_Clock_Polarity */ 90 | 91 | uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. 92 | This parameter can be a value of @ref USART_Clock_Phase */ 93 | 94 | uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted 95 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. 96 | This parameter can be a value of @ref USART_Last_Bit */ 97 | } USART_ClockInitTypeDef; 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup USART_Exported_Constants 104 | * @{ 105 | */ 106 | 107 | #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ 108 | ((PERIPH) == USART2) || \ 109 | ((PERIPH) == USART3) || \ 110 | ((PERIPH) == UART4) || \ 111 | ((PERIPH) == UART5)) 112 | 113 | #define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ 114 | ((PERIPH) == USART2) || \ 115 | ((PERIPH) == USART3)) 116 | 117 | #define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ 118 | ((PERIPH) == USART2) || \ 119 | ((PERIPH) == USART3) || \ 120 | ((PERIPH) == UART4)) 121 | /** @defgroup USART_Word_Length 122 | * @{ 123 | */ 124 | 125 | #define USART_WordLength_8b ((uint16_t)0x0000) 126 | #define USART_WordLength_9b ((uint16_t)0x1000) 127 | 128 | #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ 129 | ((LENGTH) == USART_WordLength_9b)) 130 | /** 131 | * @} 132 | */ 133 | 134 | /** @defgroup USART_Stop_Bits 135 | * @{ 136 | */ 137 | 138 | #define USART_StopBits_1 ((uint16_t)0x0000) 139 | #define USART_StopBits_0_5 ((uint16_t)0x1000) 140 | #define USART_StopBits_2 ((uint16_t)0x2000) 141 | #define USART_StopBits_1_5 ((uint16_t)0x3000) 142 | #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ 143 | ((STOPBITS) == USART_StopBits_0_5) || \ 144 | ((STOPBITS) == USART_StopBits_2) || \ 145 | ((STOPBITS) == USART_StopBits_1_5)) 146 | /** 147 | * @} 148 | */ 149 | 150 | /** @defgroup USART_Parity 151 | * @{ 152 | */ 153 | 154 | #define USART_Parity_No ((uint16_t)0x0000) 155 | #define USART_Parity_Even ((uint16_t)0x0400) 156 | #define USART_Parity_Odd ((uint16_t)0x0600) 157 | #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ 158 | ((PARITY) == USART_Parity_Even) || \ 159 | ((PARITY) == USART_Parity_Odd)) 160 | /** 161 | * @} 162 | */ 163 | 164 | /** @defgroup USART_Mode 165 | * @{ 166 | */ 167 | 168 | #define USART_Mode_Rx ((uint16_t)0x0004) 169 | #define USART_Mode_Tx ((uint16_t)0x0008) 170 | #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) 171 | /** 172 | * @} 173 | */ 174 | 175 | /** @defgroup USART_Hardware_Flow_Control 176 | * @{ 177 | */ 178 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000) 179 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) 180 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) 181 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) 182 | #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ 183 | (((CONTROL) == USART_HardwareFlowControl_None) || \ 184 | ((CONTROL) == USART_HardwareFlowControl_RTS) || \ 185 | ((CONTROL) == USART_HardwareFlowControl_CTS) || \ 186 | ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) 187 | /** 188 | * @} 189 | */ 190 | 191 | /** @defgroup USART_Clock 192 | * @{ 193 | */ 194 | #define USART_Clock_Disable ((uint16_t)0x0000) 195 | #define USART_Clock_Enable ((uint16_t)0x0800) 196 | #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ 197 | ((CLOCK) == USART_Clock_Enable)) 198 | /** 199 | * @} 200 | */ 201 | 202 | /** @defgroup USART_Clock_Polarity 203 | * @{ 204 | */ 205 | 206 | #define USART_CPOL_Low ((uint16_t)0x0000) 207 | #define USART_CPOL_High ((uint16_t)0x0400) 208 | #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) 209 | 210 | /** 211 | * @} 212 | */ 213 | 214 | /** @defgroup USART_Clock_Phase 215 | * @{ 216 | */ 217 | 218 | #define USART_CPHA_1Edge ((uint16_t)0x0000) 219 | #define USART_CPHA_2Edge ((uint16_t)0x0200) 220 | #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) 221 | 222 | /** 223 | * @} 224 | */ 225 | 226 | /** @defgroup USART_Last_Bit 227 | * @{ 228 | */ 229 | 230 | #define USART_LastBit_Disable ((uint16_t)0x0000) 231 | #define USART_LastBit_Enable ((uint16_t)0x0100) 232 | #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ 233 | ((LASTBIT) == USART_LastBit_Enable)) 234 | /** 235 | * @} 236 | */ 237 | 238 | /** @defgroup USART_Interrupt_definition 239 | * @{ 240 | */ 241 | 242 | #define USART_IT_PE ((uint16_t)0x0028) 243 | #define USART_IT_TXE ((uint16_t)0x0727) 244 | #define USART_IT_TC ((uint16_t)0x0626) 245 | #define USART_IT_RXNE ((uint16_t)0x0525) 246 | #define USART_IT_IDLE ((uint16_t)0x0424) 247 | #define USART_IT_LBD ((uint16_t)0x0846) 248 | #define USART_IT_CTS ((uint16_t)0x096A) 249 | #define USART_IT_ERR ((uint16_t)0x0060) 250 | #define USART_IT_ORE ((uint16_t)0x0360) 251 | #define USART_IT_NE ((uint16_t)0x0260) 252 | #define USART_IT_FE ((uint16_t)0x0160) 253 | #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ 254 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 255 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ 256 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) 257 | #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ 258 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 259 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ 260 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ 261 | ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) 262 | #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 263 | ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) 264 | /** 265 | * @} 266 | */ 267 | 268 | /** @defgroup USART_DMA_Requests 269 | * @{ 270 | */ 271 | 272 | #define USART_DMAReq_Tx ((uint16_t)0x0080) 273 | #define USART_DMAReq_Rx ((uint16_t)0x0040) 274 | #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) 275 | 276 | /** 277 | * @} 278 | */ 279 | 280 | /** @defgroup USART_WakeUp_methods 281 | * @{ 282 | */ 283 | 284 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000) 285 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800) 286 | #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ 287 | ((WAKEUP) == USART_WakeUp_AddressMark)) 288 | /** 289 | * @} 290 | */ 291 | 292 | /** @defgroup USART_LIN_Break_Detection_Length 293 | * @{ 294 | */ 295 | 296 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) 297 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) 298 | #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ 299 | (((LENGTH) == USART_LINBreakDetectLength_10b) || \ 300 | ((LENGTH) == USART_LINBreakDetectLength_11b)) 301 | /** 302 | * @} 303 | */ 304 | 305 | /** @defgroup USART_IrDA_Low_Power 306 | * @{ 307 | */ 308 | 309 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004) 310 | #define USART_IrDAMode_Normal ((uint16_t)0x0000) 311 | #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ 312 | ((MODE) == USART_IrDAMode_Normal)) 313 | /** 314 | * @} 315 | */ 316 | 317 | /** @defgroup USART_Flags 318 | * @{ 319 | */ 320 | 321 | #define USART_FLAG_CTS ((uint16_t)0x0200) 322 | #define USART_FLAG_LBD ((uint16_t)0x0100) 323 | #define USART_FLAG_TXE ((uint16_t)0x0080) 324 | #define USART_FLAG_TC ((uint16_t)0x0040) 325 | #define USART_FLAG_RXNE ((uint16_t)0x0020) 326 | #define USART_FLAG_IDLE ((uint16_t)0x0010) 327 | #define USART_FLAG_ORE ((uint16_t)0x0008) 328 | #define USART_FLAG_NE ((uint16_t)0x0004) 329 | #define USART_FLAG_FE ((uint16_t)0x0002) 330 | #define USART_FLAG_PE ((uint16_t)0x0001) 331 | #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ 332 | ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ 333 | ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ 334 | ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ 335 | ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) 336 | 337 | #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) 338 | #define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ 339 | ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ 340 | || ((USART_FLAG) != USART_FLAG_CTS)) 341 | #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) 342 | #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) 343 | #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) 344 | 345 | /** 346 | * @} 347 | */ 348 | 349 | /** 350 | * @} 351 | */ 352 | 353 | /** @defgroup USART_Exported_Macros 354 | * @{ 355 | */ 356 | 357 | /** 358 | * @} 359 | */ 360 | 361 | /** @defgroup USART_Exported_Functions 362 | * @{ 363 | */ 364 | 365 | void USART_DeInit(USART_TypeDef* USARTx); 366 | void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); 367 | void USART_StructInit(USART_InitTypeDef* USART_InitStruct); 368 | void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); 369 | void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); 370 | void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); 371 | void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); 372 | void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); 373 | void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); 374 | void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); 375 | void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); 376 | void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); 377 | void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); 378 | void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); 379 | uint16_t USART_ReceiveData(USART_TypeDef* USARTx); 380 | void USART_SendBreak(USART_TypeDef* USARTx); 381 | void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); 382 | void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); 383 | void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); 384 | void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); 385 | void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); 386 | void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); 387 | void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); 388 | void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); 389 | void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); 390 | FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); 391 | void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); 392 | ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); 393 | void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); 394 | 395 | #ifdef __cplusplus 396 | } 397 | #endif 398 | 399 | #endif /* __STM32F10x_USART_H */ 400 | /** 401 | * @} 402 | */ 403 | 404 | /** 405 | * @} 406 | */ 407 | 408 | /** 409 | * @} 410 | */ 411 | 412 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 413 | -------------------------------------------------------------------------------- /cmsis/core_cmFunc.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cmFunc.h 3 | * @brief CMSIS Cortex-M Core Function Access Header File 4 | * @version V3.01 5 | * @date 06. March 2012 6 | * 7 | * @note 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 9 | * 10 | * @par 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 | * processor based microcontrollers. This file can be freely distributed 13 | * within development tools that are supporting such ARM based processors. 14 | * 15 | * @par 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 | * 22 | ******************************************************************************/ 23 | 24 | #ifndef __CORE_CMFUNC_H 25 | #define __CORE_CMFUNC_H 26 | 27 | 28 | /* ########################### Core Function Access ########################### */ 29 | /** \ingroup CMSIS_Core_FunctionInterface 30 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 31 | @{ 32 | */ 33 | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 35 | /* ARM armcc specific functions */ 36 | 37 | #if (__ARMCC_VERSION < 400677) 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 39 | #endif 40 | 41 | /* intrinsic void __enable_irq(); */ 42 | /* intrinsic void __disable_irq(); */ 43 | 44 | /** \brief Get Control Register 45 | 46 | This function returns the content of the Control Register. 47 | 48 | \return Control Register value 49 | */ 50 | __STATIC_INLINE uint32_t __get_CONTROL(void) 51 | { 52 | register uint32_t __regControl __ASM("control"); 53 | return(__regControl); 54 | } 55 | 56 | 57 | /** \brief Set Control Register 58 | 59 | This function writes the given value to the Control Register. 60 | 61 | \param [in] control Control Register value to set 62 | */ 63 | __STATIC_INLINE void __set_CONTROL(uint32_t control) 64 | { 65 | register uint32_t __regControl __ASM("control"); 66 | __regControl = control; 67 | } 68 | 69 | 70 | /** \brief Get IPSR Register 71 | 72 | This function returns the content of the IPSR Register. 73 | 74 | \return IPSR Register value 75 | */ 76 | __STATIC_INLINE uint32_t __get_IPSR(void) 77 | { 78 | register uint32_t __regIPSR __ASM("ipsr"); 79 | return(__regIPSR); 80 | } 81 | 82 | 83 | /** \brief Get APSR Register 84 | 85 | This function returns the content of the APSR Register. 86 | 87 | \return APSR Register value 88 | */ 89 | __STATIC_INLINE uint32_t __get_APSR(void) 90 | { 91 | register uint32_t __regAPSR __ASM("apsr"); 92 | return(__regAPSR); 93 | } 94 | 95 | 96 | /** \brief Get xPSR Register 97 | 98 | This function returns the content of the xPSR Register. 99 | 100 | \return xPSR Register value 101 | */ 102 | __STATIC_INLINE uint32_t __get_xPSR(void) 103 | { 104 | register uint32_t __regXPSR __ASM("xpsr"); 105 | return(__regXPSR); 106 | } 107 | 108 | 109 | /** \brief Get Process Stack Pointer 110 | 111 | This function returns the current value of the Process Stack Pointer (PSP). 112 | 113 | \return PSP Register value 114 | */ 115 | __STATIC_INLINE uint32_t __get_PSP(void) 116 | { 117 | register uint32_t __regProcessStackPointer __ASM("psp"); 118 | return(__regProcessStackPointer); 119 | } 120 | 121 | 122 | /** \brief Set Process Stack Pointer 123 | 124 | This function assigns the given value to the Process Stack Pointer (PSP). 125 | 126 | \param [in] topOfProcStack Process Stack Pointer value to set 127 | */ 128 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 129 | { 130 | register uint32_t __regProcessStackPointer __ASM("psp"); 131 | __regProcessStackPointer = topOfProcStack; 132 | } 133 | 134 | 135 | /** \brief Get Main Stack Pointer 136 | 137 | This function returns the current value of the Main Stack Pointer (MSP). 138 | 139 | \return MSP Register value 140 | */ 141 | __STATIC_INLINE uint32_t __get_MSP(void) 142 | { 143 | register uint32_t __regMainStackPointer __ASM("msp"); 144 | return(__regMainStackPointer); 145 | } 146 | 147 | 148 | /** \brief Set Main Stack Pointer 149 | 150 | This function assigns the given value to the Main Stack Pointer (MSP). 151 | 152 | \param [in] topOfMainStack Main Stack Pointer value to set 153 | */ 154 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 155 | { 156 | register uint32_t __regMainStackPointer __ASM("msp"); 157 | __regMainStackPointer = topOfMainStack; 158 | } 159 | 160 | 161 | /** \brief Get Priority Mask 162 | 163 | This function returns the current state of the priority mask bit from the Priority Mask Register. 164 | 165 | \return Priority Mask value 166 | */ 167 | __STATIC_INLINE uint32_t __get_PRIMASK(void) 168 | { 169 | register uint32_t __regPriMask __ASM("primask"); 170 | return(__regPriMask); 171 | } 172 | 173 | 174 | /** \brief Set Priority Mask 175 | 176 | This function assigns the given value to the Priority Mask Register. 177 | 178 | \param [in] priMask Priority Mask 179 | */ 180 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 181 | { 182 | register uint32_t __regPriMask __ASM("primask"); 183 | __regPriMask = (priMask); 184 | } 185 | 186 | 187 | #if (__CORTEX_M >= 0x03) 188 | 189 | /** \brief Enable FIQ 190 | 191 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. 192 | Can only be executed in Privileged modes. 193 | */ 194 | #define __enable_fault_irq __enable_fiq 195 | 196 | 197 | /** \brief Disable FIQ 198 | 199 | This function disables FIQ interrupts by setting the F-bit in the CPSR. 200 | Can only be executed in Privileged modes. 201 | */ 202 | #define __disable_fault_irq __disable_fiq 203 | 204 | 205 | /** \brief Get Base Priority 206 | 207 | This function returns the current value of the Base Priority register. 208 | 209 | \return Base Priority register value 210 | */ 211 | __STATIC_INLINE uint32_t __get_BASEPRI(void) 212 | { 213 | register uint32_t __regBasePri __ASM("basepri"); 214 | return(__regBasePri); 215 | } 216 | 217 | 218 | /** \brief Set Base Priority 219 | 220 | This function assigns the given value to the Base Priority register. 221 | 222 | \param [in] basePri Base Priority value to set 223 | */ 224 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) 225 | { 226 | register uint32_t __regBasePri __ASM("basepri"); 227 | __regBasePri = (basePri & 0xff); 228 | } 229 | 230 | 231 | /** \brief Get Fault Mask 232 | 233 | This function returns the current value of the Fault Mask register. 234 | 235 | \return Fault Mask register value 236 | */ 237 | __STATIC_INLINE uint32_t __get_FAULTMASK(void) 238 | { 239 | register uint32_t __regFaultMask __ASM("faultmask"); 240 | return(__regFaultMask); 241 | } 242 | 243 | 244 | /** \brief Set Fault Mask 245 | 246 | This function assigns the given value to the Fault Mask register. 247 | 248 | \param [in] faultMask Fault Mask value to set 249 | */ 250 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 251 | { 252 | register uint32_t __regFaultMask __ASM("faultmask"); 253 | __regFaultMask = (faultMask & (uint32_t)1); 254 | } 255 | 256 | #endif /* (__CORTEX_M >= 0x03) */ 257 | 258 | 259 | #if (__CORTEX_M == 0x04) 260 | 261 | /** \brief Get FPSCR 262 | 263 | This function returns the current value of the Floating Point Status/Control register. 264 | 265 | \return Floating Point Status/Control register value 266 | */ 267 | __STATIC_INLINE uint32_t __get_FPSCR(void) 268 | { 269 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 270 | register uint32_t __regfpscr __ASM("fpscr"); 271 | return(__regfpscr); 272 | #else 273 | return(0); 274 | #endif 275 | } 276 | 277 | 278 | /** \brief Set FPSCR 279 | 280 | This function assigns the given value to the Floating Point Status/Control register. 281 | 282 | \param [in] fpscr Floating Point Status/Control value to set 283 | */ 284 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 285 | { 286 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 287 | register uint32_t __regfpscr __ASM("fpscr"); 288 | __regfpscr = (fpscr); 289 | #endif 290 | } 291 | 292 | #endif /* (__CORTEX_M == 0x04) */ 293 | 294 | 295 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 296 | /* IAR iccarm specific functions */ 297 | 298 | #include 299 | 300 | 301 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ 302 | /* TI CCS specific functions */ 303 | 304 | #include 305 | 306 | 307 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 308 | /* GNU gcc specific functions */ 309 | 310 | /** \brief Enable IRQ Interrupts 311 | 312 | This function enables IRQ interrupts by clearing the I-bit in the CPSR. 313 | Can only be executed in Privileged modes. 314 | */ 315 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) 316 | { 317 | __ASM volatile ("cpsie i"); 318 | } 319 | 320 | 321 | /** \brief Disable IRQ Interrupts 322 | 323 | This function disables IRQ interrupts by setting the I-bit in the CPSR. 324 | Can only be executed in Privileged modes. 325 | */ 326 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) 327 | { 328 | __ASM volatile ("cpsid i"); 329 | } 330 | 331 | 332 | /** \brief Get Control Register 333 | 334 | This function returns the content of the Control Register. 335 | 336 | \return Control Register value 337 | */ 338 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) 339 | { 340 | uint32_t result; 341 | 342 | __ASM volatile ("MRS %0, control" : "=r" (result) ); 343 | return(result); 344 | } 345 | 346 | 347 | /** \brief Set Control Register 348 | 349 | This function writes the given value to the Control Register. 350 | 351 | \param [in] control Control Register value to set 352 | */ 353 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) 354 | { 355 | __ASM volatile ("MSR control, %0" : : "r" (control) ); 356 | } 357 | 358 | 359 | /** \brief Get IPSR Register 360 | 361 | This function returns the content of the IPSR Register. 362 | 363 | \return IPSR Register value 364 | */ 365 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) 366 | { 367 | uint32_t result; 368 | 369 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 370 | return(result); 371 | } 372 | 373 | 374 | /** \brief Get APSR Register 375 | 376 | This function returns the content of the APSR Register. 377 | 378 | \return APSR Register value 379 | */ 380 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) 381 | { 382 | uint32_t result; 383 | 384 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 385 | return(result); 386 | } 387 | 388 | 389 | /** \brief Get xPSR Register 390 | 391 | This function returns the content of the xPSR Register. 392 | 393 | \return xPSR Register value 394 | */ 395 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) 396 | { 397 | uint32_t result; 398 | 399 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 400 | return(result); 401 | } 402 | 403 | 404 | /** \brief Get Process Stack Pointer 405 | 406 | This function returns the current value of the Process Stack Pointer (PSP). 407 | 408 | \return PSP Register value 409 | */ 410 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) 411 | { 412 | register uint32_t result; 413 | 414 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); 415 | return(result); 416 | } 417 | 418 | 419 | /** \brief Set Process Stack Pointer 420 | 421 | This function assigns the given value to the Process Stack Pointer (PSP). 422 | 423 | \param [in] topOfProcStack Process Stack Pointer value to set 424 | */ 425 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 426 | { 427 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); 428 | } 429 | 430 | 431 | /** \brief Get Main Stack Pointer 432 | 433 | This function returns the current value of the Main Stack Pointer (MSP). 434 | 435 | \return MSP Register value 436 | */ 437 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) 438 | { 439 | register uint32_t result; 440 | 441 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); 442 | return(result); 443 | } 444 | 445 | 446 | /** \brief Set Main Stack Pointer 447 | 448 | This function assigns the given value to the Main Stack Pointer (MSP). 449 | 450 | \param [in] topOfMainStack Main Stack Pointer value to set 451 | */ 452 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 453 | { 454 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); 455 | } 456 | 457 | 458 | /** \brief Get Priority Mask 459 | 460 | This function returns the current state of the priority mask bit from the Priority Mask Register. 461 | 462 | \return Priority Mask value 463 | */ 464 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) 465 | { 466 | uint32_t result; 467 | 468 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); 469 | return(result); 470 | } 471 | 472 | 473 | /** \brief Set Priority Mask 474 | 475 | This function assigns the given value to the Priority Mask Register. 476 | 477 | \param [in] priMask Priority Mask 478 | */ 479 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 480 | { 481 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); 482 | } 483 | 484 | 485 | #if (__CORTEX_M >= 0x03) 486 | 487 | /** \brief Enable FIQ 488 | 489 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. 490 | Can only be executed in Privileged modes. 491 | */ 492 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) 493 | { 494 | __ASM volatile ("cpsie f"); 495 | } 496 | 497 | 498 | /** \brief Disable FIQ 499 | 500 | This function disables FIQ interrupts by setting the F-bit in the CPSR. 501 | Can only be executed in Privileged modes. 502 | */ 503 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) 504 | { 505 | __ASM volatile ("cpsid f"); 506 | } 507 | 508 | 509 | /** \brief Get Base Priority 510 | 511 | This function returns the current value of the Base Priority register. 512 | 513 | \return Base Priority register value 514 | */ 515 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) 516 | { 517 | uint32_t result; 518 | 519 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); 520 | return(result); 521 | } 522 | 523 | 524 | /** \brief Set Base Priority 525 | 526 | This function assigns the given value to the Base Priority register. 527 | 528 | \param [in] basePri Base Priority value to set 529 | */ 530 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) 531 | { 532 | __ASM volatile ("MSR basepri, %0" : : "r" (value) ); 533 | } 534 | 535 | 536 | /** \brief Get Fault Mask 537 | 538 | This function returns the current value of the Fault Mask register. 539 | 540 | \return Fault Mask register value 541 | */ 542 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) 543 | { 544 | uint32_t result; 545 | 546 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 547 | return(result); 548 | } 549 | 550 | 551 | /** \brief Set Fault Mask 552 | 553 | This function assigns the given value to the Fault Mask register. 554 | 555 | \param [in] faultMask Fault Mask value to set 556 | */ 557 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 558 | { 559 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); 560 | } 561 | 562 | #endif /* (__CORTEX_M >= 0x03) */ 563 | 564 | 565 | #if (__CORTEX_M == 0x04) 566 | 567 | /** \brief Get FPSCR 568 | 569 | This function returns the current value of the Floating Point Status/Control register. 570 | 571 | \return Floating Point Status/Control register value 572 | */ 573 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) 574 | { 575 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 576 | uint32_t result; 577 | 578 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 579 | return(result); 580 | #else 581 | return(0); 582 | #endif 583 | } 584 | 585 | 586 | /** \brief Set FPSCR 587 | 588 | This function assigns the given value to the Floating Point Status/Control register. 589 | 590 | \param [in] fpscr Floating Point Status/Control value to set 591 | */ 592 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 593 | { 594 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 595 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); 596 | #endif 597 | } 598 | 599 | #endif /* (__CORTEX_M == 0x04) */ 600 | 601 | 602 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 603 | /* TASKING carm specific functions */ 604 | 605 | /* 606 | * The CMSIS functions have been implemented as intrinsics in the compiler. 607 | * Please use "carm -?i" to get an up to date list of all instrinsics, 608 | * Including the CMSIS ones. 609 | */ 610 | 611 | #endif 612 | 613 | /*@} end of CMSIS_Core_RegAccFunctions */ 614 | 615 | 616 | #endif /* __CORE_CMFUNC_H */ 617 | -------------------------------------------------------------------------------- /stm_lib/inc/stm32f10x_spi.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_spi.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the SPI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_SPI_H 25 | #define __STM32F10x_SPI_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup SPI 39 | * @{ 40 | */ 41 | 42 | /** @defgroup SPI_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief SPI Init structure definition 48 | */ 49 | 50 | typedef struct 51 | { 52 | uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. 53 | This parameter can be a value of @ref SPI_data_direction */ 54 | 55 | uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. 56 | This parameter can be a value of @ref SPI_mode */ 57 | 58 | uint16_t SPI_DataSize; /*!< Specifies the SPI data size. 59 | This parameter can be a value of @ref SPI_data_size */ 60 | 61 | uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. 62 | This parameter can be a value of @ref SPI_Clock_Polarity */ 63 | 64 | uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. 65 | This parameter can be a value of @ref SPI_Clock_Phase */ 66 | 67 | uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by 68 | hardware (NSS pin) or by software using the SSI bit. 69 | This parameter can be a value of @ref SPI_Slave_Select_management */ 70 | 71 | uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 72 | used to configure the transmit and receive SCK clock. 73 | This parameter can be a value of @ref SPI_BaudRate_Prescaler. 74 | @note The communication clock is derived from the master 75 | clock. The slave clock does not need to be set. */ 76 | 77 | uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 78 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 79 | 80 | uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ 81 | }SPI_InitTypeDef; 82 | 83 | /** 84 | * @brief I2S Init structure definition 85 | */ 86 | 87 | typedef struct 88 | { 89 | 90 | uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. 91 | This parameter can be a value of @ref I2S_Mode */ 92 | 93 | uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. 94 | This parameter can be a value of @ref I2S_Standard */ 95 | 96 | uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. 97 | This parameter can be a value of @ref I2S_Data_Format */ 98 | 99 | uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 100 | This parameter can be a value of @ref I2S_MCLK_Output */ 101 | 102 | uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 103 | This parameter can be a value of @ref I2S_Audio_Frequency */ 104 | 105 | uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. 106 | This parameter can be a value of @ref I2S_Clock_Polarity */ 107 | }I2S_InitTypeDef; 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @defgroup SPI_Exported_Constants 114 | * @{ 115 | */ 116 | 117 | #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ 118 | ((PERIPH) == SPI2) || \ 119 | ((PERIPH) == SPI3)) 120 | 121 | #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ 122 | ((PERIPH) == SPI3)) 123 | 124 | /** @defgroup SPI_data_direction 125 | * @{ 126 | */ 127 | 128 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 129 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 130 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 131 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 132 | #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ 133 | ((MODE) == SPI_Direction_2Lines_RxOnly) || \ 134 | ((MODE) == SPI_Direction_1Line_Rx) || \ 135 | ((MODE) == SPI_Direction_1Line_Tx)) 136 | /** 137 | * @} 138 | */ 139 | 140 | /** @defgroup SPI_mode 141 | * @{ 142 | */ 143 | 144 | #define SPI_Mode_Master ((uint16_t)0x0104) 145 | #define SPI_Mode_Slave ((uint16_t)0x0000) 146 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 147 | ((MODE) == SPI_Mode_Slave)) 148 | /** 149 | * @} 150 | */ 151 | 152 | /** @defgroup SPI_data_size 153 | * @{ 154 | */ 155 | 156 | #define SPI_DataSize_16b ((uint16_t)0x0800) 157 | #define SPI_DataSize_8b ((uint16_t)0x0000) 158 | #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ 159 | ((DATASIZE) == SPI_DataSize_8b)) 160 | /** 161 | * @} 162 | */ 163 | 164 | /** @defgroup SPI_Clock_Polarity 165 | * @{ 166 | */ 167 | 168 | #define SPI_CPOL_Low ((uint16_t)0x0000) 169 | #define SPI_CPOL_High ((uint16_t)0x0002) 170 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 171 | ((CPOL) == SPI_CPOL_High)) 172 | /** 173 | * @} 174 | */ 175 | 176 | /** @defgroup SPI_Clock_Phase 177 | * @{ 178 | */ 179 | 180 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) 181 | #define SPI_CPHA_2Edge ((uint16_t)0x0001) 182 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 183 | ((CPHA) == SPI_CPHA_2Edge)) 184 | /** 185 | * @} 186 | */ 187 | 188 | /** @defgroup SPI_Slave_Select_management 189 | * @{ 190 | */ 191 | 192 | #define SPI_NSS_Soft ((uint16_t)0x0200) 193 | #define SPI_NSS_Hard ((uint16_t)0x0000) 194 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 195 | ((NSS) == SPI_NSS_Hard)) 196 | /** 197 | * @} 198 | */ 199 | 200 | /** @defgroup SPI_BaudRate_Prescaler 201 | * @{ 202 | */ 203 | 204 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 205 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 206 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 207 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 208 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 209 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 210 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 211 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 212 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 213 | ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 214 | ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 215 | ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 216 | ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 217 | ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 218 | ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 219 | ((PRESCALER) == SPI_BaudRatePrescaler_256)) 220 | /** 221 | * @} 222 | */ 223 | 224 | /** @defgroup SPI_MSB_LSB_transmission 225 | * @{ 226 | */ 227 | 228 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) 229 | #define SPI_FirstBit_LSB ((uint16_t)0x0080) 230 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 231 | ((BIT) == SPI_FirstBit_LSB)) 232 | /** 233 | * @} 234 | */ 235 | 236 | /** @defgroup I2S_Mode 237 | * @{ 238 | */ 239 | 240 | #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 241 | #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 242 | #define I2S_Mode_MasterTx ((uint16_t)0x0200) 243 | #define I2S_Mode_MasterRx ((uint16_t)0x0300) 244 | #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ 245 | ((MODE) == I2S_Mode_SlaveRx) || \ 246 | ((MODE) == I2S_Mode_MasterTx) || \ 247 | ((MODE) == I2S_Mode_MasterRx) ) 248 | /** 249 | * @} 250 | */ 251 | 252 | /** @defgroup I2S_Standard 253 | * @{ 254 | */ 255 | 256 | #define I2S_Standard_Phillips ((uint16_t)0x0000) 257 | #define I2S_Standard_MSB ((uint16_t)0x0010) 258 | #define I2S_Standard_LSB ((uint16_t)0x0020) 259 | #define I2S_Standard_PCMShort ((uint16_t)0x0030) 260 | #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 261 | #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ 262 | ((STANDARD) == I2S_Standard_MSB) || \ 263 | ((STANDARD) == I2S_Standard_LSB) || \ 264 | ((STANDARD) == I2S_Standard_PCMShort) || \ 265 | ((STANDARD) == I2S_Standard_PCMLong)) 266 | /** 267 | * @} 268 | */ 269 | 270 | /** @defgroup I2S_Data_Format 271 | * @{ 272 | */ 273 | 274 | #define I2S_DataFormat_16b ((uint16_t)0x0000) 275 | #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 276 | #define I2S_DataFormat_24b ((uint16_t)0x0003) 277 | #define I2S_DataFormat_32b ((uint16_t)0x0005) 278 | #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ 279 | ((FORMAT) == I2S_DataFormat_16bextended) || \ 280 | ((FORMAT) == I2S_DataFormat_24b) || \ 281 | ((FORMAT) == I2S_DataFormat_32b)) 282 | /** 283 | * @} 284 | */ 285 | 286 | /** @defgroup I2S_MCLK_Output 287 | * @{ 288 | */ 289 | 290 | #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 291 | #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 292 | #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ 293 | ((OUTPUT) == I2S_MCLKOutput_Disable)) 294 | /** 295 | * @} 296 | */ 297 | 298 | /** @defgroup I2S_Audio_Frequency 299 | * @{ 300 | */ 301 | 302 | #define I2S_AudioFreq_192k ((uint32_t)192000) 303 | #define I2S_AudioFreq_96k ((uint32_t)96000) 304 | #define I2S_AudioFreq_48k ((uint32_t)48000) 305 | #define I2S_AudioFreq_44k ((uint32_t)44100) 306 | #define I2S_AudioFreq_32k ((uint32_t)32000) 307 | #define I2S_AudioFreq_22k ((uint32_t)22050) 308 | #define I2S_AudioFreq_16k ((uint32_t)16000) 309 | #define I2S_AudioFreq_11k ((uint32_t)11025) 310 | #define I2S_AudioFreq_8k ((uint32_t)8000) 311 | #define I2S_AudioFreq_Default ((uint32_t)2) 312 | 313 | #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ 314 | ((FREQ) <= I2S_AudioFreq_192k)) || \ 315 | ((FREQ) == I2S_AudioFreq_Default)) 316 | /** 317 | * @} 318 | */ 319 | 320 | /** @defgroup I2S_Clock_Polarity 321 | * @{ 322 | */ 323 | 324 | #define I2S_CPOL_Low ((uint16_t)0x0000) 325 | #define I2S_CPOL_High ((uint16_t)0x0008) 326 | #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ 327 | ((CPOL) == I2S_CPOL_High)) 328 | /** 329 | * @} 330 | */ 331 | 332 | /** @defgroup SPI_I2S_DMA_transfer_requests 333 | * @{ 334 | */ 335 | 336 | #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 337 | #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 338 | #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) 339 | /** 340 | * @} 341 | */ 342 | 343 | /** @defgroup SPI_NSS_internal_software_management 344 | * @{ 345 | */ 346 | 347 | #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 348 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 349 | #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 350 | ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 351 | /** 352 | * @} 353 | */ 354 | 355 | /** @defgroup SPI_CRC_Transmit_Receive 356 | * @{ 357 | */ 358 | 359 | #define SPI_CRC_Tx ((uint8_t)0x00) 360 | #define SPI_CRC_Rx ((uint8_t)0x01) 361 | #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) 362 | /** 363 | * @} 364 | */ 365 | 366 | /** @defgroup SPI_direction_transmit_receive 367 | * @{ 368 | */ 369 | 370 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) 371 | #define SPI_Direction_Tx ((uint16_t)0x4000) 372 | #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 373 | ((DIRECTION) == SPI_Direction_Tx)) 374 | /** 375 | * @} 376 | */ 377 | 378 | /** @defgroup SPI_I2S_interrupts_definition 379 | * @{ 380 | */ 381 | 382 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) 383 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 384 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) 385 | #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ 386 | ((IT) == SPI_I2S_IT_RXNE) || \ 387 | ((IT) == SPI_I2S_IT_ERR)) 388 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) 389 | #define SPI_IT_MODF ((uint8_t)0x55) 390 | #define SPI_IT_CRCERR ((uint8_t)0x54) 391 | #define I2S_IT_UDR ((uint8_t)0x53) 392 | #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) 393 | #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ 394 | ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ 395 | ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) 396 | /** 397 | * @} 398 | */ 399 | 400 | /** @defgroup SPI_I2S_flags_definition 401 | * @{ 402 | */ 403 | 404 | #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 405 | #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 406 | #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 407 | #define I2S_FLAG_UDR ((uint16_t)0x0008) 408 | #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 409 | #define SPI_FLAG_MODF ((uint16_t)0x0020) 410 | #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 411 | #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 412 | #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) 413 | #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ 414 | ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ 415 | ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ 416 | ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) 417 | /** 418 | * @} 419 | */ 420 | 421 | /** @defgroup SPI_CRC_polynomial 422 | * @{ 423 | */ 424 | 425 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 426 | /** 427 | * @} 428 | */ 429 | 430 | /** 431 | * @} 432 | */ 433 | 434 | /** @defgroup SPI_Exported_Macros 435 | * @{ 436 | */ 437 | 438 | /** 439 | * @} 440 | */ 441 | 442 | /** @defgroup SPI_Exported_Functions 443 | * @{ 444 | */ 445 | 446 | void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 447 | void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 448 | void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); 449 | void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 450 | void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); 451 | void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 452 | void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 453 | void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 454 | void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 455 | void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); 456 | uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); 457 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 458 | void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 459 | void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 460 | void SPI_TransmitCRC(SPI_TypeDef* SPIx); 461 | void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 462 | uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 463 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 464 | void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 465 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 466 | void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 467 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 468 | void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 469 | 470 | #ifdef __cplusplus 471 | } 472 | #endif 473 | 474 | #endif /*__STM32F10x_SPI_H */ 475 | /** 476 | * @} 477 | */ 478 | 479 | /** 480 | * @} 481 | */ 482 | 483 | /** 484 | * @} 485 | */ 486 | 487 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 488 | -------------------------------------------------------------------------------- /cmsis/core_cmInstr.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cmInstr.h 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File 4 | * @version V3.01 5 | * @date 06. March 2012 6 | * 7 | * @note 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 9 | * 10 | * @par 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 | * processor based microcontrollers. This file can be freely distributed 13 | * within development tools that are supporting such ARM based processors. 14 | * 15 | * @par 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 | * 22 | ******************************************************************************/ 23 | 24 | #ifndef __CORE_CMINSTR_H 25 | #define __CORE_CMINSTR_H 26 | 27 | 28 | /* ########################## Core Instruction Access ######################### */ 29 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 30 | Access to dedicated instructions 31 | @{ 32 | */ 33 | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 35 | /* ARM armcc specific functions */ 36 | 37 | #if (__ARMCC_VERSION < 400677) 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 39 | #endif 40 | 41 | 42 | /** \brief No Operation 43 | 44 | No Operation does nothing. This instruction can be used for code alignment purposes. 45 | */ 46 | #define __NOP __nop 47 | 48 | 49 | /** \brief Wait For Interrupt 50 | 51 | Wait For Interrupt is a hint instruction that suspends execution 52 | until one of a number of events occurs. 53 | */ 54 | #define __WFI __wfi 55 | 56 | 57 | /** \brief Wait For Event 58 | 59 | Wait For Event is a hint instruction that permits the processor to enter 60 | a low-power state until one of a number of events occurs. 61 | */ 62 | #define __WFE __wfe 63 | 64 | 65 | /** \brief Send Event 66 | 67 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. 68 | */ 69 | #define __SEV __sev 70 | 71 | 72 | /** \brief Instruction Synchronization Barrier 73 | 74 | Instruction Synchronization Barrier flushes the pipeline in the processor, 75 | so that all instructions following the ISB are fetched from cache or 76 | memory, after the instruction has been completed. 77 | */ 78 | #define __ISB() __isb(0xF) 79 | 80 | 81 | /** \brief Data Synchronization Barrier 82 | 83 | This function acts as a special kind of Data Memory Barrier. 84 | It completes when all explicit memory accesses before this instruction complete. 85 | */ 86 | #define __DSB() __dsb(0xF) 87 | 88 | 89 | /** \brief Data Memory Barrier 90 | 91 | This function ensures the apparent order of the explicit memory operations before 92 | and after the instruction, without ensuring their completion. 93 | */ 94 | #define __DMB() __dmb(0xF) 95 | 96 | 97 | /** \brief Reverse byte order (32 bit) 98 | 99 | This function reverses the byte order in integer value. 100 | 101 | \param [in] value Value to reverse 102 | \return Reversed value 103 | */ 104 | #define __REV __rev 105 | 106 | 107 | /** \brief Reverse byte order (16 bit) 108 | 109 | This function reverses the byte order in two unsigned short values. 110 | 111 | \param [in] value Value to reverse 112 | \return Reversed value 113 | */ 114 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) 115 | { 116 | rev16 r0, r0 117 | bx lr 118 | } 119 | 120 | 121 | /** \brief Reverse byte order in signed short value 122 | 123 | This function reverses the byte order in a signed short value with sign extension to integer. 124 | 125 | \param [in] value Value to reverse 126 | \return Reversed value 127 | */ 128 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) 129 | { 130 | revsh r0, r0 131 | bx lr 132 | } 133 | 134 | 135 | /** \brief Rotate Right in unsigned value (32 bit) 136 | 137 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 138 | 139 | \param [in] value Value to rotate 140 | \param [in] value Number of Bits to rotate 141 | \return Rotated value 142 | */ 143 | #define __ROR __ror 144 | 145 | 146 | #if (__CORTEX_M >= 0x03) 147 | 148 | /** \brief Reverse bit order of value 149 | 150 | This function reverses the bit order of the given value. 151 | 152 | \param [in] value Value to reverse 153 | \return Reversed value 154 | */ 155 | #define __RBIT __rbit 156 | 157 | 158 | /** \brief LDR Exclusive (8 bit) 159 | 160 | This function performs a exclusive LDR command for 8 bit value. 161 | 162 | \param [in] ptr Pointer to data 163 | \return value of type uint8_t at (*ptr) 164 | */ 165 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) 166 | 167 | 168 | /** \brief LDR Exclusive (16 bit) 169 | 170 | This function performs a exclusive LDR command for 16 bit values. 171 | 172 | \param [in] ptr Pointer to data 173 | \return value of type uint16_t at (*ptr) 174 | */ 175 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) 176 | 177 | 178 | /** \brief LDR Exclusive (32 bit) 179 | 180 | This function performs a exclusive LDR command for 32 bit values. 181 | 182 | \param [in] ptr Pointer to data 183 | \return value of type uint32_t at (*ptr) 184 | */ 185 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) 186 | 187 | 188 | /** \brief STR Exclusive (8 bit) 189 | 190 | This function performs a exclusive STR command for 8 bit values. 191 | 192 | \param [in] value Value to store 193 | \param [in] ptr Pointer to location 194 | \return 0 Function succeeded 195 | \return 1 Function failed 196 | */ 197 | #define __STREXB(value, ptr) __strex(value, ptr) 198 | 199 | 200 | /** \brief STR Exclusive (16 bit) 201 | 202 | This function performs a exclusive STR command for 16 bit values. 203 | 204 | \param [in] value Value to store 205 | \param [in] ptr Pointer to location 206 | \return 0 Function succeeded 207 | \return 1 Function failed 208 | */ 209 | #define __STREXH(value, ptr) __strex(value, ptr) 210 | 211 | 212 | /** \brief STR Exclusive (32 bit) 213 | 214 | This function performs a exclusive STR command for 32 bit values. 215 | 216 | \param [in] value Value to store 217 | \param [in] ptr Pointer to location 218 | \return 0 Function succeeded 219 | \return 1 Function failed 220 | */ 221 | #define __STREXW(value, ptr) __strex(value, ptr) 222 | 223 | 224 | /** \brief Remove the exclusive lock 225 | 226 | This function removes the exclusive lock which is created by LDREX. 227 | 228 | */ 229 | #define __CLREX __clrex 230 | 231 | 232 | /** \brief Signed Saturate 233 | 234 | This function saturates a signed value. 235 | 236 | \param [in] value Value to be saturated 237 | \param [in] sat Bit position to saturate to (1..32) 238 | \return Saturated value 239 | */ 240 | #define __SSAT __ssat 241 | 242 | 243 | /** \brief Unsigned Saturate 244 | 245 | This function saturates an unsigned value. 246 | 247 | \param [in] value Value to be saturated 248 | \param [in] sat Bit position to saturate to (0..31) 249 | \return Saturated value 250 | */ 251 | #define __USAT __usat 252 | 253 | 254 | /** \brief Count leading zeros 255 | 256 | This function counts the number of leading zeros of a data value. 257 | 258 | \param [in] value Value to count the leading zeros 259 | \return number of leading zeros in value 260 | */ 261 | #define __CLZ __clz 262 | 263 | #endif /* (__CORTEX_M >= 0x03) */ 264 | 265 | 266 | 267 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 268 | /* IAR iccarm specific functions */ 269 | 270 | #include 271 | 272 | 273 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ 274 | /* TI CCS specific functions */ 275 | 276 | #include 277 | 278 | 279 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 280 | /* GNU gcc specific functions */ 281 | 282 | /** \brief No Operation 283 | 284 | No Operation does nothing. This instruction can be used for code alignment purposes. 285 | */ 286 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) 287 | { 288 | __ASM volatile ("nop"); 289 | } 290 | 291 | 292 | /** \brief Wait For Interrupt 293 | 294 | Wait For Interrupt is a hint instruction that suspends execution 295 | until one of a number of events occurs. 296 | */ 297 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) 298 | { 299 | __ASM volatile ("wfi"); 300 | } 301 | 302 | 303 | /** \brief Wait For Event 304 | 305 | Wait For Event is a hint instruction that permits the processor to enter 306 | a low-power state until one of a number of events occurs. 307 | */ 308 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) 309 | { 310 | __ASM volatile ("wfe"); 311 | } 312 | 313 | 314 | /** \brief Send Event 315 | 316 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. 317 | */ 318 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) 319 | { 320 | __ASM volatile ("sev"); 321 | } 322 | 323 | 324 | /** \brief Instruction Synchronization Barrier 325 | 326 | Instruction Synchronization Barrier flushes the pipeline in the processor, 327 | so that all instructions following the ISB are fetched from cache or 328 | memory, after the instruction has been completed. 329 | */ 330 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) 331 | { 332 | __ASM volatile ("isb"); 333 | } 334 | 335 | 336 | /** \brief Data Synchronization Barrier 337 | 338 | This function acts as a special kind of Data Memory Barrier. 339 | It completes when all explicit memory accesses before this instruction complete. 340 | */ 341 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) 342 | { 343 | __ASM volatile ("dsb"); 344 | } 345 | 346 | 347 | /** \brief Data Memory Barrier 348 | 349 | This function ensures the apparent order of the explicit memory operations before 350 | and after the instruction, without ensuring their completion. 351 | */ 352 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) 353 | { 354 | __ASM volatile ("dmb"); 355 | } 356 | 357 | 358 | /** \brief Reverse byte order (32 bit) 359 | 360 | This function reverses the byte order in integer value. 361 | 362 | \param [in] value Value to reverse 363 | \return Reversed value 364 | */ 365 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) 366 | { 367 | uint32_t result; 368 | 369 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); 370 | return(result); 371 | } 372 | 373 | 374 | /** \brief Reverse byte order (16 bit) 375 | 376 | This function reverses the byte order in two unsigned short values. 377 | 378 | \param [in] value Value to reverse 379 | \return Reversed value 380 | */ 381 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) 382 | { 383 | uint32_t result; 384 | 385 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); 386 | return(result); 387 | } 388 | 389 | 390 | /** \brief Reverse byte order in signed short value 391 | 392 | This function reverses the byte order in a signed short value with sign extension to integer. 393 | 394 | \param [in] value Value to reverse 395 | \return Reversed value 396 | */ 397 | __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) 398 | { 399 | uint32_t result; 400 | 401 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); 402 | return(result); 403 | } 404 | 405 | 406 | /** \brief Rotate Right in unsigned value (32 bit) 407 | 408 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 409 | 410 | \param [in] value Value to rotate 411 | \param [in] value Number of Bits to rotate 412 | \return Rotated value 413 | */ 414 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 415 | { 416 | 417 | __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); 418 | return(op1); 419 | } 420 | 421 | 422 | #if (__CORTEX_M >= 0x03) 423 | 424 | /** \brief Reverse bit order of value 425 | 426 | This function reverses the bit order of the given value. 427 | 428 | \param [in] value Value to reverse 429 | \return Reversed value 430 | */ 431 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) 432 | { 433 | uint32_t result; 434 | 435 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 436 | return(result); 437 | } 438 | 439 | 440 | /** \brief LDR Exclusive (8 bit) 441 | 442 | This function performs a exclusive LDR command for 8 bit value. 443 | 444 | \param [in] ptr Pointer to data 445 | \return value of type uint8_t at (*ptr) 446 | */ 447 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) 448 | { 449 | uint8_t result; 450 | 451 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); 452 | return(result); 453 | } 454 | 455 | 456 | /** \brief LDR Exclusive (16 bit) 457 | 458 | This function performs a exclusive LDR command for 16 bit values. 459 | 460 | \param [in] ptr Pointer to data 461 | \return value of type uint16_t at (*ptr) 462 | */ 463 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) 464 | { 465 | uint16_t result; 466 | 467 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); 468 | return(result); 469 | } 470 | 471 | 472 | /** \brief LDR Exclusive (32 bit) 473 | 474 | This function performs a exclusive LDR command for 32 bit values. 475 | 476 | \param [in] ptr Pointer to data 477 | \return value of type uint32_t at (*ptr) 478 | */ 479 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) 480 | { 481 | uint32_t result; 482 | 483 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); 484 | return(result); 485 | } 486 | 487 | 488 | /** \brief STR Exclusive (8 bit) 489 | 490 | This function performs a exclusive STR command for 8 bit values. 491 | 492 | \param [in] value Value to store 493 | \param [in] ptr Pointer to location 494 | \return 0 Function succeeded 495 | \return 1 Function failed 496 | */ 497 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 498 | { 499 | uint32_t result; 500 | 501 | __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 502 | return(result); 503 | } 504 | 505 | 506 | /** \brief STR Exclusive (16 bit) 507 | 508 | This function performs a exclusive STR command for 16 bit values. 509 | 510 | \param [in] value Value to store 511 | \param [in] ptr Pointer to location 512 | \return 0 Function succeeded 513 | \return 1 Function failed 514 | */ 515 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 516 | { 517 | uint32_t result; 518 | 519 | __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 520 | return(result); 521 | } 522 | 523 | 524 | /** \brief STR Exclusive (32 bit) 525 | 526 | This function performs a exclusive STR command for 32 bit values. 527 | 528 | \param [in] value Value to store 529 | \param [in] ptr Pointer to location 530 | \return 0 Function succeeded 531 | \return 1 Function failed 532 | */ 533 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 534 | { 535 | uint32_t result; 536 | 537 | __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 538 | return(result); 539 | } 540 | 541 | 542 | /** \brief Remove the exclusive lock 543 | 544 | This function removes the exclusive lock which is created by LDREX. 545 | 546 | */ 547 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) 548 | { 549 | __ASM volatile ("clrex"); 550 | } 551 | 552 | 553 | /** \brief Signed Saturate 554 | 555 | This function saturates a signed value. 556 | 557 | \param [in] value Value to be saturated 558 | \param [in] sat Bit position to saturate to (1..32) 559 | \return Saturated value 560 | */ 561 | #define __SSAT(ARG1,ARG2) \ 562 | ({ \ 563 | uint32_t __RES, __ARG1 = (ARG1); \ 564 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 565 | __RES; \ 566 | }) 567 | 568 | 569 | /** \brief Unsigned Saturate 570 | 571 | This function saturates an unsigned value. 572 | 573 | \param [in] value Value to be saturated 574 | \param [in] sat Bit position to saturate to (0..31) 575 | \return Saturated value 576 | */ 577 | #define __USAT(ARG1,ARG2) \ 578 | ({ \ 579 | uint32_t __RES, __ARG1 = (ARG1); \ 580 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 581 | __RES; \ 582 | }) 583 | 584 | 585 | /** \brief Count leading zeros 586 | 587 | This function counts the number of leading zeros of a data value. 588 | 589 | \param [in] value Value to count the leading zeros 590 | \return number of leading zeros in value 591 | */ 592 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) 593 | { 594 | uint8_t result; 595 | 596 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); 597 | return(result); 598 | } 599 | 600 | #endif /* (__CORTEX_M >= 0x03) */ 601 | 602 | 603 | 604 | 605 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 606 | /* TASKING carm specific functions */ 607 | 608 | /* 609 | * The CMSIS functions have been implemented as intrinsics in the compiler. 610 | * Please use "carm -?i" to get an up to date list of all intrinsics, 611 | * Including the CMSIS ones. 612 | */ 613 | 614 | #endif 615 | 616 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 617 | 618 | #endif /* __CORE_CMINSTR_H */ 619 | -------------------------------------------------------------------------------- /stm_lib/inc/stm32f10x_gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_gpio.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the GPIO 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_GPIO_H 25 | #define __STM32F10x_GPIO_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup GPIO 39 | * @{ 40 | */ 41 | 42 | /** @defgroup GPIO_Exported_Types 43 | * @{ 44 | */ 45 | 46 | #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ 47 | ((PERIPH) == GPIOB) || \ 48 | ((PERIPH) == GPIOC) || \ 49 | ((PERIPH) == GPIOD) || \ 50 | ((PERIPH) == GPIOE) || \ 51 | ((PERIPH) == GPIOF) || \ 52 | ((PERIPH) == GPIOG)) 53 | 54 | /** 55 | * @brief Output Maximum frequency selection 56 | */ 57 | 58 | typedef enum 59 | { 60 | GPIO_Speed_10MHz = 1, 61 | GPIO_Speed_2MHz, 62 | GPIO_Speed_50MHz 63 | }GPIOSpeed_TypeDef; 64 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ 65 | ((SPEED) == GPIO_Speed_50MHz)) 66 | 67 | /** 68 | * @brief Configuration Mode enumeration 69 | */ 70 | 71 | typedef enum 72 | { GPIO_Mode_AIN = 0x0, 73 | GPIO_Mode_IN_FLOATING = 0x04, 74 | GPIO_Mode_IPD = 0x28, 75 | GPIO_Mode_IPU = 0x48, 76 | GPIO_Mode_Out_OD = 0x14, 77 | GPIO_Mode_Out_PP = 0x10, 78 | GPIO_Mode_AF_OD = 0x1C, 79 | GPIO_Mode_AF_PP = 0x18 80 | }GPIOMode_TypeDef; 81 | 82 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ 83 | ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ 84 | ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ 85 | ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) 86 | 87 | /** 88 | * @brief GPIO Init structure definition 89 | */ 90 | 91 | typedef struct 92 | { 93 | uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. 94 | This parameter can be any value of @ref GPIO_pins_define */ 95 | 96 | GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. 97 | This parameter can be a value of @ref GPIOSpeed_TypeDef */ 98 | 99 | GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. 100 | This parameter can be a value of @ref GPIOMode_TypeDef */ 101 | }GPIO_InitTypeDef; 102 | 103 | 104 | /** 105 | * @brief Bit_SET and Bit_RESET enumeration 106 | */ 107 | 108 | typedef enum 109 | { Bit_RESET = 0, 110 | Bit_SET 111 | }BitAction; 112 | 113 | #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @defgroup GPIO_Exported_Constants 120 | * @{ 121 | */ 122 | 123 | /** @defgroup GPIO_pins_define 124 | * @{ 125 | */ 126 | 127 | #define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ 128 | #define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ 129 | #define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ 130 | #define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ 131 | #define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ 132 | #define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ 133 | #define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ 134 | #define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ 135 | #define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ 136 | #define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ 137 | #define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ 138 | #define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ 139 | #define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ 140 | #define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ 141 | #define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ 142 | #define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ 143 | #define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ 144 | 145 | #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) 146 | 147 | #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ 148 | ((PIN) == GPIO_Pin_1) || \ 149 | ((PIN) == GPIO_Pin_2) || \ 150 | ((PIN) == GPIO_Pin_3) || \ 151 | ((PIN) == GPIO_Pin_4) || \ 152 | ((PIN) == GPIO_Pin_5) || \ 153 | ((PIN) == GPIO_Pin_6) || \ 154 | ((PIN) == GPIO_Pin_7) || \ 155 | ((PIN) == GPIO_Pin_8) || \ 156 | ((PIN) == GPIO_Pin_9) || \ 157 | ((PIN) == GPIO_Pin_10) || \ 158 | ((PIN) == GPIO_Pin_11) || \ 159 | ((PIN) == GPIO_Pin_12) || \ 160 | ((PIN) == GPIO_Pin_13) || \ 161 | ((PIN) == GPIO_Pin_14) || \ 162 | ((PIN) == GPIO_Pin_15)) 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | /** @defgroup GPIO_Remap_define 169 | * @{ 170 | */ 171 | 172 | #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ 173 | #define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ 174 | #define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ 175 | #define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ 176 | #define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ 177 | #define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ 178 | #define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ 179 | #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ 180 | #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ 181 | #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ 182 | #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ 183 | #define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ 184 | #define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ 185 | #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ 186 | #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ 187 | #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ 188 | #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ 189 | #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ 190 | #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ 191 | #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ 192 | #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ 193 | #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ 194 | #define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ 195 | #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ 196 | #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ 197 | #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ 198 | #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ 199 | #define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ 200 | #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected 201 | to TIM2 Internal Trigger 1 for calibration 202 | (only for Connectivity line devices) */ 203 | #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ 204 | 205 | #define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ 206 | #define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ 207 | #define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ 208 | #define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ 209 | #define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ 210 | 211 | #define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ 212 | #define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ 213 | #define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ 214 | #define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ 215 | #define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ 216 | #define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ 217 | 218 | #define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ 219 | #define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ 220 | #define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 221 | only for High density Value line devices) */ 222 | 223 | #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ 224 | ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ 225 | ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ 226 | ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ 227 | ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ 228 | ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ 229 | ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ 230 | ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ 231 | ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ 232 | ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ 233 | ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ 234 | ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ 235 | ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ 236 | ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ 237 | ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ 238 | ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ 239 | ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ 240 | ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ 241 | ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ 242 | ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ 243 | ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ 244 | ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) 245 | 246 | /** 247 | * @} 248 | */ 249 | 250 | /** @defgroup GPIO_Port_Sources 251 | * @{ 252 | */ 253 | 254 | #define GPIO_PortSourceGPIOA ((uint8_t)0x00) 255 | #define GPIO_PortSourceGPIOB ((uint8_t)0x01) 256 | #define GPIO_PortSourceGPIOC ((uint8_t)0x02) 257 | #define GPIO_PortSourceGPIOD ((uint8_t)0x03) 258 | #define GPIO_PortSourceGPIOE ((uint8_t)0x04) 259 | #define GPIO_PortSourceGPIOF ((uint8_t)0x05) 260 | #define GPIO_PortSourceGPIOG ((uint8_t)0x06) 261 | #define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ 262 | ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ 263 | ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ 264 | ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ 265 | ((PORTSOURCE) == GPIO_PortSourceGPIOE)) 266 | 267 | #define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ 268 | ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ 269 | ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ 270 | ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ 271 | ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ 272 | ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ 273 | ((PORTSOURCE) == GPIO_PortSourceGPIOG)) 274 | 275 | /** 276 | * @} 277 | */ 278 | 279 | /** @defgroup GPIO_Pin_sources 280 | * @{ 281 | */ 282 | 283 | #define GPIO_PinSource0 ((uint8_t)0x00) 284 | #define GPIO_PinSource1 ((uint8_t)0x01) 285 | #define GPIO_PinSource2 ((uint8_t)0x02) 286 | #define GPIO_PinSource3 ((uint8_t)0x03) 287 | #define GPIO_PinSource4 ((uint8_t)0x04) 288 | #define GPIO_PinSource5 ((uint8_t)0x05) 289 | #define GPIO_PinSource6 ((uint8_t)0x06) 290 | #define GPIO_PinSource7 ((uint8_t)0x07) 291 | #define GPIO_PinSource8 ((uint8_t)0x08) 292 | #define GPIO_PinSource9 ((uint8_t)0x09) 293 | #define GPIO_PinSource10 ((uint8_t)0x0A) 294 | #define GPIO_PinSource11 ((uint8_t)0x0B) 295 | #define GPIO_PinSource12 ((uint8_t)0x0C) 296 | #define GPIO_PinSource13 ((uint8_t)0x0D) 297 | #define GPIO_PinSource14 ((uint8_t)0x0E) 298 | #define GPIO_PinSource15 ((uint8_t)0x0F) 299 | 300 | #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ 301 | ((PINSOURCE) == GPIO_PinSource1) || \ 302 | ((PINSOURCE) == GPIO_PinSource2) || \ 303 | ((PINSOURCE) == GPIO_PinSource3) || \ 304 | ((PINSOURCE) == GPIO_PinSource4) || \ 305 | ((PINSOURCE) == GPIO_PinSource5) || \ 306 | ((PINSOURCE) == GPIO_PinSource6) || \ 307 | ((PINSOURCE) == GPIO_PinSource7) || \ 308 | ((PINSOURCE) == GPIO_PinSource8) || \ 309 | ((PINSOURCE) == GPIO_PinSource9) || \ 310 | ((PINSOURCE) == GPIO_PinSource10) || \ 311 | ((PINSOURCE) == GPIO_PinSource11) || \ 312 | ((PINSOURCE) == GPIO_PinSource12) || \ 313 | ((PINSOURCE) == GPIO_PinSource13) || \ 314 | ((PINSOURCE) == GPIO_PinSource14) || \ 315 | ((PINSOURCE) == GPIO_PinSource15)) 316 | 317 | /** 318 | * @} 319 | */ 320 | 321 | /** @defgroup Ethernet_Media_Interface 322 | * @{ 323 | */ 324 | #define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) 325 | #define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) 326 | 327 | #define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ 328 | ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) 329 | 330 | /** 331 | * @} 332 | */ 333 | /** 334 | * @} 335 | */ 336 | 337 | /** @defgroup GPIO_Exported_Macros 338 | * @{ 339 | */ 340 | 341 | /** 342 | * @} 343 | */ 344 | 345 | /** @defgroup GPIO_Exported_Functions 346 | * @{ 347 | */ 348 | 349 | void GPIO_DeInit(GPIO_TypeDef* GPIOx); 350 | void GPIO_AFIODeInit(void); 351 | void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); 352 | void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); 353 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 354 | uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); 355 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 356 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); 357 | void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 358 | void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 359 | void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); 360 | void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); 361 | void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 362 | void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 363 | void GPIO_EventOutputCmd(FunctionalState NewState); 364 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); 365 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 366 | void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); 367 | 368 | #ifdef __cplusplus 369 | } 370 | #endif 371 | 372 | #endif /* __STM32F10x_GPIO_H */ 373 | /** 374 | * @} 375 | */ 376 | 377 | /** 378 | * @} 379 | */ 380 | 381 | /** 382 | * @} 383 | */ 384 | 385 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 386 | --------------------------------------------------------------------------------