├── .gitignore ├── LICENSE ├── README.md ├── boards ├── README.md ├── doc │ └── README.md ├── hbirdkit │ ├── Hummingbird EV KIT.pdf │ ├── pics │ │ ├── p1.jpg │ │ ├── p2.jpg │ │ ├── p3.jpg │ │ ├── p4.jpg │ │ ├── p5.jpg │ │ └── p6.jpg │ ├── 蜂鸟FPGA开发板和JTAG调试器介绍.pdf │ └── 蜂鸟FPGA开发板约束文件.pdf ├── nucleikit │ ├── pics │ │ ├── 1-1.jpg │ │ ├── 2-1.jpg │ │ ├── 2-2.jpg │ │ ├── 2-3.jpg │ │ ├── 3-1.jpg │ │ ├── 3-2.jpg │ │ ├── p1.jpg │ │ ├── p10.jpg │ │ ├── p2.jpg │ │ ├── p3.jpg │ │ ├── p4.jpg │ │ ├── p5.jpg │ │ ├── p6.jpg │ │ ├── p7.jpg │ │ ├── p8.jpg │ │ └── p9.jpg │ ├── 蜂鸟FPGA开发板光绘图.pdf │ ├── 蜂鸟FPGA开发板原理图.pdf │ ├── 蜂鸟FPGA开发板和JTAG调试器介绍.pdf │ └── 蜂鸟FPGA开发板约束文件.pdf └── perf-v │ └── README.md ├── book2pic.jpg ├── bookpic.jpg ├── doc ├── I2CMasterwithWISHBONEBusInterface-Documentation.pdf ├── README.md ├── SiFive-E3-Coreplex-v1.2.pdf ├── SiFive-E300-platform-reference-manual-v1.0.1.pdf ├── SiFive-E310-G000-manual-v1.0.1.pdf ├── riscv-debug-spec-0.11nov12.pdf ├── riscv-privileged-v1.10.pdf ├── riscv-spec-v2.2.pdf ├── 蜂鸟E203开源SoC简介.pdf ├── 蜂鸟E203开源内核简介.pdf └── 蜂鸟E203快速上手介绍.pdf ├── fpga ├── .gitignore ├── Makefile ├── README.md ├── artydevkit │ ├── .gitignore │ ├── Makefile │ ├── constrs │ │ ├── arty-config.xdc │ │ └── arty-master.xdc │ ├── prebuilt_mcs │ │ └── system.mcs │ ├── script │ │ ├── board.tcl │ │ ├── cfgmem.tcl │ │ ├── impl.tcl │ │ ├── init.tcl │ │ ├── init_setup.tcl │ │ ├── ip.tcl │ │ ├── prologue.tcl │ │ └── prologue_setup.tcl │ └── src │ │ ├── clkdivider.v │ │ ├── dummy.v │ │ └── system.org ├── common.mk ├── fpga_tb_top │ └── fpga_tb_top.v ├── hbirdkit │ ├── Makefile │ ├── constrs │ │ ├── nuclei-config.xdc │ │ └── nuclei-master.xdc │ ├── prebuilt_mcs │ │ └── system.mcs │ ├── script │ │ ├── board.tcl │ │ ├── cfgmem.tcl │ │ ├── impl.tcl │ │ ├── init.tcl │ │ ├── init_setup.tcl │ │ ├── ip.tcl │ │ ├── prologue.tcl │ │ └── prologue_setup.tcl │ └── src │ │ ├── clkdivider.v │ │ ├── dummy.v │ │ └── system.org └── nucleikit │ ├── .gitignore │ ├── Makefile │ ├── constrs │ ├── nuclei-config.xdc │ └── nuclei-master.xdc │ ├── prebuilt_mcs │ └── system.mcs │ ├── script │ ├── board.tcl │ ├── cfgmem.tcl │ ├── impl.tcl │ ├── init.tcl │ ├── init_setup.tcl │ ├── ip.tcl │ ├── prologue.tcl │ └── prologue_setup.tcl │ └── src │ ├── clkdivider.v │ ├── dummy.v │ └── system.org ├── prebuilt_tools └── README.md ├── riscv-tools ├── README.md ├── build-e200-spike-rvtests.sh ├── build.common ├── fpga_test4sim │ ├── coremark4sim │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── core_list_join.c │ │ ├── core_main.c │ │ ├── core_matrix.c │ │ ├── core_portme.c │ │ ├── core_portme.h │ │ ├── core_state.c │ │ ├── core_util.c │ │ ├── coremark.dump │ │ ├── coremark.h │ │ ├── coremark.verilog │ │ ├── coremark4sim │ │ ├── coremark4sim.dump │ │ └── coremark4sim.verilog │ ├── demo_gpio4sim │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── demo_gpio.c │ │ ├── demo_gpio.o │ │ ├── demo_gpio4sim │ │ └── demo_gpio4sim.verilog │ └── dhrystone4sim │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── dhry.h │ │ ├── dhry_1.c │ │ ├── dhry_1.o │ │ ├── dhry_2.c │ │ ├── dhry_2.o │ │ ├── dhry_irq.o │ │ ├── dhry_stubs.c │ │ ├── dhry_stubs.o │ │ ├── dhrystone.dump │ │ ├── dhrystone.verilog │ │ ├── dhrystone4sim │ │ ├── dhrystone4sim.dump │ │ └── dhrystone4sim.verilog ├── riscv-fesvr │ ├── .gitignore │ ├── COPYING │ ├── LICENSE │ ├── Makefile.in │ ├── README.md │ ├── aclocal.m4 │ ├── config.h.in │ ├── configure │ ├── configure.ac │ ├── fesvr │ │ ├── context.cc │ │ ├── context.h │ │ ├── debug_defines.h │ │ ├── device.cc │ │ ├── device.h │ │ ├── dtm.cc │ │ ├── dtm.h │ │ ├── dummy.cc │ │ ├── elf.h │ │ ├── elf2hex.cc │ │ ├── elfloader.cc │ │ ├── elfloader.h │ │ ├── encoding.h │ │ ├── fesvr.ac │ │ ├── fesvr.mk.in │ │ ├── fesvr.pc.in │ │ ├── htif.cc │ │ ├── htif.h │ │ ├── htif_hexwriter.cc │ │ ├── htif_hexwriter.h │ │ ├── htif_pthread.cc │ │ ├── htif_pthread.h │ │ ├── memif.cc │ │ ├── memif.h │ │ ├── option_parser.cc │ │ ├── option_parser.h │ │ ├── rfb.cc │ │ ├── rfb.h │ │ ├── syscall.cc │ │ ├── syscall.h │ │ ├── term.cc │ │ ├── term.h │ │ ├── tsi.cc │ │ └── tsi.h │ ├── riscv-fesvr.pc.in │ └── scripts │ │ ├── config.guess │ │ ├── config.sub │ │ ├── install.sh │ │ ├── mk-install-dirs.sh │ │ └── vcs-version.sh ├── riscv-isa-sim │ ├── .gitignore │ ├── LICENSE │ ├── Makefile.in │ ├── README.md │ ├── aclocal.m4 │ ├── config.h.in │ ├── configure │ ├── configure.ac │ ├── debug_rom │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── debug_rom.S │ │ ├── debug_rom.h │ │ ├── debug_rom_defines.h │ │ └── link.ld │ ├── dummy_rocc │ │ ├── dummy_rocc.ac │ │ ├── dummy_rocc.cc │ │ ├── dummy_rocc.mk.in │ │ └── dummy_rocc_test.c │ ├── riscv-dummy_rocc.pc.in │ ├── riscv-riscv.pc.in │ ├── riscv-softfloat.pc.in │ ├── riscv-spike.pc.in │ ├── riscv-spike_main.pc.in │ ├── riscv │ │ ├── cachesim.cc │ │ ├── cachesim.h │ │ ├── clint.cc │ │ ├── common.h │ │ ├── debug_defines.h │ │ ├── debug_module.cc │ │ ├── debug_module.h │ │ ├── decode.h │ │ ├── devices.cc │ │ ├── devices.h │ │ ├── disasm.h │ │ ├── encoding.h │ │ ├── execute.cc │ │ ├── extension.cc │ │ ├── extension.h │ │ ├── extensions.cc │ │ ├── gen_icache │ │ ├── insn_template.cc │ │ ├── insn_template.h │ │ ├── insns │ │ │ ├── add.h │ │ │ ├── addi.h │ │ │ ├── addiw.h │ │ │ ├── addw.h │ │ │ ├── amoadd_d.h │ │ │ ├── amoadd_w.h │ │ │ ├── amoand_d.h │ │ │ ├── amoand_w.h │ │ │ ├── amomax_d.h │ │ │ ├── amomax_w.h │ │ │ ├── amomaxu_d.h │ │ │ ├── amomaxu_w.h │ │ │ ├── amomin_d.h │ │ │ ├── amomin_w.h │ │ │ ├── amominu_d.h │ │ │ ├── amominu_w.h │ │ │ ├── amoor_d.h │ │ │ ├── amoor_w.h │ │ │ ├── amoswap_d.h │ │ │ ├── amoswap_w.h │ │ │ ├── amoxor_d.h │ │ │ ├── amoxor_w.h │ │ │ ├── and.h │ │ │ ├── andi.h │ │ │ ├── auipc.h │ │ │ ├── beq.h │ │ │ ├── bge.h │ │ │ ├── bgeu.h │ │ │ ├── blt.h │ │ │ ├── bltu.h │ │ │ ├── bne.h │ │ │ ├── c_add.h │ │ │ ├── c_addi.h │ │ │ ├── c_addi4spn.h │ │ │ ├── c_addw.h │ │ │ ├── c_and.h │ │ │ ├── c_andi.h │ │ │ ├── c_beqz.h │ │ │ ├── c_bnez.h │ │ │ ├── c_ebreak.h │ │ │ ├── c_fld.h │ │ │ ├── c_fldsp.h │ │ │ ├── c_flw.h │ │ │ ├── c_flwsp.h │ │ │ ├── c_fsd.h │ │ │ ├── c_fsdsp.h │ │ │ ├── c_fsw.h │ │ │ ├── c_fswsp.h │ │ │ ├── c_j.h │ │ │ ├── c_jal.h │ │ │ ├── c_jalr.h │ │ │ ├── c_jr.h │ │ │ ├── c_li.h │ │ │ ├── c_lui.h │ │ │ ├── c_lw.h │ │ │ ├── c_lwsp.h │ │ │ ├── c_mv.h │ │ │ ├── c_or.h │ │ │ ├── c_slli.h │ │ │ ├── c_srai.h │ │ │ ├── c_srli.h │ │ │ ├── c_sub.h │ │ │ ├── c_subw.h │ │ │ ├── c_sw.h │ │ │ ├── c_swsp.h │ │ │ ├── c_xor.h │ │ │ ├── csrrc.h │ │ │ ├── csrrci.h │ │ │ ├── csrrs.h │ │ │ ├── csrrsi.h │ │ │ ├── csrrw.h │ │ │ ├── csrrwi.h │ │ │ ├── div.h │ │ │ ├── divu.h │ │ │ ├── divuw.h │ │ │ ├── divw.h │ │ │ ├── dret.h │ │ │ ├── ebreak.h │ │ │ ├── ecall.h │ │ │ ├── fadd_d.h │ │ │ ├── fadd_s.h │ │ │ ├── fclass_d.h │ │ │ ├── fclass_s.h │ │ │ ├── fcvt_d_l.h │ │ │ ├── fcvt_d_lu.h │ │ │ ├── fcvt_d_s.h │ │ │ ├── fcvt_d_w.h │ │ │ ├── fcvt_d_wu.h │ │ │ ├── fcvt_l_d.h │ │ │ ├── fcvt_l_s.h │ │ │ ├── fcvt_lu_d.h │ │ │ ├── fcvt_lu_s.h │ │ │ ├── fcvt_s_d.h │ │ │ ├── fcvt_s_l.h │ │ │ ├── fcvt_s_lu.h │ │ │ ├── fcvt_s_w.h │ │ │ ├── fcvt_s_wu.h │ │ │ ├── fcvt_w_d.h │ │ │ ├── fcvt_w_s.h │ │ │ ├── fcvt_wu_d.h │ │ │ ├── fcvt_wu_s.h │ │ │ ├── fdiv_d.h │ │ │ ├── fdiv_s.h │ │ │ ├── fence.h │ │ │ ├── fence_i.h │ │ │ ├── feq_d.h │ │ │ ├── feq_s.h │ │ │ ├── fld.h │ │ │ ├── fle_d.h │ │ │ ├── fle_s.h │ │ │ ├── flt_d.h │ │ │ ├── flt_s.h │ │ │ ├── flw.h │ │ │ ├── fmadd_d.h │ │ │ ├── fmadd_s.h │ │ │ ├── fmax_d.h │ │ │ ├── fmax_s.h │ │ │ ├── fmin_d.h │ │ │ ├── fmin_s.h │ │ │ ├── fmsub_d.h │ │ │ ├── fmsub_s.h │ │ │ ├── fmul_d.h │ │ │ ├── fmul_s.h │ │ │ ├── fmv_d_x.h │ │ │ ├── fmv_w_x.h │ │ │ ├── fmv_x_d.h │ │ │ ├── fmv_x_w.h │ │ │ ├── fnmadd_d.h │ │ │ ├── fnmadd_s.h │ │ │ ├── fnmsub_d.h │ │ │ ├── fnmsub_s.h │ │ │ ├── fsd.h │ │ │ ├── fsgnj_d.h │ │ │ ├── fsgnj_s.h │ │ │ ├── fsgnjn_d.h │ │ │ ├── fsgnjn_s.h │ │ │ ├── fsgnjx_d.h │ │ │ ├── fsgnjx_s.h │ │ │ ├── fsqrt_d.h │ │ │ ├── fsqrt_s.h │ │ │ ├── fsub_d.h │ │ │ ├── fsub_s.h │ │ │ ├── fsw.h │ │ │ ├── jal.h │ │ │ ├── jalr.h │ │ │ ├── lb.h │ │ │ ├── lbu.h │ │ │ ├── ld.h │ │ │ ├── lh.h │ │ │ ├── lhu.h │ │ │ ├── lr_d.h │ │ │ ├── lr_w.h │ │ │ ├── lui.h │ │ │ ├── lw.h │ │ │ ├── lwu.h │ │ │ ├── mret.h │ │ │ ├── mul.h │ │ │ ├── mulh.h │ │ │ ├── mulhsu.h │ │ │ ├── mulhu.h │ │ │ ├── mulw.h │ │ │ ├── or.h │ │ │ ├── ori.h │ │ │ ├── rem.h │ │ │ ├── remu.h │ │ │ ├── remuw.h │ │ │ ├── remw.h │ │ │ ├── sb.h │ │ │ ├── sc_d.h │ │ │ ├── sc_w.h │ │ │ ├── sd.h │ │ │ ├── sfence_vma.h │ │ │ ├── sh.h │ │ │ ├── sll.h │ │ │ ├── slli.h │ │ │ ├── slliw.h │ │ │ ├── sllw.h │ │ │ ├── slt.h │ │ │ ├── slti.h │ │ │ ├── sltiu.h │ │ │ ├── sltu.h │ │ │ ├── sra.h │ │ │ ├── srai.h │ │ │ ├── sraiw.h │ │ │ ├── sraw.h │ │ │ ├── sret.h │ │ │ ├── srl.h │ │ │ ├── srli.h │ │ │ ├── srliw.h │ │ │ ├── srlw.h │ │ │ ├── sub.h │ │ │ ├── subw.h │ │ │ ├── sw.h │ │ │ ├── wfi.h │ │ │ ├── xor.h │ │ │ └── xori.h │ │ ├── interactive.cc │ │ ├── jtag_dtm.cc │ │ ├── jtag_dtm.h │ │ ├── memtracer.h │ │ ├── mmu.cc │ │ ├── mmu.h │ │ ├── mulhi.h │ │ ├── opcodes.h │ │ ├── processor.cc │ │ ├── processor.h │ │ ├── regnames.cc │ │ ├── remote_bitbang.cc │ │ ├── remote_bitbang.h │ │ ├── riscv.ac │ │ ├── riscv.mk.in │ │ ├── rocc.cc │ │ ├── rocc.h │ │ ├── rom.cc │ │ ├── sim.cc │ │ ├── sim.h │ │ ├── tracer.h │ │ ├── trap.cc │ │ └── trap.h │ ├── scripts │ │ ├── config.guess │ │ ├── config.sub │ │ ├── install.sh │ │ ├── mk-install-dirs.sh │ │ └── vcs-version.sh │ ├── softfloat │ │ ├── f32_add.c │ │ ├── f32_classify.c │ │ ├── f32_div.c │ │ ├── f32_eq.c │ │ ├── f32_eq_signaling.c │ │ ├── f32_isSignalingNaN.c │ │ ├── f32_le.c │ │ ├── f32_le_quiet.c │ │ ├── f32_lt.c │ │ ├── f32_lt_quiet.c │ │ ├── f32_mul.c │ │ ├── f32_mulAdd.c │ │ ├── f32_rem.c │ │ ├── f32_roundToInt.c │ │ ├── f32_sqrt.c │ │ ├── f32_sub.c │ │ ├── f32_to_f64.c │ │ ├── f32_to_i32.c │ │ ├── f32_to_i32_r_minMag.c │ │ ├── f32_to_i64.c │ │ ├── f32_to_i64_r_minMag.c │ │ ├── f32_to_ui32.c │ │ ├── f32_to_ui32_r_minMag.c │ │ ├── f32_to_ui64.c │ │ ├── f32_to_ui64_r_minMag.c │ │ ├── f64_add.c │ │ ├── f64_classify.c │ │ ├── f64_div.c │ │ ├── f64_eq.c │ │ ├── f64_eq_signaling.c │ │ ├── f64_isSignalingNaN.c │ │ ├── f64_le.c │ │ ├── f64_le_quiet.c │ │ ├── f64_lt.c │ │ ├── f64_lt_quiet.c │ │ ├── f64_mul.c │ │ ├── f64_mulAdd.c │ │ ├── f64_rem.c │ │ ├── f64_roundToInt.c │ │ ├── f64_sqrt.c │ │ ├── f64_sub.c │ │ ├── f64_to_f32.c │ │ ├── f64_to_i32.c │ │ ├── f64_to_i32_r_minMag.c │ │ ├── f64_to_i64.c │ │ ├── f64_to_i64_r_minMag.c │ │ ├── f64_to_ui32.c │ │ ├── f64_to_ui32_r_minMag.c │ │ ├── f64_to_ui64.c │ │ ├── f64_to_ui64_r_minMag.c │ │ ├── i32_to_f32.c │ │ ├── i32_to_f64.c │ │ ├── i64_to_f32.c │ │ ├── i64_to_f64.c │ │ ├── internals.h │ │ ├── platform.h │ │ ├── primitiveTypes.h │ │ ├── primitives.h │ │ ├── s_add128.c │ │ ├── s_addCarryM.c │ │ ├── s_addComplCarryM.c │ │ ├── s_addM.c │ │ ├── s_addMagsF32.c │ │ ├── s_addMagsF64.c │ │ ├── s_approxRecip32_1.c │ │ ├── s_approxRecipSqrt32_1.c │ │ ├── s_commonNaNToF32UI.c │ │ ├── s_commonNaNToF64UI.c │ │ ├── s_compare96M.c │ │ ├── s_countLeadingZeros32.c │ │ ├── s_countLeadingZeros64.c │ │ ├── s_countLeadingZeros8.c │ │ ├── s_f32UIToCommonNaN.c │ │ ├── s_f64UIToCommonNaN.c │ │ ├── s_mul64To128.c │ │ ├── s_mulAddF32.c │ │ ├── s_mulAddF64.c │ │ ├── s_negXM.c │ │ ├── s_normRoundPackToF32.c │ │ ├── s_normRoundPackToF64.c │ │ ├── s_normSubnormalF32Sig.c │ │ ├── s_normSubnormalF64Sig.c │ │ ├── s_propagateNaNF32UI.c │ │ ├── s_propagateNaNF64UI.c │ │ ├── s_remStepMBy32.c │ │ ├── s_roundPackMToI64.c │ │ ├── s_roundPackMToUI64.c │ │ ├── s_roundPackToF32.c │ │ ├── s_roundPackToF64.c │ │ ├── s_roundPackToI32.c │ │ ├── s_roundPackToI64.c │ │ ├── s_roundPackToUI32.c │ │ ├── s_roundPackToUI64.c │ │ ├── s_shiftRightJam128.c │ │ ├── s_shiftRightJam32.c │ │ ├── s_shiftRightJam64.c │ │ ├── s_shiftRightJam64Extra.c │ │ ├── s_shortShiftLeft64To96M.c │ │ ├── s_shortShiftLeftM.c │ │ ├── s_shortShiftRightExtendM.c │ │ ├── s_shortShiftRightJam64.c │ │ ├── s_shortShiftRightJam64Extra.c │ │ ├── s_shortShiftRightJamM.c │ │ ├── s_shortShiftRightM.c │ │ ├── s_sub128.c │ │ ├── s_subM.c │ │ ├── s_subMagsF32.c │ │ ├── s_subMagsF64.c │ │ ├── softfloat.ac │ │ ├── softfloat.h │ │ ├── softfloat.mk.in │ │ ├── softfloat_raiseFlags.c │ │ ├── softfloat_state.c │ │ ├── softfloat_types.h │ │ ├── specialize.h │ │ ├── ui32_to_f32.c │ │ ├── ui32_to_f64.c │ │ ├── ui64_to_f32.c │ │ └── ui64_to_f64.c │ ├── spike_main │ │ ├── disasm.cc │ │ ├── spike-dasm.cc │ │ ├── spike.cc │ │ ├── spike_main.ac │ │ ├── spike_main.mk.in │ │ ├── termios-xspike.cc │ │ └── xspike.cc │ └── tests │ │ ├── ebreak.py │ │ ├── ebreak.s │ │ └── testlib.py ├── riscv-tests │ ├── .gitignore │ ├── LICENSE │ ├── Makefile.in │ ├── README.md │ ├── benchmarks │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── clean.sh │ │ ├── common │ │ │ ├── crt.S │ │ │ ├── syscalls.c │ │ │ ├── test.ld │ │ │ └── util.h │ │ ├── dhrystone │ │ │ ├── dhrystone.c │ │ │ ├── dhrystone.h │ │ │ └── dhrystone_main.c │ │ ├── fpu-perf │ │ │ ├── fpu-perf.c │ │ │ └── fpu-perf.h │ │ ├── generated │ │ │ ├── coremark.riscv │ │ │ ├── coremark.riscv.dump │ │ │ ├── dhrystone.riscv │ │ │ ├── dhrystone.riscv.dump │ │ │ ├── fpu-perf.riscv │ │ │ ├── fpu-perf.riscv.dump │ │ │ ├── fpu-perf_nofpu.riscv │ │ │ ├── fpu-perf_nofpu.riscv.dump │ │ │ ├── fpu-perf_nofpu.riscv.rpt │ │ │ ├── median.riscv │ │ │ ├── median.riscv.dump │ │ │ ├── mm.riscv │ │ │ ├── mm.riscv.dump │ │ │ ├── mt-matmul.riscv │ │ │ ├── mt-matmul.riscv.dump │ │ │ ├── mt-vvadd.riscv │ │ │ ├── mt-vvadd.riscv.dump │ │ │ ├── multiply.riscv │ │ │ ├── multiply.riscv.dump │ │ │ ├── pmp.riscv │ │ │ ├── pmp.riscv.dump │ │ │ ├── qsort.riscv │ │ │ ├── qsort.riscv.dump │ │ │ ├── rsort.riscv │ │ │ ├── rsort.riscv.dump │ │ │ ├── spmv.riscv │ │ │ ├── spmv.riscv.dump │ │ │ ├── towers.riscv │ │ │ ├── towers.riscv.dump │ │ │ ├── vvadd.riscv │ │ │ └── vvadd.riscv.dump │ │ ├── median │ │ │ ├── dataset1.h │ │ │ ├── median.c │ │ │ ├── median.h │ │ │ ├── median_gendata.pl │ │ │ └── median_main.c │ │ ├── mm │ │ │ ├── common.h │ │ │ ├── gen.scala │ │ │ ├── mm.c │ │ │ ├── mm_main.c │ │ │ └── rb.h │ │ ├── mt-matmul │ │ │ ├── dataset.h │ │ │ ├── matmul.c │ │ │ ├── matmul_gendata.pl │ │ │ └── mt-matmul.c │ │ ├── mt-vvadd │ │ │ ├── dataset.h │ │ │ ├── mt-vvadd.c │ │ │ ├── vvadd.c │ │ │ └── vvadd_gendata.pl │ │ ├── multiply │ │ │ ├── dataset1.h │ │ │ ├── multiply.c │ │ │ ├── multiply.h │ │ │ ├── multiply_gendata.pl │ │ │ └── multiply_main.c │ │ ├── qsort │ │ │ ├── dataset1.h │ │ │ ├── qsort_gendata.pl │ │ │ └── qsort_main.c │ │ ├── readme.txt │ │ ├── regen.sh │ │ ├── rsort │ │ │ ├── dataset1.h │ │ │ └── rsort.c │ │ ├── spmv │ │ │ ├── dataset1.h │ │ │ ├── spmv_gendata.scala │ │ │ └── spmv_main.c │ │ ├── towers │ │ │ └── towers_main.c │ │ └── vvadd │ │ │ ├── dataset1-large.h │ │ │ ├── dataset1.h │ │ │ ├── vvadd_gendata.pl │ │ │ └── vvadd_main.c │ ├── configure │ ├── configure.ac │ ├── debug │ │ ├── Makefile │ │ ├── README.md │ │ ├── gdbserver.py │ │ ├── openocd.py │ │ ├── programs │ │ │ ├── checksum.c │ │ │ ├── debug.c │ │ │ ├── encoding.h │ │ │ ├── entry.S │ │ │ ├── infinite_loop.S │ │ │ ├── init.c │ │ │ ├── mprv.S │ │ │ ├── priv.S │ │ │ ├── regs.S │ │ │ ├── start.S │ │ │ ├── step.S │ │ │ ├── tiny-malloc.c │ │ │ └── trigger.S │ │ ├── pylint.rc │ │ ├── requirements.txt │ │ ├── targets.py │ │ ├── targets │ │ │ ├── RISC-V │ │ │ │ ├── spike32.cfg │ │ │ │ ├── spike32.lds │ │ │ │ ├── spike32.py │ │ │ │ ├── spike64.cfg │ │ │ │ ├── spike64.lds │ │ │ │ └── spike64.py │ │ │ └── SiFive │ │ │ │ ├── Freedom │ │ │ │ ├── E300.py │ │ │ │ ├── E300Sim.py │ │ │ │ ├── Freedom.cfg │ │ │ │ ├── Freedom.lds │ │ │ │ ├── U500.py │ │ │ │ └── U500Sim.py │ │ │ │ ├── HiFive1.cfg │ │ │ │ ├── HiFive1.lds │ │ │ │ └── HiFive1.py │ │ └── testlib.py │ ├── env │ │ ├── LICENSE │ │ ├── encoding.h │ │ ├── p │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── pm │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ ├── pt │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ └── v │ │ │ ├── entry.S │ │ │ ├── link.ld │ │ │ ├── riscv_test.h │ │ │ ├── string.c │ │ │ └── vm.c │ ├── isa │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── clean.sh │ │ ├── generated │ │ │ ├── rv32mi-p-breakpoint │ │ │ ├── rv32mi-p-breakpoint.dump │ │ │ ├── rv32mi-p-breakpoint.verilog │ │ │ ├── rv32mi-p-csr │ │ │ ├── rv32mi-p-csr.dump │ │ │ ├── rv32mi-p-csr.verilog │ │ │ ├── rv32mi-p-i2c │ │ │ ├── rv32mi-p-i2c.dump │ │ │ ├── rv32mi-p-i2c.verilog │ │ │ ├── rv32mi-p-illegal │ │ │ ├── rv32mi-p-illegal.dump │ │ │ ├── rv32mi-p-illegal.verilog │ │ │ ├── rv32mi-p-ma_addr │ │ │ ├── rv32mi-p-ma_addr.dump │ │ │ ├── rv32mi-p-ma_addr.verilog │ │ │ ├── rv32mi-p-ma_fetch │ │ │ ├── rv32mi-p-ma_fetch.dump │ │ │ ├── rv32mi-p-ma_fetch.verilog │ │ │ ├── rv32mi-p-mcsr │ │ │ ├── rv32mi-p-mcsr.dump │ │ │ ├── rv32mi-p-mcsr.verilog │ │ │ ├── rv32mi-p-sbreak │ │ │ ├── rv32mi-p-sbreak.dump │ │ │ ├── rv32mi-p-sbreak.verilog │ │ │ ├── rv32mi-p-scall │ │ │ ├── rv32mi-p-scall.dump │ │ │ ├── rv32mi-p-scall.verilog │ │ │ ├── rv32mi-p-shamt │ │ │ ├── rv32mi-p-shamt.dump │ │ │ ├── rv32mi-p-shamt.verilog │ │ │ ├── rv32mi-p-soc │ │ │ ├── rv32mi-p-soc.dump │ │ │ ├── rv32mi-p-soc.log │ │ │ ├── rv32mi-p-soc.verilog │ │ │ ├── rv32ua-p-amoadd_w │ │ │ ├── rv32ua-p-amoadd_w.dump │ │ │ ├── rv32ua-p-amoadd_w.verilog │ │ │ ├── rv32ua-p-amoand_w │ │ │ ├── rv32ua-p-amoand_w.dump │ │ │ ├── rv32ua-p-amoand_w.verilog │ │ │ ├── rv32ua-p-amomax_w │ │ │ ├── rv32ua-p-amomax_w.dump │ │ │ ├── rv32ua-p-amomax_w.verilog │ │ │ ├── rv32ua-p-amomaxu_w │ │ │ ├── rv32ua-p-amomaxu_w.dump │ │ │ ├── rv32ua-p-amomaxu_w.verilog │ │ │ ├── rv32ua-p-amomin_w │ │ │ ├── rv32ua-p-amomin_w.dump │ │ │ ├── rv32ua-p-amomin_w.verilog │ │ │ ├── rv32ua-p-amominu_w │ │ │ ├── rv32ua-p-amominu_w.dump │ │ │ ├── rv32ua-p-amominu_w.verilog │ │ │ ├── rv32ua-p-amoor_w │ │ │ ├── rv32ua-p-amoor_w.dump │ │ │ ├── rv32ua-p-amoor_w.verilog │ │ │ ├── rv32ua-p-amoswap_w │ │ │ ├── rv32ua-p-amoswap_w.dump │ │ │ ├── rv32ua-p-amoswap_w.verilog │ │ │ ├── rv32ua-p-amoxor_w │ │ │ ├── rv32ua-p-amoxor_w.dump │ │ │ ├── rv32ua-p-amoxor_w.verilog │ │ │ ├── rv32ua-p-lrsc │ │ │ ├── rv32ua-p-lrsc.dump │ │ │ ├── rv32ua-p-lrsc.verilog │ │ │ ├── rv32uc-p-rvc │ │ │ ├── rv32uc-p-rvc.dump │ │ │ ├── rv32uc-p-rvc.verilog │ │ │ ├── rv32ud-p-fadd │ │ │ ├── rv32ud-p-fadd.dump │ │ │ ├── rv32ud-p-fadd.verilog │ │ │ ├── rv32ud-p-fclass │ │ │ ├── rv32ud-p-fclass.dump │ │ │ ├── rv32ud-p-fclass.verilog │ │ │ ├── rv32ud-p-fcmp │ │ │ ├── rv32ud-p-fcmp.dump │ │ │ ├── rv32ud-p-fcmp.verilog │ │ │ ├── rv32ud-p-fcvt │ │ │ ├── rv32ud-p-fcvt.dump │ │ │ ├── rv32ud-p-fcvt.verilog │ │ │ ├── rv32ud-p-fcvt_w │ │ │ ├── rv32ud-p-fcvt_w.dump │ │ │ ├── rv32ud-p-fcvt_w.verilog │ │ │ ├── rv32ud-p-fdiv │ │ │ ├── rv32ud-p-fdiv.dump │ │ │ ├── rv32ud-p-fdiv.verilog │ │ │ ├── rv32ud-p-fmadd │ │ │ ├── rv32ud-p-fmadd.dump │ │ │ ├── rv32ud-p-fmadd.verilog │ │ │ ├── rv32ud-p-fmin │ │ │ ├── rv32ud-p-fmin.dump │ │ │ ├── rv32ud-p-fmin.verilog │ │ │ ├── rv32ud-p-ldst │ │ │ ├── rv32ud-p-ldst.dump │ │ │ ├── rv32ud-p-ldst.verilog │ │ │ ├── rv32ud-p-move │ │ │ ├── rv32ud-p-move.dump │ │ │ ├── rv32ud-p-move.verilog │ │ │ ├── rv32ud-p-recoding │ │ │ ├── rv32ud-p-recoding.dump │ │ │ ├── rv32ud-p-recoding.verilog │ │ │ ├── rv32ud-p-structural │ │ │ ├── rv32ud-p-structural.dump │ │ │ ├── rv32ud-p-structural.verilog │ │ │ ├── rv32uf-p-bpu_wait │ │ │ ├── rv32uf-p-bpu_wait.dump │ │ │ ├── rv32uf-p-bpu_wait.verilog │ │ │ ├── rv32uf-p-bus │ │ │ ├── rv32uf-p-bus.dump │ │ │ ├── rv32uf-p-bus.verilog │ │ │ ├── rv32uf-p-ecc │ │ │ ├── rv32uf-p-ecc.dump │ │ │ ├── rv32uf-p-ecc.verilog │ │ │ ├── rv32uf-p-fadd │ │ │ ├── rv32uf-p-fadd.dump │ │ │ ├── rv32uf-p-fadd.verilog │ │ │ ├── rv32uf-p-fclass │ │ │ ├── rv32uf-p-fclass.dump │ │ │ ├── rv32uf-p-fclass.verilog │ │ │ ├── rv32uf-p-fcmp │ │ │ ├── rv32uf-p-fcmp.dump │ │ │ ├── rv32uf-p-fcmp.verilog │ │ │ ├── rv32uf-p-fcvt │ │ │ ├── rv32uf-p-fcvt.dump │ │ │ ├── rv32uf-p-fcvt.verilog │ │ │ ├── rv32uf-p-fcvt_w │ │ │ ├── rv32uf-p-fcvt_w.dump │ │ │ ├── rv32uf-p-fcvt_w.verilog │ │ │ ├── rv32uf-p-fdiv │ │ │ ├── rv32uf-p-fdiv.dump │ │ │ ├── rv32uf-p-fdiv.verilog │ │ │ ├── rv32uf-p-fmadd │ │ │ ├── rv32uf-p-fmadd.dump │ │ │ ├── rv32uf-p-fmadd.verilog │ │ │ ├── rv32uf-p-fmin │ │ │ ├── rv32uf-p-fmin.dump │ │ │ ├── rv32uf-p-fmin.verilog │ │ │ ├── rv32uf-p-ldst │ │ │ ├── rv32uf-p-ldst.dump │ │ │ ├── rv32uf-p-ldst.verilog │ │ │ ├── rv32uf-p-lockstep │ │ │ ├── rv32uf-p-lockstep.dump │ │ │ ├── rv32uf-p-lockstep.verilog │ │ │ ├── rv32uf-p-move │ │ │ ├── rv32uf-p-move.dump │ │ │ ├── rv32uf-p-move.verilog │ │ │ ├── rv32uf-p-recoding │ │ │ ├── rv32uf-p-recoding.dump │ │ │ ├── rv32uf-p-recoding.verilog │ │ │ ├── rv32uf-p-wfi │ │ │ ├── rv32uf-p-wfi.dump │ │ │ ├── rv32uf-p-wfi.verilog │ │ │ ├── rv32ui-p-add │ │ │ ├── rv32ui-p-add.dump │ │ │ ├── rv32ui-p-add.verilog │ │ │ ├── rv32ui-p-addi │ │ │ ├── rv32ui-p-addi.dump │ │ │ ├── rv32ui-p-addi.verilog │ │ │ ├── rv32ui-p-and │ │ │ ├── rv32ui-p-and.dump │ │ │ ├── rv32ui-p-and.verilog │ │ │ ├── rv32ui-p-andi │ │ │ ├── rv32ui-p-andi.dump │ │ │ ├── rv32ui-p-andi.verilog │ │ │ ├── rv32ui-p-auipc │ │ │ ├── rv32ui-p-auipc.dump │ │ │ ├── rv32ui-p-auipc.verilog │ │ │ ├── rv32ui-p-beq │ │ │ ├── rv32ui-p-beq.dump │ │ │ ├── rv32ui-p-beq.verilog │ │ │ ├── rv32ui-p-bge │ │ │ ├── rv32ui-p-bge.dump │ │ │ ├── rv32ui-p-bge.verilog │ │ │ ├── rv32ui-p-bgeu │ │ │ ├── rv32ui-p-bgeu.dump │ │ │ ├── rv32ui-p-bgeu.verilog │ │ │ ├── rv32ui-p-blt │ │ │ ├── rv32ui-p-blt.dump │ │ │ ├── rv32ui-p-blt.verilog │ │ │ ├── rv32ui-p-bltu │ │ │ ├── rv32ui-p-bltu.dump │ │ │ ├── rv32ui-p-bltu.verilog │ │ │ ├── rv32ui-p-bne │ │ │ ├── rv32ui-p-bne.dump │ │ │ ├── rv32ui-p-bne.verilog │ │ │ ├── rv32ui-p-fence_i │ │ │ ├── rv32ui-p-fence_i.dump │ │ │ ├── rv32ui-p-fence_i.verilog │ │ │ ├── rv32ui-p-jal │ │ │ ├── rv32ui-p-jal.dump │ │ │ ├── rv32ui-p-jal.verilog │ │ │ ├── rv32ui-p-jalr │ │ │ ├── rv32ui-p-jalr.dump │ │ │ ├── rv32ui-p-jalr.verilog │ │ │ ├── rv32ui-p-lb │ │ │ ├── rv32ui-p-lb.dump │ │ │ ├── rv32ui-p-lb.verilog │ │ │ ├── rv32ui-p-lbu │ │ │ ├── rv32ui-p-lbu.dump │ │ │ ├── rv32ui-p-lbu.verilog │ │ │ ├── rv32ui-p-lh │ │ │ ├── rv32ui-p-lh.dump │ │ │ ├── rv32ui-p-lh.verilog │ │ │ ├── rv32ui-p-lhu │ │ │ ├── rv32ui-p-lhu.dump │ │ │ ├── rv32ui-p-lhu.verilog │ │ │ ├── rv32ui-p-lui │ │ │ ├── rv32ui-p-lui.dump │ │ │ ├── rv32ui-p-lui.verilog │ │ │ ├── rv32ui-p-lw │ │ │ ├── rv32ui-p-lw.dump │ │ │ ├── rv32ui-p-lw.verilog │ │ │ ├── rv32ui-p-or │ │ │ ├── rv32ui-p-or.dump │ │ │ ├── rv32ui-p-or.verilog │ │ │ ├── rv32ui-p-ori │ │ │ ├── rv32ui-p-ori.dump │ │ │ ├── rv32ui-p-ori.verilog │ │ │ ├── rv32ui-p-sb │ │ │ ├── rv32ui-p-sb.dump │ │ │ ├── rv32ui-p-sb.verilog │ │ │ ├── rv32ui-p-sh │ │ │ ├── rv32ui-p-sh.dump │ │ │ ├── rv32ui-p-sh.verilog │ │ │ ├── rv32ui-p-simple │ │ │ ├── rv32ui-p-simple.dump │ │ │ ├── rv32ui-p-simple.verilog │ │ │ ├── rv32ui-p-sll │ │ │ ├── rv32ui-p-sll.dump │ │ │ ├── rv32ui-p-sll.verilog │ │ │ ├── rv32ui-p-slli │ │ │ ├── rv32ui-p-slli.dump │ │ │ ├── rv32ui-p-slli.verilog │ │ │ ├── rv32ui-p-slt │ │ │ ├── rv32ui-p-slt.dump │ │ │ ├── rv32ui-p-slt.verilog │ │ │ ├── rv32ui-p-slti │ │ │ ├── rv32ui-p-slti.dump │ │ │ ├── rv32ui-p-slti.verilog │ │ │ ├── rv32ui-p-sltiu │ │ │ ├── rv32ui-p-sltiu.dump │ │ │ ├── rv32ui-p-sltiu.verilog │ │ │ ├── rv32ui-p-sltu │ │ │ ├── rv32ui-p-sltu.dump │ │ │ ├── rv32ui-p-sltu.verilog │ │ │ ├── rv32ui-p-sra │ │ │ ├── rv32ui-p-sra.dump │ │ │ ├── rv32ui-p-sra.verilog │ │ │ ├── rv32ui-p-srai │ │ │ ├── rv32ui-p-srai.dump │ │ │ ├── rv32ui-p-srai.verilog │ │ │ ├── rv32ui-p-srl │ │ │ ├── rv32ui-p-srl.dump │ │ │ ├── rv32ui-p-srl.verilog │ │ │ ├── rv32ui-p-srli │ │ │ ├── rv32ui-p-srli.dump │ │ │ ├── rv32ui-p-srli.verilog │ │ │ ├── rv32ui-p-sub │ │ │ ├── rv32ui-p-sub.dump │ │ │ ├── rv32ui-p-sub.verilog │ │ │ ├── rv32ui-p-sw │ │ │ ├── rv32ui-p-sw.dump │ │ │ ├── rv32ui-p-sw.verilog │ │ │ ├── rv32ui-p-xor │ │ │ ├── rv32ui-p-xor.dump │ │ │ ├── rv32ui-p-xor.verilog │ │ │ ├── rv32ui-p-xori │ │ │ ├── rv32ui-p-xori.dump │ │ │ ├── rv32ui-p-xori.verilog │ │ │ ├── rv32um-p-div │ │ │ ├── rv32um-p-div.dump │ │ │ ├── rv32um-p-div.verilog │ │ │ ├── rv32um-p-divu │ │ │ ├── rv32um-p-divu.dump │ │ │ ├── rv32um-p-divu.verilog │ │ │ ├── rv32um-p-mul │ │ │ ├── rv32um-p-mul.dump │ │ │ ├── rv32um-p-mul.verilog │ │ │ ├── rv32um-p-mulh │ │ │ ├── rv32um-p-mulh.dump │ │ │ ├── rv32um-p-mulh.verilog │ │ │ ├── rv32um-p-mulhsu │ │ │ ├── rv32um-p-mulhsu.dump │ │ │ ├── rv32um-p-mulhsu.verilog │ │ │ ├── rv32um-p-mulhu │ │ │ ├── rv32um-p-mulhu.dump │ │ │ ├── rv32um-p-mulhu.verilog │ │ │ ├── rv32um-p-rem │ │ │ ├── rv32um-p-rem.dump │ │ │ ├── rv32um-p-rem.verilog │ │ │ ├── rv32um-p-remu │ │ │ ├── rv32um-p-remu.dump │ │ │ └── rv32um-p-remu.verilog │ │ ├── macros │ │ │ └── scalar │ │ │ │ └── test_macros.h │ │ ├── pos_proc.sh │ │ ├── regen.sh │ │ ├── rv32mi │ │ │ ├── Makefrag │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── i2c.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ ├── shamt.S │ │ │ └── soc.S │ │ ├── rv32si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ ├── rv32ua │ │ │ ├── Makefrag │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ ├── rv32uc │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ ├── rv32ud │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── structural.S │ │ ├── rv32uf │ │ │ ├── Makefrag │ │ │ ├── bpu_wait.S │ │ │ ├── bus.S │ │ │ ├── ecc.S │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── lockstep.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── wfi.S │ │ ├── rv32ui │ │ │ ├── Makefrag │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── sub.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ │ ├── rv32um │ │ │ ├── Makefrag │ │ │ ├── div.S │ │ │ ├── divu.S │ │ │ ├── mul.S │ │ │ ├── mulh.S │ │ │ ├── mulhsu.S │ │ │ ├── mulhu.S │ │ │ ├── rem.S │ │ │ └── remu.S │ │ ├── rv64mi │ │ │ ├── Makefrag │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── i2c.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── soc.S │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ ├── rv64ua │ │ │ ├── Makefrag │ │ │ ├── amoadd_d.S │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_d.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_d.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_d.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_d.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_d.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_d.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_d.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_d.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ ├── rv64uc │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ ├── rv64ud │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── structural.S │ │ ├── rv64uf │ │ │ ├── Makefrag │ │ │ ├── bpu_wait.S │ │ │ ├── bus.S │ │ │ ├── ecc.S │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── lockstep.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── wfi.S │ │ ├── rv64ui │ │ │ ├── Makefrag │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── addiw.S │ │ │ ├── addw.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── ld.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── lwu.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sd.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slliw.S │ │ │ ├── sllw.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── sraiw.S │ │ │ ├── sraw.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── srliw.S │ │ │ ├── srlw.S │ │ │ ├── sub.S │ │ │ ├── subw.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ │ └── rv64um │ │ │ ├── Makefrag │ │ │ ├── div.S │ │ │ ├── divu.S │ │ │ ├── divuw.S │ │ │ ├── divw.S │ │ │ ├── mul.S │ │ │ ├── mulh.S │ │ │ ├── mulhsu.S │ │ │ ├── mulhu.S │ │ │ ├── mulw.S │ │ │ ├── rem.S │ │ │ ├── remu.S │ │ │ ├── remuw.S │ │ │ └── remw.S │ └── mt │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── ad_matmul.c │ │ ├── ae_matmul.c │ │ ├── af_matmul.c │ │ ├── ag_matmul.c │ │ ├── ai_matmul.c │ │ ├── ak_matmul.c │ │ ├── al_matmul.c │ │ ├── am_matmul.c │ │ ├── an_matmul.c │ │ ├── ap_matmul.c │ │ ├── aq_matmul.c │ │ ├── ar_matmul.c │ │ ├── at_matmul.c │ │ ├── av_matmul.c │ │ ├── ay_matmul.c │ │ ├── az_matmul.c │ │ ├── bb_matmul.c │ │ ├── bc_matmul.c │ │ ├── bf_matmul.c │ │ ├── bh_matmul.c │ │ ├── bj_matmul.c │ │ ├── bk_matmul.c │ │ ├── bm_matmul.c │ │ ├── bo_matmul.c │ │ ├── br_matmul.c │ │ ├── bs_matmul.c │ │ ├── ce_matmul.c │ │ ├── cf_matmul.c │ │ ├── cg_matmul.c │ │ ├── ci_matmul.c │ │ ├── ck_matmul.c │ │ ├── cl_matmul.c │ │ ├── cm_matmul.c │ │ ├── cs_matmul.c │ │ ├── cv_matmul.c │ │ ├── cy_matmul.c │ │ ├── dc_matmul.c │ │ ├── df_matmul.c │ │ ├── dm_matmul.c │ │ ├── do_matmul.c │ │ ├── dr_matmul.c │ │ ├── ds_matmul.c │ │ ├── du_matmul.c │ │ ├── dv_matmul.c │ │ ├── vvadd0.c │ │ ├── vvadd1.c │ │ ├── vvadd2.c │ │ ├── vvadd3.c │ │ └── vvadd4.c └── riscv-torture │ ├── .gitignore │ ├── .gitmodules │ ├── Makefile │ ├── README │ ├── config │ ├── calu_alu.config │ ├── default.config │ ├── long_vec.config │ └── short_vec.config │ ├── env │ ├── LICENSE │ ├── encoding.h │ ├── p │ │ ├── link.ld │ │ └── riscv_test.h │ ├── pm │ │ ├── link.ld │ │ └── riscv_test.h │ ├── pt │ │ ├── link.ld │ │ └── riscv_test.h │ └── v │ │ ├── entry.S │ │ ├── link.ld │ │ ├── riscv_test.h │ │ ├── string.c │ │ └── vm.c │ ├── fileop │ └── src │ │ └── main │ │ └── scala │ │ └── main.scala │ ├── gen100.sh │ ├── generator │ └── src │ │ └── main │ │ └── scala │ │ ├── DataChunk.scala │ │ ├── HWReg.scala │ │ ├── HWRegPool.scala │ │ ├── HWShadowReg.scala │ │ ├── Inst.scala │ │ ├── InstSeq.scala │ │ ├── Mem.scala │ │ ├── Operand.scala │ │ ├── Prog.scala │ │ ├── Rand.scala │ │ ├── SeqALU.scala │ │ ├── SeqBranch.scala │ │ ├── SeqCALU.scala │ │ ├── SeqCBranch.scala │ │ ├── SeqCMem.scala │ │ ├── SeqFDiv.scala │ │ ├── SeqFPMem.scala │ │ ├── SeqFPU.scala │ │ ├── SeqFaX.scala │ │ ├── SeqMem.scala │ │ ├── SeqSeq.scala │ │ ├── SeqVALU.scala │ │ ├── SeqVMem.scala │ │ ├── SeqVOnly.scala │ │ ├── SeqVPop.scala │ │ ├── SeqVec.scala │ │ ├── VFInstSeq.scala │ │ └── main.scala │ ├── overnight │ ├── lib │ │ └── mail.jar │ └── src │ │ └── main │ │ └── scala │ │ └── main.scala │ ├── project │ ├── build.properties │ └── build.scala │ ├── sbt-launch.jar │ └── testrun │ └── src │ └── main │ └── scala │ └── main.scala ├── rtl └── e203 │ ├── core │ ├── config.v │ ├── e203_biu.v │ ├── e203_clk_ctrl.v │ ├── e203_clkgate.v │ ├── e203_core.v │ ├── e203_cpu.v │ ├── e203_cpu_top.v │ ├── e203_defines.v │ ├── e203_dtcm_ctrl.v │ ├── e203_dtcm_ram.v │ ├── e203_extend_csr.v │ ├── e203_exu.v │ ├── e203_exu_alu.v │ ├── e203_exu_alu_bjp.v │ ├── e203_exu_alu_csrctrl.v │ ├── e203_exu_alu_dpath.v │ ├── e203_exu_alu_lsuagu.v │ ├── e203_exu_alu_muldiv.v │ ├── e203_exu_alu_rglr.v │ ├── e203_exu_branchslv.v │ ├── e203_exu_commit.v │ ├── e203_exu_csr.v │ ├── e203_exu_decode.v │ ├── e203_exu_disp.v │ ├── e203_exu_excp.v │ ├── e203_exu_longpwbck.v │ ├── e203_exu_oitf.v │ ├── e203_exu_regfile.v │ ├── e203_exu_wbck.v │ ├── e203_ifu.v │ ├── e203_ifu_ifetch.v │ ├── e203_ifu_ift2icb.v │ ├── e203_ifu_litebpu.v │ ├── e203_ifu_minidec.v │ ├── e203_irq_sync.v │ ├── e203_itcm_ctrl.v │ ├── e203_itcm_ram.v │ ├── e203_lsu.v │ ├── e203_lsu_ctrl.v │ ├── e203_reset_ctrl.v │ └── e203_srams.v │ ├── debug │ ├── sirv_debug_csr.v │ ├── sirv_debug_module.v │ ├── sirv_debug_ram.v │ ├── sirv_debug_rom.v │ └── sirv_jtag_dtm.v │ ├── fab │ ├── sirv_icb1to16_bus.v │ ├── sirv_icb1to2_bus.v │ └── sirv_icb1to8_bus.v │ ├── general │ ├── sirv_1cyc_sram_ctrl.v │ ├── sirv_gnrl_bufs.v │ ├── sirv_gnrl_dffs.v │ ├── sirv_gnrl_icbs.v │ ├── sirv_gnrl_ram.v │ ├── sirv_gnrl_xchecker.v │ ├── sirv_sim_ram.v │ └── sirv_sram_icb_ctrl.v │ ├── mems │ ├── sirv_mrom.v │ └── sirv_mrom_top.v │ ├── perips │ ├── i2c_master_bit_ctrl.v │ ├── i2c_master_byte_ctrl.v │ ├── i2c_master_defines.v │ ├── i2c_master_top.v │ ├── sirv_AsyncResetReg.v │ ├── sirv_AsyncResetRegVec.v │ ├── sirv_AsyncResetRegVec_1.v │ ├── sirv_AsyncResetRegVec_129.v │ ├── sirv_AsyncResetRegVec_36.v │ ├── sirv_AsyncResetRegVec_67.v │ ├── sirv_DeglitchShiftRegister.v │ ├── sirv_LevelGateway.v │ ├── sirv_ResetCatchAndSync.v │ ├── sirv_ResetCatchAndSync_2.v │ ├── sirv_aon.v │ ├── sirv_aon_lclkgen_regs.v │ ├── sirv_aon_porrst.v │ ├── sirv_aon_top.v │ ├── sirv_aon_wrapper.v │ ├── sirv_clint.v │ ├── sirv_clint_top.v │ ├── sirv_expl_apb_slv.v │ ├── sirv_expl_axi_slv.v │ ├── sirv_flash_qspi.v │ ├── sirv_flash_qspi_top.v │ ├── sirv_gpio.v │ ├── sirv_gpio_top.v │ ├── sirv_hclkgen_regs.v │ ├── sirv_jtaggpioport.v │ ├── sirv_otp_top.v │ ├── sirv_plic_man.v │ ├── sirv_plic_top.v │ ├── sirv_pmu.v │ ├── sirv_pmu_core.v │ ├── sirv_pwm16.v │ ├── sirv_pwm16_core.v │ ├── sirv_pwm16_top.v │ ├── sirv_pwm8.v │ ├── sirv_pwm8_core.v │ ├── sirv_pwm8_top.v │ ├── sirv_pwmgpioport.v │ ├── sirv_qspi_1cs.v │ ├── sirv_qspi_1cs_top.v │ ├── sirv_qspi_4cs.v │ ├── sirv_qspi_4cs_top.v │ ├── sirv_qspi_arbiter.v │ ├── sirv_qspi_fifo.v │ ├── sirv_qspi_media.v │ ├── sirv_qspi_media_1.v │ ├── sirv_qspi_media_2.v │ ├── sirv_qspi_physical.v │ ├── sirv_qspi_physical_1.v │ ├── sirv_qspi_physical_2.v │ ├── sirv_queue.v │ ├── sirv_queue_1.v │ ├── sirv_repeater_6.v │ ├── sirv_rtc.v │ ├── sirv_spi_flashmap.v │ ├── sirv_spigpioport.v │ ├── sirv_spigpioport_1.v │ ├── sirv_spigpioport_2.v │ ├── sirv_tl_repeater_5.v │ ├── sirv_tlfragmenter_qspi_1.v │ ├── sirv_tlwidthwidget_qspi.v │ ├── sirv_uart.v │ ├── sirv_uart_top.v │ ├── sirv_uartgpioport.v │ ├── sirv_uartrx.v │ ├── sirv_uarttx.v │ └── sirv_wdog.v │ ├── soc │ └── e203_soc_top.v │ └── subsys │ ├── e203_subsys_clint.v │ ├── e203_subsys_gfcm.v │ ├── e203_subsys_hclkgen.v │ ├── e203_subsys_hclkgen_rstsync.v │ ├── e203_subsys_main.v │ ├── e203_subsys_mems.v │ ├── e203_subsys_perips.v │ ├── e203_subsys_plic.v │ ├── e203_subsys_pll.v │ ├── e203_subsys_pllclkdiv.v │ └── e203_subsys_top.v ├── sirv-e-sdk ├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── bsp │ ├── drivers │ │ ├── fe300prci │ │ │ ├── fe300prci_driver.c │ │ │ └── fe300prci_driver.h │ │ └── plic │ │ │ ├── plic_driver.c │ │ │ └── plic_driver.h │ ├── env │ │ ├── common.mk │ │ ├── coreplexip-arty.h │ │ ├── encoding.h │ │ ├── entry.S │ │ ├── hifive1.h │ │ ├── sirv-e201-arty │ │ │ ├── init.c │ │ │ ├── link.lds │ │ │ ├── openocd.cfg │ │ │ ├── platform.h │ │ │ └── settings.mk │ │ ├── sirv-e203-arty │ │ │ ├── init.c │ │ │ ├── link.lds │ │ │ ├── openocd.cfg │ │ │ ├── platform.h │ │ │ └── settings.mk │ │ ├── sirv-e205-arty │ │ │ ├── init.c │ │ │ ├── link.lds │ │ │ ├── openocd.cfg │ │ │ ├── platform.h │ │ │ └── settings.mk │ │ ├── sirv-e205f-arty │ │ │ ├── init.c │ │ │ ├── link.lds │ │ │ ├── openocd.cfg │ │ │ ├── platform.h │ │ │ └── settings.mk │ │ ├── sirv-e205fd-arty │ │ │ ├── init.c │ │ │ ├── link.lds │ │ │ ├── openocd.cfg │ │ │ ├── platform.h │ │ │ └── settings.mk │ │ ├── sirv-e225fd-arty │ │ │ ├── init.c │ │ │ ├── link.lds │ │ │ ├── openocd.cfg │ │ │ ├── platform.h │ │ │ └── settings.mk │ │ ├── sirv_printf.c │ │ └── start.S │ ├── include │ │ └── sifive │ │ │ ├── bits.h │ │ │ ├── const.h │ │ │ ├── devices │ │ │ ├── aon.h │ │ │ ├── clint.h │ │ │ ├── gpio.h │ │ │ ├── i2c.h │ │ │ ├── otp.h │ │ │ ├── plic.h │ │ │ ├── prci.h │ │ │ ├── pwm.h │ │ │ ├── spi.h │ │ │ └── uart.h │ │ │ ├── sections.h │ │ │ └── smp.h │ ├── libwrap │ │ ├── libwrap.mk │ │ ├── misc │ │ │ └── write_hex.c │ │ ├── stdlib │ │ │ └── malloc.c │ │ └── sys │ │ │ ├── _exit.c │ │ │ ├── close.c │ │ │ ├── execve.c │ │ │ ├── fork.c │ │ │ ├── fstat.c │ │ │ ├── getpid.c │ │ │ ├── isatty.c │ │ │ ├── kill.c │ │ │ ├── link.c │ │ │ ├── lseek.c │ │ │ ├── open.c │ │ │ ├── openat.c │ │ │ ├── read.c │ │ │ ├── sbrk.c │ │ │ ├── stat.c │ │ │ ├── stub.h │ │ │ ├── times.c │ │ │ ├── unlink.c │ │ │ ├── wait.c │ │ │ └── write.c │ └── tools │ │ └── openocd_upload.sh └── software │ ├── coremark │ ├── .gitignore │ ├── Makefile │ ├── core_list_join.c │ ├── core_main.c │ ├── core_matrix.c │ ├── core_portme.c │ ├── core_portme.h │ ├── core_state.c │ ├── core_util.c │ └── coremark.h │ ├── demo_gpio │ ├── .gitignore │ ├── Makefile │ └── demo_gpio.c │ └── dhrystone │ ├── .gitignore │ ├── Makefile │ ├── dhry.h │ ├── dhry_1.c │ ├── dhry_2.c │ └── dhry_stubs.c ├── tb ├── .gitignore └── tb_top.v ├── verilator ├── README.md ├── build │ ├── e203_soc_top_jtagdpi │ │ └── e203_soc_top_jtagdpi.vc │ └── e203_soc_top_verilator │ │ └── e203_soc_top_verilator.vc ├── dpi │ ├── common │ │ └── tcp_server │ │ │ ├── tcp_server.c │ │ │ └── tcp_server.h │ └── jtagdpi │ │ ├── jtagdpi.c │ │ ├── jtagdpi.h │ │ └── jtagdpi.sv ├── top │ ├── e203_soc_top_verilator.cc │ └── e203_soc_top_verilator.v └── util │ └── openocd │ └── hbird-e203.cfg └── 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-------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(insn.i_imm() + RS1)); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/addw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 + RS2)); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/and.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 & RS2); 2 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/andi.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.i_imm() & RS1); 2 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/auipc.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(insn.u_imm() + pc)); 2 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/beq.h: -------------------------------------------------------------------------------- 1 | if(RS1 == RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/bge.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yaozhaosh/e200_opensource/HEAD/riscv-tools/riscv-isa-sim/riscv/insns/bge.h -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/bgeu.h: -------------------------------------------------------------------------------- 1 | if(RS1 >= RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/blt.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yaozhaosh/e200_opensource/HEAD/riscv-tools/riscv-isa-sim/riscv/insns/blt.h -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/bltu.h: -------------------------------------------------------------------------------- 1 | if(RS1 < RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/bne.h: -------------------------------------------------------------------------------- 1 | if(RS1 != RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/c_add.h: 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set_pc(pc + insn.rvc_j_imm()); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/c_jal.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yaozhaosh/e200_opensource/HEAD/riscv-tools/riscv-isa-sim/riscv/insns/c_jal.h -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/c_jalr.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yaozhaosh/e200_opensource/HEAD/riscv-tools/riscv-isa-sim/riscv/insns/c_jalr.h -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/c_jr.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yaozhaosh/e200_opensource/HEAD/riscv-tools/riscv-isa-sim/riscv/insns/c_jr.h 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-------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(MMU.load_int64(RS1 + insn.i_imm())); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/lh.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load_int16(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/lhu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/lui.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.u_imm()); 2 | -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | require_rv64; 2 | MMU.store_uint64(RS1 + insn.s_imm(), RS2); 3 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/sh.h: -------------------------------------------------------------------------------- 1 | MMU.store_uint16(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/sll.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yaozhaosh/e200_opensource/HEAD/riscv-tools/riscv-isa-sim/riscv/insns/sll.h -------------------------------------------------------------------------------- /riscv-tools/riscv-isa-sim/riscv/insns/slliw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 << SHAMT)); 3 | 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